From 03f4d40e30f3c94e1db0b3a65b3610dee695694a Mon Sep 17 00:00:00 2001 From: Meco Man <920369182@qq.com> Date: Thu, 27 May 2021 17:33:03 +0800 Subject: [lts 3,1,x] format codes --- bsp/CME_M7/applications/application.c | 6 +- bsp/CME_M7/applications/startup.c | 2 +- bsp/CME_M7/drivers/board.h | 2 +- bsp/CME_M7/drivers/emac.c | 8 +- bsp/CME_M7/rtconfig.h | 36 +- bsp/allwinner_tina/drivers/drv_clock.c | 4 +- bsp/allwinner_tina/drivers/drv_clock.h | 2 +- bsp/allwinner_tina/drivers/drv_gpio.h | 2 +- bsp/allwinner_tina/drivers/drv_sdio.c | 42 +- bsp/allwinner_tina/drivers/drv_sdio.h | 6 +- bsp/allwinner_tina/drivers/drv_uart.c | 2 +- bsp/allwinner_tina/drivers/spi/drv_spi_flash.c | 2 +- bsp/amebaz/drivers/board.c | 6 +- bsp/amebaz/drivers/drv_uart.c | 26 +- bsp/amebaz/drivers/wlan/drv_wifi.c | 10 +- bsp/amebaz/drivers/wlan/drv_wifi.h | 2 +- bsp/amebaz/drivers/wlan/drv_wlan.c | 14 +- bsp/amebaz/drivers/wlan/drv_wlan.h | 16 +- bsp/apollo2/board/adc.c | 4 +- bsp/apollo2/board/gpio.c | 2 +- bsp/apollo2/board/gpio.h | 2 +- bsp/apollo2/board/i2c.c | 10 +- bsp/apollo2/board/pdm.c | 2 +- bsp/apollo2/board/rtc.c | 14 +- bsp/apollo2/board/rtc.h | 2 +- bsp/apollo2/board/smbus.c | 10 +- bsp/apollo2/board/spi.c | 4 +- bsp/apollo2/board/uart.c | 6 +- bsp/asm9260t/applications/application.c | 4 +- bsp/asm9260t/drivers/usart.c | 6 +- bsp/asm9260t/platform/gpio.c | 2 +- bsp/asm9260t/platform/interrupt.h | 126 +- bsp/asm9260t/platform/rt_low_level_init.h | 2 +- bsp/asm9260t/platform/system_clock.c | 398 ++-- bsp/asm9260t/platform/uart.c | 2 +- bsp/asm9260t/platform/uart.h | 22 +- bsp/at91sam9260/applications/application.c | 156 +- bsp/at91sam9260/drivers/at91_i2c_gpio.c | 130 +- bsp/at91sam9260/drivers/at91_mci.c | 1424 +++++------ bsp/at91sam9260/drivers/at91_mci.h | 168 +- bsp/at91sam9260/drivers/board.c | 254 +- bsp/at91sam9260/drivers/led.c | 84 +- bsp/at91sam9260/drivers/macb.c | 1384 +++++------ bsp/at91sam9260/drivers/macb.h | 554 ++--- bsp/at91sam9260/drivers/mii.h | 20 +- bsp/at91sam9260/drivers/usart.c | 380 +-- bsp/at91sam9260/platform/at91_aic.h | 70 +- bsp/at91sam9260/platform/at91_pdc.h | 28 +- bsp/at91sam9260/platform/at91_pio.h | 58 +- bsp/at91sam9260/platform/at91_pit.h | 24 +- bsp/at91sam9260/platform/at91_pmc.h | 226 +- bsp/at91sam9260/platform/at91_rstc.h | 42 +- bsp/at91sam9260/platform/at91_serial.h | 200 +- bsp/at91sam9260/platform/at91_shdwc.h | 36 +- bsp/at91sam9260/platform/at91_tc.h | 238 +- bsp/at91sam9260/platform/at91sam9260_matrix.h | 114 +- bsp/at91sam9260/platform/at91sam926x.h | 250 +- bsp/at91sam9260/platform/gpio.h | 200 +- bsp/at91sam9260/platform/interrupt.c | 26 +- bsp/at91sam9260/platform/io.h | 24 +- bsp/at91sam9260/platform/irq.h | 18 +- bsp/at91sam9260/platform/reset.c | 12 +- bsp/at91sam9260/platform/rt_low_level_init.c | 4 +- bsp/at91sam9260/platform/rt_low_level_init.h | 2 +- bsp/at91sam9260/platform/system_clock.c | 400 ++-- bsp/avr32uc3b0/application.c | 2 +- bsp/avr32uc3b0/board.c | 90 +- bsp/avr32uc3b0/rtconfig.h | 26 +- bsp/avr32uc3b0/startup.c | 22 +- bsp/beaglebone/applications/board.c | 84 +- bsp/bf533/rtconfig.h | 84 +- bsp/dm365/applications/application.c | 94 +- bsp/dm365/applications/board.c | 200 +- bsp/dm365/applications/board.h | 4 +- bsp/dm365/drivers/davinci_emac.c | 2354 +++++++++--------- bsp/dm365/drivers/davinci_emac.h | 670 +++--- bsp/dm365/drivers/davinci_serial.c | 232 +- bsp/dm365/drivers/gpio.c | 198 +- bsp/dm365/drivers/gpio.h | 40 +- bsp/dm365/drivers/i2c-davinci.c | 974 ++++---- bsp/dm365/drivers/mii.h | 34 +- bsp/dm365/drivers/mmcsd.c | 2148 ++++++++--------- bsp/dm365/drivers/mmcsd.h | 94 +- bsp/dm365/drivers/spi-davinci.c | 1280 +++++----- bsp/dm365/drivers/spi-davinci.h | 60 +- bsp/dm365/platform/dm365.c | 542 ++--- bsp/dm365/platform/dm365_timer.h | 82 +- bsp/dm365/platform/dm36x.h | 270 +-- bsp/dm365/platform/dma.c | 1786 +++++++------- bsp/dm365/platform/edma.h | 312 +-- bsp/dm365/platform/interrupt.c | 382 +-- bsp/dm365/platform/irqs.h | 188 +- bsp/dm365/platform/psc.c | 14 +- bsp/dm365/platform/psc.h | 120 +- bsp/dm365/platform/reset.c | 14 +- bsp/dm365/platform/system_clock.c | 6 +- bsp/dm365/platform/trap.c | 136 +- bsp/efm32/application.c | 218 +- bsp/efm32/board.c | 146 +- bsp/efm32/board.h | 126 +- bsp/efm32/copy_this_file_dfs_elm.c | 1262 +++++----- bsp/efm32/copy_this_file_shell.c | 630 ++--- bsp/efm32/dev_accel.c | 1346 +++++------ bsp/efm32/dev_accel.h | 146 +- bsp/efm32/dev_keys.c | 40 +- bsp/efm32/dev_keys.h | 8 +- bsp/efm32/dev_lcd.c | 80 +- bsp/efm32/dev_lcd.h | 8 +- bsp/efm32/dev_sflash.h | 138 +- bsp/efm32/drv_acmp.c | 482 ++-- bsp/efm32/drv_acmp.h | 20 +- bsp/efm32/drv_adc.c | 1234 +++++----- bsp/efm32/drv_adc.h | 60 +- bsp/efm32/drv_emu.c | 28 +- bsp/efm32/drv_emu.h | 12 +- bsp/efm32/drv_ethernet.c | 1644 ++++++------- bsp/efm32/drv_ethernet.h | 30 +- bsp/efm32/drv_leuart.c | 1364 +++++------ bsp/efm32/drv_leuart.h | 54 +- bsp/efm32/drv_rtc.c | 118 +- bsp/efm32/drv_rtc.h | 2 +- bsp/efm32/drv_sdcard.h | 76 +- bsp/efm32/drv_timer.c | 2 +- bsp/efm32/drv_usart.c | 4 +- bsp/efm32/enc28j60.h | 42 +- bsp/efm32/graphics/tftspi.h | 8 +- bsp/efm32/hdl_interrupt.c | 696 +++--- bsp/efm32/hdl_interrupt.h | 28 +- bsp/efm32/httpd.c | 56 +- bsp/efm32/mma7455l.h | 170 +- bsp/efm32/rtconfig.h | 128 +- bsp/efm32/startup.c | 4 +- bsp/frdm-k64f/applications/application.c | 2 +- bsp/frdm-k64f/applications/startup.c | 4 +- bsp/frdm-k64f/board/board.c | 6 +- bsp/frdm-k64f/board/board.h | 2 +- bsp/frdm-k64f/board/drv_emac.c | 110 +- bsp/frdm-k64f/board/drv_emac.h | 2 +- bsp/frdm-k64f/board/drv_uart.c | 4 +- bsp/frdm-k64f/board/drv_uart.h | 4 +- bsp/frdm-k64f/board/led.c | 2 +- bsp/frdm-k64f/board/led.h | 2 +- bsp/frdm-k64f/rtconfig.h | 46 +- bsp/gd32303e-eval/drivers/board.c | 2 +- bsp/gd32303e-eval/drivers/board.h | 2 +- bsp/gd32303e-eval/drivers/drv_gpio.c | 12 +- bsp/gd32303e-eval/drivers/drv_i2c.c | 8 +- bsp/gd32303e-eval/drivers/drv_spi.c | 16 +- bsp/gd32303e-eval/drivers/drv_spi_flash.c | 2 +- bsp/gd32303e-eval/drivers/drv_usart.c | 16 +- bsp/gd32450z-eval/drivers/board.h | 2 +- bsp/gd32450z-eval/drivers/drv_enet.c | 72 +- bsp/gd32450z-eval/drivers/drv_lcd.c | 108 +- bsp/gd32450z-eval/drivers/drv_spi.c | 56 +- bsp/gd32450z-eval/drivers/drv_spi.h | 4 +- bsp/gd32450z-eval/drivers/drv_spi_flash.c | 32 +- bsp/gd32450z-eval/drivers/drv_usart.c | 24 +- bsp/gd32450z-eval/drivers/synopsys_emac.h | 290 +-- bsp/hifive1/applications/main.c | 2 +- bsp/hifive1/drivers/drv_usart.c | 2 +- bsp/hifive1/drivers/interrupt.c | 10 +- bsp/hifive1/drivers/interrupt.h | 2 +- bsp/imx6sx/cortex-a9/applications/main.c | 2 +- bsp/imx6sx/cortex-a9/cpu/cpu.c | 16 +- bsp/imx6sx/cortex-a9/cpu/interrupt.c | 2 +- bsp/imx6sx/cortex-a9/cpu/mmu.c | 2 +- bsp/imx6sx/cortex-a9/cpu/pmu.c | 2 +- bsp/imx6sx/cortex-a9/cpu/stack.c | 52 +- bsp/imx6sx/cortex-a9/cpu/trap.c | 2 +- bsp/imx6sx/cortex-a9/drivers/board.c | 2 +- bsp/imx6sx/cortex-a9/drivers/board.h | 2 +- bsp/imx6sx/cortex-a9/drivers/emac_drv.c | 146 +- bsp/imx6sx/cortex-a9/drivers/emac_drv.h | 2 +- bsp/imx6sx/cortex-a9/drivers/serial.c | 2 +- bsp/imx6sx/cortex-a9/drivers/serial.h | 2 +- bsp/imx6ul/applications/application.c | 2 +- bsp/imx6ul/applications/startup.c | 2 +- bsp/imx6ul/drivers/board.c | 2 +- bsp/imx6ul/drivers/board.h | 2 +- bsp/imx6ul/drivers/imx6ul.h | 2 +- .../imxrt1052-atk-commander/applications/main.c | 2 +- bsp/imxrt/imxrt1052-atk-commander/board/board.c | 2 +- bsp/imxrt/imxrt1052-atk-commander/board/board.h | 2 +- .../board/ports/sdram_port.h | 2 +- .../board/ports/spi_flash_init.c | 2 +- bsp/imxrt/imxrt1052-fire-pro/applications/main.c | 2 +- bsp/imxrt/imxrt1052-fire-pro/board/board.c | 2 +- bsp/imxrt/imxrt1052-fire-pro/board/board.h | 2 +- bsp/imxrt/imxrt1052-nxp-evk/applications/main.c | 2 +- bsp/imxrt/imxrt1052-nxp-evk/applications/mnt.c | 20 +- bsp/imxrt/imxrt1052-nxp-evk/board/board.c | 6 +- bsp/imxrt/imxrt1052-nxp-evk/board/board.h | 2 +- .../imxrt1052-nxp-evk/board/ports/sdram_port.h | 2 +- bsp/imxrt/imxrt1064-nxp-evk/applications/main.c | 2 +- bsp/imxrt/imxrt1064-nxp-evk/board/board.c | 2 +- bsp/imxrt/imxrt1064-nxp-evk/board/board.h | 2 +- bsp/imxrt/libraries/drivers/drv_adc.c | 2 +- bsp/imxrt/libraries/drivers/drv_adc.h | 2 +- bsp/imxrt/libraries/drivers/drv_can.c | 4 +- bsp/imxrt/libraries/drivers/drv_can.h | 4 +- bsp/imxrt/libraries/drivers/drv_eth.c | 10 +- bsp/imxrt/libraries/drivers/drv_gpio.c | 4 +- bsp/imxrt/libraries/drivers/drv_gpio.h | 8 +- bsp/imxrt/libraries/drivers/drv_hwtimer.c | 2 +- bsp/imxrt/libraries/drivers/drv_hwtimer.h | 2 +- bsp/imxrt/libraries/drivers/drv_i2c.c | 2 +- bsp/imxrt/libraries/drivers/drv_i2c.h | 2 +- bsp/imxrt/libraries/drivers/drv_lcd.c | 2 +- bsp/imxrt/libraries/drivers/drv_log.h | 2 +- bsp/imxrt/libraries/drivers/drv_pwm.c | 2 +- bsp/imxrt/libraries/drivers/drv_pwm.h | 2 +- bsp/imxrt/libraries/drivers/drv_rtc.c | 2 +- bsp/imxrt/libraries/drivers/drv_rtc.h | 2 +- bsp/imxrt/libraries/drivers/drv_sdram.h | 4 +- bsp/imxrt/libraries/drivers/drv_spi.c | 136 +- bsp/imxrt/libraries/drivers/drv_spi.h | 4 +- bsp/imxrt/libraries/drivers/drv_uart.c | 4 +- bsp/imxrt/libraries/drivers/drv_uart.h | 2 +- bsp/imxrt/libraries/drivers/drv_wdt.c | 2 +- bsp/imxrt/libraries/drivers/drv_wdt.h | 2 +- .../templates/imxrt1050xxx/applications/main.c | 2 +- .../libraries/templates/imxrt1050xxx/board/board.c | 2 +- .../libraries/templates/imxrt1050xxx/board/board.h | 2 +- .../templates/imxrt1064xxx/applications/main.c | 2 +- .../libraries/templates/imxrt1064xxx/board/board.c | 2 +- .../libraries/templates/imxrt1064xxx/board/board.h | 2 +- bsp/lm3s8962/applications/application.c | 52 +- bsp/lm3s8962/applications/startup.c | 92 +- bsp/lm3s8962/drivers/board.c | 84 +- bsp/lm3s8962/drivers/board.h | 4 +- bsp/lm3s8962/drivers/serial.c | 394 +-- bsp/lm3s8962/rtconfig.h | 38 +- bsp/lm3s9b9x/applications/application.c | 52 +- bsp/lm3s9b9x/applications/startup.c | 86 +- bsp/lm3s9b9x/drivers/board.c | 72 +- bsp/lm3s9b9x/drivers/board.h | 14 +- bsp/lm3s9b9x/drivers/serial.c | 394 +-- bsp/lm3s9b9x/rtconfig.h | 40 +- bsp/lm4f232/applications/application.c | 52 +- bsp/lm4f232/applications/startup.c | 86 +- bsp/lm4f232/drivers/board.c | 76 +- bsp/lm4f232/drivers/board.h | 16 +- bsp/lm4f232/drivers/serial.c | 394 +-- bsp/lm4f232/rtconfig.h | 70 +- bsp/lpc176x/applications/application.c | 36 +- bsp/lpc176x/applications/platform.c | 8 +- bsp/lpc176x/applications/platform.h | 2 +- bsp/lpc176x/applications/startup.c | 56 +- bsp/lpc176x/drivers/board.c | 34 +- bsp/lpc176x/drivers/board.h | 2 +- bsp/lpc176x/drivers/emac.c | 840 +++---- bsp/lpc176x/drivers/led.h | 2 +- bsp/lpc176x/drivers/sd.c | 8 +- bsp/lpc176x/drivers/uart.c | 10 +- bsp/lpc178x/applications/application.c | 90 +- bsp/lpc178x/applications/startup.c | 64 +- bsp/lpc178x/drivers/board.c | 2 +- bsp/lpc178x/drivers/board.h | 4 +- bsp/lpc178x/drivers/emac.c | 836 +++---- bsp/lpc178x/drivers/lpc17xx_lcd.c | 96 +- bsp/lpc178x/drivers/uart.c | 342 +-- bsp/lpc178x/rtconfig.h | 56 +- bsp/lpc2148/applications/application.c | 2 +- bsp/lpc2148/applications/startup.c | 2 +- bsp/lpc2148/drivers/board.c | 86 +- bsp/lpc2148/drivers/board.h | 8 +- bsp/lpc2148/drivers/dm9000.c | 96 +- bsp/lpc2148/drivers/sd.c | 90 +- bsp/lpc2148/drivers/serial.c | 506 ++-- bsp/lpc2148/rtconfig.h | 46 +- bsp/lpc2478/applications/application.c | 2 +- bsp/lpc2478/applications/startup.c | 2 +- bsp/lpc2478/drivers/board.c | 28 +- bsp/lpc2478/drivers/board.h | 140 +- bsp/lpc2478/drivers/serial.c | 528 ++--- bsp/lpc2478/rtconfig.h | 38 +- bsp/lpc408x/drivers/board.c | 2 +- bsp/lpc408x/drivers/board.h | 2 +- bsp/lpc408x/drivers/drv_emac.c | 2 +- bsp/lpc408x/drivers/drv_emac.h | 2 +- bsp/lpc408x/drivers/drv_hwtimer.c | 2 +- bsp/lpc408x/drivers/drv_hwtimer.h | 2 +- bsp/lpc408x/drivers/drv_led.c | 2 +- bsp/lpc408x/drivers/drv_led.h | 2 +- bsp/lpc408x/drivers/drv_sdram.c | 2 +- bsp/lpc408x/drivers/drv_sdram.h | 2 +- bsp/lpc408x/drivers/drv_uart.c | 2 +- bsp/lpc408x/drivers/drv_uart.h | 2 +- bsp/lpc43xx/M0/applications/application.c | 2 +- bsp/lpc43xx/M0/applications/board.c | 2 +- bsp/lpc43xx/M0/applications/board.h | 2 +- bsp/lpc43xx/M0/applications/startup.c | 2 +- bsp/lpc43xx/M0/applications/vbus_drv.c | 2 +- bsp/lpc43xx/M0/applications/vbus_hw.h | 2 +- bsp/lpc43xx/M4/applications/application.c | 6 +- bsp/lpc43xx/M4/applications/board.c | 2 +- bsp/lpc43xx/M4/applications/board.h | 2 +- bsp/lpc43xx/M4/applications/startup.c | 2 +- bsp/lpc43xx/M4/applications/vbus_drv.c | 2 +- bsp/lpc43xx/M4/applications/vbus_hw.h | 2 +- bsp/lpc43xx/drivers/drv_emac.c | 2 +- bsp/lpc43xx/drivers/drv_emac.h | 2 +- bsp/lpc43xx/drivers/drv_led.c | 2 +- bsp/lpc43xx/drivers/drv_uart.c | 8 +- bsp/lpc5410x/applications/application.c | 2 +- bsp/lpc5410x/applications/board.h | 2 +- bsp/lpc5410x/applications/demo_thread.c | 60 +- bsp/lpc5410x/applications/startup.c | 2 +- bsp/lpc5410x/drivers/drv_led.c | 2 +- bsp/lpc5410x/drivers/drv_uart.c | 2 +- bsp/lpc5410x/rtconfig.h | 52 +- bsp/lpc54114-lite/applications/main.c | 6 +- bsp/lpc54114-lite/applications/mnt.c | 10 +- bsp/lpc54114-lite/drivers/audio/drv_mic.c | 4 +- bsp/lpc54114-lite/drivers/audio/drv_mic.h | 2 +- bsp/lpc54114-lite/drivers/audio/drv_sound.c | 4 +- bsp/lpc54114-lite/drivers/audio/drv_sound.h | 2 +- bsp/lpc54114-lite/drivers/board.c | 8 +- bsp/lpc54114-lite/drivers/board.h | 2 +- bsp/lpc54114-lite/drivers/drv_gpio.c | 132 +- bsp/lpc54114-lite/drivers/drv_gpio.h | 4 +- bsp/lpc54114-lite/drivers/drv_i2c.c | 40 +- bsp/lpc54114-lite/drivers/drv_i2c.h | 12 +- bsp/lpc54114-lite/drivers/drv_sdcard.c | 22 +- bsp/lpc54114-lite/drivers/drv_sdcard.h | 12 +- bsp/lpc54114-lite/drivers/drv_spi.c | 138 +- bsp/lpc54114-lite/drivers/drv_spi.h | 16 +- bsp/lpc54114-lite/drivers/drv_spi_flash.c | 28 +- bsp/lpc54114-lite/drivers/drv_spi_flash.h | 4 +- bsp/lpc54114-lite/drivers/drv_uart.c | 46 +- bsp/lpc54114-lite/drivers/drv_uart.h | 4 +- bsp/lpc54608-LPCXpresso/applications/application.c | 10 +- bsp/lpc54608-LPCXpresso/applications/mnt.c | 8 +- bsp/lpc54608-LPCXpresso/applications/startup.c | 6 +- bsp/lpc54608-LPCXpresso/drivers/board.h | 2 +- bsp/lpc54608-LPCXpresso/drivers/drt_mpu.c | 6 +- bsp/lpc54608-LPCXpresso/drivers/drt_mpu.h | 2 +- bsp/lpc54608-LPCXpresso/drivers/drv_emac.c | 126 +- bsp/lpc54608-LPCXpresso/drivers/drv_emac.h | 2 +- bsp/lpc54608-LPCXpresso/drivers/drv_ft5406.c | 4 +- bsp/lpc54608-LPCXpresso/drivers/drv_i2c.c | 4 +- bsp/lpc54608-LPCXpresso/drivers/drv_lcd.c | 6 +- bsp/lpc54608-LPCXpresso/drivers/drv_sd.c | 28 +- bsp/lpc54608-LPCXpresso/drivers/drv_sd.h | 4 +- bsp/lpc54608-LPCXpresso/drivers/drv_sdram.h | 2 +- bsp/lpc54608-LPCXpresso/drivers/drv_sram.c | 2 +- bsp/lpc54608-LPCXpresso/drivers/drv_sram.h | 2 +- bsp/lpc54608-LPCXpresso/drivers/drv_uart.c | 6 +- bsp/lpc824/applications/application.c | 20 +- bsp/lpc824/applications/startup.c | 4 +- bsp/lpc824/drivers/board.c | 4 +- bsp/lpc824/drivers/board.h | 2 +- bsp/lpc824/drivers/usart.c | 86 +- bsp/lpc824/drivers/usart.h | 2 +- bsp/lpc824/rtconfig.h | 20 +- bsp/ls1bdev/applications/application.c | 38 +- bsp/ls1bdev/applications/startup.c | 2 +- bsp/ls1bdev/drivers/board.c | 78 +- bsp/ls1bdev/drivers/board.h | 4 +- bsp/ls1bdev/drivers/display_controller.c | 354 +-- bsp/ls1bdev/drivers/display_controller.h | 50 +- bsp/ls1bdev/drivers/uart.c | 394 +-- bsp/ls1bdev/drivers/uart.h | 120 +- bsp/ls1cdev/applications/main.c | 4 +- bsp/ls1cdev/drivers/board.c | 64 +- bsp/ls1cdev/drivers/board.h | 2 +- bsp/ls1cdev/drivers/display_controller.c | 34 +- bsp/ls1cdev/drivers/display_controller.h | 46 +- bsp/ls1cdev/drivers/drv_can.c | 88 +- bsp/ls1cdev/drivers/drv_can.h | 2 +- bsp/ls1cdev/drivers/drv_gpio.c | 4 +- bsp/ls1cdev/drivers/drv_gpio.h | 2 +- bsp/ls1cdev/drivers/drv_i2c.c | 2 +- bsp/ls1cdev/drivers/drv_i2c.h | 2 +- bsp/ls1cdev/drivers/drv_pwm.c | 22 +- bsp/ls1cdev/drivers/drv_pwm.h | 2 +- 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| 2 +- .../libraries/HAL_Drivers/config/f1/spi_config.h | 8 +- .../libraries/HAL_Drivers/config/f1/tim_config.h | 2 +- .../libraries/HAL_Drivers/config/f1/uart_config.h | 2 +- .../libraries/HAL_Drivers/config/f1/usbd_config.h | 2 +- .../libraries/HAL_Drivers/config/f2/adc_config.h | 2 +- .../libraries/HAL_Drivers/config/f2/dma_config.h | 4 +- .../libraries/HAL_Drivers/config/f2/pwm_config.h | 2 +- .../libraries/HAL_Drivers/config/f2/sdio_config.h | 2 +- .../libraries/HAL_Drivers/config/f2/spi_config.h | 8 +- .../libraries/HAL_Drivers/config/f2/tim_config.h | 2 +- .../libraries/HAL_Drivers/config/f2/uart_config.h | 14 +- .../libraries/HAL_Drivers/config/f4/adc_config.h | 2 +- .../libraries/HAL_Drivers/config/f4/dma_config.h | 2 +- .../HAL_Drivers/config/f4/pulse_encoder_config.h | 2 +- .../libraries/HAL_Drivers/config/f4/pwm_config.h | 2 +- .../libraries/HAL_Drivers/config/f4/qspi_config.h | 4 +- .../libraries/HAL_Drivers/config/f4/sdio_config.h | 2 +- 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components/cplusplus/Mail.h | 2 +- components/cplusplus/Mutex.h | 2 +- components/cplusplus/Queue.h | 2 +- components/cplusplus/Semaphore.h | 2 +- components/cplusplus/Thread.h | 2 +- components/cplusplus/crt.h | 2 +- components/cplusplus/crt_init.c | 2 +- components/cplusplus/cxx_Mutex.cpp | 2 +- components/cplusplus/cxx_Semaphore.cpp | 2 +- components/cplusplus/cxx_Thread.cpp | 2 +- components/cplusplus/cxx_crt.cpp | 2 +- components/dfs/filesystems/devfs/devfs.c | 4 +- components/dfs/filesystems/devfs/devfs.h | 2 +- components/dfs/filesystems/elmfat/dfs_elm.c | 2 +- components/dfs/filesystems/elmfat/dfs_elm.h | 2 +- components/dfs/filesystems/nfs/dfs_nfs.c | 2 +- components/dfs/filesystems/nfs/dfs_nfs.h | 2 +- components/dfs/filesystems/nfs/mount.h | 84 +- components/dfs/filesystems/nfs/mount_clnt.c | 62 +- components/dfs/filesystems/nfs/mount_xdr.c | 126 +- components/dfs/filesystems/nfs/nfs.h | 866 +++---- components/dfs/filesystems/nfs/nfs_auth.c | 2 +- components/dfs/filesystems/nfs/nfs_clnt.c | 222 +- components/dfs/filesystems/nfs/nfs_xdr.c | 1900 +++++++-------- components/dfs/filesystems/nfs/rpc/auth.h | 102 +- components/dfs/filesystems/nfs/rpc/auth_none.c | 98 +- components/dfs/filesystems/nfs/rpc/clnt.h | 240 +- components/dfs/filesystems/nfs/rpc/clnt_generic.c | 2 +- components/dfs/filesystems/nfs/rpc/clnt_udp.c | 544 ++--- components/dfs/filesystems/nfs/rpc/pmap.c | 70 +- components/dfs/filesystems/nfs/rpc/pmap.h | 58 +- components/dfs/filesystems/nfs/rpc/rpc.h | 12 +- components/dfs/filesystems/nfs/rpc/rpc_msg.h | 152 +- components/dfs/filesystems/nfs/rpc/rpc_prot.c | 264 +-- components/dfs/filesystems/nfs/rpc/types.h | 2 +- components/dfs/filesystems/nfs/rpc/xdr.c | 830 +++---- components/dfs/filesystems/nfs/rpc/xdr.h | 174 +- components/dfs/filesystems/nfs/rpc/xdr_mem.c | 68 +- components/dfs/filesystems/ramfs/dfs_ramfs.c | 2 +- components/dfs/filesystems/ramfs/dfs_ramfs.h | 2 +- components/dfs/filesystems/romfs/dfs_romfs.c | 2 +- components/dfs/filesystems/romfs/dfs_romfs.h | 2 +- components/dfs/filesystems/romfs/romfs.c | 2 +- components/dfs/filesystems/skeleton/skeleton.c | 2 +- components/dfs/filesystems/skeleton/skeleton.h | 2 +- components/dfs/include/dfs.h | 2 +- components/dfs/include/dfs_file.h | 2 +- components/dfs/include/dfs_fs.h | 2 +- components/dfs/include/dfs_poll.h | 2 +- components/dfs/include/dfs_posix.h | 2 +- components/dfs/include/dfs_private.h | 2 +- components/dfs/include/dfs_select.h | 2 +- components/dfs/src/dfs.c | 2 +- components/dfs/src/dfs_file.c | 2 +- components/dfs/src/dfs_fs.c | 12 +- components/dfs/src/dfs_posix.c | 2 +- components/dfs/src/poll.c | 6 +- components/dfs/src/select.c | 4 +- components/drivers/audio/audio.c | 2 +- components/drivers/audio/audio_pipe.c | 2 +- components/drivers/audio/audio_pipe.h | 2 +- components/drivers/can/can.c | 2 +- components/drivers/cputime/cputime.c | 10 +- components/drivers/cputime/cputime_cortexm.c | 12 +- components/drivers/hwcrypto/hw_bignum.c | 36 +- components/drivers/hwcrypto/hw_bignum.h | 34 +- components/drivers/hwcrypto/hw_crc.c | 10 +- components/drivers/hwcrypto/hw_crc.h | 6 +- components/drivers/hwcrypto/hw_gcm.c | 2 +- components/drivers/hwcrypto/hw_gcm.h | 2 +- components/drivers/hwcrypto/hw_hash.c | 2 +- components/drivers/hwcrypto/hw_hash.h | 2 +- components/drivers/hwcrypto/hw_rng.c | 4 +- components/drivers/hwcrypto/hw_rng.h | 4 +- components/drivers/hwcrypto/hw_symmetric.c | 4 +- components/drivers/hwcrypto/hw_symmetric.h | 2 +- components/drivers/hwcrypto/hwcrypto.c | 2 +- components/drivers/hwcrypto/hwcrypto.h | 2 +- components/drivers/hwtimer/hwtimer.c | 4 +- components/drivers/i2c/i2c-bit-ops.c | 2 +- components/drivers/i2c/i2c_core.c | 2 +- components/drivers/i2c/i2c_dev.c | 6 +- components/drivers/include/drivers/adc.h | 2 +- components/drivers/include/drivers/alarm.h | 2 +- components/drivers/include/drivers/audio.h | 2 +- components/drivers/include/drivers/can.h | 2 +- components/drivers/include/drivers/cputime.h | 2 +- components/drivers/include/drivers/crypto.h | 2 +- components/drivers/include/drivers/hwtimer.h | 4 +- components/drivers/include/drivers/i2c-bit-ops.h | 2 +- components/drivers/include/drivers/i2c.h | 2 +- components/drivers/include/drivers/i2c_dev.h | 2 +- components/drivers/include/drivers/mmc.h | 258 +- components/drivers/include/drivers/mmcsd_card.h | 194 +- components/drivers/include/drivers/mmcsd_cmd.h | 12 +- components/drivers/include/drivers/mmcsd_core.h | 282 +-- components/drivers/include/drivers/mmcsd_host.h | 156 +- components/drivers/include/drivers/mtd_nand.h | 2 +- components/drivers/include/drivers/mtd_nor.h | 40 +- components/drivers/include/drivers/pin.h | 2 +- components/drivers/include/drivers/pm.h | 2 +- components/drivers/include/drivers/pulse_encoder.h | 2 +- components/drivers/include/drivers/rt_drv_pwm.h | 2 +- .../drivers/include/drivers/rt_inputcapture.h | 2 +- components/drivers/include/drivers/rtc.h | 2 +- components/drivers/include/drivers/sd.h | 2 +- components/drivers/include/drivers/sdio.h | 14 +- components/drivers/include/drivers/sdio_func_ids.h | 4 +- components/drivers/include/drivers/serial.h | 6 +- components/drivers/include/drivers/spi.h | 4 +- components/drivers/include/drivers/usb_common.h | 18 +- components/drivers/include/drivers/usb_device.h | 16 +- components/drivers/include/drivers/usb_host.h | 38 +- components/drivers/include/drivers/watchdog.h | 2 +- components/drivers/include/drivers/wlan.h | 2 +- components/drivers/include/ipc/completion.h | 2 +- components/drivers/include/ipc/dataqueue.h | 2 +- components/drivers/include/ipc/pipe.h | 2 +- components/drivers/include/ipc/poll.h | 2 +- components/drivers/include/ipc/ringblk_buf.h | 2 +- components/drivers/include/ipc/ringbuffer.h | 2 +- components/drivers/include/ipc/waitqueue.h | 4 +- components/drivers/include/ipc/workqueue.h | 2 +- components/drivers/include/rtdevice.h | 2 +- components/drivers/misc/adc.c | 2 +- components/drivers/misc/pin.c | 2 +- components/drivers/misc/pulse_encoder.c | 2 +- components/drivers/misc/rt_drv_pwm.c | 2 +- components/drivers/misc/rt_inputcapture.c | 2 +- components/drivers/mtd/mtd_nand.c | 2 +- components/drivers/mtd/mtd_nor.c | 4 +- components/drivers/pm/pm.c | 4 +- components/drivers/rtc/alarm.c | 2 +- components/drivers/rtc/rtc.c | 4 +- components/drivers/rtc/soft_rtc.c | 4 +- components/drivers/sdio/block_dev.c | 72 +- components/drivers/sdio/mmc.c | 134 +- components/drivers/sdio/mmcsd_core.c | 92 +- components/drivers/sdio/sd.c | 60 +- components/drivers/sdio/sdio.c | 126 +- components/drivers/sensors/sensor.c | 2 +- components/drivers/sensors/sensor.h | 4 +- components/drivers/sensors/sensor_cmd.c | 6 +- components/drivers/serial/serial.c | 20 +- components/drivers/spi/enc28j60.c | 4 +- components/drivers/spi/enc28j60.h | 2 +- components/drivers/spi/qspi_core.c | 10 +- components/drivers/spi/spi_core.c | 2 +- components/drivers/spi/spi_dev.c | 10 +- components/drivers/spi/spi_flash.h | 10 +- components/drivers/spi/spi_flash_sfud.c | 2 +- components/drivers/spi/spi_flash_sfud.h | 2 +- components/drivers/spi/spi_msd.c | 6 +- components/drivers/spi/spi_msd.h | 14 +- components/drivers/spi/spi_wifi_rw009.c | 2 +- components/drivers/spi/spi_wifi_rw009.h | 2 +- components/drivers/src/completion.c | 2 +- components/drivers/src/dataqueue.c | 28 +- components/drivers/src/pipe.c | 10 +- components/drivers/src/ringblk_buf.c | 2 +- components/drivers/src/ringbuffer.c | 12 +- components/drivers/src/waitqueue.c | 4 +- components/drivers/src/workqueue.c | 2 +- components/drivers/touch/touch.c | 2 +- components/drivers/touch/touch.h | 2 +- components/drivers/usb/usbdevice/class/audio_mic.c | 2 +- .../drivers/usb/usbdevice/class/audio_speaker.c | 2 +- components/drivers/usb/usbdevice/class/cdc.h | 16 +- components/drivers/usb/usbdevice/class/cdc_vcom.c | 74 +- components/drivers/usb/usbdevice/class/ecm.c | 26 +- components/drivers/usb/usbdevice/class/hid.c | 18 +- components/drivers/usb/usbdevice/class/hid.h | 2 +- components/drivers/usb/usbdevice/class/mstorage.c | 248 +- components/drivers/usb/usbdevice/class/mstorage.h | 6 +- components/drivers/usb/usbdevice/class/ndis.h | 88 +- components/drivers/usb/usbdevice/class/rndis.c | 20 +- components/drivers/usb/usbdevice/class/rndis.h | 196 +- components/drivers/usb/usbdevice/class/winusb.c | 16 +- components/drivers/usb/usbdevice/class/winusb.h | 2 +- components/drivers/usb/usbdevice/core/usbdevice.c | 4 +- .../drivers/usb/usbdevice/core/usbdevice_core.c | 150 +- components/drivers/usb/usbhost/class/adk.c | 2 +- components/drivers/usb/usbhost/class/adk.h | 4 +- components/drivers/usb/usbhost/class/hid.c | 136 +- components/drivers/usb/usbhost/class/hid.h | 6 +- components/drivers/usb/usbhost/class/mass.c | 178 +- components/drivers/usb/usbhost/class/mass.h | 10 +- components/drivers/usb/usbhost/class/udisk.c | 2 +- components/drivers/usb/usbhost/class/ukbd.c | 20 +- components/drivers/usb/usbhost/class/umouse.c | 2 +- components/drivers/usb/usbhost/core/driver.c | 22 +- components/drivers/usb/usbhost/core/hub.c | 186 +- components/drivers/usb/usbhost/core/usbhost.c | 6 +- components/drivers/usb/usbhost/core/usbhost_core.c | 126 +- components/drivers/watchdog/watchdog.c | 4 +- components/drivers/wlan/wlan_cfg.c | 2 +- components/drivers/wlan/wlan_cfg.h | 2 +- components/drivers/wlan/wlan_cmd.c | 2 +- components/drivers/wlan/wlan_dev.c | 2 +- components/drivers/wlan/wlan_dev.h | 4 +- components/drivers/wlan/wlan_lwip.c | 2 +- components/drivers/wlan/wlan_mgnt.c | 2 +- components/drivers/wlan/wlan_mgnt.h | 2 +- components/drivers/wlan/wlan_prot.c | 2 +- components/drivers/wlan/wlan_prot.h | 2 +- components/drivers/wlan/wlan_workqueue.c | 2 +- components/drivers/wlan/wlan_workqueue.h | 2 +- components/finsh/cmd.c | 2 +- components/finsh/finsh.h | 2 +- components/finsh/finsh_api.h | 2 +- components/finsh/finsh_compiler.c | 2 +- components/finsh/finsh_error.c | 2 +- components/finsh/finsh_error.h | 2 +- components/finsh/finsh_heap.c | 2 +- components/finsh/finsh_heap.h | 2 +- components/finsh/finsh_init.c | 2 +- components/finsh/finsh_node.c | 2 +- components/finsh/finsh_node.h | 2 +- components/finsh/finsh_ops.c | 2 +- components/finsh/finsh_ops.h | 100 +- components/finsh/finsh_parser.c | 2 +- components/finsh/finsh_parser.h | 2 +- components/finsh/finsh_token.c | 2 +- components/finsh/finsh_token.h | 2 +- components/finsh/finsh_var.c | 2 +- components/finsh/finsh_var.h | 2 +- components/finsh/finsh_vm.c | 2 +- components/finsh/finsh_vm.h | 2 +- components/finsh/msh.c | 2 +- components/finsh/msh.h | 2 +- components/finsh/msh_file.c | 4 +- components/finsh/shell.c | 4 +- components/finsh/shell.h | 2 +- components/finsh/symbol.c | 4 +- components/libc/aio/posix_aio.c | 378 +-- components/libc/aio/posix_aio.h | 2 +- components/libc/compilers/armlibc/dirent.h | 28 +- components/libc/compilers/armlibc/fcntl.h | 2 +- components/libc/compilers/armlibc/libc.c | 2 +- components/libc/compilers/armlibc/libc.h | 2 +- components/libc/compilers/armlibc/libc_syms.c | 2 +- components/libc/compilers/armlibc/mem_std.c | 2 +- components/libc/compilers/armlibc/stdio.c | 2 +- components/libc/compilers/armlibc/stubs.c | 8 +- components/libc/compilers/armlibc/sys/errno.h | 2 +- components/libc/compilers/armlibc/sys/ioctl.h | 2 +- components/libc/compilers/armlibc/sys/mman.h | 2 +- components/libc/compilers/armlibc/sys/stat.h | 2 +- components/libc/compilers/armlibc/sys/types.h | 2 +- components/libc/compilers/armlibc/sys/unistd.h | 2 +- components/libc/compilers/armlibc/unistd.h | 2 +- components/libc/compilers/common/sys/time.h | 2 +- components/libc/compilers/common/termios.h | 2 +- components/libc/compilers/common/time.c | 6 +- components/libc/compilers/common/unistd.c | 2 +- components/libc/compilers/dlib/dirent.h | 2 +- components/libc/compilers/dlib/environ.c | 2 +- components/libc/compilers/dlib/fcntl.h | 2 +- components/libc/compilers/dlib/libc.c | 2 +- components/libc/compilers/dlib/libc.h | 2 +- components/libc/compilers/dlib/rmtx.c | 4 +- components/libc/compilers/dlib/stdio.c | 2 +- components/libc/compilers/dlib/sys/errno.h | 2 +- components/libc/compilers/dlib/sys/mman.h | 2 +- components/libc/compilers/dlib/sys/signal.h | 2 +- components/libc/compilers/dlib/sys/stat.h | 2 +- components/libc/compilers/dlib/sys/types.h | 2 +- components/libc/compilers/dlib/sys/unistd.h | 34 +- components/libc/compilers/dlib/syscall_close.c | 2 +- components/libc/compilers/dlib/syscall_lseek.c | 2 +- components/libc/compilers/dlib/syscall_mem.c | 2 +- components/libc/compilers/dlib/syscall_open.c | 2 +- components/libc/compilers/dlib/syscall_read.c | 2 +- components/libc/compilers/dlib/syscall_remove.c | 2 +- components/libc/compilers/dlib/syscall_write.c | 2 +- components/libc/compilers/dlib/syscalls.h | 2 +- components/libc/compilers/dlib/unistd.h | 2 +- components/libc/compilers/minilibc/ctype.c | 34 +- components/libc/compilers/minilibc/ctype.h | 2 +- components/libc/compilers/minilibc/errno.h | 4 +- components/libc/compilers/minilibc/inttypes.h | 2 +- components/libc/compilers/minilibc/math.c | 2 +- components/libc/compilers/minilibc/math.h | 2 +- components/libc/compilers/minilibc/qsort.c | 4 +- components/libc/compilers/minilibc/rand.c | 16 +- components/libc/compilers/minilibc/signal.h | 2 +- components/libc/compilers/minilibc/stddef.h | 2 +- components/libc/compilers/minilibc/stdint.h | 12 +- components/libc/compilers/minilibc/stdio.h | 10 +- components/libc/compilers/minilibc/stdlib.c | 70 +- components/libc/compilers/minilibc/stdlib.h | 2 +- components/libc/compilers/minilibc/string.c | 860 +++---- components/libc/compilers/minilibc/string.h | 32 +- components/libc/compilers/minilibc/sys/mman.h | 2 +- components/libc/compilers/minilibc/sys/stat.h | 50 +- components/libc/compilers/minilibc/sys/time.h | 38 +- components/libc/compilers/minilibc/sys/types.h | 4 +- components/libc/compilers/minilibc/time.c | 2 +- components/libc/compilers/minilibc/time.h | 2 +- components/libc/compilers/newlib/libc.c | 4 +- components/libc/compilers/newlib/libc.h | 4 +- components/libc/compilers/newlib/libc_syms.c | 2 +- components/libc/compilers/newlib/stdio.c | 6 +- components/libc/compilers/newlib/sys/dirent.h | 34 +- components/libc/compilers/newlib/sys/mman.h | 2 +- components/libc/compilers/newlib/sys/statfs.h | 8 +- components/libc/compilers/newlib/sys/termios.h | 2 +- components/libc/compilers/newlib/syscalls.c | 2 +- components/libc/libdl/arch/arm.c | 4 +- components/libc/libdl/arch/x86.c | 10 +- components/libc/libdl/dlclose.c | 2 +- components/libc/libdl/dlelf.c | 10 +- components/libc/libdl/dlelf.h | 4 +- components/libc/libdl/dlerror.c | 6 +- components/libc/libdl/dlfcn.h | 4 +- components/libc/libdl/dlmodule.c | 6 +- components/libc/libdl/dlmodule.h | 2 +- components/libc/libdl/dlopen.c | 6 +- components/libc/libdl/dlsym.c | 4 +- components/libc/mmap/posix_mmap.c | 2 +- components/libc/pthreads/mqueue.c | 2 +- components/libc/pthreads/mqueue.h | 2 +- components/libc/pthreads/posix_types.h | 4 +- components/libc/pthreads/pthread.c | 4 +- components/libc/pthreads/pthread.h | 4 +- components/libc/pthreads/pthread_attr.c | 4 +- components/libc/pthreads/pthread_barrier.c | 2 +- components/libc/pthreads/pthread_cond.c | 10 +- components/libc/pthreads/pthread_internal.h | 2 +- components/libc/pthreads/pthread_mutex.c | 4 +- components/libc/pthreads/pthread_rwlock.c | 10 +- components/libc/pthreads/pthread_spin.c | 2 +- components/libc/pthreads/pthread_tls.c | 2 +- components/libc/pthreads/sched.c | 2 +- components/libc/pthreads/sched.h | 2 +- components/libc/pthreads/semaphore.c | 2 +- components/libc/pthreads/semaphore.h | 2 +- components/libc/signal/posix_signal.c | 2 +- components/libc/signal/posix_signal.h | 2 +- components/libc/termios/posix_termios.c | 2 +- components/libc/termios/posix_termios.h | 2 +- components/libc/time/clock_time.c | 4 +- components/libc/time/clock_time.h | 2 +- components/libc/time/posix_sleep.c | 2 +- components/net/at/at_socket/at_socket.c | 40 +- components/net/at/at_socket/at_socket.h | 2 +- components/net/at/include/at.h | 2 +- components/net/at/include/at_log.h | 2 +- components/net/at/src/at_base_cmd.c | 2 +- components/net/at/src/at_cli.c | 4 +- components/net/at/src/at_client.c | 4 +- components/net/at/src/at_server.c | 2 +- components/net/at/src/at_utils.c | 2 +- components/net/lwip-1.4.1/src/arch/sys_arch.c | 8 +- components/net/lwip-1.4.1/src/netif/ethernetif.c | 50 +- components/net/lwip-2.0.2/src/arch/sys_arch.c | 2 +- components/net/lwip-2.0.2/src/netif/ethernetif.c | 72 +- components/net/lwip-2.1.2/src/arch/sys_arch.c | 2 +- components/net/lwip-2.1.2/src/netif/ethernetif.c | 78 +- components/net/lwip_dhcpd/dhcp_server.c | 2 +- components/net/lwip_dhcpd/dhcp_server.h | 2 +- components/net/lwip_dhcpd/dhcp_server_raw.c | 4 +- components/net/netdev/include/arpa/inet.h | 2 +- components/net/netdev/include/netdev.h | 10 +- components/net/netdev/include/netdev_ipaddr.h | 42 +- components/net/netdev/src/netdev.c | 2 +- components/net/netdev/src/netdev_ipaddr.c | 2 +- components/net/sal_socket/dfs_net/dfs_net.c | 6 +- components/net/sal_socket/impl/af_inet.h | 2 +- components/net/sal_socket/impl/af_inet_at.c | 4 +- components/net/sal_socket/impl/af_inet_lwip.c | 8 +- components/net/sal_socket/impl/proto_mbedtls.c | 22 +- .../net/sal_socket/include/dfs_net/dfs_net.h | 2 +- .../include/dfs_net/sys_select/sys/select.h | 2 +- components/net/sal_socket/include/sal.h | 2 +- components/net/sal_socket/include/sal_netdb.h | 2 +- components/net/sal_socket/include/sal_socket.h | 4 +- components/net/sal_socket/include/sal_tls.h | 2 +- components/net/sal_socket/include/socket/netdb.h | 2 +- .../net/sal_socket/include/socket/netinet/in.h | 2 +- .../net/sal_socket/include/socket/netinet/tcp.h | 2 +- .../net/sal_socket/include/socket/netinet/udp.h | 2 +- .../include/socket/sys_socket/sys/socket.h | 2 +- components/net/sal_socket/socket/net_netdb.c | 2 +- components/net/sal_socket/socket/net_sockets.c | 6 +- components/net/sal_socket/src/sal_socket.c | 2 +- components/net/uip/rt-thread/uip_ethernetif.c | 386 +-- components/utilities/ulog/backend/console_be.c | 2 +- components/utilities/ulog/syslog/syslog.c | 2 +- components/utilities/ulog/syslog/syslog.h | 2 +- components/utilities/ulog/ulog.c | 2 +- components/utilities/ulog/ulog.h | 2 +- components/utilities/ulog/ulog_def.h | 8 +- components/utilities/utest/utest.c | 2 +- components/utilities/utest/utest.h | 60 +- components/utilities/utest/utest_assert.h | 10 +- components/utilities/utest/utest_log.h | 2 +- components/utilities/ymodem/ymodem.c | 2 +- components/vbus/prio_queue.c | 2 +- components/vbus/prio_queue.h | 2 +- components/vbus/share_hdr/vbus_api.h | 2 +- components/vbus/vbus.c | 12 +- components/vbus/vbus.h | 12 +- components/vbus/vbus_chnx.c | 2 +- components/vbus/watermark_queue.c | 2 +- components/vbus/watermark_queue.h | 2 +- components/vmm/vmm.c | 4 +- components/vmm/vmm.h | 4 +- components/vmm/vmm_context.c | 4 +- components/vmm/vmm_context.h | 4 +- components/vmm/vmm_iomap.c | 4 +- components/vmm/vmm_vector.c | 12 +- documentation/doxygen/kernel.h | 8 +- documentation/doxygen/systeminit.h | 2 +- examples/file/listdir.c | 52 +- examples/file/readspeed.c | 4 +- examples/file/writespeed.c | 38 +- examples/kernel/tc_comm.h | 2 +- examples/pm/timer_app.c | 2 +- examples/pm/wakeup_app.c | 2 +- examples/test/net_test.c | 436 ++-- examples/test/rtc_test.c | 38 +- examples/ulog/ulog_example.c | 2 +- include/libc/libc_dirent.h | 2 +- include/libc/libc_errno.h | 4 +- include/libc/libc_fcntl.h | 4 +- include/libc/libc_fdset.h | 2 +- include/libc/libc_ioctl.h | 166 +- include/libc/libc_signal.h | 8 +- include/libc/libc_stat.h | 2 +- include/rtdbg.h | 2 +- include/rtdebug.h | 2 +- include/rtdef.h | 2 +- include/rthw.h | 4 +- include/rtlibc.h | 2 +- include/rtm.h | 2 +- include/rtservice.h | 16 +- include/rtthread.h | 2 +- libcpu/arm/AT91SAM7S/AT91SAM7S.h | 478 ++-- libcpu/arm/AT91SAM7S/cpu.c | 6 +- libcpu/arm/AT91SAM7S/interrupt.c | 46 +- libcpu/arm/AT91SAM7S/serial.c | 582 ++--- libcpu/arm/AT91SAM7S/serial.h | 76 +- libcpu/arm/AT91SAM7S/stack.c | 2 +- libcpu/arm/AT91SAM7S/trap.c | 10 +- libcpu/arm/AT91SAM7X/cpu.c | 6 +- libcpu/arm/AT91SAM7X/interrupt.c | 66 +- libcpu/arm/AT91SAM7X/stack.c | 2 +- libcpu/arm/AT91SAM7X/trap.c | 24 +- libcpu/arm/am335x/am33xx.h | 90 +- libcpu/arm/am335x/cpu.c | 112 +- libcpu/arm/am335x/interrupt.c | 8 +- libcpu/arm/am335x/interrupt.h | 42 +- libcpu/arm/am335x/mmu.c | 108 +- libcpu/arm/am335x/mmu.h | 44 +- libcpu/arm/am335x/stack.c | 2 +- libcpu/arm/am335x/trap.c | 66 +- libcpu/arm/arm926/cpuport.c | 2 +- libcpu/arm/arm926/machine.c | 2 +- libcpu/arm/arm926/mmu.c | 2 +- libcpu/arm/arm926/mmu.h | 2 +- libcpu/arm/arm926/stack.c | 2 +- libcpu/arm/arm926/trap.c | 2 +- libcpu/arm/armv6/armv6.h | 42 +- libcpu/arm/armv6/cpuport.c | 172 +- libcpu/arm/armv6/mmu.c | 638 ++--- libcpu/arm/armv6/mmu.h | 54 +- libcpu/arm/armv6/stack.c | 2 +- libcpu/arm/armv6/vfp.c | 2 +- libcpu/arm/armv6/vfp.h | 4 +- libcpu/arm/common/backtrace.c | 2 +- libcpu/arm/common/div0.c | 4 +- libcpu/arm/common/showmem.c | 34 +- libcpu/arm/cortex-a/armv7.h | 68 +- libcpu/arm/cortex-a/cache.c | 4 +- libcpu/arm/cortex-a/cp15.h | 2 +- libcpu/arm/cortex-a/cpu.c | 2 +- libcpu/arm/cortex-a/gic.c | 2 +- libcpu/arm/cortex-a/gic.h | 2 +- libcpu/arm/cortex-a/interrupt.c | 2 +- libcpu/arm/cortex-a/interrupt.h | 2 +- libcpu/arm/cortex-a/mmu.c | 2 +- libcpu/arm/cortex-a/mmu.h | 2 +- libcpu/arm/cortex-a/pmu.c | 2 +- libcpu/arm/cortex-a/pmu.h | 2 +- libcpu/arm/cortex-a/stack.c | 2 +- libcpu/arm/cortex-a/trap.c | 2 +- libcpu/arm/cortex-m0/cpuport.c | 2 +- libcpu/arm/cortex-m3/cpuport.c | 2 +- libcpu/arm/cortex-m4/cpuport.c | 4 +- libcpu/arm/cortex-m7/cpuport.c | 2 +- libcpu/arm/cortex-r4/armv7.h | 36 +- libcpu/arm/cortex-r4/cpu.c | 18 +- libcpu/arm/cortex-r4/interrupt.c | 52 +- libcpu/arm/cortex-r4/stack.c | 2 +- libcpu/arm/cortex-r4/trap.c | 42 +- libcpu/arm/dm36x/cpuport.c | 172 +- libcpu/arm/dm36x/mmu.c | 232 +- libcpu/arm/dm36x/mmu.h | 22 +- libcpu/arm/dm36x/stack.c | 2 +- libcpu/arm/lpc214x/cpuport.c | 134 +- libcpu/arm/lpc24xx/LPC24xx.h | 680 +++--- libcpu/arm/lpc24xx/cpu.c | 6 +- libcpu/arm/lpc24xx/interrupt.c | 76 +- libcpu/arm/lpc24xx/stack.c | 2 +- libcpu/arm/lpc24xx/trap.c | 54 +- libcpu/arm/realview-a8-vmm/armv7.h | 68 +- libcpu/arm/realview-a8-vmm/cp15.h | 2 +- libcpu/arm/realview-a8-vmm/cpu.c | 16 +- libcpu/arm/realview-a8-vmm/gic.c | 2 +- libcpu/arm/realview-a8-vmm/gic.h | 2 +- libcpu/arm/realview-a8-vmm/interrupt.c | 2 +- libcpu/arm/realview-a8-vmm/interrupt.h | 42 +- libcpu/arm/realview-a8-vmm/mmu.c | 2 +- libcpu/arm/realview-a8-vmm/pmu.c | 2 +- libcpu/arm/realview-a8-vmm/pmu.h | 2 +- libcpu/arm/realview-a8-vmm/stack.c | 2 +- libcpu/arm/realview-a8-vmm/trap.c | 4 +- libcpu/arm/s3c24x0/cpu.c | 132 +- libcpu/arm/s3c24x0/interrupt.c | 30 +- libcpu/arm/s3c24x0/mmu.c | 268 +-- libcpu/arm/s3c24x0/rtc.c | 226 +- libcpu/arm/s3c24x0/rtc.h | 2 +- libcpu/arm/s3c24x0/s3c24x0.h | 78 +- libcpu/arm/s3c24x0/stack.c | 2 +- libcpu/arm/s3c24x0/system_clock.c | 108 +- libcpu/arm/s3c24x0/trap.c | 62 +- libcpu/arm/s3c44b0/cpu.c | 68 +- libcpu/arm/s3c44b0/interrupt.c | 150 +- libcpu/arm/s3c44b0/s3c44b0.h | 480 ++-- libcpu/arm/s3c44b0/serial.c | 72 +- libcpu/arm/s3c44b0/stack.c | 2 +- libcpu/arm/s3c44b0/trap.c | 100 +- libcpu/arm/sep4020/clk.c | 108 +- libcpu/arm/sep4020/cpu.c | 120 +- libcpu/arm/sep4020/interrupt.c | 24 +- libcpu/arm/sep4020/sep4020.h | 180 +- libcpu/arm/sep4020/serial.c | 430 ++-- libcpu/arm/sep4020/serial.h | 62 +- libcpu/arm/sep4020/stack.c | 2 +- libcpu/arm/sep4020/trap.c | 62 +- libcpu/avr32/uc3/cpu.c | 6 +- libcpu/avr32/uc3/serial.c | 396 ++-- libcpu/avr32/uc3/serial.h | 20 +- libcpu/avr32/uc3/stack.c | 40 +- libcpu/blackfin/bf53x/cpuport.c | 8 +- libcpu/blackfin/bf53x/serial.c | 430 ++-- libcpu/ia32/__udivsi3.c | 46 +- libcpu/ia32/__umodsi3.c | 46 +- libcpu/ia32/backtrace.c | 2 +- libcpu/ia32/interrupt.c | 92 +- libcpu/ia32/showmem.c | 32 +- libcpu/ia32/stack.c | 46 +- libcpu/ia32/trap.c | 88 +- libcpu/m16c/m16c62p/cpuport.c | 2 +- libcpu/mips/common/exception.h | 212 +- libcpu/mips/common/mips.h | 2 +- libcpu/mips/common/mips_addrspace.h | 138 +- libcpu/mips/common/mips_asm.h | 186 +- libcpu/mips/common/mips_cache.c | 16 +- libcpu/mips/common/mips_cache.h | 96 +- libcpu/mips/common/mips_cfg.h | 2 +- libcpu/mips/common/mips_context.h | 432 ++-- libcpu/mips/common/mips_def.h | 2248 +++++++++--------- libcpu/mips/common/mips_regs.h | 1216 +++++----- libcpu/mips/common/mipscfg.h | 2 +- libcpu/mips/loongson_1b/cache.c | 198 +- libcpu/mips/loongson_1b/cache.h | 48 +- libcpu/mips/loongson_1b/cpuport.c | 104 +- libcpu/mips/loongson_1b/exception.c | 46 +- libcpu/mips/loongson_1b/interrupt.c | 2 +- libcpu/mips/loongson_1b/ls1b.h | 174 +- libcpu/mips/loongson_1b/mipscfg.c | 60 +- libcpu/mips/loongson_1c/cache.c | 198 +- libcpu/mips/loongson_1c/cache.h | 48 +- libcpu/mips/loongson_1c/cpuport.c | 148 +- libcpu/mips/loongson_1c/exception.c | 46 +- libcpu/mips/loongson_1c/mipscfg.c | 60 +- libcpu/mips/pic32/cpuport.c | 82 +- libcpu/nios/nios_ii/stack.c | 68 +- libcpu/ppc/common/stack.c | 4 +- libcpu/ppc/ppc405/interrupt.c | 92 +- libcpu/rx/cpuport.c | 66 +- libcpu/ti-dsp/c28x/cpuport.c | 2 +- libcpu/unicore32/sep6200/cpu.c | 106 +- libcpu/unicore32/sep6200/interrupt.c | 126 +- libcpu/unicore32/sep6200/sep6200.h | 218 +- libcpu/unicore32/sep6200/serial.c | 404 ++-- libcpu/unicore32/sep6200/serial.h | 66 +- libcpu/unicore32/sep6200/stack.c | 76 +- libcpu/unicore32/sep6200/trap.c | 68 +- libcpu/xilinx/microblaze/cpu.c | 4 +- libcpu/xilinx/microblaze/serial.c | 448 ++-- libcpu/xilinx/microblaze/stack.c | 72 +- libcpu/xilinx/microblaze/trap.c | 202 +- src/clock.c | 4 +- src/components.c | 4 +- src/cpu.c | 2 +- src/device.c | 2 +- src/idle.c | 4 +- src/ipc.c | 18 +- src/irq.c | 6 +- src/kservice.c | 8 +- src/mem.c | 4 +- src/memheap.c | 4 +- src/mempool.c | 2 +- src/object.c | 10 +- src/scheduler.c | 2 +- src/signal.c | 2 +- src/slab.c | 2 +- src/thread.c | 2 +- 1584 files changed, 45209 insertions(+), 45209 deletions(-) diff --git a/bsp/CME_M7/applications/application.c b/bsp/CME_M7/applications/application.c index 1781af13bf..c5346448c3 100644 --- a/bsp/CME_M7/applications/application.c +++ b/bsp/CME_M7/applications/application.c @@ -28,10 +28,10 @@ int rt_application_init() tid = rt_thread_create("init", rt_init_thread_entry, - RT_NULL, + RT_NULL, 2048, - RT_THREAD_PRIORITY_MAX/3, - 20); + RT_THREAD_PRIORITY_MAX/3, + 20); if (tid != RT_NULL) rt_thread_startup(tid); diff --git a/bsp/CME_M7/applications/startup.c b/bsp/CME_M7/applications/startup.c index edff582d1f..d04acd1281 100644 --- a/bsp/CME_M7/applications/startup.c +++ b/bsp/CME_M7/applications/startup.c @@ -1,7 +1,7 @@ /* * File : startup.c * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2014, RT-Thread Develop Team + * COPYRIGHT (C) 2006-2021, RT-Thread Develop Team * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at diff --git a/bsp/CME_M7/drivers/board.h b/bsp/CME_M7/drivers/board.h index b6edbb5bb8..c622b546dd 100644 --- a/bsp/CME_M7/drivers/board.h +++ b/bsp/CME_M7/drivers/board.h @@ -14,7 +14,7 @@ #include "cmem7_includes.h" //#include "cmem7_retarget.h" -#define SRAM_SIZE 64 // KB +#define SRAM_SIZE 64 // KB #define SRAM_END (0x20000000 + SRAM_SIZE * 1024) //#define RT_USING_UART0 diff --git a/bsp/CME_M7/drivers/emac.c b/bsp/CME_M7/drivers/emac.c index 5f732a8c51..ebc91c5e06 100644 --- a/bsp/CME_M7/drivers/emac.c +++ b/bsp/CME_M7/drivers/emac.c @@ -1,7 +1,7 @@ /* * File : emac.c * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2014, RT-Thread Develop Team + * COPYRIGHT (C) 2006-2021, RT-Thread Develop Team * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at @@ -38,7 +38,7 @@ struct rt_cme_eth struct eth_device parent; /* interface address info. */ - rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ uint32_t ETH_Speed; uint32_t ETH_Mode; @@ -95,8 +95,8 @@ uint32_t txTotalMemory = 0x2000; BOOL isRxNoBuf = FALSE; #define ETH_MAX_PACKET_SIZE 1520 /* ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */ -#define ETH_RXBUFNB 4 -#define ETH_TXBUFNB 2 +#define ETH_RXBUFNB 4 +#define ETH_TXBUFNB 2 struct eth_rx_buffer { diff --git a/bsp/CME_M7/rtconfig.h b/bsp/CME_M7/rtconfig.h index a16dddf4d9..fadd84e9bb 100644 --- a/bsp/CME_M7/rtconfig.h +++ b/bsp/CME_M7/rtconfig.h @@ -3,16 +3,16 @@ #define __RTTHREAD_CFG_H__ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 32 +#define RT_THREAD_PRIORITY_MAX 32 /* Tick per Second */ -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 /* SECTION: RT_DEBUG */ /* Thread Debug */ @@ -61,8 +61,8 @@ /* SECTION: Console options */ #define RT_USING_CONSOLE /* the buffer size of console*/ -#define RT_CONSOLEBUF_SIZE 128 -#define RT_CONSOLE_DEVICE_NAME "uart2" +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart2" /* SECTION: finsh, a C-Express shell */ #define RT_USING_FINSH @@ -79,15 +79,15 @@ #define RT_USING_DFS_ELMFAT #define RT_DFS_ELM_REENTRANT #define RT_DFS_ELM_WORD_ACCESS -#define RT_DFS_ELM_DRIVES 1 -#define RT_DFS_ELM_USE_LFN 2 -#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 1 +#define RT_DFS_ELM_USE_LFN 2 +#define RT_DFS_ELM_MAX_LFN 255 #define RT_DFS_ELM_MAX_SECTOR_SIZE 512 /* the max number of mounted filesystem */ -#define DFS_FILESYSTEMS_MAX 2 -/* the max number of opened files */ -#define DFS_FD_MAX 4 +#define DFS_FILESYSTEMS_MAX 2 +/* the max number of opened files */ +#define DFS_FD_MAX 4 /* SECTION: lwip, a lighwight TCP/IP protocol stack */ #define RT_USING_LWIP @@ -121,13 +121,13 @@ #define RT_LWIP_MSKADDR "255.255.255.0" /* tcp thread options */ -#define RT_LWIP_TCPTHREAD_PRIORITY 12 -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4 -#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4 +#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 -#define RT_LWIP_ETHTHREAD_PRIORITY 15 -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4 -#define RT_LWIP_ETHTHREAD_STACKSIZE 512 +#define RT_LWIP_ETHTHREAD_PRIORITY 15 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4 +#define RT_LWIP_ETHTHREAD_STACKSIZE 512 // // #define RT_USING_CMSIS_OS diff --git a/bsp/allwinner_tina/drivers/drv_clock.c b/bsp/allwinner_tina/drivers/drv_clock.c index 3154f9dc3f..9fec431f4b 100644 --- a/bsp/allwinner_tina/drivers/drv_clock.c +++ b/bsp/allwinner_tina/drivers/drv_clock.c @@ -527,7 +527,7 @@ rt_err_t mmc_set_clk(enum mmc_clk_id clk_id, int hz) *mmc_clk &= ~(0x1 << 31); return RT_EOK; } - + if (hz <= 24000000) { pll = (0x0 << 24); @@ -579,7 +579,7 @@ rt_err_t mmc_set_clk(enum mmc_clk_id clk_id, int hz) oclk_dly = 1; sclk_dly = 4; } - + *mmc_clk = (0x1 << 31) | pll | (sclk_dly << 20) | \ (n << 16) | (oclk_dly << 8) | (div - 1); diff --git a/bsp/allwinner_tina/drivers/drv_clock.h b/bsp/allwinner_tina/drivers/drv_clock.h index 0d09c73f14..1623791672 100644 --- a/bsp/allwinner_tina/drivers/drv_clock.h +++ b/bsp/allwinner_tina/drivers/drv_clock.h @@ -238,4 +238,4 @@ rt_err_t dram_gate_clk_enable(enum dram_gate dram_gate); rt_err_t dram_gate_clk_disable(enum dram_gate dram_gate); rt_err_t mmc_set_clk(enum mmc_clk_id clk_id, int hz); -#endif \ No newline at end of file +#endif diff --git a/bsp/allwinner_tina/drivers/drv_gpio.h b/bsp/allwinner_tina/drivers/drv_gpio.h index 7620466353..74dd5a9be0 100644 --- a/bsp/allwinner_tina/drivers/drv_gpio.h +++ b/bsp/allwinner_tina/drivers/drv_gpio.h @@ -227,4 +227,4 @@ void gpio_set_debounce(enum gpio_port port, rt_uint8_t prescaler); void gpio_set_irq_callback(enum gpio_port port, enum gpio_pin pin, void (*irq_cb)(void *), void *irq_arg); int rt_hw_gpio_init(void); -#endif /* __DRV_GPIO_H__ */ \ No newline at end of file +#endif /* __DRV_GPIO_H__ */ diff --git a/bsp/allwinner_tina/drivers/drv_sdio.c b/bsp/allwinner_tina/drivers/drv_sdio.c index db40d01986..f19cd60d5c 100644 --- a/bsp/allwinner_tina/drivers/drv_sdio.c +++ b/bsp/allwinner_tina/drivers/drv_sdio.c @@ -20,10 +20,10 @@ #define DBG_TAG "MMC" -// #define DBG_LVL DBG_LOG -// #define DBG_LVL DBG_INFO +// #define DBG_LVL DBG_LOG +// #define DBG_LVL DBG_INFO #define DBG_LVL DBG_WARNING -// #define DBG_LVL DBG_ERROR +// #define DBG_LVL DBG_ERROR #include #ifdef RT_USING_SDIO @@ -33,12 +33,12 @@ struct mmc_xfe_des { rt_uint32_t size; /* block size */ - rt_uint32_t num; /* block num */ - rt_uint8_t *buff; /* buff addr */ - rt_uint32_t flag; /* write or read or stream */ -#define MMC_DATA_WRITE (1 << 0) -#define MMC_DATA_READ (1 << 1) -#define MMC_DATA_STREAM (1 << 2) + rt_uint32_t num; /* block num */ + rt_uint8_t *buff; /* buff addr */ + rt_uint32_t flag; /* write or read or stream */ +#define MMC_DATA_WRITE (1 << 0) +#define MMC_DATA_READ (1 << 1) +#define MMC_DATA_STREAM (1 << 2) }; struct mmc_flag @@ -57,7 +57,7 @@ struct sdio_drv tina_mmc_t mmc_des; rt_uint8_t *mmc_buf; rt_uint8_t usedma; - + }; #ifdef CONFIG_MMC_USE_DMA @@ -122,7 +122,7 @@ static int mmc_update_clk(tina_mmc_t mmc) mmc->risr_reg = mmc->risr_reg; return RT_EOK; } - + static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe) { ALIGN(32) static struct mmc_des_v4p1 pdes[128]; // mast ALIGN(32) @@ -131,7 +131,7 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe) unsigned length = xfe->size * xfe->num; unsigned buff_frag_num = length >> SDXC_DES_NUM_SHIFT; unsigned remain = length & (SDXC_DES_BUFFER_MAX_LEN - 1); - + if (remain) { buff_frag_num ++; @@ -142,7 +142,7 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe) } memset(pdes, 0, sizeof(pdes)); mmu_clean_dcache((rt_uint32_t)(xfe->buff), length); - for (i = 0, des_idx = 0; i < buff_frag_num; i++, des_idx++) + for (i = 0, des_idx = 0; i < buff_frag_num; i++, des_idx++) { // memset((void*)&pdes[des_idx], 0, sizeof(struct mmc_v4p1)); pdes[des_idx].des_chain = 1; @@ -168,8 +168,8 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe) pdes[des_idx].last_des = 1; pdes[des_idx].end_of_ring = 1; pdes[des_idx].buf_addr_ptr2 = 0; - } - else + } + else { pdes[des_idx].buf_addr_ptr2 = (unsigned long)&pdes[des_idx+1]; } @@ -203,7 +203,7 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe) mmc->dmac_reg = (1 << 1) | (1 << 7); /* idma on */ rval = mmc->idie_reg & (~3); if (xfe->flag == MMC_DATA_WRITE) - rval |= (1 << 0); + rval |= (1 << 0); else rval |= (1 << 1); mmc->idie_reg = rval; @@ -222,7 +222,7 @@ static rt_err_t mmc_trans_data_by_cpu(tina_mmc_t mmc, struct mmc_xfe_des *xfe) if (xfe->flag == MMC_DATA_WRITE) { - for (i = 0; i < (byte_cnt >> 2); i++) + for (i = 0; i < (byte_cnt >> 2); i++) { while(--timeout && (mmc->star_reg & (1 << 3))); @@ -237,7 +237,7 @@ static rt_err_t mmc_trans_data_by_cpu(tina_mmc_t mmc, struct mmc_xfe_des *xfe) } else { - for (i = 0; i < (byte_cnt >> 2); i++) + for (i = 0; i < (byte_cnt >> 2); i++) { while(--timeout && (mmc->star_reg & (1 << 2))); @@ -276,7 +276,7 @@ static rt_err_t mmc_config_clock(tina_mmc_t mmc, int clk) { mmc_set_clk(SDMMC1, clk); } - + /* Re-enable card clock */ rval = mmc->ckcr_reg; rval |= (0x1 << 16); //(3 << 16); @@ -369,7 +369,7 @@ static int mmc_send_cmd(struct rt_mmcsd_host *host, struct rt_mmcsd_cmd *cmd) cmdval |= (1 << 7); if ((resp_type(cmd) != RESP_R3) && (resp_type(cmd) != RESP_R4)) cmdval |= (1 << 8); - + if (data) { cmdval |= (1 << 9) | (1 << 13); @@ -592,7 +592,7 @@ static void sdio_request_send(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r memset(&sdio->flag, 0, sizeof(struct mmc_flag)); mmc_send_cmd(host, req->cmd); - + return; } diff --git a/bsp/allwinner_tina/drivers/drv_sdio.h b/bsp/allwinner_tina/drivers/drv_sdio.h index 589ea287f1..ef7a7c4108 100644 --- a/bsp/allwinner_tina/drivers/drv_sdio.h +++ b/bsp/allwinner_tina/drivers/drv_sdio.h @@ -119,8 +119,8 @@ REG[31] : Load cmd #define SDXC_UPDATE_CLOCK_CMD BIT(21) #define SDXC_LOAD_CMD BIT(31) -/* - SD status reg +/* + SD status reg REG[0] : FIFO_RX_LEVEL REG[1] : FIFO_TX_LEVEL REG[2] : FIFO_EMPTY @@ -129,7 +129,7 @@ REG[4-7] : FSM_STA REG[8] : CARD_PRESENT REG[9] : CARD_BUSY REG[10] : FSM_BUSY -REG[11-16]: RESP_IDX +REG[11-16]: RESP_IDX REG[17-21]: FIFO_LEVEL REG[31] : DMA_REQ */ diff --git a/bsp/allwinner_tina/drivers/drv_uart.c b/bsp/allwinner_tina/drivers/drv_uart.c index d3d015459e..a2889c598f 100644 --- a/bsp/allwinner_tina/drivers/drv_uart.c +++ b/bsp/allwinner_tina/drivers/drv_uart.c @@ -310,4 +310,4 @@ void uart_irq_handler(int irqno, void *param) } -#endif \ No newline at end of file +#endif diff --git a/bsp/allwinner_tina/drivers/spi/drv_spi_flash.c b/bsp/allwinner_tina/drivers/spi/drv_spi_flash.c index 313ab9d6a7..5e4edc9c6b 100644 --- a/bsp/allwinner_tina/drivers/spi/drv_spi_flash.c +++ b/bsp/allwinner_tina/drivers/spi/drv_spi_flash.c @@ -51,4 +51,4 @@ INIT_PREV_EXPORT(rt_hw_spi_flash_with_sfud_init); #endif -#endif \ No newline at end of file +#endif diff --git a/bsp/amebaz/drivers/board.c b/bsp/amebaz/drivers/board.c index e6ce4f999f..7631bd13d6 100644 --- a/bsp/amebaz/drivers/board.c +++ b/bsp/amebaz/drivers/board.c @@ -40,7 +40,7 @@ void __wrap_rtl_printf(const char *fmt, ...) * length. */ length = rt_vsnprintf(rt_log_buf, sizeof(rt_log_buf) - 1, fmt, args); if (length > RT_CONSOLEBUF_SIZE - 1) - length = RT_CONSOLEBUF_SIZE - 1; + length = RT_CONSOLEBUF_SIZE - 1; rt_kprintf("%s", rt_log_buf); va_end(args); } @@ -85,11 +85,11 @@ void rt_hw_board_init(void) #ifdef RT_USING_HEAP rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END); #endif - + #ifdef RT_USING_COMPONENTS_INIT rt_components_board_init(); #endif - + #ifdef RT_USING_CONSOLE rt_hw_uart_init(); rt_console_set_device(RT_CONSOLE_DEVICE_NAME); diff --git a/bsp/amebaz/drivers/drv_uart.c b/bsp/amebaz/drivers/drv_uart.c index 88a4ba9d68..008fa3bda5 100644 --- a/bsp/amebaz/drivers/drv_uart.c +++ b/bsp/amebaz/drivers/drv_uart.c @@ -111,7 +111,7 @@ static int ameba_uart_getc (struct rt_serial_device *serial) { struct device_uart* uart = serial->parent.user_data; - if(!serial_readable(&uart->serial)) + if(!serial_readable(&uart->serial)) return -1; /* Receive Data Available */ @@ -126,13 +126,13 @@ static rt_size_t ameba_uart_dma_transmit (struct rt_serial_device *serial, rt_ui static void ameba_uart_irq(uint32_t id, SerialIrq event) { struct rt_serial_device *serial = (struct rt_serial_device *)id; - if(event == RxIrq) + if(event == RxIrq) { rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); - } - else if(event == TxIrq) + } + else if(event == TxIrq) { - } + } } static rt_err_t dbg_configure(struct rt_serial_device *serial, struct serial_configure *cfg); @@ -141,7 +141,7 @@ static int dbg_putc(struct rt_serial_device *serial, char c); static int dbg_getc(struct rt_serial_device *serial); static struct rt_serial_device ameba_dbg_serial; -const struct rt_uart_ops _ambed_dbg_ops = +const struct rt_uart_ops _ambed_dbg_ops = { dbg_configure, dbg_control, @@ -163,7 +163,7 @@ void dbg_uart_irq_handler(void * data) DiagSetIsrEnReg(0); rt_hw_serial_isr(&ameba_dbg_serial, RT_SERIAL_EVENT_RX_IND); - + DiagSetIsrEnReg(IrqEn); } @@ -178,9 +178,9 @@ static rt_err_t dbg_control(struct rt_serial_device *serial, int cmd, void *arg) case RT_DEVICE_CTRL_SET_INT: /* install interrupt */ - DIAG_UartReInit((IRQ_FUN) dbg_uart_irq_handler); + DIAG_UartReInit((IRQ_FUN) dbg_uart_irq_handler); /* Enable the UART Interrupt */ - NVIC_SetPriority(UART_LOG_IRQ, 10); /* this is rom_code_patch */ + NVIC_SetPriority(UART_LOG_IRQ, 10); /* this is rom_code_patch */ break; } @@ -200,12 +200,12 @@ static int dbg_getc(struct rt_serial_device *serial) if(!UART_Readable(UART2_DEV)) return -1; - + c = DiagGetChar(_FALSE); return c; } - + /* * UART Initiation */ @@ -217,7 +217,7 @@ int rt_hw_uart_init(void) #ifdef BSP_USING_UART0 { struct device_uart *uart; - + serial = &serial0; uart = &uart0; @@ -242,7 +242,7 @@ int rt_hw_uart_init(void) serial->ops = &_ambed_dbg_ops; serial->config = config; - + rt_hw_serial_register(serial, RT_CONSOLE_DEVICE_NAME, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, diff --git a/bsp/amebaz/drivers/wlan/drv_wifi.c b/bsp/amebaz/drivers/wlan/drv_wifi.c index 4ab976a903..7d8cade15e 100644 --- a/bsp/amebaz/drivers/wlan/drv_wifi.c +++ b/bsp/amebaz/drivers/wlan/drv_wifi.c @@ -101,7 +101,7 @@ void netif_pre_sleep_processing(void) } unsigned char *rltk_wlan_get_ip(int idx) -{ +{ struct ameba_wifi *wifi; wifi = rthw_wifi_get_dev(idx); @@ -116,7 +116,7 @@ unsigned char *rltk_wlan_get_ip(int idx) int netif_is_valid_IP(int idx, unsigned char *ip_dest) { - LOG_D("F:%s L:%d is run ip: %d:%d:%d:%d", __FUNCTION__, __LINE__, + LOG_D("F:%s L:%d is run ip: %d:%d:%d:%d", __FUNCTION__, __LINE__, ip_dest[0], ip_dest[1], ip_dest[2], ip_dest[3]); return 1; } @@ -362,9 +362,9 @@ static rt_err_t rthw_wlan_join (struct rt_wlan_device *wlan, str ssid = &sta_info->ssid.val[0]; if (sta_info->key.len > 0) key = &sta_info->key.val[0]; - LOG_D("bssid connect bssid: %02x:%02x:%02x:%02x:%02x:%02x ssid:%s ssid_len:%d key:%s key_len%d", + LOG_D("bssid connect bssid: %02x:%02x:%02x:%02x:%02x:%02x ssid:%s ssid_len:%d key:%s key_len%d", sta_info->bssid[0],sta_info->bssid[1],sta_info->bssid[2],sta_info->bssid[3],sta_info->bssid[4],sta_info->bssid[5], - ssid, + ssid, sta_info->ssid.len, key, sta_info->key.len @@ -594,7 +594,7 @@ exit: return RT_EOK; } -static const struct rt_wlan_dev_ops ops = +static const struct rt_wlan_dev_ops ops = { .wlan_init = rthw_wlan_init , .wlan_mode = rthw_wlan_mode , diff --git a/bsp/amebaz/drivers/wlan/drv_wifi.h b/bsp/amebaz/drivers/wlan/drv_wifi.h index c40c200ee6..2ca7c799c8 100644 --- a/bsp/amebaz/drivers/wlan/drv_wifi.h +++ b/bsp/amebaz/drivers/wlan/drv_wifi.h @@ -7,7 +7,7 @@ * Date Author Notes * 2017-5-30 Bernard the first version */ - + #ifndef __DRV_WIFI_H__ #define __DRV_WIFI_H__ diff --git a/bsp/amebaz/drivers/wlan/drv_wlan.c b/bsp/amebaz/drivers/wlan/drv_wlan.c index 300cdeb467..1eedea54c0 100644 --- a/bsp/amebaz/drivers/wlan/drv_wlan.c +++ b/bsp/amebaz/drivers/wlan/drv_wlan.c @@ -137,20 +137,20 @@ int rthw_wifi_ap_start(char *ssid, char *password, int channel) return -1; } - while(1) + while(1) { char essid[33]; if(wext_get_ssid(name, (unsigned char *) essid) > 0) { - if(strcmp((const char *) essid, (const char *)ssid) == 0) + if(strcmp((const char *) essid, (const char *)ssid) == 0) { rt_kprintf("%s started\n", ssid); break; } } - if(timeout == 0) + if(timeout == 0) { - rt_kprintf("Start AP timeout\n"); + rt_kprintf("Start AP timeout\n"); return -1; } rt_thread_delay(1 * RT_TICK_PER_SECOND); @@ -169,7 +169,7 @@ static int rthw_wifi_disconnect(char *name) if (name == RT_NULL) return -1; - if (wext_get_ssid(name, (unsigned char *) essid) < 0) + if (wext_get_ssid(name, (unsigned char *) essid) < 0) { rt_kprintf("\nWIFI disconnected!\n"); return -1; @@ -189,7 +189,7 @@ static int rthw_wifi_disconnect(char *name) break; } - if(timeout == 0) + if(timeout == 0) { rt_kprintf("ERROR: Deassoc timeout!\n"); return -1; @@ -245,7 +245,7 @@ int rthw_wifi_ap_disconnect(void) int rthw_wifi_rssi_get(void) { - int rssi = 0; + int rssi = 0; wifi_get_rssi(&rssi); return rssi; } diff --git a/bsp/amebaz/drivers/wlan/drv_wlan.h b/bsp/amebaz/drivers/wlan/drv_wlan.h index 6062ef739c..ad300b18eb 100644 --- a/bsp/amebaz/drivers/wlan/drv_wlan.h +++ b/bsp/amebaz/drivers/wlan/drv_wlan.h @@ -11,14 +11,14 @@ #ifndef __DRV_WLAN_H__ #define __DRV_WLAN_H__ -typedef enum +typedef enum { - RTHW_MODE_NONE = 0, - RTHW_MODE_STA, - RTHW_MODE_AP, - RTHW_MODE_STA_AP, - RTHW_MODE_PROMISC, - RTHW_MODE_P2P + RTHW_MODE_NONE = 0, + RTHW_MODE_STA, + RTHW_MODE_AP, + RTHW_MODE_STA_AP, + RTHW_MODE_PROMISC, + RTHW_MODE_P2P }rthw_mode_t; #define SHARED_ENABLED 0x00008000 @@ -52,7 +52,7 @@ typedef enum { typedef enum { RTHW_WIFI_EVENT_CONNECT = 0, RTHW_WIFI_EVENT_DISCONNECT = 1, - RTHW_WIFI_EVENT_FOURWAY_HANDSHAKE_DONE = 2, + RTHW_WIFI_EVENT_FOURWAY_HANDSHAKE_DONE = 2, RTHW_WIFI_EVENT_SCAN_RESULT_REPORT = 3, RTHW_WIFI_EVENT_SCAN_DONE = 4, RTHW_WIFI_EVENT_RECONNECTION_FAIL = 5, diff --git a/bsp/apollo2/board/adc.c b/bsp/apollo2/board/adc.c index 64e3d63e2e..26b926a209 100644 --- a/bsp/apollo2/board/adc.c +++ b/bsp/apollo2/board/adc.c @@ -18,7 +18,7 @@ struct rt_messagequeue adcbat_mq; #define BATTERY_GPIO 35 /* Battery */ -#define BATTERY_ADC_PIN AM_HAL_PIN_35_ADCSE7 +#define BATTERY_ADC_PIN AM_HAL_PIN_35_ADCSE7 #define BATTERY_ADC_CHANNEL AM_HAL_ADC_SLOT_CHSEL_SE7 /* BATTERY ADC采集通道 */ #define BATTERY_ADC_CHANNELNUM 7 /* BATTERY ADC采集通道号 */ @@ -38,7 +38,7 @@ rt_uint8_t am_adc_data_get(rt_uint8_t channel, rt_int16_t *buff, rt_uint16_t siz if (channel == BATTERY_ADC_CHANNELNUM) { - /* wait adc message forever */ + /* wait adc message forever */ rt_mq_recv(&adcbat_mq, adc_bufftemp, 32, RT_WAITING_FOREVER); } diff --git a/bsp/apollo2/board/gpio.c b/bsp/apollo2/board/gpio.c index 9cd5ec4e75..edfaef1431 100644 --- a/bsp/apollo2/board/gpio.c +++ b/bsp/apollo2/board/gpio.c @@ -56,7 +56,7 @@ void am_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) else if (value == PIN_HIGH) { am_hal_gpio_out_bit_set(pin); - } + } } int am_pin_read(rt_device_t dev, rt_base_t pin) diff --git a/bsp/apollo2/board/gpio.h b/bsp/apollo2/board/gpio.h index ccf1575d7c..495fde6f6e 100644 --- a/bsp/apollo2/board/gpio.h +++ b/bsp/apollo2/board/gpio.h @@ -7,7 +7,7 @@ * Date Author Notes * 2017-09-16 Haley the first version */ - + #ifndef __GPIO_H #define __GPIO_H diff --git a/bsp/apollo2/board/i2c.c b/bsp/apollo2/board/i2c.c index d96b86ca0c..0a1311d7e6 100644 --- a/bsp/apollo2/board/i2c.c +++ b/bsp/apollo2/board/i2c.c @@ -119,7 +119,7 @@ static const struct rt_i2c_bus_device_ops am_i2c_ops = }; #ifdef RT_USING_I2C0 -static struct am_i2c_bus am_i2c_bus_0 = +static struct am_i2c_bus am_i2c_bus_0 = { {0}, AM_I2C0_IOM_INST @@ -127,7 +127,7 @@ static struct am_i2c_bus am_i2c_bus_0 = #endif #ifdef RT_USING_I2C1 -static struct am_i2c_bus am_i2c_bus_1 = +static struct am_i2c_bus am_i2c_bus_1 = { {1}, AM_I2C1_IOM_INST @@ -135,7 +135,7 @@ static struct am_i2c_bus am_i2c_bus_1 = #endif #ifdef RT_USING_I2C2 -static struct am_i2c_bus am_i2c_bus_2 = +static struct am_i2c_bus am_i2c_bus_2 = { {2}, AM_I2C2_IOM_INST @@ -143,7 +143,7 @@ static struct am_i2c_bus am_i2c_bus_2 = #endif #ifdef RT_USING_I2C3 -static struct am_i2c_bus am_i2c_bus_3 = +static struct am_i2c_bus am_i2c_bus_3 = { {3}, AM_I2C3_IOM_INST @@ -151,7 +151,7 @@ static struct am_i2c_bus am_i2c_bus_3 = #endif #ifdef RT_USING_I2C4 -static struct am_i2c_bus am_i2c_bus_4 = +static struct am_i2c_bus am_i2c_bus_4 = { {4}, AM_I2C4_IOM_INST diff --git a/bsp/apollo2/board/pdm.c b/bsp/apollo2/board/pdm.c index cfd45a8a2e..f1b719c6d1 100644 --- a/bsp/apollo2/board/pdm.c +++ b/bsp/apollo2/board/pdm.c @@ -52,7 +52,7 @@ rt_uint8_t am_pdm_data_get(rt_uint8_t *buff, rt_uint16_t size) { rt_uint8_t pdm_rbufftemp[340]; - /* wait pdm message forever */ + /* wait pdm message forever */ rt_mq_recv(&pdm_mq, pdm_rbufftemp, 340, RT_WAITING_FOREVER); /* copy the data */ diff --git a/bsp/apollo2/board/rtc.c b/bsp/apollo2/board/rtc.c index bb74409ef8..719671e31d 100644 --- a/bsp/apollo2/board/rtc.c +++ b/bsp/apollo2/board/rtc.c @@ -101,7 +101,7 @@ int rt_hw_rtc_init(void) /* Select LFRC for RTC clock source */ am_hal_rtc_osc_select(AM_HAL_RTC_OSC_LFRC); #endif - + #if RTC_CLK_SRC == XT /* Enable the XT for the RTC */ am_hal_clkgen_osc_start(AM_HAL_CLKGEN_OSC_XT); @@ -114,12 +114,12 @@ int rt_hw_rtc_init(void) am_hal_rtc_osc_enable(); /* register rtc device */ - rtc.type = RT_Device_Class_RTC; - rtc.init = RT_NULL; - rtc.open = rt_rtc_open; - rtc.close = RT_NULL; - rtc.read = rt_rtc_read; - rtc.write = RT_NULL; + rtc.type = RT_Device_Class_RTC; + rtc.init = RT_NULL; + rtc.open = rt_rtc_open; + rtc.close = RT_NULL; + rtc.read = rt_rtc_read; + rtc.write = RT_NULL; rtc.control = rt_rtc_control; /* no private */ diff --git a/bsp/apollo2/board/rtc.h b/bsp/apollo2/board/rtc.h index 5ed78e405e..a4a7fbd5e7 100644 --- a/bsp/apollo2/board/rtc.h +++ b/bsp/apollo2/board/rtc.h @@ -7,7 +7,7 @@ * Date Author Notes * 2017-09-14 Haley the first version */ - + #ifndef __RTC_H #define __RTC_H diff --git a/bsp/apollo2/board/smbus.c b/bsp/apollo2/board/smbus.c index ef47947e4a..7437b68ffa 100644 --- a/bsp/apollo2/board/smbus.c +++ b/bsp/apollo2/board/smbus.c @@ -28,8 +28,8 @@ #define mSDA_OUT() am_hal_gpio_pin_config(SMBUS_GPIO_SDA, AM_HAL_GPIO_OUTPUT) /* Set SDA as Output */ #define mSCL_OUT() am_hal_gpio_pin_config(SMBUS_GPIO_SCL, AM_HAL_GPIO_OUTPUT) /* Set SCL as Output */ -#define ACK 0 -#define NACK 1 +#define ACK 0 +#define NACK 1 /* SCL keep time */ static void keep_delay(void) @@ -46,7 +46,7 @@ static void few_delay(void) } static rt_uint8_t am_smbus_send_bit(rt_uint8_t send_bit) -{ +{ mSDA_OUT(); few_delay(); @@ -114,7 +114,7 @@ static void am_smbus_stop_bit(void) static rt_uint8_t am_smbus_tx_byte(rt_uint8_t tx_byte) { - int i; + int i; rt_uint8_t ack_bit; rt_uint8_t bit_out; @@ -162,7 +162,7 @@ rt_uint8_t am_smbus_tx_then_tx(rt_uint8_t SlaveAddress, rt_uint8_t command, rt_u int i; am_smbus_start_bit(); /* Start condition */ - + if(am_smbus_tx_byte(SlaveAddress)) /* Send SlaveAddress and write */ return 1; diff --git a/bsp/apollo2/board/spi.c b/bsp/apollo2/board/spi.c index d670dbbdc9..f59610975f 100644 --- a/bsp/apollo2/board/spi.c +++ b/bsp/apollo2/board/spi.c @@ -211,7 +211,7 @@ static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message* mes u32TransferSize = 64; am_hal_iom_spi_write(am_spi_bus->u32Module, am_spi_cs->chip_select, (uint32_t *)send_ptr, u32TransferSize, AM_HAL_IOM_RAW); - + } else { @@ -243,7 +243,7 @@ static const struct rt_spi_ops am_spi_ops = }; #ifdef RT_USING_SPI0 -static struct am_spi_bus am_spi_bus_0 = +static struct am_spi_bus am_spi_bus_0 = { {0}, AM_SPI0_IOM_INST diff --git a/bsp/apollo2/board/uart.c b/bsp/apollo2/board/uart.c index 516af5f80e..ec97599b80 100644 --- a/bsp/apollo2/board/uart.c +++ b/bsp/apollo2/board/uart.c @@ -150,11 +150,11 @@ static rt_err_t am_configure(struct rt_serial_device *serial, struct serial_conf else if (cfg->stop_bits == STOP_BITS_2) uart_cfg.bTwoStopBits = true; - if (cfg->parity == PARITY_NONE) + if (cfg->parity == PARITY_NONE) uart_cfg.ui32Parity = AM_HAL_UART_PARITY_NONE; - else if (cfg->parity == PARITY_ODD) + else if (cfg->parity == PARITY_ODD) uart_cfg.ui32Parity = AM_HAL_UART_PARITY_ODD; - else if (cfg->parity == PARITY_EVEN) + else if (cfg->parity == PARITY_EVEN) uart_cfg.ui32Parity = AM_HAL_UART_PARITY_EVEN; uart_cfg.ui32FlowCtrl = AM_HAL_UART_FLOW_CTRL_NONE; diff --git a/bsp/asm9260t/applications/application.c b/bsp/asm9260t/applications/application.c index 49c016521d..d60546ca76 100644 --- a/bsp/asm9260t/applications/application.c +++ b/bsp/asm9260t/applications/application.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version * 2015-04-27 ArdaFu Port bsp from at91sam9260 to asm9260t */ diff --git a/bsp/asm9260t/drivers/usart.c b/bsp/asm9260t/drivers/usart.c index ea5dd1a830..3a17f97b38 100644 --- a/bsp/asm9260t/drivers/usart.c +++ b/bsp/asm9260t/drivers/usart.c @@ -58,12 +58,12 @@ static rt_err_t asm_usart_configure(struct rt_serial_device *serial, RT_ASSERT(serial != RT_NULL); RT_ASSERT(cfg != RT_NULL); uart = (asm_uart_t *)serial->parent.user_data; - + Hw_UartDisable(uart->port); Hw_UartReset(uart->port); - - Hw_UartConfig(uart->port, cfg->baud_rate, cfg->data_bits, + + Hw_UartConfig(uart->port, cfg->baud_rate, cfg->data_bits, cfg->stop_bits, cfg->parity); Hw_UartEnable(uart->port); diff --git a/bsp/asm9260t/platform/gpio.c b/bsp/asm9260t/platform/gpio.c index fa5e1bee9e..8361a59589 100644 --- a/bsp/asm9260t/platform/gpio.c +++ b/bsp/asm9260t/platform/gpio.c @@ -7,7 +7,7 @@ * Date Author Notes * 2015-04-14 ArdaFu first version */ - + #include "asm9260t.h" #include "rtthread.h" diff --git a/bsp/asm9260t/platform/interrupt.h b/bsp/asm9260t/platform/interrupt.h index 6f42bd6b4b..fba92d1f2c 100644 --- a/bsp/asm9260t/platform/interrupt.h +++ b/bsp/asm9260t/platform/interrupt.h @@ -15,69 +15,69 @@ // IRQ Source -#define INT_ARM_COMMRX 0 -#define INT_ARM_COMMTX 1 -#define INT_RTC 2 -#define INT_GPIO0 3 -#define INT_GPIO1 4 -#define INT_GPIO2 5 -#define INT_GPIO3 6 -#define INT_GPIO4_IIS1 7 -#define INT_USB0 8 -#define INT_USB1 9 -#define INT_USB0_DMA 10 -#define INT_USB1_DMA 11 -#define INT_MAC 12 -#define INT_MAC_PMT 13 -#define INT_NAND 14 -#define INT_UART0 15 -#define INT_UART1 16 -#define INT_UART2 17 -#define INT_UART3 18 -#define INT_UART4 19 -#define INT_UART5 20 -#define INT_UART6 21 -#define INT_UART7 22 -#define INT_UART8 23 -#define INT_UART9 24 -#define INT_I2S0 25 -#define INT_I2C0 26 -#define INT_I2C1 27 -#define INT_CAMIF 28 -#define INT_TIMER0 29 -#define INT_TIMER1 30 -#define INT_TIMER2 31 -#define INT_TIMER3 32 -#define INT_ADC0 33 -#define INT_DAC0 34 -#define INT_USB0_RESUME_HOSTDISCONNECT 35 -#define INT_USB0_VBUSVALID 36 -#define INT_USB1_RESUME_HOSTDISCONNECT 37 -#define INT_USB1_VBUSVALID 38 -#define INT_DMA0_CH0 39 -#define INT_DMA0_CH1 40 -#define INT_DMA0_CH2 41 -#define INT_DMA0_CH3 42 -#define INT_DMA0_CH4 43 -#define INT_DMA0_CH5 44 -#define INT_DMA0_CH6 45 -#define INT_DMA0_CH7 46 -#define INT_DMA1_CH0 47 -#define INT_DMA1_CH1 48 -#define INT_DMA1_CH2 49 -#define INT_DMA1_CH3 50 -#define INT_DMA1_CH4 51 -#define INT_DMA1_CH5 52 -#define INT_DMA1_CH6 53 -#define INT_DMA1_CH7 54 -#define INT_WATCHDOG 55 -#define INT_CAN0 56 -#define INT_CAN1 57 -#define INT_QEI 58 -#define INT_MCPWM 59 -#define INT_SPI0 60 -#define INT_SPI1 61 -#define INT_QUADSPI0 62 +#define INT_ARM_COMMRX 0 +#define INT_ARM_COMMTX 1 +#define INT_RTC 2 +#define INT_GPIO0 3 +#define INT_GPIO1 4 +#define INT_GPIO2 5 +#define INT_GPIO3 6 +#define INT_GPIO4_IIS1 7 +#define INT_USB0 8 +#define INT_USB1 9 +#define INT_USB0_DMA 10 +#define INT_USB1_DMA 11 +#define INT_MAC 12 +#define INT_MAC_PMT 13 +#define INT_NAND 14 +#define INT_UART0 15 +#define INT_UART1 16 +#define INT_UART2 17 +#define INT_UART3 18 +#define INT_UART4 19 +#define INT_UART5 20 +#define INT_UART6 21 +#define INT_UART7 22 +#define INT_UART8 23 +#define INT_UART9 24 +#define INT_I2S0 25 +#define INT_I2C0 26 +#define INT_I2C1 27 +#define INT_CAMIF 28 +#define INT_TIMER0 29 +#define INT_TIMER1 30 +#define INT_TIMER2 31 +#define INT_TIMER3 32 +#define INT_ADC0 33 +#define INT_DAC0 34 +#define INT_USB0_RESUME_HOSTDISCONNECT 35 +#define INT_USB0_VBUSVALID 36 +#define INT_USB1_RESUME_HOSTDISCONNECT 37 +#define INT_USB1_VBUSVALID 38 +#define INT_DMA0_CH0 39 +#define INT_DMA0_CH1 40 +#define INT_DMA0_CH2 41 +#define INT_DMA0_CH3 42 +#define INT_DMA0_CH4 43 +#define INT_DMA0_CH5 44 +#define INT_DMA0_CH6 45 +#define INT_DMA0_CH7 46 +#define INT_DMA1_CH0 47 +#define INT_DMA1_CH1 48 +#define INT_DMA1_CH2 49 +#define INT_DMA1_CH3 50 +#define INT_DMA1_CH4 51 +#define INT_DMA1_CH5 52 +#define INT_DMA1_CH6 53 +#define INT_DMA1_CH7 54 +#define INT_WATCHDOG 55 +#define INT_CAN0 56 +#define INT_CAN1 57 +#define INT_QEI 58 +#define INT_MCPWM 59 +#define INT_SPI0 60 +#define INT_SPI1 61 +#define INT_QUADSPI0 62 #define INT_SSP0 63 #endif diff --git a/bsp/asm9260t/platform/rt_low_level_init.h b/bsp/asm9260t/platform/rt_low_level_init.h index 93a1fade4c..c79adf5284 100644 --- a/bsp/asm9260t/platform/rt_low_level_init.h +++ b/bsp/asm9260t/platform/rt_low_level_init.h @@ -9,7 +9,7 @@ */ #ifndef __RT_LOW_LEVEL_INIT_H__ #define __RT_LOW_LEVEL_INIT_H__ - + /*-------- Stack size of CPU modes -------------------------------------------*/ #define UND_STK_SIZE 512 #define SVC_STK_SIZE 4096 diff --git a/bsp/asm9260t/platform/system_clock.c b/bsp/asm9260t/platform/system_clock.c index 32dbf740d0..3a3340f48d 100644 --- a/bsp/asm9260t/platform/system_clock.c +++ b/bsp/asm9260t/platform/system_clock.c @@ -14,269 +14,269 @@ static rt_list_t clocks; struct clk { - char name[32]; - rt_uint32_t rate_hz; - struct clk *parent; - rt_list_t node; + char name[32]; + rt_uint32_t rate_hz; + struct clk *parent; + rt_list_t node; }; static struct clk clk32k = { - "clk32k", - AT91_SLOW_CLOCK, - RT_NULL, - {RT_NULL, RT_NULL}, + "clk32k", + AT91_SLOW_CLOCK, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk main_clk = { - "main", - 0, - RT_NULL, - {RT_NULL, RT_NULL}, + "main", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk plla = { - "plla", - 0, - RT_NULL, - {RT_NULL, RT_NULL}, + "plla", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk mck = { - "mck", - 0, - RT_NULL, - {RT_NULL, RT_NULL}, + "mck", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk uhpck = { - "uhpck", - 0, - RT_NULL, - {RT_NULL, RT_NULL}, + "uhpck", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk pllb = { - "pllb", - 0, - &main_clk, - {RT_NULL, RT_NULL}, + "pllb", + 0, + &main_clk, + {RT_NULL, RT_NULL}, }; static struct clk udpck = { - "udpck", - 0, - &pllb, - {RT_NULL, RT_NULL}, + "udpck", + 0, + &pllb, + {RT_NULL, RT_NULL}, }; static struct clk *const standard_pmc_clocks[] = { - // four primary clocks - &clk32k, - &main_clk, - &plla, + // four primary clocks + &clk32k, + &main_clk, + &plla, - // MCK - &mck + // MCK + &mck }; // clocks cannot be de-registered no refcounting necessary struct clk *clk_get(const char *id) { - struct clk *clk; - rt_list_t *list; - - for (list = (&clocks)->next; list != &clocks; list = list->next) - { - clk = (struct clk *)rt_list_entry(list, struct clk, node); - if (rt_strcmp(id, clk->name) == 0) - return clk; - } - - return RT_NULL; + struct clk *clk; + rt_list_t *list; + + for (list = (&clocks)->next; list != &clocks; list = list->next) + { + clk = (struct clk *)rt_list_entry(list, struct clk, node); + if (rt_strcmp(id, clk->name) == 0) + return clk; + } + + return RT_NULL; } rt_uint32_t clk_get_rate(struct clk *clk) { - rt_uint32_t rate; - - for (;;) { - rate = clk->rate_hz; - if (rate || !clk->parent) - break; - clk = clk->parent; - } - return rate; + rt_uint32_t rate; + + for (;;) { + rate = clk->rate_hz; + if (rate || !clk->parent) + break; + clk = clk->parent; + } + return rate; } static rt_uint32_t at91_pll_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg) { - unsigned mul, div; + unsigned mul, div; - div = reg & 0xff; - mul = (reg >> 16) & 0x7ff; - if (div && mul) { - freq /= div; - freq *= mul + 1; - } else - freq = 0; + div = reg & 0xff; + mul = (reg >> 16) & 0x7ff; + if (div && mul) { + freq /= div; + freq *= mul + 1; + } else + freq = 0; - return freq; + return freq; } static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq) { - unsigned i, div = 0, mul = 0, diff = 1 << 30; - unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; - - //PLL output max 240 MHz (or 180 MHz per errata) - if (out_freq > 240000000) - goto fail; - - for (i = 1; i < 256; i++) { - int diff1; - unsigned input, mul1; - - // - // PLL input between 1MHz and 32MHz per spec, but lower - // frequences seem necessary in some cases so allow 100K. - // Warning: some newer products need 2MHz min. - // - input = main_freq / i; - if (input < 100000) - continue; - if (input > 32000000) - continue; - - mul1 = out_freq / input; - if (mul1 > 2048) - continue; - if (mul1 < 2) - goto fail; - - diff1 = out_freq - input * mul1; - if (diff1 < 0) - diff1 = -diff1; - if (diff > diff1) { - diff = diff1; - div = i; - mul = mul1; - if (diff == 0) - break; - } - } - if (i == 256 && diff > (out_freq >> 5)) - goto fail; - return ret | ((mul - 1) << 16) | div; + unsigned i, div = 0, mul = 0, diff = 1 << 30; + unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; + + //PLL output max 240 MHz (or 180 MHz per errata) + if (out_freq > 240000000) + goto fail; + + for (i = 1; i < 256; i++) { + int diff1; + unsigned input, mul1; + + // + // PLL input between 1MHz and 32MHz per spec, but lower + // frequences seem necessary in some cases so allow 100K. + // Warning: some newer products need 2MHz min. + // + input = main_freq / i; + if (input < 100000) + continue; + if (input > 32000000) + continue; + + mul1 = out_freq / input; + if (mul1 > 2048) + continue; + if (mul1 < 2) + goto fail; + + diff1 = out_freq - input * mul1; + if (diff1 < 0) + diff1 = -diff1; + if (diff > diff1) { + diff = diff1; + div = i; + mul = mul1; + if (diff == 0) + break; + } + } + if (i == 256 && diff > (out_freq >> 5)) + goto fail; + return ret | ((mul - 1) << 16) | div; fail: - return 0; + return 0; } static rt_uint32_t at91_usb_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg) { - if (pll == &pllb && (reg & AT91_PMC_USB96M)) - return freq / 2; - else - return freq; + if (pll == &pllb && (reg & AT91_PMC_USB96M)) + return freq / 2; + else + return freq; } // PLLB generated USB full speed clock init static void at91_pllb_usbfs_clock_init(rt_uint32_t main_clock) { - rt_uint32_t at91_pllb_usb_init; - // - // USB clock init: choose 48 MHz PLLB value, - // disable 48MHz clock during usb peripheral suspend. - // - // REVISIT: assumes MCK doesn't derive from PLLB! - // - uhpck.parent = &pllb; - - at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; - pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); - - at91_sys_write(AT91_CKGR_PLLBR, 0); - - udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); - uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); + rt_uint32_t at91_pllb_usb_init; + // + // USB clock init: choose 48 MHz PLLB value, + // disable 48MHz clock during usb peripheral suspend. + // + // REVISIT: assumes MCK doesn't derive from PLLB! + // + uhpck.parent = &pllb; + + at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; + pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); + + at91_sys_write(AT91_CKGR_PLLBR, 0); + + udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); + uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); } static struct clk *at91_css_to_clk(unsigned long css) { - switch (css) { - case AT91_PMC_CSS_SLOW: - return &clk32k; - case AT91_PMC_CSS_MAIN: - return &main_clk; - case AT91_PMC_CSS_PLLA: - return &plla; - case AT91_PMC_CSS_PLLB: - return &pllb; - } - - return RT_NULL; + switch (css) { + case AT91_PMC_CSS_SLOW: + return &clk32k; + case AT91_PMC_CSS_MAIN: + return &main_clk; + case AT91_PMC_CSS_PLLA: + return &plla; + case AT91_PMC_CSS_PLLB: + return &pllb; + } + + return RT_NULL; } #define false 0 #define true 1 int at91_clock_init(rt_uint32_t main_clock) { - unsigned tmp, freq, mckr; - int i; - int pll_overclock = false; - - // - // When the bootloader initialized the main oscillator correctly, - // there's no problem using the cycle counter. But if it didn't, - // or when using oscillator bypass mode, we must be told the speed - // of the main clock. - // - if (!main_clock) { - do { - tmp = at91_sys_read(AT91_CKGR_MCFR); - } while (!(tmp & AT91_PMC_MAINRDY)); - main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16); - } - main_clk.rate_hz = main_clock; - - // report if PLLA is more than mildly overclocked - plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); - if (plla.rate_hz > 209000000) - pll_overclock = true; - if (pll_overclock) - ;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); - - at91_pllb_usbfs_clock_init(main_clock); - - // - // MCK and CPU derive from one of those primary clocks. - // For now, assume this parentage won't change. - // - mckr = at91_sys_read(AT91_PMC_MCKR); - mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); - freq = mck.parent->rate_hz; - freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); // prescale - - mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); // mdiv - - // Register the PMC's standard clocks - rt_list_init(&clocks); - for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) - rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node); - - rt_list_insert_after(&clocks, &pllb.node); - rt_list_insert_after(&clocks, &uhpck.node); - rt_list_insert_after(&clocks, &udpck.node); - - // MCK and CPU clock are "always on" - //clk_enable(&mck); - - //rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n", - // freq / 1000000, (unsigned) mck.rate_hz / 1000000, - // (unsigned) main_clock / 1000000, - // ((unsigned) main_clock % 1000000) / 1000); //cause blocked - - return 0; + unsigned tmp, freq, mckr; + int i; + int pll_overclock = false; + + // + // When the bootloader initialized the main oscillator correctly, + // there's no problem using the cycle counter. But if it didn't, + // or when using oscillator bypass mode, we must be told the speed + // of the main clock. + // + if (!main_clock) { + do { + tmp = at91_sys_read(AT91_CKGR_MCFR); + } while (!(tmp & AT91_PMC_MAINRDY)); + main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16); + } + main_clk.rate_hz = main_clock; + + // report if PLLA is more than mildly overclocked + plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); + if (plla.rate_hz > 209000000) + pll_overclock = true; + if (pll_overclock) + ;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); + + at91_pllb_usbfs_clock_init(main_clock); + + // + // MCK and CPU derive from one of those primary clocks. + // For now, assume this parentage won't change. + // + mckr = at91_sys_read(AT91_PMC_MCKR); + mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); + freq = mck.parent->rate_hz; + freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); // prescale + + mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); // mdiv + + // Register the PMC's standard clocks + rt_list_init(&clocks); + for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) + rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node); + + rt_list_insert_after(&clocks, &pllb.node); + rt_list_insert_after(&clocks, &uhpck.node); + rt_list_insert_after(&clocks, &udpck.node); + + // MCK and CPU clock are "always on" + //clk_enable(&mck); + + //rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n", + // freq / 1000000, (unsigned) mck.rate_hz / 1000000, + // (unsigned) main_clock / 1000000, + // ((unsigned) main_clock % 1000000) / 1000); //cause blocked + + return 0; } */ @@ -284,6 +284,6 @@ int at91_clock_init(rt_uint32_t main_clock) void rt_hw_clock_init(void) { - //at91_clock_init(18432000); + //at91_clock_init(18432000); } diff --git a/bsp/asm9260t/platform/uart.c b/bsp/asm9260t/platform/uart.c index 9dc2cca560..08613200db 100644 --- a/bsp/asm9260t/platform/uart.c +++ b/bsp/asm9260t/platform/uart.c @@ -7,7 +7,7 @@ * Date Author Notes * 2015-04-14 ArdaFu first version */ - + #include "asm9260t.h" #include "rtthread.h" #include "uart.h" diff --git a/bsp/asm9260t/platform/uart.h b/bsp/asm9260t/platform/uart.h index f6e0f30fc6..b938483882 100644 --- a/bsp/asm9260t/platform/uart.h +++ b/bsp/asm9260t/platform/uart.h @@ -36,16 +36,16 @@ typedef struct volatile rt_uint32_t ISO7816STATUS[4]; } HW_USART_TypeDef; -#define USART0 ((HW_USART_TypeDef *)UART0_BASE) -#define USART1 ((HW_USART_TypeDef *)UART1_BASE) -#define USART2 ((HW_USART_TypeDef *)UART2_BASE) -#define USART3 ((HW_USART_TypeDef *)UART3_BASE) -#define USART4 ((HW_USART_TypeDef *)UART4_BASE) -#define USART5 ((HW_USART_TypeDef *)UART5_BASE) -#define USART6 ((HW_USART_TypeDef *)UART6_BASE) -#define USART7 ((HW_USART_TypeDef *)UART7_BASE) -#define USART8 ((HW_USART_TypeDef *)UART8_BASE) -#define USART9 ((HW_USART_TypeDef *)UART9_BASE) +#define USART0 ((HW_USART_TypeDef *)UART0_BASE) +#define USART1 ((HW_USART_TypeDef *)UART1_BASE) +#define USART2 ((HW_USART_TypeDef *)UART2_BASE) +#define USART3 ((HW_USART_TypeDef *)UART3_BASE) +#define USART4 ((HW_USART_TypeDef *)UART4_BASE) +#define USART5 ((HW_USART_TypeDef *)UART5_BASE) +#define USART6 ((HW_USART_TypeDef *)UART6_BASE) +#define USART7 ((HW_USART_TypeDef *)UART7_BASE) +#define USART8 ((HW_USART_TypeDef *)UART8_BASE) +#define USART9 ((HW_USART_TypeDef *)UART9_BASE) #define ASM_UART_INTR_RXIS (1UL << 4) @@ -91,7 +91,7 @@ typedef struct extern void Hw_UartDisable(HW_USART_TypeDef* uartBase); extern void Hw_UartEnable(HW_USART_TypeDef* uartBase); extern void Hw_UartReset(HW_USART_TypeDef* uartBase); -extern void Hw_UartConfig(HW_USART_TypeDef* uartBase, int baudRate, +extern void Hw_UartConfig(HW_USART_TypeDef* uartBase, int baudRate, int dataBits, int stopBits, int parity); extern void Hw_UartInit(int index); #endif diff --git a/bsp/at91sam9260/applications/application.c b/bsp/at91sam9260/applications/application.c index be110b5bd2..f1a377e1e9 100644 --- a/bsp/at91sam9260/applications/application.c +++ b/bsp/at91sam9260/applications/application.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ /** @@ -34,106 +34,106 @@ static int rt_led_app_init(void); int main(void) { - int timeout = 0; + int timeout = 0; /* Filesystem Initialization */ #ifdef RT_USING_DFS - { + { #if defined(RT_USING_DFS_ROMFS) - if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0) - { - rt_kprintf("ROM File System initialized!\n"); - } - else - rt_kprintf("ROM File System initialzation failed!\n"); + if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0) + { + rt_kprintf("ROM File System initialized!\n"); + } + else + rt_kprintf("ROM File System initialzation failed!\n"); #endif #if defined(RT_USING_DFS_UFFS) - { - /* mount flash device as flash directory */ - if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0) - rt_kprintf("UFFS File System initialized!\n"); - else - rt_kprintf("UFFS File System initialzation failed!\n"); - } + { + /* mount flash device as flash directory */ + if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0) + rt_kprintf("UFFS File System initialized!\n"); + else + rt_kprintf("UFFS File System initialzation failed!\n"); + } #endif #ifdef RT_USING_SDIO - timeout = 0; - while ((rt_device_find("sd0") == RT_NULL) && (timeout++ < RT_TICK_PER_SECOND*2)) - { - rt_thread_delay(1); - } - - if (timeout < RT_TICK_PER_SECOND*2) - { - /* mount sd card fat partition 1 as root directory */ - if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) - { - rt_kprintf("File System initialized!\n"); - } - else - rt_kprintf("File System initialzation failed!%d\n", rt_get_errno()); - } - else - { - rt_kprintf("No SD card found.\n"); - } + timeout = 0; + while ((rt_device_find("sd0") == RT_NULL) && (timeout++ < RT_TICK_PER_SECOND*2)) + { + rt_thread_delay(1); + } + + if (timeout < RT_TICK_PER_SECOND*2) + { + /* mount sd card fat partition 1 as root directory */ + if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) + { + rt_kprintf("File System initialized!\n"); + } + else + rt_kprintf("File System initialzation failed!%d\n", rt_get_errno()); + } + else + { + rt_kprintf("No SD card found.\n"); + } #endif - } + } #endif - + #ifdef RT_USING_LED - rt_led_app_init(); + rt_led_app_init(); #endif } #ifdef RT_USING_LED void rt_led_thread_entry(void* parameter) { - rt_uint8_t cnt = 0; - led_init(); - while(1) - { - /* light on leds for one second */ - rt_thread_delay(40); - cnt++; - if (cnt&0x01) - led_on(1); - else - led_off(1); - if (cnt&0x02) - led_on(2); - else - led_off(2); - if (cnt&0x04) - led_on(3); - else - led_off(3); - } + rt_uint8_t cnt = 0; + led_init(); + while(1) + { + /* light on leds for one second */ + rt_thread_delay(40); + cnt++; + if (cnt&0x01) + led_on(1); + else + led_off(1); + if (cnt&0x02) + led_on(2); + else + led_off(2); + if (cnt&0x04) + led_on(3); + else + led_off(3); + } } #endif static int rt_led_app_init(void) { #ifdef RT_USING_LED - rt_thread_t led_thread; + rt_thread_t led_thread; #if (RT_THREAD_PRIORITY_MAX == 32) - led_thread = rt_thread_create("led", - rt_led_thread_entry, RT_NULL, - 512, 20, 20); + led_thread = rt_thread_create("led", + rt_led_thread_entry, RT_NULL, + 512, 20, 20); #else - led_thread = rt_thread_create("led", - rt_led_thread_entry, RT_NULL, - 512, 200, 20); + led_thread = rt_thread_create("led", + rt_led_thread_entry, RT_NULL, + 512, 200, 20); #endif - if(led_thread != RT_NULL) - rt_thread_startup(led_thread); + if(led_thread != RT_NULL) + rt_thread_startup(led_thread); #endif - return 0; + return 0; } /* NFSv3 Initialization */ @@ -141,14 +141,14 @@ static int rt_led_app_init(void) #include void nfs_start(void) { - nfs_init(); - - if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0) - { - rt_kprintf("NFSv3 File System initialized!\n"); - } - else - rt_kprintf("NFSv3 File System initialzation failed!\n"); + nfs_init(); + + if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0) + { + rt_kprintf("NFSv3 File System initialized!\n"); + } + else + rt_kprintf("NFSv3 File System initialzation failed!\n"); } #include "finsh.h" diff --git a/bsp/at91sam9260/drivers/at91_i2c_gpio.c b/bsp/at91sam9260/drivers/at91_i2c_gpio.c index fb4c0ccfaf..d863ffed88 100644 --- a/bsp/at91sam9260/drivers/at91_i2c_gpio.c +++ b/bsp/at91sam9260/drivers/at91_i2c_gpio.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2012-04-25 weety first version + * Date Author Notes + * 2012-04-25 weety first version */ #include @@ -15,101 +15,101 @@ static void at91_i2c_gpio_init() { - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOA); //enable PIOA clock - at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 23)); - at91_sys_write(AT91_PIOA + PIO_PER, (1 << 23)); - at91_sys_write(AT91_PIOA + PIO_MDER, (1 << 23)); - at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 24)); - at91_sys_write(AT91_PIOA + PIO_PER, (1 << 24)); - at91_sys_write(AT91_PIOA + PIO_MDER, (1 << 24)); - - at91_sys_write(AT91_PIOA + PIO_OER, (1 << 23)); - at91_sys_write(AT91_PIOA + PIO_OER, (1 << 24)); - - at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 23)); - at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 24)); + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOA); //enable PIOA clock + at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 23)); + at91_sys_write(AT91_PIOA + PIO_PER, (1 << 23)); + at91_sys_write(AT91_PIOA + PIO_MDER, (1 << 23)); + at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 24)); + at91_sys_write(AT91_PIOA + PIO_PER, (1 << 24)); + at91_sys_write(AT91_PIOA + PIO_MDER, (1 << 24)); + + at91_sys_write(AT91_PIOA + PIO_OER, (1 << 23)); + at91_sys_write(AT91_PIOA + PIO_OER, (1 << 24)); + + at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 23)); + at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 24)); } static void at91_set_sda(void *data, rt_int32_t state) { - if (state) - { - at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 23)); - } - else - { - at91_sys_write(AT91_PIOA + PIO_CODR, (1 << 23)); - } + if (state) + { + at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 23)); + } + else + { + at91_sys_write(AT91_PIOA + PIO_CODR, (1 << 23)); + } } static void at91_set_scl(void *data, rt_int32_t state) { - if (state) - { - at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 24)); - } - else - { - at91_sys_write(AT91_PIOA + PIO_CODR, (1 << 24)); - } + if (state) + { + at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 24)); + } + else + { + at91_sys_write(AT91_PIOA + PIO_CODR, (1 << 24)); + } } static rt_int32_t at91_get_sda(void *data) { - return at91_sys_read(AT91_PIOA + PIO_PDSR) & (1 << 23); + return at91_sys_read(AT91_PIOA + PIO_PDSR) & (1 << 23); } static rt_int32_t at91_get_scl(void *data) { - return at91_sys_read(AT91_PIOA + PIO_PDSR) & (1 << 24); + return at91_sys_read(AT91_PIOA + PIO_PDSR) & (1 << 24); } static void at91_udelay (rt_uint32_t us) { - rt_int32_t i; - for (; us > 0; us--) - { - i = 50000; - while(i > 0) - { - i--; - } - } + rt_int32_t i; + for (; us > 0; us--) + { + i = 50000; + while(i > 0) + { + i--; + } + } } static const struct rt_i2c_bit_ops bit_ops = { - RT_NULL, - at91_set_sda, - at91_set_scl, - at91_get_sda, - at91_get_scl, - - at91_udelay, - - 5, - 100 + RT_NULL, + at91_set_sda, + at91_set_scl, + at91_get_sda, + at91_get_scl, + + at91_udelay, + + 5, + 100 }; int at91_i2c_init(void) { - struct rt_i2c_bus_device *bus; + struct rt_i2c_bus_device *bus; + + bus = rt_malloc(sizeof(struct rt_i2c_bus_device)); + if (bus == RT_NULL) + { + rt_kprintf("rt_malloc failed\n"); + return -RT_ENOMEM; + } - bus = rt_malloc(sizeof(struct rt_i2c_bus_device)); - if (bus == RT_NULL) - { - rt_kprintf("rt_malloc failed\n"); - return -RT_ENOMEM; - } - - rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device)); + rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device)); - bus->priv = (void *)&bit_ops; + bus->priv = (void *)&bit_ops; - at91_i2c_gpio_init(); + at91_i2c_gpio_init(); - rt_i2c_bit_add_bus(bus, "i2c0"); + rt_i2c_bit_add_bus(bus, "i2c0"); - return 0; + return 0; } INIT_DEVICE_EXPORT(at91_i2c_init); diff --git a/bsp/at91sam9260/drivers/at91_mci.c b/bsp/at91sam9260/drivers/at91_mci.c index dfa5d5172e..92f7abdfec 100644 --- a/bsp/at91sam9260/drivers/at91_mci.c +++ b/bsp/at91sam9260/drivers/at91_mci.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-07-25 weety first version + * Date Author Notes + * 2011-07-25 weety first version */ #include @@ -23,32 +23,32 @@ #define mci_dbg(fmt, ...) #endif -#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31)) +#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31)) extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size); extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); -#define AT91_MCI_ERRORS (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE \ - | AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE \ - | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE) +#define AT91_MCI_ERRORS (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE \ + | AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE \ + | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE) -#define at91_mci_read(reg) readl(AT91SAM9260_BASE_MCI + (reg)) -#define at91_mci_write(reg, val) writel((val), AT91SAM9260_BASE_MCI + (reg)) +#define at91_mci_read(reg) readl(AT91SAM9260_BASE_MCI + (reg)) +#define at91_mci_write(reg, val) writel((val), AT91SAM9260_BASE_MCI + (reg)) -#define REQ_ST_INIT (1U << 0) -#define REQ_ST_CMD (1U << 1) -#define REQ_ST_STOP (1U << 2) +#define REQ_ST_INIT (1U << 0) +#define REQ_ST_CMD (1U << 1) +#define REQ_ST_STOP (1U << 2) struct at91_mci { - struct rt_mmcsd_host *host; - struct rt_mmcsd_req *req; - struct rt_mmcsd_cmd *cmd; - struct rt_timer timer; - //struct rt_semaphore sem_ack; - rt_uint32_t *buf; - rt_uint32_t current_status; + struct rt_mmcsd_host *host; + struct rt_mmcsd_req *req; + struct rt_mmcsd_cmd *cmd; + struct rt_timer timer; + //struct rt_semaphore sem_ack; + rt_uint32_t *buf; + rt_uint32_t current_status; }; /* @@ -56,36 +56,36 @@ struct at91_mci { */ static void at91_reset_host() { - rt_uint32_t mr; - rt_uint32_t sdcr; - rt_uint32_t dtor; - rt_uint32_t imr; - rt_uint32_t level; + rt_uint32_t mr; + rt_uint32_t sdcr; + rt_uint32_t dtor; + rt_uint32_t imr; + rt_uint32_t level; - level = rt_hw_interrupt_disable(); + level = rt_hw_interrupt_disable(); - imr = at91_mci_read(AT91_MCI_IMR); + imr = at91_mci_read(AT91_MCI_IMR); - at91_mci_write(AT91_MCI_IDR, 0xffffffff); + at91_mci_write(AT91_MCI_IDR, 0xffffffff); - /* save current state */ - mr = at91_mci_read(AT91_MCI_MR) & 0x7fff; - sdcr = at91_mci_read(AT91_MCI_SDCR); - dtor = at91_mci_read(AT91_MCI_DTOR); + /* save current state */ + mr = at91_mci_read(AT91_MCI_MR) & 0x7fff; + sdcr = at91_mci_read(AT91_MCI_SDCR); + dtor = at91_mci_read(AT91_MCI_DTOR); - /* reset the controller */ - at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST); + /* reset the controller */ + at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST); - /* restore state */ - at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN); - at91_mci_write(AT91_MCI_MR, mr); - at91_mci_write(AT91_MCI_SDCR, sdcr); - at91_mci_write(AT91_MCI_DTOR, dtor); - at91_mci_write(AT91_MCI_IER, imr); + /* restore state */ + at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN); + at91_mci_write(AT91_MCI_MR, mr); + at91_mci_write(AT91_MCI_SDCR, sdcr); + at91_mci_write(AT91_MCI_DTOR, dtor); + at91_mci_write(AT91_MCI_IER, imr); - /* make sure sdio interrupts will fire */ - at91_mci_read(AT91_MCI_SR); - rt_hw_interrupt_enable(level); + /* make sure sdio interrupts will fire */ + at91_mci_read(AT91_MCI_SR); + rt_hw_interrupt_enable(level); } @@ -95,19 +95,19 @@ static void at91_reset_host() */ static void at91_mci_enable() { - rt_uint32_t mr; + rt_uint32_t mr; - at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN); - at91_mci_write(AT91_MCI_IDR, 0xffffffff); - at91_mci_write(AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC); - mr = AT91_MCI_PDCMODE | 0x34a; + at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN); + at91_mci_write(AT91_MCI_IDR, 0xffffffff); + at91_mci_write(AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC); + mr = AT91_MCI_PDCMODE | 0x34a; - mr |= AT91_MCI_RDPROOF | AT91_MCI_WRPROOF; + mr |= AT91_MCI_RDPROOF | AT91_MCI_WRPROOF; - at91_mci_write(AT91_MCI_MR, mr); + at91_mci_write(AT91_MCI_MR, mr); - /* use Slot A or B (only one at same time) */ - at91_mci_write(AT91_MCI_SDCR, 1); /* use slot b */ + /* use Slot A or B (only one at same time) */ + at91_mci_write(AT91_MCI_SDCR, 1); /* use slot b */ } /* @@ -115,39 +115,39 @@ static void at91_mci_enable() */ static void at91_mci_disable() { - at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST); + at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST); } static void at91_timeout_timer(void *data) { - struct at91_mci *mci; - - mci = (struct at91_mci *)data; - - if (mci->req) - { - rt_kprintf("Timeout waiting end of packet\n"); - - if (mci->current_status == REQ_ST_CMD) - { - if (mci->req->cmd && mci->req->data) - { - mci->req->data->err = -RT_ETIMEOUT; - } - else - { - if (mci->req->cmd) - mci->req->cmd->err = -RT_ETIMEOUT; - } - } - else if (mci->current_status == REQ_ST_STOP) - { - mci->req->stop->err = -RT_ETIMEOUT; - } - - at91_reset_host(); - mmcsd_req_complete(mci->host); - } + struct at91_mci *mci; + + mci = (struct at91_mci *)data; + + if (mci->req) + { + rt_kprintf("Timeout waiting end of packet\n"); + + if (mci->current_status == REQ_ST_CMD) + { + if (mci->req->cmd && mci->req->data) + { + mci->req->data->err = -RT_ETIMEOUT; + } + else + { + if (mci->req->cmd) + mci->req->cmd->err = -RT_ETIMEOUT; + } + } + else if (mci->current_status == REQ_ST_STOP) + { + mci->req->stop->err = -RT_ETIMEOUT; + } + + at91_reset_host(); + mmcsd_req_complete(mci->host); + } } /* @@ -155,62 +155,62 @@ static void at91_timeout_timer(void *data) */ static void at91_mci_init_dma_read(struct at91_mci *mci) { - rt_uint8_t i; - struct rt_mmcsd_cmd *cmd; - struct rt_mmcsd_data *data; - rt_uint32_t length; - - mci_dbg("pre dma read\n"); - - cmd = mci->cmd; - if (!cmd) - { - mci_dbg("no command\n"); - return; - } - - data = cmd->data; - if (!data) - { - mci_dbg("no data\n"); - return; - } - - for (i = 0; i < 1; i++) - { - /* Check to see if this needs filling */ - if (i == 0) - { - if (at91_mci_read(AT91_PDC_RCR) != 0) - { - mci_dbg("Transfer active in current\n"); - continue; - } - } - else { - if (at91_mci_read(AT91_PDC_RNCR) != 0) - { - mci_dbg("Transfer active in next\n"); - continue; - } - } - - length = data->blksize * data->blks; - mci_dbg("dma address = %08X, length = %d\n", data->buf, length); - - if (i == 0) - { - at91_mci_write(AT91_PDC_RPR, (rt_uint32_t)(data->buf)); - at91_mci_write(AT91_PDC_RCR, (data->blksize & 0x3) ? length : length / 4); - } - else - { - at91_mci_write(AT91_PDC_RNPR, (rt_uint32_t)(data->buf)); - at91_mci_write(AT91_PDC_RNCR, (data->blksize & 0x3) ? length : length / 4); - } - } - - mci_dbg("pre dma read done\n"); + rt_uint8_t i; + struct rt_mmcsd_cmd *cmd; + struct rt_mmcsd_data *data; + rt_uint32_t length; + + mci_dbg("pre dma read\n"); + + cmd = mci->cmd; + if (!cmd) + { + mci_dbg("no command\n"); + return; + } + + data = cmd->data; + if (!data) + { + mci_dbg("no data\n"); + return; + } + + for (i = 0; i < 1; i++) + { + /* Check to see if this needs filling */ + if (i == 0) + { + if (at91_mci_read(AT91_PDC_RCR) != 0) + { + mci_dbg("Transfer active in current\n"); + continue; + } + } + else { + if (at91_mci_read(AT91_PDC_RNCR) != 0) + { + mci_dbg("Transfer active in next\n"); + continue; + } + } + + length = data->blksize * data->blks; + mci_dbg("dma address = %08X, length = %d\n", data->buf, length); + + if (i == 0) + { + at91_mci_write(AT91_PDC_RPR, (rt_uint32_t)(data->buf)); + at91_mci_write(AT91_PDC_RCR, (data->blksize & 0x3) ? length : length / 4); + } + else + { + at91_mci_write(AT91_PDC_RNPR, (rt_uint32_t)(data->buf)); + at91_mci_write(AT91_PDC_RNCR, (data->blksize & 0x3) ? length : length / 4); + } + } + + mci_dbg("pre dma read done\n"); } /* @@ -218,185 +218,185 @@ static void at91_mci_init_dma_read(struct at91_mci *mci) */ static void at91_mci_send_command(struct at91_mci *mci, struct rt_mmcsd_cmd *cmd) { - rt_uint32_t cmdr, mr; - rt_uint32_t block_length; - struct rt_mmcsd_data *data = cmd->data; - struct rt_mmcsd_host *host = mci->host; - - rt_uint32_t blocks; - rt_uint32_t ier = 0; - rt_uint32_t length; - - mci->cmd = cmd; - - /* Needed for leaving busy state before CMD1 */ - if ((at91_mci_read(AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->cmd_code == 1)) - { - mci_dbg("Clearing timeout\n"); - at91_mci_write(AT91_MCI_ARGR, 0); - at91_mci_write(AT91_MCI_CMDR, AT91_MCI_OPDCMD); - while (!(at91_mci_read(AT91_MCI_SR) & AT91_MCI_CMDRDY)) - { - /* spin */ - mci_dbg("Clearing: SR = %08X\n", at91_mci_read(AT91_MCI_SR)); - } - } - - cmdr = cmd->cmd_code; - - if (resp_type(cmd) == RESP_NONE) - cmdr |= AT91_MCI_RSPTYP_NONE; - else - { - /* if a response is expected then allow maximum response latancy */ - cmdr |= AT91_MCI_MAXLAT; - /* set 136 bit response for R2, 48 bit response otherwise */ - if (resp_type(cmd) == RESP_R2) - cmdr |= AT91_MCI_RSPTYP_136; - else - cmdr |= AT91_MCI_RSPTYP_48; - } - - if (data) - { - - block_length = data->blksize; - blocks = data->blks; - - /* always set data start - also set direction flag for read */ - if (data->flags & DATA_DIR_READ) - cmdr |= (AT91_MCI_TRDIR | AT91_MCI_TRCMD_START); - else if (data->flags & DATA_DIR_WRITE) - cmdr |= AT91_MCI_TRCMD_START; - - if (data->flags & DATA_STREAM) - cmdr |= AT91_MCI_TRTYP_STREAM; - if (data->blks > 1) - cmdr |= AT91_MCI_TRTYP_MULTIPLE; - } - else - { - block_length = 0; - blocks = 0; - } - - /*if (cmd->cmd_code == GO_IDLE_STATE) - { - cmdr |= AT91_MCI_SPCMD_INIT; - }*/ - - if (cmd->cmd_code == STOP_TRANSMISSION) - cmdr |= AT91_MCI_TRCMD_STOP; - - if (host->io_cfg.bus_mode == MMCSD_BUSMODE_OPENDRAIN) - cmdr |= AT91_MCI_OPDCMD; - - /* - * Set the arguments and send the command - */ - mci_dbg("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n", - cmd->cmd_code, cmdr, cmd->arg, blocks, block_length, at91_mci_read(AT91_MCI_MR)); - - if (!data) - { - at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTDIS | AT91_PDC_RXTDIS); - at91_mci_write(AT91_PDC_RPR, 0); - at91_mci_write(AT91_PDC_RCR, 0); - at91_mci_write(AT91_PDC_RNPR, 0); - at91_mci_write(AT91_PDC_RNCR, 0); - at91_mci_write(AT91_PDC_TPR, 0); - at91_mci_write(AT91_PDC_TCR, 0); - at91_mci_write(AT91_PDC_TNPR, 0); - at91_mci_write(AT91_PDC_TNCR, 0); - ier = AT91_MCI_CMDRDY; - } - else - { - /* zero block length and PDC mode */ - mr = at91_mci_read(AT91_MCI_MR) & 0x5fff; - mr |= (data->blksize & 0x3) ? AT91_MCI_PDCFBYTE : 0; - mr |= (block_length << 16); - mr |= AT91_MCI_PDCMODE; - at91_mci_write(AT91_MCI_MR, mr); - - at91_mci_write(AT91_MCI_BLKR, - AT91_MCI_BLKR_BCNT(blocks) | - AT91_MCI_BLKR_BLKLEN(block_length)); - - /* - * Disable the PDC controller - */ - at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS); - - if (cmdr & AT91_MCI_TRCMD_START) - { - if (cmdr & AT91_MCI_TRDIR) - { - /* - * Handle a read - */ - - mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blksize*data->blks); - at91_mci_init_dma_read(mci); - ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */; - } - else - { - /* - * Handle a write - */ - length = block_length * blocks; - /* - * at91mci MCI1 rev2xx Data Write Operation and - * number of bytes erratum - */ - if (length < 12) - { - length = 12; - mci->buf = rt_malloc(length); - if (!mci->buf) - { - rt_kprintf("rt alloc tx buffer failed\n"); - cmd->err = -RT_ENOMEM; - mmcsd_req_complete(mci->host); - return; - } - rt_memset(mci->buf, 0, 12); - rt_memcpy(mci->buf, data->buf, length); - mmu_clean_dcache((rt_uint32_t)mci->buf, length); - at91_mci_write(AT91_PDC_TPR, (rt_uint32_t)(mci->buf)); - at91_mci_write(AT91_PDC_TCR, (data->blksize & 0x3) ? - length : length / 4); - } - else - { - mmu_clean_dcache((rt_uint32_t)data->buf, data->blksize*data->blks); - at91_mci_write(AT91_PDC_TPR, (rt_uint32_t)(data->buf)); - at91_mci_write(AT91_PDC_TCR, (data->blksize & 0x3) ? - length : length / 4); - } - mci_dbg("Transmitting %d bytes\n", length); - ier = AT91_MCI_CMDRDY; - } - } - } - - /* - * Send the command and then enable the PDC - not the other way round as - * the data sheet says - */ - - at91_mci_write(AT91_MCI_ARGR, cmd->arg); - at91_mci_write(AT91_MCI_CMDR, cmdr); - - if (cmdr & AT91_MCI_TRCMD_START) - { - if (cmdr & AT91_MCI_TRDIR) - at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTEN); - } - - /* Enable selected interrupts */ - at91_mci_write(AT91_MCI_IER, AT91_MCI_ERRORS | ier); + rt_uint32_t cmdr, mr; + rt_uint32_t block_length; + struct rt_mmcsd_data *data = cmd->data; + struct rt_mmcsd_host *host = mci->host; + + rt_uint32_t blocks; + rt_uint32_t ier = 0; + rt_uint32_t length; + + mci->cmd = cmd; + + /* Needed for leaving busy state before CMD1 */ + if ((at91_mci_read(AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->cmd_code == 1)) + { + mci_dbg("Clearing timeout\n"); + at91_mci_write(AT91_MCI_ARGR, 0); + at91_mci_write(AT91_MCI_CMDR, AT91_MCI_OPDCMD); + while (!(at91_mci_read(AT91_MCI_SR) & AT91_MCI_CMDRDY)) + { + /* spin */ + mci_dbg("Clearing: SR = %08X\n", at91_mci_read(AT91_MCI_SR)); + } + } + + cmdr = cmd->cmd_code; + + if (resp_type(cmd) == RESP_NONE) + cmdr |= AT91_MCI_RSPTYP_NONE; + else + { + /* if a response is expected then allow maximum response latancy */ + cmdr |= AT91_MCI_MAXLAT; + /* set 136 bit response for R2, 48 bit response otherwise */ + if (resp_type(cmd) == RESP_R2) + cmdr |= AT91_MCI_RSPTYP_136; + else + cmdr |= AT91_MCI_RSPTYP_48; + } + + if (data) + { + + block_length = data->blksize; + blocks = data->blks; + + /* always set data start - also set direction flag for read */ + if (data->flags & DATA_DIR_READ) + cmdr |= (AT91_MCI_TRDIR | AT91_MCI_TRCMD_START); + else if (data->flags & DATA_DIR_WRITE) + cmdr |= AT91_MCI_TRCMD_START; + + if (data->flags & DATA_STREAM) + cmdr |= AT91_MCI_TRTYP_STREAM; + if (data->blks > 1) + cmdr |= AT91_MCI_TRTYP_MULTIPLE; + } + else + { + block_length = 0; + blocks = 0; + } + + /*if (cmd->cmd_code == GO_IDLE_STATE) + { + cmdr |= AT91_MCI_SPCMD_INIT; + }*/ + + if (cmd->cmd_code == STOP_TRANSMISSION) + cmdr |= AT91_MCI_TRCMD_STOP; + + if (host->io_cfg.bus_mode == MMCSD_BUSMODE_OPENDRAIN) + cmdr |= AT91_MCI_OPDCMD; + + /* + * Set the arguments and send the command + */ + mci_dbg("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n", + cmd->cmd_code, cmdr, cmd->arg, blocks, block_length, at91_mci_read(AT91_MCI_MR)); + + if (!data) + { + at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTDIS | AT91_PDC_RXTDIS); + at91_mci_write(AT91_PDC_RPR, 0); + at91_mci_write(AT91_PDC_RCR, 0); + at91_mci_write(AT91_PDC_RNPR, 0); + at91_mci_write(AT91_PDC_RNCR, 0); + at91_mci_write(AT91_PDC_TPR, 0); + at91_mci_write(AT91_PDC_TCR, 0); + at91_mci_write(AT91_PDC_TNPR, 0); + at91_mci_write(AT91_PDC_TNCR, 0); + ier = AT91_MCI_CMDRDY; + } + else + { + /* zero block length and PDC mode */ + mr = at91_mci_read(AT91_MCI_MR) & 0x5fff; + mr |= (data->blksize & 0x3) ? AT91_MCI_PDCFBYTE : 0; + mr |= (block_length << 16); + mr |= AT91_MCI_PDCMODE; + at91_mci_write(AT91_MCI_MR, mr); + + at91_mci_write(AT91_MCI_BLKR, + AT91_MCI_BLKR_BCNT(blocks) | + AT91_MCI_BLKR_BLKLEN(block_length)); + + /* + * Disable the PDC controller + */ + at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS); + + if (cmdr & AT91_MCI_TRCMD_START) + { + if (cmdr & AT91_MCI_TRDIR) + { + /* + * Handle a read + */ + + mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blksize*data->blks); + at91_mci_init_dma_read(mci); + ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */; + } + else + { + /* + * Handle a write + */ + length = block_length * blocks; + /* + * at91mci MCI1 rev2xx Data Write Operation and + * number of bytes erratum + */ + if (length < 12) + { + length = 12; + mci->buf = rt_malloc(length); + if (!mci->buf) + { + rt_kprintf("rt alloc tx buffer failed\n"); + cmd->err = -RT_ENOMEM; + mmcsd_req_complete(mci->host); + return; + } + rt_memset(mci->buf, 0, 12); + rt_memcpy(mci->buf, data->buf, length); + mmu_clean_dcache((rt_uint32_t)mci->buf, length); + at91_mci_write(AT91_PDC_TPR, (rt_uint32_t)(mci->buf)); + at91_mci_write(AT91_PDC_TCR, (data->blksize & 0x3) ? + length : length / 4); + } + else + { + mmu_clean_dcache((rt_uint32_t)data->buf, data->blksize*data->blks); + at91_mci_write(AT91_PDC_TPR, (rt_uint32_t)(data->buf)); + at91_mci_write(AT91_PDC_TCR, (data->blksize & 0x3) ? + length : length / 4); + } + mci_dbg("Transmitting %d bytes\n", length); + ier = AT91_MCI_CMDRDY; + } + } + } + + /* + * Send the command and then enable the PDC - not the other way round as + * the data sheet says + */ + + at91_mci_write(AT91_MCI_ARGR, cmd->arg); + at91_mci_write(AT91_MCI_CMDR, cmdr); + + if (cmdr & AT91_MCI_TRCMD_START) + { + if (cmdr & AT91_MCI_TRDIR) + at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTEN); + } + + /* Enable selected interrupts */ + at91_mci_write(AT91_MCI_IER, AT91_MCI_ERRORS | ier); } /* @@ -404,25 +404,25 @@ static void at91_mci_send_command(struct at91_mci *mci, struct rt_mmcsd_cmd *cmd */ static void at91_mci_process_next(struct at91_mci *mci) { - if (mci->current_status == REQ_ST_INIT) - { - mci->current_status = REQ_ST_CMD; - at91_mci_send_command(mci, mci->req->cmd); - } - else if ((mci->current_status == REQ_ST_CMD) && mci->req->stop) - { - mci->current_status = REQ_ST_STOP; - at91_mci_send_command(mci, mci->req->stop); - } - else - { - rt_timer_stop(&mci->timer); - /* the mci controller hangs after some transfers, - * and the workaround is to reset it after each transfer. - */ - at91_reset_host(); - mmcsd_req_complete(mci->host); - } + if (mci->current_status == REQ_ST_INIT) + { + mci->current_status = REQ_ST_CMD; + at91_mci_send_command(mci, mci->req->cmd); + } + else if ((mci->current_status == REQ_ST_CMD) && mci->req->stop) + { + mci->current_status = REQ_ST_STOP; + at91_mci_send_command(mci, mci->req->stop); + } + else + { + rt_timer_stop(&mci->timer); + /* the mci controller hangs after some transfers, + * and the workaround is to reset it after each transfer. + */ + at91_reset_host(); + mmcsd_req_complete(mci->host); + } } /* @@ -430,15 +430,15 @@ static void at91_mci_process_next(struct at91_mci *mci) */ static void at91_mci_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) { - rt_uint32_t timeout = RT_TICK_PER_SECOND; - struct at91_mci *mci = host->private_data; - mci->req = req; - mci->current_status = REQ_ST_INIT; + rt_uint32_t timeout = RT_TICK_PER_SECOND; + struct at91_mci *mci = host->private_data; + mci->req = req; + mci->current_status = REQ_ST_INIT; - rt_timer_control(&mci->timer, RT_TIMER_CTRL_SET_TIME, (void*)&timeout); - rt_timer_start(&mci->timer); + rt_timer_control(&mci->timer, RT_TIMER_CTRL_SET_TIME, (void*)&timeout); + rt_timer_start(&mci->timer); - at91_mci_process_next(mci); + at91_mci_process_next(mci); } /* @@ -446,29 +446,29 @@ static void at91_mci_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *re */ static void at91_mci_handle_transmitted(struct at91_mci *mci) { - struct rt_mmcsd_cmd *cmd; - struct rt_mmcsd_data *data; + struct rt_mmcsd_cmd *cmd; + struct rt_mmcsd_data *data; - mci_dbg("Handling the transmit\n"); + mci_dbg("Handling the transmit\n"); - /* Disable the transfer */ - at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS); + /* Disable the transfer */ + at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS); - /* Now wait for cmd ready */ - at91_mci_write(AT91_MCI_IDR, AT91_MCI_TXBUFE); + /* Now wait for cmd ready */ + at91_mci_write(AT91_MCI_IDR, AT91_MCI_TXBUFE); - cmd = mci->cmd; - if (!cmd) return; + cmd = mci->cmd; + if (!cmd) return; - data = cmd->data; - if (!data) return; + data = cmd->data; + if (!data) return; - if (data->blks > 1) - { - mci_dbg("multiple write : wait for BLKE...\n"); - at91_mci_write(AT91_MCI_IER, AT91_MCI_BLKE); - } else - at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY); + if (data->blks > 1) + { + mci_dbg("multiple write : wait for BLKE...\n"); + at91_mci_write(AT91_MCI_IER, AT91_MCI_BLKE); + } else + at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY); } @@ -477,54 +477,54 @@ static void at91_mci_handle_transmitted(struct at91_mci *mci) */ static void at91_mci_post_dma_read(struct at91_mci *mci) { - struct rt_mmcsd_cmd *cmd; - struct rt_mmcsd_data *data; + struct rt_mmcsd_cmd *cmd; + struct rt_mmcsd_data *data; - mci_dbg("post dma read\n"); + mci_dbg("post dma read\n"); - cmd = mci->cmd; - if (!cmd) - { - mci_dbg("no command\n"); - return; - } + cmd = mci->cmd; + if (!cmd) + { + mci_dbg("no command\n"); + return; + } - data = cmd->data; - if (!data) - { - mci_dbg("no data\n"); - return; - } + data = cmd->data; + if (!data) + { + mci_dbg("no data\n"); + return; + } - at91_mci_write(AT91_MCI_IDR, AT91_MCI_ENDRX); - at91_mci_write(AT91_MCI_IER, AT91_MCI_RXBUFF); + at91_mci_write(AT91_MCI_IDR, AT91_MCI_ENDRX); + at91_mci_write(AT91_MCI_IER, AT91_MCI_RXBUFF); - mci_dbg("post dma read done\n"); + mci_dbg("post dma read done\n"); } /*Handle after command sent ready*/ static int at91_mci_handle_cmdrdy(struct at91_mci *mci) { - if (!mci->cmd) - return 1; - else if (!mci->cmd->data) - { - if (mci->current_status == REQ_ST_STOP) - { - /*After multi block write, we must wait for NOTBUSY*/ - at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY); - } - else return 1; - } - else if (mci->cmd->data->flags & DATA_DIR_WRITE) - { - /*After sendding multi-block-write command, start DMA transfer*/ - at91_mci_write(AT91_MCI_IER, AT91_MCI_TXBUFE | AT91_MCI_BLKE); - at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTEN); - } - - /* command not completed, have to wait */ - return 0; + if (!mci->cmd) + return 1; + else if (!mci->cmd->data) + { + if (mci->current_status == REQ_ST_STOP) + { + /*After multi block write, we must wait for NOTBUSY*/ + at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY); + } + else return 1; + } + else if (mci->cmd->data->flags & DATA_DIR_WRITE) + { + /*After sendding multi-block-write command, start DMA transfer*/ + at91_mci_write(AT91_MCI_IER, AT91_MCI_TXBUFE | AT91_MCI_BLKE); + at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTEN); + } + + /* command not completed, have to wait */ + return 0; } /* @@ -532,64 +532,64 @@ static int at91_mci_handle_cmdrdy(struct at91_mci *mci) */ static void at91_mci_completed_command(struct at91_mci *mci, rt_uint32_t status) { - struct rt_mmcsd_cmd *cmd = mci->cmd; - struct rt_mmcsd_data *data = cmd->data; - - at91_mci_write(AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); - - cmd->resp[0] = at91_mci_read(AT91_MCI_RSPR(0)); - cmd->resp[1] = at91_mci_read(AT91_MCI_RSPR(1)); - cmd->resp[2] = at91_mci_read(AT91_MCI_RSPR(2)); - cmd->resp[3] = at91_mci_read(AT91_MCI_RSPR(3)); - - if (mci->buf) - { - //rt_memcpy(data->buf, mci->buf, data->blksize*data->blks); - rt_free(mci->buf); - mci->buf = RT_NULL; - } - - mci_dbg("Status = %08X/%08x [%08X %08X %08X %08X]\n", - status, at91_mci_read(AT91_MCI_SR), - cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); - - if (status & AT91_MCI_ERRORS) - { - if ((status & AT91_MCI_RCRCE) && (resp_type(cmd) & (RESP_R3|RESP_R4))) - { - cmd->err = 0; - } - else - { - if (status & (AT91_MCI_DTOE | AT91_MCI_DCRCE)) - { - if (data) - { - if (status & AT91_MCI_DTOE) - data->err = -RT_ETIMEOUT; - else if (status & AT91_MCI_DCRCE) - data->err = -RT_ERROR; - } - } - else - { - if (status & AT91_MCI_RTOE) - cmd->err = -RT_ETIMEOUT; - else if (status & AT91_MCI_RCRCE) - cmd->err = -RT_ERROR; - else - cmd->err = -RT_ERROR; - } - - rt_kprintf("error detected and set to %d/%d (cmd = %d)\n", - cmd->err, data ? data->err : 0, - cmd->cmd_code); - } - } - else - cmd->err = 0; - - at91_mci_process_next(mci); + struct rt_mmcsd_cmd *cmd = mci->cmd; + struct rt_mmcsd_data *data = cmd->data; + + at91_mci_write(AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); + + cmd->resp[0] = at91_mci_read(AT91_MCI_RSPR(0)); + cmd->resp[1] = at91_mci_read(AT91_MCI_RSPR(1)); + cmd->resp[2] = at91_mci_read(AT91_MCI_RSPR(2)); + cmd->resp[3] = at91_mci_read(AT91_MCI_RSPR(3)); + + if (mci->buf) + { + //rt_memcpy(data->buf, mci->buf, data->blksize*data->blks); + rt_free(mci->buf); + mci->buf = RT_NULL; + } + + mci_dbg("Status = %08X/%08x [%08X %08X %08X %08X]\n", + status, at91_mci_read(AT91_MCI_SR), + cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); + + if (status & AT91_MCI_ERRORS) + { + if ((status & AT91_MCI_RCRCE) && (resp_type(cmd) & (RESP_R3|RESP_R4))) + { + cmd->err = 0; + } + else + { + if (status & (AT91_MCI_DTOE | AT91_MCI_DCRCE)) + { + if (data) + { + if (status & AT91_MCI_DTOE) + data->err = -RT_ETIMEOUT; + else if (status & AT91_MCI_DCRCE) + data->err = -RT_ERROR; + } + } + else + { + if (status & AT91_MCI_RTOE) + cmd->err = -RT_ETIMEOUT; + else if (status & AT91_MCI_RCRCE) + cmd->err = -RT_ERROR; + else + cmd->err = -RT_ERROR; + } + + rt_kprintf("error detected and set to %d/%d (cmd = %d)\n", + cmd->err, data ? data->err : 0, + cmd->cmd_code); + } + } + else + cmd->err = 0; + + at91_mci_process_next(mci); } /* @@ -597,120 +597,120 @@ static void at91_mci_completed_command(struct at91_mci *mci, rt_uint32_t status) */ static void at91_mci_irq(int irq, void *param) { - struct at91_mci *mci = (struct at91_mci *)param; - rt_int32_t completed = 0; - rt_uint32_t int_status, int_mask; - - int_status = at91_mci_read(AT91_MCI_SR); - int_mask = at91_mci_read(AT91_MCI_IMR); - - mci_dbg("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask, - int_status & int_mask); - - int_status = int_status & int_mask; - - if (int_status & AT91_MCI_ERRORS) - { - completed = 1; - - if (int_status & AT91_MCI_UNRE) - mci_dbg("MMC: Underrun error\n"); - if (int_status & AT91_MCI_OVRE) - mci_dbg("MMC: Overrun error\n"); - if (int_status & AT91_MCI_DTOE) - mci_dbg("MMC: Data timeout\n"); - if (int_status & AT91_MCI_DCRCE) - mci_dbg("MMC: CRC error in data\n"); - if (int_status & AT91_MCI_RTOE) - mci_dbg("MMC: Response timeout\n"); - if (int_status & AT91_MCI_RENDE) - mci_dbg("MMC: Response end bit error\n"); - if (int_status & AT91_MCI_RCRCE) - mci_dbg("MMC: Response CRC error\n"); - if (int_status & AT91_MCI_RDIRE) - mci_dbg("MMC: Response direction error\n"); - if (int_status & AT91_MCI_RINDE) - mci_dbg("MMC: Response index error\n"); - } - else - { - /* Only continue processing if no errors */ - - if (int_status & AT91_MCI_TXBUFE) - { - mci_dbg("TX buffer empty\n"); - at91_mci_handle_transmitted(mci); - } - - if (int_status & AT91_MCI_ENDRX) - { - mci_dbg("ENDRX\n"); - at91_mci_post_dma_read(mci); - } - - if (int_status & AT91_MCI_RXBUFF) - { - mci_dbg("RX buffer full\n"); - at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS); - at91_mci_write(AT91_MCI_IDR, AT91_MCI_RXBUFF | AT91_MCI_ENDRX); - completed = 1; - } - - if (int_status & AT91_MCI_ENDTX) - mci_dbg("Transmit has ended\n"); - - if (int_status & AT91_MCI_NOTBUSY) - { - mci_dbg("Card is ready\n"); - //at91_mci_update_bytes_xfered(host); - completed = 1; - } - - if (int_status & AT91_MCI_DTIP) - mci_dbg("Data transfer in progress\n"); - - if (int_status & AT91_MCI_BLKE) - { - mci_dbg("Block transfer has ended\n"); - if (mci->req->data && mci->req->data->blks > 1) - { - /* multi block write : complete multi write - * command and send stop */ - completed = 1; - } - else - { - at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY); - } - } - - /*if (int_status & AT91_MCI_SDIOIRQA) - rt_mmcsd_signal_sdio_irq(host->mmc);*/ - - if (int_status & AT91_MCI_SDIOIRQB) - sdio_irq_wakeup(mci->host); - - if (int_status & AT91_MCI_TXRDY) - mci_dbg("Ready to transmit\n"); - - if (int_status & AT91_MCI_RXRDY) - mci_dbg("Ready to receive\n"); - - if (int_status & AT91_MCI_CMDRDY) - { - mci_dbg("Command ready\n"); - completed = at91_mci_handle_cmdrdy(mci); - } - } - - if (completed) - { - mci_dbg("Completed command\n"); - at91_mci_write(AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); - at91_mci_completed_command(mci, int_status); - } - else - at91_mci_write(AT91_MCI_IDR, int_status & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); + struct at91_mci *mci = (struct at91_mci *)param; + rt_int32_t completed = 0; + rt_uint32_t int_status, int_mask; + + int_status = at91_mci_read(AT91_MCI_SR); + int_mask = at91_mci_read(AT91_MCI_IMR); + + mci_dbg("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask, + int_status & int_mask); + + int_status = int_status & int_mask; + + if (int_status & AT91_MCI_ERRORS) + { + completed = 1; + + if (int_status & AT91_MCI_UNRE) + mci_dbg("MMC: Underrun error\n"); + if (int_status & AT91_MCI_OVRE) + mci_dbg("MMC: Overrun error\n"); + if (int_status & AT91_MCI_DTOE) + mci_dbg("MMC: Data timeout\n"); + if (int_status & AT91_MCI_DCRCE) + mci_dbg("MMC: CRC error in data\n"); + if (int_status & AT91_MCI_RTOE) + mci_dbg("MMC: Response timeout\n"); + if (int_status & AT91_MCI_RENDE) + mci_dbg("MMC: Response end bit error\n"); + if (int_status & AT91_MCI_RCRCE) + mci_dbg("MMC: Response CRC error\n"); + if (int_status & AT91_MCI_RDIRE) + mci_dbg("MMC: Response direction error\n"); + if (int_status & AT91_MCI_RINDE) + mci_dbg("MMC: Response index error\n"); + } + else + { + /* Only continue processing if no errors */ + + if (int_status & AT91_MCI_TXBUFE) + { + mci_dbg("TX buffer empty\n"); + at91_mci_handle_transmitted(mci); + } + + if (int_status & AT91_MCI_ENDRX) + { + mci_dbg("ENDRX\n"); + at91_mci_post_dma_read(mci); + } + + if (int_status & AT91_MCI_RXBUFF) + { + mci_dbg("RX buffer full\n"); + at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS); + at91_mci_write(AT91_MCI_IDR, AT91_MCI_RXBUFF | AT91_MCI_ENDRX); + completed = 1; + } + + if (int_status & AT91_MCI_ENDTX) + mci_dbg("Transmit has ended\n"); + + if (int_status & AT91_MCI_NOTBUSY) + { + mci_dbg("Card is ready\n"); + //at91_mci_update_bytes_xfered(host); + completed = 1; + } + + if (int_status & AT91_MCI_DTIP) + mci_dbg("Data transfer in progress\n"); + + if (int_status & AT91_MCI_BLKE) + { + mci_dbg("Block transfer has ended\n"); + if (mci->req->data && mci->req->data->blks > 1) + { + /* multi block write : complete multi write + * command and send stop */ + completed = 1; + } + else + { + at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY); + } + } + + /*if (int_status & AT91_MCI_SDIOIRQA) + rt_mmcsd_signal_sdio_irq(host->mmc);*/ + + if (int_status & AT91_MCI_SDIOIRQB) + sdio_irq_wakeup(mci->host); + + if (int_status & AT91_MCI_TXRDY) + mci_dbg("Ready to transmit\n"); + + if (int_status & AT91_MCI_RXRDY) + mci_dbg("Ready to receive\n"); + + if (int_status & AT91_MCI_CMDRDY) + { + mci_dbg("Command ready\n"); + completed = at91_mci_handle_cmdrdy(mci); + } + } + + if (completed) + { + mci_dbg("Completed command\n"); + at91_mci_write(AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); + at91_mci_completed_command(mci, int_status); + } + else + at91_mci_write(AT91_MCI_IDR, int_status & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); } @@ -720,173 +720,173 @@ static void at91_mci_irq(int irq, void *param) */ static void at91_mci_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) { - rt_uint32_t clkdiv; - //struct at91_mci *mci = host->private_data; - rt_uint32_t at91_master_clock = clk_get_rate(clk_get("mck")); - - if (io_cfg->clock == 0) - { - /* Disable the MCI controller */ - at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS); - clkdiv = 0; - } - else - { - /* Enable the MCI controller */ - at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN); - - if ((at91_master_clock % (io_cfg->clock * 2)) == 0) - clkdiv = ((at91_master_clock / io_cfg->clock) / 2) - 1; - else - clkdiv = (at91_master_clock / io_cfg->clock) / 2; - - mci_dbg("clkdiv = %d. mcck = %ld\n", clkdiv, - at91_master_clock / (2 * (clkdiv + 1))); - } - if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4) - { - mci_dbg("MMC: Setting controller bus width to 4\n"); - at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) | AT91_MCI_SDCBUS); - } - else - { - mci_dbg("MMC: Setting controller bus width to 1\n"); - at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS); - } - - /* Set the clock divider */ - at91_mci_write(AT91_MCI_MR, (at91_mci_read(AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv); - - /* maybe switch power to the card */ - switch (io_cfg->power_mode) - { - case MMCSD_POWER_OFF: - break; - case MMCSD_POWER_UP: - break; - case MMCSD_POWER_ON: - /*at91_mci_write(AT91_MCI_ARGR, 0); - at91_mci_write(AT91_MCI_CMDR, 0|AT91_MCI_SPCMD_INIT|AT91_MCI_OPDCMD); - mci_dbg("MCI_SR=0x%08x\n", at91_mci_read(AT91_MCI_SR)); - while (!(at91_mci_read(AT91_MCI_SR) & AT91_MCI_CMDRDY)) - { - - } - mci_dbg("at91 mci power on\n");*/ - break; - default: - rt_kprintf("unknown power_mode %d\n", io_cfg->power_mode); - break; - } + rt_uint32_t clkdiv; + //struct at91_mci *mci = host->private_data; + rt_uint32_t at91_master_clock = clk_get_rate(clk_get("mck")); + + if (io_cfg->clock == 0) + { + /* Disable the MCI controller */ + at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS); + clkdiv = 0; + } + else + { + /* Enable the MCI controller */ + at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN); + + if ((at91_master_clock % (io_cfg->clock * 2)) == 0) + clkdiv = ((at91_master_clock / io_cfg->clock) / 2) - 1; + else + clkdiv = (at91_master_clock / io_cfg->clock) / 2; + + mci_dbg("clkdiv = %d. mcck = %ld\n", clkdiv, + at91_master_clock / (2 * (clkdiv + 1))); + } + if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4) + { + mci_dbg("MMC: Setting controller bus width to 4\n"); + at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) | AT91_MCI_SDCBUS); + } + else + { + mci_dbg("MMC: Setting controller bus width to 1\n"); + at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS); + } + + /* Set the clock divider */ + at91_mci_write(AT91_MCI_MR, (at91_mci_read(AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv); + + /* maybe switch power to the card */ + switch (io_cfg->power_mode) + { + case MMCSD_POWER_OFF: + break; + case MMCSD_POWER_UP: + break; + case MMCSD_POWER_ON: + /*at91_mci_write(AT91_MCI_ARGR, 0); + at91_mci_write(AT91_MCI_CMDR, 0|AT91_MCI_SPCMD_INIT|AT91_MCI_OPDCMD); + mci_dbg("MCI_SR=0x%08x\n", at91_mci_read(AT91_MCI_SR)); + while (!(at91_mci_read(AT91_MCI_SR) & AT91_MCI_CMDRDY)) + { + + } + mci_dbg("at91 mci power on\n");*/ + break; + default: + rt_kprintf("unknown power_mode %d\n", io_cfg->power_mode); + break; + } } static void at91_mci_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t enable) { - at91_mci_write(enable ? AT91_MCI_IER : AT91_MCI_IDR, AT91_MCI_SDIOIRQB); + at91_mci_write(enable ? AT91_MCI_IER : AT91_MCI_IDR, AT91_MCI_SDIOIRQB); } static const struct rt_mmcsd_host_ops ops = { - at91_mci_request, - at91_mci_set_iocfg, + at91_mci_request, + at91_mci_set_iocfg, RT_NULL, - at91_mci_enable_sdio_irq, + at91_mci_enable_sdio_irq, }; void at91_mci_detect(int irq, void *param) { - rt_kprintf("mmcsd gpio detected\n"); + rt_kprintf("mmcsd gpio detected\n"); } static void mci_gpio_init() { #ifdef USE_SLOT_B - at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)); - at91_sys_write(AT91_PIOA + PIO_PUDR, (1 << 8)); - at91_sys_write(AT91_PIOA + PIO_BSR, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)); - at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 8)); - at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)|(1 << 8)); - - at91_sys_write(AT91_PIOA + PIO_IDR, (1 << 6)|(1 << 7)); - at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 6)|(1 << 7)); - at91_sys_write(AT91_PIOA + PIO_ODR, (1 << 6)|(1 << 7)); - at91_sys_write(AT91_PIOA + PIO_PER, (1 << 6)|(1 << 7)); + at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)); + at91_sys_write(AT91_PIOA + PIO_PUDR, (1 << 8)); + at91_sys_write(AT91_PIOA + PIO_BSR, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)); + at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 8)); + at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)|(1 << 8)); + + at91_sys_write(AT91_PIOA + PIO_IDR, (1 << 6)|(1 << 7)); + at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 6)|(1 << 7)); + at91_sys_write(AT91_PIOA + PIO_ODR, (1 << 6)|(1 << 7)); + at91_sys_write(AT91_PIOA + PIO_PER, (1 << 6)|(1 << 7)); #else - at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)); - at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8)); - at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8)); + at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)); + at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8)); + at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8)); #endif } int at91_mci_init(void) { - struct rt_mmcsd_host *host; - struct at91_mci *mci; - - host = mmcsd_alloc_host(); - if (!host) - { - return -RT_ERROR; - } - - mci = rt_malloc(sizeof(struct at91_mci)); - if (!mci) - { - rt_kprintf("alloc mci failed\n"); - goto err; - } - - rt_memset(mci, 0, sizeof(struct at91_mci)); - - host->ops = &ops; - host->freq_min = 375000; - host->freq_max = 25000000; - host->valid_ocr = VDD_32_33 | VDD_33_34; - host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | \ - MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ; - host->max_seg_size = 65535; - host->max_dma_segs = 2; - host->max_blk_size = 512; - host->max_blk_count = 4096; - - mci->host = host; - - mci_gpio_init(); - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_MCI); //enable MCI clock - - at91_mci_disable(); - at91_mci_enable(); - - /* instal interrupt */ - rt_hw_interrupt_install(AT91SAM9260_ID_MCI, at91_mci_irq, - (void *)mci, "MMC"); - rt_hw_interrupt_umask(AT91SAM9260_ID_MCI); - rt_hw_interrupt_install(gpio_to_irq(AT91_PIN_PA7), - at91_mci_detect, RT_NULL, "MMC_DETECT"); - rt_hw_interrupt_umask(gpio_to_irq(AT91_PIN_PA7)); - - rt_timer_init(&mci->timer, "mci_timer", - at91_timeout_timer, - mci, - RT_TICK_PER_SECOND, - RT_TIMER_FLAG_PERIODIC); - - //rt_timer_start(&mci->timer); - - //rt_sem_init(&mci->sem_ack, "sd_ack", 0, RT_IPC_FLAG_FIFO); - - host->private_data = mci; - - mmcsd_change(host); - - return 0; + struct rt_mmcsd_host *host; + struct at91_mci *mci; + + host = mmcsd_alloc_host(); + if (!host) + { + return -RT_ERROR; + } + + mci = rt_malloc(sizeof(struct at91_mci)); + if (!mci) + { + rt_kprintf("alloc mci failed\n"); + goto err; + } + + rt_memset(mci, 0, sizeof(struct at91_mci)); + + host->ops = &ops; + host->freq_min = 375000; + host->freq_max = 25000000; + host->valid_ocr = VDD_32_33 | VDD_33_34; + host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | \ + MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ; + host->max_seg_size = 65535; + host->max_dma_segs = 2; + host->max_blk_size = 512; + host->max_blk_count = 4096; + + mci->host = host; + + mci_gpio_init(); + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_MCI); //enable MCI clock + + at91_mci_disable(); + at91_mci_enable(); + + /* instal interrupt */ + rt_hw_interrupt_install(AT91SAM9260_ID_MCI, at91_mci_irq, + (void *)mci, "MMC"); + rt_hw_interrupt_umask(AT91SAM9260_ID_MCI); + rt_hw_interrupt_install(gpio_to_irq(AT91_PIN_PA7), + at91_mci_detect, RT_NULL, "MMC_DETECT"); + rt_hw_interrupt_umask(gpio_to_irq(AT91_PIN_PA7)); + + rt_timer_init(&mci->timer, "mci_timer", + at91_timeout_timer, + mci, + RT_TICK_PER_SECOND, + RT_TIMER_FLAG_PERIODIC); + + //rt_timer_start(&mci->timer); + + //rt_sem_init(&mci->sem_ack, "sd_ack", 0, RT_IPC_FLAG_FIFO); + + host->private_data = mci; + + mmcsd_change(host); + + return 0; err: - mmcsd_free_host(host); + mmcsd_free_host(host); - return -RT_ENOMEM; + return -RT_ENOMEM; } INIT_DEVICE_EXPORT(at91_mci_init); @@ -896,15 +896,15 @@ FINSH_FUNCTION_EXPORT(at91_mci_init, at91sam9260 sd init); void mci_dump(void) { - rt_uint32_t i; + rt_uint32_t i; - rt_kprintf("PIOA_PSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_PSR)); - rt_kprintf("PIOA_ABSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_ABSR)); - rt_kprintf("PIOA_PUSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_PUSR)); + rt_kprintf("PIOA_PSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_PSR)); + rt_kprintf("PIOA_ABSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_ABSR)); + rt_kprintf("PIOA_PUSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_PUSR)); - for (i = 0; i <= 0x4c; i += 4) { - rt_kprintf("0x%08x:0x%08x\n", AT91SAM9260_BASE_MCI+i, at91_mci_read(i)); - } + for (i = 0; i <= 0x4c; i += 4) { + rt_kprintf("0x%08x:0x%08x\n", AT91SAM9260_BASE_MCI+i, at91_mci_read(i)); + } } FINSH_FUNCTION_EXPORT(mci_dump, dump register for mci); diff --git a/bsp/at91sam9260/drivers/at91_mci.h b/bsp/at91sam9260/drivers/at91_mci.h index f2e4a0a56c..80eb07385d 100644 --- a/bsp/at91sam9260/drivers/at91_mci.h +++ b/bsp/at91sam9260/drivers/at91_mci.h @@ -11,99 +11,99 @@ #ifndef __AT91_MCI_H__ #define __AT91_MCI_H__ -#define AT91_MCI_CR 0x00 /* Control Register */ -#define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */ -#define AT91_MCI_MCIDIS (1 << 1) /* Multi-Media Interface Disable */ -#define AT91_MCI_PWSEN (1 << 2) /* Power Save Mode Enable */ -#define AT91_MCI_PWSDIS (1 << 3) /* Power Save Mode Disable */ -#define AT91_MCI_SWRST (1 << 7) /* Software Reset */ +#define AT91_MCI_CR 0x00 /* Control Register */ +#define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */ +#define AT91_MCI_MCIDIS (1 << 1) /* Multi-Media Interface Disable */ +#define AT91_MCI_PWSEN (1 << 2) /* Power Save Mode Enable */ +#define AT91_MCI_PWSDIS (1 << 3) /* Power Save Mode Disable */ +#define AT91_MCI_SWRST (1 << 7) /* Software Reset */ -#define AT91_MCI_MR 0x04 /* Mode Register */ -#define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */ -#define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */ -#define AT91_MCI_RDPROOF (1 << 11) /* Read Proof Enable [SAM926[03] only] */ -#define AT91_MCI_WRPROOF (1 << 12) /* Write Proof Enable [SAM926[03] only] */ -#define AT91_MCI_PDCFBYTE (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */ -#define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */ -#define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */ -#define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */ +#define AT91_MCI_MR 0x04 /* Mode Register */ +#define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */ +#define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */ +#define AT91_MCI_RDPROOF (1 << 11) /* Read Proof Enable [SAM926[03] only] */ +#define AT91_MCI_WRPROOF (1 << 12) /* Write Proof Enable [SAM926[03] only] */ +#define AT91_MCI_PDCFBYTE (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */ +#define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */ +#define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */ +#define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */ -#define AT91_MCI_DTOR 0x08 /* Data Timeout Register */ -#define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */ -#define AT91_MCI_DTOMUL (7 << 4) /* Data Timeout Multiplier */ -#define AT91_MCI_DTOMUL_1 (0 << 4) -#define AT91_MCI_DTOMUL_16 (1 << 4) -#define AT91_MCI_DTOMUL_128 (2 << 4) -#define AT91_MCI_DTOMUL_256 (3 << 4) -#define AT91_MCI_DTOMUL_1K (4 << 4) -#define AT91_MCI_DTOMUL_4K (5 << 4) -#define AT91_MCI_DTOMUL_64K (6 << 4) -#define AT91_MCI_DTOMUL_1M (7 << 4) +#define AT91_MCI_DTOR 0x08 /* Data Timeout Register */ +#define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */ +#define AT91_MCI_DTOMUL (7 << 4) /* Data Timeout Multiplier */ +#define AT91_MCI_DTOMUL_1 (0 << 4) +#define AT91_MCI_DTOMUL_16 (1 << 4) +#define AT91_MCI_DTOMUL_128 (2 << 4) +#define AT91_MCI_DTOMUL_256 (3 << 4) +#define AT91_MCI_DTOMUL_1K (4 << 4) +#define AT91_MCI_DTOMUL_4K (5 << 4) +#define AT91_MCI_DTOMUL_64K (6 << 4) +#define AT91_MCI_DTOMUL_1M (7 << 4) -#define AT91_MCI_SDCR 0x0c /* SD Card Register */ -#define AT91_MCI_SDCSEL (3 << 0) /* SD Card Selector */ -#define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */ +#define AT91_MCI_SDCR 0x0c /* SD Card Register */ +#define AT91_MCI_SDCSEL (3 << 0) /* SD Card Selector */ +#define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */ -#define AT91_MCI_ARGR 0x10 /* Argument Register */ +#define AT91_MCI_ARGR 0x10 /* Argument Register */ -#define AT91_MCI_CMDR 0x14 /* Command Register */ -#define AT91_MCI_CMDNB (0x3f << 0) /* Command Number */ -#define AT91_MCI_RSPTYP (3 << 6) /* Response Type */ -#define AT91_MCI_RSPTYP_NONE (0 << 6) -#define AT91_MCI_RSPTYP_48 (1 << 6) -#define AT91_MCI_RSPTYP_136 (2 << 6) -#define AT91_MCI_SPCMD (7 << 8) /* Special Command */ -#define AT91_MCI_SPCMD_NONE (0 << 8) -#define AT91_MCI_SPCMD_INIT (1 << 8) -#define AT91_MCI_SPCMD_SYNC (2 << 8) -#define AT91_MCI_SPCMD_ICMD (4 << 8) -#define AT91_MCI_SPCMD_IRESP (5 << 8) -#define AT91_MCI_OPDCMD (1 << 11) /* Open Drain Command */ -#define AT91_MCI_MAXLAT (1 << 12) /* Max Latency for Command to Response */ -#define AT91_MCI_TRCMD (3 << 16) /* Transfer Command */ -#define AT91_MCI_TRCMD_NONE (0 << 16) -#define AT91_MCI_TRCMD_START (1 << 16) -#define AT91_MCI_TRCMD_STOP (2 << 16) -#define AT91_MCI_TRDIR (1 << 18) /* Transfer Direction */ -#define AT91_MCI_TRTYP (3 << 19) /* Transfer Type */ -#define AT91_MCI_TRTYP_BLOCK (0 << 19) -#define AT91_MCI_TRTYP_MULTIPLE (1 << 19) -#define AT91_MCI_TRTYP_STREAM (2 << 19) +#define AT91_MCI_CMDR 0x14 /* Command Register */ +#define AT91_MCI_CMDNB (0x3f << 0) /* Command Number */ +#define AT91_MCI_RSPTYP (3 << 6) /* Response Type */ +#define AT91_MCI_RSPTYP_NONE (0 << 6) +#define AT91_MCI_RSPTYP_48 (1 << 6) +#define AT91_MCI_RSPTYP_136 (2 << 6) +#define AT91_MCI_SPCMD (7 << 8) /* Special Command */ +#define AT91_MCI_SPCMD_NONE (0 << 8) +#define AT91_MCI_SPCMD_INIT (1 << 8) +#define AT91_MCI_SPCMD_SYNC (2 << 8) +#define AT91_MCI_SPCMD_ICMD (4 << 8) +#define AT91_MCI_SPCMD_IRESP (5 << 8) +#define AT91_MCI_OPDCMD (1 << 11) /* Open Drain Command */ +#define AT91_MCI_MAXLAT (1 << 12) /* Max Latency for Command to Response */ +#define AT91_MCI_TRCMD (3 << 16) /* Transfer Command */ +#define AT91_MCI_TRCMD_NONE (0 << 16) +#define AT91_MCI_TRCMD_START (1 << 16) +#define AT91_MCI_TRCMD_STOP (2 << 16) +#define AT91_MCI_TRDIR (1 << 18) /* Transfer Direction */ +#define AT91_MCI_TRTYP (3 << 19) /* Transfer Type */ +#define AT91_MCI_TRTYP_BLOCK (0 << 19) +#define AT91_MCI_TRTYP_MULTIPLE (1 << 19) +#define AT91_MCI_TRTYP_STREAM (2 << 19) -#define AT91_MCI_BLKR 0x18 /* Block Register */ -#define AT91_MCI_BLKR_BCNT(n) ((0xffff & (n)) << 0) /* Block count */ -#define AT91_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16) /* Block lenght */ +#define AT91_MCI_BLKR 0x18 /* Block Register */ +#define AT91_MCI_BLKR_BCNT(n) ((0xffff & (n)) << 0) /* Block count */ +#define AT91_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16) /* Block lenght */ -#define AT91_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */ -#define AT91_MCR_RDR 0x30 /* Receive Data Register */ -#define AT91_MCR_TDR 0x34 /* Transmit Data Register */ +#define AT91_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */ +#define AT91_MCR_RDR 0x30 /* Receive Data Register */ +#define AT91_MCR_TDR 0x34 /* Transmit Data Register */ -#define AT91_MCI_SR 0x40 /* Status Register */ -#define AT91_MCI_CMDRDY (1U << 0) /* Command Ready */ -#define AT91_MCI_RXRDY (1U << 1) /* Receiver Ready */ -#define AT91_MCI_TXRDY (1U << 2) /* Transmit Ready */ -#define AT91_MCI_BLKE (1U << 3) /* Data Block Ended */ -#define AT91_MCI_DTIP (1U << 4) /* Data Transfer in Progress */ -#define AT91_MCI_NOTBUSY (1U << 5) /* Data Not Busy */ -#define AT91_MCI_ENDRX (1U << 6) /* End of RX Buffer */ -#define AT91_MCI_ENDTX (1U << 7) /* End fo TX Buffer */ -#define AT91_MCI_SDIOIRQA (1U << 8) /* SDIO Interrupt for Slot A */ -#define AT91_MCI_SDIOIRQB (1U << 9) /* SDIO Interrupt for Slot B */ -#define AT91_MCI_RXBUFF (1U << 14) /* RX Buffer Full */ -#define AT91_MCI_TXBUFE (1U << 15) /* TX Buffer Empty */ -#define AT91_MCI_RINDE (1U << 16) /* Response Index Error */ -#define AT91_MCI_RDIRE (1U << 17) /* Response Direction Error */ -#define AT91_MCI_RCRCE (1U << 18) /* Response CRC Error */ -#define AT91_MCI_RENDE (1U << 19) /* Response End Bit Error */ -#define AT91_MCI_RTOE (1U << 20) /* Reponse Time-out Error */ -#define AT91_MCI_DCRCE (1U << 21) /* Data CRC Error */ -#define AT91_MCI_DTOE (1U << 22) /* Data Time-out Error */ -#define AT91_MCI_OVRE (1U << 30) /* Overrun */ -#define AT91_MCI_UNRE (1U << 31) /* Underrun */ +#define AT91_MCI_SR 0x40 /* Status Register */ +#define AT91_MCI_CMDRDY (1U << 0) /* Command Ready */ +#define AT91_MCI_RXRDY (1U << 1) /* Receiver Ready */ +#define AT91_MCI_TXRDY (1U << 2) /* Transmit Ready */ +#define AT91_MCI_BLKE (1U << 3) /* Data Block Ended */ +#define AT91_MCI_DTIP (1U << 4) /* Data Transfer in Progress */ +#define AT91_MCI_NOTBUSY (1U << 5) /* Data Not Busy */ +#define AT91_MCI_ENDRX (1U << 6) /* End of RX Buffer */ +#define AT91_MCI_ENDTX (1U << 7) /* End fo TX Buffer */ +#define AT91_MCI_SDIOIRQA (1U << 8) /* SDIO Interrupt for Slot A */ +#define AT91_MCI_SDIOIRQB (1U << 9) /* SDIO Interrupt for Slot B */ +#define AT91_MCI_RXBUFF (1U << 14) /* RX Buffer Full */ +#define AT91_MCI_TXBUFE (1U << 15) /* TX Buffer Empty */ +#define AT91_MCI_RINDE (1U << 16) /* Response Index Error */ +#define AT91_MCI_RDIRE (1U << 17) /* Response Direction Error */ +#define AT91_MCI_RCRCE (1U << 18) /* Response CRC Error */ +#define AT91_MCI_RENDE (1U << 19) /* Response End Bit Error */ +#define AT91_MCI_RTOE (1U << 20) /* Reponse Time-out Error */ +#define AT91_MCI_DCRCE (1U << 21) /* Data CRC Error */ +#define AT91_MCI_DTOE (1U << 22) /* Data Time-out Error */ +#define AT91_MCI_OVRE (1U << 30) /* Overrun */ +#define AT91_MCI_UNRE (1U << 31) /* Underrun */ -#define AT91_MCI_IER 0x44 /* Interrupt Enable Register */ -#define AT91_MCI_IDR 0x48 /* Interrupt Disable Register */ -#define AT91_MCI_IMR 0x4c /* Interrupt Mask Register */ +#define AT91_MCI_IER 0x44 /* Interrupt Enable Register */ +#define AT91_MCI_IDR 0x48 /* Interrupt Disable Register */ +#define AT91_MCI_IMR 0x4c /* Interrupt Mask Register */ extern int at91_mci_init(void); diff --git a/bsp/at91sam9260/drivers/board.c b/bsp/at91sam9260/drivers/board.c index 78404a4ee0..8a063cfc86 100644 --- a/bsp/at91sam9260/drivers/board.c +++ b/bsp/at91sam9260/drivers/board.c @@ -40,56 +40,56 @@ extern void rt_hw_set_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv); extern void rt_dbgu_isr(void); static struct mem_desc at91_mem_desc[] = { - { 0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB }, /* None cached for 4G memory */ - { 0x20000000, 0x24000000-1, 0x20000000, RW_CB }, /* 64M cached SDRAM memory */ - { 0x00000000, 0x100000, 0x20000000, RW_CB }, /* isr vector table */ - { 0x90000000, 0x90400000-1, 0x00200000, RW_NCNB }, /* 4K SRAM0@2M + 4k SRAM1@3M + 16k UHP@5M */ - { 0xA0000000, 0xA4000000-1, 0x20000000, RW_NCNB } /* 64M none-cached SDRAM memory */ + { 0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB }, /* None cached for 4G memory */ + { 0x20000000, 0x24000000-1, 0x20000000, RW_CB }, /* 64M cached SDRAM memory */ + { 0x00000000, 0x100000, 0x20000000, RW_CB }, /* isr vector table */ + { 0x90000000, 0x90400000-1, 0x00200000, RW_NCNB }, /* 4K SRAM0@2M + 4k SRAM1@3M + 16k UHP@5M */ + { 0xA0000000, 0xA4000000-1, 0x20000000, RW_NCNB } /* 64M none-cached SDRAM memory */ }; -#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV) -#define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20) +#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV) +#define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20) -static rt_uint32_t pit_cycle; /* write-once */ -static rt_uint32_t pit_cnt; /* access only w/system irq blocked */ +static rt_uint32_t pit_cycle; /* write-once */ +static rt_uint32_t pit_cnt; /* access only w/system irq blocked */ /** * This function will handle rtos timer */ void rt_timer_handler(int vector, void *param) { - #ifdef RT_USING_DBGU - if (at91_sys_read(AT91_DBGU + AT91_US_CSR) & 0x1) - { - rt_dbgu_isr(); - } - #endif - if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS) - { - unsigned nr_ticks; - - /* Get number of ticks performed before irq, and ack it */ - nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR)); - rt_tick_increase(); - } + #ifdef RT_USING_DBGU + if (at91_sys_read(AT91_DBGU + AT91_US_CSR) & 0x1) + { + rt_dbgu_isr(); + } + #endif + if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS) + { + unsigned nr_ticks; + + /* Get number of ticks performed before irq, and ack it */ + nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR)); + rt_tick_increase(); + } } static void at91sam926x_pit_reset(void) { - /* Disable timer and irqs */ - at91_sys_write(AT91_PIT_MR, 0); - - /* Clear any pending interrupts, wait for PIT to stop counting */ - while (PIT_CPIV(at91_sys_read(AT91_PIT_PIVR)) != 0) - ; - - /* Start PIT but don't enable IRQ */ - //at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN); - pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR)); - at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN - | AT91_PIT_PITIEN); - rt_kprintf("PIT_MR=0x%08x\n", at91_sys_read(AT91_PIT_MR)); + /* Disable timer and irqs */ + at91_sys_write(AT91_PIT_MR, 0); + + /* Clear any pending interrupts, wait for PIT to stop counting */ + while (PIT_CPIV(at91_sys_read(AT91_PIT_PIVR)) != 0) + ; + + /* Start PIT but don't enable IRQ */ + //at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN); + pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR)); + at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN + | AT91_PIT_PITIEN); + rt_kprintf("PIT_MR=0x%08x\n", at91_sys_read(AT91_PIT_MR)); } /* @@ -97,19 +97,19 @@ static void at91sam926x_pit_reset(void) */ static void at91sam926x_pit_init(void) { - rt_uint32_t pit_rate; - rt_uint32_t bits; + rt_uint32_t pit_rate; + rt_uint32_t bits; - /* - * Use our actual MCK to figure out how many MCK/16 ticks per - * 1/HZ period (instead of a compile-time constant LATCH). - */ - pit_rate = clk_get_rate(clk_get("mck")) / 16; - rt_kprintf("pit_rate=%dHZ\n", pit_rate); - pit_cycle = (pit_rate + RT_TICK_PER_SECOND/2) / RT_TICK_PER_SECOND; + /* + * Use our actual MCK to figure out how many MCK/16 ticks per + * 1/HZ period (instead of a compile-time constant LATCH). + */ + pit_rate = clk_get_rate(clk_get("mck")) / 16; + rt_kprintf("pit_rate=%dHZ\n", pit_rate); + pit_cycle = (pit_rate + RT_TICK_PER_SECOND/2) / RT_TICK_PER_SECOND; - /* Initialize and enable the timer */ - at91sam926x_pit_reset(); + /* Initialize and enable the timer */ + at91sam926x_pit_reset(); } @@ -118,69 +118,69 @@ static void at91sam926x_pit_init(void) */ void rt_hw_timer_init() { - at91sam926x_pit_init(); + at91sam926x_pit_init(); - /* install interrupt handler */ - rt_hw_interrupt_install(AT91_ID_SYS, rt_timer_handler, - RT_NULL, "system"); - rt_hw_interrupt_umask(AT91_ID_SYS); + /* install interrupt handler */ + rt_hw_interrupt_install(AT91_ID_SYS, rt_timer_handler, + RT_NULL, "system"); + rt_hw_interrupt_umask(AT91_ID_SYS); } - + void at91_tc1_init() { - at91_sys_write(AT91_PMC_PCER, 1<CSR & TXRDY)); - DBGU->THR = c; + DBGU->THR = c; } /** @@ -191,33 +191,33 @@ static void at91_usart_putc(char c) */ void rt_hw_console_output(const char* str) { - while (*str) - { - if (*str=='\n') - { - at91_usart_putc('\r'); - } - - at91_usart_putc(*str++); - } + while (*str) + { + if (*str=='\n') + { + at91_usart_putc('\r'); + } + + at91_usart_putc(*str++); + } } static void rt_hw_console_init(void) { - int div; - int mode = 0; - - DBGU->CR = AT91_US_RSTTX | AT91_US_RSTRX | - AT91_US_RXDIS | AT91_US_TXDIS; - mode |= AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK | - AT91_US_CHMODE_NORMAL; - mode |= AT91_US_CHRL_8; - mode |= AT91_US_NBSTOP_1; - mode |= AT91_US_PAR_NONE; - DBGU->MR = mode; - div = (clk_get_rate(clk_get("mck")) / 16 + BPS/2) / BPS; - DBGU->BRGR = div; - DBGU->CR = AT91_US_RXEN | AT91_US_TXEN; + int div; + int mode = 0; + + DBGU->CR = AT91_US_RSTTX | AT91_US_RSTRX | + AT91_US_RXDIS | AT91_US_TXDIS; + mode |= AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK | + AT91_US_CHMODE_NORMAL; + mode |= AT91_US_CHRL_8; + mode |= AT91_US_NBSTOP_1; + mode |= AT91_US_PAR_NONE; + DBGU->MR = mode; + div = (clk_get_rate(clk_get("mck")) / 16 + BPS/2) / BPS; + DBGU->BRGR = div; + DBGU->CR = AT91_US_RXEN | AT91_US_TXEN; } @@ -226,31 +226,31 @@ static void rt_hw_console_init(void) */ void rt_hw_board_init() { - /* initialize the system clock */ - rt_hw_clock_init(); + /* initialize the system clock */ + rt_hw_clock_init(); - /* initialize console */ - rt_hw_console_init(); + /* initialize console */ + rt_hw_console_init(); - /* initialize mmu */ - rt_hw_mmu_init(at91_mem_desc, sizeof(at91_mem_desc)/sizeof(at91_mem_desc[0])); + /* initialize mmu */ + rt_hw_mmu_init(at91_mem_desc, sizeof(at91_mem_desc)/sizeof(at91_mem_desc[0])); - /* initialize hardware interrupt */ - rt_hw_interrupt_init(); + /* initialize hardware interrupt */ + rt_hw_interrupt_init(); - /* initialize early device */ + /* initialize early device */ #ifdef RT_USING_COMPONENTS_INIT - rt_components_board_init(); + rt_components_board_init(); #endif #ifdef RT_USING_CONSOLE - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); #endif - /* initialize timer0 */ - rt_hw_timer_init(); + /* initialize timer0 */ + rt_hw_timer_init(); /* initialize board */ #ifdef RT_USING_HEAP - rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); #endif } diff --git a/bsp/at91sam9260/drivers/led.c b/bsp/at91sam9260/drivers/led.c index 8d56a99ffa..10277813d4 100644 --- a/bsp/at91sam9260/drivers/led.c +++ b/bsp/at91sam9260/drivers/led.c @@ -14,59 +14,59 @@ #if 1 // GB9260 board -#define PIO_LED AT91_PIOB -#define LED1 (1 << 25) // LED_SYS -#define LED2 (0) -#define LED3 (1 << 23) // LED_USR -#define LED_ALL (LED1 | LED2 | LED3) +#define PIO_LED AT91_PIOB +#define LED1 (1 << 25) // LED_SYS +#define LED2 (0) +#define LED3 (1 << 23) // LED_USR +#define LED_ALL (LED1 | LED2 | LED3) #else -#define PIO_LED AT91_PIOC -#define LED1 (1 << 8) -#define LED2 (1 << 11) -#define LED3 (1 << 6) -#define LED_ALL (LED1 | LED2 | LED3) +#define PIO_LED AT91_PIOC +#define LED1 (1 << 8) +#define LED2 (1 << 11) +#define LED3 (1 << 6) +#define LED_ALL (LED1 | LED2 | LED3) #endif void led_init(void) { - at91_sys_write(PIO_LED+0x00, LED_ALL); - at91_sys_write(PIO_LED+0x10, LED_ALL); - at91_sys_write(PIO_LED+0x64, LED_ALL); - at91_sys_write(PIO_LED+0x30, LED_ALL); + at91_sys_write(PIO_LED+0x00, LED_ALL); + at91_sys_write(PIO_LED+0x10, LED_ALL); + at91_sys_write(PIO_LED+0x64, LED_ALL); + at91_sys_write(PIO_LED+0x30, LED_ALL); } void led_on(int num) { - switch(num) - { - case 1: - at91_sys_write(PIO_LED+0x34, LED1); - break; - case 2: - at91_sys_write(PIO_LED+0x34, LED2); - break; - case 3: - at91_sys_write(PIO_LED+0x34, LED3); - break; - default: - break; - } + switch(num) + { + case 1: + at91_sys_write(PIO_LED+0x34, LED1); + break; + case 2: + at91_sys_write(PIO_LED+0x34, LED2); + break; + case 3: + at91_sys_write(PIO_LED+0x34, LED3); + break; + default: + break; + } } void led_off(int num) { - switch(num) - { - case 1: - at91_sys_write(PIO_LED+0x30, LED1); - break; - case 2: - at91_sys_write(PIO_LED+0x30, LED2); - break; - case 3: - at91_sys_write(PIO_LED+0x30, LED3); - break; - default: - break; - } + switch(num) + { + case 1: + at91_sys_write(PIO_LED+0x30, LED1); + break; + case 2: + at91_sys_write(PIO_LED+0x30, LED2); + break; + case 3: + at91_sys_write(PIO_LED+0x30, LED3); + break; + default: + break; + } } diff --git a/bsp/at91sam9260/drivers/macb.c b/bsp/at91sam9260/drivers/macb.c index 78fdfab902..702d7e04a4 100644 --- a/bsp/at91sam9260/drivers/macb.c +++ b/bsp/at91sam9260/drivers/macb.c @@ -14,7 +14,7 @@ #include #include "macb.h" -#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31)) +#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31)) extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size); extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); @@ -22,11 +22,11 @@ extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); /* Cache macros - Packet buffers would be from pbuf pool which is cached */ #define EMAC_VIRT_NOCACHE(addr) (addr) #define EMAC_CACHE_INVALIDATE(addr, size) \ - mmu_invalidate_dcache((rt_uint32_t)addr, size) + mmu_invalidate_dcache((rt_uint32_t)addr, size) #define EMAC_CACHE_WRITEBACK(addr, size) \ - mmu_clean_dcache((rt_uint32_t)addr, size) + mmu_clean_dcache((rt_uint32_t)addr, size) #define EMAC_CACHE_WRITEBACK_INVALIDATE(addr, size) \ - mmu_clean_invalidated_dcache((rt_uint32_t)addr, size) + mmu_clean_invalidated_dcache((rt_uint32_t)addr, size) /* EMAC has BD's in cached memory - so need cache functions */ #define BD_CACHE_INVALIDATE(addr, size) @@ -36,7 +36,7 @@ extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); /* EMAC internal utility function */ rt_inline unsigned long emac_virt_to_phys(unsigned long addr) { - return addr; + return addr; } @@ -45,112 +45,112 @@ rt_inline unsigned long emac_virt_to_phys(unsigned long addr) #define MACB_TX_SRAM #if defined(MACB_TX_SRAM) -#define MACB_TX_RING_SIZE 2 -#define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE) -#define TX_RING_BYTES (sizeof(struct macb_dma_desc) * MACB_TX_RING_SIZE) +#define MACB_TX_RING_SIZE 2 +#define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE) +#define TX_RING_BYTES (sizeof(struct macb_dma_desc) * MACB_TX_RING_SIZE) #else -#define MACB_TX_RING_SIZE 16 -#define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE) +#define MACB_TX_RING_SIZE 16 +#define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE) #endif -#define MACB_RX_BUFFER_SIZE (4096*4) -#define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128) +#define MACB_RX_BUFFER_SIZE (4096*4) +#define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128) -#define DEF_TX_RING_PENDING (MACB_TX_RING_SIZE) +#define DEF_TX_RING_PENDING (MACB_TX_RING_SIZE) -#define TX_RING_GAP(macb) \ - (MACB_TX_RING_SIZE - (macb)->tx_pending) +#define TX_RING_GAP(macb) \ + (MACB_TX_RING_SIZE - (macb)->tx_pending) -#define TX_BUFFS_AVAIL(macb) \ - (((macb)->tx_tail <= (macb)->tx_head) ? \ - (macb)->tx_tail + (macb)->tx_pending - (macb)->tx_head : \ - (macb)->tx_tail - (macb)->tx_head - TX_RING_GAP(macb)) +#define TX_BUFFS_AVAIL(macb) \ + (((macb)->tx_tail <= (macb)->tx_head) ? \ + (macb)->tx_tail + (macb)->tx_pending - (macb)->tx_head : \ + (macb)->tx_tail - (macb)->tx_head - TX_RING_GAP(macb)) -#define NEXT_TX(n) (((n) + 1) & (MACB_TX_RING_SIZE - 1)) +#define NEXT_TX(n) (((n) + 1) & (MACB_TX_RING_SIZE - 1)) -#define NEXT_RX(n) (((n) + 1) & (MACB_RX_RING_SIZE - 1)) +#define NEXT_RX(n) (((n) + 1) & (MACB_RX_RING_SIZE - 1)) /* minimum number of free TX descriptors before waking up TX process */ -#define MACB_TX_WAKEUP_THRESH (MACB_TX_RING_SIZE / 4) +#define MACB_TX_WAKEUP_THRESH (MACB_TX_RING_SIZE / 4) -#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \ - | MACB_BIT(ISR_ROVR)) +#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \ + | MACB_BIT(ISR_ROVR)) -#define MACB_TX_TIMEOUT 1000 -#define MACB_AUTONEG_TIMEOUT 5000000 -#define MACB_LINK_TIMEOUT 500000 +#define MACB_TX_TIMEOUT 1000 +#define MACB_AUTONEG_TIMEOUT 5000000 +#define MACB_LINK_TIMEOUT 500000 #define CONFIG_RMII struct macb_dma_desc { - rt_uint32_t addr; - rt_uint32_t ctrl; + rt_uint32_t addr; + rt_uint32_t ctrl; }; -#define RXADDR_USED 0x00000001 -#define RXADDR_WRAP 0x00000002 - -#define RXBUF_FRMLEN_MASK 0x00000fff -#define RXBUF_FRAME_START 0x00004000 -#define RXBUF_FRAME_END 0x00008000 -#define RXBUF_TYPEID_MATCH 0x00400000 -#define RXBUF_ADDR4_MATCH 0x00800000 -#define RXBUF_ADDR3_MATCH 0x01000000 -#define RXBUF_ADDR2_MATCH 0x02000000 -#define RXBUF_ADDR1_MATCH 0x04000000 -#define RXBUF_BROADCAST 0x80000000 - -#define TXBUF_FRMLEN_MASK 0x000007ff -#define TXBUF_FRAME_END 0x00008000 -#define TXBUF_NOCRC 0x00010000 -#define TXBUF_EXHAUSTED 0x08000000 -#define TXBUF_UNDERRUN 0x10000000 -#define TXBUF_MAXRETRY 0x20000000 -#define TXBUF_WRAP 0x40000000 -#define TXBUF_USED 0x80000000 +#define RXADDR_USED 0x00000001 +#define RXADDR_WRAP 0x00000002 + +#define RXBUF_FRMLEN_MASK 0x00000fff +#define RXBUF_FRAME_START 0x00004000 +#define RXBUF_FRAME_END 0x00008000 +#define RXBUF_TYPEID_MATCH 0x00400000 +#define RXBUF_ADDR4_MATCH 0x00800000 +#define RXBUF_ADDR3_MATCH 0x01000000 +#define RXBUF_ADDR2_MATCH 0x02000000 +#define RXBUF_ADDR1_MATCH 0x04000000 +#define RXBUF_BROADCAST 0x80000000 + +#define TXBUF_FRMLEN_MASK 0x000007ff +#define TXBUF_FRAME_END 0x00008000 +#define TXBUF_NOCRC 0x00010000 +#define TXBUF_EXHAUSTED 0x08000000 +#define TXBUF_UNDERRUN 0x10000000 +#define TXBUF_MAXRETRY 0x20000000 +#define TXBUF_WRAP 0x40000000 +#define TXBUF_USED 0x80000000 /* Duplex, half or full. */ -#define DUPLEX_HALF 0x00 -#define DUPLEX_FULL 0x01 +#define DUPLEX_HALF 0x00 +#define DUPLEX_FULL 0x01 #define MAX_ADDR_LEN 6 struct rt_macb_eth { - /* inherit from ethernet device */ - struct eth_device parent; - - unsigned int regs; - - unsigned int rx_tail; - unsigned int tx_head; - unsigned int tx_tail; - unsigned int rx_pending; - unsigned int tx_pending; - - void *rx_buffer; - void *tx_buffer; - struct macb_dma_desc *rx_ring; - struct macb_dma_desc *tx_ring; - - unsigned long rx_buffer_dma; - unsigned long tx_buffer_dma; - unsigned long rx_ring_dma; - unsigned long tx_ring_dma; - - unsigned int tx_stop; - - /* interface address info. */ - rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ - unsigned short phy_addr; - - struct rt_semaphore mdio_bus_lock; - struct rt_semaphore tx_lock; - struct rt_semaphore rx_lock; - struct rt_semaphore tx_ack; - rt_uint32_t speed; - rt_uint32_t duplex; - rt_uint32_t link; - struct rt_timer timer; + /* inherit from ethernet device */ + struct eth_device parent; + + unsigned int regs; + + unsigned int rx_tail; + unsigned int tx_head; + unsigned int tx_tail; + unsigned int rx_pending; + unsigned int tx_pending; + + void *rx_buffer; + void *tx_buffer; + struct macb_dma_desc *rx_ring; + struct macb_dma_desc *tx_ring; + + unsigned long rx_buffer_dma; + unsigned long tx_buffer_dma; + unsigned long rx_ring_dma; + unsigned long tx_ring_dma; + + unsigned int tx_stop; + + /* interface address info. */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ + unsigned short phy_addr; + + struct rt_semaphore mdio_bus_lock; + struct rt_semaphore tx_lock; + struct rt_semaphore rx_lock; + struct rt_semaphore tx_ack; + rt_uint32_t speed; + rt_uint32_t duplex; + rt_uint32_t link; + struct rt_timer timer; }; static struct rt_macb_eth macb_device; @@ -165,253 +165,253 @@ static void udelay(rt_uint32_t us) static void rt_macb_isr(int irq, void *param) { - struct rt_macb_eth *macb = (struct rt_macb_eth *)param; - rt_device_t dev = &(macb->parent.parent); - rt_uint32_t status, rsr, tsr; - - status = macb_readl(macb, ISR); - - while (status) { - - if (status & MACB_RX_INT_FLAGS) - { - rsr = macb_readl(macb, RSR); - macb_writel(macb, RSR, rsr); - /* a frame has been received */ - eth_device_ready(&(macb_device.parent)); - - } - - if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) | - MACB_BIT(ISR_RLE))) - { - macb_tx(macb); - } - - /* - * Link change detection isn't possible with RMII, so we'll - * add that if/when we get our hands on a full-blown MII PHY. - */ - - if (status & MACB_BIT(HRESP)) - { - /* - * TODO: Reset the hardware, and maybe move the printk - * to a lower-priority context as well (work queue?) - */ - rt_kprintf("%s: DMA bus error: HRESP not OK\n", - dev->parent.name); - } - - status = macb_readl(macb, ISR); - } + struct rt_macb_eth *macb = (struct rt_macb_eth *)param; + rt_device_t dev = &(macb->parent.parent); + rt_uint32_t status, rsr, tsr; + + status = macb_readl(macb, ISR); + + while (status) { + + if (status & MACB_RX_INT_FLAGS) + { + rsr = macb_readl(macb, RSR); + macb_writel(macb, RSR, rsr); + /* a frame has been received */ + eth_device_ready(&(macb_device.parent)); + + } + + if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) | + MACB_BIT(ISR_RLE))) + { + macb_tx(macb); + } + + /* + * Link change detection isn't possible with RMII, so we'll + * add that if/when we get our hands on a full-blown MII PHY. + */ + + if (status & MACB_BIT(HRESP)) + { + /* + * TODO: Reset the hardware, and maybe move the printk + * to a lower-priority context as well (work queue?) + */ + rt_kprintf("%s: DMA bus error: HRESP not OK\n", + dev->parent.name); + } + + status = macb_readl(macb, ISR); + } } static int macb_mdio_write(struct rt_macb_eth *macb, rt_uint8_t reg, rt_uint16_t value) { - unsigned long netctl; - unsigned long netstat; - unsigned long frame; - - rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER); - netctl = macb_readl(macb, NCR); - netctl |= MACB_BIT(MPE); - macb_writel(macb, NCR, netctl); - - frame = (MACB_BF(SOF, 1) - | MACB_BF(RW, 1) - | MACB_BF(PHYA, macb->phy_addr) - | MACB_BF(REGA, reg) - | MACB_BF(CODE, 2) - | MACB_BF(DATA, value)); - macb_writel(macb, MAN, frame); - - do { - netstat = macb_readl(macb, NSR); - } while (!(netstat & MACB_BIT(IDLE))); - - netctl = macb_readl(macb, NCR); - netctl &= ~MACB_BIT(MPE); - macb_writel(macb, NCR, netctl); - rt_sem_release(&macb->mdio_bus_lock); + unsigned long netctl; + unsigned long netstat; + unsigned long frame; + + rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER); + netctl = macb_readl(macb, NCR); + netctl |= MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); + + frame = (MACB_BF(SOF, 1) + | MACB_BF(RW, 1) + | MACB_BF(PHYA, macb->phy_addr) + | MACB_BF(REGA, reg) + | MACB_BF(CODE, 2) + | MACB_BF(DATA, value)); + macb_writel(macb, MAN, frame); + + do { + netstat = macb_readl(macb, NSR); + } while (!(netstat & MACB_BIT(IDLE))); + + netctl = macb_readl(macb, NCR); + netctl &= ~MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); + rt_sem_release(&macb->mdio_bus_lock); } static int macb_mdio_read(struct rt_macb_eth *macb, rt_uint8_t reg) { - unsigned long netctl; - unsigned long netstat; - unsigned long frame; - - rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER); - netctl = macb_readl(macb, NCR); - netctl |= MACB_BIT(MPE); - macb_writel(macb, NCR, netctl); - - frame = (MACB_BF(SOF, 1) - | MACB_BF(RW, 2) - | MACB_BF(PHYA, macb->phy_addr) - | MACB_BF(REGA, reg) - | MACB_BF(CODE, 2)); - macb_writel(macb, MAN, frame); - - do { - netstat = macb_readl(macb, NSR); - } while (!(netstat & MACB_BIT(IDLE))); - - frame = macb_readl(macb, MAN); - - netctl = macb_readl(macb, NCR); - netctl &= ~MACB_BIT(MPE); - macb_writel(macb, NCR, netctl); - rt_sem_release(&macb->mdio_bus_lock); - - return MACB_BFEXT(DATA, frame); + unsigned long netctl; + unsigned long netstat; + unsigned long frame; + + rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER); + netctl = macb_readl(macb, NCR); + netctl |= MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); + + frame = (MACB_BF(SOF, 1) + | MACB_BF(RW, 2) + | MACB_BF(PHYA, macb->phy_addr) + | MACB_BF(REGA, reg) + | MACB_BF(CODE, 2)); + macb_writel(macb, MAN, frame); + + do { + netstat = macb_readl(macb, NSR); + } while (!(netstat & MACB_BIT(IDLE))); + + frame = macb_readl(macb, MAN); + + netctl = macb_readl(macb, NCR); + netctl &= ~MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); + rt_sem_release(&macb->mdio_bus_lock); + + return MACB_BFEXT(DATA, frame); } static void macb_phy_reset(rt_device_t dev) { - int i; - rt_uint16_t status, adv; - struct rt_macb_eth *macb = dev->user_data;; - - adv = ADVERTISE_CSMA | ADVERTISE_ALL; - macb_mdio_write(macb, MII_ADVERTISE, adv); - rt_kprintf("%s: Starting autonegotiation...\n", dev->parent.name); - macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE - | BMCR_ANRESTART)); - - for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) - { - status = macb_mdio_read(macb, MII_BMSR); - if (status & BMSR_ANEGCOMPLETE) - break; - udelay(100); - } - - if (status & BMSR_ANEGCOMPLETE) - rt_kprintf("%s: Autonegotiation complete\n", dev->parent.name); - else - rt_kprintf("%s: Autonegotiation timed out (status=0x%04x)\n", - dev->parent.name, status); + int i; + rt_uint16_t status, adv; + struct rt_macb_eth *macb = dev->user_data;; + + adv = ADVERTISE_CSMA | ADVERTISE_ALL; + macb_mdio_write(macb, MII_ADVERTISE, adv); + rt_kprintf("%s: Starting autonegotiation...\n", dev->parent.name); + macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE + | BMCR_ANRESTART)); + + for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) + { + status = macb_mdio_read(macb, MII_BMSR); + if (status & BMSR_ANEGCOMPLETE) + break; + udelay(100); + } + + if (status & BMSR_ANEGCOMPLETE) + rt_kprintf("%s: Autonegotiation complete\n", dev->parent.name); + else + rt_kprintf("%s: Autonegotiation timed out (status=0x%04x)\n", + dev->parent.name, status); } static int macb_phy_init(rt_device_t dev) { - struct rt_macb_eth *macb = dev->user_data; - rt_uint32_t ncfgr; - rt_uint16_t phy_id, status, adv, lpa; - int media, speed, duplex; - int i; - - /* Check if the PHY is up to snuff... */ - phy_id = macb_mdio_read(macb, MII_PHYSID1); - if (phy_id == 0xffff) - { - rt_kprintf("%s: No PHY present\n", dev->parent.name); - return 0; - } - - status = macb_mdio_read(macb, MII_BMSR); - if (!(status & BMSR_LSTATUS)) - { - /* Try to re-negotiate if we don't have link already. */ - macb_phy_reset(dev); - - for (i = 0; i < MACB_LINK_TIMEOUT / 100; i++) - { - status = macb_mdio_read(macb, MII_BMSR); - if (status & BMSR_LSTATUS) - break; - udelay(100); - } - } - - if (!(status & BMSR_LSTATUS)) - { - rt_kprintf("%s: link down (status: 0x%04x)\n", - dev->parent.name, status); - return 0; - } - else - { - adv = macb_mdio_read(macb, MII_ADVERTISE); - lpa = macb_mdio_read(macb, MII_LPA); - media = mii_nway_result(lpa & adv); - speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) - ? 1 : 0); - duplex = (media & ADVERTISE_FULL) ? 1 : 0; - rt_kprintf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n", - dev->parent.name, - speed ? "100" : "10", - duplex ? "full" : "half", - lpa); - - ncfgr = macb_readl(macb, NCFGR); - ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); - if (speed) - ncfgr |= MACB_BIT(SPD); - if (duplex) - ncfgr |= MACB_BIT(FD); - macb_writel(macb, NCFGR, ncfgr); - return 1; - } + struct rt_macb_eth *macb = dev->user_data; + rt_uint32_t ncfgr; + rt_uint16_t phy_id, status, adv, lpa; + int media, speed, duplex; + int i; + + /* Check if the PHY is up to snuff... */ + phy_id = macb_mdio_read(macb, MII_PHYSID1); + if (phy_id == 0xffff) + { + rt_kprintf("%s: No PHY present\n", dev->parent.name); + return 0; + } + + status = macb_mdio_read(macb, MII_BMSR); + if (!(status & BMSR_LSTATUS)) + { + /* Try to re-negotiate if we don't have link already. */ + macb_phy_reset(dev); + + for (i = 0; i < MACB_LINK_TIMEOUT / 100; i++) + { + status = macb_mdio_read(macb, MII_BMSR); + if (status & BMSR_LSTATUS) + break; + udelay(100); + } + } + + if (!(status & BMSR_LSTATUS)) + { + rt_kprintf("%s: link down (status: 0x%04x)\n", + dev->parent.name, status); + return 0; + } + else + { + adv = macb_mdio_read(macb, MII_ADVERTISE); + lpa = macb_mdio_read(macb, MII_LPA); + media = mii_nway_result(lpa & adv); + speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) + ? 1 : 0); + duplex = (media & ADVERTISE_FULL) ? 1 : 0; + rt_kprintf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n", + dev->parent.name, + speed ? "100" : "10", + duplex ? "full" : "half", + lpa); + + ncfgr = macb_readl(macb, NCFGR); + ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); + if (speed) + ncfgr |= MACB_BIT(SPD); + if (duplex) + ncfgr |= MACB_BIT(FD); + macb_writel(macb, NCFGR, ncfgr); + return 1; + } } void macb_update_link(void *param) { - struct rt_macb_eth *macb = (struct rt_macb_eth *)param; - rt_device_t dev = &macb->parent.parent; - int status, status_change = 0; - rt_uint32_t link; - rt_uint32_t media; - rt_uint16_t adv, lpa; - - /* Do a fake read */ - status = macb_mdio_read(macb, MII_BMSR); - if (status < 0) - return; - - /* Read link and autonegotiation status */ - status = macb_mdio_read(macb, MII_BMSR); - if (status < 0) - return; - - if ((status & BMSR_LSTATUS) == 0) - link = 0; - else - link = 1; - - if (link != macb->link) - { - macb->link = link; - status_change = 1; - } - - if (status_change) - { - if (macb->link) - { - adv = macb_mdio_read(macb, MII_ADVERTISE); - lpa = macb_mdio_read(macb, MII_LPA); - media = mii_nway_result(lpa & adv); - macb->speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) - ? 100 : 10); - macb->duplex = (media & ADVERTISE_FULL) ? 1 : 0; - rt_kprintf("%s: link up (%dMbps/%s-duplex)\n", - dev->parent.name, macb->speed, - DUPLEX_FULL == macb->duplex ? "Full":"Half"); - eth_device_linkchange(&macb->parent, RT_TRUE); - } - else - { - rt_kprintf("%s: link down\n", dev->parent.name); - eth_device_linkchange(&macb->parent, RT_FALSE); - } - - } + struct rt_macb_eth *macb = (struct rt_macb_eth *)param; + rt_device_t dev = &macb->parent.parent; + int status, status_change = 0; + rt_uint32_t link; + rt_uint32_t media; + rt_uint16_t adv, lpa; + + /* Do a fake read */ + status = macb_mdio_read(macb, MII_BMSR); + if (status < 0) + return; + + /* Read link and autonegotiation status */ + status = macb_mdio_read(macb, MII_BMSR); + if (status < 0) + return; + + if ((status & BMSR_LSTATUS) == 0) + link = 0; + else + link = 1; + + if (link != macb->link) + { + macb->link = link; + status_change = 1; + } + + if (status_change) + { + if (macb->link) + { + adv = macb_mdio_read(macb, MII_ADVERTISE); + lpa = macb_mdio_read(macb, MII_LPA); + media = mii_nway_result(lpa & adv); + macb->speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) + ? 100 : 10); + macb->duplex = (media & ADVERTISE_FULL) ? 1 : 0; + rt_kprintf("%s: link up (%dMbps/%s-duplex)\n", + dev->parent.name, macb->speed, + DUPLEX_FULL == macb->duplex ? "Full":"Half"); + eth_device_linkchange(&macb->parent, RT_TRUE); + } + else + { + rt_kprintf("%s: link down\n", dev->parent.name); + eth_device_linkchange(&macb->parent, RT_FALSE); + } + + } } @@ -420,190 +420,190 @@ void macb_update_link(void *param) static rt_err_t rt_macb_init(rt_device_t dev) { - struct rt_macb_eth *macb = dev->user_data; - unsigned long paddr; - rt_uint32_t hwaddr_bottom; - rt_uint16_t hwaddr_top; - int i; - - /* - * macb_halt should have been called at some point before now, - * so we'll assume the controller is idle. - */ - - /* initialize DMA descriptors */ - paddr = macb->rx_buffer_dma; - for (i = 0; i < MACB_RX_RING_SIZE; i++) - { - if (i == (MACB_RX_RING_SIZE - 1)) - paddr |= RXADDR_WRAP; - macb->rx_ring[i].addr = paddr; - macb->rx_ring[i].ctrl = 0; - paddr += 128; - } - paddr = macb->tx_buffer_dma; - for (i = 0; i < MACB_TX_RING_SIZE; i++) - { - macb->tx_ring[i].addr = paddr; - if (i == (MACB_TX_RING_SIZE - 1)) - macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP; - else - macb->tx_ring[i].ctrl = TXBUF_USED; - paddr += 1536; - } - macb->rx_tail = macb->tx_head = macb->tx_tail = 0; - - BD_CACHE_WRITEBACK_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); - BD_CACHE_WRITEBACK_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc)); - macb_writel(macb, RBQP, macb->rx_ring_dma); - macb_writel(macb, TBQP, macb->tx_ring_dma); - - /* set hardware address */ - hwaddr_bottom = (*((rt_uint32_t *)macb->dev_addr)); - macb_writel(macb, SA1B, hwaddr_bottom); - hwaddr_top = (*((rt_uint16_t *)(macb->dev_addr + 4))); - macb_writel(macb, SA1T, hwaddr_top); - - - /* choose RMII or MII mode. This depends on the board */ + struct rt_macb_eth *macb = dev->user_data; + unsigned long paddr; + rt_uint32_t hwaddr_bottom; + rt_uint16_t hwaddr_top; + int i; + + /* + * macb_halt should have been called at some point before now, + * so we'll assume the controller is idle. + */ + + /* initialize DMA descriptors */ + paddr = macb->rx_buffer_dma; + for (i = 0; i < MACB_RX_RING_SIZE; i++) + { + if (i == (MACB_RX_RING_SIZE - 1)) + paddr |= RXADDR_WRAP; + macb->rx_ring[i].addr = paddr; + macb->rx_ring[i].ctrl = 0; + paddr += 128; + } + paddr = macb->tx_buffer_dma; + for (i = 0; i < MACB_TX_RING_SIZE; i++) + { + macb->tx_ring[i].addr = paddr; + if (i == (MACB_TX_RING_SIZE - 1)) + macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP; + else + macb->tx_ring[i].ctrl = TXBUF_USED; + paddr += 1536; + } + macb->rx_tail = macb->tx_head = macb->tx_tail = 0; + + BD_CACHE_WRITEBACK_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); + BD_CACHE_WRITEBACK_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc)); + macb_writel(macb, RBQP, macb->rx_ring_dma); + macb_writel(macb, TBQP, macb->tx_ring_dma); + + /* set hardware address */ + hwaddr_bottom = (*((rt_uint32_t *)macb->dev_addr)); + macb_writel(macb, SA1B, hwaddr_bottom); + hwaddr_top = (*((rt_uint16_t *)(macb->dev_addr + 4))); + macb_writel(macb, SA1T, hwaddr_top); + + + /* choose RMII or MII mode. This depends on the board */ #ifdef CONFIG_RMII - macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN)); + macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN)); #else - macb_writel(macb, USRIO, MACB_BIT(CLKEN)); + macb_writel(macb, USRIO, MACB_BIT(CLKEN)); #endif /* CONFIG_RMII */ - if (!macb_phy_init(dev)) - return -RT_ERROR; - - /* Enable TX and RX */ - macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(MPE)); - - /* Enable interrupts */ - macb_writel(macb, IER, (MACB_BIT(RCOMP) - | MACB_BIT(RXUBR) - | MACB_BIT(ISR_TUND) - | MACB_BIT(ISR_RLE) - | MACB_BIT(TXERR) - | MACB_BIT(TCOMP) - | MACB_BIT(ISR_ROVR) - | MACB_BIT(HRESP))); - - /* instal interrupt */ - rt_hw_interrupt_install(AT91SAM9260_ID_EMAC, rt_macb_isr, - (void *)macb, "emac"); - rt_hw_interrupt_umask(AT91SAM9260_ID_EMAC); - - rt_timer_init(&macb->timer, "link_timer", - macb_update_link, - (void *)macb, - RT_TICK_PER_SECOND, - RT_TIMER_FLAG_PERIODIC); - - rt_timer_start(&macb->timer); - - return RT_EOK; + if (!macb_phy_init(dev)) + return -RT_ERROR; + + /* Enable TX and RX */ + macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(MPE)); + + /* Enable interrupts */ + macb_writel(macb, IER, (MACB_BIT(RCOMP) + | MACB_BIT(RXUBR) + | MACB_BIT(ISR_TUND) + | MACB_BIT(ISR_RLE) + | MACB_BIT(TXERR) + | MACB_BIT(TCOMP) + | MACB_BIT(ISR_ROVR) + | MACB_BIT(HRESP))); + + /* instal interrupt */ + rt_hw_interrupt_install(AT91SAM9260_ID_EMAC, rt_macb_isr, + (void *)macb, "emac"); + rt_hw_interrupt_umask(AT91SAM9260_ID_EMAC); + + rt_timer_init(&macb->timer, "link_timer", + macb_update_link, + (void *)macb, + RT_TICK_PER_SECOND, + RT_TIMER_FLAG_PERIODIC); + + rt_timer_start(&macb->timer); + + return RT_EOK; } static rt_err_t rt_macb_open(rt_device_t dev, rt_uint16_t oflag) { - return RT_EOK; + return RT_EOK; } static rt_err_t rt_macb_close(rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_size_t rt_macb_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_size_t rt_macb_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_err_t rt_macb_control(rt_device_t dev, int cmd, void *args) { - switch(cmd) - { - case NIOCTL_GADDR: - /* get mac address */ - if(args) rt_memcpy(args, macb_device.dev_addr, 6); - else return -RT_ERROR; - break; - - default : - break; - } - - return RT_EOK; + switch(cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if(args) rt_memcpy(args, macb_device.dev_addr, 6); + else return -RT_ERROR; + break; + + default : + break; + } + + return RT_EOK; } static void macb_tx(struct rt_macb_eth *macb) { - unsigned int tail; - unsigned int head; - rt_uint32_t status; + unsigned int tail; + unsigned int head; + rt_uint32_t status; - status = macb_readl(macb, TSR); - macb_writel(macb, TSR, status); + status = macb_readl(macb, TSR); + macb_writel(macb, TSR, status); - /*rt_kprintf("macb_tx status = %02lx\n", - (unsigned long)status);*/ + /*rt_kprintf("macb_tx status = %02lx\n", + (unsigned long)status);*/ - if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE))) - { - int i; - rt_kprintf("%s: TX %s, resetting buffers\n", - macb->parent.parent.parent.name, status & MACB_BIT(UND) ? - "underrun" : "retry limit exceeded"); + if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE))) + { + int i; + rt_kprintf("%s: TX %s, resetting buffers\n", + macb->parent.parent.parent.name, status & MACB_BIT(UND) ? + "underrun" : "retry limit exceeded"); - /* Transfer ongoing, disable transmitter, to avoid confusion */ - if (status & MACB_BIT(TGO)) - macb_writel(macb, NCR, macb_readl(macb, NCR) & ~MACB_BIT(TE)); + /* Transfer ongoing, disable transmitter, to avoid confusion */ + if (status & MACB_BIT(TGO)) + macb_writel(macb, NCR, macb_readl(macb, NCR) & ~MACB_BIT(TE)); - head = macb->tx_head; + head = macb->tx_head; - /*Mark all the buffer as used to avoid sending a lost buffer*/ - for (i = 0; i < MACB_TX_RING_SIZE; i++) - macb->tx_ring[i].ctrl = MACB_BIT(TX_USED); + /*Mark all the buffer as used to avoid sending a lost buffer*/ + for (i = 0; i < MACB_TX_RING_SIZE; i++) + macb->tx_ring[i].ctrl = MACB_BIT(TX_USED); - /* free transmit buffer in upper layer*/ + /* free transmit buffer in upper layer*/ - macb->tx_head = macb->tx_tail = 0; + macb->tx_head = macb->tx_tail = 0; - /* Enable the transmitter again */ - if (status & MACB_BIT(TGO)) - macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TE)); - } + /* Enable the transmitter again */ + if (status & MACB_BIT(TGO)) + macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TE)); + } - if (!(status & MACB_BIT(COMP))) - /* - * This may happen when a buffer becomes complete - * between reading the ISR and scanning the - * descriptors. Nothing to worry about. - */ - return; + if (!(status & MACB_BIT(COMP))) + /* + * This may happen when a buffer becomes complete + * between reading the ISR and scanning the + * descriptors. Nothing to worry about. + */ + return; - head = macb->tx_head; - for (tail = macb->tx_tail; tail != head; tail = NEXT_TX(tail)) - { - rt_uint32_t bufstat; + head = macb->tx_head; + for (tail = macb->tx_tail; tail != head; tail = NEXT_TX(tail)) + { + rt_uint32_t bufstat; - bufstat = macb->tx_ring[tail].ctrl; + bufstat = macb->tx_ring[tail].ctrl; - if (!(bufstat & MACB_BIT(TX_USED))) - break; - } + if (!(bufstat & MACB_BIT(TX_USED))) + break; + } - macb->tx_tail = tail; - if ((macb->tx_stop == 1) && - TX_BUFFS_AVAIL(macb) > MACB_TX_WAKEUP_THRESH) - rt_sem_release(&macb->tx_ack); + macb->tx_tail = tail; + if ((macb->tx_stop == 1) && + TX_BUFFS_AVAIL(macb) > MACB_TX_WAKEUP_THRESH) + rt_sem_release(&macb->tx_ack); } @@ -611,286 +611,286 @@ static void macb_tx(struct rt_macb_eth *macb) /* transmit packet. */ rt_err_t rt_macb_tx( rt_device_t dev, struct pbuf* p) { - unsigned long ctrl; - struct pbuf* q; - rt_uint8_t* bufptr; - rt_uint32_t mapping; - struct rt_macb_eth *macb = dev->user_data; - unsigned int tx_head = macb->tx_head; - - rt_sem_take(&macb->tx_lock, RT_WAITING_FOREVER); - if (TX_BUFFS_AVAIL(macb) < 1) - { - rt_sem_release(&macb->tx_lock); - rt_kprintf("Tx Ring full!\n"); - rt_kprintf("tx_head = %u, tx_tail = %u\n", - macb->tx_head, macb->tx_tail); - return -RT_ERROR; - } - - macb->tx_stop = 0; - - ctrl = p->tot_len & TXBUF_FRMLEN_MASK; - ctrl |= TXBUF_FRAME_END; - if (tx_head == (MACB_TX_RING_SIZE - 1)) - { - ctrl |= TXBUF_WRAP; - } + unsigned long ctrl; + struct pbuf* q; + rt_uint8_t* bufptr; + rt_uint32_t mapping; + struct rt_macb_eth *macb = dev->user_data; + unsigned int tx_head = macb->tx_head; + + rt_sem_take(&macb->tx_lock, RT_WAITING_FOREVER); + if (TX_BUFFS_AVAIL(macb) < 1) + { + rt_sem_release(&macb->tx_lock); + rt_kprintf("Tx Ring full!\n"); + rt_kprintf("tx_head = %u, tx_tail = %u\n", + macb->tx_head, macb->tx_tail); + return -RT_ERROR; + } + + macb->tx_stop = 0; + + ctrl = p->tot_len & TXBUF_FRMLEN_MASK; + ctrl |= TXBUF_FRAME_END; + if (tx_head == (MACB_TX_RING_SIZE - 1)) + { + ctrl |= TXBUF_WRAP; + } #if defined(MACB_TX_SRAM) - bufptr = macb->tx_buffer + tx_head * 1536; + bufptr = macb->tx_buffer + tx_head * 1536; #else - mapping = (unsigned long)macb->tx_buffer + tx_head * 1536; - bufptr = (rt_uint8_t *)mapping; + mapping = (unsigned long)macb->tx_buffer + tx_head * 1536; + bufptr = (rt_uint8_t *)mapping; #endif - for (q = p; q != NULL; q = q->next) - { - memcpy(bufptr, q->payload, q->len); - bufptr += q->len; - } + for (q = p; q != NULL; q = q->next) + { + memcpy(bufptr, q->payload, q->len); + bufptr += q->len; + } #if !defined(MACB_TX_SRAM) - EMAC_CACHE_WRITEBACK(mapping, p->tot_len); + EMAC_CACHE_WRITEBACK(mapping, p->tot_len); #endif - macb->tx_ring[tx_head].ctrl = ctrl; - BD_CACHE_WRITEBACK_INVALIDATE(&macb->tx_ring[tx_head], sizeof(struct macb_dma_desc)); - tx_head = NEXT_TX(tx_head); - macb->tx_head = tx_head; - macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART)); - macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART)); - - if (TX_BUFFS_AVAIL(macb) < 1) - { - macb->tx_stop = 1; - rt_sem_take(&macb->tx_ack, RT_WAITING_FOREVER); - } - rt_sem_release(&macb->tx_lock); - - return RT_EOK; + macb->tx_ring[tx_head].ctrl = ctrl; + BD_CACHE_WRITEBACK_INVALIDATE(&macb->tx_ring[tx_head], sizeof(struct macb_dma_desc)); + tx_head = NEXT_TX(tx_head); + macb->tx_head = tx_head; + macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART)); + macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART)); + + if (TX_BUFFS_AVAIL(macb) < 1) + { + macb->tx_stop = 1; + rt_sem_take(&macb->tx_ack, RT_WAITING_FOREVER); + } + rt_sem_release(&macb->tx_lock); + + return RT_EOK; } static void reclaim_rx_buffers(struct rt_macb_eth *macb, - unsigned int new_tail) + unsigned int new_tail) { - unsigned int i; - - i = macb->rx_tail; - while (i > new_tail) - { - macb->rx_ring[i].addr &= ~RXADDR_USED; - i++; - if (i > MACB_RX_RING_SIZE) - i = 0; - } - - while (i < new_tail) - { - macb->rx_ring[i].addr &= ~RXADDR_USED; - i++; - } - - macb->rx_tail = new_tail; + unsigned int i; + + i = macb->rx_tail; + while (i > new_tail) + { + macb->rx_ring[i].addr &= ~RXADDR_USED; + i++; + if (i > MACB_RX_RING_SIZE) + i = 0; + } + + while (i < new_tail) + { + macb->rx_ring[i].addr &= ~RXADDR_USED; + i++; + } + + macb->rx_tail = new_tail; } /* reception packet. */ struct pbuf *rt_macb_rx(rt_device_t dev) { - struct rt_macb_eth *macb = dev->user_data; - struct pbuf* p = RT_NULL; - rt_uint32_t len; - unsigned int rx_tail = macb->rx_tail; - void *buffer; - int wrapped = 0; - rt_uint32_t status; - - rt_sem_take(&macb->rx_lock, RT_WAITING_FOREVER); - for (;;) - { - if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED)) - break; - - status = macb->rx_ring[rx_tail].ctrl; - if (status & RXBUF_FRAME_START) - { - if (rx_tail != macb->rx_tail) - reclaim_rx_buffers(macb, rx_tail); - wrapped = 0; - } - - if (status & RXBUF_FRAME_END) - { - buffer = (void *)((unsigned int)macb->rx_buffer + 128 * macb->rx_tail); - len = status & RXBUF_FRMLEN_MASK; - p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM); - if (!p) - { - rt_kprintf("alloc pbuf failed\n"); - break; - } - if (wrapped) - { - unsigned int headlen, taillen; - - headlen = 128 * (MACB_RX_RING_SIZE - - macb->rx_tail); - taillen = len - headlen; - EMAC_CACHE_INVALIDATE(buffer, headlen); - EMAC_CACHE_INVALIDATE(macb->rx_buffer, taillen); - memcpy((void *)p->payload, buffer, headlen); - memcpy((void *)((unsigned int)p->payload + headlen), - macb->rx_buffer, taillen); - } - else - { - EMAC_CACHE_INVALIDATE(buffer, len); - memcpy((void *)p->payload, buffer, p->len); - } - - if (++rx_tail >= MACB_RX_RING_SIZE) - rx_tail = 0; - reclaim_rx_buffers(macb, rx_tail); - break; - } - else - { - if (++rx_tail >= MACB_RX_RING_SIZE) - { - wrapped = 1; - rx_tail = 0; - } - } - } - - rt_sem_release(&macb->rx_lock); - - return p; + struct rt_macb_eth *macb = dev->user_data; + struct pbuf* p = RT_NULL; + rt_uint32_t len; + unsigned int rx_tail = macb->rx_tail; + void *buffer; + int wrapped = 0; + rt_uint32_t status; + + rt_sem_take(&macb->rx_lock, RT_WAITING_FOREVER); + for (;;) + { + if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED)) + break; + + status = macb->rx_ring[rx_tail].ctrl; + if (status & RXBUF_FRAME_START) + { + if (rx_tail != macb->rx_tail) + reclaim_rx_buffers(macb, rx_tail); + wrapped = 0; + } + + if (status & RXBUF_FRAME_END) + { + buffer = (void *)((unsigned int)macb->rx_buffer + 128 * macb->rx_tail); + len = status & RXBUF_FRMLEN_MASK; + p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM); + if (!p) + { + rt_kprintf("alloc pbuf failed\n"); + break; + } + if (wrapped) + { + unsigned int headlen, taillen; + + headlen = 128 * (MACB_RX_RING_SIZE + - macb->rx_tail); + taillen = len - headlen; + EMAC_CACHE_INVALIDATE(buffer, headlen); + EMAC_CACHE_INVALIDATE(macb->rx_buffer, taillen); + memcpy((void *)p->payload, buffer, headlen); + memcpy((void *)((unsigned int)p->payload + headlen), + macb->rx_buffer, taillen); + } + else + { + EMAC_CACHE_INVALIDATE(buffer, len); + memcpy((void *)p->payload, buffer, p->len); + } + + if (++rx_tail >= MACB_RX_RING_SIZE) + rx_tail = 0; + reclaim_rx_buffers(macb, rx_tail); + break; + } + else + { + if (++rx_tail >= MACB_RX_RING_SIZE) + { + wrapped = 1; + rx_tail = 0; + } + } + } + + rt_sem_release(&macb->rx_lock); + + return p; } void macb_gpio_init() { - /* Pins used for MII and RMII */ - at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20)); - at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20)); + /* Pins used for MII and RMII */ + at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20)); + at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20)); #ifndef GONFIG_RMII - at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29)); - at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29)); + at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29)); + at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29)); #endif } rt_err_t macb_initialize() { - struct rt_macb_eth *macb = &macb_device; - unsigned long macb_hz; - rt_uint32_t ncfgr; - + struct rt_macb_eth *macb = &macb_device; + unsigned long macb_hz; + rt_uint32_t ncfgr; + #if defined(MACB_TX_SRAM) - macb->tx_ring_dma = AT91SAM9260_SRAM0_BASE; - macb->tx_ring = (struct macb_dma_desc *)AT91SAM9260_SRAM0_VIRT_BASE; - macb->tx_buffer = (char *) macb->tx_ring + TX_RING_BYTES; - macb->tx_buffer_dma = macb->tx_ring_dma + TX_RING_BYTES; + macb->tx_ring_dma = AT91SAM9260_SRAM0_BASE; + macb->tx_ring = (struct macb_dma_desc *)AT91SAM9260_SRAM0_VIRT_BASE; + macb->tx_buffer = (char *) macb->tx_ring + TX_RING_BYTES; + macb->tx_buffer_dma = macb->tx_ring_dma + TX_RING_BYTES; #else - macb->tx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); - if (macb->tx_ring == RT_NULL) - goto err1; - EMAC_CACHE_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc)); - macb->tx_ring_dma = emac_virt_to_phys((unsigned long)macb->tx_ring); - macb->tx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->tx_ring); - macb->tx_buffer = rt_malloc(MACB_TX_BUFFER_SIZE); - if (macb->tx_buffer == RT_NULL) - goto err2; - macb->tx_buffer_dma = emac_virt_to_phys((unsigned long)macb->tx_buffer); + macb->tx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); + if (macb->tx_ring == RT_NULL) + goto err1; + EMAC_CACHE_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc)); + macb->tx_ring_dma = emac_virt_to_phys((unsigned long)macb->tx_ring); + macb->tx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->tx_ring); + macb->tx_buffer = rt_malloc(MACB_TX_BUFFER_SIZE); + if (macb->tx_buffer == RT_NULL) + goto err2; + macb->tx_buffer_dma = emac_virt_to_phys((unsigned long)macb->tx_buffer); #endif - macb->rx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); - if (macb->rx_ring == RT_NULL) - goto err3; - EMAC_CACHE_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); - macb->rx_ring_dma = emac_virt_to_phys((unsigned long)macb->rx_ring); - macb->rx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->rx_ring); - macb->rx_buffer = rt_malloc(MACB_RX_BUFFER_SIZE); - if (macb->rx_buffer == RT_NULL) - goto err4; - macb->rx_buffer_dma = emac_virt_to_phys((unsigned long)macb->rx_buffer); - - macb->tx_pending = DEF_TX_RING_PENDING; - - macb->regs = AT91SAM9260_BASE_EMAC; - macb->phy_addr = 0x00; - - /* - * Do some basic initialization so that we at least can talk - * to the PHY - */ - macb_hz = clk_get_rate(clk_get("mck")); - if (macb_hz < 20000000) - ncfgr = MACB_BF(CLK, MACB_CLK_DIV8); - else if (macb_hz < 40000000) - ncfgr = MACB_BF(CLK, MACB_CLK_DIV16); - else if (macb_hz < 80000000) - ncfgr = MACB_BF(CLK, MACB_CLK_DIV32); - else - ncfgr = MACB_BF(CLK, MACB_CLK_DIV64); - - macb_writel(macb, NCFGR, ncfgr); - - macb->link = 0; - - return RT_EOK; + macb->rx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); + if (macb->rx_ring == RT_NULL) + goto err3; + EMAC_CACHE_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); + macb->rx_ring_dma = emac_virt_to_phys((unsigned long)macb->rx_ring); + macb->rx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->rx_ring); + macb->rx_buffer = rt_malloc(MACB_RX_BUFFER_SIZE); + if (macb->rx_buffer == RT_NULL) + goto err4; + macb->rx_buffer_dma = emac_virt_to_phys((unsigned long)macb->rx_buffer); + + macb->tx_pending = DEF_TX_RING_PENDING; + + macb->regs = AT91SAM9260_BASE_EMAC; + macb->phy_addr = 0x00; + + /* + * Do some basic initialization so that we at least can talk + * to the PHY + */ + macb_hz = clk_get_rate(clk_get("mck")); + if (macb_hz < 20000000) + ncfgr = MACB_BF(CLK, MACB_CLK_DIV8); + else if (macb_hz < 40000000) + ncfgr = MACB_BF(CLK, MACB_CLK_DIV16); + else if (macb_hz < 80000000) + ncfgr = MACB_BF(CLK, MACB_CLK_DIV32); + else + ncfgr = MACB_BF(CLK, MACB_CLK_DIV64); + + macb_writel(macb, NCFGR, ncfgr); + + macb->link = 0; + + return RT_EOK; err4: - rt_free(macb->rx_ring); - macb->rx_ring = RT_NULL; + rt_free(macb->rx_ring); + macb->rx_ring = RT_NULL; err3: #if !defined(MACB_TX_SRAM) - rt_free(macb->tx_buffer); - macb->tx_buffer = RT_NULL; + rt_free(macb->tx_buffer); + macb->tx_buffer = RT_NULL; err2: - rt_free(macb->tx_ring); - macb->tx_ring = RT_NULL; + rt_free(macb->tx_ring); + macb->tx_ring = RT_NULL; err1: #endif - return -RT_ENOMEM; + return -RT_ENOMEM; } int rt_hw_macb_init(void) { - rt_err_t ret; - at91_sys_write(AT91_PMC + AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); //enable macb clock - macb_gpio_init(); - rt_memset(&macb_device, 0, sizeof(macb_device)); - ret = macb_initialize(); - if (ret != RT_EOK) - { - rt_kprintf("AT91 EMAC initialized failed\n"); - return -1; - } - rt_sem_init(&macb_device.tx_ack, "tx_ack", 0, RT_IPC_FLAG_FIFO); - rt_sem_init(&macb_device.tx_lock, "tx_lock", 1, RT_IPC_FLAG_FIFO); - rt_sem_init(&macb_device.rx_lock, "rx_lock", 1, RT_IPC_FLAG_FIFO); - - macb_device.dev_addr[0] = 0x00; - macb_device.dev_addr[1] = 0x60; - macb_device.dev_addr[2] = 0x6E; - macb_device.dev_addr[3] = 0x11; - macb_device.dev_addr[4] = 0x22; - macb_device.dev_addr[5] = 0x33; - - macb_device.parent.parent.init = rt_macb_init; - macb_device.parent.parent.open = rt_macb_open; - macb_device.parent.parent.close = rt_macb_close; - macb_device.parent.parent.read = rt_macb_read; - macb_device.parent.parent.write = rt_macb_write; - macb_device.parent.parent.control = rt_macb_control; - macb_device.parent.parent.user_data = &macb_device; - - macb_device.parent.eth_rx = rt_macb_rx; - macb_device.parent.eth_tx = rt_macb_tx; - - rt_sem_init(&macb_device.mdio_bus_lock, "mdio_bus_lock", 1, RT_IPC_FLAG_FIFO); - - eth_device_init(&(macb_device.parent), "e0"); - - return 0; + rt_err_t ret; + at91_sys_write(AT91_PMC + AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); //enable macb clock + macb_gpio_init(); + rt_memset(&macb_device, 0, sizeof(macb_device)); + ret = macb_initialize(); + if (ret != RT_EOK) + { + rt_kprintf("AT91 EMAC initialized failed\n"); + return -1; + } + rt_sem_init(&macb_device.tx_ack, "tx_ack", 0, RT_IPC_FLAG_FIFO); + rt_sem_init(&macb_device.tx_lock, "tx_lock", 1, RT_IPC_FLAG_FIFO); + rt_sem_init(&macb_device.rx_lock, "rx_lock", 1, RT_IPC_FLAG_FIFO); + + macb_device.dev_addr[0] = 0x00; + macb_device.dev_addr[1] = 0x60; + macb_device.dev_addr[2] = 0x6E; + macb_device.dev_addr[3] = 0x11; + macb_device.dev_addr[4] = 0x22; + macb_device.dev_addr[5] = 0x33; + + macb_device.parent.parent.init = rt_macb_init; + macb_device.parent.parent.open = rt_macb_open; + macb_device.parent.parent.close = rt_macb_close; + macb_device.parent.parent.read = rt_macb_read; + macb_device.parent.parent.write = rt_macb_write; + macb_device.parent.parent.control = rt_macb_control; + macb_device.parent.parent.user_data = &macb_device; + + macb_device.parent.eth_rx = rt_macb_rx; + macb_device.parent.eth_tx = rt_macb_tx; + + rt_sem_init(&macb_device.mdio_bus_lock, "mdio_bus_lock", 1, RT_IPC_FLAG_FIFO); + + eth_device_init(&(macb_device.parent), "e0"); + + return 0; } INIT_DEVICE_EXPORT(rt_hw_macb_init); diff --git a/bsp/at91sam9260/drivers/macb.h b/bsp/at91sam9260/drivers/macb.h index d6ecb2dd56..ed2ad390b7 100644 --- a/bsp/at91sam9260/drivers/macb.h +++ b/bsp/at91sam9260/drivers/macb.h @@ -12,319 +12,319 @@ #include /* MACB register offsets */ -#define MACB_NCR 0x0000 -#define MACB_NCFGR 0x0004 -#define MACB_NSR 0x0008 -#define MACB_TSR 0x0014 -#define MACB_RBQP 0x0018 -#define MACB_TBQP 0x001c -#define MACB_RSR 0x0020 -#define MACB_ISR 0x0024 -#define MACB_IER 0x0028 -#define MACB_IDR 0x002c -#define MACB_IMR 0x0030 -#define MACB_MAN 0x0034 -#define MACB_PTR 0x0038 -#define MACB_PFR 0x003c -#define MACB_FTO 0x0040 -#define MACB_SCF 0x0044 -#define MACB_MCF 0x0048 -#define MACB_FRO 0x004c -#define MACB_FCSE 0x0050 -#define MACB_ALE 0x0054 -#define MACB_DTF 0x0058 -#define MACB_LCOL 0x005c -#define MACB_EXCOL 0x0060 -#define MACB_TUND 0x0064 -#define MACB_CSE 0x0068 -#define MACB_RRE 0x006c -#define MACB_ROVR 0x0070 -#define MACB_RSE 0x0074 -#define MACB_ELE 0x0078 -#define MACB_RJA 0x007c -#define MACB_USF 0x0080 -#define MACB_STE 0x0084 -#define MACB_RLE 0x0088 -#define MACB_TPF 0x008c -#define MACB_HRB 0x0090 -#define MACB_HRT 0x0094 -#define MACB_SA1B 0x0098 -#define MACB_SA1T 0x009c -#define MACB_SA2B 0x00a0 -#define MACB_SA2T 0x00a4 -#define MACB_SA3B 0x00a8 -#define MACB_SA3T 0x00ac -#define MACB_SA4B 0x00b0 -#define MACB_SA4T 0x00b4 -#define MACB_TID 0x00b8 -#define MACB_TPQ 0x00bc -#define MACB_USRIO 0x00c0 -#define MACB_WOL 0x00c4 +#define MACB_NCR 0x0000 +#define MACB_NCFGR 0x0004 +#define MACB_NSR 0x0008 +#define MACB_TSR 0x0014 +#define MACB_RBQP 0x0018 +#define MACB_TBQP 0x001c +#define MACB_RSR 0x0020 +#define MACB_ISR 0x0024 +#define MACB_IER 0x0028 +#define MACB_IDR 0x002c +#define MACB_IMR 0x0030 +#define MACB_MAN 0x0034 +#define MACB_PTR 0x0038 +#define MACB_PFR 0x003c +#define MACB_FTO 0x0040 +#define MACB_SCF 0x0044 +#define MACB_MCF 0x0048 +#define MACB_FRO 0x004c +#define MACB_FCSE 0x0050 +#define MACB_ALE 0x0054 +#define MACB_DTF 0x0058 +#define MACB_LCOL 0x005c +#define MACB_EXCOL 0x0060 +#define MACB_TUND 0x0064 +#define MACB_CSE 0x0068 +#define MACB_RRE 0x006c +#define MACB_ROVR 0x0070 +#define MACB_RSE 0x0074 +#define MACB_ELE 0x0078 +#define MACB_RJA 0x007c +#define MACB_USF 0x0080 +#define MACB_STE 0x0084 +#define MACB_RLE 0x0088 +#define MACB_TPF 0x008c +#define MACB_HRB 0x0090 +#define MACB_HRT 0x0094 +#define MACB_SA1B 0x0098 +#define MACB_SA1T 0x009c +#define MACB_SA2B 0x00a0 +#define MACB_SA2T 0x00a4 +#define MACB_SA3B 0x00a8 +#define MACB_SA3T 0x00ac +#define MACB_SA4B 0x00b0 +#define MACB_SA4T 0x00b4 +#define MACB_TID 0x00b8 +#define MACB_TPQ 0x00bc +#define MACB_USRIO 0x00c0 +#define MACB_WOL 0x00c4 /* Bitfields in NCR */ -#define MACB_LB_OFFSET 0 -#define MACB_LB_SIZE 1 -#define MACB_LLB_OFFSET 1 -#define MACB_LLB_SIZE 1 -#define MACB_RE_OFFSET 2 -#define MACB_RE_SIZE 1 -#define MACB_TE_OFFSET 3 -#define MACB_TE_SIZE 1 -#define MACB_MPE_OFFSET 4 -#define MACB_MPE_SIZE 1 -#define MACB_CLRSTAT_OFFSET 5 -#define MACB_CLRSTAT_SIZE 1 -#define MACB_INCSTAT_OFFSET 6 -#define MACB_INCSTAT_SIZE 1 -#define MACB_WESTAT_OFFSET 7 -#define MACB_WESTAT_SIZE 1 -#define MACB_BP_OFFSET 8 -#define MACB_BP_SIZE 1 -#define MACB_TSTART_OFFSET 9 -#define MACB_TSTART_SIZE 1 -#define MACB_THALT_OFFSET 10 -#define MACB_THALT_SIZE 1 -#define MACB_NCR_TPF_OFFSET 11 -#define MACB_NCR_TPF_SIZE 1 -#define MACB_TZQ_OFFSET 12 -#define MACB_TZQ_SIZE 1 +#define MACB_LB_OFFSET 0 +#define MACB_LB_SIZE 1 +#define MACB_LLB_OFFSET 1 +#define MACB_LLB_SIZE 1 +#define MACB_RE_OFFSET 2 +#define MACB_RE_SIZE 1 +#define MACB_TE_OFFSET 3 +#define MACB_TE_SIZE 1 +#define MACB_MPE_OFFSET 4 +#define MACB_MPE_SIZE 1 +#define MACB_CLRSTAT_OFFSET 5 +#define MACB_CLRSTAT_SIZE 1 +#define MACB_INCSTAT_OFFSET 6 +#define MACB_INCSTAT_SIZE 1 +#define MACB_WESTAT_OFFSET 7 +#define MACB_WESTAT_SIZE 1 +#define MACB_BP_OFFSET 8 +#define MACB_BP_SIZE 1 +#define MACB_TSTART_OFFSET 9 +#define MACB_TSTART_SIZE 1 +#define MACB_THALT_OFFSET 10 +#define MACB_THALT_SIZE 1 +#define MACB_NCR_TPF_OFFSET 11 +#define MACB_NCR_TPF_SIZE 1 +#define MACB_TZQ_OFFSET 12 +#define MACB_TZQ_SIZE 1 /* Bitfields in NCFGR */ -#define MACB_SPD_OFFSET 0 -#define MACB_SPD_SIZE 1 -#define MACB_FD_OFFSET 1 -#define MACB_FD_SIZE 1 -#define MACB_BIT_RATE_OFFSET 2 -#define MACB_BIT_RATE_SIZE 1 -#define MACB_JFRAME_OFFSET 3 -#define MACB_JFRAME_SIZE 1 -#define MACB_CAF_OFFSET 4 -#define MACB_CAF_SIZE 1 -#define MACB_NBC_OFFSET 5 -#define MACB_NBC_SIZE 1 -#define MACB_NCFGR_MTI_OFFSET 6 -#define MACB_NCFGR_MTI_SIZE 1 -#define MACB_UNI_OFFSET 7 -#define MACB_UNI_SIZE 1 -#define MACB_BIG_OFFSET 8 -#define MACB_BIG_SIZE 1 -#define MACB_EAE_OFFSET 9 -#define MACB_EAE_SIZE 1 -#define MACB_CLK_OFFSET 10 -#define MACB_CLK_SIZE 2 -#define MACB_RTY_OFFSET 12 -#define MACB_RTY_SIZE 1 -#define MACB_PAE_OFFSET 13 -#define MACB_PAE_SIZE 1 -#define MACB_RBOF_OFFSET 14 -#define MACB_RBOF_SIZE 2 -#define MACB_RLCE_OFFSET 16 -#define MACB_RLCE_SIZE 1 -#define MACB_DRFCS_OFFSET 17 -#define MACB_DRFCS_SIZE 1 -#define MACB_EFRHD_OFFSET 18 -#define MACB_EFRHD_SIZE 1 -#define MACB_IRXFCS_OFFSET 19 -#define MACB_IRXFCS_SIZE 1 +#define MACB_SPD_OFFSET 0 +#define MACB_SPD_SIZE 1 +#define MACB_FD_OFFSET 1 +#define MACB_FD_SIZE 1 +#define MACB_BIT_RATE_OFFSET 2 +#define MACB_BIT_RATE_SIZE 1 +#define MACB_JFRAME_OFFSET 3 +#define MACB_JFRAME_SIZE 1 +#define MACB_CAF_OFFSET 4 +#define MACB_CAF_SIZE 1 +#define MACB_NBC_OFFSET 5 +#define MACB_NBC_SIZE 1 +#define MACB_NCFGR_MTI_OFFSET 6 +#define MACB_NCFGR_MTI_SIZE 1 +#define MACB_UNI_OFFSET 7 +#define MACB_UNI_SIZE 1 +#define MACB_BIG_OFFSET 8 +#define MACB_BIG_SIZE 1 +#define MACB_EAE_OFFSET 9 +#define MACB_EAE_SIZE 1 +#define MACB_CLK_OFFSET 10 +#define MACB_CLK_SIZE 2 +#define MACB_RTY_OFFSET 12 +#define MACB_RTY_SIZE 1 +#define MACB_PAE_OFFSET 13 +#define MACB_PAE_SIZE 1 +#define MACB_RBOF_OFFSET 14 +#define MACB_RBOF_SIZE 2 +#define MACB_RLCE_OFFSET 16 +#define MACB_RLCE_SIZE 1 +#define MACB_DRFCS_OFFSET 17 +#define MACB_DRFCS_SIZE 1 +#define MACB_EFRHD_OFFSET 18 +#define MACB_EFRHD_SIZE 1 +#define MACB_IRXFCS_OFFSET 19 +#define MACB_IRXFCS_SIZE 1 /* Bitfields in NSR */ -#define MACB_NSR_LINK_OFFSET 0 -#define MACB_NSR_LINK_SIZE 1 -#define MACB_MDIO_OFFSET 1 -#define MACB_MDIO_SIZE 1 -#define MACB_IDLE_OFFSET 2 -#define MACB_IDLE_SIZE 1 +#define MACB_NSR_LINK_OFFSET 0 +#define MACB_NSR_LINK_SIZE 1 +#define MACB_MDIO_OFFSET 1 +#define MACB_MDIO_SIZE 1 +#define MACB_IDLE_OFFSET 2 +#define MACB_IDLE_SIZE 1 /* Bitfields in TSR */ -#define MACB_UBR_OFFSET 0 -#define MACB_UBR_SIZE 1 -#define MACB_COL_OFFSET 1 -#define MACB_COL_SIZE 1 -#define MACB_TSR_RLE_OFFSET 2 -#define MACB_TSR_RLE_SIZE 1 -#define MACB_TGO_OFFSET 3 -#define MACB_TGO_SIZE 1 -#define MACB_BEX_OFFSET 4 -#define MACB_BEX_SIZE 1 -#define MACB_COMP_OFFSET 5 -#define MACB_COMP_SIZE 1 -#define MACB_UND_OFFSET 6 -#define MACB_UND_SIZE 1 +#define MACB_UBR_OFFSET 0 +#define MACB_UBR_SIZE 1 +#define MACB_COL_OFFSET 1 +#define MACB_COL_SIZE 1 +#define MACB_TSR_RLE_OFFSET 2 +#define MACB_TSR_RLE_SIZE 1 +#define MACB_TGO_OFFSET 3 +#define MACB_TGO_SIZE 1 +#define MACB_BEX_OFFSET 4 +#define MACB_BEX_SIZE 1 +#define MACB_COMP_OFFSET 5 +#define MACB_COMP_SIZE 1 +#define MACB_UND_OFFSET 6 +#define MACB_UND_SIZE 1 /* Bitfields in RSR */ -#define MACB_BNA_OFFSET 0 -#define MACB_BNA_SIZE 1 -#define MACB_REC_OFFSET 1 -#define MACB_REC_SIZE 1 -#define MACB_OVR_OFFSET 2 -#define MACB_OVR_SIZE 1 +#define MACB_BNA_OFFSET 0 +#define MACB_BNA_SIZE 1 +#define MACB_REC_OFFSET 1 +#define MACB_REC_SIZE 1 +#define MACB_OVR_OFFSET 2 +#define MACB_OVR_SIZE 1 /* Bitfields in ISR/IER/IDR/IMR */ -#define MACB_MFD_OFFSET 0 -#define MACB_MFD_SIZE 1 -#define MACB_RCOMP_OFFSET 1 -#define MACB_RCOMP_SIZE 1 -#define MACB_RXUBR_OFFSET 2 -#define MACB_RXUBR_SIZE 1 -#define MACB_TXUBR_OFFSET 3 -#define MACB_TXUBR_SIZE 1 -#define MACB_ISR_TUND_OFFSET 4 -#define MACB_ISR_TUND_SIZE 1 -#define MACB_ISR_RLE_OFFSET 5 -#define MACB_ISR_RLE_SIZE 1 -#define MACB_TXERR_OFFSET 6 -#define MACB_TXERR_SIZE 1 -#define MACB_TCOMP_OFFSET 7 -#define MACB_TCOMP_SIZE 1 -#define MACB_ISR_LINK_OFFSET 9 -#define MACB_ISR_LINK_SIZE 1 -#define MACB_ISR_ROVR_OFFSET 10 -#define MACB_ISR_ROVR_SIZE 1 -#define MACB_HRESP_OFFSET 11 -#define MACB_HRESP_SIZE 1 -#define MACB_PFR_OFFSET 12 -#define MACB_PFR_SIZE 1 -#define MACB_PTZ_OFFSET 13 -#define MACB_PTZ_SIZE 1 +#define MACB_MFD_OFFSET 0 +#define MACB_MFD_SIZE 1 +#define MACB_RCOMP_OFFSET 1 +#define MACB_RCOMP_SIZE 1 +#define MACB_RXUBR_OFFSET 2 +#define MACB_RXUBR_SIZE 1 +#define MACB_TXUBR_OFFSET 3 +#define MACB_TXUBR_SIZE 1 +#define MACB_ISR_TUND_OFFSET 4 +#define MACB_ISR_TUND_SIZE 1 +#define MACB_ISR_RLE_OFFSET 5 +#define MACB_ISR_RLE_SIZE 1 +#define MACB_TXERR_OFFSET 6 +#define MACB_TXERR_SIZE 1 +#define MACB_TCOMP_OFFSET 7 +#define MACB_TCOMP_SIZE 1 +#define MACB_ISR_LINK_OFFSET 9 +#define MACB_ISR_LINK_SIZE 1 +#define MACB_ISR_ROVR_OFFSET 10 +#define MACB_ISR_ROVR_SIZE 1 +#define MACB_HRESP_OFFSET 11 +#define MACB_HRESP_SIZE 1 +#define MACB_PFR_OFFSET 12 +#define MACB_PFR_SIZE 1 +#define MACB_PTZ_OFFSET 13 +#define MACB_PTZ_SIZE 1 /* Bitfields in MAN */ -#define MACB_DATA_OFFSET 0 -#define MACB_DATA_SIZE 16 -#define MACB_CODE_OFFSET 16 -#define MACB_CODE_SIZE 2 -#define MACB_REGA_OFFSET 18 -#define MACB_REGA_SIZE 5 -#define MACB_PHYA_OFFSET 23 -#define MACB_PHYA_SIZE 5 -#define MACB_RW_OFFSET 28 -#define MACB_RW_SIZE 2 -#define MACB_SOF_OFFSET 30 -#define MACB_SOF_SIZE 2 +#define MACB_DATA_OFFSET 0 +#define MACB_DATA_SIZE 16 +#define MACB_CODE_OFFSET 16 +#define MACB_CODE_SIZE 2 +#define MACB_REGA_OFFSET 18 +#define MACB_REGA_SIZE 5 +#define MACB_PHYA_OFFSET 23 +#define MACB_PHYA_SIZE 5 +#define MACB_RW_OFFSET 28 +#define MACB_RW_SIZE 2 +#define MACB_SOF_OFFSET 30 +#define MACB_SOF_SIZE 2 /* Bitfields in USRIO (AVR32) */ -#define MACB_MII_OFFSET 0 -#define MACB_MII_SIZE 1 -#define MACB_EAM_OFFSET 1 -#define MACB_EAM_SIZE 1 -#define MACB_TX_PAUSE_OFFSET 2 -#define MACB_TX_PAUSE_SIZE 1 -#define MACB_TX_PAUSE_ZERO_OFFSET 3 -#define MACB_TX_PAUSE_ZERO_SIZE 1 +#define MACB_MII_OFFSET 0 +#define MACB_MII_SIZE 1 +#define MACB_EAM_OFFSET 1 +#define MACB_EAM_SIZE 1 +#define MACB_TX_PAUSE_OFFSET 2 +#define MACB_TX_PAUSE_SIZE 1 +#define MACB_TX_PAUSE_ZERO_OFFSET 3 +#define MACB_TX_PAUSE_ZERO_SIZE 1 /* Bitfields in USRIO (AT91) */ -#define MACB_RMII_OFFSET 0 -#define MACB_RMII_SIZE 1 -#define MACB_CLKEN_OFFSET 1 -#define MACB_CLKEN_SIZE 1 +#define MACB_RMII_OFFSET 0 +#define MACB_RMII_SIZE 1 +#define MACB_CLKEN_OFFSET 1 +#define MACB_CLKEN_SIZE 1 /* Bitfields in WOL */ -#define MACB_IP_OFFSET 0 -#define MACB_IP_SIZE 16 -#define MACB_MAG_OFFSET 16 -#define MACB_MAG_SIZE 1 -#define MACB_ARP_OFFSET 17 -#define MACB_ARP_SIZE 1 -#define MACB_SA1_OFFSET 18 -#define MACB_SA1_SIZE 1 -#define MACB_WOL_MTI_OFFSET 19 -#define MACB_WOL_MTI_SIZE 1 +#define MACB_IP_OFFSET 0 +#define MACB_IP_SIZE 16 +#define MACB_MAG_OFFSET 16 +#define MACB_MAG_SIZE 1 +#define MACB_ARP_OFFSET 17 +#define MACB_ARP_SIZE 1 +#define MACB_SA1_OFFSET 18 +#define MACB_SA1_SIZE 1 +#define MACB_WOL_MTI_OFFSET 19 +#define MACB_WOL_MTI_SIZE 1 /* Constants for CLK */ -#define MACB_CLK_DIV8 0 -#define MACB_CLK_DIV16 1 -#define MACB_CLK_DIV32 2 -#define MACB_CLK_DIV64 3 +#define MACB_CLK_DIV8 0 +#define MACB_CLK_DIV16 1 +#define MACB_CLK_DIV32 2 +#define MACB_CLK_DIV64 3 /* Constants for MAN register */ -#define MACB_MAN_SOF 1 -#define MACB_MAN_WRITE 1 -#define MACB_MAN_READ 2 -#define MACB_MAN_CODE 2 +#define MACB_MAN_SOF 1 +#define MACB_MAN_WRITE 1 +#define MACB_MAN_READ 2 +#define MACB_MAN_CODE 2 /* Bit manipulation macros */ -#define MACB_BIT(name) \ - (1 << MACB_##name##_OFFSET) -#define MACB_BF(name,value) \ - (((value) & ((1 << MACB_##name##_SIZE) - 1)) \ - << MACB_##name##_OFFSET) +#define MACB_BIT(name) \ + (1 << MACB_##name##_OFFSET) +#define MACB_BF(name,value) \ + (((value) & ((1 << MACB_##name##_SIZE) - 1)) \ + << MACB_##name##_OFFSET) #define MACB_BFEXT(name,value)\ - (((value) >> MACB_##name##_OFFSET) \ - & ((1 << MACB_##name##_SIZE) - 1)) -#define MACB_BFINS(name,value,old) \ - (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \ - << MACB_##name##_OFFSET)) \ - | MACB_BF(name,value)) + (((value) >> MACB_##name##_OFFSET) \ + & ((1 << MACB_##name##_SIZE) - 1)) +#define MACB_BFINS(name,value,old) \ + (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \ + << MACB_##name##_OFFSET)) \ + | MACB_BF(name,value)) /* Register access macros */ -#define macb_readl(port,reg) \ - readl((port)->regs + MACB_##reg) -#define macb_writel(port,reg,value) \ - writel((value), (port)->regs + MACB_##reg) +#define macb_readl(port,reg) \ + readl((port)->regs + MACB_##reg) +#define macb_writel(port,reg,value) \ + writel((value), (port)->regs + MACB_##reg) struct dma_desc { - rt_uint32_t addr; - rt_uint32_t ctrl; + rt_uint32_t addr; + rt_uint32_t ctrl; }; /* DMA descriptor bitfields */ -#define MACB_RX_USED_OFFSET 0 -#define MACB_RX_USED_SIZE 1 -#define MACB_RX_WRAP_OFFSET 1 -#define MACB_RX_WRAP_SIZE 1 -#define MACB_RX_WADDR_OFFSET 2 -#define MACB_RX_WADDR_SIZE 30 +#define MACB_RX_USED_OFFSET 0 +#define MACB_RX_USED_SIZE 1 +#define MACB_RX_WRAP_OFFSET 1 +#define MACB_RX_WRAP_SIZE 1 +#define MACB_RX_WADDR_OFFSET 2 +#define MACB_RX_WADDR_SIZE 30 -#define MACB_RX_FRMLEN_OFFSET 0 -#define MACB_RX_FRMLEN_SIZE 12 -#define MACB_RX_OFFSET_OFFSET 12 -#define MACB_RX_OFFSET_SIZE 2 -#define MACB_RX_SOF_OFFSET 14 -#define MACB_RX_SOF_SIZE 1 -#define MACB_RX_EOF_OFFSET 15 -#define MACB_RX_EOF_SIZE 1 -#define MACB_RX_CFI_OFFSET 16 -#define MACB_RX_CFI_SIZE 1 -#define MACB_RX_VLAN_PRI_OFFSET 17 -#define MACB_RX_VLAN_PRI_SIZE 3 -#define MACB_RX_PRI_TAG_OFFSET 20 -#define MACB_RX_PRI_TAG_SIZE 1 -#define MACB_RX_VLAN_TAG_OFFSET 21 -#define MACB_RX_VLAN_TAG_SIZE 1 -#define MACB_RX_TYPEID_MATCH_OFFSET 22 -#define MACB_RX_TYPEID_MATCH_SIZE 1 -#define MACB_RX_SA4_MATCH_OFFSET 23 -#define MACB_RX_SA4_MATCH_SIZE 1 -#define MACB_RX_SA3_MATCH_OFFSET 24 -#define MACB_RX_SA3_MATCH_SIZE 1 -#define MACB_RX_SA2_MATCH_OFFSET 25 -#define MACB_RX_SA2_MATCH_SIZE 1 -#define MACB_RX_SA1_MATCH_OFFSET 26 -#define MACB_RX_SA1_MATCH_SIZE 1 -#define MACB_RX_EXT_MATCH_OFFSET 28 -#define MACB_RX_EXT_MATCH_SIZE 1 -#define MACB_RX_UHASH_MATCH_OFFSET 29 -#define MACB_RX_UHASH_MATCH_SIZE 1 -#define MACB_RX_MHASH_MATCH_OFFSET 30 -#define MACB_RX_MHASH_MATCH_SIZE 1 -#define MACB_RX_BROADCAST_OFFSET 31 -#define MACB_RX_BROADCAST_SIZE 1 +#define MACB_RX_FRMLEN_OFFSET 0 +#define MACB_RX_FRMLEN_SIZE 12 +#define MACB_RX_OFFSET_OFFSET 12 +#define MACB_RX_OFFSET_SIZE 2 +#define MACB_RX_SOF_OFFSET 14 +#define MACB_RX_SOF_SIZE 1 +#define MACB_RX_EOF_OFFSET 15 +#define MACB_RX_EOF_SIZE 1 +#define MACB_RX_CFI_OFFSET 16 +#define MACB_RX_CFI_SIZE 1 +#define MACB_RX_VLAN_PRI_OFFSET 17 +#define MACB_RX_VLAN_PRI_SIZE 3 +#define MACB_RX_PRI_TAG_OFFSET 20 +#define MACB_RX_PRI_TAG_SIZE 1 +#define MACB_RX_VLAN_TAG_OFFSET 21 +#define MACB_RX_VLAN_TAG_SIZE 1 +#define MACB_RX_TYPEID_MATCH_OFFSET 22 +#define MACB_RX_TYPEID_MATCH_SIZE 1 +#define MACB_RX_SA4_MATCH_OFFSET 23 +#define MACB_RX_SA4_MATCH_SIZE 1 +#define MACB_RX_SA3_MATCH_OFFSET 24 +#define MACB_RX_SA3_MATCH_SIZE 1 +#define MACB_RX_SA2_MATCH_OFFSET 25 +#define MACB_RX_SA2_MATCH_SIZE 1 +#define MACB_RX_SA1_MATCH_OFFSET 26 +#define MACB_RX_SA1_MATCH_SIZE 1 +#define MACB_RX_EXT_MATCH_OFFSET 28 +#define MACB_RX_EXT_MATCH_SIZE 1 +#define MACB_RX_UHASH_MATCH_OFFSET 29 +#define MACB_RX_UHASH_MATCH_SIZE 1 +#define MACB_RX_MHASH_MATCH_OFFSET 30 +#define MACB_RX_MHASH_MATCH_SIZE 1 +#define MACB_RX_BROADCAST_OFFSET 31 +#define MACB_RX_BROADCAST_SIZE 1 -#define MACB_TX_FRMLEN_OFFSET 0 -#define MACB_TX_FRMLEN_SIZE 11 -#define MACB_TX_LAST_OFFSET 15 -#define MACB_TX_LAST_SIZE 1 -#define MACB_TX_NOCRC_OFFSET 16 -#define MACB_TX_NOCRC_SIZE 1 -#define MACB_TX_BUF_EXHAUSTED_OFFSET 27 -#define MACB_TX_BUF_EXHAUSTED_SIZE 1 -#define MACB_TX_UNDERRUN_OFFSET 28 -#define MACB_TX_UNDERRUN_SIZE 1 -#define MACB_TX_ERROR_OFFSET 29 -#define MACB_TX_ERROR_SIZE 1 -#define MACB_TX_WRAP_OFFSET 30 -#define MACB_TX_WRAP_SIZE 1 -#define MACB_TX_USED_OFFSET 31 -#define MACB_TX_USED_SIZE 1 +#define MACB_TX_FRMLEN_OFFSET 0 +#define MACB_TX_FRMLEN_SIZE 11 +#define MACB_TX_LAST_OFFSET 15 +#define MACB_TX_LAST_SIZE 1 +#define MACB_TX_NOCRC_OFFSET 16 +#define MACB_TX_NOCRC_SIZE 1 +#define MACB_TX_BUF_EXHAUSTED_OFFSET 27 +#define MACB_TX_BUF_EXHAUSTED_SIZE 1 +#define MACB_TX_UNDERRUN_OFFSET 28 +#define MACB_TX_UNDERRUN_SIZE 1 +#define MACB_TX_ERROR_OFFSET 29 +#define MACB_TX_ERROR_SIZE 1 +#define MACB_TX_WRAP_OFFSET 30 +#define MACB_TX_WRAP_SIZE 1 +#define MACB_TX_USED_OFFSET 31 +#define MACB_TX_USED_SIZE 1 extern int rt_hw_macb_init(); diff --git a/bsp/at91sam9260/drivers/mii.h b/bsp/at91sam9260/drivers/mii.h index 84f7cfe91c..03d914b7c3 100644 --- a/bsp/at91sam9260/drivers/mii.h +++ b/bsp/at91sam9260/drivers/mii.h @@ -22,7 +22,7 @@ #define MII_EXPANSION 0x06 /* Expansion register */ #define MII_CTRL1000 0x09 /* 1000BASE-T control */ #define MII_STAT1000 0x0a /* 1000BASE-T status */ -#define MII_ESTATUS 0x0f /* Extended Status */ +#define MII_ESTATUS 0x0f /* Extended Status */ #define MII_DCOUNTER 0x12 /* Disconnect counter */ #define MII_FCSCOUNTER 0x13 /* False carrier counter */ #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ @@ -37,7 +37,7 @@ /* Basic mode control register. */ #define BMCR_RESV 0x003f /* Unused... */ -#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ +#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ #define BMCR_CTST 0x0080 /* Collision test */ #define BMCR_FULLDPLX 0x0100 /* Full duplex */ #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ @@ -56,7 +56,7 @@ #define BMSR_RFAULT 0x0010 /* Remote fault detected */ #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ #define BMSR_RESV 0x00c0 /* Unused... */ -#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ +#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */ #define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */ #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ @@ -85,7 +85,7 @@ #define ADVERTISE_NPAGE 0x8000 /* Next page bit */ #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ - ADVERTISE_CSMA) + ADVERTISE_CSMA) #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ ADVERTISE_100HALF | ADVERTISE_100FULL) @@ -107,8 +107,8 @@ #define LPA_LPACK 0x4000 /* Link partner acked us */ #define LPA_NPAGE 0x8000 /* Next page bit */ -#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) -#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) +#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) +#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) /* Expansion register for auto-negotiation. */ #define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */ @@ -118,8 +118,8 @@ #define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ #define EXPANSION_RESV 0xffe0 /* Unused... */ -#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ -#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ +#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ +#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ /* N-way test register. */ #define NWAYTEST_RESV1 0x00ff /* Unused... */ @@ -137,8 +137,8 @@ #define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */ /* Flow control flags */ -#define FLOW_CTRL_TX 0x01 -#define FLOW_CTRL_RX 0x02 +#define FLOW_CTRL_TX 0x01 +#define FLOW_CTRL_RX 0x02 /** * mii_nway_result diff --git a/bsp/at91sam9260/drivers/usart.c b/bsp/at91sam9260/drivers/usart.c index dee5585f36..2d493a21bb 100644 --- a/bsp/at91sam9260/drivers/usart.c +++ b/bsp/at91sam9260/drivers/usart.c @@ -14,54 +14,54 @@ #include #include -#define RXRDY 0x01 -#define TXRDY (1 << 1) +#define RXRDY 0x01 +#define TXRDY (1 << 1) typedef struct uartport { - volatile rt_uint32_t CR; - volatile rt_uint32_t MR; - volatile rt_uint32_t IER; - volatile rt_uint32_t IDR; - volatile rt_uint32_t IMR; - volatile rt_uint32_t CSR; - volatile rt_uint32_t RHR; - volatile rt_uint32_t THR; - volatile rt_uint32_t BRGR; - volatile rt_uint32_t RTOR; - volatile rt_uint32_t TTGR; - volatile rt_uint32_t reserved0[5]; - volatile rt_uint32_t FIDI; - volatile rt_uint32_t NER; - volatile rt_uint32_t reserved1; - volatile rt_uint32_t IFR; - volatile rt_uint32_t reserved2[44]; - volatile rt_uint32_t RPR; - volatile rt_uint32_t RCR; - volatile rt_uint32_t TPR; - volatile rt_uint32_t TCR; - volatile rt_uint32_t RNPR; - volatile rt_uint32_t RNCR; - volatile rt_uint32_t TNPR; - volatile rt_uint32_t TNCR; - volatile rt_uint32_t PTCR; - volatile rt_uint32_t PTSR; + volatile rt_uint32_t CR; + volatile rt_uint32_t MR; + volatile rt_uint32_t IER; + volatile rt_uint32_t IDR; + volatile rt_uint32_t IMR; + volatile rt_uint32_t CSR; + volatile rt_uint32_t RHR; + volatile rt_uint32_t THR; + volatile rt_uint32_t BRGR; + volatile rt_uint32_t RTOR; + volatile rt_uint32_t TTGR; + volatile rt_uint32_t reserved0[5]; + volatile rt_uint32_t FIDI; + volatile rt_uint32_t NER; + volatile rt_uint32_t reserved1; + volatile rt_uint32_t IFR; + volatile rt_uint32_t reserved2[44]; + volatile rt_uint32_t RPR; + volatile rt_uint32_t RCR; + volatile rt_uint32_t TPR; + volatile rt_uint32_t TCR; + volatile rt_uint32_t RNPR; + volatile rt_uint32_t RNCR; + volatile rt_uint32_t TNPR; + volatile rt_uint32_t TNCR; + volatile rt_uint32_t PTCR; + volatile rt_uint32_t PTSR; }uartport; #define CIDR FIDI #define EXID NER #define FNR reserved1 -#define DBGU ((struct uartport *)AT91SAM9260_BASE_DBGU) +#define DBGU ((struct uartport *)AT91SAM9260_BASE_DBGU) -#define UART0 ((struct uartport *)AT91SAM9260_BASE_US0) -#define UART1 ((struct uartport *)AT91SAM9260_BASE_US1) -#define UART2 ((struct uartport *)AT91SAM9260_BASE_US2) -#define UART3 ((struct uartport *)AT91SAM9260_BASE_US3) +#define UART0 ((struct uartport *)AT91SAM9260_BASE_US0) +#define UART1 ((struct uartport *)AT91SAM9260_BASE_US1) +#define UART2 ((struct uartport *)AT91SAM9260_BASE_US2) +#define UART3 ((struct uartport *)AT91SAM9260_BASE_US3) struct at91_uart { - uartport *port; - int irq; + uartport *port; + int irq; }; @@ -71,18 +71,18 @@ struct at91_uart { */ void rt_at91_usart_handler(int vector, void *param) { - int status; - struct at91_uart *uart; - rt_device_t dev = (rt_device_t)param; - uart = (struct at91_uart *)dev->user_data; - status = uart->port->CSR; - if (!(status & uart->port->IMR)) - { - return; - } - rt_interrupt_enter(); - rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_RX_IND); - rt_interrupt_leave(); + int status; + struct at91_uart *uart; + rt_device_t dev = (rt_device_t)param; + uart = (struct at91_uart *)dev->user_data; + status = uart->port->CSR; + if (!(status & uart->port->IMR)) + { + return; + } + rt_interrupt_enter(); + rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_RX_IND); + rt_interrupt_leave(); } /** @@ -91,67 +91,67 @@ void rt_at91_usart_handler(int vector, void *param) static rt_err_t at91_usart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { - int div; - int mode = 0; - struct at91_uart *uart; + int div; + int mode = 0; + struct at91_uart *uart; - RT_ASSERT(serial != RT_NULL); + RT_ASSERT(serial != RT_NULL); RT_ASSERT(cfg != RT_NULL); - uart = (struct at91_uart *)serial->parent.user_data; - - uart->port->CR = AT91_US_RSTTX | AT91_US_RSTRX | - AT91_US_RXDIS | AT91_US_TXDIS; - mode |= AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK | - AT91_US_CHMODE_NORMAL; - switch (cfg->data_bits) - { - case DATA_BITS_8: - mode |= AT91_US_CHRL_8; - break; - case DATA_BITS_7: - mode |= AT91_US_CHRL_7; - break; - case DATA_BITS_6: - mode |= AT91_US_CHRL_6; - break; - case DATA_BITS_5: - mode |= AT91_US_CHRL_5; - break; - default: - mode |= AT91_US_CHRL_8; - break; - } - - switch (cfg->stop_bits) - { - case STOP_BITS_2: - mode |= AT91_US_NBSTOP_2; - break; - case STOP_BITS_1: - default: - mode |= AT91_US_NBSTOP_1; - break; - } - - switch (cfg->parity) - { - case PARITY_ODD: - mode |= AT91_US_PAR_ODD; - break; - case PARITY_EVEN: - mode |= AT91_US_PAR_EVEN; - break; - case PARITY_NONE: - default: - mode |= AT91_US_PAR_NONE; - break; - } - - uart->port->MR = mode; - div = (clk_get_rate(clk_get("mck")) / 16 + cfg->baud_rate/2) / cfg->baud_rate; - uart->port->BRGR = div; - uart->port->CR = AT91_US_RXEN | AT91_US_TXEN; - uart->port->IER = 0x01; + uart = (struct at91_uart *)serial->parent.user_data; + + uart->port->CR = AT91_US_RSTTX | AT91_US_RSTRX | + AT91_US_RXDIS | AT91_US_TXDIS; + mode |= AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK | + AT91_US_CHMODE_NORMAL; + switch (cfg->data_bits) + { + case DATA_BITS_8: + mode |= AT91_US_CHRL_8; + break; + case DATA_BITS_7: + mode |= AT91_US_CHRL_7; + break; + case DATA_BITS_6: + mode |= AT91_US_CHRL_6; + break; + case DATA_BITS_5: + mode |= AT91_US_CHRL_5; + break; + default: + mode |= AT91_US_CHRL_8; + break; + } + + switch (cfg->stop_bits) + { + case STOP_BITS_2: + mode |= AT91_US_NBSTOP_2; + break; + case STOP_BITS_1: + default: + mode |= AT91_US_NBSTOP_1; + break; + } + + switch (cfg->parity) + { + case PARITY_ODD: + mode |= AT91_US_PAR_ODD; + break; + case PARITY_EVEN: + mode |= AT91_US_PAR_EVEN; + break; + case PARITY_NONE: + default: + mode |= AT91_US_PAR_NONE; + break; + } + + uart->port->MR = mode; + div = (clk_get_rate(clk_get("mck")) / 16 + cfg->baud_rate/2) / cfg->baud_rate; + uart->port->BRGR = div; + uart->port->CR = AT91_US_RXEN | AT91_US_TXEN; + uart->port->IER = 0x01; return RT_EOK; } @@ -168,11 +168,11 @@ static rt_err_t at91_usart_control(struct rt_serial_device *serial, { case RT_DEVICE_CTRL_CLR_INT: /* disable rx irq */ - rt_hw_interrupt_mask(uart->irq); + rt_hw_interrupt_mask(uart->irq); break; case RT_DEVICE_CTRL_SET_INT: /* enable rx irq */ - rt_hw_interrupt_umask(uart->irq); + rt_hw_interrupt_umask(uart->irq); break; } @@ -182,10 +182,10 @@ static rt_err_t at91_usart_control(struct rt_serial_device *serial, static int at91_usart_putc(struct rt_serial_device *serial, char c) { rt_uint32_t level; - struct at91_uart *uart = serial->parent.user_data; + struct at91_uart *uart = serial->parent.user_data; while (!(uart->port->CSR & TXRDY)); - uart->port->THR = c; + uart->port->THR = c; return 1; } @@ -193,16 +193,16 @@ static int at91_usart_putc(struct rt_serial_device *serial, char c) static int at91_usart_getc(struct rt_serial_device *serial) { int result; - struct at91_uart *uart = serial->parent.user_data; + struct at91_uart *uart = serial->parent.user_data; if (uart->port->CSR & RXRDY) - { - result = uart->port->RHR & 0xff; - } - else - { - result = -1; - } + { + result = uart->port->RHR & 0xff; + } + else + { + result = -1; + } return result; } @@ -218,8 +218,8 @@ static const struct rt_uart_ops at91_usart_ops = #if defined(RT_USING_DBGU) static struct rt_serial_device serial_dbgu; struct at91_uart dbgu = { - DBGU, - AT91_ID_SYS + DBGU, + AT91_ID_SYS }; #endif @@ -227,82 +227,82 @@ struct at91_uart dbgu = { #if defined(RT_USING_UART0) static struct rt_serial_device serial0; struct at91_uart uart0 = { - UART0, - AT91SAM9260_ID_US0 + UART0, + AT91SAM9260_ID_US0 }; #endif #if defined(RT_USING_UART1) static struct rt_serial_device serial1; struct at91_uart uart1 = { - UART1, - AT91SAM9260_ID_US1 + UART1, + AT91SAM9260_ID_US1 }; #endif #if defined(RT_USING_UART2) static struct rt_serial_device serial2; struct at91_uart uart2 = { - UART2, - AT91SAM9260_ID_US2 + UART2, + AT91SAM9260_ID_US2 }; #endif #if defined(RT_USING_UART3) static struct rt_serial_device serial3; struct at91_uart uart3 = { - UART3, - AT91SAM9260_ID_US3 + UART3, + AT91SAM9260_ID_US3 }; #endif void at91_usart_gpio_init(void) { - rt_uint32_t val; + rt_uint32_t val; #ifdef RT_USING_DBGU - at91_sys_write(AT91_PIOB + PIO_IDR, (1<<14)|(1<<15)); - //at91_sys_write(AT91_PIOB + PIO_PUER, (1<<6)); - at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<14)|(1<<15)); - at91_sys_write(AT91_PIOB + PIO_ASR, (1<<14)|(1<<15)); - at91_sys_write(AT91_PIOB + PIO_PDR, (1<<14)|(1<<15)); - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); + at91_sys_write(AT91_PIOB + PIO_IDR, (1<<14)|(1<<15)); + //at91_sys_write(AT91_PIOB + PIO_PUER, (1<<6)); + at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<14)|(1<<15)); + at91_sys_write(AT91_PIOB + PIO_ASR, (1<<14)|(1<<15)); + at91_sys_write(AT91_PIOB + PIO_PDR, (1<<14)|(1<<15)); + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); #endif #ifdef RT_USING_UART0 - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US0); - at91_sys_write(AT91_PIOB + PIO_IDR, (1<<4)|(1<<5)); - at91_sys_write(AT91_PIOB + PIO_PUER, (1<<4)); - at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<5)); - at91_sys_write(AT91_PIOB + PIO_ASR, (1<<4)|(1<<5)); - at91_sys_write(AT91_PIOB + PIO_PDR, (1<<4)|(1<<5)); + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US0); + at91_sys_write(AT91_PIOB + PIO_IDR, (1<<4)|(1<<5)); + at91_sys_write(AT91_PIOB + PIO_PUER, (1<<4)); + at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<5)); + at91_sys_write(AT91_PIOB + PIO_ASR, (1<<4)|(1<<5)); + at91_sys_write(AT91_PIOB + PIO_PDR, (1<<4)|(1<<5)); #endif #ifdef RT_USING_UART1 - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1); - at91_sys_write(AT91_PIOB + PIO_IDR, (1<<6)|(1<<7)); - at91_sys_write(AT91_PIOB + PIO_PUER, (1<<6)); - at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<7)); - at91_sys_write(AT91_PIOB + PIO_ASR, (1<<6)|(1<<7)); - at91_sys_write(AT91_PIOB + PIO_PDR, (1<<6)|(1<<7)); + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1); + at91_sys_write(AT91_PIOB + PIO_IDR, (1<<6)|(1<<7)); + at91_sys_write(AT91_PIOB + PIO_PUER, (1<<6)); + at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<7)); + at91_sys_write(AT91_PIOB + PIO_ASR, (1<<6)|(1<<7)); + at91_sys_write(AT91_PIOB + PIO_PDR, (1<<6)|(1<<7)); #endif #ifdef RT_USING_UART2 - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US2); - at91_sys_write(AT91_PIOB + PIO_IDR, (1<<8)|(1<<9)); - at91_sys_write(AT91_PIOB + PIO_PUER, (1<<8)); - at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<9)); - at91_sys_write(AT91_PIOB + PIO_ASR, (1<<8)|(1<<9)); - at91_sys_write(AT91_PIOB + PIO_PDR, (1<<8)|(1<<9)); + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US2); + at91_sys_write(AT91_PIOB + PIO_IDR, (1<<8)|(1<<9)); + at91_sys_write(AT91_PIOB + PIO_PUER, (1<<8)); + at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<9)); + at91_sys_write(AT91_PIOB + PIO_ASR, (1<<8)|(1<<9)); + at91_sys_write(AT91_PIOB + PIO_PDR, (1<<8)|(1<<9)); #endif #ifdef RT_USING_UART3 - at91_sys_write(AT91_PMC_PCER, 1< #include -#define PIN_BASE AIC_IRQS +#define PIN_BASE AIC_IRQS -#define MAX_GPIO_BANKS 3 +#define MAX_GPIO_BANKS 3 -#define PIN_IRQS (MAX_GPIO_BANKS*32) +#define PIN_IRQS (MAX_GPIO_BANKS*32) /* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */ -#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0) -#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1) -#define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2) -#define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3) -#define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4) -#define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5) -#define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6) -#define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7) -#define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8) -#define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9) -#define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10) -#define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11) -#define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12) -#define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13) -#define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14) -#define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15) -#define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16) -#define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17) -#define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18) -#define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19) -#define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20) -#define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21) -#define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22) -#define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23) -#define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24) -#define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25) -#define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26) -#define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27) -#define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28) -#define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29) -#define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30) -#define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31) +#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0) +#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1) +#define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2) +#define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3) +#define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4) +#define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5) +#define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6) +#define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7) +#define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8) +#define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9) +#define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10) +#define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11) +#define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12) +#define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13) +#define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14) +#define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15) +#define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16) +#define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17) +#define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18) +#define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19) +#define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20) +#define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21) +#define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22) +#define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23) +#define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24) +#define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25) +#define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26) +#define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27) +#define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28) +#define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29) +#define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30) +#define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31) -#define AT91_PIN_PB0 (PIN_BASE + 0x20 + 0) -#define AT91_PIN_PB1 (PIN_BASE + 0x20 + 1) -#define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2) -#define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3) -#define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4) -#define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5) -#define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6) -#define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7) -#define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8) -#define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9) -#define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10) -#define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11) -#define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12) -#define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13) -#define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14) -#define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15) -#define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16) -#define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17) -#define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18) -#define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19) -#define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20) -#define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21) -#define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22) -#define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23) -#define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24) -#define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25) -#define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26) -#define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27) -#define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28) -#define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29) -#define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30) -#define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31) +#define AT91_PIN_PB0 (PIN_BASE + 0x20 + 0) +#define AT91_PIN_PB1 (PIN_BASE + 0x20 + 1) +#define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2) +#define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3) +#define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4) +#define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5) +#define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6) +#define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7) +#define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8) +#define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9) +#define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10) +#define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11) +#define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12) +#define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13) +#define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14) +#define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15) +#define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16) +#define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17) +#define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18) +#define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19) +#define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20) +#define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21) +#define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22) +#define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23) +#define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24) +#define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25) +#define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26) +#define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27) +#define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28) +#define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29) +#define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30) +#define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31) -#define AT91_PIN_PC0 (PIN_BASE + 0x40 + 0) -#define AT91_PIN_PC1 (PIN_BASE + 0x40 + 1) -#define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2) -#define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3) -#define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4) -#define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5) -#define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6) -#define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7) -#define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8) -#define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9) -#define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10) -#define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11) -#define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12) -#define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13) -#define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14) -#define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15) -#define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16) -#define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17) -#define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18) -#define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19) -#define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20) -#define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21) -#define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22) -#define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23) -#define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24) -#define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25) -#define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26) -#define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27) -#define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28) -#define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29) -#define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30) -#define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31) +#define AT91_PIN_PC0 (PIN_BASE + 0x40 + 0) +#define AT91_PIN_PC1 (PIN_BASE + 0x40 + 1) +#define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2) +#define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3) +#define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4) +#define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5) +#define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6) +#define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7) +#define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8) +#define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9) +#define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10) +#define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11) +#define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12) +#define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13) +#define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14) +#define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15) +#define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16) +#define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17) +#define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18) +#define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19) +#define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20) +#define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21) +#define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22) +#define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23) +#define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24) +#define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25) +#define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26) +#define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27) +#define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28) +#define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29) +#define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30) +#define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31) rt_inline rt_uint32_t gpio_to_irq(rt_uint32_t gpio) { - return gpio; + return gpio; } #endif diff --git a/bsp/at91sam9260/platform/interrupt.c b/bsp/at91sam9260/platform/interrupt.c index 21aa17e7c6..7c40ffbdad 100644 --- a/bsp/at91sam9260/platform/interrupt.c +++ b/bsp/at91sam9260/platform/interrupt.c @@ -175,7 +175,7 @@ static void at91_gpio_irq_init() rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, name[i]); irq_desc[idx].counter = 0; #endif - idx++; + idx++; } rt_hw_interrupt_umask(AT91SAM9260_ID_PIOA); @@ -308,7 +308,7 @@ void rt_hw_interrupt_umask(int irq) * @param name the interrupt name * @return old handler */ -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, void *param, const char *name) { rt_isr_handler_t old_handler = RT_NULL; @@ -322,7 +322,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, irq_desc[vector].param = param; #ifdef RT_USING_INTERRUPT_INFO rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name); - irq_desc[vector].counter = 0; + irq_desc[vector].counter = 0; #endif } } @@ -400,16 +400,16 @@ void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id) #ifdef RT_USING_INTERRUPT_INFO void list_irq(void) { - int irq; - - rt_kprintf("number\tcount\tname\n"); - for (irq = 0; irq < MAX_HANDLERS; irq++) - { - if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default"))) - { - rt_kprintf("%02ld: %10ld %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name); - } - } + int irq; + + rt_kprintf("number\tcount\tname\n"); + for (irq = 0; irq < MAX_HANDLERS; irq++) + { + if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default"))) + { + rt_kprintf("%02ld: %10ld %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name); + } + } } #include diff --git a/bsp/at91sam9260/platform/io.h b/bsp/at91sam9260/platform/io.h index 8252d185ba..3e41feee90 100644 --- a/bsp/at91sam9260/platform/io.h +++ b/bsp/at91sam9260/platform/io.h @@ -11,31 +11,31 @@ #ifndef __ASM_ARCH_IO_H #define __ASM_ARCH_IO_H -#define AT91_BASE_SYS 0xffffe800 +#define AT91_BASE_SYS 0xffffe800 -#define IO_SPACE_LIMIT 0xFFFFFFFF +#define IO_SPACE_LIMIT 0xFFFFFFFF -#define readb(a) (*(volatile unsigned char *)(a)) -#define readw(a) (*(volatile unsigned short *)(a)) -#define readl(a) (*(volatile unsigned int *)(a)) +#define readb(a) (*(volatile unsigned char *)(a)) +#define readw(a) (*(volatile unsigned short *)(a)) +#define readl(a) (*(volatile unsigned int *)(a)) -#define writeb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define writew(v,a) (*(volatile unsigned short *)(a) = (v)) -#define writel(v,a) (*(volatile unsigned int *)(a) = (v)) +#define writeb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define writew(v,a) (*(volatile unsigned short *)(a) = (v)) +#define writel(v,a) (*(volatile unsigned int *)(a) = (v)) rt_inline unsigned int at91_sys_read(unsigned int reg_offset) { - unsigned int addr = AT91_BASE_SYS; + unsigned int addr = AT91_BASE_SYS; - return readl(addr + reg_offset); + return readl(addr + reg_offset); } rt_inline void at91_sys_write(unsigned int reg_offset, unsigned long value) { - unsigned int addr = AT91_BASE_SYS; + unsigned int addr = AT91_BASE_SYS; - writel(value, addr + reg_offset); + writel(value, addr + reg_offset); } diff --git a/bsp/at91sam9260/platform/irq.h b/bsp/at91sam9260/platform/irq.h index 339ec1f766..76d4200d3b 100644 --- a/bsp/at91sam9260/platform/irq.h +++ b/bsp/at91sam9260/platform/irq.h @@ -7,7 +7,7 @@ * Date Author Notes * 2011-01-13 weety first version */ - + #ifndef __IRQ_H__ #define __IRQ_H__ @@ -18,18 +18,18 @@ extern "C" { /* * IRQ line status. * - * Bits 0-7 are reserved + * Bits 0-7 are reserved * * IRQ types */ -#define IRQ_TYPE_NONE 0x00000000 /* Default, unspecified type */ -#define IRQ_TYPE_EDGE_RISING 0x00000001 /* Edge rising type */ -#define IRQ_TYPE_EDGE_FALLING 0x00000002 /* Edge falling type */ +#define IRQ_TYPE_NONE 0x00000000 /* Default, unspecified type */ +#define IRQ_TYPE_EDGE_RISING 0x00000001 /* Edge rising type */ +#define IRQ_TYPE_EDGE_FALLING 0x00000002 /* Edge falling type */ #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) -#define IRQ_TYPE_LEVEL_HIGH 0x00000004 /* Level high type */ -#define IRQ_TYPE_LEVEL_LOW 0x00000008 /* Level low type */ -#define IRQ_TYPE_SENSE_MASK 0x0000000f /* Mask of the above */ -#define IRQ_TYPE_PROBE 0x00000010 /* Probing in progress */ +#define IRQ_TYPE_LEVEL_HIGH 0x00000004 /* Level high type */ +#define IRQ_TYPE_LEVEL_LOW 0x00000008 /* Level low type */ +#define IRQ_TYPE_SENSE_MASK 0x0000000f /* Mask of the above */ +#define IRQ_TYPE_PROBE 0x00000010 /* Probing in progress */ #ifdef __cplusplus } diff --git a/bsp/at91sam9260/platform/reset.c b/bsp/at91sam9260/platform/reset.c index b793b9589d..4b5462a9e1 100644 --- a/bsp/at91sam9260/platform/reset.c +++ b/bsp/at91sam9260/platform/reset.c @@ -19,12 +19,12 @@ void machine_reset(void) { - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); + at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); } void machine_shutdown(void) { - at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); + at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); } #ifdef RT_USING_FINSH @@ -35,14 +35,14 @@ FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_cpu_reset, reset, restart the system); #ifdef FINSH_USING_MSH int cmd_reset(int argc, char** argv) { - rt_hw_cpu_reset(); - return 0; + rt_hw_cpu_reset(); + return 0; } int cmd_shutdown(int argc, char** argv) { - rt_hw_cpu_shutdown(); - return 0; + rt_hw_cpu_shutdown(); + return 0; } FINSH_FUNCTION_EXPORT_ALIAS(cmd_reset, __cmd_reset, restart the system.); diff --git a/bsp/at91sam9260/platform/rt_low_level_init.c b/bsp/at91sam9260/platform/rt_low_level_init.c index 4af18b0eee..31ddf27ae6 100644 --- a/bsp/at91sam9260/platform/rt_low_level_init.c +++ b/bsp/at91sam9260/platform/rt_low_level_init.c @@ -7,9 +7,9 @@ * Date Author Notes * 2015-04-14 ArdaFu first version */ - + /* write register a=address, v=value */ -#define write_reg(a,v) (*(volatile unsigned int *)(a) = (v)) +#define write_reg(a,v) (*(volatile unsigned int *)(a) = (v)) /* Processor Reset */ #define AT91_RSTC_PROCRST (1 << 0) #define AT91_RSTC_PERRST (1 << 2) diff --git a/bsp/at91sam9260/platform/rt_low_level_init.h b/bsp/at91sam9260/platform/rt_low_level_init.h index 93a1fade4c..c79adf5284 100644 --- a/bsp/at91sam9260/platform/rt_low_level_init.h +++ b/bsp/at91sam9260/platform/rt_low_level_init.h @@ -9,7 +9,7 @@ */ #ifndef __RT_LOW_LEVEL_INIT_H__ #define __RT_LOW_LEVEL_INIT_H__ - + /*-------- Stack size of CPU modes -------------------------------------------*/ #define UND_STK_SIZE 512 #define SVC_STK_SIZE 4096 diff --git a/bsp/at91sam9260/platform/system_clock.c b/bsp/at91sam9260/platform/system_clock.c index f59aba016c..a8f866fdd6 100644 --- a/bsp/at91sam9260/platform/system_clock.c +++ b/bsp/at91sam9260/platform/system_clock.c @@ -14,270 +14,270 @@ static rt_list_t clocks; struct clk { - char name[32]; - rt_uint32_t rate_hz; - struct clk *parent; - rt_list_t node; + char name[32]; + rt_uint32_t rate_hz; + struct clk *parent; + rt_list_t node; }; static struct clk clk32k = { - "clk32k", - AT91_SLOW_CLOCK, - RT_NULL, - {RT_NULL, RT_NULL}, + "clk32k", + AT91_SLOW_CLOCK, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk main_clk = { - "main", - 0, - RT_NULL, - {RT_NULL, RT_NULL}, + "main", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk plla = { - "plla", - 0, - RT_NULL, - {RT_NULL, RT_NULL}, + "plla", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk mck = { - "mck", - 0, - RT_NULL, - {RT_NULL, RT_NULL}, + "mck", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk uhpck = { - "uhpck", - 0, - RT_NULL, - {RT_NULL, RT_NULL}, + "uhpck", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk pllb = { - "pllb", - 0, - &main_clk, - {RT_NULL, RT_NULL}, + "pllb", + 0, + &main_clk, + {RT_NULL, RT_NULL}, }; static struct clk udpck = { - "udpck", - 0, - &pllb, - {RT_NULL, RT_NULL}, + "udpck", + 0, + &pllb, + {RT_NULL, RT_NULL}, }; static struct clk *const standard_pmc_clocks[] = { - /* four primary clocks */ - &clk32k, - &main_clk, - &plla, + /* four primary clocks */ + &clk32k, + &main_clk, + &plla, - /* MCK */ - &mck + /* MCK */ + &mck }; /* clocks cannot be de-registered no refcounting necessary */ struct clk *clk_get(const char *id) { - struct clk *clk; - rt_list_t *list; - - for (list = (&clocks)->next; list != &clocks; list = list->next) - { - clk = (struct clk *)rt_list_entry(list, struct clk, node); - if (rt_strcmp(id, clk->name) == 0) - return clk; - } - - return RT_NULL; + struct clk *clk; + rt_list_t *list; + + for (list = (&clocks)->next; list != &clocks; list = list->next) + { + clk = (struct clk *)rt_list_entry(list, struct clk, node); + if (rt_strcmp(id, clk->name) == 0) + return clk; + } + + return RT_NULL; } rt_uint32_t clk_get_rate(struct clk *clk) { - rt_uint32_t flags; - rt_uint32_t rate; - - for (;;) { - rate = clk->rate_hz; - if (rate || !clk->parent) - break; - clk = clk->parent; - } - return rate; + rt_uint32_t flags; + rt_uint32_t rate; + + for (;;) { + rate = clk->rate_hz; + if (rate || !clk->parent) + break; + clk = clk->parent; + } + return rate; } static rt_uint32_t at91_pll_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg) { - unsigned mul, div; + unsigned mul, div; - div = reg & 0xff; - mul = (reg >> 16) & 0x7ff; - if (div && mul) { - freq /= div; - freq *= mul + 1; - } else - freq = 0; + div = reg & 0xff; + mul = (reg >> 16) & 0x7ff; + if (div && mul) { + freq /= div; + freq *= mul + 1; + } else + freq = 0; - return freq; + return freq; } static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq) { - unsigned i, div = 0, mul = 0, diff = 1 << 30; - unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; - - /* PLL output max 240 MHz (or 180 MHz per errata) */ - if (out_freq > 240000000) - goto fail; - - for (i = 1; i < 256; i++) { - int diff1; - unsigned input, mul1; - - /* - * PLL input between 1MHz and 32MHz per spec, but lower - * frequences seem necessary in some cases so allow 100K. - * Warning: some newer products need 2MHz min. - */ - input = main_freq / i; - if (input < 100000) - continue; - if (input > 32000000) - continue; - - mul1 = out_freq / input; - if (mul1 > 2048) - continue; - if (mul1 < 2) - goto fail; - - diff1 = out_freq - input * mul1; - if (diff1 < 0) - diff1 = -diff1; - if (diff > diff1) { - diff = diff1; - div = i; - mul = mul1; - if (diff == 0) - break; - } - } - if (i == 256 && diff > (out_freq >> 5)) - goto fail; - return ret | ((mul - 1) << 16) | div; + unsigned i, div = 0, mul = 0, diff = 1 << 30; + unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; + + /* PLL output max 240 MHz (or 180 MHz per errata) */ + if (out_freq > 240000000) + goto fail; + + for (i = 1; i < 256; i++) { + int diff1; + unsigned input, mul1; + + /* + * PLL input between 1MHz and 32MHz per spec, but lower + * frequences seem necessary in some cases so allow 100K. + * Warning: some newer products need 2MHz min. + */ + input = main_freq / i; + if (input < 100000) + continue; + if (input > 32000000) + continue; + + mul1 = out_freq / input; + if (mul1 > 2048) + continue; + if (mul1 < 2) + goto fail; + + diff1 = out_freq - input * mul1; + if (diff1 < 0) + diff1 = -diff1; + if (diff > diff1) { + diff = diff1; + div = i; + mul = mul1; + if (diff == 0) + break; + } + } + if (i == 256 && diff > (out_freq >> 5)) + goto fail; + return ret | ((mul - 1) << 16) | div; fail: - return 0; + return 0; } static rt_uint32_t at91_usb_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg) { - if (pll == &pllb && (reg & AT91_PMC_USB96M)) - return freq / 2; - else - return freq; + if (pll == &pllb && (reg & AT91_PMC_USB96M)) + return freq / 2; + else + return freq; } /* PLLB generated USB full speed clock init */ static void at91_pllb_usbfs_clock_init(rt_uint32_t main_clock) { - rt_uint32_t at91_pllb_usb_init; - /* - * USB clock init: choose 48 MHz PLLB value, - * disable 48MHz clock during usb peripheral suspend. - * - * REVISIT: assumes MCK doesn't derive from PLLB! - */ - uhpck.parent = &pllb; - - at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; - pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); - - at91_sys_write(AT91_CKGR_PLLBR, 0); - - udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); - uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); + rt_uint32_t at91_pllb_usb_init; + /* + * USB clock init: choose 48 MHz PLLB value, + * disable 48MHz clock during usb peripheral suspend. + * + * REVISIT: assumes MCK doesn't derive from PLLB! + */ + uhpck.parent = &pllb; + + at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; + pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); + + at91_sys_write(AT91_CKGR_PLLBR, 0); + + udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); + uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); } static struct clk *at91_css_to_clk(unsigned long css) { - switch (css) { - case AT91_PMC_CSS_SLOW: - return &clk32k; - case AT91_PMC_CSS_MAIN: - return &main_clk; - case AT91_PMC_CSS_PLLA: - return &plla; - case AT91_PMC_CSS_PLLB: - return &pllb; - } - - return RT_NULL; + switch (css) { + case AT91_PMC_CSS_SLOW: + return &clk32k; + case AT91_PMC_CSS_MAIN: + return &main_clk; + case AT91_PMC_CSS_PLLA: + return &plla; + case AT91_PMC_CSS_PLLB: + return &pllb; + } + + return RT_NULL; } #define false 0 #define true 1 int at91_clock_init(rt_uint32_t main_clock) { - unsigned tmp, freq, mckr; - int i; - int pll_overclock = false; - - /* - * When the bootloader initialized the main oscillator correctly, - * there's no problem using the cycle counter. But if it didn't, - * or when using oscillator bypass mode, we must be told the speed - * of the main clock. - */ - if (!main_clock) { - do { - tmp = at91_sys_read(AT91_CKGR_MCFR); - } while (!(tmp & AT91_PMC_MAINRDY)); - main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16); - } - main_clk.rate_hz = main_clock; - - /* report if PLLA is more than mildly overclocked */ - plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); - if (plla.rate_hz > 209000000) - pll_overclock = true; - if (pll_overclock) - ;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); - - at91_pllb_usbfs_clock_init(main_clock); - - /* - * MCK and CPU derive from one of those primary clocks. - * For now, assume this parentage won't change. - */ - mckr = at91_sys_read(AT91_PMC_MCKR); - mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); - freq = mck.parent->rate_hz; - freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */ - - mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ - - /* Register the PMC's standard clocks */ - rt_list_init(&clocks); - for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) - rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node); - - rt_list_insert_after(&clocks, &pllb.node); - rt_list_insert_after(&clocks, &uhpck.node); - rt_list_insert_after(&clocks, &udpck.node); - - /* MCK and CPU clock are "always on" */ - //clk_enable(&mck); - - /*rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n", - freq / 1000000, (unsigned) mck.rate_hz / 1000000, - (unsigned) main_clock / 1000000, - ((unsigned) main_clock % 1000000) / 1000);*///cause blocked - - return 0; + unsigned tmp, freq, mckr; + int i; + int pll_overclock = false; + + /* + * When the bootloader initialized the main oscillator correctly, + * there's no problem using the cycle counter. But if it didn't, + * or when using oscillator bypass mode, we must be told the speed + * of the main clock. + */ + if (!main_clock) { + do { + tmp = at91_sys_read(AT91_CKGR_MCFR); + } while (!(tmp & AT91_PMC_MAINRDY)); + main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16); + } + main_clk.rate_hz = main_clock; + + /* report if PLLA is more than mildly overclocked */ + plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); + if (plla.rate_hz > 209000000) + pll_overclock = true; + if (pll_overclock) + ;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); + + at91_pllb_usbfs_clock_init(main_clock); + + /* + * MCK and CPU derive from one of those primary clocks. + * For now, assume this parentage won't change. + */ + mckr = at91_sys_read(AT91_PMC_MCKR); + mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); + freq = mck.parent->rate_hz; + freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */ + + mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ + + /* Register the PMC's standard clocks */ + rt_list_init(&clocks); + for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) + rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node); + + rt_list_insert_after(&clocks, &pllb.node); + rt_list_insert_after(&clocks, &uhpck.node); + rt_list_insert_after(&clocks, &udpck.node); + + /* MCK and CPU clock are "always on" */ + //clk_enable(&mck); + + /*rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n", + freq / 1000000, (unsigned) mck.rate_hz / 1000000, + (unsigned) main_clock / 1000000, + ((unsigned) main_clock % 1000000) / 1000);*///cause blocked + + return 0; } /** @@ -285,6 +285,6 @@ int at91_clock_init(rt_uint32_t main_clock) */ void rt_hw_clock_init(void) { - at91_clock_init(18432000); + at91_clock_init(18432000); } diff --git a/bsp/avr32uc3b0/application.c b/bsp/avr32uc3b0/application.c index aeca191c18..6b87b226f4 100644 --- a/bsp/avr32uc3b0/application.c +++ b/bsp/avr32uc3b0/application.c @@ -52,7 +52,7 @@ int rt_application_init() { /* create led1 thread */ rt_thread_init(&thread_led1, - "led1", + "led1", rt_thread_entry_led1, RT_NULL, &thread_led1_stack[0], diff --git a/bsp/avr32uc3b0/board.c b/bsp/avr32uc3b0/board.c index 4227eee47d..226e59e551 100644 --- a/bsp/avr32uc3b0/board.c +++ b/bsp/avr32uc3b0/board.c @@ -16,11 +16,11 @@ #include "intc.h" #include "serial.h" -#define FOSC0 12000000 -#define FCPU 60000000 -#define FHSB FCPU -#define FPBA FCPU -#define FPBB FCPU +#define FOSC0 12000000 +#define FCPU 60000000 +#define FHSB FCPU +#define FPBA FCPU +#define FPBB FCPU extern void rt_hw_serial_isr(void); extern void rt_hw_usart_init(void); @@ -30,10 +30,10 @@ extern void rt_hw_usart_init(void); */ static void rt_hw_timer_handler(void) { - // Clears the interrupt request. - Set_system_register(AVR32_COMPARE, FCPU / RT_TICK_PER_SECOND); + // Clears the interrupt request. + Set_system_register(AVR32_COMPARE, FCPU / RT_TICK_PER_SECOND); - rt_tick_increase(); + rt_tick_increase(); } /** @@ -41,35 +41,35 @@ static void rt_hw_timer_handler(void) */ static void peripherals_init(void) { - /* - * PM initialization: OSC0 = 12MHz XTAL, PLL0 = 60MHz System Clock - */ - pm_freq_param_t pm_freq_param = - { - .cpu_f = FCPU, - .pba_f = FPBA, - .osc0_f = FOSC0, - .osc0_startup = AVR32_PM_OSCCTRL0_STARTUP_2048_RCOSC - }; - pm_configure_clocks(&pm_freq_param); + /* + * PM initialization: OSC0 = 12MHz XTAL, PLL0 = 60MHz System Clock + */ + pm_freq_param_t pm_freq_param = + { + .cpu_f = FCPU, + .pba_f = FPBA, + .osc0_f = FOSC0, + .osc0_startup = AVR32_PM_OSCCTRL0_STARTUP_2048_RCOSC + }; + pm_configure_clocks(&pm_freq_param); - /* - * USART1 initialization - */ - gpio_enable_module_pin(AVR32_USART1_TXD_0_1_PIN, AVR32_USART1_TXD_0_1_FUNCTION); - gpio_enable_module_pin(AVR32_USART1_RXD_0_1_PIN, AVR32_USART1_RXD_0_1_FUNCTION); - static const usart_options_t usartOptions = { - .baudrate = 115200, - .charlength = 8, - .paritytype = USART_NO_PARITY, - .stopbits = USART_1_STOPBIT, - .channelmode = USART_NORMAL_CHMODE - }; - usart_init_rs232(&AVR32_USART1, &usartOptions, FCPU); + /* + * USART1 initialization + */ + gpio_enable_module_pin(AVR32_USART1_TXD_0_1_PIN, AVR32_USART1_TXD_0_1_FUNCTION); + gpio_enable_module_pin(AVR32_USART1_RXD_0_1_PIN, AVR32_USART1_RXD_0_1_FUNCTION); + static const usart_options_t usartOptions = { + .baudrate = 115200, + .charlength = 8, + .paritytype = USART_NO_PARITY, + .stopbits = USART_1_STOPBIT, + .channelmode = USART_NORMAL_CHMODE + }; + usart_init_rs232(&AVR32_USART1, &usartOptions, FCPU); - INTC_init_interrupts(); - INTC_register_interrupt(&rt_hw_serial_isr, AVR32_USART1_IRQ, AVR32_INTC_INT0); - AVR32_USART1.ier = AVR32_USART_IER_RXRDY_MASK; + INTC_init_interrupts(); + INTC_register_interrupt(&rt_hw_serial_isr, AVR32_USART1_IRQ, AVR32_INTC_INT0); + AVR32_USART1.ier = AVR32_USART_IER_RXRDY_MASK; } /** @@ -77,21 +77,21 @@ static void peripherals_init(void) */ static void cpu_counter_init(void) { - INTC_register_interrupt(&rt_hw_timer_handler, AVR32_CORE_COMPARE_IRQ, AVR32_INTC_INT3); - Set_system_register(AVR32_COMPARE, FCPU / RT_TICK_PER_SECOND); - Set_system_register(AVR32_COUNT, 0); + INTC_register_interrupt(&rt_hw_timer_handler, AVR32_CORE_COMPARE_IRQ, AVR32_INTC_INT3); + Set_system_register(AVR32_COMPARE, FCPU / RT_TICK_PER_SECOND); + Set_system_register(AVR32_COUNT, 0); } void rt_hw_board_init(void) { - extern struct rt_device _rt_usart_device; - extern struct avr32_serial_device uart; + extern struct rt_device _rt_usart_device; + extern struct avr32_serial_device uart; - Disable_global_interrupt(); + Disable_global_interrupt(); - peripherals_init(); - cpu_counter_init(); + peripherals_init(); + cpu_counter_init(); - rt_hw_serial_register(&_rt_usart_device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, &uart); - rt_console_set_device("uart1"); + rt_hw_serial_register(&_rt_usart_device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, &uart); + rt_console_set_device("uart1"); } diff --git a/bsp/avr32uc3b0/rtconfig.h b/bsp/avr32uc3b0/rtconfig.h index 93d95f1046..16e8194a89 100644 --- a/bsp/avr32uc3b0/rtconfig.h +++ b/bsp/avr32uc3b0/rtconfig.h @@ -12,16 +12,16 @@ #define RTCONFIG_H_ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX*/ -#define RT_THREAD_PRIORITY_MAX 32 +#define RT_THREAD_PRIORITY_MAX 32 /* Tick per Second*/ -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 /* SECTION: RT_DEBUG */ /* Thread Debug*/ @@ -69,7 +69,7 @@ /* SECTION: Console options */ /* the buffer size of console*/ #define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 /* SECTION: FinSH shell options */ /* Using FinSH as Shell*/ @@ -84,21 +84,21 @@ #define RT_USING_DFS_ELMFAT #define RT_DFS_ELM_WORD_ACCESS -#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_DRIVES 2 /* SECTION: DFS options */ /* the max number of mounted filesystem */ -#define DFS_FILESYSTEMS_MAX 2 -/* the max number of opened files */ -#define DFS_FD_MAX 8 -/* the max number of cached sector */ -#define DFS_CACHE_MAX_NUM 4 +#define DFS_FILESYSTEMS_MAX 2 +/* the max number of opened files */ +#define DFS_FD_MAX 8 +/* the max number of cached sector */ +#define DFS_CACHE_MAX_NUM 4 /* SECTION: RT-Thread/GUI */ //#define RT_USING_RTGUI /* name length of RTGUI object */ -#define RTGUI_NAME_MAX 12 +#define RTGUI_NAME_MAX 12 /* support 16 weight font */ #define RTGUI_USING_FONT16 /* support Chinese font */ @@ -112,6 +112,6 @@ /* use mouse cursor */ /* #define RTGUI_USING_MOUSE_CURSOR */ /* default font size in RTGUI */ -#define RTGUI_DEFAULT_FONT_SIZE 16 +#define RTGUI_DEFAULT_FONT_SIZE 16 #endif /* RTCONFIG_H_ */ diff --git a/bsp/avr32uc3b0/startup.c b/bsp/avr32uc3b0/startup.c index dbebd21ceb..278b248599 100644 --- a/bsp/avr32uc3b0/startup.c +++ b/bsp/avr32uc3b0/startup.c @@ -21,21 +21,21 @@ extern void finsh_set_device(const char* device); int main(void) { #ifdef RT_USING_HEAP - extern void __heap_start__; - extern void __heap_end__; + extern void __heap_start__; + extern void __heap_end__; #endif - rt_hw_board_init(); - rt_system_tick_init(); - rt_system_object_init(); - rt_system_timer_init(); + rt_hw_board_init(); + rt_system_tick_init(); + rt_system_object_init(); + rt_system_timer_init(); #ifdef RT_USING_HEAP - rt_system_heap_init(&__heap_start__, &__heap_end__); + rt_system_heap_init(&__heap_start__, &__heap_end__); #endif - rt_system_scheduler_init(); - rt_application_init(); + rt_system_scheduler_init(); + rt_application_init(); #ifdef RT_USING_FINSH /* init finsh */ @@ -44,7 +44,7 @@ int main(void) #endif rt_thread_idle_init(); - rt_system_scheduler_start(); + rt_system_scheduler_start(); - return 0; + return 0; } diff --git a/bsp/beaglebone/applications/board.c b/bsp/beaglebone/applications/board.c index 1ee0081b17..ff25dd7dd7 100644 --- a/bsp/beaglebone/applications/board.c +++ b/bsp/beaglebone/applications/board.c @@ -45,7 +45,7 @@ static rt_uint32_t DMTIMER = 0; static void rt_hw_timer_isr(int vector, void* param) { - rt_tick_increase(); + rt_tick_increase(); DMTIMER_IRQSTATUS(TIMER_HW_BASE) = DMTIMER_IRQSTATUS_RAW_OVF_IT_FLAG; } @@ -67,73 +67,73 @@ static void timer_clk_init(void) while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & (1<<8))) ; - /* Select the clock source for the Timer2 instance. */ - CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) &= ~(CM_DPLL_CLKSEL_CLK_CLKSEL); - /* 32k clock source */ - CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) |= CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3; + /* Select the clock source for the Timer2 instance. */ + CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) &= ~(CM_DPLL_CLKSEL_CLK_CLKSEL); + /* 32k clock source */ + CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) |= CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3; - while ((CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) & CM_DPLL_CLKSEL_CLK_CLKSEL) != - CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3); + while ((CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) & CM_DPLL_CLKSEL_CLK_CLKSEL) != + CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3); - /* Writing to MODULEMODE field of CM_PER_TIMER7_CLKCTRL register. */ - CM_PER_TIMER7_CLKCTRL(prcm_base) |= CM_PER_CLKCTRL_MODULEMODE_ENABLE; + /* Writing to MODULEMODE field of CM_PER_TIMER7_CLKCTRL register. */ + CM_PER_TIMER7_CLKCTRL(prcm_base) |= CM_PER_CLKCTRL_MODULEMODE_ENABLE; - /* Waiting for MODULEMODE field to reflect the written value. */ - while ((CM_PER_TIMER7_CLKCTRL(prcm_base) & CM_PER_CLKCTRL_MODULEMODE) != - CM_PER_CLKCTRL_MODULEMODE_ENABLE); + /* Waiting for MODULEMODE field to reflect the written value. */ + while ((CM_PER_TIMER7_CLKCTRL(prcm_base) & CM_PER_CLKCTRL_MODULEMODE) != + CM_PER_CLKCTRL_MODULEMODE_ENABLE); - /* - * Waiting for IDLEST field in CM_PER_TIMER7_CLKCTRL register - * for the module is fully functional. - */ - while ((CM_PER_TIMER7_CLKCTRL(prcm_base) & CM_PER_CLKCTRL_IDLEST) != - CM_PER_CLKCTRL_IDLEST_FUNC); + /* + * Waiting for IDLEST field in CM_PER_TIMER7_CLKCTRL register + * for the module is fully functional. + */ + while ((CM_PER_TIMER7_CLKCTRL(prcm_base) & CM_PER_CLKCTRL_IDLEST) != + CM_PER_CLKCTRL_IDLEST_FUNC); - /* Waiting for the L4LS clock */ - while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK)); - /* Waiting for the TIMER7 clock */ - while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK)); + /* Waiting for the L4LS clock */ + while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK)); + /* Waiting for the TIMER7 clock */ + while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK)); } int rt_hw_timer_init(void) { - rt_uint32_t counter; + rt_uint32_t counter; #ifdef RT_USING_VMM DMTIMER = vmm_find_iomap("TIMER7"); #endif - timer_clk_init(); + timer_clk_init(); - /* soft reset the timer */ - DMTIMER_TIOCP_CFG(TIMER_HW_BASE) |= 1; + /* soft reset the timer */ + DMTIMER_TIOCP_CFG(TIMER_HW_BASE) |= 1; while ((DMTIMER_TIOCP_CFG(TIMER_HW_BASE) & 0x1) == 1) ; - /* calculate count */ - counter = 0xffffffff - (32768UL/RT_TICK_PER_SECOND); + /* calculate count */ + counter = 0xffffffff - (32768UL/RT_TICK_PER_SECOND); - /* set initial count */ - DMTIMER_TCRR(TIMER_HW_BASE) = counter; - /* set reload count */ - DMTIMER_TLDR(TIMER_HW_BASE) = counter; + /* set initial count */ + DMTIMER_TCRR(TIMER_HW_BASE) = counter; + /* set reload count */ + DMTIMER_TLDR(TIMER_HW_BASE) = counter; - /* set mode: auto reload */ - DMTIMER_TCLR(TIMER_HW_BASE) |= DMTIMER_TCLR_AR; + /* set mode: auto reload */ + DMTIMER_TCLR(TIMER_HW_BASE) |= DMTIMER_TCLR_AR; - /* interrupt enable for match */ - DMTIMER_IRQENABLE_SET(TIMER_HW_BASE) = DMTIMER_IRQENABLE_SET_OVF_EN_FLAG; + /* interrupt enable for match */ + DMTIMER_IRQENABLE_SET(TIMER_HW_BASE) = DMTIMER_IRQENABLE_SET_OVF_EN_FLAG; DMTIMER_IRQSTATUS(TIMER_HW_BASE) = DMTIMER_IRQSTATUS_RAW_OVF_IT_FLAG; - rt_hw_interrupt_install(TINT7, rt_hw_timer_isr, RT_NULL, "tick"); - rt_hw_interrupt_control(TINT7, 0, 0); - rt_hw_interrupt_umask(TINT7); + rt_hw_interrupt_install(TINT7, rt_hw_timer_isr, RT_NULL, "tick"); + rt_hw_interrupt_control(TINT7, 0, 0); + rt_hw_interrupt_umask(TINT7); while (DMTIMER_TWPS(TIMER_HW_BASE) != 0) ; - /* start timer */ - DMTIMER_TCLR(TIMER_HW_BASE) |= DMTIMER_TCLR_ST; + /* start timer */ + DMTIMER_TCLR(TIMER_HW_BASE) |= DMTIMER_TCLR_ST; while (DMTIMER_TWPS(TIMER_HW_BASE) != 0) ; @@ -148,7 +148,7 @@ INIT_BOARD_EXPORT(rt_hw_timer_init); void rt_hw_board_init(void) { rt_components_board_init(); - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); } void rt_hw_cpu_reset(void) diff --git a/bsp/bf533/rtconfig.h b/bsp/bf533/rtconfig.h index 788fa32299..1945283a68 100644 --- a/bsp/bf533/rtconfig.h +++ b/bsp/bf533/rtconfig.h @@ -6,16 +6,16 @@ #define IDLE_THREAD_STACK_SIZE 512 /* RT_NAME_MAX*/ -#define RT_NAME_MAX 32 +#define RT_NAME_MAX 32 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 256 +#define RT_THREAD_PRIORITY_MAX 256 /* Tick per Second */ -#define RT_TICK_PER_SECOND 1000 +#define RT_TICK_PER_SECOND 1000 /* SECTION: RT_DEBUG */ /* Thread Debug */ @@ -29,9 +29,9 @@ /* Using Software Timer */ //#define RT_USING_TIMER_SOFT -#define RT_TIMER_THREAD_PRIO 8 -#define RT_TIMER_THREAD_STACK_SIZE 512 -#define RT_TIMER_TICK_PER_SECOND 1000 +#define RT_TIMER_THREAD_PRIO 8 +#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_TICK_PER_SECOND 1000 /* SECTION: IPC */ /* Using Semaphore */ @@ -73,7 +73,7 @@ #define RT_USING_CONSOLE /* the buffer size of console */ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 /* SECTION: finsh, a C-Express shell */ /* Using FinSH as Shell*/ @@ -96,25 +96,25 @@ /* using DFS support */ //#define RT_USING_DFS #define RT_USING_DFS_ELMFAT -/* use long file name feature */ -#define RT_DFS_ELM_USE_LFN 1 -/* the max number of file length */ -#define RT_DFS_ELM_MAX_LFN 128 +/* use long file name feature */ +#define RT_DFS_ELM_USE_LFN 1 +/* the max number of file length */ +#define RT_DFS_ELM_MAX_LFN 128 /* #define RT_USING_DFS_YAFFS2 */ /* #define RT_USING_DFS_UFFS */ #define RT_USING_DFS_DEVFS /* #define RT_USING_DFS_NFS */ -#define RT_NFS_HOST_EXPORT "192.168.1.5:/" +#define RT_NFS_HOST_EXPORT "192.168.1.5:/" #define DFS_USING_WORKDIR /* the max number of mounted filesystem */ -#define DFS_FILESYSTEMS_MAX 4 -/* the max number of opened files */ -#define DFS_FD_MAX 16 -/* the max number of cached sector */ -#define DFS_CACHE_MAX_NUM 4 +#define DFS_FILESYSTEMS_MAX 4 +/* the max number of opened files */ +#define DFS_FD_MAX 16 +/* the max number of cached sector */ +#define DFS_CACHE_MAX_NUM 4 /* Enable freemodbus protocal stack*/ /* #define RT_USING_MODBUS */ @@ -140,13 +140,13 @@ #define RT_LWIP_TCP /* the number of simulatenously active TCP connections*/ -#define RT_LWIP_TCP_PCB_NUM 5 +#define RT_LWIP_TCP_PCB_NUM 5 /* TCP sender buffer space */ -#define RT_LWIP_TCP_SND_BUF 1024*8 +#define RT_LWIP_TCP_SND_BUF 1024*8 /* TCP receive window. */ -#define RT_LWIP_TCP_WND 1024*8 +#define RT_LWIP_TCP_WND 1024*8 /* Enable SNMP protocol */ /* #define RT_LWIP_SNMP */ @@ -155,53 +155,53 @@ /* #define RT_LWIP_DHCP */ /* ip address of target */ -#define RT_LWIP_IPADDR0 192 -#define RT_LWIP_IPADDR1 168 -#define RT_LWIP_IPADDR2 1 -#define RT_LWIP_IPADDR3 30 +#define RT_LWIP_IPADDR0 192 +#define RT_LWIP_IPADDR1 168 +#define RT_LWIP_IPADDR2 1 +#define RT_LWIP_IPADDR3 30 /* gateway address of target */ -#define RT_LWIP_GWADDR0 192 -#define RT_LWIP_GWADDR1 168 -#define RT_LWIP_GWADDR2 1 -#define RT_LWIP_GWADDR3 1 +#define RT_LWIP_GWADDR0 192 +#define RT_LWIP_GWADDR1 168 +#define RT_LWIP_GWADDR2 1 +#define RT_LWIP_GWADDR3 1 /* mask address of target */ -#define RT_LWIP_MSKADDR0 255 -#define RT_LWIP_MSKADDR1 255 -#define RT_LWIP_MSKADDR2 255 -#define RT_LWIP_MSKADDR3 0 +#define RT_LWIP_MSKADDR0 255 +#define RT_LWIP_MSKADDR1 255 +#define RT_LWIP_MSKADDR2 255 +#define RT_LWIP_MSKADDR3 0 /* the number of blocks for pbuf */ -#define RT_LWIP_PBUF_NUM 16 +#define RT_LWIP_PBUF_NUM 16 /* the number of simultaneously queued TCP */ #define RT_LWIP_TCP_SEG_NUM 40 /* thread priority of tcpip thread */ -#define RT_LWIP_TCPTHREAD_PRIORITY 128 +#define RT_LWIP_TCPTHREAD_PRIORITY 128 /* mail box size of tcpip thread to wait for */ -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 32 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 32 /* thread stack size of tcpip thread */ -#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 +#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 /* thread priority of ethnetif thread */ -#define RT_LWIP_ETHTHREAD_PRIORITY 144 +#define RT_LWIP_ETHTHREAD_PRIORITY 144 /* mail box size of ethnetif thread to wait for */ -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 32 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 32 /* thread stack size of ethnetif thread */ -#define RT_LWIP_ETHTHREAD_STACKSIZE 1024 +#define RT_LWIP_ETHTHREAD_STACKSIZE 1024 /* SECTION: RTGUI support */ /* using RTGUI support */ #define RT_USING_RTGUI /* name length of RTGUI object */ -#define RTGUI_NAME_MAX 16 +#define RTGUI_NAME_MAX 16 /* support 16 weight font */ #define RTGUI_USING_FONT16 /* support 16 weight font */ @@ -236,7 +236,7 @@ * #define DFS_USING_WORKDIR * * And the maximal length must great than 64 - * #define RT_DFS_ELM_MAX_LFN 128 + * #define RT_DFS_ELM_MAX_LFN 128 */ #endif diff --git a/bsp/dm365/applications/application.c b/bsp/dm365/applications/application.c index 59a9a60d27..3d5207b516 100644 --- a/bsp/dm365/applications/application.c +++ b/bsp/dm365/applications/application.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ @@ -27,57 +27,57 @@ int main(void) { - int timeout = 0; + int timeout = 0; /* Filesystem Initialization */ #ifdef RT_USING_DFS - { + { #if defined(RT_USING_DFS_ROMFS) - if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0) - { - rt_kprintf("ROM File System initialized!\n"); - } - else - rt_kprintf("ROM File System initialzation failed!\n"); + if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0) + { + rt_kprintf("ROM File System initialized!\n"); + } + else + rt_kprintf("ROM File System initialzation failed!\n"); #endif #if defined(RT_USING_DFS_UFFS) - { - /* mount flash device as flash directory */ - if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0) - rt_kprintf("UFFS File System initialized!\n"); - else - rt_kprintf("UFFS File System initialzation failed!\n"); - } + { + /* mount flash device as flash directory */ + if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0) + rt_kprintf("UFFS File System initialized!\n"); + else + rt_kprintf("UFFS File System initialzation failed!\n"); + } #endif #ifdef RT_USING_SDIO - timeout = 0; - while ((rt_device_find("sd0") == RT_NULL) && (timeout++ < RT_TICK_PER_SECOND*2)) - { - rt_thread_delay(1); - } - - if (timeout < RT_TICK_PER_SECOND*2) - { - /* mount sd card fat partition 1 as root directory */ - if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) - { - rt_kprintf("File System initialized!\n"); - } - else - rt_kprintf("File System initialzation failed!%d\n", rt_get_errno()); - } - else - { - rt_kprintf("No SD card found.\n"); - } + timeout = 0; + while ((rt_device_find("sd0") == RT_NULL) && (timeout++ < RT_TICK_PER_SECOND*2)) + { + rt_thread_delay(1); + } + + if (timeout < RT_TICK_PER_SECOND*2) + { + /* mount sd card fat partition 1 as root directory */ + if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) + { + rt_kprintf("File System initialized!\n"); + } + else + rt_kprintf("File System initialzation failed!%d\n", rt_get_errno()); + } + else + { + rt_kprintf("No SD card found.\n"); + } #endif - } + } #endif - /* put user application code here */ + /* put user application code here */ } @@ -87,14 +87,14 @@ int main(void) #include void nfs_start(void) { - nfs_init(); - - if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0) - { - rt_kprintf("NFSv3 File System initialized!\n"); - } - else - rt_kprintf("NFSv3 File System initialzation failed!\n"); + nfs_init(); + + if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0) + { + rt_kprintf("NFSv3 File System initialized!\n"); + } + else + rt_kprintf("NFSv3 File System initialzation failed!\n"); } #include "finsh.h" diff --git a/bsp/dm365/applications/board.c b/bsp/dm365/applications/board.c index d3db954a1a..8748d6aeae 100644 --- a/bsp/dm365/applications/board.c +++ b/bsp/dm365/applications/board.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ @@ -19,28 +19,28 @@ */ /*@{*/ #if defined(__CC_ARM) - extern int Image$$ER_ZI$$ZI$$Base; - extern int Image$$ER_ZI$$ZI$$Length; - extern int Image$$ER_ZI$$ZI$$Limit; + extern int Image$$ER_ZI$$ZI$$Base; + extern int Image$$ER_ZI$$ZI$$Length; + extern int Image$$ER_ZI$$ZI$$Limit; #elif (defined (__GNUC__)) - rt_uint8_t _irq_stack_start[1024]; - rt_uint8_t _fiq_stack_start[1024]; - rt_uint8_t _undefined_stack_start[512]; - rt_uint8_t _abort_stack_start[512]; - rt_uint8_t _svc_stack_start[1024] SECTION(".nobss"); - extern unsigned char __bss_start; - extern unsigned char __bss_end; + rt_uint8_t _irq_stack_start[1024]; + rt_uint8_t _fiq_stack_start[1024]; + rt_uint8_t _undefined_stack_start[512]; + rt_uint8_t _abort_stack_start[512]; + rt_uint8_t _svc_stack_start[1024] SECTION(".nobss"); + extern unsigned char __bss_start; + extern unsigned char __bss_end; #endif extern void rt_hw_clock_init(void); extern void rt_hw_uart_init(void); static struct mem_desc dm365_mem_desc[] = { - { 0x80000000, 0x88000000-1, 0x80000000, SECT_RW_CB, 0, SECT_MAPPED }, /* 128M cached SDRAM memory */ - { 0xA0000000, 0xA8000000-1, 0x80000000, SECT_RW_NCNB, 0, SECT_MAPPED }, /* 128M No cached SDRAM memory */ - { 0xFFFF0000, 0xFFFF1000-1, 0x80000000, SECT_TO_PAGE, PAGE_RO_CB, PAGE_MAPPED }, /* isr vector table */ - { 0x01C00000, 0x02000000-1, 0x01C00000, SECT_RW_NCNB, 0, SECT_MAPPED }, /* CFG BUS peripherals */ - { 0x02000000, 0x0A000000-1, 0x02000000, SECT_RW_NCNB, 0, SECT_MAPPED }, /* AEMIF */ + { 0x80000000, 0x88000000-1, 0x80000000, SECT_RW_CB, 0, SECT_MAPPED }, /* 128M cached SDRAM memory */ + { 0xA0000000, 0xA8000000-1, 0x80000000, SECT_RW_NCNB, 0, SECT_MAPPED }, /* 128M No cached SDRAM memory */ + { 0xFFFF0000, 0xFFFF1000-1, 0x80000000, SECT_TO_PAGE, PAGE_RO_CB, PAGE_MAPPED }, /* isr vector table */ + { 0x01C00000, 0x02000000-1, 0x01C00000, SECT_RW_NCNB, 0, SECT_MAPPED }, /* CFG BUS peripherals */ + { 0x02000000, 0x0A000000-1, 0x02000000, SECT_RW_NCNB, 0, SECT_MAPPED }, /* AEMIF */ }; @@ -49,7 +49,7 @@ static struct mem_desc dm365_mem_desc[] = { */ void rt_timer_handler(int vector, void *param) { - rt_tick_increase(); + rt_tick_increase(); } /** @@ -57,70 +57,70 @@ void rt_timer_handler(int vector, void *param) */ void rt_hw_timer_init() { - /* timer0, input clocks 24MHz */ - volatile timer_regs_t *regs = - (volatile timer_regs_t*)DAVINCI_TIMER1_BASE;//DAVINCI_TIMER0_BASE; + /* timer0, input clocks 24MHz */ + volatile timer_regs_t *regs = + (volatile timer_regs_t*)DAVINCI_TIMER1_BASE;//DAVINCI_TIMER0_BASE; - psc_change_state(DAVINCI_DM365_LPSC_TIMER0, 3); - psc_change_state(DAVINCI_DM365_LPSC_TIMER1, 3); + psc_change_state(DAVINCI_DM365_LPSC_TIMER0, 3); + psc_change_state(DAVINCI_DM365_LPSC_TIMER1, 3); - /*disable timer*/ - regs->tcr &= ~(0x3UL << 6); + /*disable timer*/ + regs->tcr &= ~(0x3UL << 6); - //TIMMODE 32BIT UNCHAINED MODE - regs->tgcr |=(0x1UL << 2); + //TIMMODE 32BIT UNCHAINED MODE + regs->tgcr |=(0x1UL << 2); - /*not in reset timer */ - regs->tgcr |= (0x1UL << 0); + /*not in reset timer */ + regs->tgcr |= (0x1UL << 0); - //regs->tgcr &= ~(0x1UL << 1); + //regs->tgcr &= ~(0x1UL << 1); - /* set Period Registers */ - regs->prd12 = 24000000/RT_TICK_PER_SECOND; - regs->tim12 = 0; + /* set Period Registers */ + regs->prd12 = 24000000/RT_TICK_PER_SECOND; + regs->tim12 = 0; - /* Set enable mode */ - regs->tcr |= (0x2UL << 6); //period mode - + /* Set enable mode */ + regs->tcr |= (0x2UL << 6); //period mode - /* install interrupt handler */ - rt_hw_interrupt_install(IRQ_DM365_TINT2, rt_timer_handler, - RT_NULL, "timer1_12");//IRQ_DM365_TINT0_TINT12 - rt_hw_interrupt_umask(IRQ_DM365_TINT2);//IRQ_DM365_TINT2 + + /* install interrupt handler */ + rt_hw_interrupt_install(IRQ_DM365_TINT2, rt_timer_handler, + RT_NULL, "timer1_12");//IRQ_DM365_TINT0_TINT12 + rt_hw_interrupt_umask(IRQ_DM365_TINT2);//IRQ_DM365_TINT2 } -#define LSR_DR 0x01 /* Data ready */ -#define LSR_THRE 0x20 /* Xmit holding register empty */ -#define BPS 115200 /* serial baudrate */ +#define LSR_DR 0x01 /* Data ready */ +#define LSR_THRE 0x20 /* Xmit holding register empty */ +#define BPS 115200 /* serial baudrate */ typedef struct uartport { - volatile rt_uint32_t rbr; - volatile rt_uint32_t ier; - volatile rt_uint32_t fcr; - volatile rt_uint32_t lcr; - volatile rt_uint32_t mcr; - volatile rt_uint32_t lsr; - volatile rt_uint32_t msr; - volatile rt_uint32_t scr; - volatile rt_uint32_t dll; - volatile rt_uint32_t dlh; - - volatile rt_uint32_t res[2]; - volatile rt_uint32_t pwremu_mgmt; - volatile rt_uint32_t mdr; + volatile rt_uint32_t rbr; + volatile rt_uint32_t ier; + volatile rt_uint32_t fcr; + volatile rt_uint32_t lcr; + volatile rt_uint32_t mcr; + volatile rt_uint32_t lsr; + volatile rt_uint32_t msr; + volatile rt_uint32_t scr; + volatile rt_uint32_t dll; + volatile rt_uint32_t dlh; + + volatile rt_uint32_t res[2]; + volatile rt_uint32_t pwremu_mgmt; + volatile rt_uint32_t mdr; }uartport; #define thr rbr #define iir fcr -#define UART0 ((struct uartport *)DAVINCI_UART0_BASE) +#define UART0 ((struct uartport *)DAVINCI_UART0_BASE) static void davinci_uart_putc(char c) { while (!(UART0->lsr & LSR_THRE)); - UART0->thr = c; + UART0->thr = c; } /** @@ -131,35 +131,35 @@ static void davinci_uart_putc(char c) */ void rt_hw_console_output(const char* str) { - while (*str) - { - if (*str=='\n') - { - davinci_uart_putc('\r'); - } - - davinci_uart_putc(*str++); - } + while (*str) + { + if (*str=='\n') + { + davinci_uart_putc('\r'); + } + + davinci_uart_putc(*str++); + } } static void rt_hw_console_init(void) { - rt_uint32_t divisor; - - divisor = (24000000 + (BPS * (16 / 2))) / (16 * BPS); - UART0->ier = 0; - UART0->lcr = 0x83; //8N1 - UART0->dll = 0; - UART0->dlh = 0; - UART0->lcr = 0x03; - UART0->mcr = 0x03; //RTS,CTS - UART0->fcr = 0x07; //FIFO - UART0->lcr = 0x83; - UART0->dll = divisor & 0xff; - UART0->dlh = (divisor >> 8) & 0xff; - UART0->lcr = 0x03; - UART0->mdr = 0; //16x over-sampling - UART0->pwremu_mgmt = 0x6000; + rt_uint32_t divisor; + + divisor = (24000000 + (BPS * (16 / 2))) / (16 * BPS); + UART0->ier = 0; + UART0->lcr = 0x83; //8N1 + UART0->dll = 0; + UART0->dlh = 0; + UART0->lcr = 0x03; + UART0->mcr = 0x03; //RTS,CTS + UART0->fcr = 0x07; //FIFO + UART0->lcr = 0x83; + UART0->dll = divisor & 0xff; + UART0->dlh = (divisor >> 8) & 0xff; + UART0->lcr = 0x03; + UART0->mdr = 0; //16x over-sampling + UART0->pwremu_mgmt = 0x6000; } /** @@ -167,35 +167,35 @@ static void rt_hw_console_init(void) */ void rt_hw_board_init() { - /* initialize console */ - rt_hw_console_init(); + /* initialize console */ + rt_hw_console_init(); - /* initialize mmu */ - rt_hw_mmu_init(dm365_mem_desc, sizeof(dm365_mem_desc)/sizeof(dm365_mem_desc[0])); + /* initialize mmu */ + rt_hw_mmu_init(dm365_mem_desc, sizeof(dm365_mem_desc)/sizeof(dm365_mem_desc[0])); - /* initialize hardware interrupt */ - rt_hw_interrupt_init(); + /* initialize hardware interrupt */ + rt_hw_interrupt_init(); - /* initialize the system clock */ - rt_hw_clock_init(); + /* initialize the system clock */ + rt_hw_clock_init(); - /* initialize heap memory system */ + /* initialize heap memory system */ #ifdef __CC_ARM - rt_system_heap_init((void*)&Image$$ER_ZI$$ZI$$Limit, (void*)0x88000000); + rt_system_heap_init((void*)&Image$$ER_ZI$$ZI$$Limit, (void*)0x88000000); #else - rt_system_heap_init((void*)&__bss_end, (void*)0x88000000); + rt_system_heap_init((void*)&__bss_end, (void*)0x88000000); #endif - /* initialize early device */ + /* initialize early device */ #ifdef RT_USING_COMPONENTS_INIT - rt_components_board_init(); + rt_components_board_init(); #endif #ifdef RT_USING_CONSOLE - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); #endif - /* initialize timer0 */ - rt_hw_timer_init(); + /* initialize timer0 */ + rt_hw_timer_init(); } diff --git a/bsp/dm365/applications/board.h b/bsp/dm365/applications/board.h index 81f05372df..b8763d9938 100644 --- a/bsp/dm365/applications/board.h +++ b/bsp/dm365/applications/board.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ diff --git a/bsp/dm365/drivers/davinci_emac.c b/bsp/dm365/drivers/davinci_emac.c index 9043493290..7ad539fb09 100644 --- a/bsp/dm365/drivers/davinci_emac.c +++ b/bsp/dm365/drivers/davinci_emac.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ @@ -15,8 +15,8 @@ #include #include "davinci_emac.h" -#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<29)) -#define CACHE_LINE_SIZE 32 +#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<29)) +#define CACHE_LINE_SIZE 32 extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size); extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); @@ -24,22 +24,22 @@ extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); /* EMAC internal utility function */ static inline rt_uint32_t emac_virt_to_phys(void *addr) { - return (rt_uint32_t)addr; + return (rt_uint32_t)addr; } static inline rt_uint32_t virt_to_phys(void *addr) { - return (rt_uint32_t)addr; + return (rt_uint32_t)addr; } /* Cache macros - Packet buffers would be from pbuf pool which is cached */ #define EMAC_VIRT_NOCACHE(addr) (addr) #define EMAC_CACHE_INVALIDATE(addr, size) \ - mmu_invalidate_dcache(addr, size) + mmu_invalidate_dcache(addr, size) #define EMAC_CACHE_WRITEBACK(addr, size) \ - mmu_clean_dcache(addr, size) + mmu_clean_dcache(addr, size) #define EMAC_CACHE_WRITEBACK_INVALIDATE(addr, size) \ - mmu_clean_invalidated_dcache(addr, size) + mmu_clean_invalidated_dcache(addr, size) /* DM644x does not have BD's in cached memory - so no cache functions */ #define BD_CACHE_INVALIDATE(addr, size) @@ -53,34 +53,34 @@ static struct emac_priv davinci_emac_device; static unsigned long emac_bus_frequency; static unsigned long mdio_max_freq; -#define EMAC_AUTONEG_TIMEOUT 5000000 -#define EMAC_LINK_TIMEOUT 500000 +#define EMAC_AUTONEG_TIMEOUT 5000000 +#define EMAC_LINK_TIMEOUT 500000 /* EMAC TX Host Error description strings */ static char *emac_txhost_errcodes[16] = { - "No error", "SOP error", "Ownership bit not set in SOP buffer", - "Zero Next Buffer Descriptor Pointer Without EOP", - "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error", - "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", - "Reserved", "Reserved", "Reserved", "Reserved" + "No error", "SOP error", "Ownership bit not set in SOP buffer", + "Zero Next Buffer Descriptor Pointer Without EOP", + "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error", + "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", + "Reserved", "Reserved", "Reserved", "Reserved" }; /* EMAC RX Host Error description strings */ static char *emac_rxhost_errcodes[16] = { - "No error", "Reserved", "Ownership bit not set in input buffer", - "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved", - "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", - "Reserved", "Reserved", "Reserved", "Reserved" + "No error", "Reserved", "Ownership bit not set in input buffer", + "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved", + "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", + "Reserved", "Reserved", "Reserved", "Reserved" }; -#define emac_read(reg) davinci_readl(priv->emac_base + (reg)) +#define emac_read(reg) davinci_readl(priv->emac_base + (reg)) #define emac_write(reg, val) davinci_writel(val, priv->emac_base + (reg)) -#define emac_ctrl_read(reg) davinci_readl((priv->ctrl_base + (reg))) +#define emac_ctrl_read(reg) davinci_readl((priv->ctrl_base + (reg))) #define emac_ctrl_write(reg, val) davinci_writel(val, (priv->ctrl_base + (reg))) -#define emac_mdio_read(reg) davinci_readl(priv->mdio_base + (reg)) +#define emac_mdio_read(reg) davinci_readl(priv->mdio_base + (reg)) #define emac_mdio_write(reg, val) davinci_writel(val, (priv->mdio_base + (reg))) static void emac_int_enable(struct emac_priv *priv); @@ -91,74 +91,74 @@ static int emac_init_txch(struct emac_priv *priv, rt_uint32_t ch); /* Wait until mdio is ready for next command */ #define MDIO_WAIT_FOR_USER_ACCESS\ - while ((emac_mdio_read((MDIO_USERACCESS(0))) &\ - MDIO_USERACCESS_GO) != 0) + while ((emac_mdio_read((MDIO_USERACCESS(0))) &\ + MDIO_USERACCESS_GO) != 0) static int emac_mii_read(struct emac_priv *priv, int phy_id, int phy_reg) { - unsigned int phy_data = 0; - unsigned int phy_control; + unsigned int phy_data = 0; + unsigned int phy_control; - /* Wait until mdio is ready for next command */ - MDIO_WAIT_FOR_USER_ACCESS; + /* Wait until mdio is ready for next command */ + MDIO_WAIT_FOR_USER_ACCESS; - phy_control = (MDIO_USERACCESS_GO | - MDIO_USERACCESS_READ | - ((phy_reg << 21) & MDIO_USERACCESS_REGADR) | - ((phy_id << 16) & MDIO_USERACCESS_PHYADR) | - (phy_data & MDIO_USERACCESS_DATA)); - emac_mdio_write(MDIO_USERACCESS(0), phy_control); + phy_control = (MDIO_USERACCESS_GO | + MDIO_USERACCESS_READ | + ((phy_reg << 21) & MDIO_USERACCESS_REGADR) | + ((phy_id << 16) & MDIO_USERACCESS_PHYADR) | + (phy_data & MDIO_USERACCESS_DATA)); + emac_mdio_write(MDIO_USERACCESS(0), phy_control); - /* Wait until mdio is ready for next command */ - MDIO_WAIT_FOR_USER_ACCESS; + /* Wait until mdio is ready for next command */ + MDIO_WAIT_FOR_USER_ACCESS; - return emac_mdio_read(MDIO_USERACCESS(0)) & MDIO_USERACCESS_DATA; + return emac_mdio_read(MDIO_USERACCESS(0)) & MDIO_USERACCESS_DATA; } static int emac_mii_write(struct emac_priv *priv, int phy_id, - int phy_reg, rt_uint16_t phy_data) + int phy_reg, rt_uint16_t phy_data) { - unsigned int control; + unsigned int control; - /* until mdio is ready for next command */ - MDIO_WAIT_FOR_USER_ACCESS; + /* until mdio is ready for next command */ + MDIO_WAIT_FOR_USER_ACCESS; - control = (MDIO_USERACCESS_GO | - MDIO_USERACCESS_WRITE | - ((phy_reg << 21) & MDIO_USERACCESS_REGADR) | - ((phy_id << 16) & MDIO_USERACCESS_PHYADR) | - (phy_data & MDIO_USERACCESS_DATA)); - emac_mdio_write(MDIO_USERACCESS(0), control); + control = (MDIO_USERACCESS_GO | + MDIO_USERACCESS_WRITE | + ((phy_reg << 21) & MDIO_USERACCESS_REGADR) | + ((phy_id << 16) & MDIO_USERACCESS_PHYADR) | + (phy_data & MDIO_USERACCESS_DATA)); + emac_mdio_write(MDIO_USERACCESS(0), control); - return 0; + return 0; } static int emac_mii_reset(struct emac_priv *priv) { - unsigned int clk_div; - int mdio_bus_freq = emac_bus_frequency; + unsigned int clk_div; + int mdio_bus_freq = emac_bus_frequency; - if (mdio_max_freq && mdio_bus_freq) - clk_div = ((mdio_bus_freq / mdio_max_freq) - 1); - else - clk_div = 0xFF; + if (mdio_max_freq && mdio_bus_freq) + clk_div = ((mdio_bus_freq / mdio_max_freq) - 1); + else + clk_div = 0xFF; - clk_div &= MDIO_CONTROL_CLKDIV; + clk_div &= MDIO_CONTROL_CLKDIV; - /* Set enable and clock divider in MDIOControl */ - emac_mdio_write(MDIO_CONTROL, (clk_div | MDIO_CONTROL_ENABLE)); + /* Set enable and clock divider in MDIOControl */ + emac_mdio_write(MDIO_CONTROL, (clk_div | MDIO_CONTROL_ENABLE)); - return 0; + return 0; } /* Duplex, half or full. */ -#define DUPLEX_HALF 0x00 -#define DUPLEX_FULL 0x01 +#define DUPLEX_HALF 0x00 +#define DUPLEX_FULL 0x01 static void udelay(rt_uint32_t us) { @@ -169,83 +169,83 @@ static void udelay(rt_uint32_t us) static void davinci_emac_phy_reset(rt_device_t dev) { - int i; - rt_uint16_t status, adv; - struct emac_priv *priv = dev->user_data;; - - adv = ADVERTISE_CSMA | ADVERTISE_ALL; - emac_mii_write(priv, priv->phy_addr, MII_ADVERTISE, adv); - rt_kprintf("%s: Starting autonegotiation...\n", dev->parent.name); - emac_mii_write(priv, priv->phy_addr, MII_BMCR, (BMCR_ANENABLE - | BMCR_ANRESTART)); - - for (i = 0; i < EMAC_AUTONEG_TIMEOUT / 100; i++) { - status = emac_mii_read(priv, priv->phy_addr, MII_BMSR); - if (status & BMSR_ANEGCOMPLETE) - break; - udelay(100); - } - - if (status & BMSR_ANEGCOMPLETE) - rt_kprintf("%s: Autonegotiation complete\n", dev->parent.name); - else - rt_kprintf("%s: Autonegotiation timed out (status=0x%04x)\n", - dev->parent.name, status); + int i; + rt_uint16_t status, adv; + struct emac_priv *priv = dev->user_data;; + + adv = ADVERTISE_CSMA | ADVERTISE_ALL; + emac_mii_write(priv, priv->phy_addr, MII_ADVERTISE, adv); + rt_kprintf("%s: Starting autonegotiation...\n", dev->parent.name); + emac_mii_write(priv, priv->phy_addr, MII_BMCR, (BMCR_ANENABLE + | BMCR_ANRESTART)); + + for (i = 0; i < EMAC_AUTONEG_TIMEOUT / 100; i++) { + status = emac_mii_read(priv, priv->phy_addr, MII_BMSR); + if (status & BMSR_ANEGCOMPLETE) + break; + udelay(100); + } + + if (status & BMSR_ANEGCOMPLETE) + rt_kprintf("%s: Autonegotiation complete\n", dev->parent.name); + else + rt_kprintf("%s: Autonegotiation timed out (status=0x%04x)\n", + dev->parent.name, status); } static int davinci_emac_phy_init(rt_device_t dev) { - struct emac_priv *priv = dev->user_data; - rt_uint16_t phy_id, status, adv, lpa; - int media, speed, duplex; - int i; - - /* Check if the PHY is up to snuff... */ - phy_id = emac_mii_read(priv, priv->phy_addr, MII_PHYSID1); - if (phy_id == 0xffff) { - rt_kprintf("%s: No PHY present\n", dev->parent.name); - return 0; - } - - status = emac_mii_read(priv, priv->phy_addr, MII_BMSR); - if (!(status & BMSR_LSTATUS)) { - /* Try to re-negotiate if we don't have link already. */ - davinci_emac_phy_reset(dev); - - for (i = 0; i < EMAC_LINK_TIMEOUT / 100; i++) { - status = emac_mii_read(priv, priv->phy_addr, MII_BMSR); - if (status & BMSR_LSTATUS) - break; - udelay(100); - } - } - - if (!(status & BMSR_LSTATUS)) { - rt_kprintf("%s: link down (status: 0x%04x)\n", - dev->parent.name, status); - priv->link = 0; - eth_device_linkchange(&priv->parent, RT_FALSE); - return 0; - } else { - adv = emac_mii_read(priv, priv->phy_addr, MII_ADVERTISE); - lpa = emac_mii_read(priv, priv->phy_addr, MII_LPA); - media = mii_nway_result(lpa & adv); - speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) - ? 1 : 0); - duplex = (media & ADVERTISE_FULL) ? 1 : 0; - rt_kprintf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n", - dev->parent.name, - speed ? "100" : "10", - duplex ? "full" : "half", - lpa); - priv->speed = speed; - priv->duplex = duplex; - priv->link = 1; - eth_device_linkchange(&priv->parent, RT_TRUE); - - return 1; - } + struct emac_priv *priv = dev->user_data; + rt_uint16_t phy_id, status, adv, lpa; + int media, speed, duplex; + int i; + + /* Check if the PHY is up to snuff... */ + phy_id = emac_mii_read(priv, priv->phy_addr, MII_PHYSID1); + if (phy_id == 0xffff) { + rt_kprintf("%s: No PHY present\n", dev->parent.name); + return 0; + } + + status = emac_mii_read(priv, priv->phy_addr, MII_BMSR); + if (!(status & BMSR_LSTATUS)) { + /* Try to re-negotiate if we don't have link already. */ + davinci_emac_phy_reset(dev); + + for (i = 0; i < EMAC_LINK_TIMEOUT / 100; i++) { + status = emac_mii_read(priv, priv->phy_addr, MII_BMSR); + if (status & BMSR_LSTATUS) + break; + udelay(100); + } + } + + if (!(status & BMSR_LSTATUS)) { + rt_kprintf("%s: link down (status: 0x%04x)\n", + dev->parent.name, status); + priv->link = 0; + eth_device_linkchange(&priv->parent, RT_FALSE); + return 0; + } else { + adv = emac_mii_read(priv, priv->phy_addr, MII_ADVERTISE); + lpa = emac_mii_read(priv, priv->phy_addr, MII_LPA); + media = mii_nway_result(lpa & adv); + speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) + ? 1 : 0); + duplex = (media & ADVERTISE_FULL) ? 1 : 0; + rt_kprintf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n", + dev->parent.name, + speed ? "100" : "10", + duplex ? "full" : "half", + lpa); + priv->speed = speed; + priv->duplex = duplex; + priv->link = 1; + eth_device_linkchange(&priv->parent, RT_TRUE); + + return 1; + } } /** @@ -258,94 +258,94 @@ static int davinci_emac_phy_init(rt_device_t dev) */ static void emac_update_phystatus(struct emac_priv *priv) { - rt_uint32_t mac_control; - rt_uint32_t new_duplex; - rt_uint32_t cur_duplex; - - mac_control = emac_read(EMAC_MACCONTROL); - cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ? - DUPLEX_FULL : DUPLEX_HALF; - if (priv->phy_mask) - new_duplex = priv->duplex; - else - new_duplex = DUPLEX_FULL; - - /* We get called only if link has changed (speed/duplex/status) */ - if ((priv->link) && (new_duplex != cur_duplex)) { - priv->duplex = new_duplex; - if (DUPLEX_FULL == priv->duplex) - mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN); - else - mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN); - } - - if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) { - mac_control = emac_read(EMAC_MACCONTROL); - mac_control |= (EMAC_DM646X_MACCONTORL_GIG | - EMAC_DM646X_MACCONTORL_GIGFORCE); - } else { - /* Clear the GIG bit and GIGFORCE bit */ - mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE | - EMAC_DM646X_MACCONTORL_GIG); - - if (priv->rmii_en && (priv->speed == SPEED_100)) - mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK; - else - mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK; - } - - /* Update mac_control if changed */ - emac_write(EMAC_MACCONTROL, mac_control); + rt_uint32_t mac_control; + rt_uint32_t new_duplex; + rt_uint32_t cur_duplex; + + mac_control = emac_read(EMAC_MACCONTROL); + cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ? + DUPLEX_FULL : DUPLEX_HALF; + if (priv->phy_mask) + new_duplex = priv->duplex; + else + new_duplex = DUPLEX_FULL; + + /* We get called only if link has changed (speed/duplex/status) */ + if ((priv->link) && (new_duplex != cur_duplex)) { + priv->duplex = new_duplex; + if (DUPLEX_FULL == priv->duplex) + mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN); + else + mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN); + } + + if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) { + mac_control = emac_read(EMAC_MACCONTROL); + mac_control |= (EMAC_DM646X_MACCONTORL_GIG | + EMAC_DM646X_MACCONTORL_GIGFORCE); + } else { + /* Clear the GIG bit and GIGFORCE bit */ + mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE | + EMAC_DM646X_MACCONTORL_GIG); + + if (priv->rmii_en && (priv->speed == SPEED_100)) + mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK; + else + mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK; + } + + /* Update mac_control if changed */ + emac_write(EMAC_MACCONTROL, mac_control); #if 0 - if (priv->link) { - /* link ON */ - /* reactivate the transmit queue if it is stopped */ - } else { - /* link OFF */ - } + if (priv->link) { + /* link ON */ + /* reactivate the transmit queue if it is stopped */ + } else { + /* link OFF */ + } #endif } void davinci_emac_update_link(void *param) { - struct emac_priv *priv = param; - rt_device_t dev = &(priv->parent.parent); - rt_uint32_t status, status_change = 0; - rt_uint32_t link; - rt_uint32_t media; - rt_uint16_t adv, lpa; - - status = emac_mii_read(priv, priv->phy_addr, MII_BMSR); - if ((status & BMSR_LSTATUS) == 0) - link = 0; - else - link = 1; - - if (link != priv->link) { - priv->link = link; - status_change = 1; - } - - if (status_change) { - if (priv->link) { - adv = emac_mii_read(priv, priv->phy_addr, MII_ADVERTISE); - lpa = emac_mii_read(priv, priv->phy_addr, MII_LPA); - media = mii_nway_result(lpa & adv); - priv->speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) - ? 100 : 10); - priv->duplex = (media & ADVERTISE_FULL) ? 1 : 0; - rt_kprintf("%s: link up (%dMbps/%s-duplex)\n", - dev->parent.name, priv->speed, - DUPLEX_FULL == priv->duplex ? "Full":"Half"); - eth_device_linkchange(&priv->parent, RT_TRUE); - } else { - rt_kprintf("%s: link down\n", dev->parent.name); - eth_device_linkchange(&priv->parent, RT_FALSE); - } - emac_update_phystatus(priv); - - } + struct emac_priv *priv = param; + rt_device_t dev = &(priv->parent.parent); + rt_uint32_t status, status_change = 0; + rt_uint32_t link; + rt_uint32_t media; + rt_uint16_t adv, lpa; + + status = emac_mii_read(priv, priv->phy_addr, MII_BMSR); + if ((status & BMSR_LSTATUS) == 0) + link = 0; + else + link = 1; + + if (link != priv->link) { + priv->link = link; + status_change = 1; + } + + if (status_change) { + if (priv->link) { + adv = emac_mii_read(priv, priv->phy_addr, MII_ADVERTISE); + lpa = emac_mii_read(priv, priv->phy_addr, MII_LPA); + media = mii_nway_result(lpa & adv); + priv->speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) + ? 100 : 10); + priv->duplex = (media & ADVERTISE_FULL) ? 1 : 0; + rt_kprintf("%s: link up (%dMbps/%s-duplex)\n", + dev->parent.name, priv->speed, + DUPLEX_FULL == priv->duplex ? "Full":"Half"); + eth_device_linkchange(&priv->parent, RT_TRUE); + } else { + rt_kprintf("%s: link down\n", dev->parent.name); + eth_device_linkchange(&priv->parent, RT_FALSE); + } + emac_update_phystatus(priv); + + } } @@ -361,21 +361,21 @@ void davinci_emac_update_link(void *param) * */ static int emac_net_tx_complete(struct emac_priv *priv, - void **net_data_tokens, - int num_tokens, rt_uint32_t ch) + void **net_data_tokens, + int num_tokens, rt_uint32_t ch) { - rt_uint32_t cnt; - - for (cnt = 0; cnt < num_tokens; cnt++) { - struct pbuf *p = (struct pbuf *)net_data_tokens[cnt]; - if (p == RT_NULL) - continue; - priv->net_dev_stats.tx_packets++; - priv->net_dev_stats.tx_bytes += p->len; - //free pbuf - } - - return 0; + rt_uint32_t cnt; + + for (cnt = 0; cnt < num_tokens; cnt++) { + struct pbuf *p = (struct pbuf *)net_data_tokens[cnt]; + if (p == RT_NULL) + continue; + priv->net_dev_stats.tx_packets++; + priv->net_dev_stats.tx_bytes += p->len; + //free pbuf + } + + return 0; } /** @@ -388,36 +388,36 @@ static int emac_net_tx_complete(struct emac_priv *priv, */ static void emac_txch_teardown(struct emac_priv *priv, rt_uint32_t ch) { - rt_uint32_t teardown_cnt = 0xFFFFFFF0; /* Some high value */ - struct emac_txch *txch = priv->txch[ch]; - struct emac_tx_bd __iomem *curr_bd; - - while ((emac_read(EMAC_TXCP(ch)) & EMAC_TEARDOWN_VALUE) != - EMAC_TEARDOWN_VALUE) { - /* wait till tx teardown complete */ - --teardown_cnt; - if (0 == teardown_cnt) { - rt_kprintf("EMAC: TX teardown aborted\n"); - break; - } - } - emac_write(EMAC_TXCP(ch), EMAC_TEARDOWN_VALUE); - - /* process sent packets and return pbuf's to upper layer */ - if (1 == txch->queue_active) { - curr_bd = txch->active_queue_head; - while (curr_bd != RT_NULL) { - emac_net_tx_complete(priv, (void *) - &curr_bd->buf_token, 1, ch); - if (curr_bd != txch->active_queue_tail) - curr_bd = curr_bd->next; - else - break; - } - txch->bd_pool_head = txch->active_queue_head; - txch->active_queue_head = - txch->active_queue_tail = RT_NULL; - } + rt_uint32_t teardown_cnt = 0xFFFFFFF0; /* Some high value */ + struct emac_txch *txch = priv->txch[ch]; + struct emac_tx_bd __iomem *curr_bd; + + while ((emac_read(EMAC_TXCP(ch)) & EMAC_TEARDOWN_VALUE) != + EMAC_TEARDOWN_VALUE) { + /* wait till tx teardown complete */ + --teardown_cnt; + if (0 == teardown_cnt) { + rt_kprintf("EMAC: TX teardown aborted\n"); + break; + } + } + emac_write(EMAC_TXCP(ch), EMAC_TEARDOWN_VALUE); + + /* process sent packets and return pbuf's to upper layer */ + if (1 == txch->queue_active) { + curr_bd = txch->active_queue_head; + while (curr_bd != RT_NULL) { + emac_net_tx_complete(priv, (void *) + &curr_bd->buf_token, 1, ch); + if (curr_bd != txch->active_queue_tail) + curr_bd = curr_bd->next; + else + break; + } + txch->bd_pool_head = txch->active_queue_head; + txch->active_queue_head = + txch->active_queue_tail = RT_NULL; + } } @@ -431,15 +431,15 @@ static void emac_txch_teardown(struct emac_priv *priv, rt_uint32_t ch) */ static void emac_stop_txch(struct emac_priv *priv, rt_uint32_t ch) { - struct emac_txch *txch = priv->txch[ch]; - - if (txch) { - txch->teardown_pending = 1; - emac_write(EMAC_TXTEARDOWN, 0); - emac_txch_teardown(priv, ch); - txch->teardown_pending = 0; - emac_write(EMAC_TXINTMASKCLEAR, BIT(ch)); - } + struct emac_txch *txch = priv->txch[ch]; + + if (txch) { + txch->teardown_pending = 1; + emac_write(EMAC_TXTEARDOWN, 0); + emac_txch_teardown(priv, ch); + txch->teardown_pending = 0; + emac_write(EMAC_TXINTMASKCLEAR, BIT(ch)); + } } @@ -460,65 +460,65 @@ static void emac_stop_txch(struct emac_priv *priv, rt_uint32_t ch) */ static int emac_tx_bdproc(struct emac_priv *priv, rt_uint32_t ch, rt_uint32_t budget) { - unsigned long flags; - rt_uint32_t frame_status; - rt_uint32_t pkts_processed = 0; - rt_uint32_t tx_complete_cnt = 0; - struct emac_tx_bd __iomem *curr_bd; - struct emac_txch *txch = priv->txch[ch]; - rt_uint32_t *tx_complete_ptr = txch->tx_complete; - - if (1 == txch->teardown_pending) { - rt_kprintf("DaVinci EMAC:emac_tx_bdproc: "\ - "teardown pending\n"); - return 0; /* dont handle any pkt completions */ - } - - ++txch->proc_count; - rt_sem_take(&priv->tx_lock, RT_WAITING_FOREVER); - curr_bd = txch->active_queue_head; - if (RT_NULL == curr_bd) { - emac_write(EMAC_TXCP(ch), - emac_virt_to_phys(txch->last_hw_bdprocessed)); - txch->no_active_pkts++; - rt_sem_release(&priv->tx_lock); - return 0; - } - BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); - frame_status = curr_bd->mode; - while ((curr_bd) && - ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) && - (pkts_processed < budget)) { - emac_write(EMAC_TXCP(ch), emac_virt_to_phys(curr_bd)); - txch->active_queue_head = curr_bd->next; - if (frame_status & EMAC_CPPI_EOQ_BIT) { - if (curr_bd->next) { /* misqueued packet */ - emac_write(EMAC_TXHDP(ch), curr_bd->h_next); - ++txch->mis_queued_packets; - } else { - txch->queue_active = 0; /* end of queue */ - } - } - *tx_complete_ptr = (rt_uint32_t) curr_bd->buf_token; - ++tx_complete_ptr; - ++tx_complete_cnt; - curr_bd->next = txch->bd_pool_head; - txch->bd_pool_head = curr_bd; - --txch->active_queue_count; - pkts_processed++; - txch->last_hw_bdprocessed = curr_bd; - curr_bd = txch->active_queue_head; - if (curr_bd) { - BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); - frame_status = curr_bd->mode; - } - } /* end of pkt processing loop */ - - emac_net_tx_complete(priv, - (void *)&txch->tx_complete[0], - tx_complete_cnt, ch); - rt_sem_release(&priv->tx_lock); - return pkts_processed; + unsigned long flags; + rt_uint32_t frame_status; + rt_uint32_t pkts_processed = 0; + rt_uint32_t tx_complete_cnt = 0; + struct emac_tx_bd __iomem *curr_bd; + struct emac_txch *txch = priv->txch[ch]; + rt_uint32_t *tx_complete_ptr = txch->tx_complete; + + if (1 == txch->teardown_pending) { + rt_kprintf("DaVinci EMAC:emac_tx_bdproc: "\ + "teardown pending\n"); + return 0; /* dont handle any pkt completions */ + } + + ++txch->proc_count; + rt_sem_take(&priv->tx_lock, RT_WAITING_FOREVER); + curr_bd = txch->active_queue_head; + if (RT_NULL == curr_bd) { + emac_write(EMAC_TXCP(ch), + emac_virt_to_phys(txch->last_hw_bdprocessed)); + txch->no_active_pkts++; + rt_sem_release(&priv->tx_lock); + return 0; + } + BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); + frame_status = curr_bd->mode; + while ((curr_bd) && + ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) && + (pkts_processed < budget)) { + emac_write(EMAC_TXCP(ch), emac_virt_to_phys(curr_bd)); + txch->active_queue_head = curr_bd->next; + if (frame_status & EMAC_CPPI_EOQ_BIT) { + if (curr_bd->next) { /* misqueued packet */ + emac_write(EMAC_TXHDP(ch), curr_bd->h_next); + ++txch->mis_queued_packets; + } else { + txch->queue_active = 0; /* end of queue */ + } + } + *tx_complete_ptr = (rt_uint32_t) curr_bd->buf_token; + ++tx_complete_ptr; + ++tx_complete_cnt; + curr_bd->next = txch->bd_pool_head; + txch->bd_pool_head = curr_bd; + --txch->active_queue_count; + pkts_processed++; + txch->last_hw_bdprocessed = curr_bd; + curr_bd = txch->active_queue_head; + if (curr_bd) { + BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); + frame_status = curr_bd->mode; + } + } /* end of pkt processing loop */ + + emac_net_tx_complete(priv, + (void *)&txch->tx_complete[0], + tx_complete_cnt, ch); + rt_sem_release(&priv->tx_lock); + return pkts_processed; } @@ -536,81 +536,81 @@ static int emac_tx_bdproc(struct emac_priv *priv, rt_uint32_t ch, rt_uint32_t bu */ static int emac_send(struct emac_priv *priv, struct emac_netpktobj *pkt, rt_uint32_t ch) { - unsigned long flags; - struct emac_tx_bd __iomem *curr_bd; - struct emac_txch *txch; - struct emac_netbufobj *buf_list; - rt_uint32_t num_pkts = 0; - int retry = 0; - - txch = priv->txch[ch]; - buf_list = pkt->buf_list; /* get handle to the buffer array */ - - /* check packet size and pad if short */ - if (pkt->pkt_length < EMAC_DEF_MIN_ETHPKTSIZE) { - buf_list->length += (EMAC_DEF_MIN_ETHPKTSIZE - pkt->pkt_length); - pkt->pkt_length = EMAC_DEF_MIN_ETHPKTSIZE; - } + unsigned long flags; + struct emac_tx_bd __iomem *curr_bd; + struct emac_txch *txch; + struct emac_netbufobj *buf_list; + rt_uint32_t num_pkts = 0; + int retry = 0; + + txch = priv->txch[ch]; + buf_list = pkt->buf_list; /* get handle to the buffer array */ + + /* check packet size and pad if short */ + if (pkt->pkt_length < EMAC_DEF_MIN_ETHPKTSIZE) { + buf_list->length += (EMAC_DEF_MIN_ETHPKTSIZE - pkt->pkt_length); + pkt->pkt_length = EMAC_DEF_MIN_ETHPKTSIZE; + } try: - rt_sem_take(&priv->tx_lock, RT_WAITING_FOREVER); - curr_bd = txch->bd_pool_head; - if (curr_bd == RT_NULL) { - txch->out_of_tx_bd++; - rt_sem_release(&priv->tx_lock); - num_pkts = emac_tx_bdproc(priv, EMAC_DEF_TX_CH, - EMAC_DEF_TX_MAX_SERVICE); - if (!num_pkts) { - retry++; - if (retry > 5) - return EMAC_ERR_TX_OUT_OF_BD; - rt_thread_delay(1); - } - goto try; - } - - txch->bd_pool_head = curr_bd->next; - curr_bd->buf_token = buf_list->buf_token; - curr_bd->buff_ptr = virt_to_phys(buf_list->data_ptr); - curr_bd->off_b_len = buf_list->length; - curr_bd->h_next = 0; - curr_bd->next = RT_NULL; - curr_bd->mode = (EMAC_CPPI_SOP_BIT | EMAC_CPPI_OWNERSHIP_BIT | - EMAC_CPPI_EOP_BIT | pkt->pkt_length); - - /* flush the packet from cache if write back cache is present */ - BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); - - /* send the packet */ - if (txch->active_queue_head == RT_NULL) { - txch->active_queue_head = curr_bd; - txch->active_queue_tail = curr_bd; - if (1 != txch->queue_active) { - emac_write(EMAC_TXHDP(ch), - emac_virt_to_phys(curr_bd)); - txch->queue_active = 1; - } - ++txch->queue_reinit; - } else { - register struct emac_tx_bd __iomem *tail_bd; - register rt_uint32_t frame_status; - - tail_bd = txch->active_queue_tail; - tail_bd->next = curr_bd; - txch->active_queue_tail = curr_bd; - tail_bd = EMAC_VIRT_NOCACHE(tail_bd); - tail_bd->h_next = (int)emac_virt_to_phys(curr_bd); - frame_status = tail_bd->mode; - if (frame_status & EMAC_CPPI_EOQ_BIT) { - emac_write(EMAC_TXHDP(ch), emac_virt_to_phys(curr_bd)); - frame_status &= ~(EMAC_CPPI_EOQ_BIT); - tail_bd->mode = frame_status; - ++txch->end_of_queue_add; - } - } - txch->active_queue_count++; - rt_sem_release(&priv->tx_lock); - return 0; + rt_sem_take(&priv->tx_lock, RT_WAITING_FOREVER); + curr_bd = txch->bd_pool_head; + if (curr_bd == RT_NULL) { + txch->out_of_tx_bd++; + rt_sem_release(&priv->tx_lock); + num_pkts = emac_tx_bdproc(priv, EMAC_DEF_TX_CH, + EMAC_DEF_TX_MAX_SERVICE); + if (!num_pkts) { + retry++; + if (retry > 5) + return EMAC_ERR_TX_OUT_OF_BD; + rt_thread_delay(1); + } + goto try; + } + + txch->bd_pool_head = curr_bd->next; + curr_bd->buf_token = buf_list->buf_token; + curr_bd->buff_ptr = virt_to_phys(buf_list->data_ptr); + curr_bd->off_b_len = buf_list->length; + curr_bd->h_next = 0; + curr_bd->next = RT_NULL; + curr_bd->mode = (EMAC_CPPI_SOP_BIT | EMAC_CPPI_OWNERSHIP_BIT | + EMAC_CPPI_EOP_BIT | pkt->pkt_length); + + /* flush the packet from cache if write back cache is present */ + BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); + + /* send the packet */ + if (txch->active_queue_head == RT_NULL) { + txch->active_queue_head = curr_bd; + txch->active_queue_tail = curr_bd; + if (1 != txch->queue_active) { + emac_write(EMAC_TXHDP(ch), + emac_virt_to_phys(curr_bd)); + txch->queue_active = 1; + } + ++txch->queue_reinit; + } else { + register struct emac_tx_bd __iomem *tail_bd; + register rt_uint32_t frame_status; + + tail_bd = txch->active_queue_tail; + tail_bd->next = curr_bd; + txch->active_queue_tail = curr_bd; + tail_bd = EMAC_VIRT_NOCACHE(tail_bd); + tail_bd->h_next = (int)emac_virt_to_phys(curr_bd); + frame_status = tail_bd->mode; + if (frame_status & EMAC_CPPI_EOQ_BIT) { + emac_write(EMAC_TXHDP(ch), emac_virt_to_phys(curr_bd)); + frame_status &= ~(EMAC_CPPI_EOQ_BIT); + tail_bd->mode = frame_status; + ++txch->end_of_queue_add; + } + } + txch->active_queue_count++; + rt_sem_release(&priv->tx_lock); + return 0; } /** @@ -625,40 +625,40 @@ try: */ static int emac_dev_xmit(struct pbuf *p, struct emac_priv *priv) { - int ret_code; - struct emac_netbufobj tx_buf; /* buffer obj-only single frame support */ - struct emac_netpktobj tx_packet; /* packet object */ - - /* If no link, return */ - if (!priv->link) { - rt_kprintf("DaVinci EMAC: No link to transmit\n"); - return -RT_EBUSY; - } - - /* Build the buffer and packet objects - Since only single fragment is - * supported, need not set length and token in both packet & object. - * Doing so for completeness sake & to show that this needs to be done - * in multifragment case - */ - tx_packet.buf_list = &tx_buf; - tx_packet.num_bufs = 1; /* only single fragment supported */ - tx_packet.pkt_length = p->len; - tx_packet.pkt_token = (void *)p; - tx_buf.length = p->len; - tx_buf.buf_token = (void *)p; - tx_buf.data_ptr = p->payload; - EMAC_CACHE_WRITEBACK((unsigned long)p->payload, p->len); - ret_code = emac_send(priv, &tx_packet, EMAC_DEF_TX_CH); - if (ret_code != 0) { - if (ret_code == EMAC_ERR_TX_OUT_OF_BD) { - rt_kprintf("DaVinci EMAC: xmit() fatal"\ - " err. Out of TX BD's\n"); - } - priv->net_dev_stats.tx_dropped++; - return -RT_EBUSY; - } - - return RT_EOK; + int ret_code; + struct emac_netbufobj tx_buf; /* buffer obj-only single frame support */ + struct emac_netpktobj tx_packet; /* packet object */ + + /* If no link, return */ + if (!priv->link) { + rt_kprintf("DaVinci EMAC: No link to transmit\n"); + return -RT_EBUSY; + } + + /* Build the buffer and packet objects - Since only single fragment is + * supported, need not set length and token in both packet & object. + * Doing so for completeness sake & to show that this needs to be done + * in multifragment case + */ + tx_packet.buf_list = &tx_buf; + tx_packet.num_bufs = 1; /* only single fragment supported */ + tx_packet.pkt_length = p->len; + tx_packet.pkt_token = (void *)p; + tx_buf.length = p->len; + tx_buf.buf_token = (void *)p; + tx_buf.data_ptr = p->payload; + EMAC_CACHE_WRITEBACK((unsigned long)p->payload, p->len); + ret_code = emac_send(priv, &tx_packet, EMAC_DEF_TX_CH); + if (ret_code != 0) { + if (ret_code == EMAC_ERR_TX_OUT_OF_BD) { + rt_kprintf("DaVinci EMAC: xmit() fatal"\ + " err. Out of TX BD's\n"); + } + priv->net_dev_stats.tx_dropped++; + return -RT_EBUSY; + } + + return RT_EOK; } /** @@ -671,15 +671,15 @@ static int emac_dev_xmit(struct pbuf *p, struct emac_priv *priv) */ static void emac_cleanup_txch(struct emac_priv *priv, rt_uint32_t ch) { - struct emac_txch *txch = priv->txch[ch]; - - if (txch) { - if (txch->bd_mem) - txch->bd_mem = NULL; - rt_free(txch->tx_complete); - rt_free(txch); - priv->txch[ch] = NULL; - } + struct emac_txch *txch = priv->txch[ch]; + + if (txch) { + if (txch->bd_mem) + txch->bd_mem = NULL; + rt_free(txch->tx_complete); + rt_free(txch); + priv->txch[ch] = NULL; + } } @@ -695,15 +695,15 @@ static void emac_cleanup_txch(struct emac_priv *priv, rt_uint32_t ch) */ static void emac_dev_tx_timeout(struct emac_priv *priv) { - rt_kprintf("emac tx timeout.\n"); - priv->net_dev_stats.tx_errors++; - emac_int_disable(priv); - emac_stop_txch(priv, EMAC_DEF_TX_CH); - emac_cleanup_txch(priv, EMAC_DEF_TX_CH); - emac_init_txch(priv, EMAC_DEF_TX_CH); - emac_write(EMAC_TXHDP(0), 0); - emac_write(EMAC_TXINTMASKSET, BIT(EMAC_DEF_TX_CH)); - emac_int_enable(priv); + rt_kprintf("emac tx timeout.\n"); + priv->net_dev_stats.tx_errors++; + emac_int_disable(priv); + emac_stop_txch(priv, EMAC_DEF_TX_CH); + emac_cleanup_txch(priv, EMAC_DEF_TX_CH); + emac_init_txch(priv, EMAC_DEF_TX_CH); + emac_write(EMAC_TXHDP(0), 0); + emac_write(EMAC_TXINTMASKSET, BIT(EMAC_DEF_TX_CH)); + emac_int_enable(priv); } @@ -711,16 +711,16 @@ static void emac_dev_tx_timeout(struct emac_priv *priv) /* transmit packet. */ rt_err_t rt_davinci_emac_tx( rt_device_t dev, struct pbuf* p) { - rt_err_t err; - struct emac_priv *priv = dev->user_data; + rt_err_t err; + struct emac_priv *priv = dev->user_data; - err = emac_dev_xmit(p, priv); - if (err != RT_EOK) - { - emac_dev_tx_timeout(priv); - } + err = emac_dev_xmit(p, priv); + if (err != RT_EOK) + { + emac_dev_tx_timeout(priv); + } - return RT_EOK; + return RT_EOK; } /** @@ -737,49 +737,49 @@ rt_err_t rt_davinci_emac_tx( rt_device_t dev, struct pbuf* p) * */ static void emac_addbd_to_rx_queue(struct emac_priv *priv, rt_uint32_t ch, - struct emac_rx_bd __iomem *curr_bd, - char *buffer, void *buf_token) + struct emac_rx_bd __iomem *curr_bd, + char *buffer, void *buf_token) { - struct emac_rxch *rxch = priv->rxch[ch]; - - /* populate the hardware descriptor */ - curr_bd->h_next = 0; - curr_bd->buff_ptr = virt_to_phys(buffer); - curr_bd->off_b_len = rxch->buf_size; - curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT; - curr_bd->next = RT_NULL; - curr_bd->data_ptr = buffer; - curr_bd->buf_token = buf_token; - - /* write back */ - BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); - if (rxch->active_queue_head == RT_NULL) { - rxch->active_queue_head = curr_bd; - rxch->active_queue_tail = curr_bd; - if (0 != rxch->queue_active) { - emac_write(EMAC_RXHDP(ch), - emac_virt_to_phys(rxch->active_queue_head)); - rxch->queue_active = 1; - } - } else { - struct emac_rx_bd __iomem *tail_bd; - rt_uint32_t frame_status; - - tail_bd = rxch->active_queue_tail; - rxch->active_queue_tail = curr_bd; - tail_bd->next = curr_bd; - tail_bd = EMAC_VIRT_NOCACHE(tail_bd); - tail_bd->h_next = emac_virt_to_phys(curr_bd); - frame_status = tail_bd->mode; - if (frame_status & EMAC_CPPI_EOQ_BIT) { - emac_write(EMAC_RXHDP(ch), - emac_virt_to_phys(curr_bd)); - frame_status &= ~(EMAC_CPPI_EOQ_BIT); - tail_bd->mode = frame_status; - ++rxch->end_of_queue_add; - } - } - ++rxch->recycled_bd; + struct emac_rxch *rxch = priv->rxch[ch]; + + /* populate the hardware descriptor */ + curr_bd->h_next = 0; + curr_bd->buff_ptr = virt_to_phys(buffer); + curr_bd->off_b_len = rxch->buf_size; + curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT; + curr_bd->next = RT_NULL; + curr_bd->data_ptr = buffer; + curr_bd->buf_token = buf_token; + + /* write back */ + BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); + if (rxch->active_queue_head == RT_NULL) { + rxch->active_queue_head = curr_bd; + rxch->active_queue_tail = curr_bd; + if (0 != rxch->queue_active) { + emac_write(EMAC_RXHDP(ch), + emac_virt_to_phys(rxch->active_queue_head)); + rxch->queue_active = 1; + } + } else { + struct emac_rx_bd __iomem *tail_bd; + rt_uint32_t frame_status; + + tail_bd = rxch->active_queue_tail; + rxch->active_queue_tail = curr_bd; + tail_bd->next = curr_bd; + tail_bd = EMAC_VIRT_NOCACHE(tail_bd); + tail_bd->h_next = emac_virt_to_phys(curr_bd); + frame_status = tail_bd->mode; + if (frame_status & EMAC_CPPI_EOQ_BIT) { + emac_write(EMAC_RXHDP(ch), + emac_virt_to_phys(curr_bd)); + frame_status &= ~(EMAC_CPPI_EOQ_BIT); + tail_bd->mode = frame_status; + ++rxch->end_of_queue_add; + } + } + ++rxch->recycled_bd; } /** @@ -793,22 +793,22 @@ static void emac_addbd_to_rx_queue(struct emac_priv *priv, rt_uint32_t ch, * Returns success or appropriate error code (none as of now) */ static int emac_net_rx_cb(struct emac_priv *priv, - struct emac_netpktobj *net_pkt_list) + struct emac_netpktobj *net_pkt_list) { - struct eth_device *device = &priv->parent; - struct pbuf *p; - p = (struct pbuf *)net_pkt_list->pkt_token; - /* set length of packet */ - p->tot_len = net_pkt_list->pkt_length; - p->len = net_pkt_list->pkt_length; - EMAC_CACHE_INVALIDATE((unsigned long)p->payload, p->len); - if (device->netif->input(p, device->netif) != RT_EOK) - { - pbuf_free(p); - } - priv->net_dev_stats.rx_bytes += net_pkt_list->pkt_length; - priv->net_dev_stats.rx_packets++; - return 0; + struct eth_device *device = &priv->parent; + struct pbuf *p; + p = (struct pbuf *)net_pkt_list->pkt_token; + /* set length of packet */ + p->tot_len = net_pkt_list->pkt_length; + p->len = net_pkt_list->pkt_length; + EMAC_CACHE_INVALIDATE((unsigned long)p->payload, p->len); + if (device->netif->input(p, device->netif) != RT_EOK) + { + pbuf_free(p); + } + priv->net_dev_stats.rx_bytes += net_pkt_list->pkt_length; + priv->net_dev_stats.rx_packets++; + return 0; } /** @@ -824,20 +824,20 @@ static int emac_net_rx_cb(struct emac_priv *priv, * Returns pbuf data pointer or 0 on failure to alloc pbuf */ static void *emac_net_alloc_rx_buf(struct emac_priv *priv, int buf_size, - void **data_token, rt_uint32_t ch) + void **data_token, rt_uint32_t ch) { - struct pbuf* p; - - p = pbuf_alloc(PBUF_LINK, buf_size, PBUF_RAM); - if (RT_NULL == p) { - rt_kprintf("DaVinci EMAC: failed to alloc pbuf\n"); - return RT_NULL; - } - - /* set device pointer in p and reserve space for extra bytes */ - *data_token = (void *) p; - EMAC_CACHE_WRITEBACK_INVALIDATE((unsigned long)p->payload, buf_size); - return p->payload; + struct pbuf* p; + + p = pbuf_alloc(PBUF_LINK, buf_size, PBUF_RAM); + if (RT_NULL == p) { + rt_kprintf("DaVinci EMAC: failed to alloc pbuf\n"); + return RT_NULL; + } + + /* set device pointer in p and reserve space for extra bytes */ + *data_token = (void *) p; + EMAC_CACHE_WRITEBACK_INVALIDATE((unsigned long)p->payload, buf_size); + return p->payload; } @@ -857,160 +857,160 @@ static void *emac_net_alloc_rx_buf(struct emac_priv *priv, int buf_size, */ static int emac_rx_bdproc(struct emac_priv *priv, rt_uint32_t ch, rt_uint32_t budget) { - unsigned long flags; - rt_uint32_t frame_status; - rt_uint32_t pkts_processed = 0; - char *new_buffer; - struct emac_rx_bd __iomem *curr_bd; - struct emac_rx_bd __iomem *last_bd; - struct emac_netpktobj *curr_pkt, pkt_obj; - struct emac_netbufobj buf_obj; - struct emac_netbufobj *rx_buf_obj; - void *new_buf_token; - struct emac_rxch *rxch = priv->rxch[ch]; - - if (1 == rxch->teardown_pending) - return 0; - ++rxch->proc_count; - rt_sem_take(&priv->rx_lock, RT_WAITING_FOREVER); - pkt_obj.buf_list = &buf_obj; - curr_pkt = &pkt_obj; - curr_bd = rxch->active_queue_head; - BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); - frame_status = curr_bd->mode; - - while ((curr_bd) && - ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) && - (pkts_processed < budget)) { - - new_buffer = emac_net_alloc_rx_buf(priv, rxch->buf_size, - &new_buf_token, EMAC_DEF_RX_CH); - if (RT_NULL == new_buffer) { - ++rxch->out_of_rx_buffers; - goto end_emac_rx_bdproc; - } - - /* populate received packet data structure */ - rx_buf_obj = &curr_pkt->buf_list[0]; - rx_buf_obj->data_ptr = (char *)curr_bd->data_ptr; - rx_buf_obj->length = curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE; - rx_buf_obj->buf_token = curr_bd->buf_token; - curr_pkt->pkt_token = curr_pkt->buf_list->buf_token; - curr_pkt->num_bufs = 1; - curr_pkt->pkt_length = - (frame_status & EMAC_RX_BD_PKT_LENGTH_MASK); - emac_write(EMAC_RXCP(ch), emac_virt_to_phys(curr_bd)); - ++rxch->processed_bd; - last_bd = curr_bd; - curr_bd = last_bd->next; - rxch->active_queue_head = curr_bd; - - /* check if end of RX queue ? */ - if (frame_status & EMAC_CPPI_EOQ_BIT) { - if (curr_bd) { - ++rxch->mis_queued_packets; - emac_write(EMAC_RXHDP(ch), - emac_virt_to_phys(curr_bd)); - } else { - ++rxch->end_of_queue; - rxch->queue_active = 0; - } - } - - /* recycle BD */ - emac_addbd_to_rx_queue(priv, ch, last_bd, new_buffer, - new_buf_token); - - /* return the packet to the user - BD ptr passed in - * last parameter for potential *future* use */ - rt_sem_release(&priv->rx_lock); - emac_net_rx_cb(priv, curr_pkt);//??? - rt_sem_take(&priv->rx_lock, RT_WAITING_FOREVER); - curr_bd = rxch->active_queue_head; - if (curr_bd) { - BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); - frame_status = curr_bd->mode; - } - ++pkts_processed; - } + unsigned long flags; + rt_uint32_t frame_status; + rt_uint32_t pkts_processed = 0; + char *new_buffer; + struct emac_rx_bd __iomem *curr_bd; + struct emac_rx_bd __iomem *last_bd; + struct emac_netpktobj *curr_pkt, pkt_obj; + struct emac_netbufobj buf_obj; + struct emac_netbufobj *rx_buf_obj; + void *new_buf_token; + struct emac_rxch *rxch = priv->rxch[ch]; + + if (1 == rxch->teardown_pending) + return 0; + ++rxch->proc_count; + rt_sem_take(&priv->rx_lock, RT_WAITING_FOREVER); + pkt_obj.buf_list = &buf_obj; + curr_pkt = &pkt_obj; + curr_bd = rxch->active_queue_head; + BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); + frame_status = curr_bd->mode; + + while ((curr_bd) && + ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) && + (pkts_processed < budget)) { + + new_buffer = emac_net_alloc_rx_buf(priv, rxch->buf_size, + &new_buf_token, EMAC_DEF_RX_CH); + if (RT_NULL == new_buffer) { + ++rxch->out_of_rx_buffers; + goto end_emac_rx_bdproc; + } + + /* populate received packet data structure */ + rx_buf_obj = &curr_pkt->buf_list[0]; + rx_buf_obj->data_ptr = (char *)curr_bd->data_ptr; + rx_buf_obj->length = curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE; + rx_buf_obj->buf_token = curr_bd->buf_token; + curr_pkt->pkt_token = curr_pkt->buf_list->buf_token; + curr_pkt->num_bufs = 1; + curr_pkt->pkt_length = + (frame_status & EMAC_RX_BD_PKT_LENGTH_MASK); + emac_write(EMAC_RXCP(ch), emac_virt_to_phys(curr_bd)); + ++rxch->processed_bd; + last_bd = curr_bd; + curr_bd = last_bd->next; + rxch->active_queue_head = curr_bd; + + /* check if end of RX queue ? */ + if (frame_status & EMAC_CPPI_EOQ_BIT) { + if (curr_bd) { + ++rxch->mis_queued_packets; + emac_write(EMAC_RXHDP(ch), + emac_virt_to_phys(curr_bd)); + } else { + ++rxch->end_of_queue; + rxch->queue_active = 0; + } + } + + /* recycle BD */ + emac_addbd_to_rx_queue(priv, ch, last_bd, new_buffer, + new_buf_token); + + /* return the packet to the user - BD ptr passed in + * last parameter for potential *future* use */ + rt_sem_release(&priv->rx_lock); + emac_net_rx_cb(priv, curr_pkt);//??? + rt_sem_take(&priv->rx_lock, RT_WAITING_FOREVER); + curr_bd = rxch->active_queue_head; + if (curr_bd) { + BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); + frame_status = curr_bd->mode; + } + ++pkts_processed; + } end_emac_rx_bdproc: - rt_sem_release(&priv->rx_lock); - return pkts_processed; + rt_sem_release(&priv->rx_lock); + return pkts_processed; } /* reception packet. */ struct pbuf *rt_davinci_emac_rx(rt_device_t dev) { - struct emac_priv *priv = dev->user_data; - struct pbuf* p = RT_NULL; - rt_uint32_t len; - void *buffer; - - struct pbuf* q; - rt_uint8_t *buf = RT_NULL; - unsigned int mask; - rt_uint32_t status = 0; - rt_uint32_t num_pkts = 0; - - /* Check interrupt vectors and call packet processing */ - status = emac_read(EMAC_MACINVECTOR); - - mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC; - - if (priv->version == EMAC_VERSION_2) - mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC; - - if (status & mask) { - num_pkts = emac_tx_bdproc(priv, EMAC_DEF_TX_CH, - EMAC_DEF_TX_MAX_SERVICE); - } /* TX processing */ - - /*if (num_pkts) - //return budget; - return RT_NULL;*/ - - mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC; - - if (priv->version == EMAC_VERSION_2) - mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC; - - if (status & mask) { - num_pkts = emac_rx_bdproc(priv, EMAC_DEF_RX_CH, EMAC_DEF_RX_MAX_SERVICE); - } /* RX processing */ - - /*if (num_pkts < EMAC_DEF_RX_MAX_SERVICE) { - emac_int_enable(priv); - }*/ - - mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT; - if (priv->version == EMAC_VERSION_2) - mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT; - - if (status & mask) { - rt_uint32_t ch, cause; - rt_kprintf("DaVinci EMAC: Fatal Hardware Error\n"); - - status = emac_read(EMAC_MACSTATUS); - cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >> - EMAC_MACSTATUS_TXERRCODE_SHIFT); - if (cause) { - ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >> - EMAC_MACSTATUS_TXERRCH_SHIFT); - } - cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >> - EMAC_MACSTATUS_RXERRCODE_SHIFT); - if (cause) { - ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >> - EMAC_MACSTATUS_RXERRCH_SHIFT); - } - } /* Host error processing */ - - //return num_pkts; - //return p; - emac_int_enable(priv); - return RT_NULL; + struct emac_priv *priv = dev->user_data; + struct pbuf* p = RT_NULL; + rt_uint32_t len; + void *buffer; + + struct pbuf* q; + rt_uint8_t *buf = RT_NULL; + unsigned int mask; + rt_uint32_t status = 0; + rt_uint32_t num_pkts = 0; + + /* Check interrupt vectors and call packet processing */ + status = emac_read(EMAC_MACINVECTOR); + + mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC; + + if (priv->version == EMAC_VERSION_2) + mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC; + + if (status & mask) { + num_pkts = emac_tx_bdproc(priv, EMAC_DEF_TX_CH, + EMAC_DEF_TX_MAX_SERVICE); + } /* TX processing */ + + /*if (num_pkts) + //return budget; + return RT_NULL;*/ + + mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC; + + if (priv->version == EMAC_VERSION_2) + mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC; + + if (status & mask) { + num_pkts = emac_rx_bdproc(priv, EMAC_DEF_RX_CH, EMAC_DEF_RX_MAX_SERVICE); + } /* RX processing */ + + /*if (num_pkts < EMAC_DEF_RX_MAX_SERVICE) { + emac_int_enable(priv); + }*/ + + mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT; + if (priv->version == EMAC_VERSION_2) + mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT; + + if (status & mask) { + rt_uint32_t ch, cause; + rt_kprintf("DaVinci EMAC: Fatal Hardware Error\n"); + + status = emac_read(EMAC_MACSTATUS); + cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >> + EMAC_MACSTATUS_TXERRCODE_SHIFT); + if (cause) { + ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >> + EMAC_MACSTATUS_TXERRCH_SHIFT); + } + cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >> + EMAC_MACSTATUS_RXERRCODE_SHIFT); + if (cause) { + ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >> + EMAC_MACSTATUS_RXERRCH_SHIFT); + } + } /* Host error processing */ + + //return num_pkts; + //return p; + emac_int_enable(priv); + return RT_NULL; } @@ -1026,19 +1026,19 @@ struct pbuf *rt_davinci_emac_rx(rt_device_t dev) */ static void emac_set_type0addr(struct emac_priv *priv, rt_uint32_t ch, char *mac_addr) { - rt_uint32_t val; - val = ((mac_addr[5] << 8) | (mac_addr[4])); - emac_write(EMAC_MACSRCADDRLO, val); - - val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ - (mac_addr[1] << 8) | (mac_addr[0])); - emac_write(EMAC_MACSRCADDRHI, val); - val = emac_read(EMAC_RXUNICASTSET); - val |= BIT(ch); - emac_write(EMAC_RXUNICASTSET, val); - val = emac_read(EMAC_RXUNICASTCLEAR); - val &= ~BIT(ch); - emac_write(EMAC_RXUNICASTCLEAR, val); + rt_uint32_t val; + val = ((mac_addr[5] << 8) | (mac_addr[4])); + emac_write(EMAC_MACSRCADDRLO, val); + + val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ + (mac_addr[1] << 8) | (mac_addr[0])); + emac_write(EMAC_MACSRCADDRHI, val); + val = emac_read(EMAC_RXUNICASTSET); + val |= BIT(ch); + emac_write(EMAC_RXUNICASTSET, val); + val = emac_read(EMAC_RXUNICASTCLEAR); + val &= ~BIT(ch); + emac_write(EMAC_RXUNICASTCLEAR, val); } /** @@ -1053,14 +1053,14 @@ static void emac_set_type0addr(struct emac_priv *priv, rt_uint32_t ch, char *mac */ static void emac_set_type1addr(struct emac_priv *priv, rt_uint32_t ch, char *mac_addr) { - rt_uint32_t val; - emac_write(EMAC_MACINDEX, ch); - val = ((mac_addr[5] << 8) | mac_addr[4]); - emac_write(EMAC_MACADDRLO, val); - val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ - (mac_addr[1] << 8) | (mac_addr[0])); - emac_write(EMAC_MACADDRHI, val); - emac_set_type0addr(priv, ch, mac_addr); + rt_uint32_t val; + emac_write(EMAC_MACINDEX, ch); + val = ((mac_addr[5] << 8) | mac_addr[4]); + emac_write(EMAC_MACADDRLO, val); + val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ + (mac_addr[1] << 8) | (mac_addr[0])); + emac_write(EMAC_MACADDRHI, val); + emac_set_type0addr(priv, ch, mac_addr); } /** @@ -1076,17 +1076,17 @@ static void emac_set_type1addr(struct emac_priv *priv, rt_uint32_t ch, char *mac * Returns success (0) or appropriate error code (none as of now) */ static void emac_set_type2addr(struct emac_priv *priv, rt_uint32_t ch, - char *mac_addr, int index, int match) + char *mac_addr, int index, int match) { - rt_uint32_t val; - emac_write(EMAC_MACINDEX, index); - val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ - (mac_addr[1] << 8) | (mac_addr[0])); - emac_write(EMAC_MACADDRHI, val); - val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \ - (match << 19) | BIT(20)); - emac_write(EMAC_MACADDRLO, val); - emac_set_type0addr(priv, ch, mac_addr); + rt_uint32_t val; + emac_write(EMAC_MACINDEX, index); + val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ + (mac_addr[1] << 8) | (mac_addr[0])); + emac_write(EMAC_MACADDRHI, val); + val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \ + (match << 19) | BIT(20)); + emac_write(EMAC_MACADDRLO, val); + emac_set_type0addr(priv, ch, mac_addr); } /** @@ -1101,18 +1101,18 @@ static void emac_set_type2addr(struct emac_priv *priv, rt_uint32_t ch, */ static void emac_setmac(struct emac_priv *priv, rt_uint32_t ch, char *mac_addr) { - if (priv->rx_addr_type == 0) { - emac_set_type0addr(priv, ch, mac_addr); - } else if (priv->rx_addr_type == 1) { - rt_uint32_t cnt; - for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++) - emac_set_type1addr(priv, ch, mac_addr); - } else if (priv->rx_addr_type == 2) { - emac_set_type2addr(priv, ch, mac_addr, ch, 1); - emac_set_type0addr(priv, ch, mac_addr); - } else { - rt_kprintf("DaVinci EMAC: Wrong addressing\n"); - } + if (priv->rx_addr_type == 0) { + emac_set_type0addr(priv, ch, mac_addr); + } else if (priv->rx_addr_type == 1) { + rt_uint32_t cnt; + for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++) + emac_set_type1addr(priv, ch, mac_addr); + } else if (priv->rx_addr_type == 2) { + emac_set_type2addr(priv, ch, mac_addr, ch, 1); + emac_set_type0addr(priv, ch, mac_addr); + } else { + rt_kprintf("DaVinci EMAC: Wrong addressing\n"); + } } @@ -1125,9 +1125,9 @@ static void emac_setmac(struct emac_priv *priv, rt_uint32_t ch, char *mac_addr) * pointer to the memory * */ -#define EMAC_TX_BD_MEM(priv) ((priv)->emac_ctrl_ram) -#define EMAC_RX_BD_MEM(priv) ((priv)->emac_ctrl_ram + \ - (((priv)->ctrl_ram_size) >> 1)) +#define EMAC_TX_BD_MEM(priv) ((priv)->emac_ctrl_ram) +#define EMAC_RX_BD_MEM(priv) ((priv)->emac_ctrl_ram + \ + (((priv)->ctrl_ram_size) >> 1)) /** * emac_init_txch: TX channel initialization @@ -1141,59 +1141,59 @@ static void emac_setmac(struct emac_priv *priv, rt_uint32_t ch, char *mac_addr) */ static int emac_init_txch(struct emac_priv *priv, rt_uint32_t ch) { - rt_uint32_t cnt, bd_size; - void __iomem *mem; - struct emac_tx_bd __iomem *curr_bd; - struct emac_txch *txch = RT_NULL; - - txch = rt_malloc(sizeof(struct emac_txch)); - if (RT_NULL == txch) { - rt_kprintf("DaVinci EMAC: TX Ch mem alloc failed"); - return -RT_ENOMEM; - } - rt_memset(txch, 0, sizeof(struct emac_txch)); - priv->txch[ch] = txch; - txch->service_max = EMAC_DEF_TX_MAX_SERVICE; - txch->active_queue_head = RT_NULL; - txch->active_queue_tail = RT_NULL; - txch->queue_active = 0; - txch->teardown_pending = 0; - - /* allocate memory for TX CPPI channel on a 4 byte boundry */ - txch->tx_complete = rt_malloc(txch->service_max * sizeof(rt_uint32_t)); - if (RT_NULL == txch->tx_complete) { - rt_kprintf("DaVinci EMAC: Tx service mem alloc failed"); - rt_free(txch); - return -RT_ENOMEM; - } - memset(txch->tx_complete, 0, txch->service_max * sizeof(rt_uint32_t)); - - /* allocate buffer descriptor pool align every BD on four word - * boundry for future requirements */ - bd_size = (sizeof(struct emac_tx_bd) + 0xF) & ~0xF; - txch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size; - txch->alloc_size = (((bd_size * txch->num_bd) + 0xF) & ~0xF); - - /* alloc TX BD memory */ - txch->bd_mem = EMAC_TX_BD_MEM(priv); - rt_memset((void *)txch->bd_mem, 0, txch->alloc_size); - - /* initialize the BD linked list */ - mem = (void __iomem *) - (((rt_uint32_t) txch->bd_mem + 0xF) & ~0xF); - txch->bd_pool_head = RT_NULL; - for (cnt = 0; cnt < txch->num_bd; cnt++) { - curr_bd = mem + (cnt * bd_size); - curr_bd->next = txch->bd_pool_head; - txch->bd_pool_head = curr_bd; - } - - /* reset statistics counters */ - txch->out_of_tx_bd = 0; - txch->no_active_pkts = 0; - txch->active_queue_count = 0; - - return 0; + rt_uint32_t cnt, bd_size; + void __iomem *mem; + struct emac_tx_bd __iomem *curr_bd; + struct emac_txch *txch = RT_NULL; + + txch = rt_malloc(sizeof(struct emac_txch)); + if (RT_NULL == txch) { + rt_kprintf("DaVinci EMAC: TX Ch mem alloc failed"); + return -RT_ENOMEM; + } + rt_memset(txch, 0, sizeof(struct emac_txch)); + priv->txch[ch] = txch; + txch->service_max = EMAC_DEF_TX_MAX_SERVICE; + txch->active_queue_head = RT_NULL; + txch->active_queue_tail = RT_NULL; + txch->queue_active = 0; + txch->teardown_pending = 0; + + /* allocate memory for TX CPPI channel on a 4 byte boundry */ + txch->tx_complete = rt_malloc(txch->service_max * sizeof(rt_uint32_t)); + if (RT_NULL == txch->tx_complete) { + rt_kprintf("DaVinci EMAC: Tx service mem alloc failed"); + rt_free(txch); + return -RT_ENOMEM; + } + memset(txch->tx_complete, 0, txch->service_max * sizeof(rt_uint32_t)); + + /* allocate buffer descriptor pool align every BD on four word + * boundry for future requirements */ + bd_size = (sizeof(struct emac_tx_bd) + 0xF) & ~0xF; + txch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size; + txch->alloc_size = (((bd_size * txch->num_bd) + 0xF) & ~0xF); + + /* alloc TX BD memory */ + txch->bd_mem = EMAC_TX_BD_MEM(priv); + rt_memset((void *)txch->bd_mem, 0, txch->alloc_size); + + /* initialize the BD linked list */ + mem = (void __iomem *) + (((rt_uint32_t) txch->bd_mem + 0xF) & ~0xF); + txch->bd_pool_head = RT_NULL; + for (cnt = 0; cnt < txch->num_bd; cnt++) { + curr_bd = mem + (cnt * bd_size); + curr_bd->next = txch->bd_pool_head; + txch->bd_pool_head = curr_bd; + } + + /* reset statistics counters */ + txch->out_of_tx_bd = 0; + txch->no_active_pkts = 0; + txch->active_queue_count = 0; + + return 0; } /** @@ -1209,74 +1209,74 @@ static int emac_init_txch(struct emac_priv *priv, rt_uint32_t ch) */ static int emac_init_rxch(struct emac_priv *priv, rt_uint32_t ch, char *param) { - rt_uint32_t cnt, bd_size; - void __iomem *mem; - struct emac_rx_bd __iomem *curr_bd; - struct emac_rxch *rxch = RT_NULL; - - rxch = rt_malloc(sizeof(struct emac_rxch)); - if (RT_NULL == rxch) { - rt_kprintf("DaVinci EMAC: RX Ch mem alloc failed"); - return -ENOMEM; - } - rt_memset(rxch, 0, sizeof(struct emac_rxch)); - priv->rxch[ch] = rxch; - rxch->buf_size = priv->rx_buf_size; - rxch->service_max = EMAC_DEF_RX_MAX_SERVICE; - rxch->queue_active = 0; - rxch->teardown_pending = 0; - - /* save mac address */ - for (cnt = 0; cnt < 6; cnt++) - rxch->mac_addr[cnt] = param[cnt]; - - /* allocate buffer descriptor pool align every BD on four word - * boundry for future requirements */ - bd_size = (sizeof(struct emac_rx_bd) + 0xF) & ~0xF; - rxch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size; - rxch->alloc_size = (((bd_size * rxch->num_bd) + 0xF) & ~0xF); - rxch->bd_mem = EMAC_RX_BD_MEM(priv); - - rt_memset((void *)rxch->bd_mem, 0, rxch->alloc_size); - rxch->pkt_queue.buf_list = &rxch->buf_queue; - - /* allocate RX buffer and initialize the BD linked list */ - mem = (void __iomem *) - (((rt_uint32_t) rxch->bd_mem + 0xF) & ~0xF); - rxch->active_queue_head = RT_NULL; - rxch->active_queue_tail = mem; - for (cnt = 0; cnt < rxch->num_bd; cnt++) { - curr_bd = mem + (cnt * bd_size); - /* for future use the last parameter contains the BD ptr */ - curr_bd->data_ptr = emac_net_alloc_rx_buf(priv, - rxch->buf_size, - (void **)&curr_bd->buf_token, - EMAC_DEF_RX_CH); - if (curr_bd->data_ptr == RT_NULL) { - rt_kprintf("DaVinci EMAC: RX buf mem alloc " \ - "failed for ch %d\n", ch); - rt_free(rxch); - return -RT_ENOMEM; - } - - /* populate the hardware descriptor */ - curr_bd->h_next = emac_virt_to_phys(rxch->active_queue_head); - curr_bd->buff_ptr = virt_to_phys(curr_bd->data_ptr); - curr_bd->off_b_len = rxch->buf_size; - curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT; - - /* write back to hardware memory */ - BD_CACHE_WRITEBACK_INVALIDATE((rt_uint32_t) curr_bd, - EMAC_BD_LENGTH_FOR_CACHE); - curr_bd->next = rxch->active_queue_head; - rxch->active_queue_head = curr_bd; - } - - /* At this point rxCppi->activeQueueHead points to the first - RX BD ready to be given to RX HDP and rxch->active_queue_tail - points to the last RX BD - */ - return 0; + rt_uint32_t cnt, bd_size; + void __iomem *mem; + struct emac_rx_bd __iomem *curr_bd; + struct emac_rxch *rxch = RT_NULL; + + rxch = rt_malloc(sizeof(struct emac_rxch)); + if (RT_NULL == rxch) { + rt_kprintf("DaVinci EMAC: RX Ch mem alloc failed"); + return -ENOMEM; + } + rt_memset(rxch, 0, sizeof(struct emac_rxch)); + priv->rxch[ch] = rxch; + rxch->buf_size = priv->rx_buf_size; + rxch->service_max = EMAC_DEF_RX_MAX_SERVICE; + rxch->queue_active = 0; + rxch->teardown_pending = 0; + + /* save mac address */ + for (cnt = 0; cnt < 6; cnt++) + rxch->mac_addr[cnt] = param[cnt]; + + /* allocate buffer descriptor pool align every BD on four word + * boundry for future requirements */ + bd_size = (sizeof(struct emac_rx_bd) + 0xF) & ~0xF; + rxch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size; + rxch->alloc_size = (((bd_size * rxch->num_bd) + 0xF) & ~0xF); + rxch->bd_mem = EMAC_RX_BD_MEM(priv); + + rt_memset((void *)rxch->bd_mem, 0, rxch->alloc_size); + rxch->pkt_queue.buf_list = &rxch->buf_queue; + + /* allocate RX buffer and initialize the BD linked list */ + mem = (void __iomem *) + (((rt_uint32_t) rxch->bd_mem + 0xF) & ~0xF); + rxch->active_queue_head = RT_NULL; + rxch->active_queue_tail = mem; + for (cnt = 0; cnt < rxch->num_bd; cnt++) { + curr_bd = mem + (cnt * bd_size); + /* for future use the last parameter contains the BD ptr */ + curr_bd->data_ptr = emac_net_alloc_rx_buf(priv, + rxch->buf_size, + (void **)&curr_bd->buf_token, + EMAC_DEF_RX_CH); + if (curr_bd->data_ptr == RT_NULL) { + rt_kprintf("DaVinci EMAC: RX buf mem alloc " \ + "failed for ch %d\n", ch); + rt_free(rxch); + return -RT_ENOMEM; + } + + /* populate the hardware descriptor */ + curr_bd->h_next = emac_virt_to_phys(rxch->active_queue_head); + curr_bd->buff_ptr = virt_to_phys(curr_bd->data_ptr); + curr_bd->off_b_len = rxch->buf_size; + curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT; + + /* write back to hardware memory */ + BD_CACHE_WRITEBACK_INVALIDATE((rt_uint32_t) curr_bd, + EMAC_BD_LENGTH_FOR_CACHE); + curr_bd->next = rxch->active_queue_head; + rxch->active_queue_head = curr_bd; + } + + /* At this point rxCppi->activeQueueHead points to the first + RX BD ready to be given to RX HDP and rxch->active_queue_tail + points to the last RX BD + */ + return 0; } @@ -1289,23 +1289,23 @@ static int emac_init_rxch(struct emac_priv *priv, rt_uint32_t ch, char *param) */ static void emac_int_disable(struct emac_priv *priv) { - if (priv->version == EMAC_VERSION_2) { - unsigned long flags; + if (priv->version == EMAC_VERSION_2) { + unsigned long flags; - rt_interrupt_enter(); + rt_interrupt_enter(); - /* Program C0_Int_En to zero to turn off - * interrupts to the CPU */ - emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0); - emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0); - /* NOTE: Rx Threshold and Misc interrupts are not disabled */ + /* Program C0_Int_En to zero to turn off + * interrupts to the CPU */ + emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0); + emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0); + /* NOTE: Rx Threshold and Misc interrupts are not disabled */ - rt_interrupt_leave(); + rt_interrupt_leave(); - } else { - /* Set DM644x control registers for interrupt control */ - emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0); - } + } else { + /* Set DM644x control registers for interrupt control */ + emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0); + } } @@ -1318,31 +1318,31 @@ static void emac_int_disable(struct emac_priv *priv) */ static void emac_int_enable(struct emac_priv *priv) { - if (priv->version == EMAC_VERSION_2) { - /*if (priv->int_enable) - priv->int_enable();*/ + if (priv->version == EMAC_VERSION_2) { + /*if (priv->int_enable) + priv->int_enable();*/ - emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff); - emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff); + emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff); + emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff); - /* In addition to turning on interrupt Enable, we need - * ack by writing appropriate values to the EOI - * register */ + /* In addition to turning on interrupt Enable, we need + * ack by writing appropriate values to the EOI + * register */ - /* NOTE: Rx Threshold and Misc interrupts are not enabled */ + /* NOTE: Rx Threshold and Misc interrupts are not enabled */ - /* ack rxen only then a new pulse will be generated */ - emac_write(EMAC_DM646X_MACEOIVECTOR, - EMAC_DM646X_MAC_EOI_C0_RXEN); + /* ack rxen only then a new pulse will be generated */ + emac_write(EMAC_DM646X_MACEOIVECTOR, + EMAC_DM646X_MAC_EOI_C0_RXEN); - /* ack txen- only then a new pulse will be generated */ - emac_write(EMAC_DM646X_MACEOIVECTOR, - EMAC_DM646X_MAC_EOI_C0_TXEN); + /* ack txen- only then a new pulse will be generated */ + emac_write(EMAC_DM646X_MACEOIVECTOR, + EMAC_DM646X_MAC_EOI_C0_TXEN); - } else { - /* Set DM644x control registers for interrupt control */ - emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1); - } + } else { + /* Set DM644x control registers for interrupt control */ + emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1); + } } @@ -1354,11 +1354,11 @@ static void emac_int_enable(struct emac_priv *priv) */ static void emac_irq(int irq, void *param) { - struct emac_priv *priv = param; + struct emac_priv *priv = param; - ++priv->isr_count; - emac_int_disable(priv); - eth_device_ready(&priv->parent); + ++priv->isr_count; + emac_int_disable(priv); + eth_device_ready(&priv->parent); } @@ -1374,77 +1374,77 @@ static void emac_irq(int irq, void *param) */ static int emac_hw_enable(struct emac_priv *priv) { - rt_uint32_t ch, val, mbp_enable, mac_control; - - /* Soft reset */ - emac_write(EMAC_SOFTRESET, 1); - while (emac_read(EMAC_SOFTRESET)); - - /* Disable interrupt & Set pacing for more interrupts initially */ - emac_int_disable(priv); - - /* Full duplex enable bit set when auto negotiation happens */ - mac_control = - (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) | - ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) | - ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) | - ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0)); - emac_write(EMAC_MACCONTROL, mac_control); - - mbp_enable = - (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) | - ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) | - ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) | - ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) | - ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) | - ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) | - ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) | - ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \ - EMAC_RXMBP_PROMCH_SHIFT) | - ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) | - ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \ - EMAC_RXMBP_BROADCH_SHIFT) | - ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) | - ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \ - EMAC_RXMBP_MULTICH_SHIFT)); - emac_write(EMAC_RXMBPENABLE, mbp_enable); - emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE & - EMAC_RX_MAX_LEN_MASK)); - emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET & - EMAC_RX_BUFFER_OFFSET_MASK)); - emac_write(EMAC_RXFILTERLOWTHRESH, 0); - emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL); - priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF; - - val = emac_read(EMAC_TXCONTROL); - val |= EMAC_TX_CONTROL_TX_ENABLE_VAL; - emac_write(EMAC_TXCONTROL, val); - val = emac_read(EMAC_RXCONTROL); - val |= EMAC_RX_CONTROL_RX_ENABLE_VAL; - emac_write(EMAC_RXCONTROL, val); - emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL); - - for (ch = 0; ch < EMAC_DEF_MAX_TX_CH; ch++) { - emac_write(EMAC_TXHDP(ch), 0); - emac_write(EMAC_TXINTMASKSET, BIT(ch)); - } - for (ch = 0; ch < EMAC_DEF_MAX_RX_CH; ch++) { - struct emac_rxch *rxch = priv->rxch[ch]; - emac_setmac(priv, ch, rxch->mac_addr); - emac_write(EMAC_RXINTMASKSET, BIT(ch)); - rxch->queue_active = 1; - emac_write(EMAC_RXHDP(ch), - (unsigned int)(rxch->active_queue_head)); /* physcal addr */ - } - - /* Enable MII */ - val = emac_read(EMAC_MACCONTROL); - val |= (EMAC_MACCONTROL_GMIIEN); - emac_write(EMAC_MACCONTROL, val); - - /* Enable interrupts */ - emac_int_enable(priv); - return 0; + rt_uint32_t ch, val, mbp_enable, mac_control; + + /* Soft reset */ + emac_write(EMAC_SOFTRESET, 1); + while (emac_read(EMAC_SOFTRESET)); + + /* Disable interrupt & Set pacing for more interrupts initially */ + emac_int_disable(priv); + + /* Full duplex enable bit set when auto negotiation happens */ + mac_control = + (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) | + ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) | + ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) | + ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0)); + emac_write(EMAC_MACCONTROL, mac_control); + + mbp_enable = + (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) | + ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) | + ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) | + ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) | + ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) | + ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) | + ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) | + ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \ + EMAC_RXMBP_PROMCH_SHIFT) | + ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) | + ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \ + EMAC_RXMBP_BROADCH_SHIFT) | + ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) | + ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \ + EMAC_RXMBP_MULTICH_SHIFT)); + emac_write(EMAC_RXMBPENABLE, mbp_enable); + emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE & + EMAC_RX_MAX_LEN_MASK)); + emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET & + EMAC_RX_BUFFER_OFFSET_MASK)); + emac_write(EMAC_RXFILTERLOWTHRESH, 0); + emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL); + priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF; + + val = emac_read(EMAC_TXCONTROL); + val |= EMAC_TX_CONTROL_TX_ENABLE_VAL; + emac_write(EMAC_TXCONTROL, val); + val = emac_read(EMAC_RXCONTROL); + val |= EMAC_RX_CONTROL_RX_ENABLE_VAL; + emac_write(EMAC_RXCONTROL, val); + emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL); + + for (ch = 0; ch < EMAC_DEF_MAX_TX_CH; ch++) { + emac_write(EMAC_TXHDP(ch), 0); + emac_write(EMAC_TXINTMASKSET, BIT(ch)); + } + for (ch = 0; ch < EMAC_DEF_MAX_RX_CH; ch++) { + struct emac_rxch *rxch = priv->rxch[ch]; + emac_setmac(priv, ch, rxch->mac_addr); + emac_write(EMAC_RXINTMASKSET, BIT(ch)); + rxch->queue_active = 1; + emac_write(EMAC_RXHDP(ch), + (unsigned int)(rxch->active_queue_head)); /* physcal addr */ + } + + /* Enable MII */ + val = emac_read(EMAC_MACCONTROL); + val |= (EMAC_MACCONTROL_GMIIEN); + emac_write(EMAC_MACCONTROL, val); + + /* Enable interrupts */ + emac_int_enable(priv); + return 0; } @@ -1458,51 +1458,51 @@ static int emac_hw_enable(struct emac_priv *priv) */ static struct net_device_stats *emac_dev_getnetstats(struct emac_priv *priv) { - rt_uint32_t mac_control; - rt_uint32_t stats_clear_mask; + rt_uint32_t mac_control; + rt_uint32_t stats_clear_mask; - /* update emac hardware stats and reset the registers*/ + /* update emac hardware stats and reset the registers*/ - mac_control = emac_read(EMAC_MACCONTROL); + mac_control = emac_read(EMAC_MACCONTROL); - if (mac_control & EMAC_MACCONTROL_GMIIEN) - stats_clear_mask = EMAC_STATS_CLR_MASK; - else - stats_clear_mask = 0; + if (mac_control & EMAC_MACCONTROL_GMIIEN) + stats_clear_mask = EMAC_STATS_CLR_MASK; + else + stats_clear_mask = 0; - priv->net_dev_stats.multicast += emac_read(EMAC_RXMCASTFRAMES); - emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask); + priv->net_dev_stats.multicast += emac_read(EMAC_RXMCASTFRAMES); + emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask); - priv->net_dev_stats.collisions += (emac_read(EMAC_TXCOLLISION) + - emac_read(EMAC_TXSINGLECOLL) + - emac_read(EMAC_TXMULTICOLL)); - emac_write(EMAC_TXCOLLISION, stats_clear_mask); - emac_write(EMAC_TXSINGLECOLL, stats_clear_mask); - emac_write(EMAC_TXMULTICOLL, stats_clear_mask); + priv->net_dev_stats.collisions += (emac_read(EMAC_TXCOLLISION) + + emac_read(EMAC_TXSINGLECOLL) + + emac_read(EMAC_TXMULTICOLL)); + emac_write(EMAC_TXCOLLISION, stats_clear_mask); + emac_write(EMAC_TXSINGLECOLL, stats_clear_mask); + emac_write(EMAC_TXMULTICOLL, stats_clear_mask); - priv->net_dev_stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) + - emac_read(EMAC_RXJABBER) + - emac_read(EMAC_RXUNDERSIZED)); - emac_write(EMAC_RXOVERSIZED, stats_clear_mask); - emac_write(EMAC_RXJABBER, stats_clear_mask); - emac_write(EMAC_RXUNDERSIZED, stats_clear_mask); + priv->net_dev_stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) + + emac_read(EMAC_RXJABBER) + + emac_read(EMAC_RXUNDERSIZED)); + emac_write(EMAC_RXOVERSIZED, stats_clear_mask); + emac_write(EMAC_RXJABBER, stats_clear_mask); + emac_write(EMAC_RXUNDERSIZED, stats_clear_mask); - priv->net_dev_stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) + - emac_read(EMAC_RXMOFOVERRUNS)); - emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask); - emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask); + priv->net_dev_stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) + + emac_read(EMAC_RXMOFOVERRUNS)); + emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask); + emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask); - priv->net_dev_stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS); - emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask); + priv->net_dev_stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS); + emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask); - priv->net_dev_stats.tx_carrier_errors += - emac_read(EMAC_TXCARRIERSENSE); - emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask); + priv->net_dev_stats.tx_carrier_errors += + emac_read(EMAC_TXCARRIERSENSE); + emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask); - priv->net_dev_stats.tx_fifo_errors = emac_read(EMAC_TXUNDERRUN); - emac_write(EMAC_TXUNDERRUN, stats_clear_mask); + priv->net_dev_stats.tx_fifo_errors = emac_read(EMAC_TXUNDERRUN); + emac_write(EMAC_TXUNDERRUN, stats_clear_mask); - return &priv->net_dev_stats; + return &priv->net_dev_stats; } @@ -1511,164 +1511,164 @@ static struct net_device_stats *emac_dev_getnetstats(struct emac_priv *priv) static rt_err_t rt_davinci_emac_init(rt_device_t dev) { - struct emac_priv *priv = dev->user_data; - unsigned long paddr; - rt_uint32_t ch, rc; - int i; - - /* Configuration items */ - priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN; - - /* Clear basic hardware */ - for (ch = 0; ch < EMAC_MAX_TXRX_CHANNELS; ch++) { - emac_write(EMAC_TXHDP(ch), 0); - emac_write(EMAC_RXHDP(ch), 0); - emac_write(EMAC_RXHDP(ch), 0); - emac_write(EMAC_RXINTMASKCLEAR, EMAC_INT_MASK_CLEAR); - emac_write(EMAC_TXINTMASKCLEAR, EMAC_INT_MASK_CLEAR); - } - priv->mac_hash1 = 0; - priv->mac_hash2 = 0; - emac_write(EMAC_MACHASH1, 0); - emac_write(EMAC_MACHASH2, 0); - - /* multi ch not supported - open 1 TX, 1RX ch by default */ - rc = emac_init_txch(priv, EMAC_DEF_TX_CH); - if (0 != rc) { - rt_kprintf("DaVinci EMAC: emac_init_txch() failed"); - return rc; - } - rc = emac_init_rxch(priv, EMAC_DEF_RX_CH, priv->mac_addr); - if (0 != rc) { - rt_kprintf("DaVinci EMAC: emac_init_rxch() failed"); - return rc; - } - - rt_hw_interrupt_install(IRQ_DM365_EMAC_RXPULSE, emac_irq, - (void *)priv, "EMAC_RXPULSE"); - rt_hw_interrupt_umask(IRQ_DM365_EMAC_RXPULSE); - rt_hw_interrupt_install(IRQ_DM365_EMAC_TXPULSE, emac_irq, - (void *)priv, "EMAC_TXPULSE"); - rt_hw_interrupt_umask(IRQ_DM365_EMAC_TXPULSE); - rt_hw_interrupt_install(IRQ_DM365_EMAC_RXTHRESH, emac_irq, - (void *)priv, "EMAC_RXTHRESH"); - rt_hw_interrupt_umask(IRQ_DM365_EMAC_RXTHRESH); - rt_hw_interrupt_install(IRQ_DM365_EMAC_MISCPULSE, emac_irq, - (void *)priv, "EMAC_MISCPULSE"); - rt_hw_interrupt_umask(IRQ_DM365_EMAC_MISCPULSE); - - emac_mii_reset(priv); - davinci_emac_phy_init(dev); - - /* Start/Enable EMAC hardware */ - emac_hw_enable(priv); - - rt_timer_init(&priv->timer, "link_timer", - davinci_emac_update_link, - (void *)priv, - RT_TICK_PER_SECOND, - RT_TIMER_FLAG_PERIODIC); - - rt_timer_start(&priv->timer); - rt_kprintf("davinci emac initialized\n"); - - return RT_EOK; + struct emac_priv *priv = dev->user_data; + unsigned long paddr; + rt_uint32_t ch, rc; + int i; + + /* Configuration items */ + priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN; + + /* Clear basic hardware */ + for (ch = 0; ch < EMAC_MAX_TXRX_CHANNELS; ch++) { + emac_write(EMAC_TXHDP(ch), 0); + emac_write(EMAC_RXHDP(ch), 0); + emac_write(EMAC_RXHDP(ch), 0); + emac_write(EMAC_RXINTMASKCLEAR, EMAC_INT_MASK_CLEAR); + emac_write(EMAC_TXINTMASKCLEAR, EMAC_INT_MASK_CLEAR); + } + priv->mac_hash1 = 0; + priv->mac_hash2 = 0; + emac_write(EMAC_MACHASH1, 0); + emac_write(EMAC_MACHASH2, 0); + + /* multi ch not supported - open 1 TX, 1RX ch by default */ + rc = emac_init_txch(priv, EMAC_DEF_TX_CH); + if (0 != rc) { + rt_kprintf("DaVinci EMAC: emac_init_txch() failed"); + return rc; + } + rc = emac_init_rxch(priv, EMAC_DEF_RX_CH, priv->mac_addr); + if (0 != rc) { + rt_kprintf("DaVinci EMAC: emac_init_rxch() failed"); + return rc; + } + + rt_hw_interrupt_install(IRQ_DM365_EMAC_RXPULSE, emac_irq, + (void *)priv, "EMAC_RXPULSE"); + rt_hw_interrupt_umask(IRQ_DM365_EMAC_RXPULSE); + rt_hw_interrupt_install(IRQ_DM365_EMAC_TXPULSE, emac_irq, + (void *)priv, "EMAC_TXPULSE"); + rt_hw_interrupt_umask(IRQ_DM365_EMAC_TXPULSE); + rt_hw_interrupt_install(IRQ_DM365_EMAC_RXTHRESH, emac_irq, + (void *)priv, "EMAC_RXTHRESH"); + rt_hw_interrupt_umask(IRQ_DM365_EMAC_RXTHRESH); + rt_hw_interrupt_install(IRQ_DM365_EMAC_MISCPULSE, emac_irq, + (void *)priv, "EMAC_MISCPULSE"); + rt_hw_interrupt_umask(IRQ_DM365_EMAC_MISCPULSE); + + emac_mii_reset(priv); + davinci_emac_phy_init(dev); + + /* Start/Enable EMAC hardware */ + emac_hw_enable(priv); + + rt_timer_init(&priv->timer, "link_timer", + davinci_emac_update_link, + (void *)priv, + RT_TICK_PER_SECOND, + RT_TIMER_FLAG_PERIODIC); + + rt_timer_start(&priv->timer); + rt_kprintf("davinci emac initialized\n"); + + return RT_EOK; } static rt_err_t rt_davinci_emac_open(rt_device_t dev, rt_uint16_t oflag) { - return RT_EOK; + return RT_EOK; } static rt_err_t rt_davinci_emac_close(rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_size_t rt_davinci_emac_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_size_t rt_davinci_emac_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_err_t rt_davinci_emac_control(rt_device_t dev, int cmd, void *args) { - struct emac_priv *priv = dev->user_data; - switch(cmd) - { - case NIOCTL_GADDR: - /* get mac address */ - if(args) rt_memcpy(args, priv->mac_addr, 6); - else return -RT_ERROR; - break; - - default : - break; - } - - return RT_EOK; + struct emac_priv *priv = dev->user_data; + switch(cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if(args) rt_memcpy(args, priv->mac_addr, 6); + else return -RT_ERROR; + break; + + default : + break; + } + + return RT_EOK; } void dm365_emac_gpio_init(void) { - rt_uint32_t arm_intmux; - - /* - * EMAC interrupts are multiplexed with GPIO interrupts - * Details are available at the DM365 ARM - * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134 - */ - arm_intmux = davinci_readl(DM365_ARM_INTMUX); - arm_intmux |= (1 << 14)|(1 << 15)|(1 << 16)|(1 << 17); - davinci_writel(arm_intmux, DM365_ARM_INTMUX); + rt_uint32_t arm_intmux; + + /* + * EMAC interrupts are multiplexed with GPIO interrupts + * Details are available at the DM365 ARM + * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134 + */ + arm_intmux = davinci_readl(DM365_ARM_INTMUX); + arm_intmux |= (1 << 14)|(1 << 15)|(1 << 16)|(1 << 17); + davinci_writel(arm_intmux, DM365_ARM_INTMUX); } int rt_hw_davinci_emac_init() { - struct emac_priv *priv = &davinci_emac_device; - struct clk *emac_clk; - emac_clk = clk_get("EMACCLK"); - emac_bus_frequency = clk_get_rate(emac_clk); - psc_change_state(DAVINCI_DM365_LPSC_CPGMAC, PSC_ENABLE); - dm365_emac_gpio_init(); - rt_memset(&davinci_emac_device, 0, sizeof(davinci_emac_device)); - davinci_emac_device.emac_base = (void __iomem *)DM365_EMAC_CNTRL_BASE; - davinci_emac_device.ctrl_base = (void __iomem *)DM365_EMAC_WRAP_CNTRL_BASE; - davinci_emac_device.ctrl_ram_size = DM365_EMAC_CNTRL_RAM_SIZE; - davinci_emac_device.emac_ctrl_ram = (void __iomem *)DM365_EMAC_WRAP_RAM_BASE; - davinci_emac_device.mdio_base = (void __iomem *)DM365_EMAC_MDIO_BASE; - davinci_emac_device.version = EMAC_VERSION_2; - davinci_emac_device.rmii_en = 0; - davinci_emac_device.phy_addr = 0x09; - rt_sem_init(&priv->tx_lock, "tx_lock", 1, RT_IPC_FLAG_FIFO); - rt_sem_init(&priv->rx_lock, "rx_lock", 1, RT_IPC_FLAG_FIFO); - - davinci_emac_device.mac_addr[0] = 0x00; - davinci_emac_device.mac_addr[1] = 0x60; - davinci_emac_device.mac_addr[2] = 0x6E; - davinci_emac_device.mac_addr[3] = 0x11; - davinci_emac_device.mac_addr[4] = 0x22; - davinci_emac_device.mac_addr[5] = 0x33; - - davinci_emac_device.parent.parent.init = rt_davinci_emac_init; - davinci_emac_device.parent.parent.open = rt_davinci_emac_open; - davinci_emac_device.parent.parent.close = rt_davinci_emac_close; - davinci_emac_device.parent.parent.read = rt_davinci_emac_read; - davinci_emac_device.parent.parent.write = rt_davinci_emac_write; - davinci_emac_device.parent.parent.control = rt_davinci_emac_control; - davinci_emac_device.parent.parent.user_data = &davinci_emac_device; - - davinci_emac_device.parent.eth_rx = rt_davinci_emac_rx; - davinci_emac_device.parent.eth_tx = rt_davinci_emac_tx; - - eth_device_init(&(davinci_emac_device.parent), "e0"); - + struct emac_priv *priv = &davinci_emac_device; + struct clk *emac_clk; + emac_clk = clk_get("EMACCLK"); + emac_bus_frequency = clk_get_rate(emac_clk); + psc_change_state(DAVINCI_DM365_LPSC_CPGMAC, PSC_ENABLE); + dm365_emac_gpio_init(); + rt_memset(&davinci_emac_device, 0, sizeof(davinci_emac_device)); + davinci_emac_device.emac_base = (void __iomem *)DM365_EMAC_CNTRL_BASE; + davinci_emac_device.ctrl_base = (void __iomem *)DM365_EMAC_WRAP_CNTRL_BASE; + davinci_emac_device.ctrl_ram_size = DM365_EMAC_CNTRL_RAM_SIZE; + davinci_emac_device.emac_ctrl_ram = (void __iomem *)DM365_EMAC_WRAP_RAM_BASE; + davinci_emac_device.mdio_base = (void __iomem *)DM365_EMAC_MDIO_BASE; + davinci_emac_device.version = EMAC_VERSION_2; + davinci_emac_device.rmii_en = 0; + davinci_emac_device.phy_addr = 0x09; + rt_sem_init(&priv->tx_lock, "tx_lock", 1, RT_IPC_FLAG_FIFO); + rt_sem_init(&priv->rx_lock, "rx_lock", 1, RT_IPC_FLAG_FIFO); + + davinci_emac_device.mac_addr[0] = 0x00; + davinci_emac_device.mac_addr[1] = 0x60; + davinci_emac_device.mac_addr[2] = 0x6E; + davinci_emac_device.mac_addr[3] = 0x11; + davinci_emac_device.mac_addr[4] = 0x22; + davinci_emac_device.mac_addr[5] = 0x33; + + davinci_emac_device.parent.parent.init = rt_davinci_emac_init; + davinci_emac_device.parent.parent.open = rt_davinci_emac_open; + davinci_emac_device.parent.parent.close = rt_davinci_emac_close; + davinci_emac_device.parent.parent.read = rt_davinci_emac_read; + davinci_emac_device.parent.parent.write = rt_davinci_emac_write; + davinci_emac_device.parent.parent.control = rt_davinci_emac_control; + davinci_emac_device.parent.parent.user_data = &davinci_emac_device; + + davinci_emac_device.parent.eth_rx = rt_davinci_emac_rx; + davinci_emac_device.parent.eth_tx = rt_davinci_emac_tx; + + eth_device_init(&(davinci_emac_device.parent), "e0"); + } INIT_DEVICE_EXPORT(rt_hw_davinci_emac_init); @@ -1679,68 +1679,68 @@ INIT_DEVICE_EXPORT(rt_hw_davinci_emac_init); void dump_emac_stats(void) { - int i; - struct emac_priv *emac; - struct net_device_stats *stats; - rt_device_t dev = rt_device_find("e0"); - - if(dev == RT_NULL) - return; - - emac = (struct emac_priv *)dev->user_data; - - stats = emac_dev_getnetstats(emac); - rt_kprintf("rx_packets = %d\n" - "tx_packets = %d\n" - "rx_bytes = %d\n" - "tx_bytes = %d\n" - "rx_errors = %d\n" - "tx_errors = %d\n" - "rx_dropped = %d\n" - "tx_dropped = %d\n" - "multicast = %d\n" - "collisions = %d\n", - stats->rx_packets, - stats->tx_packets, - stats->rx_bytes, - stats->tx_bytes, - stats->rx_errors, - stats->tx_errors, - stats->rx_dropped, - stats->tx_dropped, - stats->multicast, - stats->collisions); - - rt_kprintf("rx_length_errors = %d\n" - "rx_over_errors = %d\n" - "rx_crc_errors = %d\n" - "rx_frame_errors = %d\n" - "rx_fifo_errors = %d\n" - "rx_missed_errors = %d\n", - stats->rx_length_errors, - stats->rx_over_errors, - stats->rx_crc_errors, - stats->rx_frame_errors, - stats->rx_fifo_errors, - stats->rx_missed_errors); - - rt_kprintf("tx_aborted_errors = %d\n" - "tx_carrier_errors = %d\n" - "tx_fifo_errors = %d\n" - "tx_heartbeat_errors = %d\n" - "tx_window_errors = %d\n", - stats->tx_aborted_errors, - stats->tx_carrier_errors, - stats->tx_fifo_errors, - stats->tx_heartbeat_errors, - stats->tx_window_errors); - - rt_kprintf("rx_compressed = %d\n" - "tx_compressed = %d\n", - stats->rx_compressed, - stats->tx_compressed); - - rt_kprintf("\n"); + int i; + struct emac_priv *emac; + struct net_device_stats *stats; + rt_device_t dev = rt_device_find("e0"); + + if(dev == RT_NULL) + return; + + emac = (struct emac_priv *)dev->user_data; + + stats = emac_dev_getnetstats(emac); + rt_kprintf("rx_packets = %d\n" + "tx_packets = %d\n" + "rx_bytes = %d\n" + "tx_bytes = %d\n" + "rx_errors = %d\n" + "tx_errors = %d\n" + "rx_dropped = %d\n" + "tx_dropped = %d\n" + "multicast = %d\n" + "collisions = %d\n", + stats->rx_packets, + stats->tx_packets, + stats->rx_bytes, + stats->tx_bytes, + stats->rx_errors, + stats->tx_errors, + stats->rx_dropped, + stats->tx_dropped, + stats->multicast, + stats->collisions); + + rt_kprintf("rx_length_errors = %d\n" + "rx_over_errors = %d\n" + "rx_crc_errors = %d\n" + "rx_frame_errors = %d\n" + "rx_fifo_errors = %d\n" + "rx_missed_errors = %d\n", + stats->rx_length_errors, + stats->rx_over_errors, + stats->rx_crc_errors, + stats->rx_frame_errors, + stats->rx_fifo_errors, + stats->rx_missed_errors); + + rt_kprintf("tx_aborted_errors = %d\n" + "tx_carrier_errors = %d\n" + "tx_fifo_errors = %d\n" + "tx_heartbeat_errors = %d\n" + "tx_window_errors = %d\n", + stats->tx_aborted_errors, + stats->tx_carrier_errors, + stats->tx_fifo_errors, + stats->tx_heartbeat_errors, + stats->tx_window_errors); + + rt_kprintf("rx_compressed = %d\n" + "tx_compressed = %d\n", + stats->rx_compressed, + stats->tx_compressed); + + rt_kprintf("\n"); } FINSH_FUNCTION_EXPORT(dump_emac_stats, dump emac statistics); @@ -1748,8 +1748,8 @@ FINSH_FUNCTION_EXPORT(dump_emac_stats, dump emac statistics); #ifdef FINSH_USING_MSH int cmd_dump_emac_stats(int argc, char** argv) { - dump_emac_stats(); - return 0; + dump_emac_stats(); + return 0; } FINSH_FUNCTION_EXPORT_ALIAS(cmd_dump_emac_stats, __cmd_dump_emac_stats, dump emac statistics.); #endif diff --git a/bsp/dm365/drivers/davinci_emac.h b/bsp/dm365/drivers/davinci_emac.h index 2b07834583..1d80c754c9 100644 --- a/bsp/dm365/drivers/davinci_emac.h +++ b/bsp/dm365/drivers/davinci_emac.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2013-01-30 weety first version + * Date Author Notes + * 2013-01-30 weety first version */ #ifndef _DAVINCI_EMAC_H @@ -17,249 +17,249 @@ #endif enum { - EMAC_VERSION_1, /* DM644x */ - EMAC_VERSION_2, /* DM646x */ + EMAC_VERSION_1, /* DM644x */ + EMAC_VERSION_2, /* DM646x */ }; #define __iomem -#define BIT(nr) (1UL << (nr)) +#define BIT(nr) (1UL << (nr)) /* Configuration items */ -#define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC upto frames */ -#define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */ -#define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */ -#define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */ -#define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */ -#define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */ -#define EMAC_DEF_PROM_EN (0) /* Promiscous disabled */ -#define EMAC_DEF_PROM_CH (0) /* Promiscous channel is 0 */ -#define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */ -#define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */ -#define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */ -#define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */ - -#define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */ -#define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/ - -#define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */ -#define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */ -#define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4) -#define EMAC_DEF_TX_CH (0) /* Default 0th channel */ -#define EMAC_DEF_RX_CH (0) /* Default 0th channel */ -#define EMAC_DEF_MDIO_TICK_MS (10) /* typically 1 tick=1 ms) */ -#define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */ -#define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */ -#define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */ +#define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC upto frames */ +#define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */ +#define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */ +#define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */ +#define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */ +#define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */ +#define EMAC_DEF_PROM_EN (0) /* Promiscous disabled */ +#define EMAC_DEF_PROM_CH (0) /* Promiscous channel is 0 */ +#define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */ +#define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */ +#define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */ +#define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */ + +#define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */ +#define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/ + +#define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */ +#define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */ +#define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4) +#define EMAC_DEF_TX_CH (0) /* Default 0th channel */ +#define EMAC_DEF_RX_CH (0) /* Default 0th channel */ +#define EMAC_DEF_MDIO_TICK_MS (10) /* typically 1 tick=1 ms) */ +#define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */ +#define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */ +#define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */ /* Buffer descriptor parameters */ -#define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */ -#define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */ +#define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */ +#define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */ /* EMAC register related defines */ -#define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF) -#define EMAC_NUM_MULTICAST_BITS (64) -#define EMAC_TEARDOWN_VALUE (0xFFFFFFFC) -#define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1) -#define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1) -#define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2) -#define EMAC_RX_UNICAST_CLEAR_ALL (0xFF) -#define EMAC_INT_MASK_CLEAR (0xFF) +#define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF) +#define EMAC_NUM_MULTICAST_BITS (64) +#define EMAC_TEARDOWN_VALUE (0xFFFFFFFC) +#define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1) +#define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1) +#define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2) +#define EMAC_RX_UNICAST_CLEAR_ALL (0xFF) +#define EMAC_INT_MASK_CLEAR (0xFF) /* RX MBP register bit positions */ -#define EMAC_RXMBP_PASSCRC_MASK BIT(30) -#define EMAC_RXMBP_QOSEN_MASK BIT(29) -#define EMAC_RXMBP_NOCHAIN_MASK BIT(28) -#define EMAC_RXMBP_CMFEN_MASK BIT(24) -#define EMAC_RXMBP_CSFEN_MASK BIT(23) -#define EMAC_RXMBP_CEFEN_MASK BIT(22) -#define EMAC_RXMBP_CAFEN_MASK BIT(21) -#define EMAC_RXMBP_PROMCH_SHIFT (16) -#define EMAC_RXMBP_PROMCH_MASK (0x7 << 16) -#define EMAC_RXMBP_BROADEN_MASK BIT(13) -#define EMAC_RXMBP_BROADCH_SHIFT (8) -#define EMAC_RXMBP_BROADCH_MASK (0x7 << 8) -#define EMAC_RXMBP_MULTIEN_MASK BIT(5) -#define EMAC_RXMBP_MULTICH_SHIFT (0) -#define EMAC_RXMBP_MULTICH_MASK (0x7) -#define EMAC_RXMBP_CHMASK (0x7) +#define EMAC_RXMBP_PASSCRC_MASK BIT(30) +#define EMAC_RXMBP_QOSEN_MASK BIT(29) +#define EMAC_RXMBP_NOCHAIN_MASK BIT(28) +#define EMAC_RXMBP_CMFEN_MASK BIT(24) +#define EMAC_RXMBP_CSFEN_MASK BIT(23) +#define EMAC_RXMBP_CEFEN_MASK BIT(22) +#define EMAC_RXMBP_CAFEN_MASK BIT(21) +#define EMAC_RXMBP_PROMCH_SHIFT (16) +#define EMAC_RXMBP_PROMCH_MASK (0x7 << 16) +#define EMAC_RXMBP_BROADEN_MASK BIT(13) +#define EMAC_RXMBP_BROADCH_SHIFT (8) +#define EMAC_RXMBP_BROADCH_MASK (0x7 << 8) +#define EMAC_RXMBP_MULTIEN_MASK BIT(5) +#define EMAC_RXMBP_MULTICH_SHIFT (0) +#define EMAC_RXMBP_MULTICH_MASK (0x7) +#define EMAC_RXMBP_CHMASK (0x7) /* EMAC register definitions/bit maps used */ -# define EMAC_MBP_RXPROMISC (0x00200000) -# define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16) -# define EMAC_MBP_RXBCAST (0x00002000) -# define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8) -# define EMAC_MBP_RXMCAST (0x00000020) -# define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7) +# define EMAC_MBP_RXPROMISC (0x00200000) +# define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16) +# define EMAC_MBP_RXBCAST (0x00002000) +# define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8) +# define EMAC_MBP_RXMCAST (0x00000020) +# define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7) /* EMAC mac_control register */ -#define EMAC_MACCONTROL_TXPTYPE BIT(9) -#define EMAC_MACCONTROL_TXPACEEN BIT(6) -#define EMAC_MACCONTROL_GMIIEN BIT(5) -#define EMAC_MACCONTROL_GIGABITEN BIT(7) -#define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0) -#define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15) +#define EMAC_MACCONTROL_TXPTYPE BIT(9) +#define EMAC_MACCONTROL_TXPACEEN BIT(6) +#define EMAC_MACCONTROL_GMIIEN BIT(5) +#define EMAC_MACCONTROL_GIGABITEN BIT(7) +#define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0) +#define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15) /* GIGABIT MODE related bits */ -#define EMAC_DM646X_MACCONTORL_GIG BIT(7) -#define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17) +#define EMAC_DM646X_MACCONTORL_GIG BIT(7) +#define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17) /* EMAC mac_status register */ -#define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000) -#define EMAC_MACSTATUS_TXERRCODE_SHIFT (20) -#define EMAC_MACSTATUS_TXERRCH_MASK (0x7) -#define EMAC_MACSTATUS_TXERRCH_SHIFT (16) -#define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000) -#define EMAC_MACSTATUS_RXERRCODE_SHIFT (12) -#define EMAC_MACSTATUS_RXERRCH_MASK (0x7) -#define EMAC_MACSTATUS_RXERRCH_SHIFT (8) +#define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000) +#define EMAC_MACSTATUS_TXERRCODE_SHIFT (20) +#define EMAC_MACSTATUS_TXERRCH_MASK (0x7) +#define EMAC_MACSTATUS_TXERRCH_SHIFT (16) +#define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000) +#define EMAC_MACSTATUS_RXERRCODE_SHIFT (12) +#define EMAC_MACSTATUS_RXERRCH_MASK (0x7) +#define EMAC_MACSTATUS_RXERRCH_SHIFT (8) /* EMAC RX register masks */ -#define EMAC_RX_MAX_LEN_MASK (0xFFFF) -#define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF) +#define EMAC_RX_MAX_LEN_MASK (0xFFFF) +#define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF) /* MAC_IN_VECTOR (0x180) register bit fields */ -#define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17) -#define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16) -#define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8) -#define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0) +#define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17) +#define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16) +#define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8) +#define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0) /** NOTE:: For DM646x the IN_VECTOR has changed */ -#define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH) -#define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH) -#define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26) -#define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27) +#define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH) +#define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH) +#define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26) +#define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27) /* CPPI bit positions */ -#define EMAC_CPPI_SOP_BIT BIT(31) -#define EMAC_CPPI_EOP_BIT BIT(30) -#define EMAC_CPPI_OWNERSHIP_BIT BIT(29) -#define EMAC_CPPI_EOQ_BIT BIT(28) +#define EMAC_CPPI_SOP_BIT BIT(31) +#define EMAC_CPPI_EOP_BIT BIT(30) +#define EMAC_CPPI_OWNERSHIP_BIT BIT(29) +#define EMAC_CPPI_EOQ_BIT BIT(28) #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27) -#define EMAC_CPPI_PASS_CRC_BIT BIT(26) -#define EMAC_RX_BD_BUF_SIZE (0xFFFF) -#define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */ -#define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF) +#define EMAC_CPPI_PASS_CRC_BIT BIT(26) +#define EMAC_RX_BD_BUF_SIZE (0xFFFF) +#define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */ +#define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF) /* Max hardware defines */ -#define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */ +#define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */ #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */ /* EMAC Peripheral Device Register Memory Layout structure */ -#define EMAC_TXIDVER 0x0 -#define EMAC_TXCONTROL 0x4 -#define EMAC_TXTEARDOWN 0x8 -#define EMAC_RXIDVER 0x10 -#define EMAC_RXCONTROL 0x14 -#define EMAC_RXTEARDOWN 0x18 -#define EMAC_TXINTSTATRAW 0x80 -#define EMAC_TXINTSTATMASKED 0x84 -#define EMAC_TXINTMASKSET 0x88 -#define EMAC_TXINTMASKCLEAR 0x8C -#define EMAC_MACINVECTOR 0x90 - -#define EMAC_DM646X_MACEOIVECTOR 0x94 - -#define EMAC_RXINTSTATRAW 0xA0 -#define EMAC_RXINTSTATMASKED 0xA4 -#define EMAC_RXINTMASKSET 0xA8 -#define EMAC_RXINTMASKCLEAR 0xAC -#define EMAC_MACINTSTATRAW 0xB0 -#define EMAC_MACINTSTATMASKED 0xB4 -#define EMAC_MACINTMASKSET 0xB8 -#define EMAC_MACINTMASKCLEAR 0xBC - -#define EMAC_RXMBPENABLE 0x100 -#define EMAC_RXUNICASTSET 0x104 -#define EMAC_RXUNICASTCLEAR 0x108 -#define EMAC_RXMAXLEN 0x10C -#define EMAC_RXBUFFEROFFSET 0x110 -#define EMAC_RXFILTERLOWTHRESH 0x114 - -#define EMAC_MACCONTROL 0x160 -#define EMAC_MACSTATUS 0x164 -#define EMAC_EMCONTROL 0x168 -#define EMAC_FIFOCONTROL 0x16C -#define EMAC_MACCONFIG 0x170 -#define EMAC_SOFTRESET 0x174 -#define EMAC_MACSRCADDRLO 0x1D0 -#define EMAC_MACSRCADDRHI 0x1D4 -#define EMAC_MACHASH1 0x1D8 -#define EMAC_MACHASH2 0x1DC -#define EMAC_MACADDRLO 0x500 -#define EMAC_MACADDRHI 0x504 -#define EMAC_MACINDEX 0x508 +#define EMAC_TXIDVER 0x0 +#define EMAC_TXCONTROL 0x4 +#define EMAC_TXTEARDOWN 0x8 +#define EMAC_RXIDVER 0x10 +#define EMAC_RXCONTROL 0x14 +#define EMAC_RXTEARDOWN 0x18 +#define EMAC_TXINTSTATRAW 0x80 +#define EMAC_TXINTSTATMASKED 0x84 +#define EMAC_TXINTMASKSET 0x88 +#define EMAC_TXINTMASKCLEAR 0x8C +#define EMAC_MACINVECTOR 0x90 + +#define EMAC_DM646X_MACEOIVECTOR 0x94 + +#define EMAC_RXINTSTATRAW 0xA0 +#define EMAC_RXINTSTATMASKED 0xA4 +#define EMAC_RXINTMASKSET 0xA8 +#define EMAC_RXINTMASKCLEAR 0xAC +#define EMAC_MACINTSTATRAW 0xB0 +#define EMAC_MACINTSTATMASKED 0xB4 +#define EMAC_MACINTMASKSET 0xB8 +#define EMAC_MACINTMASKCLEAR 0xBC + +#define EMAC_RXMBPENABLE 0x100 +#define EMAC_RXUNICASTSET 0x104 +#define EMAC_RXUNICASTCLEAR 0x108 +#define EMAC_RXMAXLEN 0x10C +#define EMAC_RXBUFFEROFFSET 0x110 +#define EMAC_RXFILTERLOWTHRESH 0x114 + +#define EMAC_MACCONTROL 0x160 +#define EMAC_MACSTATUS 0x164 +#define EMAC_EMCONTROL 0x168 +#define EMAC_FIFOCONTROL 0x16C +#define EMAC_MACCONFIG 0x170 +#define EMAC_SOFTRESET 0x174 +#define EMAC_MACSRCADDRLO 0x1D0 +#define EMAC_MACSRCADDRHI 0x1D4 +#define EMAC_MACHASH1 0x1D8 +#define EMAC_MACHASH2 0x1DC +#define EMAC_MACADDRLO 0x500 +#define EMAC_MACADDRHI 0x504 +#define EMAC_MACINDEX 0x508 /* EMAC HDP and Completion registors */ -#define EMAC_TXHDP(ch) (0x600 + (ch * 4)) -#define EMAC_RXHDP(ch) (0x620 + (ch * 4)) -#define EMAC_TXCP(ch) (0x640 + (ch * 4)) -#define EMAC_RXCP(ch) (0x660 + (ch * 4)) +#define EMAC_TXHDP(ch) (0x600 + (ch * 4)) +#define EMAC_RXHDP(ch) (0x620 + (ch * 4)) +#define EMAC_TXCP(ch) (0x640 + (ch * 4)) +#define EMAC_RXCP(ch) (0x660 + (ch * 4)) /* EMAC statistics registers */ -#define EMAC_RXGOODFRAMES 0x200 -#define EMAC_RXBCASTFRAMES 0x204 -#define EMAC_RXMCASTFRAMES 0x208 -#define EMAC_RXPAUSEFRAMES 0x20C -#define EMAC_RXCRCERRORS 0x210 -#define EMAC_RXALIGNCODEERRORS 0x214 -#define EMAC_RXOVERSIZED 0x218 -#define EMAC_RXJABBER 0x21C -#define EMAC_RXUNDERSIZED 0x220 -#define EMAC_RXFRAGMENTS 0x224 -#define EMAC_RXFILTERED 0x228 -#define EMAC_RXQOSFILTERED 0x22C -#define EMAC_RXOCTETS 0x230 -#define EMAC_TXGOODFRAMES 0x234 -#define EMAC_TXBCASTFRAMES 0x238 -#define EMAC_TXMCASTFRAMES 0x23C -#define EMAC_TXPAUSEFRAMES 0x240 -#define EMAC_TXDEFERRED 0x244 -#define EMAC_TXCOLLISION 0x248 -#define EMAC_TXSINGLECOLL 0x24C -#define EMAC_TXMULTICOLL 0x250 -#define EMAC_TXEXCESSIVECOLL 0x254 -#define EMAC_TXLATECOLL 0x258 -#define EMAC_TXUNDERRUN 0x25C -#define EMAC_TXCARRIERSENSE 0x260 -#define EMAC_TXOCTETS 0x264 -#define EMAC_NETOCTETS 0x280 -#define EMAC_RXSOFOVERRUNS 0x284 -#define EMAC_RXMOFOVERRUNS 0x288 -#define EMAC_RXDMAOVERRUNS 0x28C +#define EMAC_RXGOODFRAMES 0x200 +#define EMAC_RXBCASTFRAMES 0x204 +#define EMAC_RXMCASTFRAMES 0x208 +#define EMAC_RXPAUSEFRAMES 0x20C +#define EMAC_RXCRCERRORS 0x210 +#define EMAC_RXALIGNCODEERRORS 0x214 +#define EMAC_RXOVERSIZED 0x218 +#define EMAC_RXJABBER 0x21C +#define EMAC_RXUNDERSIZED 0x220 +#define EMAC_RXFRAGMENTS 0x224 +#define EMAC_RXFILTERED 0x228 +#define EMAC_RXQOSFILTERED 0x22C +#define EMAC_RXOCTETS 0x230 +#define EMAC_TXGOODFRAMES 0x234 +#define EMAC_TXBCASTFRAMES 0x238 +#define EMAC_TXMCASTFRAMES 0x23C +#define EMAC_TXPAUSEFRAMES 0x240 +#define EMAC_TXDEFERRED 0x244 +#define EMAC_TXCOLLISION 0x248 +#define EMAC_TXSINGLECOLL 0x24C +#define EMAC_TXMULTICOLL 0x250 +#define EMAC_TXEXCESSIVECOLL 0x254 +#define EMAC_TXLATECOLL 0x258 +#define EMAC_TXUNDERRUN 0x25C +#define EMAC_TXCARRIERSENSE 0x260 +#define EMAC_TXOCTETS 0x264 +#define EMAC_NETOCTETS 0x280 +#define EMAC_RXSOFOVERRUNS 0x284 +#define EMAC_RXMOFOVERRUNS 0x288 +#define EMAC_RXDMAOVERRUNS 0x28C /* EMAC DM644x control registers */ -#define EMAC_CTRL_EWCTL (0x4) -#define EMAC_CTRL_EWINTTCNT (0x8) +#define EMAC_CTRL_EWCTL (0x4) +#define EMAC_CTRL_EWINTTCNT (0x8) /* EMAC MDIO related */ /* Mask & Control defines */ -#define MDIO_CONTROL_CLKDIV (0xFF) -#define MDIO_CONTROL_ENABLE BIT(30) -#define MDIO_USERACCESS_GO BIT(31) -#define MDIO_USERACCESS_WRITE BIT(30) -#define MDIO_USERACCESS_READ (0) -#define MDIO_USERACCESS_REGADR (0x1F << 21) -#define MDIO_USERACCESS_PHYADR (0x1F << 16) -#define MDIO_USERACCESS_DATA (0xFFFF) -#define MDIO_USERPHYSEL_LINKSEL BIT(7) -#define MDIO_VER_MODID (0xFFFF << 16) -#define MDIO_VER_REVMAJ (0xFF << 8) -#define MDIO_VER_REVMIN (0xFF) - -#define MDIO_USERACCESS(inst) (0x80 + (inst * 8)) -#define MDIO_USERPHYSEL(inst) (0x84 + (inst * 8)) -#define MDIO_CONTROL (0x04) +#define MDIO_CONTROL_CLKDIV (0xFF) +#define MDIO_CONTROL_ENABLE BIT(30) +#define MDIO_USERACCESS_GO BIT(31) +#define MDIO_USERACCESS_WRITE BIT(30) +#define MDIO_USERACCESS_READ (0) +#define MDIO_USERACCESS_REGADR (0x1F << 21) +#define MDIO_USERACCESS_PHYADR (0x1F << 16) +#define MDIO_USERACCESS_DATA (0xFFFF) +#define MDIO_USERPHYSEL_LINKSEL BIT(7) +#define MDIO_VER_MODID (0xFFFF << 16) +#define MDIO_VER_REVMAJ (0xFF << 8) +#define MDIO_VER_REVMIN (0xFF) + +#define MDIO_USERACCESS(inst) (0x80 + (inst * 8)) +#define MDIO_USERPHYSEL(inst) (0x84 + (inst * 8)) +#define MDIO_CONTROL (0x04) /* EMAC DM646X control module registers */ -#define EMAC_DM646X_CMRXINTEN (0x14) -#define EMAC_DM646X_CMTXINTEN (0x18) +#define EMAC_DM646X_CMRXINTEN (0x14) +#define EMAC_DM646X_CMTXINTEN (0x18) /* EMAC EOI codes for C0 */ -#define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01) -#define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02) +#define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01) +#define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02) /* EMAC Stats Clear Mask */ #define EMAC_STATS_CLR_MASK (0xFFFFFFFF) @@ -269,9 +269,9 @@ enum { * EMAC network buffer data structure */ struct emac_netbufobj { - void *buf_token; - char *data_ptr; - int length; + void *buf_token; + char *data_ptr; + int length; }; /** net_pkt_obj: EMAC network packet data structure @@ -279,10 +279,10 @@ struct emac_netbufobj { * EMAC network packet data structure - supports buffer list (for future) */ struct emac_netpktobj { - void *pkt_token; /* data token may hold tx/rx chan id */ - struct emac_netbufobj *buf_list; /* array of network buffer objects */ - int num_bufs; - int pkt_length; + void *pkt_token; /* data token may hold tx/rx chan id */ + struct emac_netbufobj *buf_list; /* array of network buffer objects */ + int num_bufs; + int pkt_length; }; /** emac_tx_bd: EMAC TX Buffer descriptor data structure @@ -290,12 +290,12 @@ struct emac_netpktobj { * EMAC TX Buffer descriptor data structure */ struct emac_tx_bd { - int h_next; - int buff_ptr; - int off_b_len; - int mode; /* SOP, EOP, ownership, EOQ, teardown,Qstarv, length */ - struct emac_tx_bd __iomem *next; - void *buf_token; + int h_next; + int buff_ptr; + int off_b_len; + int mode; /* SOP, EOP, ownership, EOQ, teardown,Qstarv, length */ + struct emac_tx_bd __iomem *next; + void *buf_token; }; /** emac_txch: EMAC TX Channel data structure @@ -303,29 +303,29 @@ struct emac_tx_bd { * EMAC TX Channel data structure */ struct emac_txch { - /* Config related */ - rt_uint32_t num_bd; - rt_uint32_t service_max; - - /* CPPI specific */ - rt_uint32_t alloc_size; - void __iomem *bd_mem; - struct emac_tx_bd __iomem *bd_pool_head; - struct emac_tx_bd __iomem *active_queue_head; - struct emac_tx_bd __iomem *active_queue_tail; - struct emac_tx_bd __iomem *last_hw_bdprocessed; - rt_uint32_t queue_active; - rt_uint32_t teardown_pending; - rt_uint32_t *tx_complete; - - /** statistics */ - rt_uint32_t proc_count; /* TX: # of times emac_tx_bdproc is called */ - rt_uint32_t mis_queued_packets; - rt_uint32_t queue_reinit; - rt_uint32_t end_of_queue_add; - rt_uint32_t out_of_tx_bd; - rt_uint32_t no_active_pkts; /* IRQ when there were no packets to process */ - rt_uint32_t active_queue_count; + /* Config related */ + rt_uint32_t num_bd; + rt_uint32_t service_max; + + /* CPPI specific */ + rt_uint32_t alloc_size; + void __iomem *bd_mem; + struct emac_tx_bd __iomem *bd_pool_head; + struct emac_tx_bd __iomem *active_queue_head; + struct emac_tx_bd __iomem *active_queue_tail; + struct emac_tx_bd __iomem *last_hw_bdprocessed; + rt_uint32_t queue_active; + rt_uint32_t teardown_pending; + rt_uint32_t *tx_complete; + + /** statistics */ + rt_uint32_t proc_count; /* TX: # of times emac_tx_bdproc is called */ + rt_uint32_t mis_queued_packets; + rt_uint32_t queue_reinit; + rt_uint32_t end_of_queue_add; + rt_uint32_t out_of_tx_bd; + rt_uint32_t no_active_pkts; /* IRQ when there were no packets to process */ + rt_uint32_t active_queue_count; }; /** emac_rx_bd: EMAC RX Buffer descriptor data structure @@ -333,13 +333,13 @@ struct emac_txch { * EMAC RX Buffer descriptor data structure */ struct emac_rx_bd { - int h_next; - int buff_ptr; - int off_b_len; - int mode; - struct emac_rx_bd __iomem *next; - void *data_ptr; - void *buf_token; + int h_next; + int buff_ptr; + int off_b_len; + int mode; + struct emac_rx_bd __iomem *next; + void *data_ptr; + void *buf_token; }; /** emac_rxch: EMAC RX Channel data structure @@ -347,68 +347,68 @@ struct emac_rx_bd { * EMAC RX Channel data structure */ struct emac_rxch { - /* configuration info */ - rt_uint32_t num_bd; - rt_uint32_t service_max; - rt_uint32_t buf_size; - char mac_addr[6]; - - /** CPPI specific */ - rt_uint32_t alloc_size; - void __iomem *bd_mem; - struct emac_rx_bd __iomem *bd_pool_head; - struct emac_rx_bd __iomem *active_queue_head; - struct emac_rx_bd __iomem *active_queue_tail; - rt_uint32_t queue_active; - rt_uint32_t teardown_pending; - - /* packet and buffer objects */ - struct emac_netpktobj pkt_queue; - struct emac_netbufobj buf_queue; - - /** statistics */ - rt_uint32_t proc_count; /* number of times emac_rx_bdproc is called */ - rt_uint32_t processed_bd; - rt_uint32_t recycled_bd; - rt_uint32_t out_of_rx_bd; - rt_uint32_t out_of_rx_buffers; - rt_uint32_t queue_reinit; - rt_uint32_t end_of_queue_add; - rt_uint32_t end_of_queue; - rt_uint32_t mis_queued_packets; + /* configuration info */ + rt_uint32_t num_bd; + rt_uint32_t service_max; + rt_uint32_t buf_size; + char mac_addr[6]; + + /** CPPI specific */ + rt_uint32_t alloc_size; + void __iomem *bd_mem; + struct emac_rx_bd __iomem *bd_pool_head; + struct emac_rx_bd __iomem *active_queue_head; + struct emac_rx_bd __iomem *active_queue_tail; + rt_uint32_t queue_active; + rt_uint32_t teardown_pending; + + /* packet and buffer objects */ + struct emac_netpktobj pkt_queue; + struct emac_netbufobj buf_queue; + + /** statistics */ + rt_uint32_t proc_count; /* number of times emac_rx_bdproc is called */ + rt_uint32_t processed_bd; + rt_uint32_t recycled_bd; + rt_uint32_t out_of_rx_bd; + rt_uint32_t out_of_rx_buffers; + rt_uint32_t queue_reinit; + rt_uint32_t end_of_queue_add; + rt_uint32_t end_of_queue; + rt_uint32_t mis_queued_packets; }; struct net_device_stats { - unsigned long rx_packets; /* total packets received */ - unsigned long tx_packets; /* total packets transmitted */ - unsigned long rx_bytes; /* total bytes received */ - unsigned long tx_bytes; /* total bytes transmitted */ - unsigned long rx_errors; /* bad packets received */ - unsigned long tx_errors; /* packet transmit problems */ - unsigned long rx_dropped; /* no space in linux buffers */ - unsigned long tx_dropped; /* no space available in linux */ - unsigned long multicast; /* multicast packets received */ - unsigned long collisions; - - /* detailed rx_errors: */ - unsigned long rx_length_errors; - unsigned long rx_over_errors; /* receiver ring buff overflow */ - unsigned long rx_crc_errors; /* recved pkt with crc error */ - unsigned long rx_frame_errors; /* recv'd frame alignment error */ - unsigned long rx_fifo_errors; /* recv'r fifo overrun */ - unsigned long rx_missed_errors; /* receiver missed packet */ - - /* detailed tx_errors */ - unsigned long tx_aborted_errors; - unsigned long tx_carrier_errors; - unsigned long tx_fifo_errors; - unsigned long tx_heartbeat_errors; - unsigned long tx_window_errors; - - /* for cslip etc */ - unsigned long rx_compressed; - unsigned long tx_compressed; + unsigned long rx_packets; /* total packets received */ + unsigned long tx_packets; /* total packets transmitted */ + unsigned long rx_bytes; /* total bytes received */ + unsigned long tx_bytes; /* total bytes transmitted */ + unsigned long rx_errors; /* bad packets received */ + unsigned long tx_errors; /* packet transmit problems */ + unsigned long rx_dropped; /* no space in linux buffers */ + unsigned long tx_dropped; /* no space available in linux */ + unsigned long multicast; /* multicast packets received */ + unsigned long collisions; + + /* detailed rx_errors: */ + unsigned long rx_length_errors; + unsigned long rx_over_errors; /* receiver ring buff overflow */ + unsigned long rx_crc_errors; /* recved pkt with crc error */ + unsigned long rx_frame_errors; /* recv'd frame alignment error */ + unsigned long rx_fifo_errors; /* recv'r fifo overrun */ + unsigned long rx_missed_errors; /* receiver missed packet */ + + /* detailed tx_errors */ + unsigned long tx_aborted_errors; + unsigned long tx_carrier_errors; + unsigned long tx_fifo_errors; + unsigned long tx_heartbeat_errors; + unsigned long tx_window_errors; + + /* for cslip etc */ + unsigned long rx_compressed; + unsigned long tx_compressed; }; @@ -419,44 +419,44 @@ struct net_device_stats #define MAX_ADDR_LEN 6 struct emac_priv { - /* inherit from ethernet device */ - struct eth_device parent; - - /* interface address info. */ - rt_uint8_t mac_addr[MAX_ADDR_LEN]; /* hw address */ - unsigned short phy_addr; - - struct rt_semaphore tx_lock; - struct rt_semaphore rx_lock; - void __iomem *remap_addr; - rt_uint32_t emac_base_phys; - void __iomem *emac_base; - void __iomem *ctrl_base; - void __iomem *emac_ctrl_ram; - void __iomem *mdio_base; - rt_uint32_t ctrl_ram_size; - rt_uint32_t hw_ram_addr; - struct emac_txch *txch[EMAC_DEF_MAX_TX_CH]; - struct emac_rxch *rxch[EMAC_DEF_MAX_RX_CH]; - rt_uint32_t link; /* 1=link on, 0=link off */ - rt_uint32_t speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */ - rt_uint32_t duplex; /* Link duplex: 0=Half, 1=Full */ - rt_uint32_t rx_buf_size; - rt_uint32_t isr_count; - rt_uint8_t rmii_en; - rt_uint8_t version; - struct net_device_stats net_dev_stats; - rt_uint32_t mac_hash1; - rt_uint32_t mac_hash2; - rt_uint32_t multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS]; - rt_uint32_t rx_addr_type; - /* periodic timer required for MDIO polling */ - struct rt_timer timer; - rt_uint32_t periodic_ticks; - rt_uint32_t timer_active; - rt_uint32_t phy_mask; - /* mii_bus,phy members */ - struct rt_semaphore lock; + /* inherit from ethernet device */ + struct eth_device parent; + + /* interface address info. */ + rt_uint8_t mac_addr[MAX_ADDR_LEN]; /* hw address */ + unsigned short phy_addr; + + struct rt_semaphore tx_lock; + struct rt_semaphore rx_lock; + void __iomem *remap_addr; + rt_uint32_t emac_base_phys; + void __iomem *emac_base; + void __iomem *ctrl_base; + void __iomem *emac_ctrl_ram; + void __iomem *mdio_base; + rt_uint32_t ctrl_ram_size; + rt_uint32_t hw_ram_addr; + struct emac_txch *txch[EMAC_DEF_MAX_TX_CH]; + struct emac_rxch *rxch[EMAC_DEF_MAX_RX_CH]; + rt_uint32_t link; /* 1=link on, 0=link off */ + rt_uint32_t speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */ + rt_uint32_t duplex; /* Link duplex: 0=Half, 1=Full */ + rt_uint32_t rx_buf_size; + rt_uint32_t isr_count; + rt_uint8_t rmii_en; + rt_uint8_t version; + struct net_device_stats net_dev_stats; + rt_uint32_t mac_hash1; + rt_uint32_t mac_hash2; + rt_uint32_t multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS]; + rt_uint32_t rx_addr_type; + /* periodic timer required for MDIO polling */ + struct rt_timer timer; + rt_uint32_t periodic_ticks; + rt_uint32_t timer_active; + rt_uint32_t phy_mask; + /* mii_bus,phy members */ + struct rt_semaphore lock; }; diff --git a/bsp/dm365/drivers/davinci_serial.c b/bsp/dm365/drivers/davinci_serial.c index 1b6b4b944b..96118ac347 100644 --- a/bsp/dm365/drivers/davinci_serial.c +++ b/bsp/dm365/drivers/davinci_serial.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ #include @@ -18,35 +18,35 @@ static struct rt_serial_device davinci_serial_dev0; static struct rt_serial_device davinci_serial_dev1; -#define LSR_DR 0x01 /* Data ready */ -#define LSR_THRE 0x20 /* Xmit holding register empty */ -//#define USTAT_TXB_EMPTY 0x02 /* tx buffer empty */ -#define BPS 115200 /* serial baudrate */ +#define LSR_DR 0x01 /* Data ready */ +#define LSR_THRE 0x20 /* Xmit holding register empty */ +//#define USTAT_TXB_EMPTY 0x02 /* tx buffer empty */ +#define BPS 115200 /* serial baudrate */ typedef struct uartport { - volatile rt_uint32_t rbr; - volatile rt_uint32_t ier; - volatile rt_uint32_t fcr; - volatile rt_uint32_t lcr; - volatile rt_uint32_t mcr; - volatile rt_uint32_t lsr; - volatile rt_uint32_t msr; - volatile rt_uint32_t scr; - volatile rt_uint32_t dll; - volatile rt_uint32_t dlh; - - volatile rt_uint32_t res[2]; - volatile rt_uint32_t pwremu_mgmt; - volatile rt_uint32_t mdr; + volatile rt_uint32_t rbr; + volatile rt_uint32_t ier; + volatile rt_uint32_t fcr; + volatile rt_uint32_t lcr; + volatile rt_uint32_t mcr; + volatile rt_uint32_t lsr; + volatile rt_uint32_t msr; + volatile rt_uint32_t scr; + volatile rt_uint32_t dll; + volatile rt_uint32_t dlh; + + volatile rt_uint32_t res[2]; + volatile rt_uint32_t pwremu_mgmt; + volatile rt_uint32_t mdr; }uartport; #define thr rbr #define iir fcr -#define UART0 ((struct uartport *)DAVINCI_UART0_BASE) +#define UART0 ((struct uartport *)DAVINCI_UART0_BASE) -#define UART1 ((struct uartport *)DM365_UART1_BASE) +#define UART1 ((struct uartport *)DM365_UART1_BASE) /** @@ -54,8 +54,8 @@ typedef struct uartport */ void rt_davinci_serial_handler(int vector, void *param) { - struct rt_serial_device *dev = (struct rt_serial_device *)param; - rt_hw_serial_isr(dev, RT_SERIAL_EVENT_RX_IND); + struct rt_serial_device *dev = (struct rt_serial_device *)param; + rt_hw_serial_isr(dev, RT_SERIAL_EVENT_RX_IND); } /** @@ -70,23 +70,23 @@ static rt_err_t davinci_uart_configure(struct rt_serial_device *serial, static rt_err_t davinci_uart_control(struct rt_serial_device *serial, int cmd, void *arg) { - uartport *uart = serial->parent.user_data; + uartport *uart = serial->parent.user_data; switch (cmd) { case RT_DEVICE_CTRL_CLR_INT: /* disable rx irq */ - if (uart == UART0) - rt_hw_interrupt_mask(IRQ_UARTINT0); - else if (uart == UART1) - rt_hw_interrupt_mask(IRQ_UARTINT1); + if (uart == UART0) + rt_hw_interrupt_mask(IRQ_UARTINT0); + else if (uart == UART1) + rt_hw_interrupt_mask(IRQ_UARTINT1); break; case RT_DEVICE_CTRL_SET_INT: /* enable rx irq */ - if (uart == UART0) - rt_hw_interrupt_umask(IRQ_UARTINT0); - else if (uart == UART1) - rt_hw_interrupt_umask(IRQ_UARTINT1); + if (uart == UART0) + rt_hw_interrupt_umask(IRQ_UARTINT0); + else if (uart == UART1) + rt_hw_interrupt_umask(IRQ_UARTINT1); break; } @@ -96,10 +96,10 @@ static rt_err_t davinci_uart_control(struct rt_serial_device *serial, static int davinci_uart_putc(struct rt_serial_device *serial, char c) { rt_uint32_t level; - uartport *uart = serial->parent.user_data; + uartport *uart = serial->parent.user_data; while (!(uart->lsr & LSR_THRE)); - uart->thr = c; + uart->thr = c; return 1; } @@ -107,16 +107,16 @@ static int davinci_uart_putc(struct rt_serial_device *serial, char c) static int davinci_uart_getc(struct rt_serial_device *serial) { int result; - uartport *uart = serial->parent.user_data; + uartport *uart = serial->parent.user_data; if (uart->lsr & LSR_DR) - { - result = uart->rbr & 0xff; - } - else - { - result = -1; - } + { + result = uart->rbr & 0xff; + } + else + { + result = -1; + } return result; } @@ -131,78 +131,78 @@ static const struct rt_uart_ops davinci_uart_ops = void davinci_uart0_init(void) { - rt_uint32_t divisor; - - divisor = (24000000 + (115200 * (16 / 2))) / (16 * 115200); - UART0->ier = 0; - UART0->lcr = 0x83; //8N1 - UART0->dll = 0; - UART0->dlh = 0; - UART0->lcr = 0x03; - UART0->mcr = 0x03; //RTS,CTS - UART0->fcr = 0x07; //FIFO - UART0->lcr = 0x83; - UART0->dll = divisor & 0xff; - UART0->dlh = (divisor >> 8) & 0xff; - UART0->lcr = 0x03; - UART0->mdr = 0; //16x over-sampling - UART0->pwremu_mgmt = 0x6000; - rt_hw_interrupt_install(IRQ_UARTINT0, rt_davinci_serial_handler, - (void *)&davinci_serial_dev0, "UART0"); - rt_hw_interrupt_mask(IRQ_UARTINT0); - UART0->ier = 0x05; + rt_uint32_t divisor; + + divisor = (24000000 + (115200 * (16 / 2))) / (16 * 115200); + UART0->ier = 0; + UART0->lcr = 0x83; //8N1 + UART0->dll = 0; + UART0->dlh = 0; + UART0->lcr = 0x03; + UART0->mcr = 0x03; //RTS,CTS + UART0->fcr = 0x07; //FIFO + UART0->lcr = 0x83; + UART0->dll = divisor & 0xff; + UART0->dlh = (divisor >> 8) & 0xff; + UART0->lcr = 0x03; + UART0->mdr = 0; //16x over-sampling + UART0->pwremu_mgmt = 0x6000; + rt_hw_interrupt_install(IRQ_UARTINT0, rt_davinci_serial_handler, + (void *)&davinci_serial_dev0, "UART0"); + rt_hw_interrupt_mask(IRQ_UARTINT0); + UART0->ier = 0x05; } void davinci_uart_gpio_init() { - rt_uint32_t val; - - val = davinci_readl(PINMUX3); - val &= 0xf3ffffff; /* gio23 RS485_CTRL */ - val |= 0x60000000; /*UART1_TXD (gio25)*/ - davinci_writel(val, PINMUX3); - val = davinci_readl(PINMUX4); - val |= 0x0000c000; /* UART1_RXD (gio34) */ - davinci_writel(val, PINMUX4); - - val = davinci_readl(DAVINCI_GPIO_BASE + 0x10); - val &= ~(1 << 23); - davinci_writel(val, DAVINCI_GPIO_BASE + 0x10); - davinci_writel((1<<23), DAVINCI_GPIO_BASE + 0x1C); + rt_uint32_t val; + + val = davinci_readl(PINMUX3); + val &= 0xf3ffffff; /* gio23 RS485_CTRL */ + val |= 0x60000000; /*UART1_TXD (gio25)*/ + davinci_writel(val, PINMUX3); + val = davinci_readl(PINMUX4); + val |= 0x0000c000; /* UART1_RXD (gio34) */ + davinci_writel(val, PINMUX4); + + val = davinci_readl(DAVINCI_GPIO_BASE + 0x10); + val &= ~(1 << 23); + davinci_writel(val, DAVINCI_GPIO_BASE + 0x10); + davinci_writel((1<<23), DAVINCI_GPIO_BASE + 0x1C); } void davinci_uart1_init(void) { - rt_uint32_t divisor; - rt_uint32_t freq; - rt_uint32_t baudrate; - struct clk *clk; - - davinci_uart_gpio_init(); - psc_change_state(DAVINCI_DM365_LPSC_UART1, PSC_ENABLE); - clk = clk_get("UART1"); - freq = clk_get_rate(clk); - - baudrate = 9600; - divisor = (freq + (baudrate * (16 / 2))) / (16 * baudrate); - UART1->ier = 0; - UART1->lcr = 0x87; //8N2, 0x83 8N1 - UART1->dll = 0; - UART1->dlh = 0; - UART1->lcr = 0x07; - UART1->mcr = 0x03; //RTS,CTS - UART1->fcr = 0x07; //FIFO - UART1->lcr = 0x87; - UART1->dll = divisor & 0xff; - UART1->dlh = (divisor >> 8) & 0xff; - UART1->lcr = 0x07; - UART1->mdr = 0; //16x over-sampling - UART1->pwremu_mgmt = 0x6000; - - rt_hw_interrupt_install(IRQ_UARTINT1, rt_davinci_serial_handler, - (void *)&davinci_serial_dev1, "UART1"); - rt_hw_interrupt_mask(IRQ_UARTINT1); - UART1->ier = 0x05; + rt_uint32_t divisor; + rt_uint32_t freq; + rt_uint32_t baudrate; + struct clk *clk; + + davinci_uart_gpio_init(); + psc_change_state(DAVINCI_DM365_LPSC_UART1, PSC_ENABLE); + clk = clk_get("UART1"); + freq = clk_get_rate(clk); + + baudrate = 9600; + divisor = (freq + (baudrate * (16 / 2))) / (16 * baudrate); + UART1->ier = 0; + UART1->lcr = 0x87; //8N2, 0x83 8N1 + UART1->dll = 0; + UART1->dlh = 0; + UART1->lcr = 0x07; + UART1->mcr = 0x03; //RTS,CTS + UART1->fcr = 0x07; //FIFO + UART1->lcr = 0x87; + UART1->dll = divisor & 0xff; + UART1->dlh = (divisor >> 8) & 0xff; + UART1->lcr = 0x07; + UART1->mdr = 0; //16x over-sampling + UART1->pwremu_mgmt = 0x6000; + + rt_hw_interrupt_install(IRQ_UARTINT1, rt_davinci_serial_handler, + (void *)&davinci_serial_dev1, "UART1"); + rt_hw_interrupt_mask(IRQ_UARTINT1); + UART1->ier = 0x05; } @@ -211,39 +211,39 @@ void davinci_uart1_init(void) */ int rt_hw_uart_init(void) { - davinci_serial_dev0.ops = &davinci_uart_ops; + davinci_serial_dev0.ops = &davinci_uart_ops; //davinci_serial_dev0.config = RT_SERIAL_CONFIG_DEFAULT; - davinci_serial_dev0.config.baud_rate = BAUD_RATE_115200; + davinci_serial_dev0.config.baud_rate = BAUD_RATE_115200; davinci_serial_dev0.config.bit_order = BIT_ORDER_LSB; davinci_serial_dev0.config.data_bits = DATA_BITS_8; davinci_serial_dev0.config.parity = PARITY_NONE; davinci_serial_dev0.config.stop_bits = STOP_BITS_1; davinci_serial_dev0.config.invert = NRZ_NORMAL; - davinci_serial_dev0.config.bufsz = RT_SERIAL_RB_BUFSZ; + davinci_serial_dev0.config.bufsz = RT_SERIAL_RB_BUFSZ; /* register vcom device */ rt_hw_serial_register(&davinci_serial_dev0, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, UART0); - davinci_uart0_init(); + davinci_uart0_init(); - davinci_serial_dev1.ops = &davinci_uart_ops; + davinci_serial_dev1.ops = &davinci_uart_ops; //davinci_serial_dev1.config = RT_SERIAL_CONFIG_DEFAULT; - davinci_serial_dev1.config.baud_rate = BAUD_RATE_115200; + davinci_serial_dev1.config.baud_rate = BAUD_RATE_115200; davinci_serial_dev1.config.bit_order = BIT_ORDER_LSB; davinci_serial_dev1.config.data_bits = DATA_BITS_8; davinci_serial_dev1.config.parity = PARITY_NONE; davinci_serial_dev1.config.stop_bits = STOP_BITS_1; davinci_serial_dev1.config.invert = NRZ_NORMAL; - davinci_serial_dev1.config.bufsz = RT_SERIAL_RB_BUFSZ; + davinci_serial_dev1.config.bufsz = RT_SERIAL_RB_BUFSZ; /* register vcom device */ rt_hw_serial_register(&davinci_serial_dev1, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, UART1); - davinci_uart1_init(); + davinci_uart1_init(); - return 0; + return 0; } INIT_BOARD_EXPORT(rt_hw_uart_init); diff --git a/bsp/dm365/drivers/gpio.c b/bsp/dm365/drivers/gpio.c index 47c40b2e19..b226c736c8 100644 --- a/bsp/dm365/drivers/gpio.c +++ b/bsp/dm365/drivers/gpio.c @@ -4,159 +4,159 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ #include #include "gpio.h" -#define GPIO0_BASE (DAVINCI_GPIO_BASE + 0x10) -#define GPIO1_BASE (DAVINCI_GPIO_BASE + 0x38) -#define GPIO2_BASE (DAVINCI_GPIO_BASE + 0x60) -#define GPIO3_BASE (DAVINCI_GPIO_BASE + 0x88) +#define GPIO0_BASE (DAVINCI_GPIO_BASE + 0x10) +#define GPIO1_BASE (DAVINCI_GPIO_BASE + 0x38) +#define GPIO2_BASE (DAVINCI_GPIO_BASE + 0x60) +#define GPIO3_BASE (DAVINCI_GPIO_BASE + 0x88) static unsigned int dm365_gpio_base = (unsigned int)GPIO0_BASE; -#define GPIO_OE (dm365_gpio_base + 0x00) -#define GPIO_DATAIN (dm365_gpio_base + 0x10) -#define GPIO_DATAOUT (dm365_gpio_base + 0x04) -#define GPIO_CLROUT (dm365_gpio_base + 0x0C) -#define GPIO_SETOUT (dm365_gpio_base + 0x08) +#define GPIO_OE (dm365_gpio_base + 0x00) +#define GPIO_DATAIN (dm365_gpio_base + 0x10) +#define GPIO_DATAOUT (dm365_gpio_base + 0x04) +#define GPIO_CLROUT (dm365_gpio_base + 0x0C) +#define GPIO_SETOUT (dm365_gpio_base + 0x08) -#define gpio_dirin(n) *(volatile unsigned int *)((GPIO_OE)) |= 1<<(n) -#define gpio_dirout(n) *(volatile unsigned int *)((GPIO_OE)) &= ~(1u<<(n)) -#define gpio_set(n) *(volatile unsigned int *)((GPIO_SETOUT)) = 1<<(n) -#define gpio_clr(n) *(volatile unsigned int *)((GPIO_CLROUT)) = 1<<(n) -#define gpio_get(n) ( ( *(volatile unsigned int *)((GPIO_DATAIN)) & (1<<(n)) ) ? 1 : 0 ) +#define gpio_dirin(n) *(volatile unsigned int *)((GPIO_OE)) |= 1<<(n) +#define gpio_dirout(n) *(volatile unsigned int *)((GPIO_OE)) &= ~(1u<<(n)) +#define gpio_set(n) *(volatile unsigned int *)((GPIO_SETOUT)) = 1<<(n) +#define gpio_clr(n) *(volatile unsigned int *)((GPIO_CLROUT)) = 1<<(n) +#define gpio_get(n) ( ( *(volatile unsigned int *)((GPIO_DATAIN)) & (1<<(n)) ) ? 1 : 0 ) #define GPIO_GRP_MASK (5) - + static int gpio_to_base(unsigned int gpio) { - unsigned int grp_idx; - int ret; - - grp_idx = gpio >> GPIO_GRP_MASK; - - switch (grp_idx) { - case 0: - dm365_gpio_base = (unsigned int)GPIO0_BASE; - ret = 0; - break; - case 1: - dm365_gpio_base = (unsigned int)GPIO1_BASE; - ret = 0; - break; - case 2: - dm365_gpio_base = (unsigned int)GPIO2_BASE; - ret = 0; - break; - case 3: - dm365_gpio_base = (unsigned int)GPIO3_BASE; - ret = 0; - break; - default: - ret =-RT_EIO; - break; - } - return ret; + unsigned int grp_idx; + int ret; + + grp_idx = gpio >> GPIO_GRP_MASK; + + switch (grp_idx) { + case 0: + dm365_gpio_base = (unsigned int)GPIO0_BASE; + ret = 0; + break; + case 1: + dm365_gpio_base = (unsigned int)GPIO1_BASE; + ret = 0; + break; + case 2: + dm365_gpio_base = (unsigned int)GPIO2_BASE; + ret = 0; + break; + case 3: + dm365_gpio_base = (unsigned int)GPIO3_BASE; + ret = 0; + break; + default: + ret =-RT_EIO; + break; + } + return ret; } int gpio_direction_input(unsigned int gpio) { - unsigned int offset; - int ret=0; + unsigned int offset; + int ret=0; - rt_ubase_t temp = rt_hw_interrupt_disable(); - ret = gpio_to_base(gpio); - if (ret < 0) { - goto gpio_free; - } - offset = gpio & ((1 << GPIO_GRP_MASK) -1); + rt_ubase_t temp = rt_hw_interrupt_disable(); + ret = gpio_to_base(gpio); + if (ret < 0) { + goto gpio_free; + } + offset = gpio & ((1 << GPIO_GRP_MASK) -1); - gpio_dirin(offset); + gpio_dirin(offset); gpio_free: - rt_hw_interrupt_enable(temp); + rt_hw_interrupt_enable(temp); - return ret; + return ret; } int gpio_direction_output(unsigned int gpio, int value) { - unsigned int offset; - int ret=0; + unsigned int offset; + int ret=0; - rt_ubase_t temp = rt_hw_interrupt_disable(); - ret = gpio_to_base(gpio); - if (ret < 0) { - goto gpio_free; - } + rt_ubase_t temp = rt_hw_interrupt_disable(); + ret = gpio_to_base(gpio); + if (ret < 0) { + goto gpio_free; + } - offset = gpio & ((1 << GPIO_GRP_MASK) -1); + offset = gpio & ((1 << GPIO_GRP_MASK) -1); - if (value) { - gpio_set(offset); - } - else { - gpio_clr(offset); - } + if (value) { + gpio_set(offset); + } + else { + gpio_clr(offset); + } - gpio_dirout(offset); + gpio_dirout(offset); gpio_free: - rt_hw_interrupt_enable(temp); + rt_hw_interrupt_enable(temp); - return ret; + return ret; } int gpio_set_value(unsigned int gpio, int value) { - unsigned int offset; - int ret=0; + unsigned int offset; + int ret=0; - rt_ubase_t temp = rt_hw_interrupt_disable(); - ret = gpio_to_base(gpio); - if (ret < 0) { - goto gpio_free; - } + rt_ubase_t temp = rt_hw_interrupt_disable(); + ret = gpio_to_base(gpio); + if (ret < 0) { + goto gpio_free; + } - offset = gpio & ((1 << GPIO_GRP_MASK) -1); + offset = gpio & ((1 << GPIO_GRP_MASK) -1); - if (value) { - gpio_set(offset); - } - else { - gpio_clr(offset); - } + if (value) { + gpio_set(offset); + } + else { + gpio_clr(offset); + } gpio_free: - rt_hw_interrupt_enable(temp); + rt_hw_interrupt_enable(temp); - return ret; + return ret; } int gpio_get_value(unsigned int gpio) { - unsigned int offset; - int ret=0; + unsigned int offset; + int ret=0; - rt_ubase_t temp = rt_hw_interrupt_disable(); - ret = gpio_to_base(gpio); - if (ret < 0) { - goto gpio_free; - } + rt_ubase_t temp = rt_hw_interrupt_disable(); + ret = gpio_to_base(gpio); + if (ret < 0) { + goto gpio_free; + } - offset = gpio & ((1 << GPIO_GRP_MASK) -1); - ret = gpio_get(offset); + offset = gpio & ((1 << GPIO_GRP_MASK) -1); + ret = gpio_get(offset); gpio_free: - rt_hw_interrupt_enable(temp); + rt_hw_interrupt_enable(temp); - return ret; + return ret; } diff --git a/bsp/dm365/drivers/gpio.h b/bsp/dm365/drivers/gpio.h index 5e648596ee..a6c8265648 100644 --- a/bsp/dm365/drivers/gpio.h +++ b/bsp/dm365/drivers/gpio.h @@ -4,34 +4,34 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ -#ifndef __DM365_GPIO_H -#define __DM365_GPIO_H +#ifndef __DM365_GPIO_H +#define __DM365_GPIO_H #include -#define GPIO(X) (X) +#define GPIO(X) (X) -#define get_io(r) *((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) -#define set_io(r,v) *((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) = (v) -#define and_io(r,v) *((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) &= (v) -#define or_io(r,v) *((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) |= (v) +#define get_io(r) *((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) +#define set_io(r,v) *((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) = (v) +#define and_io(r,v) *((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) &= (v) +#define or_io(r,v) *((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) |= (v) -#define v_get_io(r) *((volatile u_int *)(r)) -#define v_set_io(r,v) *((volatile u_int *)(r)) = (v) -#define v_and_io(r,v) *((volatile u_int *)(r)) &= (v) -#define v_or_io(r,v) *((volatile u_int *)(r)) |= (v) +#define v_get_io(r) *((volatile u_int *)(r)) +#define v_set_io(r,v) *((volatile u_int *)(r)) = (v) +#define v_and_io(r,v) *((volatile u_int *)(r)) &= (v) +#define v_or_io(r,v) *((volatile u_int *)(r)) |= (v) enum gpio_intr_mode { LEVELDETECT_LOW = 0, LEVELDETECT_HIGH, - RISINGDETECT, + RISINGDETECT, FALLINGDETECT, - EDGEDETECT //both rising-edge and falling-edge detect + EDGEDETECT //both rising-edge and falling-edge detect }; enum gpio_intr_req @@ -42,10 +42,10 @@ enum gpio_intr_req enum gpio_intr_num { - GPIOINT0A = 96, - GPIOINT0B, - GPIOINT1A, - GPIOINT1B, + GPIOINT0A = 96, + GPIOINT0B, + GPIOINT1A, + GPIOINT1B, }; enum pin_func_mod @@ -56,4 +56,4 @@ enum pin_func_mod IIC_MOD=0x20 }; -#endif /* __TI814X_GPIO_H */ +#endif /* __TI814X_GPIO_H */ diff --git a/bsp/dm365/drivers/i2c-davinci.c b/bsp/dm365/drivers/i2c-davinci.c index 8c67cfce80..6da4e72d6c 100644 --- a/bsp/dm365/drivers/i2c-davinci.c +++ b/bsp/dm365/drivers/i2c-davinci.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ #include @@ -13,61 +13,61 @@ #include /* ----- global defines ----------------------------------------------- */ -#define BIT(nr) (1UL << (nr)) +#define BIT(nr) (1UL << (nr)) -#define DAVINCI_I2C_TIMEOUT (1*RT_TICK_PER_SECOND) -#define DAVINCI_I2C_MAX_TRIES 2 +#define DAVINCI_I2C_TIMEOUT (1*RT_TICK_PER_SECOND) +#define DAVINCI_I2C_MAX_TRIES 2 #define I2C_DAVINCI_INTR_ALL (DAVINCI_I2C_IMR_AAS | \ - DAVINCI_I2C_IMR_SCD | \ - DAVINCI_I2C_IMR_ARDY | \ - DAVINCI_I2C_IMR_NACK | \ - DAVINCI_I2C_IMR_AL) - -#define DAVINCI_I2C_OAR_REG 0x00 -#define DAVINCI_I2C_IMR_REG 0x04 -#define DAVINCI_I2C_STR_REG 0x08 -#define DAVINCI_I2C_CLKL_REG 0x0c -#define DAVINCI_I2C_CLKH_REG 0x10 -#define DAVINCI_I2C_CNT_REG 0x14 -#define DAVINCI_I2C_DRR_REG 0x18 -#define DAVINCI_I2C_SAR_REG 0x1c -#define DAVINCI_I2C_DXR_REG 0x20 -#define DAVINCI_I2C_MDR_REG 0x24 -#define DAVINCI_I2C_IVR_REG 0x28 -#define DAVINCI_I2C_EMDR_REG 0x2c -#define DAVINCI_I2C_PSC_REG 0x30 - -#define DAVINCI_I2C_IVR_AAS 0x07 -#define DAVINCI_I2C_IVR_SCD 0x06 -#define DAVINCI_I2C_IVR_XRDY 0x05 -#define DAVINCI_I2C_IVR_RDR 0x04 -#define DAVINCI_I2C_IVR_ARDY 0x03 -#define DAVINCI_I2C_IVR_NACK 0x02 -#define DAVINCI_I2C_IVR_AL 0x01 - -#define DAVINCI_I2C_STR_BB BIT(12) -#define DAVINCI_I2C_STR_RSFULL BIT(11) -#define DAVINCI_I2C_STR_SCD BIT(5) -#define DAVINCI_I2C_STR_ARDY BIT(2) -#define DAVINCI_I2C_STR_NACK BIT(1) -#define DAVINCI_I2C_STR_AL BIT(0) - -#define DAVINCI_I2C_MDR_NACK BIT(15) -#define DAVINCI_I2C_MDR_STT BIT(13) -#define DAVINCI_I2C_MDR_STP BIT(11) -#define DAVINCI_I2C_MDR_MST BIT(10) -#define DAVINCI_I2C_MDR_TRX BIT(9) -#define DAVINCI_I2C_MDR_XA BIT(8) -#define DAVINCI_I2C_MDR_RM BIT(7) -#define DAVINCI_I2C_MDR_IRS BIT(5) - -#define DAVINCI_I2C_IMR_AAS BIT(6) -#define DAVINCI_I2C_IMR_SCD BIT(5) -#define DAVINCI_I2C_IMR_XRDY BIT(4) -#define DAVINCI_I2C_IMR_RRDY BIT(3) -#define DAVINCI_I2C_IMR_ARDY BIT(2) -#define DAVINCI_I2C_IMR_NACK BIT(1) -#define DAVINCI_I2C_IMR_AL BIT(0) + DAVINCI_I2C_IMR_SCD | \ + DAVINCI_I2C_IMR_ARDY | \ + DAVINCI_I2C_IMR_NACK | \ + DAVINCI_I2C_IMR_AL) + +#define DAVINCI_I2C_OAR_REG 0x00 +#define DAVINCI_I2C_IMR_REG 0x04 +#define DAVINCI_I2C_STR_REG 0x08 +#define DAVINCI_I2C_CLKL_REG 0x0c +#define DAVINCI_I2C_CLKH_REG 0x10 +#define DAVINCI_I2C_CNT_REG 0x14 +#define DAVINCI_I2C_DRR_REG 0x18 +#define DAVINCI_I2C_SAR_REG 0x1c +#define DAVINCI_I2C_DXR_REG 0x20 +#define DAVINCI_I2C_MDR_REG 0x24 +#define DAVINCI_I2C_IVR_REG 0x28 +#define DAVINCI_I2C_EMDR_REG 0x2c +#define DAVINCI_I2C_PSC_REG 0x30 + +#define DAVINCI_I2C_IVR_AAS 0x07 +#define DAVINCI_I2C_IVR_SCD 0x06 +#define DAVINCI_I2C_IVR_XRDY 0x05 +#define DAVINCI_I2C_IVR_RDR 0x04 +#define DAVINCI_I2C_IVR_ARDY 0x03 +#define DAVINCI_I2C_IVR_NACK 0x02 +#define DAVINCI_I2C_IVR_AL 0x01 + +#define DAVINCI_I2C_STR_BB BIT(12) +#define DAVINCI_I2C_STR_RSFULL BIT(11) +#define DAVINCI_I2C_STR_SCD BIT(5) +#define DAVINCI_I2C_STR_ARDY BIT(2) +#define DAVINCI_I2C_STR_NACK BIT(1) +#define DAVINCI_I2C_STR_AL BIT(0) + +#define DAVINCI_I2C_MDR_NACK BIT(15) +#define DAVINCI_I2C_MDR_STT BIT(13) +#define DAVINCI_I2C_MDR_STP BIT(11) +#define DAVINCI_I2C_MDR_MST BIT(10) +#define DAVINCI_I2C_MDR_TRX BIT(9) +#define DAVINCI_I2C_MDR_XA BIT(8) +#define DAVINCI_I2C_MDR_RM BIT(7) +#define DAVINCI_I2C_MDR_IRS BIT(5) + +#define DAVINCI_I2C_IMR_AAS BIT(6) +#define DAVINCI_I2C_IMR_SCD BIT(5) +#define DAVINCI_I2C_IMR_XRDY BIT(4) +#define DAVINCI_I2C_IMR_RRDY BIT(3) +#define DAVINCI_I2C_IMR_ARDY BIT(2) +#define DAVINCI_I2C_IMR_NACK BIT(1) +#define DAVINCI_I2C_IMR_AL BIT(0) #ifdef RT_EDMA_DEBUG #define i2c_dbg(fmt, ...) rt_kprintf(fmt, ##__VA_ARGS__) @@ -77,42 +77,42 @@ struct davinci_i2c_dev { - void *base; - struct rt_semaphore completion; - struct clk *clk; - int cmd_err; - rt_uint8_t *buf; - rt_uint32_t buf_len; - int irq; - int stop; - rt_uint8_t terminate; - rt_uint32_t bus_freq; - rt_uint32_t bus_delay; - struct rt_i2c_bus_device *bus; + void *base; + struct rt_semaphore completion; + struct clk *clk; + int cmd_err; + rt_uint8_t *buf; + rt_uint32_t buf_len; + int irq; + int stop; + rt_uint8_t terminate; + rt_uint32_t bus_freq; + rt_uint32_t bus_delay; + struct rt_i2c_bus_device *bus; }; static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev, - int reg, rt_uint16_t val) + int reg, rt_uint16_t val) { - davinci_writew(val, i2c_dev->base + reg); + davinci_writew(val, i2c_dev->base + reg); } static inline rt_uint16_t davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg) { - return davinci_readw(i2c_dev->base + reg); + return davinci_readw(i2c_dev->base + reg); } static void udelay (rt_uint32_t us) { - rt_int32_t i; - for (; us > 0; us--) - { - i = 50000; - while(i > 0) - { - i--; - } - } + rt_int32_t i; + for (; us > 0; us--) + { + i = 50000; + while(i > 0) + { + i--; + } + } } @@ -120,17 +120,17 @@ static void udelay (rt_uint32_t us) /* Generate a pulse on the i2c clock pin. */ static void generic_i2c_clock_pulse(unsigned int scl_pin) { - rt_uint16_t i; - - if (scl_pin) { - /* Send high and low on the SCL line */ - for (i = 0; i < 9; i++) { - gpio_set_value(scl_pin, 0); - udelay(20); - gpio_set_value(scl_pin, 1); - udelay(20); - } - } + rt_uint16_t i; + + if (scl_pin) { + /* Send high and low on the SCL line */ + for (i = 0; i < 9; i++) { + gpio_set_value(scl_pin, 0); + udelay(20); + gpio_set_value(scl_pin, 1); + udelay(20); + } + } } #endif @@ -139,78 +139,78 @@ static void generic_i2c_clock_pulse(unsigned int scl_pin) */ static void i2c_recover_bus(struct davinci_i2c_dev *dev) { - rt_uint32_t flag = 0; - - i2c_dbg("initiating i2c bus recovery\n"); - /* Send NACK to the slave */ - flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); - flag |= DAVINCI_I2C_MDR_NACK; - /* write the data into mode register */ - davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); + rt_uint32_t flag = 0; + + i2c_dbg("initiating i2c bus recovery\n"); + /* Send NACK to the slave */ + flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); + flag |= DAVINCI_I2C_MDR_NACK; + /* write the data into mode register */ + davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); #if 0 - if (pdata) - generic_i2c_clock_pulse(pdata->scl_pin); + if (pdata) + generic_i2c_clock_pulse(pdata->scl_pin); #endif - /* Send STOP */ - flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); - flag |= DAVINCI_I2C_MDR_STP; - davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); + /* Send STOP */ + flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); + flag |= DAVINCI_I2C_MDR_STP; + davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); } static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev, - int val) + int val) { - rt_uint16_t w; + rt_uint16_t w; - w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG); - if (!val) /* put I2C into reset */ - w &= ~DAVINCI_I2C_MDR_IRS; - else /* take I2C out of reset */ - w |= DAVINCI_I2C_MDR_IRS; + w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG); + if (!val) /* put I2C into reset */ + w &= ~DAVINCI_I2C_MDR_IRS; + else /* take I2C out of reset */ + w |= DAVINCI_I2C_MDR_IRS; - davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w); + davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w); } static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev) { - rt_uint16_t psc; - rt_uint32_t clk; - rt_uint32_t d; - rt_uint32_t clkh; - rt_uint32_t clkl; - rt_uint32_t input_clock = clk_get_rate(dev->clk); - - /* NOTE: I2C Clock divider programming info - * As per I2C specs the following formulas provide prescaler - * and low/high divider values - * input clk --> PSC Div -----------> ICCL/H Div --> output clock - * module clk - * - * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ] - * - * Thus, - * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d; - * - * where if PSC == 0, d = 7, - * if PSC == 1, d = 6 - * if PSC > 1 , d = 5 - */ - - /* get minimum of 7 MHz clock, but max of 12 MHz */ - psc = (input_clock / 7000000) - 1; - if ((input_clock / (psc + 1)) > 12000000) - psc++; /* better to run under spec than over */ - d = (psc >= 2) ? 5 : 7 - psc; - - clk = ((input_clock / (psc + 1)) / (dev->bus_freq * 1000)) - (d << 1); - clkh = clk >> 1; - clkl = clk - clkh; - - davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc); - davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh); - davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl); - - i2c_dbg("input_clock = %d, CLK = %d\n", input_clock, clk); + rt_uint16_t psc; + rt_uint32_t clk; + rt_uint32_t d; + rt_uint32_t clkh; + rt_uint32_t clkl; + rt_uint32_t input_clock = clk_get_rate(dev->clk); + + /* NOTE: I2C Clock divider programming info + * As per I2C specs the following formulas provide prescaler + * and low/high divider values + * input clk --> PSC Div -----------> ICCL/H Div --> output clock + * module clk + * + * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ] + * + * Thus, + * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d; + * + * where if PSC == 0, d = 7, + * if PSC == 1, d = 6 + * if PSC > 1 , d = 5 + */ + + /* get minimum of 7 MHz clock, but max of 12 MHz */ + psc = (input_clock / 7000000) - 1; + if ((input_clock / (psc + 1)) > 12000000) + psc++; /* better to run under spec than over */ + d = (psc >= 2) ? 5 : 7 - psc; + + clk = ((input_clock / (psc + 1)) / (dev->bus_freq * 1000)) - (d << 1); + clkh = clk >> 1; + clkl = clk - clkh; + + davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc); + davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh); + davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl); + + i2c_dbg("input_clock = %d, CLK = %d\n", input_clock, clk); } /* @@ -220,65 +220,65 @@ static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev) */ static int i2c_davinci_init(struct davinci_i2c_dev *dev) { - /* put I2C into reset */ - davinci_i2c_reset_ctrl(dev, 0); + /* put I2C into reset */ + davinci_i2c_reset_ctrl(dev, 0); - /* compute clock dividers */ - i2c_davinci_calc_clk_dividers(dev); + /* compute clock dividers */ + i2c_davinci_calc_clk_dividers(dev); - /* Respond at reserved "SMBus Host" slave address" (and zero); - * we seem to have no option to not respond... - */ - davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, 0x08); + /* Respond at reserved "SMBus Host" slave address" (and zero); + * we seem to have no option to not respond... + */ + davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, 0x08); - i2c_dbg("PSC = %d\n", - davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG)); - i2c_dbg("CLKL = %d\n", - davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG)); - i2c_dbg("CLKH = %d\n", - davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG)); - i2c_dbg("bus_freq = %dkHz, bus_delay = %d\n", - dev->bus_freq, dev->bus_delay); + i2c_dbg("PSC = %d\n", + davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG)); + i2c_dbg("CLKL = %d\n", + davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG)); + i2c_dbg("CLKH = %d\n", + davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG)); + i2c_dbg("bus_freq = %dkHz, bus_delay = %d\n", + dev->bus_freq, dev->bus_delay); - /* Take the I2C module out of reset: */ - davinci_i2c_reset_ctrl(dev, 1); + /* Take the I2C module out of reset: */ + davinci_i2c_reset_ctrl(dev, 1); - /* Enable interrupts */ - davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL); + /* Enable interrupts */ + davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL); - return 0; + return 0; } /* * Waiting for bus not busy */ static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev, - char allow_sleep) + char allow_sleep) { - unsigned long timeout; - static rt_uint16_t to_cnt; - RT_ASSERT(dev != RT_NULL); - RT_ASSERT(dev->bus != RT_NULL); - - timeout = rt_tick_get() + dev->bus->timeout; - while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) - & DAVINCI_I2C_STR_BB) { - if (to_cnt <= DAVINCI_I2C_MAX_TRIES) { - if (rt_tick_get() >= timeout) { - rt_kprintf("timeout waiting for bus ready\n"); - to_cnt++; - return -RT_ETIMEOUT; - } else { - to_cnt = 0; - i2c_recover_bus(dev); - i2c_davinci_init(dev); - } - } - if (allow_sleep) - rt_thread_delay(2); - } - - return 0; + unsigned long timeout; + static rt_uint16_t to_cnt; + RT_ASSERT(dev != RT_NULL); + RT_ASSERT(dev->bus != RT_NULL); + + timeout = rt_tick_get() + dev->bus->timeout; + while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) + & DAVINCI_I2C_STR_BB) { + if (to_cnt <= DAVINCI_I2C_MAX_TRIES) { + if (rt_tick_get() >= timeout) { + rt_kprintf("timeout waiting for bus ready\n"); + to_cnt++; + return -RT_ETIMEOUT; + } else { + to_cnt = 0; + i2c_recover_bus(dev); + i2c_davinci_init(dev); + } + } + if (allow_sleep) + rt_thread_delay(2); + } + + return 0; } /* @@ -288,125 +288,125 @@ static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev, static int i2c_davinci_xfer_msg(struct rt_i2c_bus_device *bus, struct rt_i2c_msg *msg, int stop) { - struct davinci_i2c_dev *dev = bus->priv; - rt_uint32_t flag; - rt_uint16_t w; - int r; - - /* Introduce a delay, required for some boards (e.g Davinci EVM) */ - if (dev->bus_delay) - udelay(dev->bus_delay); - - /* set the slave address */ - davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr); - - dev->buf = msg->buf; - dev->buf_len = msg->len; - dev->stop = stop; - - davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len); - - //INIT_COMPLETION(dev->cmd_complete); - dev->cmd_err = 0; - - /* Take I2C out of reset and configure it as master */ - flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST; - - /* if the slave address is ten bit address, enable XA bit */ - if (msg->flags & RT_I2C_ADDR_10BIT) - flag |= DAVINCI_I2C_MDR_XA; - if (!(msg->flags & RT_I2C_RD)) - flag |= DAVINCI_I2C_MDR_TRX; - if (msg->len == 0) - flag |= DAVINCI_I2C_MDR_RM; - - /* Enable receive or transmit interrupts */ - w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG); - if (msg->flags & RT_I2C_RD) - w |= DAVINCI_I2C_IMR_RRDY; - else - w |= DAVINCI_I2C_IMR_XRDY; - davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w); - - dev->terminate = 0; - - /* - * Write mode register first as needed for correct behaviour - * on OMAP-L138, but don't set STT yet to avoid a race with XRDY - * occurring before we have loaded DXR - */ - davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); - - /* - * First byte should be set here, not after interrupt, - * because transmit-data-ready interrupt can come before - * NACK-interrupt during sending of previous message and - * ICDXR may have wrong data - * It also saves us one interrupt, slightly faster - */ - if ((!(msg->flags & RT_I2C_RD)) && dev->buf_len) - { - davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++); - dev->buf_len--; - } - - /* Set STT to begin transmit now DXR is loaded */ - flag |= DAVINCI_I2C_MDR_STT; - if (stop && msg->len != 0) - flag |= DAVINCI_I2C_MDR_STP; - davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); - - r = rt_sem_take(&dev->completion, dev->bus->timeout); - if (r == -RT_ETIMEOUT) - { - rt_kprintf("controller timed out\n"); - i2c_recover_bus(dev); - i2c_davinci_init(dev); - dev->buf_len = 0; - return -RT_ETIMEOUT; - } - if (dev->buf_len) - { - /* This should be 0 if all bytes were transferred - * or dev->cmd_err denotes an error. - * A signal may have aborted the transfer. - */ - if (r == RT_EOK) - { - rt_kprintf("abnormal termination buf_len=%i\n", - dev->buf_len); - r = -RT_EIO; - } - dev->terminate = 1; - dev->buf_len = 0; - } - if (r < 0) - return r; - - /* no error */ - if (!dev->cmd_err) - return msg->len; - - /* We have an error */ - if (dev->cmd_err & DAVINCI_I2C_STR_AL) - { - i2c_davinci_init(dev); - return -RT_EIO; - } - - if (dev->cmd_err & DAVINCI_I2C_STR_NACK) - { - if (msg->flags & RT_I2C_IGNORE_NACK) - return msg->len; - if (stop) - { - w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); - w |= DAVINCI_I2C_MDR_STP; - davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); - } - return -RT_EIO; - } - return -RT_EIO; + struct davinci_i2c_dev *dev = bus->priv; + rt_uint32_t flag; + rt_uint16_t w; + int r; + + /* Introduce a delay, required for some boards (e.g Davinci EVM) */ + if (dev->bus_delay) + udelay(dev->bus_delay); + + /* set the slave address */ + davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr); + + dev->buf = msg->buf; + dev->buf_len = msg->len; + dev->stop = stop; + + davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len); + + //INIT_COMPLETION(dev->cmd_complete); + dev->cmd_err = 0; + + /* Take I2C out of reset and configure it as master */ + flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST; + + /* if the slave address is ten bit address, enable XA bit */ + if (msg->flags & RT_I2C_ADDR_10BIT) + flag |= DAVINCI_I2C_MDR_XA; + if (!(msg->flags & RT_I2C_RD)) + flag |= DAVINCI_I2C_MDR_TRX; + if (msg->len == 0) + flag |= DAVINCI_I2C_MDR_RM; + + /* Enable receive or transmit interrupts */ + w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG); + if (msg->flags & RT_I2C_RD) + w |= DAVINCI_I2C_IMR_RRDY; + else + w |= DAVINCI_I2C_IMR_XRDY; + davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w); + + dev->terminate = 0; + + /* + * Write mode register first as needed for correct behaviour + * on OMAP-L138, but don't set STT yet to avoid a race with XRDY + * occurring before we have loaded DXR + */ + davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); + + /* + * First byte should be set here, not after interrupt, + * because transmit-data-ready interrupt can come before + * NACK-interrupt during sending of previous message and + * ICDXR may have wrong data + * It also saves us one interrupt, slightly faster + */ + if ((!(msg->flags & RT_I2C_RD)) && dev->buf_len) + { + davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++); + dev->buf_len--; + } + + /* Set STT to begin transmit now DXR is loaded */ + flag |= DAVINCI_I2C_MDR_STT; + if (stop && msg->len != 0) + flag |= DAVINCI_I2C_MDR_STP; + davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); + + r = rt_sem_take(&dev->completion, dev->bus->timeout); + if (r == -RT_ETIMEOUT) + { + rt_kprintf("controller timed out\n"); + i2c_recover_bus(dev); + i2c_davinci_init(dev); + dev->buf_len = 0; + return -RT_ETIMEOUT; + } + if (dev->buf_len) + { + /* This should be 0 if all bytes were transferred + * or dev->cmd_err denotes an error. + * A signal may have aborted the transfer. + */ + if (r == RT_EOK) + { + rt_kprintf("abnormal termination buf_len=%i\n", + dev->buf_len); + r = -RT_EIO; + } + dev->terminate = 1; + dev->buf_len = 0; + } + if (r < 0) + return r; + + /* no error */ + if (!dev->cmd_err) + return msg->len; + + /* We have an error */ + if (dev->cmd_err & DAVINCI_I2C_STR_AL) + { + i2c_davinci_init(dev); + return -RT_EIO; + } + + if (dev->cmd_err & DAVINCI_I2C_STR_NACK) + { + if (msg->flags & RT_I2C_IGNORE_NACK) + return msg->len; + if (stop) + { + w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); + w |= DAVINCI_I2C_MDR_STP; + davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); + } + return -RT_EIO; + } + return -RT_EIO; } /* @@ -415,52 +415,52 @@ i2c_davinci_xfer_msg(struct rt_i2c_bus_device *bus, struct rt_i2c_msg *msg, int static int i2c_davinci_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], int num) { - struct davinci_i2c_dev *dev = bus->priv; - int i; - int ret; - - i2c_dbg("%s: msgs: %d\n", __func__, num); - - ret = i2c_davinci_wait_bus_not_busy(dev, 1); - if (ret < 0) - { - i2c_dbg("timeout waiting for bus ready\n"); - return ret; - } - - for (i = 0; i < num; i++) - { - ret = i2c_davinci_xfer_msg(bus, &msgs[i], (i == (num - 1))); - i2c_dbg("%s [%d/%d] ret: %d\n", __func__, i + 1, num, - ret); - if (ret < 0) - return ret; - } - - - return num; + struct davinci_i2c_dev *dev = bus->priv; + int i; + int ret; + + i2c_dbg("%s: msgs: %d\n", __func__, num); + + ret = i2c_davinci_wait_bus_not_busy(dev, 1); + if (ret < 0) + { + i2c_dbg("timeout waiting for bus ready\n"); + return ret; + } + + for (i = 0; i < num; i++) + { + ret = i2c_davinci_xfer_msg(bus, &msgs[i], (i == (num - 1))); + i2c_dbg("%s [%d/%d] ret: %d\n", __func__, i + 1, num, + ret); + if (ret < 0) + return ret; + } + + + return num; } static void terminate_read(struct davinci_i2c_dev *dev) { - rt_uint16_t w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); - w |= DAVINCI_I2C_MDR_NACK; - davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); - - /* Throw away data */ - davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG); - if (!dev->terminate) - rt_kprintf("RDR IRQ while no data requested\n"); + rt_uint16_t w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); + w |= DAVINCI_I2C_MDR_NACK; + davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); + + /* Throw away data */ + davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG); + if (!dev->terminate) + rt_kprintf("RDR IRQ while no data requested\n"); } static void terminate_write(struct davinci_i2c_dev *dev) { - rt_uint16_t w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); - w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP; - davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); + rt_uint16_t w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); + w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP; + davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); - if (!dev->terminate) - i2c_dbg("TDR IRQ while no data to send\n"); + if (!dev->terminate) + i2c_dbg("TDR IRQ while no data to send\n"); } /* @@ -469,173 +469,173 @@ static void terminate_write(struct davinci_i2c_dev *dev) */ static void i2c_davinci_isr(int irq, void *param) { - struct davinci_i2c_dev *dev = (struct davinci_i2c_dev *)param; - rt_uint32_t stat; - int count = 0; - rt_uint16_t w; - - while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) { - i2c_dbg("%s: stat=0x%x\n", __func__, stat); - if (count++ == 100) { - rt_kprintf("Too much work in one IRQ\n"); - break; - } - - switch (stat) { - case DAVINCI_I2C_IVR_AL: - /* Arbitration lost, must retry */ - dev->cmd_err |= DAVINCI_I2C_STR_AL; - dev->buf_len = 0; - rt_sem_release(&dev->completion); - break; - - case DAVINCI_I2C_IVR_NACK: - dev->cmd_err |= DAVINCI_I2C_STR_NACK; - dev->buf_len = 0; - rt_sem_release(&dev->completion); - break; - - case DAVINCI_I2C_IVR_ARDY: - davinci_i2c_write_reg(dev, - DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY); - if (((dev->buf_len == 0) && (dev->stop != 0)) || - (dev->cmd_err & DAVINCI_I2C_STR_NACK)) { - w = davinci_i2c_read_reg(dev, - DAVINCI_I2C_MDR_REG); - w |= DAVINCI_I2C_MDR_STP; - davinci_i2c_write_reg(dev, - DAVINCI_I2C_MDR_REG, w); - } - rt_sem_release(&dev->completion); - break; - - case DAVINCI_I2C_IVR_RDR: - if (dev->buf_len) { - *dev->buf++ = - davinci_i2c_read_reg(dev, - DAVINCI_I2C_DRR_REG); - dev->buf_len--; - if (dev->buf_len) - continue; - - davinci_i2c_write_reg(dev, - DAVINCI_I2C_STR_REG, - DAVINCI_I2C_IMR_RRDY); - } else { - /* signal can terminate transfer */ - terminate_read(dev); - } - break; - - case DAVINCI_I2C_IVR_XRDY: - if (dev->buf_len) { - davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, - *dev->buf++); - dev->buf_len--; - if (dev->buf_len) - continue; - - w = davinci_i2c_read_reg(dev, - DAVINCI_I2C_IMR_REG); - w &= ~DAVINCI_I2C_IMR_XRDY; - davinci_i2c_write_reg(dev, - DAVINCI_I2C_IMR_REG, - w); - } else { - /* signal can terminate transfer */ - terminate_write(dev); - } - break; - - case DAVINCI_I2C_IVR_SCD: - davinci_i2c_write_reg(dev, - DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD); - rt_sem_release(&dev->completion); - break; - - case DAVINCI_I2C_IVR_AAS: - i2c_dbg("Address as slave interrupt\n"); - break; - - default: - i2c_dbg("Unrecognized irq stat %d\n", stat); - break; - } - } + struct davinci_i2c_dev *dev = (struct davinci_i2c_dev *)param; + rt_uint32_t stat; + int count = 0; + rt_uint16_t w; + + while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) { + i2c_dbg("%s: stat=0x%x\n", __func__, stat); + if (count++ == 100) { + rt_kprintf("Too much work in one IRQ\n"); + break; + } + + switch (stat) { + case DAVINCI_I2C_IVR_AL: + /* Arbitration lost, must retry */ + dev->cmd_err |= DAVINCI_I2C_STR_AL; + dev->buf_len = 0; + rt_sem_release(&dev->completion); + break; + + case DAVINCI_I2C_IVR_NACK: + dev->cmd_err |= DAVINCI_I2C_STR_NACK; + dev->buf_len = 0; + rt_sem_release(&dev->completion); + break; + + case DAVINCI_I2C_IVR_ARDY: + davinci_i2c_write_reg(dev, + DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY); + if (((dev->buf_len == 0) && (dev->stop != 0)) || + (dev->cmd_err & DAVINCI_I2C_STR_NACK)) { + w = davinci_i2c_read_reg(dev, + DAVINCI_I2C_MDR_REG); + w |= DAVINCI_I2C_MDR_STP; + davinci_i2c_write_reg(dev, + DAVINCI_I2C_MDR_REG, w); + } + rt_sem_release(&dev->completion); + break; + + case DAVINCI_I2C_IVR_RDR: + if (dev->buf_len) { + *dev->buf++ = + davinci_i2c_read_reg(dev, + DAVINCI_I2C_DRR_REG); + dev->buf_len--; + if (dev->buf_len) + continue; + + davinci_i2c_write_reg(dev, + DAVINCI_I2C_STR_REG, + DAVINCI_I2C_IMR_RRDY); + } else { + /* signal can terminate transfer */ + terminate_read(dev); + } + break; + + case DAVINCI_I2C_IVR_XRDY: + if (dev->buf_len) { + davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, + *dev->buf++); + dev->buf_len--; + if (dev->buf_len) + continue; + + w = davinci_i2c_read_reg(dev, + DAVINCI_I2C_IMR_REG); + w &= ~DAVINCI_I2C_IMR_XRDY; + davinci_i2c_write_reg(dev, + DAVINCI_I2C_IMR_REG, + w); + } else { + /* signal can terminate transfer */ + terminate_write(dev); + } + break; + + case DAVINCI_I2C_IVR_SCD: + davinci_i2c_write_reg(dev, + DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD); + rt_sem_release(&dev->completion); + break; + + case DAVINCI_I2C_IVR_AAS: + i2c_dbg("Address as slave interrupt\n"); + break; + + default: + i2c_dbg("Unrecognized irq stat %d\n", stat); + break; + } + } } static struct rt_i2c_bus_device_ops bus_ops = { - .master_xfer = i2c_davinci_xfer, + .master_xfer = i2c_davinci_xfer, }; int davinci_i2c_init(char *bus_name) { - struct rt_i2c_bus_device *bus; - struct davinci_i2c_dev *dev; - int r; + struct rt_i2c_bus_device *bus; + struct davinci_i2c_dev *dev; + int r; - bus = rt_malloc(sizeof(struct rt_i2c_bus_device)); - if (bus == RT_NULL) - { - rt_kprintf("rt_malloc failed\n"); - return -RT_ENOMEM; - } - - rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device)); + bus = rt_malloc(sizeof(struct rt_i2c_bus_device)); + if (bus == RT_NULL) + { + rt_kprintf("rt_malloc failed\n"); + return -RT_ENOMEM; + } - bus->ops = &bus_ops; - bus->timeout = DAVINCI_I2C_TIMEOUT; + rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device)); - dev = rt_malloc(sizeof(struct davinci_i2c_dev)); - if (!dev) - { - r = -RT_ENOMEM; - goto err; - } + bus->ops = &bus_ops; + bus->timeout = DAVINCI_I2C_TIMEOUT; - rt_memset((void *)dev, 0, sizeof(struct davinci_i2c_dev)); + dev = rt_malloc(sizeof(struct davinci_i2c_dev)); + if (!dev) + { + r = -RT_ENOMEM; + goto err; + } - rt_sem_init(&dev->completion, "i2c_ack", 0, RT_IPC_FLAG_FIFO); + rt_memset((void *)dev, 0, sizeof(struct davinci_i2c_dev)); - dev->irq = IRQ_I2C; + rt_sem_init(&dev->completion, "i2c_ack", 0, RT_IPC_FLAG_FIFO); - dev->clk = clk_get("I2CCLK"); - if (dev->clk == RT_NULL) { - r = -RT_ERROR; - goto err1; - } + dev->irq = IRQ_I2C; - psc_change_state(DAVINCI_DM365_LPSC_I2C, 3); + dev->clk = clk_get("I2CCLK"); + if (dev->clk == RT_NULL) { + r = -RT_ERROR; + goto err1; + } - dev->base = DAVINCI_I2C_BASE; - dev->bus_freq = 100; - dev->bus_delay = 0; - dev->bus = bus; + psc_change_state(DAVINCI_DM365_LPSC_I2C, 3); - bus->priv = dev; + dev->base = DAVINCI_I2C_BASE; + dev->bus_freq = 100; + dev->bus_delay = 0; + dev->bus = bus; - i2c_davinci_init(dev); + bus->priv = dev; - rt_hw_interrupt_install(dev->irq, i2c_davinci_isr, (void *)dev, "I2C"); - rt_hw_interrupt_umask(dev->irq); + i2c_davinci_init(dev); - return rt_i2c_bus_device_register(bus, bus_name); + rt_hw_interrupt_install(dev->irq, i2c_davinci_isr, (void *)dev, "I2C"); + rt_hw_interrupt_umask(dev->irq); + + return rt_i2c_bus_device_register(bus, bus_name); err1: - rt_free(dev); + rt_free(dev); err: - rt_free(bus); + rt_free(bus); - return r; + return r; } int rt_hw_iic_init(void) { - davinci_i2c_init("I2C1"); + davinci_i2c_init("I2C1"); } INIT_DEVICE_EXPORT(rt_hw_iic_init); diff --git a/bsp/dm365/drivers/mii.h b/bsp/dm365/drivers/mii.h index d567b9fa84..8b42352bf4 100644 --- a/bsp/dm365/drivers/mii.h +++ b/bsp/dm365/drivers/mii.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-03-18 weety first version + * Date Author Notes + * 2011-03-18 weety first version */ @@ -23,7 +23,7 @@ #define MII_EXPANSION 0x06 /* Expansion register */ #define MII_CTRL1000 0x09 /* 1000BASE-T control */ #define MII_STAT1000 0x0a /* 1000BASE-T status */ -#define MII_ESTATUS 0x0f /* Extended Status */ +#define MII_ESTATUS 0x0f /* Extended Status */ #define MII_DCOUNTER 0x12 /* Disconnect counter */ #define MII_FCSCOUNTER 0x13 /* False carrier counter */ #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ @@ -38,7 +38,7 @@ /* Basic mode control register. */ #define BMCR_RESV 0x003f /* Unused... */ -#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ +#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ #define BMCR_CTST 0x0080 /* Collision test */ #define BMCR_FULLDPLX 0x0100 /* Full duplex */ #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ @@ -57,7 +57,7 @@ #define BMSR_RFAULT 0x0010 /* Remote fault detected */ #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ #define BMSR_RESV 0x00c0 /* Unused... */ -#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ +#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */ #define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */ #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ @@ -86,7 +86,7 @@ #define ADVERTISE_NPAGE 0x8000 /* Next page bit */ #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ - ADVERTISE_CSMA) + ADVERTISE_CSMA) #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ ADVERTISE_100HALF | ADVERTISE_100FULL) @@ -108,8 +108,8 @@ #define LPA_LPACK 0x4000 /* Link partner acked us */ #define LPA_NPAGE 0x8000 /* Next page bit */ -#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) -#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) +#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) +#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) /* Expansion register for auto-negotiation. */ #define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */ @@ -119,8 +119,8 @@ #define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ #define EXPANSION_RESV 0xffe0 /* Unused... */ -#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ -#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ +#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ +#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ /* N-way test register. */ #define NWAYTEST_RESV1 0x00ff /* Unused... */ @@ -138,8 +138,8 @@ #define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */ /* Flow control flags */ -#define FLOW_CTRL_TX 0x01 -#define FLOW_CTRL_RX 0x02 +#define FLOW_CTRL_TX 0x01 +#define FLOW_CTRL_RX 0x02 /** * mii_nway_result @@ -174,11 +174,11 @@ rt_inline unsigned int mii_nway_result (unsigned int negotiated) } /* The forced speed, 10Mb, 100Mb, gigabit, 2.5Gb, 10GbE. */ -#define SPEED_10 10 -#define SPEED_100 100 -#define SPEED_1000 1000 -#define SPEED_2500 2500 -#define SPEED_10000 10000 +#define SPEED_10 10 +#define SPEED_100 100 +#define SPEED_1000 1000 +#define SPEED_2500 2500 +#define SPEED_10000 10000 #endif /* __MII_H__ */ diff --git a/bsp/dm365/drivers/mmcsd.c b/bsp/dm365/drivers/mmcsd.c index 7fcd0ef0c7..8e12236256 100644 --- a/bsp/dm365/drivers/mmcsd.c +++ b/bsp/dm365/drivers/mmcsd.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ #include @@ -18,66 +18,66 @@ #define RT_USING_MMCSD0 -#define MMCSD_DEBUG 0 +#define MMCSD_DEBUG 0 #if MMCSD_DEBUG -#define mmc_dbg(fmt, ...) rt_kprintf(fmt, ##__VA_ARGS__) +#define mmc_dbg(fmt, ...) rt_kprintf(fmt, ##__VA_ARGS__) #else #define mmc_dbg(fmt, ...) #endif -#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<29)) -#define CACHE_LINE_SIZE 32 +#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<29)) +#define CACHE_LINE_SIZE 32 extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size); extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); -#define EVT_QUEUE_NUM 0 /* EDMA3 Event queue number. */ +#define EVT_QUEUE_NUM 0 /* EDMA3 Event queue number. */ static unsigned rw_threshold = 32; static rt_bool_t use_dma = RT_TRUE; enum DATA_DIR_TYPE { - DM365_MMC_DATADIR_NONE = 0, - DM365_MMC_DATADIR_READ, - DM365_MMC_DATADIR_WRITE, + DM365_MMC_DATADIR_NONE = 0, + DM365_MMC_DATADIR_READ, + DM365_MMC_DATADIR_WRITE, }; -struct mmc_dm365_host +struct mmc_dm365_host { - struct rt_mmcsd_host *mmc; - struct rt_mmcsd_req *req; - struct rt_mmcsd_data *data; - struct rt_mmcsd_cmd *cmd; - struct edmacc_param tx_template; - struct edmacc_param rx_template; + struct rt_mmcsd_host *mmc; + struct rt_mmcsd_req *req; + struct rt_mmcsd_data *data; + struct rt_mmcsd_cmd *cmd; + struct edmacc_param tx_template; + struct edmacc_param rx_template; - rt_uint32_t mmc_input_clk; - rt_uint32_t ns_in_one_cycle; /* for ns in one cycle calculation */ + rt_uint32_t mmc_input_clk; + rt_uint32_t ns_in_one_cycle; /* for ns in one cycle calculation */ - mmcsd_regs_t *mmcsd_regs; - rt_uint8_t bus_mode; + mmcsd_regs_t *mmcsd_regs; + rt_uint8_t bus_mode; - enum DATA_DIR_TYPE data_dir; + enum DATA_DIR_TYPE data_dir; - rt_uint32_t rxdma; - rt_uint32_t txdma; - rt_bool_t use_dma; - rt_bool_t do_dma; + rt_uint32_t rxdma; + rt_uint32_t txdma; + rt_bool_t use_dma; + rt_bool_t do_dma; - rt_uint8_t *buffer; - rt_uint32_t buffer_bytes_left; - rt_uint32_t bytes_left; + rt_uint8_t *buffer; + rt_uint32_t buffer_bytes_left; + rt_uint32_t bytes_left; - rt_uint8_t *dma_buffer; - rt_bool_t use_dma_buffer; - rt_bool_t sdio_int; + rt_uint8_t *dma_buffer; + rt_bool_t use_dma_buffer; + rt_bool_t sdio_int; }; void *mmc_priv(struct rt_mmcsd_host *host) { - return (void *)host->private_data; + return (void *)host->private_data; } static void delay_us(rt_uint32_t us) @@ -90,968 +90,968 @@ static void delay_us(rt_uint32_t us) /******************************************************************************************************* ** 函数名称: calculate_freq_for_card() ** 功能描述: 此函数用于计算设置SD卡频率所需的分频数 -** -** 输　入: host -> DM365 MMC host句柄 -** mmc_req_freq -> MMC工作频率 +** +** 输　入: host -> DM365 MMC host句柄 +** mmc_req_freq -> MMC工作频率 ** ** 输　出: 分频值 -** -** 全局变量: +** +** 全局变量: ** 调用模块: 无 ** ********************************************************************************************************/ static rt_uint32_t calculate_freq_for_card(struct mmc_dm365_host *host, rt_uint32_t mmc_req_freq) { - rt_uint32_t mmc_freq = 0; - rt_uint32_t mmc_pclk = 0; - rt_uint32_t mmc_push_pull_divisor = 0; - - mmc_pclk = host->mmc_input_clk; - - if (mmc_req_freq && mmc_pclk > (2 * mmc_req_freq)) - mmc_push_pull_divisor = ((rt_uint32_t)mmc_pclk / (2 * mmc_req_freq)) - 1; - else - mmc_push_pull_divisor = 0; - - mmc_freq = (rt_uint32_t)mmc_pclk / (2 * (mmc_push_pull_divisor + 1)); - - if (mmc_freq > mmc_req_freq) - mmc_push_pull_divisor = mmc_push_pull_divisor + 1; - - /* Convert ns to clock cycles */ - if (mmc_req_freq <= 400000) - host->ns_in_one_cycle = (1000000)/(((mmc_pclk/(2*(mmc_push_pull_divisor+1)))/1000)); - else - host->ns_in_one_cycle = (1000000)/(((mmc_pclk/(2*(mmc_push_pull_divisor+1)))/1000000)); - - return mmc_push_pull_divisor; + rt_uint32_t mmc_freq = 0; + rt_uint32_t mmc_pclk = 0; + rt_uint32_t mmc_push_pull_divisor = 0; + + mmc_pclk = host->mmc_input_clk; + + if (mmc_req_freq && mmc_pclk > (2 * mmc_req_freq)) + mmc_push_pull_divisor = ((rt_uint32_t)mmc_pclk / (2 * mmc_req_freq)) - 1; + else + mmc_push_pull_divisor = 0; + + mmc_freq = (rt_uint32_t)mmc_pclk / (2 * (mmc_push_pull_divisor + 1)); + + if (mmc_freq > mmc_req_freq) + mmc_push_pull_divisor = mmc_push_pull_divisor + 1; + + /* Convert ns to clock cycles */ + if (mmc_req_freq <= 400000) + host->ns_in_one_cycle = (1000000)/(((mmc_pclk/(2*(mmc_push_pull_divisor+1)))/1000)); + else + host->ns_in_one_cycle = (1000000)/(((mmc_pclk/(2*(mmc_push_pull_divisor+1)))/1000000)); + + return mmc_push_pull_divisor; } /******************************************************************************************************* ** 函数名称: calculate_freq_for_card() ** 功能描述: 此函数用于计算MMC clock分频数 -** -** 输　入: host -> DM365 MMC host句柄 -** ios -> MMC 操作句柄 +** +** 输　入: host -> DM365 MMC host句柄 +** ios -> MMC 操作句柄 ** ** 输　出: 读取到的PHY寄存器值 -** -** 全局变量: +** +** 全局变量: ** 调用模块: 无 ** ********************************************************************************************************/ static void calculate_clk_divider(struct rt_mmcsd_host *mmc, struct rt_mmcsd_io_cfg *ios) { - rt_uint32_t temp = 0; - rt_uint32_t mmc_pclk = 0; - rt_uint32_t open_drain_freq = 0; - rt_uint32_t mmc_push_pull_freq = 0; - struct mmc_dm365_host *host = mmc_priv(mmc); - - mmc_pclk = host->mmc_input_clk; - - if (ios->bus_mode == MMCSD_BUSMODE_OPENDRAIN) - { - /* Ignoring the init clock value passed for fixing the inter - * operability with different cards. - */ - open_drain_freq = ((rt_uint32_t)mmc_pclk / (2 * MMCSD_INIT_CLOCK)) - 1; - - if (open_drain_freq > 0xFF) - open_drain_freq = 0xFF; - - temp = host->mmcsd_regs->MMCCLK & ~MMCCLK_CLKRT_MASK; - temp |= open_drain_freq; - host->mmcsd_regs->MMCCLK = temp; - - - /* Convert ns to clock cycles */ - host->ns_in_one_cycle = (1000000) / (MMCSD_INIT_CLOCK / 1000); - } - else - { - mmc_push_pull_freq = calculate_freq_for_card(host, ios->clock); - - if (mmc_push_pull_freq > 0xFF) - mmc_push_pull_freq = 0xFF; - - temp = host->mmcsd_regs->MMCCLK & ~MMCCLK_CLKEN; - host->mmcsd_regs->MMCCLK = temp; - - delay_us(10); - - temp = host->mmcsd_regs->MMCCLK & ~MMCCLK_CLKRT_MASK; - temp |= mmc_push_pull_freq; - host->mmcsd_regs->MMCCLK = temp; - - host->mmcsd_regs->MMCCLK = temp | MMCCLK_CLKEN; - - delay_us(10); - } + rt_uint32_t temp = 0; + rt_uint32_t mmc_pclk = 0; + rt_uint32_t open_drain_freq = 0; + rt_uint32_t mmc_push_pull_freq = 0; + struct mmc_dm365_host *host = mmc_priv(mmc); + + mmc_pclk = host->mmc_input_clk; + + if (ios->bus_mode == MMCSD_BUSMODE_OPENDRAIN) + { + /* Ignoring the init clock value passed for fixing the inter + * operability with different cards. + */ + open_drain_freq = ((rt_uint32_t)mmc_pclk / (2 * MMCSD_INIT_CLOCK)) - 1; + + if (open_drain_freq > 0xFF) + open_drain_freq = 0xFF; + + temp = host->mmcsd_regs->MMCCLK & ~MMCCLK_CLKRT_MASK; + temp |= open_drain_freq; + host->mmcsd_regs->MMCCLK = temp; + + + /* Convert ns to clock cycles */ + host->ns_in_one_cycle = (1000000) / (MMCSD_INIT_CLOCK / 1000); + } + else + { + mmc_push_pull_freq = calculate_freq_for_card(host, ios->clock); + + if (mmc_push_pull_freq > 0xFF) + mmc_push_pull_freq = 0xFF; + + temp = host->mmcsd_regs->MMCCLK & ~MMCCLK_CLKEN; + host->mmcsd_regs->MMCCLK = temp; + + delay_us(10); + + temp = host->mmcsd_regs->MMCCLK & ~MMCCLK_CLKRT_MASK; + temp |= mmc_push_pull_freq; + host->mmcsd_regs->MMCCLK = temp; + + host->mmcsd_regs->MMCCLK = temp | MMCCLK_CLKEN; + + delay_us(10); + } } /******************************************************************************************************* ** 函数名称: mmc_dm365_set_ios() ** 功能描述: 此函数是mmc设置设置 -** -** 输　入: mmc -> mmc host 句柄 -** ios -> mmc 操作句柄 +** +** 输　入: mmc -> mmc host 句柄 +** ios -> mmc 操作句柄 ** ** 输　出: 无 -** -** 全局变量: +** +** 全局变量: ** 调用模块: 无 ** ********************************************************************************************************/ static void mmc_dm365_set_ios(struct rt_mmcsd_host *mmc, struct rt_mmcsd_io_cfg *ios) { - struct mmc_dm365_host *host = mmc_priv(mmc); + struct mmc_dm365_host *host = mmc_priv(mmc); - mmc_dbg("clock %dHz busmode %d powermode %d Vdd %04x\n", ios->clock, ios->bus_mode, ios->power_mode, ios->vdd); + mmc_dbg("clock %dHz busmode %d powermode %d Vdd %04x\n", ios->clock, ios->bus_mode, ios->power_mode, ios->vdd); - switch (ios->bus_width) + switch (ios->bus_width) { - case MMCSD_BUS_WIDTH_8: + case MMCSD_BUS_WIDTH_8: mmc_dbg("Enabling 8 bit mode\n"); - host->mmcsd_regs->MMCCTL = (host->mmcsd_regs->MMCCTL & ~MMCCTL_WIDTH_4_BIT) | MMCCTL_WIDTH_8_BIT; - break; - case MMCSD_BUS_WIDTH_4: + host->mmcsd_regs->MMCCTL = (host->mmcsd_regs->MMCCTL & ~MMCCTL_WIDTH_4_BIT) | MMCCTL_WIDTH_8_BIT; + break; + case MMCSD_BUS_WIDTH_4: mmc_dbg("Enabling 4 bit mode\n"); - host->mmcsd_regs->MMCCTL = (host->mmcsd_regs->MMCCTL & ~MMCCTL_WIDTH_8_BIT) | MMCCTL_WIDTH_4_BIT; - break; - case MMCSD_BUS_WIDTH_1: + host->mmcsd_regs->MMCCTL = (host->mmcsd_regs->MMCCTL & ~MMCCTL_WIDTH_8_BIT) | MMCCTL_WIDTH_4_BIT; + break; + case MMCSD_BUS_WIDTH_1: mmc_dbg("Enabling 1 bit mode\n"); - host->mmcsd_regs->MMCCTL = host->mmcsd_regs->MMCCTL & ~(MMCCTL_WIDTH_8_BIT | MMCCTL_WIDTH_4_BIT); - break; - } + host->mmcsd_regs->MMCCTL = host->mmcsd_regs->MMCCTL & ~(MMCCTL_WIDTH_8_BIT | MMCCTL_WIDTH_4_BIT); + break; + } - calculate_clk_divider(mmc, ios); + calculate_clk_divider(mmc, ios); - host->bus_mode = ios->bus_mode; - if (ios->power_mode == MMCSD_POWER_UP) + host->bus_mode = ios->bus_mode; + if (ios->power_mode == MMCSD_POWER_UP) { - unsigned long timeout = rt_tick_get() + 500; - rt_bool_t lose = 1; - - host->mmcsd_regs->MMCARGHL = 0; - host->mmcsd_regs->MMCCMD = MMCCMD_INITCK; - - while (rt_tick_get() < timeout) - { - rt_uint32_t tmp = host->mmcsd_regs->MMCST0; - - if (tmp & MMCST0_RSPDNE) - { - lose = 0; - break; - } - } - if (lose) - mmc_dbg("powerup timeout\n"); - } + unsigned long timeout = rt_tick_get() + 500; + rt_bool_t lose = 1; + + host->mmcsd_regs->MMCARGHL = 0; + host->mmcsd_regs->MMCCMD = MMCCMD_INITCK; + + while (rt_tick_get() < timeout) + { + rt_uint32_t tmp = host->mmcsd_regs->MMCST0; + + if (tmp & MMCST0_RSPDNE) + { + lose = 0; + break; + } + } + if (lose) + mmc_dbg("powerup timeout\n"); + } } /******************************************************************************************************* ** 函数名称: dm365_fifo_data_trans() ** 功能描述: 此函数是fifo模式传输 -** -** 输　入: host -> DM365 mmc host 句柄 -** n -> 传输字节数 +** +** 输　入: host -> DM365 mmc host 句柄 +** n -> 传输字节数 ** ** 输　出: 无 -** -** 全局变量: +** +** 全局变量: ** 调用模块: 无 ** ********************************************************************************************************/ static void dm365_fifo_data_trans(struct mmc_dm365_host *host, rt_uint32_t n) { - rt_uint8_t *p; - rt_uint32_t i; - - p = host->buffer; - - if (host->bytes_left < n) - n = host->bytes_left; - - host->bytes_left -= n; - - /* NOTE: we never transfer more than rw_threshold bytes - * to/from the fifo here; there's no I/O overlap. - * This also assumes that access width( i.e. ACCWD) is 4 bytes - */ - if (host->data_dir == DM365_MMC_DATADIR_WRITE) - { - for (i = 0; i < (n >> 2); i++) - { - host->mmcsd_regs->MMCDXR = *((rt_uint32_t *)p); - p = p + 4; - } - if (n & 3) - { - rt_kprintf("to do ... \n"); -// iowrite8_rep(host->base + MMCSD_MMCDXR, p, (n & 3)); - p = p + (n & 3); - } - } - else - { - for (i = 0; i < (n >> 2); i++) - { - *((rt_uint32_t *)p) = host->mmcsd_regs->MMCDRR; - p = p + 4; - } - if (n & 3) - { + rt_uint8_t *p; + rt_uint32_t i; + + p = host->buffer; + + if (host->bytes_left < n) + n = host->bytes_left; + + host->bytes_left -= n; + + /* NOTE: we never transfer more than rw_threshold bytes + * to/from the fifo here; there's no I/O overlap. + * This also assumes that access width( i.e. ACCWD) is 4 bytes + */ + if (host->data_dir == DM365_MMC_DATADIR_WRITE) + { + for (i = 0; i < (n >> 2); i++) + { + host->mmcsd_regs->MMCDXR = *((rt_uint32_t *)p); + p = p + 4; + } + if (n & 3) + { + rt_kprintf("to do ... \n"); +// iowrite8_rep(host->base + MMCSD_MMCDXR, p, (n & 3)); + p = p + (n & 3); + } + } + else + { + for (i = 0; i < (n >> 2); i++) + { + *((rt_uint32_t *)p) = host->mmcsd_regs->MMCDRR; + p = p + 4; + } + if (n & 3) + { rt_kprintf("to do ... \n"); -// ioread8_rep(host->base + MMCSD_MMCDRR, p, (n & 3)); - p = p + (n & 3); - } - } - host->buffer = p; +// ioread8_rep(host->base + MMCSD_MMCDRR, p, (n & 3)); + p = p + (n & 3); + } + } + host->buffer = p; } /******************************************************************************************************* ** 函数名称: mmc_dm365_start_command() ** 功能描述: 此函数是开始发送SD命令 -** -** 输　入: host -> DM365 mmc host 句柄 -** cmd -> SD命令句柄 +** +** 输　入: host -> DM365 mmc host 句柄 +** cmd -> SD命令句柄 ** ** 输　出: 无 -** -** 全局变量: +** +** 全局变量: ** 调用模块: 无 ** ********************************************************************************************************/ static void mmc_dm365_start_command(struct mmc_dm365_host *host, struct rt_mmcsd_cmd *cmd) { - rt_uint32_t cmd_reg = 0; - rt_uint32_t im_val; - - host->cmd = cmd; - - switch (resp_type(cmd)) - { - case RESP_R1B: - /* There's some spec confusion about when R1B is - * allowed, but if the card doesn't issue a BUSY - * then it's harmless for us to allow it. - */ - cmd_reg |= MMCCMD_BSYEXP; - /* FALLTHROUGH */ - case RESP_R1: /* 48 bits, CRC */ + rt_uint32_t cmd_reg = 0; + rt_uint32_t im_val; + + host->cmd = cmd; + + switch (resp_type(cmd)) + { + case RESP_R1B: + /* There's some spec confusion about when R1B is + * allowed, but if the card doesn't issue a BUSY + * then it's harmless for us to allow it. + */ + cmd_reg |= MMCCMD_BSYEXP; + /* FALLTHROUGH */ + case RESP_R1: /* 48 bits, CRC */ case RESP_R4: - case RESP_R5: + case RESP_R5: case RESP_R6: - case RESP_R7: - cmd_reg |= MMCCMD_RSPFMT_R1456; - break; - case RESP_R2: /* 136 bits, CRC */ - cmd_reg |= MMCCMD_RSPFMT_R2; - break; - case RESP_R3: /* 48 bits, no CRC */ - cmd_reg |= MMCCMD_RSPFMT_R3; - break; - default: - cmd_reg |= MMCCMD_RSPFMT_NONE; - mmc_dbg("unknown resp_type %04x\n", resp_type(cmd)); - break; - } - - /* Set command index */ - cmd_reg |= cmd->cmd_code; - - /* Enable EDMA transfer triggers */ - if (host->do_dma == RT_TRUE) - cmd_reg |= MMCCMD_DMATRIG; - - if (host->data != RT_NULL && host->data_dir == DM365_MMC_DATADIR_READ) - cmd_reg |= MMCCMD_DMATRIG; - - /* Setting whether command involves data transfer or not */ - if (cmd->data) - cmd_reg |= MMCCMD_WDATX; - - /* Setting whether stream or block transfer */ - if (cmd->flags & MMC_DATA_STREAM) - { - mmc_dbg("to do\n"); - cmd_reg |= MMCCMD_STRMTP; - } - - /* Setting whether data read or write */ - if (host->data_dir == DM365_MMC_DATADIR_WRITE) - cmd_reg |= MMCCMD_DTRW; - - if (host->bus_mode == MMCSD_BUSMODE_PUSHPULL) - { - cmd_reg |= MMCCMD_PPLEN; - } - - /* set Command timeout */ - host->mmcsd_regs->MMCTOR = 0x1FFF; - - /* Enable interrupt (calculate here, defer until FIFO is stuffed). */ - im_val = MMCST0_RSPDNE | MMCST0_CRCRS | MMCST0_TOUTRS; - if (host->data_dir == DM365_MMC_DATADIR_WRITE) - { - im_val |= MMCST0_DATDNE | MMCST0_CRCWR; - - if (host->do_dma == RT_FALSE) - im_val |= MMCST0_DXRDY; - } - else if (host->data_dir == DM365_MMC_DATADIR_READ) - { - im_val |= MMCST0_DATDNE | MMCST0_CRCRD | MMCST0_TOUTRD; - - if (host->do_dma == RT_FALSE) - im_val |= MMCST0_DRRDY; - } - - /* - * Before non-DMA WRITE commands the controller needs priming: - * FIFO should be populated with 32 bytes i.e. whatever is the FIFO size - */ - if ((host->do_dma == RT_FALSE) && (host->data_dir == DM365_MMC_DATADIR_WRITE)) - dm365_fifo_data_trans(host, rw_threshold); - - host->mmcsd_regs->MMCARGHL = cmd->arg; - host->mmcsd_regs->MMCCMD = cmd_reg; - host->mmcsd_regs->MMCIM = im_val; + case RESP_R7: + cmd_reg |= MMCCMD_RSPFMT_R1456; + break; + case RESP_R2: /* 136 bits, CRC */ + cmd_reg |= MMCCMD_RSPFMT_R2; + break; + case RESP_R3: /* 48 bits, no CRC */ + cmd_reg |= MMCCMD_RSPFMT_R3; + break; + default: + cmd_reg |= MMCCMD_RSPFMT_NONE; + mmc_dbg("unknown resp_type %04x\n", resp_type(cmd)); + break; + } + + /* Set command index */ + cmd_reg |= cmd->cmd_code; + + /* Enable EDMA transfer triggers */ + if (host->do_dma == RT_TRUE) + cmd_reg |= MMCCMD_DMATRIG; + + if (host->data != RT_NULL && host->data_dir == DM365_MMC_DATADIR_READ) + cmd_reg |= MMCCMD_DMATRIG; + + /* Setting whether command involves data transfer or not */ + if (cmd->data) + cmd_reg |= MMCCMD_WDATX; + + /* Setting whether stream or block transfer */ + if (cmd->flags & MMC_DATA_STREAM) + { + mmc_dbg("to do\n"); + cmd_reg |= MMCCMD_STRMTP; + } + + /* Setting whether data read or write */ + if (host->data_dir == DM365_MMC_DATADIR_WRITE) + cmd_reg |= MMCCMD_DTRW; + + if (host->bus_mode == MMCSD_BUSMODE_PUSHPULL) + { + cmd_reg |= MMCCMD_PPLEN; + } + + /* set Command timeout */ + host->mmcsd_regs->MMCTOR = 0x1FFF; + + /* Enable interrupt (calculate here, defer until FIFO is stuffed). */ + im_val = MMCST0_RSPDNE | MMCST0_CRCRS | MMCST0_TOUTRS; + if (host->data_dir == DM365_MMC_DATADIR_WRITE) + { + im_val |= MMCST0_DATDNE | MMCST0_CRCWR; + + if (host->do_dma == RT_FALSE) + im_val |= MMCST0_DXRDY; + } + else if (host->data_dir == DM365_MMC_DATADIR_READ) + { + im_val |= MMCST0_DATDNE | MMCST0_CRCRD | MMCST0_TOUTRD; + + if (host->do_dma == RT_FALSE) + im_val |= MMCST0_DRRDY; + } + + /* + * Before non-DMA WRITE commands the controller needs priming: + * FIFO should be populated with 32 bytes i.e. whatever is the FIFO size + */ + if ((host->do_dma == RT_FALSE) && (host->data_dir == DM365_MMC_DATADIR_WRITE)) + dm365_fifo_data_trans(host, rw_threshold); + + host->mmcsd_regs->MMCARGHL = cmd->arg; + host->mmcsd_regs->MMCCMD = cmd_reg; + host->mmcsd_regs->MMCIM = im_val; } /******************************************************************************************************* ** 函数名称: dm365_abort_dma() ** 功能描述: 此函数终止DMA传输 -** -** 输　入: host -> DM365 mmc host 句柄 +** +** 输　入: host -> DM365 mmc host 句柄 ** ** 输　出: 无 -** -** 全局变量: +** +** 全局变量: ** 调用模块: 无 ** ********************************************************************************************************/ static void dm365_abort_dma(struct mmc_dm365_host *host) { - int sync_dev; + int sync_dev; - if (host->data_dir == DM365_MMC_DATADIR_READ) - sync_dev = host->rxdma; - else - sync_dev = host->txdma; + if (host->data_dir == DM365_MMC_DATADIR_READ) + sync_dev = host->rxdma; + else + sync_dev = host->txdma; - //EDMA3DisableTransfer(EDMA0CC0_REG_BASE, sync_dev, EDMA3_TRIG_MODE_EVENT); - edma_stop(sync_dev); - edma_clean_channel(sync_dev); + //EDMA3DisableTransfer(EDMA0CC0_REG_BASE, sync_dev, EDMA3_TRIG_MODE_EVENT); + edma_stop(sync_dev); + edma_clean_channel(sync_dev); } /******************************************************************************************************* ** 函数名称: mmc_request_done() ** 功能描述: 此函数用于结束处理一个MMC请求 -** -** 输　入: host -> DM365 mmc host 句柄 -** mrq -> request 句柄 +** +** 输　入: host -> DM365 mmc host 句柄 +** mrq -> request 句柄 ** ** 输　出: 无 -** -** 全局变量: +** +** 全局变量: ** 调用模块: 无 ** ********************************************************************************************************/ void mmc_request_done(struct rt_mmcsd_host *host, struct rt_mmcsd_req *mrq) { - struct rt_mmcsd_cmd *cmd = mrq->cmd; - int err = cmd->err; - - if (err && cmd->retries) - { - mmc_dbg("req failed (CMD%u): %d, retrying...\n", cmd->cmd_code, err); - - cmd->retries--; - cmd->err = 0; - host->ops->request(host, mrq); - } - else - { - mmc_dbg("%s: req done (CMD%u): %d: %08x %08x %08x %08x\n", - "dm365 host", cmd->cmd_code, err, - cmd->resp[0], cmd->resp[1], - cmd->resp[2], cmd->resp[3]); - - if (mrq->data) - { - mmc_dbg("%s: %d bytes transferred: %d\n", - "dm365 host", - mrq->data->bytes_xfered, mrq->data->err); - } - - if (mrq->stop) - { - mmc_dbg("%s: (CMD%u): %d: %08x %08x %08x %08x\n", - "dm365 host", mrq->stop->cmd_code, - mrq->stop->err, - mrq->stop->resp[0], mrq->stop->resp[1], - mrq->stop->resp[2], mrq->stop->resp[3]); - } - - mmcsd_req_complete(host); - } + struct rt_mmcsd_cmd *cmd = mrq->cmd; + int err = cmd->err; + + if (err && cmd->retries) + { + mmc_dbg("req failed (CMD%u): %d, retrying...\n", cmd->cmd_code, err); + + cmd->retries--; + cmd->err = 0; + host->ops->request(host, mrq); + } + else + { + mmc_dbg("%s: req done (CMD%u): %d: %08x %08x %08x %08x\n", + "dm365 host", cmd->cmd_code, err, + cmd->resp[0], cmd->resp[1], + cmd->resp[2], cmd->resp[3]); + + if (mrq->data) + { + mmc_dbg("%s: %d bytes transferred: %d\n", + "dm365 host", + mrq->data->bytes_xfered, mrq->data->err); + } + + if (mrq->stop) + { + mmc_dbg("%s: (CMD%u): %d: %08x %08x %08x %08x\n", + "dm365 host", mrq->stop->cmd_code, + mrq->stop->err, + mrq->stop->resp[0], mrq->stop->resp[1], + mrq->stop->resp[2], mrq->stop->resp[3]); + } + + mmcsd_req_complete(host); + } } /******************************************************************************************************* ** 函数名称: mmc_dm365_xfer_done() ** 功能描述: 数据传送结束调用此函数 -** -** 输　入: host -> DM365 mmc host 句柄 -** data -> data 句柄 +** +** 输　入: host -> DM365 mmc host 句柄 +** data -> data 句柄 ** ** 输　出: 无 -** -** 全局变量: +** +** 全局变量: ** 调用模块: 无 ** ********************************************************************************************************/ static void mmc_dm365_xfer_done(struct mmc_dm365_host *host, struct rt_mmcsd_data *data) { - host->data = RT_NULL; - - if (host->mmc->flags & MMCSD_SUP_SDIO_IRQ) { - /* - * SDIO Interrupt Detection work-around as suggested by - * Davinci Errata (TMS320DM355 Silicon Revision 1.1 Errata - * 2.1.6): Signal SDIO interrupt only if it is enabled by core - */ - if (host->sdio_int && !(host->mmcsd_regs->SDIOST0 & - SDIOST0_DAT1_HI)) { - host->mmcsd_regs->SDIOIST = SDIOIST_IOINT; - sdio_irq_wakeup(host->mmc); - } - } - - if (host->do_dma == RT_TRUE) - { - dm365_abort_dma(host); - - if (data->flags & DATA_DIR_READ) - { - /* read operation */ - if (host->use_dma_buffer == RT_TRUE) - { - /* copy DMA buffer to read buffer */ - memcpy(data->buf, (void*)MMU_NOCACHE_ADDR(host->dma_buffer), data->blks * data->blksize); - } - /*else - { - mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blks * data->blksize); - }*/ - } - - host->do_dma = RT_FALSE; - } - - host->data_dir = DM365_MMC_DATADIR_NONE; - - if (!data->stop || (host->cmd && host->cmd->err)) - { - mmc_request_done(host->mmc, data->mrq); - host->mmcsd_regs->MMCIM = 0; - } - else - mmc_dm365_start_command(host, data->stop); + host->data = RT_NULL; + + if (host->mmc->flags & MMCSD_SUP_SDIO_IRQ) { + /* + * SDIO Interrupt Detection work-around as suggested by + * Davinci Errata (TMS320DM355 Silicon Revision 1.1 Errata + * 2.1.6): Signal SDIO interrupt only if it is enabled by core + */ + if (host->sdio_int && !(host->mmcsd_regs->SDIOST0 & + SDIOST0_DAT1_HI)) { + host->mmcsd_regs->SDIOIST = SDIOIST_IOINT; + sdio_irq_wakeup(host->mmc); + } + } + + if (host->do_dma == RT_TRUE) + { + dm365_abort_dma(host); + + if (data->flags & DATA_DIR_READ) + { + /* read operation */ + if (host->use_dma_buffer == RT_TRUE) + { + /* copy DMA buffer to read buffer */ + memcpy(data->buf, (void*)MMU_NOCACHE_ADDR(host->dma_buffer), data->blks * data->blksize); + } + /*else + { + mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blks * data->blksize); + }*/ + } + + host->do_dma = RT_FALSE; + } + + host->data_dir = DM365_MMC_DATADIR_NONE; + + if (!data->stop || (host->cmd && host->cmd->err)) + { + mmc_request_done(host->mmc, data->mrq); + host->mmcsd_regs->MMCIM = 0; + } + else + mmc_dm365_start_command(host, data->stop); } static void mmc_dm365_dma_cb(unsigned channel, rt_uint16_t ch_status, void *data) { - if (DMA_COMPLETE != ch_status) { - struct mmc_dm365_host *host = data; - - /* Currently means: DMA Event Missed, or "null" transfer - * request was seen. In the future, TC errors (like bad - * addresses) might be presented too. - */ - mmc_dbg("DMA %s error\n", - (host->data->flags & MMC_DATA_WRITE) - ? "write" : "read"); - host->data->err = -RT_EIO; - mmc_dm365_xfer_done(host, host->data); - } + if (DMA_COMPLETE != ch_status) { + struct mmc_dm365_host *host = data; + + /* Currently means: DMA Event Missed, or "null" transfer + * request was seen. In the future, TC errors (like bad + * addresses) might be presented too. + */ + mmc_dbg("DMA %s error\n", + (host->data->flags & MMC_DATA_WRITE) + ? "write" : "read"); + host->data->err = -RT_EIO; + mmc_dm365_xfer_done(host, host->data); + } } /******************************************************************************************************* ** 函数名称: mmc_dm365_dma_setup() ** 功能描述: DMA 设置函数 -** -** 输　入: host -> DM365 mmc host 句柄 -** tx -> 布尔变量，用于判断Tx或者是Rx -** template -> 用于保存EDMA3CCPaRAMEntry机构数据 +** +** 输　入: host -> DM365 mmc host 句柄 +** tx -> 布尔变量，用于判断Tx或者是Rx +** template -> 用于保存EDMA3CCPaRAMEntry机构数据 ** ** 输　出: 无 -** -** 全局变量: +** +** 全局变量: ** 调用模块: 无 ** ********************************************************************************************************/ static void mmc_dm365_dma_setup(struct mmc_dm365_host *host, rt_bool_t tx, struct edmacc_param *template) { - rt_uint32_t sync_dev; - const rt_uint16_t acnt = 4; - const rt_uint16_t bcnt = rw_threshold >> 2; - const rt_uint16_t ccnt = 0; - rt_uint32_t src_port = 0; - rt_uint32_t dst_port = 0; - rt_int16_t src_bidx, dst_bidx; - rt_int16_t src_cidx, dst_cidx; + rt_uint32_t sync_dev; + const rt_uint16_t acnt = 4; + const rt_uint16_t bcnt = rw_threshold >> 2; + const rt_uint16_t ccnt = 0; + rt_uint32_t src_port = 0; + rt_uint32_t dst_port = 0; + rt_int16_t src_bidx, dst_bidx; + rt_int16_t src_cidx, dst_cidx; //edmacc_param paramSet; - /* - * A-B Sync transfer: each DMA request is for one "frame" of - * rw_threshold bytes, broken into "acnt"-size chunks repeated - * "bcnt" times. Each segment needs "ccnt" such frames; since - * we tell the block layer our mmc->max_seg_size limit, we can - * trust (later) that it's within bounds. - * - * The FIFOs are read/written in 4-byte chunks (acnt == 4) and - * EDMA will optimize memory operations to use larger bursts. - */ - if (tx) - { - sync_dev = host->txdma; - - /* src_prt, ccnt, and link to be set up later */ - /*paramSet.srcBIdx = acnt; - paramSet.srcCIdx = acnt * bcnt; - - paramSet.destAddr = (rt_uint32_t)&(host->mmcsd_regs->MMCDXR); - paramSet.destBIdx = 0; - paramSet.destCIdx = 0;*/ - /* src_prt, ccnt, and link to be set up later */ - src_bidx = acnt; - src_cidx = acnt * bcnt; - - dst_port = (rt_uint32_t)&(host->mmcsd_regs->MMCDXR); - dst_bidx = 0; - dst_cidx = 0; - } - else - { - sync_dev = host->rxdma; - - /* dst_prt, ccnt, and link to be set up later */ - /*paramSet.srcAddr = (rt_uint32_t)&(host->mmcsd_regs->MMCDRR); - paramSet.srcBIdx = 0; - paramSet.srcCIdx = 0; - - paramSet.destBIdx = acnt; - paramSet.destCIdx = acnt * bcnt;*/ - src_port = (rt_uint32_t)&(host->mmcsd_regs->MMCDRR); - src_bidx = 0; - src_cidx = 0; - - /* dst_prt, ccnt, and link to be set up later */ - dst_bidx = acnt; - dst_cidx = acnt * bcnt; - } - /* - * We can't use FIFO mode for the FIFOs because MMC FIFO addresses - * are not 256-bit (32-byte) aligned. So we use INCR, and the W8BIT - * parameter is ignored. - */ - edma_set_src(sync_dev, src_port, INCR, W8BIT); - edma_set_dest(sync_dev, dst_port, INCR, W8BIT); - - edma_set_src_index(sync_dev, src_bidx, src_cidx); - edma_set_dest_index(sync_dev, dst_bidx, dst_cidx); - - edma_set_transfer_params(sync_dev, acnt, bcnt, ccnt, 8, ABSYNC); - - edma_read_slot(sync_dev, template); - - /* don't bother with irqs or chaining */ - template->opt |= EDMA_CHAN_SLOT(sync_dev) << 12; - + /* + * A-B Sync transfer: each DMA request is for one "frame" of + * rw_threshold bytes, broken into "acnt"-size chunks repeated + * "bcnt" times. Each segment needs "ccnt" such frames; since + * we tell the block layer our mmc->max_seg_size limit, we can + * trust (later) that it's within bounds. + * + * The FIFOs are read/written in 4-byte chunks (acnt == 4) and + * EDMA will optimize memory operations to use larger bursts. + */ + if (tx) + { + sync_dev = host->txdma; + + /* src_prt, ccnt, and link to be set up later */ + /*paramSet.srcBIdx = acnt; + paramSet.srcCIdx = acnt * bcnt; + + paramSet.destAddr = (rt_uint32_t)&(host->mmcsd_regs->MMCDXR); + paramSet.destBIdx = 0; + paramSet.destCIdx = 0;*/ + /* src_prt, ccnt, and link to be set up later */ + src_bidx = acnt; + src_cidx = acnt * bcnt; + + dst_port = (rt_uint32_t)&(host->mmcsd_regs->MMCDXR); + dst_bidx = 0; + dst_cidx = 0; + } + else + { + sync_dev = host->rxdma; + + /* dst_prt, ccnt, and link to be set up later */ + /*paramSet.srcAddr = (rt_uint32_t)&(host->mmcsd_regs->MMCDRR); + paramSet.srcBIdx = 0; + paramSet.srcCIdx = 0; + + paramSet.destBIdx = acnt; + paramSet.destCIdx = acnt * bcnt;*/ + src_port = (rt_uint32_t)&(host->mmcsd_regs->MMCDRR); + src_bidx = 0; + src_cidx = 0; + + /* dst_prt, ccnt, and link to be set up later */ + dst_bidx = acnt; + dst_cidx = acnt * bcnt; + } + /* + * We can't use FIFO mode for the FIFOs because MMC FIFO addresses + * are not 256-bit (32-byte) aligned. So we use INCR, and the W8BIT + * parameter is ignored. + */ + edma_set_src(sync_dev, src_port, INCR, W8BIT); + edma_set_dest(sync_dev, dst_port, INCR, W8BIT); + + edma_set_src_index(sync_dev, src_bidx, src_cidx); + edma_set_dest_index(sync_dev, dst_bidx, dst_cidx); + + edma_set_transfer_params(sync_dev, acnt, bcnt, ccnt, 8, ABSYNC); + + edma_read_slot(sync_dev, template); + + /* don't bother with irqs or chaining */ + template->opt |= EDMA_CHAN_SLOT(sync_dev) << 12; + #if 0 - paramSet.opt = 0u; - /* Src & Dest are in INCR modes */ - paramSet.opt &= 0xFFFFFFFCu; - /* Program the TCC */ - paramSet.opt |= ((sync_dev << EDMA3CC_OPT_TCC_SHIFT) & EDMA3CC_OPT_TCC); - - paramSet.aCnt = acnt; - paramSet.bCnt = bcnt; - - /* AB Sync Transfer Mode */ - paramSet.opt |= (1 << EDMA3CC_OPT_SYNCDIM_SHIFT); - - /* Now, write the PaRAM Set. */ - EDMA3SetPaRAM(EDMA0CC0_REG_BASE, sync_dev, ¶mSet); - - EDMA3GetPaRAM(EDMA0CC0_REG_BASE, sync_dev, template); + paramSet.opt = 0u; + /* Src & Dest are in INCR modes */ + paramSet.opt &= 0xFFFFFFFCu; + /* Program the TCC */ + paramSet.opt |= ((sync_dev << EDMA3CC_OPT_TCC_SHIFT) & EDMA3CC_OPT_TCC); + + paramSet.aCnt = acnt; + paramSet.bCnt = bcnt; + + /* AB Sync Transfer Mode */ + paramSet.opt |= (1 << EDMA3CC_OPT_SYNCDIM_SHIFT); + + /* Now, write the PaRAM Set. */ + EDMA3SetPaRAM(EDMA0CC0_REG_BASE, sync_dev, ¶mSet); + + EDMA3GetPaRAM(EDMA0CC0_REG_BASE, sync_dev, template); #endif } /******************************************************************************************************* ** 函数名称: mmc_dm365_send_dma_request() ** 功能描述: 发送DMA请求 -** -** 输　入: host -> DM365 mmc host 句柄 -** data -> DMA传送数据结构句柄 +** +** 输　入: host -> DM365 mmc host 句柄 +** data -> DMA传送数据结构句柄 ** ** 输　出: 无 -** -** 全局变量: +** +** 全局变量: ** 调用模块: 无 ** ********************************************************************************************************/ static void mmc_dm365_send_dma_request(struct mmc_dm365_host *host, struct rt_mmcsd_data *data) { - //struct EDMA3CCPaRAMEntry *template; - struct edmacc_param *template; - rt_uint32_t buf_ptr; - rt_uint32_t channel; - rt_uint32_t bytes_left = host->bytes_left; - rt_uint32_t count = host->bytes_left; - const rt_uint32_t shift = ffs(rw_threshold) - 1; - - if (host->use_dma_buffer == RT_TRUE) - buf_ptr = host->dma_buffer;//MMU_NOCACHE_ADDR(host->dma_buffer); - else - buf_ptr = (rt_uint32_t)data->buf; - - if (host->data_dir == DM365_MMC_DATADIR_WRITE) - { - template = &host->tx_template; - channel = host->txdma; - } - else - { - template = &host->rx_template; - channel = host->rxdma; - } - - template->link_bcntrld = 0xffff; - //template->bCntReload = 0x0; - - if (count > bytes_left) - count = bytes_left; - bytes_left -= count; - - if (host->data_dir == DM365_MMC_DATADIR_WRITE) - template->src = buf_ptr; - else - template->dst = buf_ptr; - template->ccnt = count >> shift; - - edma_write_slot(channel, template); - - edma_clear_event(channel); - - /*EDMA3SetPaRAM(EDMA0CC0_REG_BASE, channel, template); - EDMA3ClrEvt(EDMA0CC0_REG_BASE, channel); - EDMA3EnableTransfer(EDMA0CC0_REG_BASE, channel, EDMA3_TRIG_MODE_EVENT);*/ - edma_start(channel); + //struct EDMA3CCPaRAMEntry *template; + struct edmacc_param *template; + rt_uint32_t buf_ptr; + rt_uint32_t channel; + rt_uint32_t bytes_left = host->bytes_left; + rt_uint32_t count = host->bytes_left; + const rt_uint32_t shift = ffs(rw_threshold) - 1; + + if (host->use_dma_buffer == RT_TRUE) + buf_ptr = host->dma_buffer;//MMU_NOCACHE_ADDR(host->dma_buffer); + else + buf_ptr = (rt_uint32_t)data->buf; + + if (host->data_dir == DM365_MMC_DATADIR_WRITE) + { + template = &host->tx_template; + channel = host->txdma; + } + else + { + template = &host->rx_template; + channel = host->rxdma; + } + + template->link_bcntrld = 0xffff; + //template->bCntReload = 0x0; + + if (count > bytes_left) + count = bytes_left; + bytes_left -= count; + + if (host->data_dir == DM365_MMC_DATADIR_WRITE) + template->src = buf_ptr; + else + template->dst = buf_ptr; + template->ccnt = count >> shift; + + edma_write_slot(channel, template); + + edma_clear_event(channel); + + /*EDMA3SetPaRAM(EDMA0CC0_REG_BASE, channel, template); + EDMA3ClrEvt(EDMA0CC0_REG_BASE, channel); + EDMA3EnableTransfer(EDMA0CC0_REG_BASE, channel, EDMA3_TRIG_MODE_EVENT);*/ + edma_start(channel); } /******************************************************************************************************* ** 函数名称: mmc_dm365_start_dma_transfer() ** 功能描述: 开始DMA传输 -** -** 输　入: host -> DM365 mmc host 句柄 -** data -> DMA传送数据结构句柄 +** +** 输　入: host -> DM365 mmc host 句柄 +** data -> DMA传送数据结构句柄 ** ** 输　出: DMA传输字节数 -** -** 全局变量: +** +** 全局变量: ** 调用模块: 无 ** ********************************************************************************************************/ static int mmc_dm365_start_dma_transfer(struct mmc_dm365_host *host, struct rt_mmcsd_data *data) { - /* set initial value */ - host->use_dma_buffer = RT_FALSE; - - if (!(data->flags & DATA_DIR_READ)) - { - if ((rt_uint32_t)data->buf & (RT_ALIGN_SIZE - 1)) - { - /* not align to basic size, use DMA buffer */ - host->use_dma_buffer = RT_TRUE; - memcpy((void*)MMU_NOCACHE_ADDR(host->dma_buffer), data->buf, data->blks * data->blksize); - } - else - { - rt_uint32_t addr; - addr = ((rt_uint32_t)data->buf & ~(CACHE_LINE_SIZE - 1)); - /* write data case, always clean DCache */ - mmu_clean_dcache(addr, (data->blks + 1)* data->blksize); - } - } - else - { - /* whether align to cache line in read operation */ - if (((rt_uint32_t)data->buf) & (CACHE_LINE_SIZE - 1)) - host->use_dma_buffer = RT_TRUE; - else - mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blks * data->blksize); - } - - host->do_dma = RT_TRUE; - mmc_dm365_send_dma_request(host, data); - - return 0; + /* set initial value */ + host->use_dma_buffer = RT_FALSE; + + if (!(data->flags & DATA_DIR_READ)) + { + if ((rt_uint32_t)data->buf & (RT_ALIGN_SIZE - 1)) + { + /* not align to basic size, use DMA buffer */ + host->use_dma_buffer = RT_TRUE; + memcpy((void*)MMU_NOCACHE_ADDR(host->dma_buffer), data->buf, data->blks * data->blksize); + } + else + { + rt_uint32_t addr; + addr = ((rt_uint32_t)data->buf & ~(CACHE_LINE_SIZE - 1)); + /* write data case, always clean DCache */ + mmu_clean_dcache(addr, (data->blks + 1)* data->blksize); + } + } + else + { + /* whether align to cache line in read operation */ + if (((rt_uint32_t)data->buf) & (CACHE_LINE_SIZE - 1)) + host->use_dma_buffer = RT_TRUE; + else + mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blks * data->blksize); + } + + host->do_dma = RT_TRUE; + mmc_dm365_send_dma_request(host, data); + + return 0; } #if 0 /******************************************************************************************************* ** 函数名称: acquire_dma_channels() ** 功能描述: 获取DMA channel -** -** 输　入: host -> DM365 mmc host 句柄 +** +** 输　入: host -> DM365 mmc host 句柄 ** ** 输　出: DMA 通道号 -** -** 全局变量: +** +** 全局变量: ** 调用模块: 无 ** ********************************************************************************************************/ static int acquire_dma_channels(struct mmc_dm365_host *host) { - int r; - - /* Acquire master DMA write channel */ - r = EDMA3RequestChannel(EDMA0CC0_REG_BASE, EDMA3_CHANNEL_TYPE_DMA, host->txdma, host->txdma, EVT_QUEUE_NUM); - if (r < 0) - { - rt_kprintf("alloc %s channel err %d\n", "tx", r); - return r; - } - mmc_dm365_dma_setup(host, RT_TRUE, &host->tx_template); - - /* Acquire master DMA read channel */ - r = EDMA3RequestChannel(EDMA0CC0_REG_BASE, EDMA3_CHANNEL_TYPE_DMA, host->rxdma, host->rxdma, EVT_QUEUE_NUM); - if (r < 0) - { - rt_kprintf("alloc %s channel err %d\n", "rx", r); - goto free_master_write; - } - mmc_dm365_dma_setup(host, RT_FALSE, &host->rx_template); - - return 0; + int r; + + /* Acquire master DMA write channel */ + r = EDMA3RequestChannel(EDMA0CC0_REG_BASE, EDMA3_CHANNEL_TYPE_DMA, host->txdma, host->txdma, EVT_QUEUE_NUM); + if (r < 0) + { + rt_kprintf("alloc %s channel err %d\n", "tx", r); + return r; + } + mmc_dm365_dma_setup(host, RT_TRUE, &host->tx_template); + + /* Acquire master DMA read channel */ + r = EDMA3RequestChannel(EDMA0CC0_REG_BASE, EDMA3_CHANNEL_TYPE_DMA, host->rxdma, host->rxdma, EVT_QUEUE_NUM); + if (r < 0) + { + rt_kprintf("alloc %s channel err %d\n", "rx", r); + goto free_master_write; + } + mmc_dm365_dma_setup(host, RT_FALSE, &host->rx_template); + + return 0; free_master_write: - EDMA3FreeChannel(EDMA0CC0_REG_BASE, EDMA3_CHANNEL_TYPE_DMA, host->txdma, EDMA3_TRIG_MODE_EVENT, host->txdma, EVT_QUEUE_NUM); + EDMA3FreeChannel(EDMA0CC0_REG_BASE, EDMA3_CHANNEL_TYPE_DMA, host->txdma, EDMA3_TRIG_MODE_EVENT, host->txdma, EVT_QUEUE_NUM); - return r; + return r; } #endif static int acquire_dma_channels(struct mmc_dm365_host *host) { - //u32 link_size; - int r, i; - - /* Acquire master DMA write channel */ - r = edma_alloc_channel(host->txdma, mmc_dm365_dma_cb, host, - EVENTQ_DEFAULT); - if (r < 0) { - mmc_dbg("alloc %s channel err %d\n", - "tx", r); - return r; - } - mmc_dm365_dma_setup(host, RT_TRUE, &host->tx_template); - - /* Acquire master DMA read channel */ - r = edma_alloc_channel(host->rxdma, mmc_dm365_dma_cb, host, - EVENTQ_DEFAULT); - if (r < 0) { - mmc_dbg("alloc %s channel err %d\n", - "rx", r); - goto free_master_write; - } - mmc_dm365_dma_setup(host, RT_FALSE, &host->rx_template); - - /* Allocate parameter RAM slots, which will later be bound to a - * channel as needed to handle a scatterlist. - */ + //u32 link_size; + int r, i; + + /* Acquire master DMA write channel */ + r = edma_alloc_channel(host->txdma, mmc_dm365_dma_cb, host, + EVENTQ_DEFAULT); + if (r < 0) { + mmc_dbg("alloc %s channel err %d\n", + "tx", r); + return r; + } + mmc_dm365_dma_setup(host, RT_TRUE, &host->tx_template); + + /* Acquire master DMA read channel */ + r = edma_alloc_channel(host->rxdma, mmc_dm365_dma_cb, host, + EVENTQ_DEFAULT); + if (r < 0) { + mmc_dbg("alloc %s channel err %d\n", + "rx", r); + goto free_master_write; + } + mmc_dm365_dma_setup(host, RT_FALSE, &host->rx_template); + + /* Allocate parameter RAM slots, which will later be bound to a + * channel as needed to handle a scatterlist. + */ #if 0 - link_size = min_t(unsigned, host->nr_sg, ARRAY_SIZE(host->links)); - for (i = 0; i < link_size; i++) { - r = edma_alloc_slot(EDMA_CTLR(host->txdma), EDMA_SLOT_ANY); - if (r < 0) { - mmc_dbg("dma PaRAM alloc --> %d\n", - r); - break; - } - host->links[i] = r; - } - host->n_link = i; + link_size = min_t(unsigned, host->nr_sg, ARRAY_SIZE(host->links)); + for (i = 0; i < link_size; i++) { + r = edma_alloc_slot(EDMA_CTLR(host->txdma), EDMA_SLOT_ANY); + if (r < 0) { + mmc_dbg("dma PaRAM alloc --> %d\n", + r); + break; + } + host->links[i] = r; + } + host->n_link = i; #endif - return 0; + return 0; free_master_write: - edma_free_channel(host->txdma); + edma_free_channel(host->txdma); - return r; + return r; } /******************************************************************************************************* ** 函数名称: mmc_dm365_prepare_data() ** 功能描述: 准备 DMA 数据 -** -** 输　入: host -> DM365 mmc host 句柄 -** req -> SD request 结构句柄 +** +** 输　入: host -> DM365 mmc host 句柄 +** req -> SD request 结构句柄 ** ** 输　出: 无 -** -** 全局变量: +** +** 全局变量: ** 调用模块: 无 ** ********************************************************************************************************/ static void mmc_dm365_prepare_data(struct mmc_dm365_host *host, struct rt_mmcsd_req *req) { - int timeout; - int fifo_lev; - struct rt_mmcsd_data *data = req->data; - - fifo_lev = (rw_threshold == 64) ? MMCFIFOCTL_FIFOLEV : 0; - - host->data = data; - if (data == RT_NULL) - { - host->data_dir = DM365_MMC_DATADIR_NONE; - host->mmcsd_regs->MMCBLEN = 0; - host->mmcsd_regs->MMCNBLK = 0; - return; - } - - mmc_dbg("%s %s, %d blocks of %d bytes\n", - (data->flags & DATA_STREAM) ? "stream" : "block", - (data->flags & DATA_DIR_WRITE) ? "write" : "read", - data->blks, data->blksize); - mmc_dbg(" DTO %d cycles + %d ns\n", - data->timeout_clks, data->timeout_ns); - timeout = data->timeout_clks + (data->timeout_ns / host->ns_in_one_cycle); - if (timeout > 0xffff) - timeout = 0xffff; - - host->mmcsd_regs->MMCTOD = timeout; - host->mmcsd_regs->MMCNBLK = data->blks; - host->mmcsd_regs->MMCBLEN = data->blksize; - - /* Configure the FIFO */ - switch (data->flags & DATA_DIR_WRITE) - { - case DATA_DIR_WRITE: - host->data_dir = DM365_MMC_DATADIR_WRITE; - host->mmcsd_regs->MMCFIFOCTL = fifo_lev | MMCFIFOCTL_FIFODIR_WR | MMCFIFOCTL_FIFORST; - host->mmcsd_regs->MMCFIFOCTL = fifo_lev | MMCFIFOCTL_FIFODIR_WR; - break; - - default: - host->data_dir = DM365_MMC_DATADIR_READ; - host->mmcsd_regs->MMCFIFOCTL = fifo_lev | MMCFIFOCTL_FIFODIR_RD | MMCFIFOCTL_FIFORST; - host->mmcsd_regs->MMCFIFOCTL = fifo_lev | MMCFIFOCTL_FIFODIR_RD; - break; - } - - host->buffer = RT_NULL; - host->bytes_left = data->blks * data->blksize; - - /* For now we try to use DMA whenever we won't need partial FIFO - * reads or writes, either for the whole transfer (as tested here) - * or for any individual scatterlist segment (tested when we call - * start_dma_transfer). - * - * While we *could* change that, unusual block sizes are rarely - * used. The occasional fallback to PIO should't hurt. - */ - if ((host->use_dma == RT_TRUE) && (host->bytes_left & (rw_threshold - 1)) == 0 && - mmc_dm365_start_dma_transfer(host, data) == 0) - { - /* zero this to ensure we take no PIO paths */ - host->bytes_left = 0; - } - else - { - /* Revert to CPU Copy */ - host->buffer = (rt_uint8_t*)req->data->buf; - } + int timeout; + int fifo_lev; + struct rt_mmcsd_data *data = req->data; + + fifo_lev = (rw_threshold == 64) ? MMCFIFOCTL_FIFOLEV : 0; + + host->data = data; + if (data == RT_NULL) + { + host->data_dir = DM365_MMC_DATADIR_NONE; + host->mmcsd_regs->MMCBLEN = 0; + host->mmcsd_regs->MMCNBLK = 0; + return; + } + + mmc_dbg("%s %s, %d blocks of %d bytes\n", + (data->flags & DATA_STREAM) ? "stream" : "block", + (data->flags & DATA_DIR_WRITE) ? "write" : "read", + data->blks, data->blksize); + mmc_dbg(" DTO %d cycles + %d ns\n", + data->timeout_clks, data->timeout_ns); + timeout = data->timeout_clks + (data->timeout_ns / host->ns_in_one_cycle); + if (timeout > 0xffff) + timeout = 0xffff; + + host->mmcsd_regs->MMCTOD = timeout; + host->mmcsd_regs->MMCNBLK = data->blks; + host->mmcsd_regs->MMCBLEN = data->blksize; + + /* Configure the FIFO */ + switch (data->flags & DATA_DIR_WRITE) + { + case DATA_DIR_WRITE: + host->data_dir = DM365_MMC_DATADIR_WRITE; + host->mmcsd_regs->MMCFIFOCTL = fifo_lev | MMCFIFOCTL_FIFODIR_WR | MMCFIFOCTL_FIFORST; + host->mmcsd_regs->MMCFIFOCTL = fifo_lev | MMCFIFOCTL_FIFODIR_WR; + break; + + default: + host->data_dir = DM365_MMC_DATADIR_READ; + host->mmcsd_regs->MMCFIFOCTL = fifo_lev | MMCFIFOCTL_FIFODIR_RD | MMCFIFOCTL_FIFORST; + host->mmcsd_regs->MMCFIFOCTL = fifo_lev | MMCFIFOCTL_FIFODIR_RD; + break; + } + + host->buffer = RT_NULL; + host->bytes_left = data->blks * data->blksize; + + /* For now we try to use DMA whenever we won't need partial FIFO + * reads or writes, either for the whole transfer (as tested here) + * or for any individual scatterlist segment (tested when we call + * start_dma_transfer). + * + * While we *could* change that, unusual block sizes are rarely + * used. The occasional fallback to PIO should't hurt. + */ + if ((host->use_dma == RT_TRUE) && (host->bytes_left & (rw_threshold - 1)) == 0 && + mmc_dm365_start_dma_transfer(host, data) == 0) + { + /* zero this to ensure we take no PIO paths */ + host->bytes_left = 0; + } + else + { + /* Revert to CPU Copy */ + host->buffer = (rt_uint8_t*)req->data->buf; + } } /******************************************************************************************************* ** 函数名称: mmc_dm365_request() ** 功能描述: 此函数实现SD request操作 -** -** 输　入: host -> DM365 mmc host 句柄 -** req -> SD request 结构句柄 +** +** 输　入: host -> DM365 mmc host 句柄 +** req -> SD request 结构句柄 ** ** 输　出: 无 -** -** 全局变量: +** +** 全局变量: ** 调用模块: 无 ** ********************************************************************************************************/ static void mmc_dm365_request(struct rt_mmcsd_host *mmc, struct rt_mmcsd_req *req) { - struct mmc_dm365_host *host = mmc_priv(mmc); - unsigned long timeout = rt_tick_get() + 900; - rt_uint32_t mmcst1 = 0; - - /* Card may still be sending BUSY after a previous operation, - * typically some kind of write. If so, we can't proceed yet. - */ - while (rt_tick_get() < timeout) + struct mmc_dm365_host *host = mmc_priv(mmc); + unsigned long timeout = rt_tick_get() + 900; + rt_uint32_t mmcst1 = 0; + + /* Card may still be sending BUSY after a previous operation, + * typically some kind of write. If so, we can't proceed yet. + */ + while (rt_tick_get() < timeout) { - mmcst1 = host->mmcsd_regs->MMCST1; - if (!(mmcst1 & MMCST1_BUSY)) - break; - } - if (mmcst1 & MMCST1_BUSY) + mmcst1 = host->mmcsd_regs->MMCST1; + if (!(mmcst1 & MMCST1_BUSY)) + break; + } + if (mmcst1 & MMCST1_BUSY) { - mmc_dbg("still BUSY? bad ... \n"); - req->cmd->err = -RT_ETIMEOUT; - mmc_request_done(mmc, req); - return; - } - - host->do_dma = RT_FALSE; - mmc_dm365_prepare_data(host, req); - mmc_dm365_start_command(host, req->cmd); + mmc_dbg("still BUSY? bad ... \n"); + req->cmd->err = -RT_ETIMEOUT; + mmc_request_done(mmc, req); + return; + } + + host->do_dma = RT_FALSE; + mmc_dm365_prepare_data(host, req); + mmc_dm365_start_command(host, req->cmd); } static void mmc_dm365_enable_sdio_irq(struct rt_mmcsd_host *mmc, rt_int32_t enable) { - struct mmc_dm365_host *host = mmc_priv(mmc); - - if (enable) - { - if (!(host->mmcsd_regs->SDIOST0 & SDIOST0_DAT1_HI)) - { - host->mmcsd_regs->SDIOIST = SDIOIST_IOINT; - sdio_irq_wakeup(host->mmc); - } - else - { - host->sdio_int = RT_TRUE; - host->mmcsd_regs->SDIOIEN |= SDIOIEN_IOINTEN; - } - } - else - { - host->sdio_int = RT_FALSE; - host->mmcsd_regs->SDIOIEN &= ~SDIOIEN_IOINTEN; - } + struct mmc_dm365_host *host = mmc_priv(mmc); + + if (enable) + { + if (!(host->mmcsd_regs->SDIOST0 & SDIOST0_DAT1_HI)) + { + host->mmcsd_regs->SDIOIST = SDIOIST_IOINT; + sdio_irq_wakeup(host->mmc); + } + else + { + host->sdio_int = RT_TRUE; + host->mmcsd_regs->SDIOIEN |= SDIOIEN_IOINTEN; + } + } + else + { + host->sdio_int = RT_FALSE; + host->mmcsd_regs->SDIOIEN &= ~SDIOIEN_IOINTEN; + } } -static const struct rt_mmcsd_host_ops mmc_dm365_ops = +static const struct rt_mmcsd_host_ops mmc_dm365_ops = { - mmc_dm365_request, - mmc_dm365_set_ios, + mmc_dm365_request, + mmc_dm365_set_ios, RT_NULL, mmc_dm365_enable_sdio_irq }; @@ -1059,409 +1059,409 @@ static const struct rt_mmcsd_host_ops mmc_dm365_ops = /******************************************************************************************************* ** 函数名称: mmc_dm365_reset_ctrl() ** 功能描述: 此函数用于reset mmc控制器 -** -** 输　入: host -> DM365 mmc host 句柄 -** val -> 判断做reset还是enable +** +** 输　入: host -> DM365 mmc host 句柄 +** val -> 判断做reset还是enable ** ** 输　出: 无 -** -** 全局变量: +** +** 全局变量: ** 调用模块: 无 ** ********************************************************************************************************/ static void mmc_dm365_reset_ctrl(struct mmc_dm365_host *host, int val) { - rt_uint32_t temp; + rt_uint32_t temp; - temp = host->mmcsd_regs->MMCCTL; - - if (val) /* reset */ - temp |= MMCCTL_CMDRST | MMCCTL_DATRST; - else /* enable */ - temp &= ~(MMCCTL_CMDRST | MMCCTL_DATRST); + temp = host->mmcsd_regs->MMCCTL; - host->mmcsd_regs->MMCCTL = temp; + if (val) /* reset */ + temp |= MMCCTL_CMDRST | MMCCTL_DATRST; + else /* enable */ + temp &= ~(MMCCTL_CMDRST | MMCCTL_DATRST); - delay_us(10); + host->mmcsd_regs->MMCCTL = temp; + + delay_us(10); } /******************************************************************************************************* ** 函数名称: init_mmcsd_host() ** 功能描述: 此函数用于初始化DM365 MMCSD控制器 -** -** 输　入: host -> DM365 mmc host 句柄 +** +** 输　入: host -> DM365 mmc host 句柄 ** ** 输　出: 无 -** -** 全局变量: +** +** 全局变量: ** 调用模块: 无 ** ********************************************************************************************************/ static void init_mmcsd_host(struct mmc_dm365_host *host) { - mmc_dm365_reset_ctrl(host, 1); + mmc_dm365_reset_ctrl(host, 1); + + host->mmcsd_regs->MMCCLK = 0; + host->mmcsd_regs->MMCCLK = MMCCLK_CLKEN; - host->mmcsd_regs->MMCCLK = 0; - host->mmcsd_regs->MMCCLK = MMCCLK_CLKEN; + host->mmcsd_regs->MMCTOR = 0x1FFF; + host->mmcsd_regs->MMCTOD = 0xFFFF; - host->mmcsd_regs->MMCTOR = 0x1FFF; - host->mmcsd_regs->MMCTOD = 0xFFFF; - - mmc_dm365_reset_ctrl(host, 0); + mmc_dm365_reset_ctrl(host, 0); } /******************************************************************************************************* ** 函数名称: mmc_dm365_cmd_done() ** 功能描述: 结束SD 命令后调用此函数 -** -** 输　入: host -> DM365 mmc host 句柄 -** cmd -> SD 命令结构句柄 +** +** 输　入: host -> DM365 mmc host 句柄 +** cmd -> SD 命令结构句柄 ** ** 输　出: 无 -** -** 全局变量: +** +** 全局变量: ** 调用模块: 无 ** ********************************************************************************************************/ static void mmc_dm365_cmd_done(struct mmc_dm365_host *host, struct rt_mmcsd_cmd *cmd) { - host->cmd = RT_NULL; - - if (resp_type(cmd) != RESP_NONE) - { - if (resp_type(cmd) == RESP_R2) - { - /* response type 2 */ - cmd->resp[3] = host->mmcsd_regs->MMCRSP01; - cmd->resp[2] = host->mmcsd_regs->MMCRSP23; - cmd->resp[1] = host->mmcsd_regs->MMCRSP45; - cmd->resp[0] = host->mmcsd_regs->MMCRSP67; - } - else - { - /* response types 1, 1b, 3, 4, 5, 6 */ - cmd->resp[0] = host->mmcsd_regs->MMCRSP67; - } - } - - if (host->data == RT_NULL || cmd->err) - { - if (cmd->err == -RT_ETIMEOUT) - cmd->mrq->cmd->retries = 0; - mmc_request_done(host->mmc, cmd->mrq); - host->mmcsd_regs->MMCIM = 0; - } + host->cmd = RT_NULL; + + if (resp_type(cmd) != RESP_NONE) + { + if (resp_type(cmd) == RESP_R2) + { + /* response type 2 */ + cmd->resp[3] = host->mmcsd_regs->MMCRSP01; + cmd->resp[2] = host->mmcsd_regs->MMCRSP23; + cmd->resp[1] = host->mmcsd_regs->MMCRSP45; + cmd->resp[0] = host->mmcsd_regs->MMCRSP67; + } + else + { + /* response types 1, 1b, 3, 4, 5, 6 */ + cmd->resp[0] = host->mmcsd_regs->MMCRSP67; + } + } + + if (host->data == RT_NULL || cmd->err) + { + if (cmd->err == -RT_ETIMEOUT) + cmd->mrq->cmd->retries = 0; + mmc_request_done(host->mmc, cmd->mrq); + host->mmcsd_regs->MMCIM = 0; + } } /******************************************************************************************************* ** 函数名称: dm365_abort_data() ** 功能描述: 此函数用于终止数据传输 -** -** 输　入: host -> DM365 mmc host 句柄 -** data -> data 结构句柄 +** +** 输　入: host -> DM365 mmc host 句柄 +** data -> data 结构句柄 ** ** 输　出: 无 -** -** 全局变量: +** +** 全局变量: ** 调用模块: 无 ** ********************************************************************************************************/ static void dm365_abort_data(struct mmc_dm365_host *host, struct rt_mmcsd_data *data) { - mmc_dm365_reset_ctrl(host, 1); - mmc_dm365_reset_ctrl(host, 0); + mmc_dm365_reset_ctrl(host, 1); + mmc_dm365_reset_ctrl(host, 0); } static void mmc_dm365_sdio_irq(int irq, void *param) { - struct mmc_dm365_host *host = (struct mmc_dm365_host *)param; - rt_uint32_t status; - - status = host->mmcsd_regs->SDIOIST;//readl(host->base + DAVINCI_SDIOIST); - if (status & SDIOIST_IOINT) { - mmc_dbg("SDIO interrupt status %x\n", status); - //writel(status | SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); - host->mmcsd_regs->SDIOIST = status | SDIOIST_IOINT; - sdio_irq_wakeup(host->mmc); - } + struct mmc_dm365_host *host = (struct mmc_dm365_host *)param; + rt_uint32_t status; + + status = host->mmcsd_regs->SDIOIST;//readl(host->base + DAVINCI_SDIOIST); + if (status & SDIOIST_IOINT) { + mmc_dbg("SDIO interrupt status %x\n", status); + //writel(status | SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); + host->mmcsd_regs->SDIOIST = status | SDIOIST_IOINT; + sdio_irq_wakeup(host->mmc); + } } /******************************************************************************************************* ** 函数名称: mmc_dm365_irq() ** 功能描述: MMCSD的中断处理程序 -** -** 输　入: irq ->中断向量号 +** +** 输　入: irq ->中断向量号 ** ** 输　出: 无 -** -** 全局变量: +** +** 全局变量: ** 调用模块: 无 ** ********************************************************************************************************/ static void mmc_dm365_irq(int irq, void *param) { - struct mmc_dm365_host *host = (struct mmc_dm365_host *)param; - rt_uint32_t status, qstatus; - int end_command = 0; - int end_transfer = 0; - struct rt_mmcsd_data *data = host->data; - - if (host->cmd == RT_NULL && host->data == RT_NULL) - { - status = host->mmcsd_regs->MMCST0; - mmc_dbg("Spurious interrupt 0x%04x\n", status); - /* Disable the interrupt from mmcsd */ - host->mmcsd_regs->MMCIM = 0; - return; - } - - status = host->mmcsd_regs->MMCST0; - qstatus = status; - - /* handle FIFO first when using PIO for data. - * bytes_left will decrease to zero as I/O progress and status will - * read zero over iteration because this controller status - * register(MMCST0) reports any status only once and it is cleared - * by read. So, it is not unbouned loop even in the case of - * non-dma. - */ - while (host->bytes_left && (status & (MMCST0_DXRDY | MMCST0_DRRDY))) - { - dm365_fifo_data_trans(host, rw_threshold); - status = host->mmcsd_regs->MMCST0; - if (!status) - break; - qstatus |= status; - } - - if (qstatus & MMCST0_DATDNE) - { - /* All blocks sent/received, and CRC checks passed */ - if (data != RT_NULL) - { - if ((host->do_dma == RT_FALSE) && (host->bytes_left > 0)) - { - /* if datasize < rw_threshold - * no RX ints are generated - */ - rt_kprintf("to do! host->bytes_left=0x%x\n", host->bytes_left); - dm365_fifo_data_trans(host, host->bytes_left); - } - end_transfer = 1; - data->bytes_xfered = data->blks* data->blksize; - } - else - { - mmc_dbg("DATDNE with no host->data\n"); - } - } - - if (qstatus & MMCST0_TOUTRD) - { - /* Read data timeout */ - data->err = -RT_ETIMEOUT; - end_transfer = 1; - - mmc_dbg("read data timeout, status %x\n", qstatus); - rt_kprintf("read data timeout, status %x\n", qstatus); - - dm365_abort_data(host, data); - } - - if (qstatus & (MMCST0_CRCWR | MMCST0_CRCRD)) - { - /* Data CRC error */ - data->err = -RT_ERROR; - end_transfer = 1; - - /* NOTE: this controller uses CRCWR to report both CRC - * errors and timeouts (on writes). MMCDRSP values are - * only weakly documented, but 0x9f was clearly a timeout - * case and the two three-bit patterns in various SD specs - * (101, 010) aren't part of it ... - */ - if (qstatus & MMCST0_CRCWR) - { - rt_uint32_t temp = host->mmcsd_regs->MMCDRSP; - - if (temp == 0x9f) - data->err = -RT_ETIMEOUT; - } - mmc_dbg("data %s %s error\n", (qstatus & MMCST0_CRCWR) ? "write" : "read", (data->err == -110) ? "timeout" : "CRC"); - - rt_kprintf("data %s %s error\n", (qstatus & MMCST0_CRCWR) ? "write" : "read", (data->err == -110) ? "timeout" : "CRC"); - - dm365_abort_data(host, data); - } - - if (qstatus & MMCST0_TOUTRS) - { - /* Command timeout */ - if (host->cmd) - { - mmc_dbg("CMD%d timeout, status %x\n", host->cmd->cmd_code, qstatus); - host->cmd->err = -RT_ETIMEOUT; - if (data) - { - end_transfer = 1; - dm365_abort_data(host, data); - } - else - end_command = 1; - } - } - - if (qstatus & MMCST0_CRCRS) - { - /* Command CRC error */ - mmc_dbg("Command CRC error\n"); - if (host->cmd) - { - host->cmd->err = -RT_ERROR; - end_command = 1; - } - } - - if (qstatus & MMCST0_RSPDNE) - { - /* End of command phase */ - end_command = (int) host->cmd; - } - - if (end_command) - mmc_dm365_cmd_done(host, host->cmd); - if (end_transfer) - mmc_dm365_xfer_done(host, data); - - return; + struct mmc_dm365_host *host = (struct mmc_dm365_host *)param; + rt_uint32_t status, qstatus; + int end_command = 0; + int end_transfer = 0; + struct rt_mmcsd_data *data = host->data; + + if (host->cmd == RT_NULL && host->data == RT_NULL) + { + status = host->mmcsd_regs->MMCST0; + mmc_dbg("Spurious interrupt 0x%04x\n", status); + /* Disable the interrupt from mmcsd */ + host->mmcsd_regs->MMCIM = 0; + return; + } + + status = host->mmcsd_regs->MMCST0; + qstatus = status; + + /* handle FIFO first when using PIO for data. + * bytes_left will decrease to zero as I/O progress and status will + * read zero over iteration because this controller status + * register(MMCST0) reports any status only once and it is cleared + * by read. So, it is not unbouned loop even in the case of + * non-dma. + */ + while (host->bytes_left && (status & (MMCST0_DXRDY | MMCST0_DRRDY))) + { + dm365_fifo_data_trans(host, rw_threshold); + status = host->mmcsd_regs->MMCST0; + if (!status) + break; + qstatus |= status; + } + + if (qstatus & MMCST0_DATDNE) + { + /* All blocks sent/received, and CRC checks passed */ + if (data != RT_NULL) + { + if ((host->do_dma == RT_FALSE) && (host->bytes_left > 0)) + { + /* if datasize < rw_threshold + * no RX ints are generated + */ + rt_kprintf("to do! host->bytes_left=0x%x\n", host->bytes_left); + dm365_fifo_data_trans(host, host->bytes_left); + } + end_transfer = 1; + data->bytes_xfered = data->blks* data->blksize; + } + else + { + mmc_dbg("DATDNE with no host->data\n"); + } + } + + if (qstatus & MMCST0_TOUTRD) + { + /* Read data timeout */ + data->err = -RT_ETIMEOUT; + end_transfer = 1; + + mmc_dbg("read data timeout, status %x\n", qstatus); + rt_kprintf("read data timeout, status %x\n", qstatus); + + dm365_abort_data(host, data); + } + + if (qstatus & (MMCST0_CRCWR | MMCST0_CRCRD)) + { + /* Data CRC error */ + data->err = -RT_ERROR; + end_transfer = 1; + + /* NOTE: this controller uses CRCWR to report both CRC + * errors and timeouts (on writes). MMCDRSP values are + * only weakly documented, but 0x9f was clearly a timeout + * case and the two three-bit patterns in various SD specs + * (101, 010) aren't part of it ... + */ + if (qstatus & MMCST0_CRCWR) + { + rt_uint32_t temp = host->mmcsd_regs->MMCDRSP; + + if (temp == 0x9f) + data->err = -RT_ETIMEOUT; + } + mmc_dbg("data %s %s error\n", (qstatus & MMCST0_CRCWR) ? "write" : "read", (data->err == -110) ? "timeout" : "CRC"); + + rt_kprintf("data %s %s error\n", (qstatus & MMCST0_CRCWR) ? "write" : "read", (data->err == -110) ? "timeout" : "CRC"); + + dm365_abort_data(host, data); + } + + if (qstatus & MMCST0_TOUTRS) + { + /* Command timeout */ + if (host->cmd) + { + mmc_dbg("CMD%d timeout, status %x\n", host->cmd->cmd_code, qstatus); + host->cmd->err = -RT_ETIMEOUT; + if (data) + { + end_transfer = 1; + dm365_abort_data(host, data); + } + else + end_command = 1; + } + } + + if (qstatus & MMCST0_CRCRS) + { + /* Command CRC error */ + mmc_dbg("Command CRC error\n"); + if (host->cmd) + { + host->cmd->err = -RT_ERROR; + end_command = 1; + } + } + + if (qstatus & MMCST0_RSPDNE) + { + /* End of command phase */ + end_command = (int) host->cmd; + } + + if (end_command) + mmc_dm365_cmd_done(host, host->cmd); + if (end_transfer) + mmc_dm365_xfer_done(host, data); + + return; } #if 0 /******************************************************************************************************* ** 函数名称: rt_hw_edma_init() ** 功能描述: 此函数用于初始化EDMA3 -** +** ** 输　入: 无 ** ** 输　出: 无 -** -** 全局变量: +** +** 全局变量: ** 调用模块: 无 ** ********************************************************************************************************/ static void rt_hw_edma_init(void) { - psc_transition(PSC0, DOMAIN0, LPSC_TPCC, PSC_ENABLE); - psc_transition(PSC0, DOMAIN0, LPSC_TPTC0, PSC_ENABLE); + psc_transition(PSC0, DOMAIN0, LPSC_TPCC, PSC_ENABLE); + psc_transition(PSC0, DOMAIN0, LPSC_TPTC0, PSC_ENABLE); - /* Initialization of EDMA3 */ + /* Initialization of EDMA3 */ edma3_init(EDMA0CC0_REG_BASE, EVT_QUEUE_NUM); - + /* Register EDMA3 Interrupts */ -// ConfigureAINTCIntEDMA3(); +// ConfigureAINTCIntEDMA3(); } #endif /******************************************************************************************************* ** 函数名称: rt_hw_mmcsd_init() ** 功能描述: 此函数用于初始化MMC驱动模块 -** +** ** 输　入: 无 ** ** 输　出: 如果初始化成功，返回0；如果初始化失败，返回-RT_ENOMEM -** -** 全局变量: +** +** 全局变量: ** 调用模块: 无 ** ********************************************************************************************************/ int rt_hw_mmcsd_init(void) { - struct clk *clk; - struct mmc_dm365_host *dm365_host; - struct rt_mmcsd_host *mmc = RT_NULL; - - mmc = mmcsd_alloc_host(); - if (!mmc) - { - mmc_dbg("alloc mmc failed\n"); - return -RT_ERROR; - } - - dm365_host = rt_malloc(sizeof(struct mmc_dm365_host)); - if (!dm365_host) - { - mmc_dbg("alloc mci failed\n"); - goto err; - } - - rt_memset(dm365_host, 0, sizeof(struct mmc_dm365_host)); + struct clk *clk; + struct mmc_dm365_host *dm365_host; + struct rt_mmcsd_host *mmc = RT_NULL; + + mmc = mmcsd_alloc_host(); + if (!mmc) + { + mmc_dbg("alloc mmc failed\n"); + return -RT_ERROR; + } + + dm365_host = rt_malloc(sizeof(struct mmc_dm365_host)); + if (!dm365_host) + { + mmc_dbg("alloc mci failed\n"); + goto err; + } + + rt_memset(dm365_host, 0, sizeof(struct mmc_dm365_host)); #ifdef RT_USING_MMCSD0 - //psc_transition(PSC0, DOMAIN0, LPSC_MMCSD0, PSC_ENABLE); - //pinmux_config(PINMUX_MMCSD0_REG, PINMUX_MMCSD0_MASK, PINMUX_MMCSD0_VAL); - psc_change_state(DAVINCI_DM365_LPSC_MMC_SD0, PSC_ENABLE); - dm365_host->mmcsd_regs = (mmcsd_regs_t *)DM365_MMC_SD0_BASE; + //psc_transition(PSC0, DOMAIN0, LPSC_MMCSD0, PSC_ENABLE); + //pinmux_config(PINMUX_MMCSD0_REG, PINMUX_MMCSD0_MASK, PINMUX_MMCSD0_VAL); + psc_change_state(DAVINCI_DM365_LPSC_MMC_SD0, PSC_ENABLE); + dm365_host->mmcsd_regs = (mmcsd_regs_t *)DM365_MMC_SD0_BASE; #else #ifdef RT_USING_MMCSD1 - psc_transition(PSC1, DOMAIN0, LPSC_MMCSD1, PSC_ENABLE); - pinmux_config(PINMUX_MMCSD1_REG, PINMUX_MMCSD1_MASK, PINMUX_MMCSD1_VAL); - dm365_host->mmcsd_regs = MMCSD1; + psc_transition(PSC1, DOMAIN0, LPSC_MMCSD1, PSC_ENABLE); + pinmux_config(PINMUX_MMCSD1_REG, PINMUX_MMCSD1_MASK, PINMUX_MMCSD1_VAL); + dm365_host->mmcsd_regs = MMCSD1; #endif #endif - //rt_hw_edma_init(); - - clk = clk_get("MMCSDCLK0"); - dm365_host->mmc_input_clk = clk_get_rate(clk); - dm365_host->rxdma = DM365_DMA_MMC0RXEVT; - dm365_host->txdma = DM365_DMA_MMC0TXEVT; - dm365_host->use_dma = use_dma; - if ((dm365_host->use_dma == RT_TRUE)&& acquire_dma_channels(dm365_host) != 0) - { - dm365_host->use_dma = RT_FALSE; - } - else - { - dm365_host->dma_buffer = (rt_uint8_t*)rt_malloc_align(64*1024, 32); - if (dm365_host->dma_buffer == RT_NULL) - dm365_host->use_dma = RT_FALSE; - } - - mmc->ops = &mmc_dm365_ops; - mmc->freq_min = 312500; - mmc->freq_max = 25000000; - mmc->valid_ocr = VDD_32_33 | VDD_33_34; - mmc->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE; - mmc->flags |= MMCSD_SUP_SDIO_IRQ; - - dm365_host->mmc = mmc; - mmc->private_data = dm365_host; - - /* install interrupt */ + //rt_hw_edma_init(); + + clk = clk_get("MMCSDCLK0"); + dm365_host->mmc_input_clk = clk_get_rate(clk); + dm365_host->rxdma = DM365_DMA_MMC0RXEVT; + dm365_host->txdma = DM365_DMA_MMC0TXEVT; + dm365_host->use_dma = use_dma; + if ((dm365_host->use_dma == RT_TRUE)&& acquire_dma_channels(dm365_host) != 0) + { + dm365_host->use_dma = RT_FALSE; + } + else + { + dm365_host->dma_buffer = (rt_uint8_t*)rt_malloc_align(64*1024, 32); + if (dm365_host->dma_buffer == RT_NULL) + dm365_host->use_dma = RT_FALSE; + } + + mmc->ops = &mmc_dm365_ops; + mmc->freq_min = 312500; + mmc->freq_max = 25000000; + mmc->valid_ocr = VDD_32_33 | VDD_33_34; + mmc->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE; + mmc->flags |= MMCSD_SUP_SDIO_IRQ; + + dm365_host->mmc = mmc; + mmc->private_data = dm365_host; + + /* install interrupt */ #ifdef RT_USING_MMCSD0 - rt_hw_interrupt_install(IRQ_DM3XX_MMCINT0, mmc_dm365_irq, - (void *)dm365_host, "MMC0"); - rt_hw_interrupt_umask(IRQ_DM3XX_MMCINT0); - rt_hw_interrupt_install(IRQ_DM3XX_SDIOINT0, mmc_dm365_sdio_irq, - (void *)dm365_host, "SDIO0"); - rt_hw_interrupt_umask(IRQ_DM3XX_SDIOINT0); + rt_hw_interrupt_install(IRQ_DM3XX_MMCINT0, mmc_dm365_irq, + (void *)dm365_host, "MMC0"); + rt_hw_interrupt_umask(IRQ_DM3XX_MMCINT0); + rt_hw_interrupt_install(IRQ_DM3XX_SDIOINT0, mmc_dm365_sdio_irq, + (void *)dm365_host, "SDIO0"); + rt_hw_interrupt_umask(IRQ_DM3XX_SDIOINT0); #endif #ifdef RT_USING_MMCSD1 - rt_hw_interrupt_install(MMCSD_INT1, mmc_dm365_irq, - (void *)dm365_host, "MMC1"); - rt_hw_interrupt_umask(MMCSD_INT1); + rt_hw_interrupt_install(MMCSD_INT1, mmc_dm365_irq, + (void *)dm365_host, "MMC1"); + rt_hw_interrupt_umask(MMCSD_INT1); #endif - init_mmcsd_host(dm365_host); + init_mmcsd_host(dm365_host); - mmcsd_change(mmc); + mmcsd_change(mmc); - return 0; + return 0; err: - mmcsd_free_host(mmc); + mmcsd_free_host(mmc); - return -RT_ENOMEM; + return -RT_ENOMEM; } INIT_DEVICE_EXPORT(rt_hw_mmcsd_init); diff --git a/bsp/dm365/drivers/mmcsd.h b/bsp/dm365/drivers/mmcsd.h index 70a57b87f3..812b44a72e 100644 --- a/bsp/dm365/drivers/mmcsd.h +++ b/bsp/dm365/drivers/mmcsd.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ #ifndef __DAVINCI_MMC_H__ @@ -30,18 +30,18 @@ #define MMCCLK_CLKRT_MASK (0xFF << 0) /* IRQ bit definitions, for DAVINCI_MMCST0 and DAVINCI_MMCIM */ -#define MMCST0_DATDNE (1 << 0) /* data done */ -#define MMCST0_BSYDNE (1 << 1) /* busy done */ -#define MMCST0_RSPDNE (1 << 2) /* command done */ -#define MMCST0_TOUTRD (1 << 3) /* data read timeout */ -#define MMCST0_TOUTRS (1 << 4) /* command response timeout */ -#define MMCST0_CRCWR (1 << 5) /* data write CRC error */ -#define MMCST0_CRCRD (1 << 6) /* data read CRC error */ -#define MMCST0_CRCRS (1 << 7) /* command response CRC error */ -#define MMCST0_DXRDY (1 << 9) /* data transmit ready (fifo empty) */ -#define MMCST0_DRRDY (1 << 10) /* data receive ready (data in fifo)*/ -#define MMCST0_DATED (1 << 11) /* DAT3 edge detect */ -#define MMCST0_TRNDNE (1 << 12) /* transfer done */ +#define MMCST0_DATDNE (1 << 0) /* data done */ +#define MMCST0_BSYDNE (1 << 1) /* busy done */ +#define MMCST0_RSPDNE (1 << 2) /* command done */ +#define MMCST0_TOUTRD (1 << 3) /* data read timeout */ +#define MMCST0_TOUTRS (1 << 4) /* command response timeout */ +#define MMCST0_CRCWR (1 << 5) /* data write CRC error */ +#define MMCST0_CRCRD (1 << 6) /* data read CRC error */ +#define MMCST0_CRCRS (1 << 7) /* command response CRC error */ +#define MMCST0_DXRDY (1 << 9) /* data transmit ready (fifo empty) */ +#define MMCST0_DRRDY (1 << 10) /* data receive ready (data in fifo)*/ +#define MMCST0_DATED (1 << 11) /* DAT3 edge detect */ +#define MMCST0_TRNDNE (1 << 12) /* transfer done */ /* DAVINCI_MMCST1 definitions */ #define MMCST1_BUSY (1 << 0) @@ -86,44 +86,44 @@ #define SDIOIST_RWS (1 << 1) /* MMCSD Init clock in Hz in opendrain mode */ -#define MMCSD_INIT_CLOCK 200000 +#define MMCSD_INIT_CLOCK 200000 -#define MAX_CCNT ((1 << 16) - 1) +#define MAX_CCNT ((1 << 16) - 1) -#define MAX_NR_SG 16 +#define MAX_NR_SG 16 -#define MMC_DATA_WRITE (1 << 8) -#define MMC_DATA_READ (1 << 9) -#define MMC_DATA_STREAM (1 << 10) +#define MMC_DATA_WRITE (1 << 8) +#define MMC_DATA_READ (1 << 9) +#define MMC_DATA_STREAM (1 << 10) typedef struct { - volatile rt_uint32_t MMCCTL; - volatile rt_uint32_t MMCCLK; - volatile rt_uint32_t MMCST0; - volatile rt_uint32_t MMCST1; - volatile rt_uint32_t MMCIM; - volatile rt_uint32_t MMCTOR; - volatile rt_uint32_t MMCTOD; - volatile rt_uint32_t MMCBLEN; - volatile rt_uint32_t MMCNBLK; - volatile rt_uint32_t MMCNBLC; - volatile rt_uint32_t MMCDRR; - volatile rt_uint32_t MMCDXR; - volatile rt_uint32_t MMCCMD; - volatile rt_uint32_t MMCARGHL; - volatile rt_uint32_t MMCRSP01; - volatile rt_uint32_t MMCRSP23; - volatile rt_uint32_t MMCRSP45; - volatile rt_uint32_t MMCRSP67; - volatile rt_uint32_t MMCDRSP; - volatile rt_uint32_t reserved0; - volatile rt_uint32_t MMCCIDX; - volatile rt_uint32_t reserved1[4]; - volatile rt_uint32_t SDIOCTL; - volatile rt_uint32_t SDIOST0; - volatile rt_uint32_t SDIOIEN; - volatile rt_uint32_t SDIOIST; - volatile rt_uint32_t MMCFIFOCTL; + volatile rt_uint32_t MMCCTL; + volatile rt_uint32_t MMCCLK; + volatile rt_uint32_t MMCST0; + volatile rt_uint32_t MMCST1; + volatile rt_uint32_t MMCIM; + volatile rt_uint32_t MMCTOR; + volatile rt_uint32_t MMCTOD; + volatile rt_uint32_t MMCBLEN; + volatile rt_uint32_t MMCNBLK; + volatile rt_uint32_t MMCNBLC; + volatile rt_uint32_t MMCDRR; + volatile rt_uint32_t MMCDXR; + volatile rt_uint32_t MMCCMD; + volatile rt_uint32_t MMCARGHL; + volatile rt_uint32_t MMCRSP01; + volatile rt_uint32_t MMCRSP23; + volatile rt_uint32_t MMCRSP45; + volatile rt_uint32_t MMCRSP67; + volatile rt_uint32_t MMCDRSP; + volatile rt_uint32_t reserved0; + volatile rt_uint32_t MMCCIDX; + volatile rt_uint32_t reserved1[4]; + volatile rt_uint32_t SDIOCTL; + volatile rt_uint32_t SDIOST0; + volatile rt_uint32_t SDIOIEN; + volatile rt_uint32_t SDIOIST; + volatile rt_uint32_t MMCFIFOCTL; }mmcsd_regs_t; extern int rt_hw_mmcsd_init(void); diff --git a/bsp/dm365/drivers/spi-davinci.c b/bsp/dm365/drivers/spi-davinci.c index 18425cdf72..35de558e14 100644 --- a/bsp/dm365/drivers/spi-davinci.c +++ b/bsp/dm365/drivers/spi-davinci.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ #include @@ -20,13 +20,13 @@ #define barrier() __asm__ __volatile__("": : :"memory") #define cpu_relax() barrier() -#define SPI_DEBUG 0 +#define SPI_DEBUG 0 #if SPI_DEBUG #define spi_dbg(dev, fmt, ...) \ - do { \ - rt_kprintf("%s:", dev->parent.name); \ - rt_kprintf(fmt, ##__VA_ARGS__); \ - } while(0) + do { \ + rt_kprintf("%s:", dev->parent.name); \ + rt_kprintf(fmt, ##__VA_ARGS__); \ + } while(0) #else #define spi_dbg(dev, fmt, ...) #endif @@ -34,50 +34,50 @@ #define SZ_64K 0x10000 #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) -#define SPI_NO_RESOURCE ((resource_size_t)-1) +#define SPI_NO_RESOURCE ((resource_size_t)-1) -#define SPI_MAX_CHIPSELECT 2 +#define SPI_MAX_CHIPSELECT 2 -#define CS_DEFAULT 0xFF +#define CS_DEFAULT 0xFF #define __iomem -#define BIT(nr) (1UL << (nr)) - -#define SPIFMT_PHASE_MASK BIT(16) -#define SPIFMT_POLARITY_MASK BIT(17) -#define SPIFMT_DISTIMER_MASK BIT(18) -#define SPIFMT_SHIFTDIR_MASK BIT(20) -#define SPIFMT_WAITENA_MASK BIT(21) -#define SPIFMT_PARITYENA_MASK BIT(22) -#define SPIFMT_ODD_PARITY_MASK BIT(23) -#define SPIFMT_WDELAY_MASK 0x3f000000u -#define SPIFMT_WDELAY_SHIFT 24 -#define SPIFMT_PRESCALE_SHIFT 8 +#define BIT(nr) (1UL << (nr)) + +#define SPIFMT_PHASE_MASK BIT(16) +#define SPIFMT_POLARITY_MASK BIT(17) +#define SPIFMT_DISTIMER_MASK BIT(18) +#define SPIFMT_SHIFTDIR_MASK BIT(20) +#define SPIFMT_WAITENA_MASK BIT(21) +#define SPIFMT_PARITYENA_MASK BIT(22) +#define SPIFMT_ODD_PARITY_MASK BIT(23) +#define SPIFMT_WDELAY_MASK 0x3f000000u +#define SPIFMT_WDELAY_SHIFT 24 +#define SPIFMT_PRESCALE_SHIFT 8 /* SPIPC0 */ -#define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ -#define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */ -#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ -#define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */ +#define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ +#define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */ +#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ +#define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */ -#define SPIINT_MASKALL 0x0101035F -#define SPIINT_MASKINT 0x0000015F -#define SPI_INTLVL_1 0x000001FF -#define SPI_INTLVL_0 0x00000000 +#define SPIINT_MASKALL 0x0101035F +#define SPIINT_MASKINT 0x0000015F +#define SPI_INTLVL_1 0x000001FF +#define SPI_INTLVL_0 0x00000000 /* SPIDAT1 (upper 16 bit defines) */ -#define SPIDAT1_CSHOLD_MASK BIT(12) +#define SPIDAT1_CSHOLD_MASK BIT(12) /* SPIGCR1 */ -#define SPIGCR1_CLKMOD_MASK BIT(1) +#define SPIGCR1_CLKMOD_MASK BIT(1) #define SPIGCR1_MASTER_MASK BIT(0) -#define SPIGCR1_POWERDOWN_MASK BIT(8) -#define SPIGCR1_LOOPBACK_MASK BIT(16) -#define SPIGCR1_SPIENA_MASK BIT(24) +#define SPIGCR1_POWERDOWN_MASK BIT(8) +#define SPIGCR1_LOOPBACK_MASK BIT(16) +#define SPIGCR1_SPIENA_MASK BIT(24) /* SPIBUF */ -#define SPIBUF_TXFULL_MASK BIT(29) -#define SPIBUF_RXEMPTY_MASK BIT(31) +#define SPIBUF_TXFULL_MASK BIT(29) +#define SPIBUF_RXEMPTY_MASK BIT(31) /* SPIDELAY */ #define SPIDELAY_C2TDELAY_SHIFT 24 @@ -90,67 +90,67 @@ #define SPIDELAY_C2EDELAY_MASK 0xFF /* Error Masks */ -#define SPIFLG_DLEN_ERR_MASK BIT(0) -#define SPIFLG_TIMEOUT_MASK BIT(1) -#define SPIFLG_PARERR_MASK BIT(2) -#define SPIFLG_DESYNC_MASK BIT(3) -#define SPIFLG_BITERR_MASK BIT(4) -#define SPIFLG_OVRRUN_MASK BIT(6) -#define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) -#define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \ - | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ - | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ - | SPIFLG_OVRRUN_MASK) - -#define SPIINT_DMA_REQ_EN BIT(16) +#define SPIFLG_DLEN_ERR_MASK BIT(0) +#define SPIFLG_TIMEOUT_MASK BIT(1) +#define SPIFLG_PARERR_MASK BIT(2) +#define SPIFLG_DESYNC_MASK BIT(3) +#define SPIFLG_BITERR_MASK BIT(4) +#define SPIFLG_OVRRUN_MASK BIT(6) +#define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) +#define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \ + | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ + | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ + | SPIFLG_OVRRUN_MASK) + +#define SPIINT_DMA_REQ_EN BIT(16) /* SPI Controller registers */ -#define SPIGCR0 0x00 -#define SPIGCR1 0x04 -#define SPIINT 0x08 -#define SPILVL 0x0c -#define SPIFLG 0x10 -#define SPIPC0 0x14 -#define SPIDAT1 0x3c -#define SPIBUF 0x40 -#define SPIDELAY 0x48 -#define SPIDEF 0x4c -#define SPIFMT0 0x50 +#define SPIGCR0 0x00 +#define SPIGCR1 0x04 +#define SPIINT 0x08 +#define SPILVL 0x0c +#define SPIFLG 0x10 +#define SPIPC0 0x14 +#define SPIDAT1 0x3c +#define SPIBUF 0x40 +#define SPIDELAY 0x48 +#define SPIDEF 0x4c +#define SPIFMT0 0x50 /* We have 2 DMA channels per CS, one for RX and one for TX */ struct davinci_spi_dma { - int tx_channel; - int rx_channel; - int dummy_param_slot; - enum dma_event_q eventq; + int tx_channel; + int rx_channel; + int dummy_param_slot; + enum dma_event_q eventq; }; /* SPI Controller driver's private data. */ struct davinci_spi { - struct rt_spi_bus parent; - struct clk *clk; + struct rt_spi_bus parent; + struct clk *clk; - u8 version; - void __iomem *base; - u32 irq; - struct rt_completion done; + u8 version; + void __iomem *base; + u32 irq; + struct rt_completion done; - const void *tx; - void *rx; + const void *tx; + void *rx; #define SMP_CACHE_BYTES 32 -#define SPI_TMP_BUFSZ (SMP_CACHE_BYTES + 1) - u8 rx_tmp_buf[SPI_TMP_BUFSZ]; - int rcount; - int wcount; - struct davinci_spi_dma dma; - - void (*get_rx)(u32 rx_data, struct davinci_spi *); - u32 (*get_tx)(struct davinci_spi *); - - u8 bytes_per_word[SPI_MAX_CHIPSELECT]; - u8 chip_sel[SPI_MAX_CHIPSELECT]; - struct davinci_spi_config *controller_data; - int cshold_bug; +#define SPI_TMP_BUFSZ (SMP_CACHE_BYTES + 1) + u8 rx_tmp_buf[SPI_TMP_BUFSZ]; + int rcount; + int wcount; + struct davinci_spi_dma dma; + + void (*get_rx)(u32 rx_data, struct davinci_spi *); + u32 (*get_tx)(struct davinci_spi *); + + u8 bytes_per_word[SPI_MAX_CHIPSELECT]; + u8 chip_sel[SPI_MAX_CHIPSELECT]; + struct davinci_spi_config *controller_data; + int cshold_bug; }; static struct davinci_spi_config davinci_spi_default_cfg; @@ -160,58 +160,58 @@ extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi) { - if (dspi->rx) { - u8 *rx = dspi->rx; - *rx++ = (u8)data; - dspi->rx = rx; - } + if (dspi->rx) { + u8 *rx = dspi->rx; + *rx++ = (u8)data; + dspi->rx = rx; + } } static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi) { - if (dspi->rx) { - u16 *rx = dspi->rx; - *rx++ = (u16)data; - dspi->rx = rx; - } + if (dspi->rx) { + u16 *rx = dspi->rx; + *rx++ = (u16)data; + dspi->rx = rx; + } } static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi) { - u32 data = 0; - if (dspi->tx) { - const u8 *tx = dspi->tx; - data = *tx++; - dspi->tx = tx; - } - return data; + u32 data = 0; + if (dspi->tx) { + const u8 *tx = dspi->tx; + data = *tx++; + dspi->tx = tx; + } + return data; } static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi) { - u32 data = 0; - if (dspi->tx) { - const u16 *tx = dspi->tx; - data = *tx++; - dspi->tx = tx; - } - return data; + u32 data = 0; + if (dspi->tx) { + const u16 *tx = dspi->tx; + data = *tx++; + dspi->tx = tx; + } + return data; } static inline void set_io_bits(void __iomem *addr, u32 bits) { - u32 v = readl(addr); + u32 v = readl(addr); - v |= bits; - writel(v, addr); + v |= bits; + writel(v, addr); } static inline void clear_io_bits(void __iomem *addr, u32 bits) { - u32 v = readl(addr); + u32 v = readl(addr); - v &= ~bits; - writel(v, addr); + v &= ~bits; + writel(v, addr); } /* @@ -219,39 +219,39 @@ static inline void clear_io_bits(void __iomem *addr, u32 bits) */ static void davinci_spi_chipselect(struct rt_spi_device *spi, int value) { - struct davinci_spi *dspi; - u8 chip_sel = (u8)spi->parent.user_data; - u16 spidat1 = CS_DEFAULT; - bool gpio_chipsel = RT_FALSE; - - dspi = spi->bus->parent.user_data; - - if (chip_sel < SPI_MAX_CHIPSELECT && - dspi->chip_sel[chip_sel] != SPI_INTERN_CS) - gpio_chipsel = RT_TRUE; - - /* - * Board specific chip select logic decides the polarity and cs - * line for the controller - */ - if (gpio_chipsel) { - if (value == 0) - gpio_set_value(dspi->chip_sel[chip_sel], 0); - else - gpio_set_value(dspi->chip_sel[chip_sel], 1); - } else { - spidat1 = readw(dspi->base + SPIDAT1 + 2); - if (value == 0) { - spidat1 |= SPIDAT1_CSHOLD_MASK; - spidat1 &= ~(0x1 << chip_sel); - } else { - spidat1 &= ~SPIDAT1_CSHOLD_MASK; - spidat1 |= 0x03; - } - rt_kprintf("0x%04x\n", spidat1); - - writew(spidat1, dspi->base + SPIDAT1 + 2); - } + struct davinci_spi *dspi; + u8 chip_sel = (u8)spi->parent.user_data; + u16 spidat1 = CS_DEFAULT; + bool gpio_chipsel = RT_FALSE; + + dspi = spi->bus->parent.user_data; + + if (chip_sel < SPI_MAX_CHIPSELECT && + dspi->chip_sel[chip_sel] != SPI_INTERN_CS) + gpio_chipsel = RT_TRUE; + + /* + * Board specific chip select logic decides the polarity and cs + * line for the controller + */ + if (gpio_chipsel) { + if (value == 0) + gpio_set_value(dspi->chip_sel[chip_sel], 0); + else + gpio_set_value(dspi->chip_sel[chip_sel], 1); + } else { + spidat1 = readw(dspi->base + SPIDAT1 + 2); + if (value == 0) { + spidat1 |= SPIDAT1_CSHOLD_MASK; + spidat1 &= ~(0x1 << chip_sel); + } else { + spidat1 &= ~SPIDAT1_CSHOLD_MASK; + spidat1 |= 0x03; + } + rt_kprintf("0x%04x\n", spidat1); + + writew(spidat1, dspi->base + SPIDAT1 + 2); + } } /** @@ -265,25 +265,25 @@ static void davinci_spi_chipselect(struct rt_spi_device *spi, int value) * or negative error number if valid prescalar cannot be updated. */ static inline int davinci_spi_get_prescale(struct davinci_spi *dspi, - u32 max_speed_hz) + u32 max_speed_hz) { - int ret; + int ret; - ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz); + ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz); - if (ret < 3) { - rt_kprintf("spi clock freq too high\n"); - ret = 3; - } - if (ret > 256) { - rt_kprintf("spi clock freq too litter\n"); - ret = 256; - } + if (ret < 3) { + rt_kprintf("spi clock freq too high\n"); + ret = 3; + } + if (ret > 256) { + rt_kprintf("spi clock freq too litter\n"); + ret = 256; + } - /*if (ret < 3 || ret > 256) - return -RT_ERROR;*/ + /*if (ret < 3 || ret > 256) + return -RT_ERROR;*/ - return ret - 1; + return ret - 1; } /** @@ -296,104 +296,104 @@ static inline int davinci_spi_get_prescale(struct davinci_spi *dspi, * SPI slave device freq. */ static int davinci_spi_setup_transfer(struct rt_spi_device *spi, - struct rt_spi_configuration *cfg) + struct rt_spi_configuration *cfg) { - struct davinci_spi *dspi; - struct davinci_spi_config *spicfg; - u8 bits_per_word = 0; - u32 hz = 0, spifmt = 0, prescale = 0; - u8 chip_select = (u8)spi->parent.user_data; - - dspi = spi->bus->parent.user_data; - spicfg = (struct davinci_spi_config *)dspi->controller_data; - if (!spicfg) - spicfg = &davinci_spi_default_cfg; - - bits_per_word = cfg->data_width; - hz = cfg->max_hz; - - /* - * Assign function pointer to appropriate transfer method - * 8bit, 16bit or 32bit transfer - */ - if (bits_per_word <= 8 && bits_per_word >= 2) { - dspi->get_rx = davinci_spi_rx_buf_u8; - dspi->get_tx = davinci_spi_tx_buf_u8; - dspi->bytes_per_word[chip_select] = 1; - } else if (bits_per_word <= 16 && bits_per_word >= 2) { - dspi->get_rx = davinci_spi_rx_buf_u16; - dspi->get_tx = davinci_spi_tx_buf_u16; - dspi->bytes_per_word[chip_select] = 2; - } else - return -RT_ERROR; - - /* Set up SPIFMTn register, unique to this chipselect. */ - - prescale = davinci_spi_get_prescale(dspi, hz); - if (prescale < 0) - return prescale; - - spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f); - - if (!(cfg->mode & RT_SPI_MSB)) - spifmt |= SPIFMT_SHIFTDIR_MASK; - - if (cfg->mode & RT_SPI_CPOL) - spifmt |= SPIFMT_POLARITY_MASK; - - if (!(cfg->mode & RT_SPI_CPHA)) - spifmt |= SPIFMT_PHASE_MASK; - - /* - * Version 1 hardware supports two basic SPI modes: - * - Standard SPI mode uses 4 pins, with chipselect - * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) - * (distinct from SPI_3WIRE, with just one data wire; - * or similar variants without MOSI or without MISO) - * - * Version 2 hardware supports an optional handshaking signal, - * so it can support two more modes: - * - 5 pin SPI variant is standard SPI plus SPI_READY - * - 4 pin with enable is (SPI_READY | SPI_NO_CS) - */ - - if (dspi->version == SPI_VERSION_2) { - - u32 delay = 0; - - spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT) - & SPIFMT_WDELAY_MASK); - - if (spicfg->odd_parity) - spifmt |= SPIFMT_ODD_PARITY_MASK; - - if (spicfg->parity_enable) - spifmt |= SPIFMT_PARITYENA_MASK; - - if (spicfg->timer_disable) { - spifmt |= SPIFMT_DISTIMER_MASK; - } else { - delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT) - & SPIDELAY_C2TDELAY_MASK; - delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT) - & SPIDELAY_T2CDELAY_MASK; - } - - if (cfg->mode & RT_SPI_READY) { - spifmt |= SPIFMT_WAITENA_MASK; - delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT) - & SPIDELAY_T2EDELAY_MASK; - delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT) - & SPIDELAY_C2EDELAY_MASK; - } - - writel(delay, dspi->base + SPIDELAY); - } - - writel(spifmt, dspi->base + SPIFMT0); - - return 0; + struct davinci_spi *dspi; + struct davinci_spi_config *spicfg; + u8 bits_per_word = 0; + u32 hz = 0, spifmt = 0, prescale = 0; + u8 chip_select = (u8)spi->parent.user_data; + + dspi = spi->bus->parent.user_data; + spicfg = (struct davinci_spi_config *)dspi->controller_data; + if (!spicfg) + spicfg = &davinci_spi_default_cfg; + + bits_per_word = cfg->data_width; + hz = cfg->max_hz; + + /* + * Assign function pointer to appropriate transfer method + * 8bit, 16bit or 32bit transfer + */ + if (bits_per_word <= 8 && bits_per_word >= 2) { + dspi->get_rx = davinci_spi_rx_buf_u8; + dspi->get_tx = davinci_spi_tx_buf_u8; + dspi->bytes_per_word[chip_select] = 1; + } else if (bits_per_word <= 16 && bits_per_word >= 2) { + dspi->get_rx = davinci_spi_rx_buf_u16; + dspi->get_tx = davinci_spi_tx_buf_u16; + dspi->bytes_per_word[chip_select] = 2; + } else + return -RT_ERROR; + + /* Set up SPIFMTn register, unique to this chipselect. */ + + prescale = davinci_spi_get_prescale(dspi, hz); + if (prescale < 0) + return prescale; + + spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f); + + if (!(cfg->mode & RT_SPI_MSB)) + spifmt |= SPIFMT_SHIFTDIR_MASK; + + if (cfg->mode & RT_SPI_CPOL) + spifmt |= SPIFMT_POLARITY_MASK; + + if (!(cfg->mode & RT_SPI_CPHA)) + spifmt |= SPIFMT_PHASE_MASK; + + /* + * Version 1 hardware supports two basic SPI modes: + * - Standard SPI mode uses 4 pins, with chipselect + * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) + * (distinct from SPI_3WIRE, with just one data wire; + * or similar variants without MOSI or without MISO) + * + * Version 2 hardware supports an optional handshaking signal, + * so it can support two more modes: + * - 5 pin SPI variant is standard SPI plus SPI_READY + * - 4 pin with enable is (SPI_READY | SPI_NO_CS) + */ + + if (dspi->version == SPI_VERSION_2) { + + u32 delay = 0; + + spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT) + & SPIFMT_WDELAY_MASK); + + if (spicfg->odd_parity) + spifmt |= SPIFMT_ODD_PARITY_MASK; + + if (spicfg->parity_enable) + spifmt |= SPIFMT_PARITYENA_MASK; + + if (spicfg->timer_disable) { + spifmt |= SPIFMT_DISTIMER_MASK; + } else { + delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT) + & SPIDELAY_C2TDELAY_MASK; + delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT) + & SPIDELAY_T2CDELAY_MASK; + } + + if (cfg->mode & RT_SPI_READY) { + spifmt |= SPIFMT_WAITENA_MASK; + delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT) + & SPIDELAY_T2EDELAY_MASK; + delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT) + & SPIDELAY_C2EDELAY_MASK; + } + + writel(delay, dspi->base + SPIDELAY); + } + + writel(spifmt, dspi->base + SPIFMT0); + + return 0; } #if 0 @@ -405,73 +405,73 @@ static int davinci_spi_setup_transfer(struct rt_spi_device *spi, */ static int davinci_spi_setup(struct spi_device *spi) { - int retval = 0; - struct davinci_spi *dspi; - struct davinci_spi_platform_data *pdata; + int retval = 0; + struct davinci_spi *dspi; + struct davinci_spi_platform_data *pdata; - dspi = spi_master_get_devdata(spi->master); - pdata = dspi->pdata; + dspi = spi_master_get_devdata(spi->master); + pdata = dspi->pdata; - /* if bits per word length is zero then set it default 8 */ - if (!spi->bits_per_word) - spi->bits_per_word = 8; + /* if bits per word length is zero then set it default 8 */ + if (!spi->bits_per_word) + spi->bits_per_word = 8; - if (!(spi->mode & SPI_NO_CS)) { - if ((pdata->chip_sel == NULL) || - (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS)) - set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select); + if (!(spi->mode & SPI_NO_CS)) { + if ((pdata->chip_sel == NULL) || + (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS)) + set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select); - } + } - if (spi->mode & SPI_READY) - set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK); + if (spi->mode & SPI_READY) + set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK); - if (spi->mode & SPI_LOOP) - set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); - else - clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); + if (spi->mode & SPI_LOOP) + set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); + else + clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); - return retval; + return retval; } #endif static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status) { - struct rt_device *sdev = &dspi->parent.parent; - - if (int_status & SPIFLG_TIMEOUT_MASK) { - spi_dbg(sdev, "SPI Time-out Error\n"); - return -RT_ETIMEOUT; - } - if (int_status & SPIFLG_DESYNC_MASK) { - spi_dbg(sdev, "SPI Desynchronization Error\n"); - return -RT_EIO; - } - if (int_status & SPIFLG_BITERR_MASK) { - spi_dbg(sdev, "SPI Bit error\n"); - return -RT_EIO; - } - - if (dspi->version == SPI_VERSION_2) { - if (int_status & SPIFLG_DLEN_ERR_MASK) { - spi_dbg(sdev, "SPI Data Length Error\n"); - return -RT_EIO; - } - if (int_status & SPIFLG_PARERR_MASK) { - spi_dbg(sdev, "SPI Parity Error\n"); - return -RT_EIO; - } - if (int_status & SPIFLG_OVRRUN_MASK) { - spi_dbg(sdev, "SPI Data Overrun error\n"); - return -RT_EIO; - } - if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) { - spi_dbg(sdev, "SPI Buffer Init Active\n"); - return -RT_EBUSY; - } - } - - return 0; + struct rt_device *sdev = &dspi->parent.parent; + + if (int_status & SPIFLG_TIMEOUT_MASK) { + spi_dbg(sdev, "SPI Time-out Error\n"); + return -RT_ETIMEOUT; + } + if (int_status & SPIFLG_DESYNC_MASK) { + spi_dbg(sdev, "SPI Desynchronization Error\n"); + return -RT_EIO; + } + if (int_status & SPIFLG_BITERR_MASK) { + spi_dbg(sdev, "SPI Bit error\n"); + return -RT_EIO; + } + + if (dspi->version == SPI_VERSION_2) { + if (int_status & SPIFLG_DLEN_ERR_MASK) { + spi_dbg(sdev, "SPI Data Length Error\n"); + return -RT_EIO; + } + if (int_status & SPIFLG_PARERR_MASK) { + spi_dbg(sdev, "SPI Parity Error\n"); + return -RT_EIO; + } + if (int_status & SPIFLG_OVRRUN_MASK) { + spi_dbg(sdev, "SPI Data Overrun error\n"); + return -RT_EIO; + } + if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) { + spi_dbg(sdev, "SPI Buffer Init Active\n"); + return -RT_EBUSY; + } + } + + return 0; } /** @@ -483,50 +483,50 @@ static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status) */ static int davinci_spi_process_events(struct davinci_spi *dspi) { - u32 buf, status, errors = 0, spidat1; + u32 buf, status, errors = 0, spidat1; - buf = readl(dspi->base + SPIBUF); + buf = readl(dspi->base + SPIBUF); - if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) { - dspi->get_rx(buf & 0xFFFF, dspi); - dspi->rcount--; - } + if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) { + dspi->get_rx(buf & 0xFFFF, dspi); + dspi->rcount--; + } - status = readl(dspi->base + SPIFLG); + status = readl(dspi->base + SPIFLG); - if (unlikely(status & SPIFLG_ERROR_MASK)) { - errors = status & SPIFLG_ERROR_MASK; - goto out; - } + if (unlikely(status & SPIFLG_ERROR_MASK)) { + errors = status & SPIFLG_ERROR_MASK; + goto out; + } - if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) { - spidat1 = readl(dspi->base + SPIDAT1); - dspi->wcount--; - spidat1 &= ~0xFFFF; - spidat1 |= 0xFFFF & dspi->get_tx(dspi); - writel(spidat1, dspi->base + SPIDAT1); - } + if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) { + spidat1 = readl(dspi->base + SPIDAT1); + dspi->wcount--; + spidat1 &= ~0xFFFF; + spidat1 |= 0xFFFF & dspi->get_tx(dspi); + writel(spidat1, dspi->base + SPIDAT1); + } out: - return errors; + return errors; } static void davinci_spi_dma_callback(unsigned lch, u16 status, void *data) { - struct davinci_spi *dspi = data; - struct davinci_spi_dma *dma = &dspi->dma; + struct davinci_spi *dspi = data; + struct davinci_spi_dma *dma = &dspi->dma; - edma_stop(lch); + edma_stop(lch); - if (status == DMA_COMPLETE) { - if (lch == dma->rx_channel) - dspi->rcount = 0; - if (lch == dma->tx_channel) - dspi->wcount = 0; - } + if (status == DMA_COMPLETE) { + if (lch == dma->rx_channel) + dspi->rcount = 0; + if (lch == dma->tx_channel) + dspi->wcount = 0; + } - if ((!dspi->wcount && !dspi->rcount) || (status != DMA_COMPLETE)) - rt_completion_done(&dspi->done); + if ((!dspi->wcount && !dspi->rcount) || (status != DMA_COMPLETE)) + rt_completion_done(&dspi->done); } /** @@ -540,186 +540,186 @@ static void davinci_spi_dma_callback(unsigned lch, u16 status, void *data) */ static int davinci_spi_bufs(struct rt_spi_device *spi, struct rt_spi_message *msg) { - struct davinci_spi *dspi; - int data_type, ret; - u32 tx_data, spidat1; - u32 errors = 0; - struct davinci_spi_config *spicfg; - unsigned rx_buf_count; - struct rt_device *sdev; - u8 chip_select = (u8)spi->parent.user_data; - - dspi = spi->bus->parent.user_data; - spicfg = (struct davinci_spi_config *)dspi->controller_data; - if (!spicfg) - spicfg = &davinci_spi_default_cfg; - sdev = &dspi->parent.parent; - - /* convert len to words based on bits_per_word */ - data_type = dspi->bytes_per_word[chip_select]; - - dspi->tx = msg->send_buf; - dspi->rx = msg->recv_buf; - dspi->wcount = msg->length / data_type; - dspi->rcount = dspi->wcount; - - spidat1 = readl(dspi->base + SPIDAT1); - - clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); - set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); - - rt_completion_init(&(dspi->done)); - - if (msg->cs_take) - davinci_spi_chipselect(spi, 0); - - if (spicfg->io_type == SPI_IO_TYPE_INTR) - set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); - - if (msg->length > 0) { - if (spicfg->io_type != SPI_IO_TYPE_DMA) { - /* start the transfer */ - dspi->wcount--; - tx_data = dspi->get_tx(dspi); - spidat1 &= 0xFFFF0000; - spidat1 |= tx_data & 0xFFFF; - writel(spidat1, dspi->base + SPIDAT1); - } else { - struct davinci_spi_dma *dma; - unsigned long tx_reg, rx_reg; - struct edmacc_param param; - void *rx_buf; - int b, c; - - dma = &dspi->dma; - - tx_reg = (unsigned long)dspi->base + SPIDAT1; - rx_reg = (unsigned long)dspi->base + SPIBUF; - - /* - * Transmit DMA setup - * - * If there is transmit data, map the transmit buffer, set it - * as the source of data and set the source B index to data - * size. If there is no transmit data, set the transmit register - * as the source of data, and set the source B index to zero. - * - * The destination is always the transmit register itself. And - * the destination never increments. - */ - - if (msg->send_buf) { - mmu_clean_dcache((rt_uint32_t)msg->send_buf, (rt_uint32_t)msg->length); - } - - /* - * If number of words is greater than 65535, then we need - * to configure a 3 dimension transfer. Use the BCNTRLD - * feature to allow for transfers that aren't even multiples - * of 65535 (or any other possible b size) by first transferring - * the remainder amount then grabbing the next N blocks of - * 65535 words. - */ - - c = dspi->wcount / (SZ_64K - 1); /* N 65535 Blocks */ - b = dspi->wcount - c * (SZ_64K - 1); /* Remainder */ - if (b) - c++; - else - b = SZ_64K - 1; - - param.opt = TCINTEN | EDMA_TCC(dma->tx_channel); - param.src = msg->send_buf ? msg->send_buf : tx_reg; - param.a_b_cnt = b << 16 | data_type; - param.dst = tx_reg; - param.src_dst_bidx = msg->send_buf ? data_type : 0; - param.link_bcntrld = 0xffffffff; - param.src_dst_cidx = msg->send_buf ? data_type : 0; - param.ccnt = c; - edma_write_slot(dma->tx_channel, ¶m); - edma_link(dma->tx_channel, dma->dummy_param_slot); - - /* - * Receive DMA setup - * - * If there is receive buffer, use it to receive data. If there - * is none provided, use a temporary receive buffer. Set the - * destination B index to 0 so effectively only one byte is used - * in the temporary buffer (address does not increment). - * - * The source of receive data is the receive data register. The - * source address never increments. - */ - - if (msg->recv_buf) { - rx_buf = msg->recv_buf; - rx_buf_count = msg->length; - } else { - rx_buf = dspi->rx_tmp_buf; - rx_buf_count = sizeof(dspi->rx_tmp_buf); - } - - mmu_invalidate_dcache((rt_uint32_t)rx_buf, (rt_uint32_t)rx_buf_count); - - param.opt = TCINTEN | EDMA_TCC(dma->rx_channel); - param.src = rx_reg; - param.a_b_cnt = b << 16 | data_type; - param.dst = rx_buf; - param.src_dst_bidx = (msg->recv_buf ? data_type : 0) << 16; - param.link_bcntrld = 0xffffffff; - param.src_dst_cidx = (msg->recv_buf ? data_type : 0) << 16; - param.ccnt = c; - edma_write_slot(dma->rx_channel, ¶m); - - if (dspi->cshold_bug) - writew(spidat1 >> 16, dspi->base + SPIDAT1 + 2); - - edma_start(dma->rx_channel); - edma_start(dma->tx_channel); - set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); - } - - /* Wait for the transfer to complete */ - if (spicfg->io_type != SPI_IO_TYPE_POLL) { - rt_completion_wait(&(dspi->done), RT_WAITING_FOREVER); - } else { - while (dspi->rcount > 0 || dspi->wcount > 0) { - errors = davinci_spi_process_events(dspi); - if (errors) - break; - cpu_relax(); - } - } - } - - if (msg->cs_release) - davinci_spi_chipselect(spi, 1); - - clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL); - if (spicfg->io_type == SPI_IO_TYPE_DMA) { - clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); - } - - clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); - set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); - - /* - * Check for bit error, desync error,parity error,timeout error and - * receive overflow errors - */ - if (errors) { - ret = davinci_spi_check_error(dspi, errors); - rt_kprintf("%s: error reported but no error found!\n", - spi->bus->parent.parent.name); - return ret; - } - - if (dspi->rcount != 0 || dspi->wcount != 0) { - spi_dbg(sdev, "SPI data transfer error\n"); - return -RT_EIO; - } - - return msg->length; + struct davinci_spi *dspi; + int data_type, ret; + u32 tx_data, spidat1; + u32 errors = 0; + struct davinci_spi_config *spicfg; + unsigned rx_buf_count; + struct rt_device *sdev; + u8 chip_select = (u8)spi->parent.user_data; + + dspi = spi->bus->parent.user_data; + spicfg = (struct davinci_spi_config *)dspi->controller_data; + if (!spicfg) + spicfg = &davinci_spi_default_cfg; + sdev = &dspi->parent.parent; + + /* convert len to words based on bits_per_word */ + data_type = dspi->bytes_per_word[chip_select]; + + dspi->tx = msg->send_buf; + dspi->rx = msg->recv_buf; + dspi->wcount = msg->length / data_type; + dspi->rcount = dspi->wcount; + + spidat1 = readl(dspi->base + SPIDAT1); + + clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); + set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); + + rt_completion_init(&(dspi->done)); + + if (msg->cs_take) + davinci_spi_chipselect(spi, 0); + + if (spicfg->io_type == SPI_IO_TYPE_INTR) + set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); + + if (msg->length > 0) { + if (spicfg->io_type != SPI_IO_TYPE_DMA) { + /* start the transfer */ + dspi->wcount--; + tx_data = dspi->get_tx(dspi); + spidat1 &= 0xFFFF0000; + spidat1 |= tx_data & 0xFFFF; + writel(spidat1, dspi->base + SPIDAT1); + } else { + struct davinci_spi_dma *dma; + unsigned long tx_reg, rx_reg; + struct edmacc_param param; + void *rx_buf; + int b, c; + + dma = &dspi->dma; + + tx_reg = (unsigned long)dspi->base + SPIDAT1; + rx_reg = (unsigned long)dspi->base + SPIBUF; + + /* + * Transmit DMA setup + * + * If there is transmit data, map the transmit buffer, set it + * as the source of data and set the source B index to data + * size. If there is no transmit data, set the transmit register + * as the source of data, and set the source B index to zero. + * + * The destination is always the transmit register itself. And + * the destination never increments. + */ + + if (msg->send_buf) { + mmu_clean_dcache((rt_uint32_t)msg->send_buf, (rt_uint32_t)msg->length); + } + + /* + * If number of words is greater than 65535, then we need + * to configure a 3 dimension transfer. Use the BCNTRLD + * feature to allow for transfers that aren't even multiples + * of 65535 (or any other possible b size) by first transferring + * the remainder amount then grabbing the next N blocks of + * 65535 words. + */ + + c = dspi->wcount / (SZ_64K - 1); /* N 65535 Blocks */ + b = dspi->wcount - c * (SZ_64K - 1); /* Remainder */ + if (b) + c++; + else + b = SZ_64K - 1; + + param.opt = TCINTEN | EDMA_TCC(dma->tx_channel); + param.src = msg->send_buf ? msg->send_buf : tx_reg; + param.a_b_cnt = b << 16 | data_type; + param.dst = tx_reg; + param.src_dst_bidx = msg->send_buf ? data_type : 0; + param.link_bcntrld = 0xffffffff; + param.src_dst_cidx = msg->send_buf ? data_type : 0; + param.ccnt = c; + edma_write_slot(dma->tx_channel, ¶m); + edma_link(dma->tx_channel, dma->dummy_param_slot); + + /* + * Receive DMA setup + * + * If there is receive buffer, use it to receive data. If there + * is none provided, use a temporary receive buffer. Set the + * destination B index to 0 so effectively only one byte is used + * in the temporary buffer (address does not increment). + * + * The source of receive data is the receive data register. The + * source address never increments. + */ + + if (msg->recv_buf) { + rx_buf = msg->recv_buf; + rx_buf_count = msg->length; + } else { + rx_buf = dspi->rx_tmp_buf; + rx_buf_count = sizeof(dspi->rx_tmp_buf); + } + + mmu_invalidate_dcache((rt_uint32_t)rx_buf, (rt_uint32_t)rx_buf_count); + + param.opt = TCINTEN | EDMA_TCC(dma->rx_channel); + param.src = rx_reg; + param.a_b_cnt = b << 16 | data_type; + param.dst = rx_buf; + param.src_dst_bidx = (msg->recv_buf ? data_type : 0) << 16; + param.link_bcntrld = 0xffffffff; + param.src_dst_cidx = (msg->recv_buf ? data_type : 0) << 16; + param.ccnt = c; + edma_write_slot(dma->rx_channel, ¶m); + + if (dspi->cshold_bug) + writew(spidat1 >> 16, dspi->base + SPIDAT1 + 2); + + edma_start(dma->rx_channel); + edma_start(dma->tx_channel); + set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); + } + + /* Wait for the transfer to complete */ + if (spicfg->io_type != SPI_IO_TYPE_POLL) { + rt_completion_wait(&(dspi->done), RT_WAITING_FOREVER); + } else { + while (dspi->rcount > 0 || dspi->wcount > 0) { + errors = davinci_spi_process_events(dspi); + if (errors) + break; + cpu_relax(); + } + } + } + + if (msg->cs_release) + davinci_spi_chipselect(spi, 1); + + clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL); + if (spicfg->io_type == SPI_IO_TYPE_DMA) { + clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); + } + + clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); + set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); + + /* + * Check for bit error, desync error,parity error,timeout error and + * receive overflow errors + */ + if (errors) { + ret = davinci_spi_check_error(dspi, errors); + rt_kprintf("%s: error reported but no error found!\n", + spi->bus->parent.parent.name); + return ret; + } + + if (dspi->rcount != 0 || dspi->wcount != 0) { + spi_dbg(sdev, "SPI data transfer error\n"); + return -RT_EIO; + } + + return msg->length; } /** @@ -735,65 +735,65 @@ static int davinci_spi_bufs(struct rt_spi_device *spi, struct rt_spi_message *ms */ static void davinci_spi_irq(int irq, void *data) { - struct davinci_spi *dspi = data; - int status; + struct davinci_spi *dspi = data; + int status; - status = davinci_spi_process_events(dspi); - if (unlikely(status != 0)) - clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); + status = davinci_spi_process_events(dspi); + if (unlikely(status != 0)) + clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); - if ((!dspi->rcount && !dspi->wcount) || status) - rt_completion_done(&dspi->done); + if ((!dspi->rcount && !dspi->wcount) || status) + rt_completion_done(&dspi->done); } static int davinci_spi_request_dma(struct davinci_spi *dspi) { - int r; - struct davinci_spi_dma *dma = &dspi->dma; - - r = edma_alloc_channel(dma->rx_channel, davinci_spi_dma_callback, dspi, - dma->eventq); - if (r < 0) { - rt_kprintf("Unable to request DMA channel for SPI RX\n"); - r = -RT_EFULL; - goto rx_dma_failed; - } - - r = edma_alloc_channel(dma->tx_channel, davinci_spi_dma_callback, dspi, - dma->eventq); - if (r < 0) { - rt_kprintf("Unable to request DMA channel for SPI TX\n"); - r = -RT_EFULL; - goto tx_dma_failed; - } - - r = edma_alloc_slot(EDMA_CTLR(dma->tx_channel), EDMA_SLOT_ANY); - if (r < 0) { - rt_kprintf("Unable to request SPI TX DMA param slot\n"); - r = -RT_EFULL; - goto param_failed; - } - dma->dummy_param_slot = r; - edma_link(dma->dummy_param_slot, dma->dummy_param_slot); - - return 0; + int r; + struct davinci_spi_dma *dma = &dspi->dma; + + r = edma_alloc_channel(dma->rx_channel, davinci_spi_dma_callback, dspi, + dma->eventq); + if (r < 0) { + rt_kprintf("Unable to request DMA channel for SPI RX\n"); + r = -RT_EFULL; + goto rx_dma_failed; + } + + r = edma_alloc_channel(dma->tx_channel, davinci_spi_dma_callback, dspi, + dma->eventq); + if (r < 0) { + rt_kprintf("Unable to request DMA channel for SPI TX\n"); + r = -RT_EFULL; + goto tx_dma_failed; + } + + r = edma_alloc_slot(EDMA_CTLR(dma->tx_channel), EDMA_SLOT_ANY); + if (r < 0) { + rt_kprintf("Unable to request SPI TX DMA param slot\n"); + r = -RT_EFULL; + goto param_failed; + } + dma->dummy_param_slot = r; + edma_link(dma->dummy_param_slot, dma->dummy_param_slot); + + return 0; param_failed: - edma_free_channel(dma->tx_channel); + edma_free_channel(dma->tx_channel); tx_dma_failed: - edma_free_channel(dma->rx_channel); + edma_free_channel(dma->rx_channel); rx_dma_failed: - return r; + return r; } static rt_err_t configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration) { - return davinci_spi_setup_transfer(device, configuration); + return davinci_spi_setup_transfer(device, configuration); } static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message *message) { - return davinci_spi_bufs(device, message); + return davinci_spi_bufs(device, message); }; @@ -806,29 +806,29 @@ static struct rt_spi_ops davinci_spi_ops = static void udelay (volatile rt_uint32_t us) { - volatile rt_int32_t i; - for (; us > 0; us--) - { - i = 5000; - while(i > 0) - { - i--; - } - } + volatile rt_int32_t i; + for (; us > 0; us--) + { + i = 5000; + while(i > 0) + { + i--; + } + } } void spi_pin_cfg(void) { - rt_uint32_t val; + rt_uint32_t val; - val = davinci_readl(PINMUX3); - val |= 0x80000000; /* SPI1 */ - davinci_writel(val, PINMUX3); + val = davinci_readl(PINMUX3); + val |= 0x80000000; /* SPI1 */ + davinci_writel(val, PINMUX3); - val = davinci_readl(PINMUX4); - val &= 0xffffffc0; /* SPI1 */ - val |= 0x05;//0x00000015; /* SPI1 */ - davinci_writel(val, PINMUX4); + val = davinci_readl(PINMUX4); + val &= 0xffffffc0; /* SPI1 */ + val |= 0x05;//0x00000015; /* SPI1 */ + davinci_writel(val, PINMUX4); } /** @@ -844,87 +844,87 @@ void spi_pin_cfg(void) */ static int davinci_spi_probe(struct davinci_spi *dspi, char *spi_bus_name) { - int i = 0, ret = 0; - u32 spipc0; + int i = 0, ret = 0; + u32 spipc0; - spi_pin_cfg(); - psc_change_state(DAVINCI_DM365_LPSC_SPI1, PSC_ENABLE); + spi_pin_cfg(); + psc_change_state(DAVINCI_DM365_LPSC_SPI1, PSC_ENABLE); - dspi->base = DM3XX_SPI1_BASE;//spi; + dspi->base = DM3XX_SPI1_BASE;//spi; - dspi->irq = IRQ_DM3XX_SPINT1_0; + dspi->irq = IRQ_DM3XX_SPINT1_0; - rt_hw_interrupt_install(dspi->irq, davinci_spi_irq, dspi, spi_bus_name); - rt_hw_interrupt_umask(dspi->irq); + rt_hw_interrupt_install(dspi->irq, davinci_spi_irq, dspi, spi_bus_name); + rt_hw_interrupt_umask(dspi->irq); - dspi->clk = clk_get("SPICLK"); + dspi->clk = clk_get("SPICLK"); - dspi->version = SPI_VERSION_1; - dspi->chip_sel[0] = 29;//SPI_INTERN_CS; - dspi->chip_sel[1] = 0;//GPIO0 + dspi->version = SPI_VERSION_1; + dspi->chip_sel[0] = 29;//SPI_INTERN_CS; + dspi->chip_sel[1] = 0;//GPIO0 - dspi->dma.rx_channel = 15; - dspi->dma.tx_channel = 14; - dspi->dma.eventq = EVENTQ_3; + dspi->dma.rx_channel = 15; + dspi->dma.tx_channel = 14; + dspi->dma.eventq = EVENTQ_3; - ret = davinci_spi_request_dma(dspi); - if (ret) - goto err; + ret = davinci_spi_request_dma(dspi); + if (ret) + goto err; - rt_kprintf("%s: DMA: supported\n", spi_bus_name); - rt_kprintf("%s: DMA: RX channel: %d, TX channel: %d, " - "event queue: %d\n", spi_bus_name, dspi->dma.rx_channel, - dspi->dma.tx_channel, dspi->dma.eventq); + rt_kprintf("%s: DMA: supported\n", spi_bus_name); + rt_kprintf("%s: DMA: RX channel: %d, TX channel: %d, " + "event queue: %d\n", spi_bus_name, dspi->dma.rx_channel, + dspi->dma.tx_channel, dspi->dma.eventq); - dspi->get_rx = davinci_spi_rx_buf_u8; - dspi->get_tx = davinci_spi_tx_buf_u8; + dspi->get_rx = davinci_spi_rx_buf_u8; + dspi->get_tx = davinci_spi_tx_buf_u8; - rt_completion_init(&dspi->done); + rt_completion_init(&dspi->done); - /* Reset In/OUT SPI module */ - writel(0, dspi->base + SPIGCR0); - udelay(100); - writel(1, dspi->base + SPIGCR0); + /* Reset In/OUT SPI module */ + writel(0, dspi->base + SPIGCR0); + udelay(100); + writel(1, dspi->base + SPIGCR0); - /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */ - spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; - writel(spipc0, dspi->base + SPIPC0); + /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */ + spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; + writel(spipc0, dspi->base + SPIPC0); - /* initialize chip selects */ - for (i = 0; i < SPI_MAX_CHIPSELECT; i++) { - if (dspi->chip_sel[i] != SPI_INTERN_CS) - gpio_direction_output(dspi->chip_sel[i], 1); - } + /* initialize chip selects */ + for (i = 0; i < SPI_MAX_CHIPSELECT; i++) { + if (dspi->chip_sel[i] != SPI_INTERN_CS) + gpio_direction_output(dspi->chip_sel[i], 1); + } - if (0) - writel(SPI_INTLVL_1, dspi->base + SPILVL); - else - writel(SPI_INTLVL_0, dspi->base + SPILVL); + if (0) + writel(SPI_INTLVL_1, dspi->base + SPILVL); + else + writel(SPI_INTLVL_0, dspi->base + SPILVL); - writel(CS_DEFAULT, dspi->base + SPIDEF); + writel(CS_DEFAULT, dspi->base + SPIDEF); - /* master mode default */ - set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK); - set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK); - set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); + /* master mode default */ + set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK); + set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK); + set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); - //set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);//LOOP BACK mode + //set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);//LOOP BACK mode - rt_kprintf("%s: Controller at 0x%p\n", spi_bus_name, dspi->base); + rt_kprintf("%s: Controller at 0x%p\n", spi_bus_name, dspi->base); - dspi->parent.parent.user_data = dspi; + dspi->parent.parent.user_data = dspi; - return rt_spi_bus_register(&dspi->parent, spi_bus_name, &davinci_spi_ops); + return rt_spi_bus_register(&dspi->parent, spi_bus_name, &davinci_spi_ops); - return ret; + return ret; free_dma: - edma_free_channel(dspi->dma.tx_channel); - edma_free_channel(dspi->dma.rx_channel); - edma_free_slot(dspi->dma.dummy_param_slot); + edma_free_channel(dspi->dma.tx_channel); + edma_free_channel(dspi->dma.rx_channel); + edma_free_slot(dspi->dma.dummy_param_slot); err: - return ret; + return ret; } @@ -933,15 +933,15 @@ int rt_hw_spi_init(void) /* register spi bus */ { static struct davinci_spi dspi; - rt_memset(&dspi, 0, sizeof(dspi)); - davinci_spi_probe(&dspi, "spi1"); + rt_memset(&dspi, 0, sizeof(dspi)); + davinci_spi_probe(&dspi, "spi1"); } /* attach cs */ { static struct rt_spi_device spi_device; rt_spi_bus_attach_device(&spi_device, "spi10", "spi1", (void *)0); } - { + { static struct rt_spi_device spi_device; rt_spi_bus_attach_device(&spi_device, "spi11", "spi1", (void *)1); } diff --git a/bsp/dm365/drivers/spi-davinci.h b/bsp/dm365/drivers/spi-davinci.h index 0aa0a7eac1..d1761e03f3 100644 --- a/bsp/dm365/drivers/spi-davinci.h +++ b/bsp/dm365/drivers/spi-davinci.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ #ifndef __DAVINCI_SPI_H @@ -16,46 +16,46 @@ typedef unsigned short u16; typedef unsigned char u8; typedef unsigned int bool; -#define SPI_INTERN_CS 0xFF +#define SPI_INTERN_CS 0xFF enum { - SPI_VERSION_1, /* For DM355/DM365/DM6467 */ - SPI_VERSION_2, /* For DA8xx */ + SPI_VERSION_1, /* For DM355/DM365/DM6467 */ + SPI_VERSION_2, /* For DA8xx */ }; /** * davinci_spi_config - Per-chip-select configuration for SPI slave devices * - * @wdelay: amount of delay between transmissions. Measured in number of - * SPI module clocks. - * @odd_parity: polarity of parity flag at the end of transmit data stream. - * 0 - odd parity, 1 - even parity. + * @wdelay: amount of delay between transmissions. Measured in number of + * SPI module clocks. + * @odd_parity: polarity of parity flag at the end of transmit data stream. + * 0 - odd parity, 1 - even parity. * @parity_enable: enable transmission of parity at end of each transmit - * data stream. - * @io_type: type of IO transfer. Choose between polled, interrupt and DMA. + * data stream. + * @io_type: type of IO transfer. Choose between polled, interrupt and DMA. * @timer_disable: disable chip-select timers (setup and hold) - * @c2tdelay: chip-select setup time. Measured in number of SPI module clocks. - * @t2cdelay: chip-select hold time. Measured in number of SPI module clocks. - * @t2edelay: transmit data finished to SPI ENAn pin inactive time. Measured - * in number of SPI clocks. - * @c2edelay: chip-select active to SPI ENAn signal active time. Measured in - * number of SPI clocks. + * @c2tdelay: chip-select setup time. Measured in number of SPI module clocks. + * @t2cdelay: chip-select hold time. Measured in number of SPI module clocks. + * @t2edelay: transmit data finished to SPI ENAn pin inactive time. Measured + * in number of SPI clocks. + * @c2edelay: chip-select active to SPI ENAn signal active time. Measured in + * number of SPI clocks. */ struct davinci_spi_config { - u8 wdelay; - u8 odd_parity; - u8 parity_enable; -#define SPI_IO_TYPE_INTR 0 -#define SPI_IO_TYPE_POLL 1 -#define SPI_IO_TYPE_DMA 2 - u8 io_type; - u8 timer_disable; - u8 c2tdelay; - u8 t2cdelay; - u8 t2edelay; - u8 c2edelay; + u8 wdelay; + u8 odd_parity; + u8 parity_enable; +#define SPI_IO_TYPE_INTR 0 +#define SPI_IO_TYPE_POLL 1 +#define SPI_IO_TYPE_DMA 2 + u8 io_type; + u8 timer_disable; + u8 c2tdelay; + u8 t2cdelay; + u8 t2edelay; + u8 c2edelay; }; extern int rt_hw_spi_init(void); -#endif /* __DAVINCI_SPI_H */ +#endif /* __DAVINCI_SPI_H */ diff --git a/bsp/dm365/platform/dm365.c b/bsp/dm365/platform/dm365.c index 376bbeb115..0fe2d0a94a 100644 --- a/bsp/dm365/platform/dm365.c +++ b/bsp/dm365/platform/dm365.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ #include @@ -26,285 +26,285 @@ static rt_uint32_t vpssrate, vencrate_sd, vencrate_hd; /* Four Transfer Controllers on DM365 */ static const rt_int8_t dm365_queue_tc_mapping[][2] = { - /* {event queue no, TC no} */ - {0, 0}, - {1, 1}, - {2, 2}, - {3, 3}, - {-1, -1}, + /* {event queue no, TC no} */ + {0, 0}, + {1, 1}, + {2, 2}, + {3, 3}, + {-1, -1}, }; static const rt_int8_t dm365_queue_priority_mapping[][2] = { - /* {event queue no, Priority} */ - {0, 7}, - {1, 7}, - {2, 7}, - {3, 0}, - {-1, -1}, + /* {event queue no, Priority} */ + {0, 7}, + {1, 7}, + {2, 7}, + {3, 0}, + {-1, -1}, }; static struct edma_soc_info edma_cc0_info = { - .n_channel = 64, - .n_region = 4, - .n_slot = 256, - .n_tc = 4, - .n_cc = 1, - .queue_tc_mapping = dm365_queue_tc_mapping, - .queue_priority_mapping = dm365_queue_priority_mapping, - .default_queue = EVENTQ_3, + .n_channel = 64, + .n_region = 4, + .n_slot = 256, + .n_tc = 4, + .n_cc = 1, + .queue_tc_mapping = dm365_queue_tc_mapping, + .queue_priority_mapping = dm365_queue_priority_mapping, + .default_queue = EVENTQ_3, }; static struct edma_soc_info *dm365_edma_info[EDMA_MAX_CC] = { - &edma_cc0_info, + &edma_cc0_info, }; static rt_list_t clocks; struct clk { - char name[32]; - rt_uint32_t *rate_hz; - struct clk *parent; - rt_list_t node; + char name[32]; + rt_uint32_t *rate_hz; + struct clk *parent; + rt_list_t node; }; static struct clk davinci_dm365_clks[] = { - { - .name = "ARMCLK", - .rate_hz = &armrate, - }, - { - .name = "UART0", - .rate_hz = &fixedrate, - }, - { - .name = "UART1", - .rate_hz = &commonrate, - }, - { - .name = "HPI", - .rate_hz = &commonrate, - }, - { - .name = "EMACCLK", - .rate_hz = &commonrate, - }, - { - .name = "I2CCLK", - .rate_hz = &fixedrate, - }, - { - .name = "McBSPCLK", - .rate_hz = &commonrate, - }, - { - .name = "MMCSDCLK0", - .rate_hz = &mmcsdrate, - }, - { - .name = "MMCSDCLK1", - .rate_hz = &mmcsdrate, - }, - { - .name = "SPICLK", - .rate_hz = &commonrate, - }, - { - .name = "gpio", - .rate_hz = &commonrate, - }, - { - .name = "AEMIFCLK", - .rate_hz = &commonrate, - }, - { - .name = "PWM0_CLK", - .rate_hz = &fixedrate, - }, - { - .name = "PWM1_CLK", - .rate_hz = &fixedrate, - }, - { - .name = "PWM2_CLK", - .rate_hz = &fixedrate, - }, - { - .name = "PWM3_CLK", - .rate_hz = &fixedrate, - }, - { - .name = "USBCLK", - .rate_hz = &fixedrate, - }, - { - .name = "VOICECODEC_CLK", - .rate_hz = &voicerate, - }, - { - .name = "RTC_CLK", - .rate_hz = &fixedrate, - }, - { - .name = "KEYSCAN_CLK", - .rate_hz = &fixedrate, - }, - { - .name = "ADCIF_CLK", - .rate_hz = &fixedrate, - }, + { + .name = "ARMCLK", + .rate_hz = &armrate, + }, + { + .name = "UART0", + .rate_hz = &fixedrate, + }, + { + .name = "UART1", + .rate_hz = &commonrate, + }, + { + .name = "HPI", + .rate_hz = &commonrate, + }, + { + .name = "EMACCLK", + .rate_hz = &commonrate, + }, + { + .name = "I2CCLK", + .rate_hz = &fixedrate, + }, + { + .name = "McBSPCLK", + .rate_hz = &commonrate, + }, + { + .name = "MMCSDCLK0", + .rate_hz = &mmcsdrate, + }, + { + .name = "MMCSDCLK1", + .rate_hz = &mmcsdrate, + }, + { + .name = "SPICLK", + .rate_hz = &commonrate, + }, + { + .name = "gpio", + .rate_hz = &commonrate, + }, + { + .name = "AEMIFCLK", + .rate_hz = &commonrate, + }, + { + .name = "PWM0_CLK", + .rate_hz = &fixedrate, + }, + { + .name = "PWM1_CLK", + .rate_hz = &fixedrate, + }, + { + .name = "PWM2_CLK", + .rate_hz = &fixedrate, + }, + { + .name = "PWM3_CLK", + .rate_hz = &fixedrate, + }, + { + .name = "USBCLK", + .rate_hz = &fixedrate, + }, + { + .name = "VOICECODEC_CLK", + .rate_hz = &voicerate, + }, + { + .name = "RTC_CLK", + .rate_hz = &fixedrate, + }, + { + .name = "KEYSCAN_CLK", + .rate_hz = &fixedrate, + }, + { + .name = "ADCIF_CLK", + .rate_hz = &fixedrate, + }, }; /* clocks cannot be de-registered no refcounting necessary */ struct clk *clk_get(const char *id) { - struct clk *clk; - rt_list_t *list; - - for (list = (&clocks)->next; list != &clocks; list = list->next) - { - clk = (struct clk *)rt_list_entry(list, struct clk, node); - if (rt_strcmp(id, clk->name) == 0) - return clk; - } - - return RT_NULL; + struct clk *clk; + rt_list_t *list; + + for (list = (&clocks)->next; list != &clocks; list = list->next) + { + clk = (struct clk *)rt_list_entry(list, struct clk, node); + if (rt_strcmp(id, clk->name) == 0) + return clk; + } + + return RT_NULL; } rt_uint32_t clk_get_rate(struct clk *clk) { - rt_uint32_t flags; - rt_uint32_t *rate; - - for (;;) { - rate = clk->rate_hz; - if (rate || !clk->parent) - break; - clk = clk->parent; - } - return *rate; + rt_uint32_t flags; + rt_uint32_t *rate; + + for (;;) { + rate = clk->rate_hz; + if (rate || !clk->parent) + break; + clk = clk->parent; + } + return *rate; } void clk_register(struct clk *clk) { - rt_list_insert_after(&clocks, &clk->node); + rt_list_insert_after(&clocks, &clk->node); } int davinci_register_clks(struct clk *clk_list, int num_clks) { - struct clk *clkp; - int i; + struct clk *clkp; + int i; - for (i = 0, clkp = clk_list; i < num_clks; i++, clkp++) - { - //rt_kprintf("1:%s\n", clkp->name); - clk_register(clkp); - //rt_kprintf("2:%s\n", clkp->name); - } + for (i = 0, clkp = clk_list; i < num_clks; i++, clkp++) + { + //rt_kprintf("1:%s\n", clkp->name); + clk_register(clkp); + //rt_kprintf("2:%s\n", clkp->name); + } - return 0; + return 0; } /* PLL/Reset register offsets */ -#define PLLM 0x110 -#define PREDIV 0x114 -#define PLLDIV2 0x11C -#define POSTDIV 0x128 -#define PLLDIV4 0x160 -#define PLLDIV5 0x164 -#define PLLDIV6 0x168 -#define PLLDIV7 0x16C -#define PLLDIV8 0x170 +#define PLLM 0x110 +#define PREDIV 0x114 +#define PLLDIV2 0x11C +#define POSTDIV 0x128 +#define PLLDIV4 0x160 +#define PLLDIV5 0x164 +#define PLLDIV6 0x168 +#define PLLDIV7 0x16C +#define PLLDIV8 0x170 int davinci_clk_init(void) { - struct clk *clk_list; - int num_clks; - rt_uint32_t pll0_mult, pll1_mult; - - unsigned long prediv, postdiv; - unsigned long pll_rate; - unsigned long pll_div2, pll_div4, pll_div5, - pll_div6, pll_div7, pll_div8; - - rt_list_init(&clocks); - - //davinci_psc_register(davinci_psc_base, 1); - - pll0_mult = davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLM); - pll1_mult = davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLM); - - commonrate = ((pll0_mult + 1) * 27000000) / 6; - armrate = ((pll0_mult + 1) * 27000000) / 2; - - fixedrate = 24000000; - - /* Read PLL0 configuration */ - prediv = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PREDIV) & - 0x1f) + 1; - postdiv = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + POSTDIV) & - 0x1f) + 1; - - /* PLL0 dividers */ - pll_div4 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV4) & - 0x1f) + 1; /* EDMA, EMAC, config, common */ - pll_div5 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV5) & - 0x1f) + 1; /* VPSS */ - pll_div6 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV6) & - 0x1f) + 1; /* VENC */ - pll_div7 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV7) & - 0x1f) + 1; /* DDR */ - pll_div8 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV8) & - 0x1f) + 1; /* MMC/SD */ - - pll_rate = ((fixedrate / prediv) * (2 * pll0_mult)) / postdiv; - - commonrate = pll_rate / pll_div4; /* 486/4 = 121.5MHz */ - vpssrate = pll_rate / pll_div5; /* 486/2 = 243MHz */ - vencrate_sd = pll_rate / pll_div6; /* 486/18 = 27MHz */ - ddrrate = pll_rate / pll_div7; /* 486/2 = 243MHz */ - mmcsdrate = pll_rate / pll_div8; /* 486/4 = 121.5MHz */ - - rt_kprintf( - "PLL0: fixedrate: %d, commonrate: %d, vpssrate: %d\n", - fixedrate, commonrate, vpssrate); - rt_kprintf( - "PLL0: vencrate_sd: %d, ddrrate: %d mmcsdrate: %d\n", - vencrate_sd, (ddrrate/2), mmcsdrate); - - /* Read PLL1 configuration */ - prediv = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PREDIV) & - 0x1f) + 1; - postdiv = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + POSTDIV) & - 0x1f) + 1; - pll_rate = ((fixedrate / prediv) * (2 * pll1_mult)) / postdiv; - - /* PLL1 dividers */ - pll_div2 = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLDIV2) & - 0x1f) + 1; /* ARM */ - pll_div4 = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLDIV4) & - 0x1f) + 1; /* VOICE */ - pll_div5 = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLDIV5) & - 0x1f) + 1; /* VENC */ - - armrate = pll_rate / pll_div2; /* 594/2 = 297MHz */ - voicerate = pll_rate / pll_div4; /* 594/6 = 99MHz */ - vencrate_hd = pll_rate / pll_div5; /* 594/8 = 74.25MHz */ - - rt_kprintf( - "PLL1: armrate: %d, voicerate: %d, vencrate_hd: %d\n", - armrate, voicerate, vencrate_hd); - - clk_list = davinci_dm365_clks; - num_clks = ARRAY_SIZE(davinci_dm365_clks); - - return davinci_register_clks(clk_list, num_clks); + struct clk *clk_list; + int num_clks; + rt_uint32_t pll0_mult, pll1_mult; + + unsigned long prediv, postdiv; + unsigned long pll_rate; + unsigned long pll_div2, pll_div4, pll_div5, + pll_div6, pll_div7, pll_div8; + + rt_list_init(&clocks); + + //davinci_psc_register(davinci_psc_base, 1); + + pll0_mult = davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLM); + pll1_mult = davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLM); + + commonrate = ((pll0_mult + 1) * 27000000) / 6; + armrate = ((pll0_mult + 1) * 27000000) / 2; + + fixedrate = 24000000; + + /* Read PLL0 configuration */ + prediv = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PREDIV) & + 0x1f) + 1; + postdiv = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + POSTDIV) & + 0x1f) + 1; + + /* PLL0 dividers */ + pll_div4 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV4) & + 0x1f) + 1; /* EDMA, EMAC, config, common */ + pll_div5 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV5) & + 0x1f) + 1; /* VPSS */ + pll_div6 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV6) & + 0x1f) + 1; /* VENC */ + pll_div7 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV7) & + 0x1f) + 1; /* DDR */ + pll_div8 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV8) & + 0x1f) + 1; /* MMC/SD */ + + pll_rate = ((fixedrate / prediv) * (2 * pll0_mult)) / postdiv; + + commonrate = pll_rate / pll_div4; /* 486/4 = 121.5MHz */ + vpssrate = pll_rate / pll_div5; /* 486/2 = 243MHz */ + vencrate_sd = pll_rate / pll_div6; /* 486/18 = 27MHz */ + ddrrate = pll_rate / pll_div7; /* 486/2 = 243MHz */ + mmcsdrate = pll_rate / pll_div8; /* 486/4 = 121.5MHz */ + + rt_kprintf( + "PLL0: fixedrate: %d, commonrate: %d, vpssrate: %d\n", + fixedrate, commonrate, vpssrate); + rt_kprintf( + "PLL0: vencrate_sd: %d, ddrrate: %d mmcsdrate: %d\n", + vencrate_sd, (ddrrate/2), mmcsdrate); + + /* Read PLL1 configuration */ + prediv = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PREDIV) & + 0x1f) + 1; + postdiv = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + POSTDIV) & + 0x1f) + 1; + pll_rate = ((fixedrate / prediv) * (2 * pll1_mult)) / postdiv; + + /* PLL1 dividers */ + pll_div2 = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLDIV2) & + 0x1f) + 1; /* ARM */ + pll_div4 = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLDIV4) & + 0x1f) + 1; /* VOICE */ + pll_div5 = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLDIV5) & + 0x1f) + 1; /* VENC */ + + armrate = pll_rate / pll_div2; /* 594/2 = 297MHz */ + voicerate = pll_rate / pll_div4; /* 594/6 = 99MHz */ + vencrate_hd = pll_rate / pll_div5; /* 594/8 = 74.25MHz */ + + rt_kprintf( + "PLL1: armrate: %d, voicerate: %d, vencrate_hd: %d\n", + armrate, voicerate, vencrate_hd); + + clk_list = davinci_dm365_clks; + num_clks = ARRAY_SIZE(davinci_dm365_clks); + + return davinci_register_clks(clk_list, num_clks); } int platform_init(void) { - edma_init(dm365_edma_info); + edma_init(dm365_edma_info); } INIT_BOARD_EXPORT(platform_init); @@ -312,44 +312,44 @@ INIT_BOARD_EXPORT(platform_init); /* Reset board using the watchdog timer */ void reset_system(void) { - rt_uint32_t tgcr, wdtcr; - rt_uint32_t base = DAVINCI_WDOG_BASE; - - /* Disable, internal clock source */ - davinci_writel(0, base + TCR); - - /* Reset timer, set mode to 64-bit watchdog, and unreset */ - davinci_writel(0, base + TGCR); - tgcr = (TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT) | - (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | - (TGCR_UNRESET << TGCR_TIM34RS_SHIFT); - davinci_writel(tgcr, base + TGCR); - - /* Clear counter and period regs */ - davinci_writel(0, base + TIM12); - davinci_writel(0, base + TIM34); - davinci_writel(0, base + PRD12); - davinci_writel(0, base + PRD34); - - /* Enable periodic mode */ - davinci_writel(TCR_ENAMODE_PERIODIC << ENAMODE12_SHIFT, base + TCR); - - /* Put watchdog in pre-active state */ - wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) | - (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT); - davinci_writel(wdtcr, base + WDTCR); - - /* Put watchdog in active state */ - wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) | - (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT); - davinci_writel(wdtcr, base + WDTCR); - - /* - * Write an invalid value to the WDKEY field to trigger - * a watchdog reset. - */ - wdtcr = 0xDEADBEEF; - davinci_writel(wdtcr, base + WDTCR); + rt_uint32_t tgcr, wdtcr; + rt_uint32_t base = DAVINCI_WDOG_BASE; + + /* Disable, internal clock source */ + davinci_writel(0, base + TCR); + + /* Reset timer, set mode to 64-bit watchdog, and unreset */ + davinci_writel(0, base + TGCR); + tgcr = (TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT) | + (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | + (TGCR_UNRESET << TGCR_TIM34RS_SHIFT); + davinci_writel(tgcr, base + TGCR); + + /* Clear counter and period regs */ + davinci_writel(0, base + TIM12); + davinci_writel(0, base + TIM34); + davinci_writel(0, base + PRD12); + davinci_writel(0, base + PRD34); + + /* Enable periodic mode */ + davinci_writel(TCR_ENAMODE_PERIODIC << ENAMODE12_SHIFT, base + TCR); + + /* Put watchdog in pre-active state */ + wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) | + (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT); + davinci_writel(wdtcr, base + WDTCR); + + /* Put watchdog in active state */ + wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) | + (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT); + davinci_writel(wdtcr, base + WDTCR); + + /* + * Write an invalid value to the WDKEY field to trigger + * a watchdog reset. + */ + wdtcr = 0xDEADBEEF; + davinci_writel(wdtcr, base + WDTCR); } diff --git a/bsp/dm365/platform/dm365_timer.h b/bsp/dm365/platform/dm365_timer.h index 3bb1d761ed..93a0e3ef6b 100644 --- a/bsp/dm365/platform/dm365_timer.h +++ b/bsp/dm365/platform/dm365_timer.h @@ -4,57 +4,57 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ #ifndef __ASM_ARCH_TIME_H #define __ASM_ARCH_TIME_H /* Timer register offsets */ -#define PID12 0x0 -#define TIM12 0x10 -#define TIM34 0x14 -#define PRD12 0x18 -#define PRD34 0x1c -#define TCR 0x20 -#define TGCR 0x24 -#define WDTCR 0x28 -#define CMP12(n) (0x60 + ((n) << 2)) +#define PID12 0x0 +#define TIM12 0x10 +#define TIM34 0x14 +#define PRD12 0x18 +#define PRD34 0x1c +#define TCR 0x20 +#define TGCR 0x24 +#define WDTCR 0x28 +#define CMP12(n) (0x60 + ((n) << 2)) /* Timer register bitfields */ -#define ENAMODE12_SHIFT 6 -#define ENAMODE34_SHIFT 22 -#define TCR_ENAMODE_DISABLE 0x0 -#define TCR_ENAMODE_ONESHOT 0x1 -#define TCR_ENAMODE_PERIODIC 0x2 -#define TCR_ENAMODE_MASK 0x3 - -#define TGCR_TIMMODE_SHIFT 2 -#define TGCR_TIMMODE_64BIT_GP 0x0 -#define TGCR_TIMMODE_32BIT_UNCHAINED 0x1 -#define TGCR_TIMMODE_64BIT_WDOG 0x2 -#define TGCR_TIMMODE_32BIT_CHAINED 0x3 - -#define TGCR_TIM12RS_SHIFT 0 -#define TGCR_TIM34RS_SHIFT 1 -#define TGCR_RESET 0x0 -#define TGCR_UNRESET 0x1 -#define TGCR_RESET_MASK 0x3 - -#define WDTCR_WDEN_SHIFT 14 -#define WDTCR_WDEN_DISABLE 0x0 -#define WDTCR_WDEN_ENABLE 0x1 -#define WDTCR_WDKEY_SHIFT 16 -#define WDTCR_WDKEY_SEQ0 0xA5C6 -#define WDTCR_WDKEY_SEQ1 0xDA7E +#define ENAMODE12_SHIFT 6 +#define ENAMODE34_SHIFT 22 +#define TCR_ENAMODE_DISABLE 0x0 +#define TCR_ENAMODE_ONESHOT 0x1 +#define TCR_ENAMODE_PERIODIC 0x2 +#define TCR_ENAMODE_MASK 0x3 + +#define TGCR_TIMMODE_SHIFT 2 +#define TGCR_TIMMODE_64BIT_GP 0x0 +#define TGCR_TIMMODE_32BIT_UNCHAINED 0x1 +#define TGCR_TIMMODE_64BIT_WDOG 0x2 +#define TGCR_TIMMODE_32BIT_CHAINED 0x3 + +#define TGCR_TIM12RS_SHIFT 0 +#define TGCR_TIM34RS_SHIFT 1 +#define TGCR_RESET 0x0 +#define TGCR_UNRESET 0x1 +#define TGCR_RESET_MASK 0x3 + +#define WDTCR_WDEN_SHIFT 14 +#define WDTCR_WDEN_DISABLE 0x0 +#define WDTCR_WDEN_ENABLE 0x1 +#define WDTCR_WDKEY_SHIFT 16 +#define WDTCR_WDKEY_SEQ0 0xA5C6 +#define WDTCR_WDKEY_SEQ1 0xDA7E enum { - T0_BOT, - T0_TOP, - T1_BOT, - T1_TOP, - NUM_TIMERS + T0_BOT, + T0_TOP, + T1_BOT, + T1_TOP, + NUM_TIMERS }; #endif /* __ASM_ARCH_TIME_H__ */ diff --git a/bsp/dm365/platform/dm36x.h b/bsp/dm365/platform/dm36x.h index 1e7b4102be..2aa72a23ce 100644 --- a/bsp/dm365/platform/dm36x.h +++ b/bsp/dm365/platform/dm36x.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ #ifndef __DM36X_H__ @@ -29,43 +29,43 @@ extern "C" { /* * Base register addresses */ -#define DAVINCI_DMA_3PCC_BASE (0x01C00000) -#define DAVINCI_DMA_3PTC0_BASE (0x01C10000) -#define DAVINCI_DMA_3PTC1_BASE (0x01C10400) -#define DAVINCI_I2C_BASE (0x01C21000) -#define DAVINCI_TIMER0_BASE (0x01C21400) -#define DAVINCI_TIMER1_BASE (0x01C21800) -#define DAVINCI_WDOG_BASE (0x01C21C00) -#define DAVINCI_PWM0_BASE (0x01C22000) -#define DAVINCI_PWM1_BASE (0x01C22400) -#define DAVINCI_PWM2_BASE (0x01C22800) -#define DAVINCI_SYSTEM_MODULE_BASE (0x01C40000) -#define DAVINCI_PLL_CNTRL0_BASE (0x01C40800) -#define DAVINCI_PLL_CNTRL1_BASE (0x01C40C00) -#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01C41000) -#define DAVINCI_SYSTEM_DFT_BASE (0x01C42000) -#define DAVINCI_IEEE1394_BASE (0x01C60000) -#define DAVINCI_USB_OTG_BASE (0x01C64000) -#define DAVINCI_CFC_ATA_BASE (0x01C66000) -#define DAVINCI_SPI_BASE (0x01C66800) -#define DAVINCI_GPIO_BASE (0x01C67000) -#define DAVINCI_UHPI_BASE (0x01C67800) -#define DAVINCI_VPSS_REGS_BASE (0x01C70000) -#define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01C80000) -#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01C81000) -#define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01C82000) -#define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01C84000) -#define DAVINCI_IMCOP_BASE (0x01CC0000) -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x01E00000) -#define DAVINCI_VLYNQ_BASE (0x01E01000) -#define DAVINCI_MCBSP_BASE (0x01E02000) -#define DAVINCI_MMC_SD_BASE (0x01E10000) -#define DAVINCI_MS_BASE (0x01E20000) -#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000) -#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000) -#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000) -#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000) -#define DAVINCI_VLYNQ_REMOTE_BASE (0x0C000000) +#define DAVINCI_DMA_3PCC_BASE (0x01C00000) +#define DAVINCI_DMA_3PTC0_BASE (0x01C10000) +#define DAVINCI_DMA_3PTC1_BASE (0x01C10400) +#define DAVINCI_I2C_BASE (0x01C21000) +#define DAVINCI_TIMER0_BASE (0x01C21400) +#define DAVINCI_TIMER1_BASE (0x01C21800) +#define DAVINCI_WDOG_BASE (0x01C21C00) +#define DAVINCI_PWM0_BASE (0x01C22000) +#define DAVINCI_PWM1_BASE (0x01C22400) +#define DAVINCI_PWM2_BASE (0x01C22800) +#define DAVINCI_SYSTEM_MODULE_BASE (0x01C40000) +#define DAVINCI_PLL_CNTRL0_BASE (0x01C40800) +#define DAVINCI_PLL_CNTRL1_BASE (0x01C40C00) +#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01C41000) +#define DAVINCI_SYSTEM_DFT_BASE (0x01C42000) +#define DAVINCI_IEEE1394_BASE (0x01C60000) +#define DAVINCI_USB_OTG_BASE (0x01C64000) +#define DAVINCI_CFC_ATA_BASE (0x01C66000) +#define DAVINCI_SPI_BASE (0x01C66800) +#define DAVINCI_GPIO_BASE (0x01C67000) +#define DAVINCI_UHPI_BASE (0x01C67800) +#define DAVINCI_VPSS_REGS_BASE (0x01C70000) +#define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01C80000) +#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01C81000) +#define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01C82000) +#define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01C84000) +#define DAVINCI_IMCOP_BASE (0x01CC0000) +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x01E00000) +#define DAVINCI_VLYNQ_BASE (0x01E01000) +#define DAVINCI_MCBSP_BASE (0x01E02000) +#define DAVINCI_MMC_SD_BASE (0x01E10000) +#define DAVINCI_MS_BASE (0x01E20000) +#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000) +#define DAVINCI_VLYNQ_REMOTE_BASE (0x0C000000) /* @@ -77,14 +77,14 @@ extern "C" { * In case of only one VLYNQ IP, define only the * 'LOW_VLYNQ_CONTROL_BASE'. */ -#define LOW_VLYNQ_CONTROL_BASE DAVINCI_VLYNQ_BASE +#define LOW_VLYNQ_CONTROL_BASE DAVINCI_VLYNQ_BASE -#define DM365_EMAC_BASE (0x01D07000) -#define DM365_EMAC_CNTRL_OFFSET (0x0000) -#define DM365_EMAC_CNTRL_MOD_OFFSET (0x3000) -#define DM365_EMAC_CNTRL_RAM_OFFSET (0x1000) -#define DM365_EMAC_MDIO_OFFSET (0x4000) -#define DM365_EMAC_CNTRL_RAM_SIZE (0x2000) +#define DM365_EMAC_BASE (0x01D07000) +#define DM365_EMAC_CNTRL_OFFSET (0x0000) +#define DM365_EMAC_CNTRL_MOD_OFFSET (0x3000) +#define DM365_EMAC_CNTRL_RAM_OFFSET (0x1000) +#define DM365_EMAC_MDIO_OFFSET (0x4000) +#define DM365_EMAC_CNTRL_RAM_SIZE (0x2000) /* @@ -96,117 +96,117 @@ extern "C" { /* * System module registers */ -#define PINMUX0 (DAVINCI_SYSTEM_MODULE_BASE + 0x00) -#define PINMUX1 (DAVINCI_SYSTEM_MODULE_BASE + 0x04) -#define PINMUX2 (DAVINCI_SYSTEM_MODULE_BASE + 0x08) -#define PINMUX3 (DAVINCI_SYSTEM_MODULE_BASE + 0x0c) -#define PINMUX4 (DAVINCI_SYSTEM_MODULE_BASE + 0x10) +#define PINMUX0 (DAVINCI_SYSTEM_MODULE_BASE + 0x00) +#define PINMUX1 (DAVINCI_SYSTEM_MODULE_BASE + 0x04) +#define PINMUX2 (DAVINCI_SYSTEM_MODULE_BASE + 0x08) +#define PINMUX3 (DAVINCI_SYSTEM_MODULE_BASE + 0x0c) +#define PINMUX4 (DAVINCI_SYSTEM_MODULE_BASE + 0x10) -#define DM365_ARM_INTMUX (DAVINCI_SYSTEM_MODULE_BASE + 0x18) -#define DM365_EDMA_EVTMUX (DAVINCI_SYSTEM_MODULE_BASE + 0x1C) -#define DAVINCI_PUPDCTL1 (DAVINCI_SYSTEM_MODULE_BASE + 0x7C) +#define DM365_ARM_INTMUX (DAVINCI_SYSTEM_MODULE_BASE + 0x18) +#define DM365_EDMA_EVTMUX (DAVINCI_SYSTEM_MODULE_BASE + 0x1C) +#define DAVINCI_PUPDCTL1 (DAVINCI_SYSTEM_MODULE_BASE + 0x7C) -#define ASYNC_EMIF_REVID 0x00 -#define ASYNC_EMIF_AWCCR 0x04 -#define ASYNC_EMIF_A1CR 0x10 -#define ASYNC_EMIF_A2CR 0x14 -#define ASYNC_EMIF_A3CR 0x18 +#define ASYNC_EMIF_REVID 0x00 +#define ASYNC_EMIF_AWCCR 0x04 +#define ASYNC_EMIF_A1CR 0x10 +#define ASYNC_EMIF_A2CR 0x14 +#define ASYNC_EMIF_A3CR 0x18 /* * Base register addresses common across DM355 and DM365 */ -#define DM3XX_TIMER2_BASE (0x01C20800) -#define DM3XX_REALTIME_BASE (0x01C20C00) -#define DM3XX_PWM3_BASE (0x01C22C00) -#define DM3XX_SPI_BASE (0x01C66000) -#define DM3XX_SPI0_BASE DM3XX_SPI_BASE -#define DM3XX_SPI1_BASE (0x01C66800) -#define DM3XX_SPI2_BASE (0x01C67800) +#define DM3XX_TIMER2_BASE (0x01C20800) +#define DM3XX_REALTIME_BASE (0x01C20C00) +#define DM3XX_PWM3_BASE (0x01C22C00) +#define DM3XX_SPI_BASE (0x01C66000) +#define DM3XX_SPI0_BASE DM3XX_SPI_BASE +#define DM3XX_SPI1_BASE (0x01C66800) +#define DM3XX_SPI2_BASE (0x01C67800) /* * DM365 base register address */ -#define DM365_DMA_3PTC2_BASE (0x01C10800) -#define DM365_DMA_3PTC3_BASE (0x01C10C00) -#define DM365_TIMER3_BASE (0x01C23800) -#define DM365_ADCIF_BASE (0x01C23C00) -#define DM365_SPI3_BASE (0x01C68000) -#define DM365_SPI4_BASE (0x01C23000) -#define DM365_RTC_BASE (0x01C69000) -#define DM365_KEYSCAN_BASE (0x01C69400) -#define DM365_UHPI_BASE (0x01C69800) -#define DM365_IMCOP_BASE (0x01CA0000) -#define DM365_MMC_SD1_BASE (0x01D00000) -#define DM365_MCBSP_BASE (0x01D02000) -#define DM365_UART1_BASE (0x01D06000) -#define DM365_EMAC_CNTRL_BASE (0x01D07000) -#define DM365_EMAC_WRAP_RAM_BASE (0x01D08000) -#define DM365_EMAC_WRAP_CNTRL_BASE (0x01D0A000) -#define DM365_EMAC_MDIO_BASE (0x01D0B000) -#define DM365_VOICE_CODEC_BASE (0x01D0C000) -#define DM365_ASYNC_EMIF_CNTRL_BASE (0x01D10000) -#define DM365_MMC_SD0_BASE (0x01D11000) -#define DM365_MS_BASE (0x01D20000) -#define DM365_KALEIDO_BASE (0x01E00000) - -#define DAVINCI_UART0_BASE (0x01C20000) - -#define PSC_MDCTL_BASE (0x01c41a00) -#define PSC_MDSTAT_BASE (0x01c41800) -#define PSC_PTCMD (0x01c41120) -#define PSC_PTSTAT (0x01c41128) - -#define DM365_EINT_ENABLE0 0x01c48018 -#define DM365_EINT_ENABLE1 0x01c4801c - -#define davinci_readb(a) (*(volatile unsigned char *)(a)) -#define davinci_readw(a) (*(volatile unsigned short *)(a)) -#define davinci_readl(a) (*(volatile unsigned int *)(a)) - -#define davinci_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define davinci_writew(v,a) (*(volatile unsigned short *)(a) = (v)) -#define davinci_writel(v,a) (*(volatile unsigned int *)(a) = (v)) - -#define readb(a) davinci_readb(a) -#define readw(a) davinci_readw(a) -#define readl(a) davinci_readl(a) - -#define write(v,a) davinci_writeb(v,a) -#define writew(v,a) davinci_writew(v,a) -#define writel(v,a) davinci_writel(v,a) +#define DM365_DMA_3PTC2_BASE (0x01C10800) +#define DM365_DMA_3PTC3_BASE (0x01C10C00) +#define DM365_TIMER3_BASE (0x01C23800) +#define DM365_ADCIF_BASE (0x01C23C00) +#define DM365_SPI3_BASE (0x01C68000) +#define DM365_SPI4_BASE (0x01C23000) +#define DM365_RTC_BASE (0x01C69000) +#define DM365_KEYSCAN_BASE (0x01C69400) +#define DM365_UHPI_BASE (0x01C69800) +#define DM365_IMCOP_BASE (0x01CA0000) +#define DM365_MMC_SD1_BASE (0x01D00000) +#define DM365_MCBSP_BASE (0x01D02000) +#define DM365_UART1_BASE (0x01D06000) +#define DM365_EMAC_CNTRL_BASE (0x01D07000) +#define DM365_EMAC_WRAP_RAM_BASE (0x01D08000) +#define DM365_EMAC_WRAP_CNTRL_BASE (0x01D0A000) +#define DM365_EMAC_MDIO_BASE (0x01D0B000) +#define DM365_VOICE_CODEC_BASE (0x01D0C000) +#define DM365_ASYNC_EMIF_CNTRL_BASE (0x01D10000) +#define DM365_MMC_SD0_BASE (0x01D11000) +#define DM365_MS_BASE (0x01D20000) +#define DM365_KALEIDO_BASE (0x01E00000) + +#define DAVINCI_UART0_BASE (0x01C20000) + +#define PSC_MDCTL_BASE (0x01c41a00) +#define PSC_MDSTAT_BASE (0x01c41800) +#define PSC_PTCMD (0x01c41120) +#define PSC_PTSTAT (0x01c41128) + +#define DM365_EINT_ENABLE0 0x01c48018 +#define DM365_EINT_ENABLE1 0x01c4801c + +#define davinci_readb(a) (*(volatile unsigned char *)(a)) +#define davinci_readw(a) (*(volatile unsigned short *)(a)) +#define davinci_readl(a) (*(volatile unsigned int *)(a)) + +#define davinci_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define davinci_writew(v,a) (*(volatile unsigned short *)(a) = (v)) +#define davinci_writel(v,a) (*(volatile unsigned int *)(a) = (v)) + +#define readb(a) davinci_readb(a) +#define readw(a) davinci_readw(a) +#define readl(a) davinci_readl(a) + +#define write(v,a) davinci_writeb(v,a) +#define writew(v,a) davinci_writew(v,a) +#define writel(v,a) davinci_writel(v,a) /* define timer register struct*/ typedef struct timer_regs_s { - rt_uint32_t pid12; /* 0x0 */ - rt_uint32_t emumgt_clksped; /* 0x4 */ - rt_uint32_t gpint_en; /* 0x8 */ - rt_uint32_t gpdir_dat; /* 0xC */ - rt_uint32_t tim12; /* 0x10 */ - rt_uint32_t tim34; /* 0x14 */ - rt_uint32_t prd12; /* 0x18 */ - rt_uint32_t prd34; /* 0x1C */ - rt_uint32_t tcr; /* 0x20 */ - rt_uint32_t tgcr; /* 0x24 */ - rt_uint32_t wdtcr; /* 0x28 */ - rt_uint32_t tlgc; /* 0x2C */ - rt_uint32_t tlmr; /* 0x30 */ + rt_uint32_t pid12; /* 0x0 */ + rt_uint32_t emumgt_clksped; /* 0x4 */ + rt_uint32_t gpint_en; /* 0x8 */ + rt_uint32_t gpdir_dat; /* 0xC */ + rt_uint32_t tim12; /* 0x10 */ + rt_uint32_t tim34; /* 0x14 */ + rt_uint32_t prd12; /* 0x18 */ + rt_uint32_t prd34; /* 0x1C */ + rt_uint32_t tcr; /* 0x20 */ + rt_uint32_t tgcr; /* 0x24 */ + rt_uint32_t wdtcr; /* 0x28 */ + rt_uint32_t tlgc; /* 0x2C */ + rt_uint32_t tlmr; /* 0x30 */ } timer_regs_t; /*****************************/ /* CPU Mode */ /*****************************/ -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define ABORTMODE 0x17 -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define ABORTMODE 0x17 +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 struct rt_hw_register { diff --git a/bsp/dm365/platform/dma.c b/bsp/dm365/platform/dma.c index 4316d9739e..baaedf650a 100644 --- a/bsp/dm365/platform/dma.c +++ b/bsp/dm365/platform/dma.c @@ -4,96 +4,96 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ #include /* Offsets matching "struct edmacc_param" */ -#define PARM_OPT 0x00 -#define PARM_SRC 0x04 -#define PARM_A_B_CNT 0x08 -#define PARM_DST 0x0c -#define PARM_SRC_DST_BIDX 0x10 -#define PARM_LINK_BCNTRLD 0x14 -#define PARM_SRC_DST_CIDX 0x18 -#define PARM_CCNT 0x1c +#define PARM_OPT 0x00 +#define PARM_SRC 0x04 +#define PARM_A_B_CNT 0x08 +#define PARM_DST 0x0c +#define PARM_SRC_DST_BIDX 0x10 +#define PARM_LINK_BCNTRLD 0x14 +#define PARM_SRC_DST_CIDX 0x18 +#define PARM_CCNT 0x1c -#define PARM_SIZE 0x20 +#define PARM_SIZE 0x20 /* Offsets for EDMA CC global channel registers and their shadows */ -#define SH_ER 0x00 /* 64 bits */ -#define SH_ECR 0x08 /* 64 bits */ -#define SH_ESR 0x10 /* 64 bits */ -#define SH_CER 0x18 /* 64 bits */ -#define SH_EER 0x20 /* 64 bits */ -#define SH_EECR 0x28 /* 64 bits */ -#define SH_EESR 0x30 /* 64 bits */ -#define SH_SER 0x38 /* 64 bits */ -#define SH_SECR 0x40 /* 64 bits */ -#define SH_IER 0x50 /* 64 bits */ -#define SH_IECR 0x58 /* 64 bits */ -#define SH_IESR 0x60 /* 64 bits */ -#define SH_IPR 0x68 /* 64 bits */ -#define SH_ICR 0x70 /* 64 bits */ -#define SH_IEVAL 0x78 -#define SH_QER 0x80 -#define SH_QEER 0x84 -#define SH_QEECR 0x88 -#define SH_QEESR 0x8c -#define SH_QSER 0x90 -#define SH_QSECR 0x94 -#define SH_SIZE 0x200 +#define SH_ER 0x00 /* 64 bits */ +#define SH_ECR 0x08 /* 64 bits */ +#define SH_ESR 0x10 /* 64 bits */ +#define SH_CER 0x18 /* 64 bits */ +#define SH_EER 0x20 /* 64 bits */ +#define SH_EECR 0x28 /* 64 bits */ +#define SH_EESR 0x30 /* 64 bits */ +#define SH_SER 0x38 /* 64 bits */ +#define SH_SECR 0x40 /* 64 bits */ +#define SH_IER 0x50 /* 64 bits */ +#define SH_IECR 0x58 /* 64 bits */ +#define SH_IESR 0x60 /* 64 bits */ +#define SH_IPR 0x68 /* 64 bits */ +#define SH_ICR 0x70 /* 64 bits */ +#define SH_IEVAL 0x78 +#define SH_QER 0x80 +#define SH_QEER 0x84 +#define SH_QEECR 0x88 +#define SH_QEESR 0x8c +#define SH_QSER 0x90 +#define SH_QSECR 0x94 +#define SH_SIZE 0x200 /* Offsets for EDMA CC global registers */ -#define EDMA_REV 0x0000 -#define EDMA_CCCFG 0x0004 -#define EDMA_QCHMAP 0x0200 /* 8 registers */ -#define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */ -#define EDMA_QDMAQNUM 0x0260 -#define EDMA_QUETCMAP 0x0280 -#define EDMA_QUEPRI 0x0284 -#define EDMA_EMR 0x0300 /* 64 bits */ -#define EDMA_EMCR 0x0308 /* 64 bits */ -#define EDMA_QEMR 0x0310 -#define EDMA_QEMCR 0x0314 -#define EDMA_CCERR 0x0318 -#define EDMA_CCERRCLR 0x031c -#define EDMA_EEVAL 0x0320 -#define EDMA_DRAE 0x0340 /* 4 x 64 bits*/ -#define EDMA_QRAE 0x0380 /* 4 registers */ -#define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */ -#define EDMA_QSTAT 0x0600 /* 2 registers */ -#define EDMA_QWMTHRA 0x0620 -#define EDMA_QWMTHRB 0x0624 -#define EDMA_CCSTAT 0x0640 - -#define EDMA_M 0x1000 /* global channel registers */ -#define EDMA_ECR 0x1008 -#define EDMA_ECRH 0x100C -#define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */ -#define EDMA_PARM 0x4000 /* 128 param entries */ - -#define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5)) - -#define EDMA_DCHMAP 0x0100 /* 64 registers */ -#define CHMAP_EXIST BIT(24) +#define EDMA_REV 0x0000 +#define EDMA_CCCFG 0x0004 +#define EDMA_QCHMAP 0x0200 /* 8 registers */ +#define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */ +#define EDMA_QDMAQNUM 0x0260 +#define EDMA_QUETCMAP 0x0280 +#define EDMA_QUEPRI 0x0284 +#define EDMA_EMR 0x0300 /* 64 bits */ +#define EDMA_EMCR 0x0308 /* 64 bits */ +#define EDMA_QEMR 0x0310 +#define EDMA_QEMCR 0x0314 +#define EDMA_CCERR 0x0318 +#define EDMA_CCERRCLR 0x031c +#define EDMA_EEVAL 0x0320 +#define EDMA_DRAE 0x0340 /* 4 x 64 bits*/ +#define EDMA_QRAE 0x0380 /* 4 registers */ +#define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */ +#define EDMA_QSTAT 0x0600 /* 2 registers */ +#define EDMA_QWMTHRA 0x0620 +#define EDMA_QWMTHRB 0x0624 +#define EDMA_CCSTAT 0x0640 + +#define EDMA_M 0x1000 /* global channel registers */ +#define EDMA_ECR 0x1008 +#define EDMA_ECRH 0x100C +#define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */ +#define EDMA_PARM 0x4000 /* 128 param entries */ + +#define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5)) + +#define EDMA_DCHMAP 0x0100 /* 64 registers */ +#define CHMAP_EXIST BIT(24) #define EDMA_MAX_DMACH 64 #define EDMA_MAX_PARAMENTRY 512 -#define EDMA_CC0_BASE_REG 0x01c00000 -#define EDMA_TC0_BASE_REG 0x01c10000 -#define EDMA_TC1_BASE_REG 0x01c10400 -#define EDMA_TC2_BASE_REG 0x01c10800 -#define EDMA_TC3_BASE_REG 0x01c10c00 +#define EDMA_CC0_BASE_REG 0x01c00000 +#define EDMA_TC0_BASE_REG 0x01c10000 +#define EDMA_TC1_BASE_REG 0x01c10400 +#define EDMA_TC2_BASE_REG 0x01c10800 +#define EDMA_TC3_BASE_REG 0x01c10c00 -#define min_t(type, x, y) ({ \ - type __min1 = (x); \ - type __min2 = (y); \ - __min1 < __min2 ? __min1: __min2; }) +#define min_t(type, x, y) ({ \ + type __min1 = (x); \ + type __min2 = (y); \ + __min1 < __min2 ? __min1: __min2; }) @@ -103,130 +103,130 @@ static void volatile *edmacc_regs_base[EDMA_MAX_CC]; static inline unsigned int edma_read(unsigned ctlr, int offset) { - return (unsigned int)davinci_readl(edmacc_regs_base[ctlr] + offset); + return (unsigned int)davinci_readl(edmacc_regs_base[ctlr] + offset); } static inline void edma_write(unsigned ctlr, int offset, int val) { - davinci_writel(val, edmacc_regs_base[ctlr] + offset); + davinci_writel(val, edmacc_regs_base[ctlr] + offset); } static inline void edma_modify(unsigned ctlr, int offset, unsigned and, - unsigned or) + unsigned or) { - unsigned val = edma_read(ctlr, offset); - val &= and; - val |= or; - edma_write(ctlr, offset, val); + unsigned val = edma_read(ctlr, offset); + val &= and; + val |= or; + edma_write(ctlr, offset, val); } static inline void edma_and(unsigned ctlr, int offset, unsigned and) { - unsigned val = edma_read(ctlr, offset); - val &= and; - edma_write(ctlr, offset, val); + unsigned val = edma_read(ctlr, offset); + val &= and; + edma_write(ctlr, offset, val); } static inline void edma_or(unsigned ctlr, int offset, unsigned or) { - unsigned val = edma_read(ctlr, offset); - val |= or; - edma_write(ctlr, offset, val); + unsigned val = edma_read(ctlr, offset); + val |= or; + edma_write(ctlr, offset, val); } static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i) { - return edma_read(ctlr, offset + (i << 2)); + return edma_read(ctlr, offset + (i << 2)); } static inline void edma_write_array(unsigned ctlr, int offset, int i, - unsigned val) + unsigned val) { - edma_write(ctlr, offset + (i << 2), val); + edma_write(ctlr, offset + (i << 2), val); } static inline void edma_modify_array(unsigned ctlr, int offset, int i, - unsigned and, unsigned or) + unsigned and, unsigned or) { - edma_modify(ctlr, offset + (i << 2), and, or); + edma_modify(ctlr, offset + (i << 2), and, or); } static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or) { - edma_or(ctlr, offset + (i << 2), or); + edma_or(ctlr, offset + (i << 2), or); } static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j, - unsigned or) + unsigned or) { - edma_or(ctlr, offset + ((i*2 + j) << 2), or); + edma_or(ctlr, offset + ((i*2 + j) << 2), or); } static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j, - unsigned val) + unsigned val) { - edma_write(ctlr, offset + ((i*2 + j) << 2), val); + edma_write(ctlr, offset + ((i*2 + j) << 2), val); } static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset) { - return edma_read(ctlr, EDMA_SHADOW0 + offset); + return edma_read(ctlr, EDMA_SHADOW0 + offset); } static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset, - int i) + int i) { - return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2)); + return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2)); } static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val) { - edma_write(ctlr, EDMA_SHADOW0 + offset, val); + edma_write(ctlr, EDMA_SHADOW0 + offset, val); } static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i, - unsigned val) + unsigned val) { - edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val); + edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val); } static inline unsigned int edma_parm_read(unsigned ctlr, int offset, - int param_no) + int param_no) { - return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5)); + return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5)); } static inline void edma_parm_write(unsigned ctlr, int offset, int param_no, - unsigned val) + unsigned val) { - edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val); + edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val); } static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no, - unsigned and, unsigned or) + unsigned and, unsigned or) { - edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or); + edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or); } static inline void edma_parm_and(unsigned ctlr, int offset, int param_no, - unsigned and) + unsigned and) { - edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and); + edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and); } static inline void edma_parm_or(unsigned ctlr, int offset, int param_no, - unsigned or) + unsigned or) { - edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or); + edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or); } #if 0 static inline void set_bits(int offset, int len, unsigned long *p) { - for (; len > 0; len--) - set_bit(offset + (len - 1), p); + for (; len > 0; len--) + set_bit(offset + (len - 1), p); } static inline void clear_bits(int offset, int len, unsigned long *p) { - for (; len > 0; len--) - clear_bit(offset + (len - 1), p); + for (; len > 0; len--) + clear_bit(offset + (len - 1), p); } #endif /*****************************************************************************/ -#define BIT(nr) (1UL << (nr)) +#define BIT(nr) (1UL << (nr)) #define BITS_PER_LONG 32 -#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) -#define BIT_WORD(nr) ((nr) / BITS_PER_LONG) -#define BITS_PER_BYTE 8 +#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) +#define BIT_WORD(nr) ((nr) / BITS_PER_LONG) +#define BITS_PER_BYTE 8 #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) -#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long)) +#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long)) #define DECLARE_BITMAP(name,bits) \ - unsigned long name[BITS_TO_LONGS(bits)] + unsigned long name[BITS_TO_LONGS(bits)] /** * test_bit - Determine whether a bit is set @@ -235,44 +235,44 @@ static inline void clear_bits(int offset, int len, unsigned long *p) */ static inline int test_bit(int nr, const volatile unsigned long *addr) { - return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1))); + return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1))); } static inline void clear_bit(int nr, volatile unsigned long *addr) { - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - rt_base_t level; + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + rt_base_t level; - level = rt_hw_interrupt_disable(); - *p &= ~mask; - rt_hw_interrupt_enable(level); + level = rt_hw_interrupt_disable(); + *p &= ~mask; + rt_hw_interrupt_enable(level); } static inline int test_and_set_bit(int nr, volatile unsigned long *addr) { - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long old; - rt_base_t level; + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old; + rt_base_t level; - level = rt_hw_interrupt_disable(); - old = *p; - *p = old | mask; - rt_hw_interrupt_enable(level); + level = rt_hw_interrupt_disable(); + old = *p; + *p = old | mask; + rt_hw_interrupt_enable(level); - return (old & mask) != 0; + return (old & mask) != 0; } static inline void set_bit(int nr, volatile unsigned long *addr) { - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - rt_base_t level; + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + rt_base_t level; - level = rt_hw_interrupt_disable(); - *p |= mask; - rt_hw_interrupt_enable(level); + level = rt_hw_interrupt_disable(); + *p |= mask; + rt_hw_interrupt_enable(level); } /* @@ -286,45 +286,45 @@ extern int _find_next_bit_le(const unsigned long *p, int size, int offset); /* * These are the little endian, atomic definitions. */ -#define find_first_zero_bit(p,sz) _find_first_zero_bit_le(p,sz) -#define find_next_zero_bit(p,sz,off) _find_next_zero_bit_le(p,sz,off) -#define find_first_bit(p,sz) _find_first_bit_le(p,sz) -#define find_next_bit(p,sz,off) _find_next_bit_le(p,sz,off) +#define find_first_zero_bit(p,sz) _find_first_zero_bit_le(p,sz) +#define find_next_zero_bit(p,sz,off) _find_next_zero_bit_le(p,sz,off) +#define find_first_bit(p,sz) _find_first_bit_le(p,sz) +#define find_next_bit(p,sz,off) _find_next_bit_le(p,sz,off) /* actual number of DMA channels and slots on this silicon */ struct edma { - /* how many dma resources of each type */ - unsigned num_channels; - unsigned num_region; - unsigned num_slots; - unsigned num_tc; - unsigned num_cc; - enum dma_event_q default_queue; - - /* list of channels with no even trigger; terminated by "-1" */ - const rt_int8_t *noevent; - - /* The edma_inuse bit for each PaRAM slot is clear unless the - * channel is in use ... by ARM or DSP, for QDMA, or whatever. - */ - DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY); - - /* The edma_unused bit for each channel is clear unless - * it is not being used on this platform. It uses a bit - * of SOC-specific initialization code. - */ - DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH); - - unsigned irq_res_start; - unsigned irq_res_end; - - struct dma_interrupt_data { - void (*callback)(unsigned channel, unsigned short ch_status, - void *data); - void *data; - } intr_data[EDMA_MAX_DMACH]; + /* how many dma resources of each type */ + unsigned num_channels; + unsigned num_region; + unsigned num_slots; + unsigned num_tc; + unsigned num_cc; + enum dma_event_q default_queue; + + /* list of channels with no even trigger; terminated by "-1" */ + const rt_int8_t *noevent; + + /* The edma_inuse bit for each PaRAM slot is clear unless the + * channel is in use ... by ARM or DSP, for QDMA, or whatever. + */ + DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY); + + /* The edma_unused bit for each channel is clear unless + * it is not being used on this platform. It uses a bit + * of SOC-specific initialization code. + */ + DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH); + + unsigned irq_res_start; + unsigned irq_res_end; + + struct dma_interrupt_data { + void (*callback)(unsigned channel, unsigned short ch_status, + void *data); + void *data; + } intr_data[EDMA_MAX_DMACH]; }; static struct edma *edma_cc[EDMA_MAX_CC]; @@ -332,38 +332,38 @@ static int arch_num_cc; /* dummy param set used to (re)initialize parameter RAM slots */ static const struct edmacc_param dummy_paramset = { - .link_bcntrld = 0xffff, - .ccnt = 1, + .link_bcntrld = 0xffff, + .ccnt = 1, }; /*****************************************************************************/ static void map_dmach_queue(unsigned ctlr, unsigned ch_no, - enum dma_event_q queue_no) + enum dma_event_q queue_no) { - int bit = (ch_no & 0x7) * 4; + int bit = (ch_no & 0x7) * 4; - /* default to low priority queue */ - if (queue_no == EVENTQ_DEFAULT) - queue_no = edma_cc[ctlr]->default_queue; + /* default to low priority queue */ + if (queue_no == EVENTQ_DEFAULT) + queue_no = edma_cc[ctlr]->default_queue; - queue_no &= 7; - edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3), - ~(0x7 << bit), queue_no << bit); + queue_no &= 7; + edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3), + ~(0x7 << bit), queue_no << bit); } static void map_queue_tc(unsigned ctlr, int queue_no, int tc_no) { - int bit = queue_no * 4; - edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit)); + int bit = queue_no * 4; + edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit)); } static void assign_priority_to_queue(unsigned ctlr, int queue_no, - int priority) + int priority) { - int bit = queue_no * 4; - edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit), - ((priority & 0x7) << bit)); + int bit = queue_no * 4; + edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit), + ((priority & 0x7) << bit)); } /** @@ -379,45 +379,45 @@ static void assign_priority_to_queue(unsigned ctlr, int queue_no, */ static void map_dmach_param(unsigned ctlr) { - int i; - for (i = 0; i < EDMA_MAX_DMACH; i++) - edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5)); + int i; + for (i = 0; i < EDMA_MAX_DMACH; i++) + edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5)); } static inline void setup_dma_interrupt(unsigned lch, - void (*callback)(unsigned channel, rt_uint16_t ch_status, void *data), - void *data) + void (*callback)(unsigned channel, rt_uint16_t ch_status, void *data), + void *data) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(lch); - lch = EDMA_CHAN_SLOT(lch); + ctlr = EDMA_CTLR(lch); + lch = EDMA_CHAN_SLOT(lch); - if (!callback) - edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5, - BIT(lch & 0x1f)); + if (!callback) + edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5, + BIT(lch & 0x1f)); - edma_cc[ctlr]->intr_data[lch].callback = callback; - edma_cc[ctlr]->intr_data[lch].data = data; + edma_cc[ctlr]->intr_data[lch].callback = callback; + edma_cc[ctlr]->intr_data[lch].data = data; - if (callback) { - edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5, - BIT(lch & 0x1f)); - edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5, - BIT(lch & 0x1f)); - } + if (callback) { + edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5, + BIT(lch & 0x1f)); + edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5, + BIT(lch & 0x1f)); + } } static int irq2ctlr(int irq) { - if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end) - return 0; - else if (irq >= edma_cc[1]->irq_res_start && - irq <= edma_cc[1]->irq_res_end) - return 1; + if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end) + return 0; + else if (irq >= edma_cc[1]->irq_res_start && + irq <= edma_cc[1]->irq_res_end) + return 1; - return -1; + return -1; } /****************************************************************************** @@ -427,53 +427,53 @@ static int irq2ctlr(int irq) *****************************************************************************/ static void dma_irq_handler(int irq, void *data) { - int i; - int ctlr; - unsigned int cnt = 0; - - ctlr = irq2ctlr(irq); - if (ctlr < 0) - return ; - - edma_dbg("dma_irq_handler\n"); - - if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0) && - (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0)) - return ; - - while (1) { - int j; - if (edma_shadow0_read_array(ctlr, SH_IPR, 0) & - edma_shadow0_read_array(ctlr, SH_IER, 0)) - j = 0; - else if (edma_shadow0_read_array(ctlr, SH_IPR, 1) & - edma_shadow0_read_array(ctlr, SH_IER, 1)) - j = 1; - else - break; - edma_dbg("IPR%d %08x\n", j, - edma_shadow0_read_array(ctlr, SH_IPR, j)); - for (i = 0; i < 32; i++) { - int k = (j << 5) + i; - if ((edma_shadow0_read_array(ctlr, SH_IPR, j) & BIT(i)) - && (edma_shadow0_read_array(ctlr, - SH_IER, j) & BIT(i))) { - /* Clear the corresponding IPR bits */ - edma_shadow0_write_array(ctlr, SH_ICR, j, - BIT(i)); - if (edma_cc[ctlr]->intr_data[k].callback) - edma_cc[ctlr]->intr_data[k].callback( - k, DMA_COMPLETE, - edma_cc[ctlr]->intr_data[k]. - data); - } - } - cnt++; - if (cnt > 10) - break; - } - edma_shadow0_write(ctlr, SH_IEVAL, 1); - return ; + int i; + int ctlr; + unsigned int cnt = 0; + + ctlr = irq2ctlr(irq); + if (ctlr < 0) + return ; + + edma_dbg("dma_irq_handler\n"); + + if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0) && + (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0)) + return ; + + while (1) { + int j; + if (edma_shadow0_read_array(ctlr, SH_IPR, 0) & + edma_shadow0_read_array(ctlr, SH_IER, 0)) + j = 0; + else if (edma_shadow0_read_array(ctlr, SH_IPR, 1) & + edma_shadow0_read_array(ctlr, SH_IER, 1)) + j = 1; + else + break; + edma_dbg("IPR%d %08x\n", j, + edma_shadow0_read_array(ctlr, SH_IPR, j)); + for (i = 0; i < 32; i++) { + int k = (j << 5) + i; + if ((edma_shadow0_read_array(ctlr, SH_IPR, j) & BIT(i)) + && (edma_shadow0_read_array(ctlr, + SH_IER, j) & BIT(i))) { + /* Clear the corresponding IPR bits */ + edma_shadow0_write_array(ctlr, SH_ICR, j, + BIT(i)); + if (edma_cc[ctlr]->intr_data[k].callback) + edma_cc[ctlr]->intr_data[k].callback( + k, DMA_COMPLETE, + edma_cc[ctlr]->intr_data[k]. + data); + } + } + cnt++; + if (cnt > 10) + break; + } + edma_shadow0_write(ctlr, SH_IEVAL, 1); + return ; } /****************************************************************************** @@ -483,90 +483,90 @@ static void dma_irq_handler(int irq, void *data) *****************************************************************************/ static void dma_ccerr_handler(int irq, void *data) { - int i; - int ctlr; - unsigned int cnt = 0; - - ctlr = irq2ctlr(irq); - if (ctlr < 0) - return ; - - edma_dbg("dma_ccerr_handler\n"); - - if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) && - (edma_read_array(ctlr, EDMA_EMR, 1) == 0) && - (edma_read(ctlr, EDMA_QEMR) == 0) && - (edma_read(ctlr, EDMA_CCERR) == 0)) - return ; - - while (1) { - int j = -1; - if (edma_read_array(ctlr, EDMA_EMR, 0)) - j = 0; - else if (edma_read_array(ctlr, EDMA_EMR, 1)) - j = 1; - if (j >= 0) { - edma_dbg("EMR%d %08x\n", j, - edma_read_array(ctlr, EDMA_EMR, j)); - for (i = 0; i < 32; i++) { - int k = (j << 5) + i; - if (edma_read_array(ctlr, EDMA_EMR, j) & - BIT(i)) { - /* Clear the corresponding EMR bits */ - edma_write_array(ctlr, EDMA_EMCR, j, - BIT(i)); - /* Clear any SER */ - edma_shadow0_write_array(ctlr, SH_SECR, - j, BIT(i)); - if (edma_cc[ctlr]->intr_data[k]. - callback) { - edma_cc[ctlr]->intr_data[k]. - callback(k, - DMA_CC_ERROR, - edma_cc[ctlr]->intr_data - [k].data); - } - } - } - } else if (edma_read(ctlr, EDMA_QEMR)) { - edma_dbg("QEMR %02x\n", - edma_read(ctlr, EDMA_QEMR)); - for (i = 0; i < 8; i++) { - if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) { - /* Clear the corresponding IPR bits */ - edma_write(ctlr, EDMA_QEMCR, BIT(i)); - edma_shadow0_write(ctlr, SH_QSECR, - BIT(i)); - - /* NOTE: not reported!! */ - } - } - } else if (edma_read(ctlr, EDMA_CCERR)) { - edma_dbg("CCERR %08x\n", - edma_read(ctlr, EDMA_CCERR)); - /* FIXME: CCERR.BIT(16) ignored! much better - * to just write CCERRCLR with CCERR value... - */ - for (i = 0; i < 8; i++) { - if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) { - /* Clear the corresponding IPR bits */ - edma_write(ctlr, EDMA_CCERRCLR, BIT(i)); - - /* NOTE: not reported!! */ - } - } - } - if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) && - (edma_read_array(ctlr, EDMA_EMR, 1) == 0) && - (edma_read(ctlr, EDMA_QEMR) == 0) && - (edma_read(ctlr, EDMA_CCERR) == 0)) - break; - cnt++; - if (cnt > 10) - break; - } - edma_write(ctlr, EDMA_EEVAL, 1); - return ; + int i; + int ctlr; + unsigned int cnt = 0; + + ctlr = irq2ctlr(irq); + if (ctlr < 0) + return ; + + edma_dbg("dma_ccerr_handler\n"); + + if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) && + (edma_read_array(ctlr, EDMA_EMR, 1) == 0) && + (edma_read(ctlr, EDMA_QEMR) == 0) && + (edma_read(ctlr, EDMA_CCERR) == 0)) + return ; + + while (1) { + int j = -1; + if (edma_read_array(ctlr, EDMA_EMR, 0)) + j = 0; + else if (edma_read_array(ctlr, EDMA_EMR, 1)) + j = 1; + if (j >= 0) { + edma_dbg("EMR%d %08x\n", j, + edma_read_array(ctlr, EDMA_EMR, j)); + for (i = 0; i < 32; i++) { + int k = (j << 5) + i; + if (edma_read_array(ctlr, EDMA_EMR, j) & + BIT(i)) { + /* Clear the corresponding EMR bits */ + edma_write_array(ctlr, EDMA_EMCR, j, + BIT(i)); + /* Clear any SER */ + edma_shadow0_write_array(ctlr, SH_SECR, + j, BIT(i)); + if (edma_cc[ctlr]->intr_data[k]. + callback) { + edma_cc[ctlr]->intr_data[k]. + callback(k, + DMA_CC_ERROR, + edma_cc[ctlr]->intr_data + [k].data); + } + } + } + } else if (edma_read(ctlr, EDMA_QEMR)) { + edma_dbg("QEMR %02x\n", + edma_read(ctlr, EDMA_QEMR)); + for (i = 0; i < 8; i++) { + if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) { + /* Clear the corresponding IPR bits */ + edma_write(ctlr, EDMA_QEMCR, BIT(i)); + edma_shadow0_write(ctlr, SH_QSECR, + BIT(i)); + + /* NOTE: not reported!! */ + } + } + } else if (edma_read(ctlr, EDMA_CCERR)) { + edma_dbg("CCERR %08x\n", + edma_read(ctlr, EDMA_CCERR)); + /* FIXME: CCERR.BIT(16) ignored! much better + * to just write CCERRCLR with CCERR value... + */ + for (i = 0; i < 8; i++) { + if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) { + /* Clear the corresponding IPR bits */ + edma_write(ctlr, EDMA_CCERRCLR, BIT(i)); + + /* NOTE: not reported!! */ + } + } + } + if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) && + (edma_read_array(ctlr, EDMA_EMR, 1) == 0) && + (edma_read(ctlr, EDMA_QEMR) == 0) && + (edma_read(ctlr, EDMA_CCERR) == 0)) + break; + cnt++; + if (cnt > 10) + break; + } + edma_write(ctlr, EDMA_EEVAL, 1); + return ; } /****************************************************************************** @@ -575,92 +575,92 @@ static void dma_ccerr_handler(int irq, void *data) * *****************************************************************************/ -#define tc_errs_handled RT_FALSE/* disabled as long as they're NOPs */ +#define tc_errs_handled RT_FALSE/* disabled as long as they're NOPs */ static void dma_tc0err_handler(int irq, void *data) { - edma_dbg("dma_tc0err_handler\n"); - return ; + edma_dbg("dma_tc0err_handler\n"); + return ; } static void dma_tc1err_handler(int irq, void *data) { - edma_dbg("dma_tc1err_handler\n"); - return ; + edma_dbg("dma_tc1err_handler\n"); + return ; } static int reserve_contiguous_slots(int ctlr, unsigned int id, - unsigned int num_slots, - unsigned int start_slot) + unsigned int num_slots, + unsigned int start_slot) { - int i, j; - unsigned int count = num_slots; - int stop_slot = start_slot; - DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY); - - for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) { - j = EDMA_CHAN_SLOT(i); - if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) { - /* Record our current beginning slot */ - if (count == num_slots) - stop_slot = i; - - count--; - set_bit(j, tmp_inuse); - - if (count == 0) - break; - } else { - clear_bit(j, tmp_inuse); - - if (id == EDMA_CONT_PARAMS_FIXED_EXACT) { - stop_slot = i; - break; - } else { - count = num_slots; - } - } - } - - /* - * We have to clear any bits that we set - * if we run out parameter RAM slots, i.e we do find a set - * of contiguous parameter RAM slots but do not find the exact number - * requested as we may reach the total number of parameter RAM slots - */ - if (i == edma_cc[ctlr]->num_slots) - stop_slot = i; - - for (j = start_slot; j < stop_slot; j++) - if (test_bit(j, tmp_inuse)) - clear_bit(j, edma_cc[ctlr]->edma_inuse); - - if (count) - return -RT_EBUSY; - - for (j = i - num_slots + 1; j <= i; ++j) - rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(j)), - &dummy_paramset, PARM_SIZE); - - return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1); + int i, j; + unsigned int count = num_slots; + int stop_slot = start_slot; + DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY); + + for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) { + j = EDMA_CHAN_SLOT(i); + if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) { + /* Record our current beginning slot */ + if (count == num_slots) + stop_slot = i; + + count--; + set_bit(j, tmp_inuse); + + if (count == 0) + break; + } else { + clear_bit(j, tmp_inuse); + + if (id == EDMA_CONT_PARAMS_FIXED_EXACT) { + stop_slot = i; + break; + } else { + count = num_slots; + } + } + } + + /* + * We have to clear any bits that we set + * if we run out parameter RAM slots, i.e we do find a set + * of contiguous parameter RAM slots but do not find the exact number + * requested as we may reach the total number of parameter RAM slots + */ + if (i == edma_cc[ctlr]->num_slots) + stop_slot = i; + + for (j = start_slot; j < stop_slot; j++) + if (test_bit(j, tmp_inuse)) + clear_bit(j, edma_cc[ctlr]->edma_inuse); + + if (count) + return -RT_EBUSY; + + for (j = i - num_slots + 1; j <= i; ++j) + rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(j)), + &dummy_paramset, PARM_SIZE); + + return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1); } #if 0 static int prepare_unused_channel_list(struct device *dev, void *data) { - struct platform_device *pdev = to_platform_device(dev); - int i, ctlr; - - for (i = 0; i < pdev->num_resources; i++) { - if ((pdev->resource[i].flags & IORESOURCE_DMA) && - (int)pdev->resource[i].start >= 0) { - ctlr = EDMA_CTLR(pdev->resource[i].start); - clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start), - edma_cc[ctlr]->edma_unused); - } - } - - return 0; + struct platform_device *pdev = to_platform_device(dev); + int i, ctlr; + + for (i = 0; i < pdev->num_resources; i++) { + if ((pdev->resource[i].flags & IORESOURCE_DMA) && + (int)pdev->resource[i].start >= 0) { + ctlr = EDMA_CTLR(pdev->resource[i].start); + clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start), + edma_cc[ctlr]->edma_unused); + } + } + + return 0; } #endif @@ -676,8 +676,8 @@ static rt_bool_t unused_chan_list_done; * @callback: optional; to be issued on DMA completion or errors * @data: passed to callback * @eventq_no: an EVENTQ_* constant, used to choose which Transfer - * Controller (TC) executes requests using this channel. Use - * EVENTQ_DEFAULT unless you really need a high priority queue. + * Controller (TC) executes requests using this channel. Use + * EVENTQ_DEFAULT unless you really need a high priority queue. * * This allocates a DMA channel and its associated parameter RAM slot. * The parameter RAM is initialized to hold a dummy transfer. @@ -701,77 +701,77 @@ static rt_bool_t unused_chan_list_done; * Returns the number of the channel, else negative errno. */ int edma_alloc_channel(int channel, - void (*callback)(unsigned channel, rt_uint16_t ch_status, void *data), - void *data, - enum dma_event_q eventq_no) + void (*callback)(unsigned channel, rt_uint16_t ch_status, void *data), + void *data, + enum dma_event_q eventq_no) { - unsigned i, done = 0, ctlr = 0; - int ret = 0; + unsigned i, done = 0, ctlr = 0; + int ret = 0; #if 0 - if (!unused_chan_list_done) { - /* - * Scan all the platform devices to find out the EDMA channels - * used and clear them in the unused list, making the rest - * available for ARM usage. - */ - ret = bus_for_each_dev(&platform_bus_type, NULL, NULL, - prepare_unused_channel_list); - if (ret < 0) - return ret; - - unused_chan_list_done = true; - } + if (!unused_chan_list_done) { + /* + * Scan all the platform devices to find out the EDMA channels + * used and clear them in the unused list, making the rest + * available for ARM usage. + */ + ret = bus_for_each_dev(&platform_bus_type, NULL, NULL, + prepare_unused_channel_list); + if (ret < 0) + return ret; + + unused_chan_list_done = true; + } #endif - if (channel >= 0) { - ctlr = EDMA_CTLR(channel); - channel = EDMA_CHAN_SLOT(channel); - clear_bit(channel, edma_cc[ctlr]->edma_unused); - } - - if (channel < 0) { - for (i = 0; i < arch_num_cc; i++) { - channel = 0; - for (;;) { - channel = find_next_bit(edma_cc[i]->edma_unused, - edma_cc[i]->num_channels, - channel); - if (channel == edma_cc[i]->num_channels) - break; - if (!test_and_set_bit(channel, - edma_cc[i]->edma_inuse)) { - done = 1; - ctlr = i; - break; - } - channel++; - } - if (done) - break; - } - if (!done) - return -RT_ENOMEM; - } else if (channel >= edma_cc[ctlr]->num_channels) { - return -RT_ERROR; - } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) { - return -RT_EBUSY; - } - - /* ensure access through shadow region 0 */ - edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f)); - - /* ensure no events are pending */ - edma_stop(EDMA_CTLR_CHAN(ctlr, channel)); - rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(channel)), - &dummy_paramset, PARM_SIZE); - - if (callback) - setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel), - callback, data); - - map_dmach_queue(ctlr, channel, eventq_no); - - return EDMA_CTLR_CHAN(ctlr, channel); + if (channel >= 0) { + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); + clear_bit(channel, edma_cc[ctlr]->edma_unused); + } + + if (channel < 0) { + for (i = 0; i < arch_num_cc; i++) { + channel = 0; + for (;;) { + channel = find_next_bit(edma_cc[i]->edma_unused, + edma_cc[i]->num_channels, + channel); + if (channel == edma_cc[i]->num_channels) + break; + if (!test_and_set_bit(channel, + edma_cc[i]->edma_inuse)) { + done = 1; + ctlr = i; + break; + } + channel++; + } + if (done) + break; + } + if (!done) + return -RT_ENOMEM; + } else if (channel >= edma_cc[ctlr]->num_channels) { + return -RT_ERROR; + } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) { + return -RT_EBUSY; + } + + /* ensure access through shadow region 0 */ + edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f)); + + /* ensure no events are pending */ + edma_stop(EDMA_CTLR_CHAN(ctlr, channel)); + rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(channel)), + &dummy_paramset, PARM_SIZE); + + if (callback) + setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel), + callback, data); + + map_dmach_queue(ctlr, channel, eventq_no); + + return EDMA_CTLR_CHAN(ctlr, channel); } @@ -788,20 +788,20 @@ int edma_alloc_channel(int channel, */ void edma_free_channel(unsigned channel) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(channel); - channel = EDMA_CHAN_SLOT(channel); + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); - if (channel >= edma_cc[ctlr]->num_channels) - return; + if (channel >= edma_cc[ctlr]->num_channels) + return; - setup_dma_interrupt(channel, RT_NULL, RT_NULL); - /* REVISIT should probably take out of shadow region 0 */ + setup_dma_interrupt(channel, RT_NULL, RT_NULL); + /* REVISIT should probably take out of shadow region 0 */ - rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(channel)), - &dummy_paramset, PARM_SIZE); - clear_bit(channel, edma_cc[ctlr]->edma_inuse); + rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(channel)), + &dummy_paramset, PARM_SIZE); + clear_bit(channel, edma_cc[ctlr]->edma_inuse); } @@ -821,30 +821,30 @@ void edma_free_channel(unsigned channel) */ int edma_alloc_slot(unsigned ctlr, int slot) { - if (slot >= 0) - slot = EDMA_CHAN_SLOT(slot); - - if (slot < 0) { - slot = edma_cc[ctlr]->num_channels; - for (;;) { - slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse, - edma_cc[ctlr]->num_slots, slot); - if (slot == edma_cc[ctlr]->num_slots) - return -RT_ENOMEM; - if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) - break; - } - } else if (slot < edma_cc[ctlr]->num_channels || - slot >= edma_cc[ctlr]->num_slots) { - return -RT_ERROR; - } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) { - return -RT_EBUSY; - } - - rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot)), - &dummy_paramset, PARM_SIZE); - - return EDMA_CTLR_CHAN(ctlr, slot); + if (slot >= 0) + slot = EDMA_CHAN_SLOT(slot); + + if (slot < 0) { + slot = edma_cc[ctlr]->num_channels; + for (;;) { + slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse, + edma_cc[ctlr]->num_slots, slot); + if (slot == edma_cc[ctlr]->num_slots) + return -RT_ENOMEM; + if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) + break; + } + } else if (slot < edma_cc[ctlr]->num_channels || + slot >= edma_cc[ctlr]->num_slots) { + return -RT_ERROR; + } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) { + return -RT_EBUSY; + } + + rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot)), + &dummy_paramset, PARM_SIZE); + + return EDMA_CTLR_CHAN(ctlr, slot); } @@ -858,18 +858,18 @@ int edma_alloc_slot(unsigned ctlr, int slot) */ void edma_free_slot(unsigned slot) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); - if (slot < edma_cc[ctlr]->num_channels || - slot >= edma_cc[ctlr]->num_slots) - return; + if (slot < edma_cc[ctlr]->num_channels || + slot >= edma_cc[ctlr]->num_slots) + return; - rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot)), - &dummy_paramset, PARM_SIZE); - clear_bit(slot, edma_cc[ctlr]->edma_inuse); + rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot)), + &dummy_paramset, PARM_SIZE); + clear_bit(slot, edma_cc[ctlr]->edma_inuse); } @@ -901,35 +901,35 @@ void edma_free_slot(unsigned slot) */ int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count) { - /* - * The start slot requested should be greater than - * the number of channels and lesser than the total number - * of slots - */ - if ((id != EDMA_CONT_PARAMS_ANY) && - (slot < edma_cc[ctlr]->num_channels || - slot >= edma_cc[ctlr]->num_slots)) - return -RT_ERROR; - - /* - * The number of parameter RAM slots requested cannot be less than 1 - * and cannot be more than the number of slots minus the number of - * channels - */ - if (count < 1 || count > - (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels)) - return -RT_ERROR; - - switch (id) { - case EDMA_CONT_PARAMS_ANY: - return reserve_contiguous_slots(ctlr, id, count, - edma_cc[ctlr]->num_channels); - case EDMA_CONT_PARAMS_FIXED_EXACT: - case EDMA_CONT_PARAMS_FIXED_NOT_EXACT: - return reserve_contiguous_slots(ctlr, id, count, slot); - default: - return -RT_ERROR; - } + /* + * The start slot requested should be greater than + * the number of channels and lesser than the total number + * of slots + */ + if ((id != EDMA_CONT_PARAMS_ANY) && + (slot < edma_cc[ctlr]->num_channels || + slot >= edma_cc[ctlr]->num_slots)) + return -RT_ERROR; + + /* + * The number of parameter RAM slots requested cannot be less than 1 + * and cannot be more than the number of slots minus the number of + * channels + */ + if (count < 1 || count > + (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels)) + return -RT_ERROR; + + switch (id) { + case EDMA_CONT_PARAMS_ANY: + return reserve_contiguous_slots(ctlr, id, count, + edma_cc[ctlr]->num_channels); + case EDMA_CONT_PARAMS_FIXED_EXACT: + case EDMA_CONT_PARAMS_FIXED_NOT_EXACT: + return reserve_contiguous_slots(ctlr, id, count, slot); + default: + return -RT_ERROR; + } } @@ -949,27 +949,27 @@ int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count) */ int edma_free_cont_slots(unsigned slot, int count) { - unsigned ctlr, slot_to_free; - int i; + unsigned ctlr, slot_to_free; + int i; - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); - if (slot < edma_cc[ctlr]->num_channels || - slot >= edma_cc[ctlr]->num_slots || - count < 1) - return -RT_ERROR; + if (slot < edma_cc[ctlr]->num_channels || + slot >= edma_cc[ctlr]->num_slots || + count < 1) + return -RT_ERROR; - for (i = slot; i < slot + count; ++i) { - ctlr = EDMA_CTLR(i); - slot_to_free = EDMA_CHAN_SLOT(i); + for (i = slot; i < slot + count; ++i) { + ctlr = EDMA_CTLR(i); + slot_to_free = EDMA_CHAN_SLOT(i); - rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free)), - &dummy_paramset, PARM_SIZE); - clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse); - } + rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free)), + &dummy_paramset, PARM_SIZE); + clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse); + } - return 0; + return 0; } @@ -983,35 +983,35 @@ int edma_free_cont_slots(unsigned slot, int count) * @src_port: physical address of source (memory, controller FIFO, etc) * @addressMode: INCR, except in very rare cases * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the - * width to use when addressing the fifo (e.g. W8BIT, W32BIT) + * width to use when addressing the fifo (e.g. W8BIT, W32BIT) * * Note that the source address is modified during the DMA transfer * according to edma_set_src_index(). */ void edma_set_src(unsigned slot, rt_uint32_t src_port, - enum address_mode mode, enum fifo_width width) + enum address_mode mode, enum fifo_width width) { - unsigned ctlr; - - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); - - if (slot < edma_cc[ctlr]->num_slots) { - unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); - - if (mode) { - /* set SAM and program FWID */ - i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8)); - } else { - /* clear SAM */ - i &= ~SAM; - } - edma_parm_write(ctlr, PARM_OPT, slot, i); - - /* set the source port address - in source register of param structure */ - edma_parm_write(ctlr, PARM_SRC, slot, src_port); - } + unsigned ctlr; + + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); + + if (slot < edma_cc[ctlr]->num_slots) { + unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); + + if (mode) { + /* set SAM and program FWID */ + i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8)); + } else { + /* clear SAM */ + i &= ~SAM; + } + edma_parm_write(ctlr, PARM_OPT, slot, i); + + /* set the source port address + in source register of param structure */ + edma_parm_write(ctlr, PARM_SRC, slot, src_port); + } } @@ -1021,34 +1021,34 @@ void edma_set_src(unsigned slot, rt_uint32_t src_port, * @dest_port: physical address of destination (memory, controller FIFO, etc) * @addressMode: INCR, except in very rare cases * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the - * width to use when addressing the fifo (e.g. W8BIT, W32BIT) + * width to use when addressing the fifo (e.g. W8BIT, W32BIT) * * Note that the destination address is modified during the DMA transfer * according to edma_set_dest_index(). */ void edma_set_dest(unsigned slot, rt_uint32_t dest_port, - enum address_mode mode, enum fifo_width width) + enum address_mode mode, enum fifo_width width) { - unsigned ctlr; - - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); - - if (slot < edma_cc[ctlr]->num_slots) { - unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); - - if (mode) { - /* set DAM and program FWID */ - i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8)); - } else { - /* clear DAM */ - i &= ~DAM; - } - edma_parm_write(ctlr, PARM_OPT, slot, i); - /* set the destination port address - in dest register of param structure */ - edma_parm_write(ctlr, PARM_DST, slot, dest_port); - } + unsigned ctlr; + + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); + + if (slot < edma_cc[ctlr]->num_slots) { + unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); + + if (mode) { + /* set DAM and program FWID */ + i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8)); + } else { + /* clear DAM */ + i &= ~DAM; + } + edma_parm_write(ctlr, PARM_OPT, slot, i); + /* set the destination port address + in dest register of param structure */ + edma_parm_write(ctlr, PARM_DST, slot, dest_port); + } } @@ -1063,17 +1063,17 @@ void edma_set_dest(unsigned slot, rt_uint32_t dest_port, */ void edma_get_position(unsigned slot, rt_uint32_t *src, rt_uint32_t *dst) { - struct edmacc_param temp; - unsigned ctlr; + struct edmacc_param temp; + unsigned ctlr; - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); - edma_read_slot(EDMA_CTLR_CHAN(ctlr, slot), &temp); - if (src != RT_NULL) - *src = temp.src; - if (dst != RT_NULL) - *dst = temp.dst; + edma_read_slot(EDMA_CTLR_CHAN(ctlr, slot), &temp); + if (src != RT_NULL) + *src = temp.src; + if (dst != RT_NULL) + *dst = temp.dst; } @@ -1089,17 +1089,17 @@ void edma_get_position(unsigned slot, rt_uint32_t *src, rt_uint32_t *dst) */ void edma_set_src_index(unsigned slot, rt_int16_t src_bidx, rt_int16_t src_cidx) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); - if (slot < edma_cc[ctlr]->num_slots) { - edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, - 0xffff0000, src_bidx); - edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, - 0xffff0000, src_cidx); - } + if (slot < edma_cc[ctlr]->num_slots) { + edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, + 0xffff0000, src_bidx); + edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, + 0xffff0000, src_cidx); + } } @@ -1115,17 +1115,17 @@ void edma_set_src_index(unsigned slot, rt_int16_t src_bidx, rt_int16_t src_cidx) */ void edma_set_dest_index(unsigned slot, rt_int16_t dest_bidx, rt_int16_t dest_cidx) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); - if (slot < edma_cc[ctlr]->num_slots) { - edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, - 0x0000ffff, dest_bidx << 16); - edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, - 0x0000ffff, dest_cidx << 16); - } + if (slot < edma_cc[ctlr]->num_slots) { + edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, + 0x0000ffff, dest_bidx << 16); + edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, + 0x0000ffff, dest_cidx << 16); + } } @@ -1136,7 +1136,7 @@ void edma_set_dest_index(unsigned slot, rt_int16_t dest_bidx, rt_int16_t dest_ci * @bcnt: how many arrays per frame (at least one) * @ccnt: how many frames per block (at least one) * @bcnt_rld: used only for A-Synchronized transfers; this specifies - * the value to reload into bcnt when it decrements to zero + * the value to reload into bcnt when it decrements to zero * @sync_mode: ASYNC or ABSYNC * * See the EDMA3 documentation to understand how to configure and link @@ -1159,25 +1159,25 @@ void edma_set_dest_index(unsigned slot, rt_int16_t dest_bidx, rt_int16_t dest_ci * efficient burst modes to access memory. */ void edma_set_transfer_params(unsigned slot, - rt_uint16_t acnt, rt_uint16_t bcnt, rt_uint16_t ccnt, - rt_uint16_t bcnt_rld, enum sync_dimension sync_mode) + rt_uint16_t acnt, rt_uint16_t bcnt, rt_uint16_t ccnt, + rt_uint16_t bcnt_rld, enum sync_dimension sync_mode) { - unsigned ctlr; - - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); - - if (slot < edma_cc[ctlr]->num_slots) { - edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot, - 0x0000ffff, bcnt_rld << 16); - if (sync_mode == ASYNC) - edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM); - else - edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM); - /* Set the acount, bcount, ccount registers */ - edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt); - edma_parm_write(ctlr, PARM_CCNT, slot, ccnt); - } + unsigned ctlr; + + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); + + if (slot < edma_cc[ctlr]->num_slots) { + edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot, + 0x0000ffff, bcnt_rld << 16); + if (sync_mode == ASYNC) + edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM); + else + edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM); + /* Set the acount, bcount, ccount registers */ + edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt); + edma_parm_write(ctlr, PARM_CCNT, slot, ccnt); + } } @@ -1190,19 +1190,19 @@ void edma_set_transfer_params(unsigned slot, */ void edma_link(unsigned from, unsigned to) { - unsigned ctlr_from, ctlr_to; - - ctlr_from = EDMA_CTLR(from); - from = EDMA_CHAN_SLOT(from); - ctlr_to = EDMA_CTLR(to); - to = EDMA_CHAN_SLOT(to); - - if (from >= edma_cc[ctlr_from]->num_slots) - return; - if (to >= edma_cc[ctlr_to]->num_slots) - return; - edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000, - PARM_OFFSET(to)); + unsigned ctlr_from, ctlr_to; + + ctlr_from = EDMA_CTLR(from); + from = EDMA_CHAN_SLOT(from); + ctlr_to = EDMA_CTLR(to); + to = EDMA_CHAN_SLOT(to); + + if (from >= edma_cc[ctlr_from]->num_slots) + return; + if (to >= edma_cc[ctlr_to]->num_slots) + return; + edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000, + PARM_OFFSET(to)); } @@ -1215,14 +1215,14 @@ void edma_link(unsigned from, unsigned to) */ void edma_unlink(unsigned from) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(from); - from = EDMA_CHAN_SLOT(from); + ctlr = EDMA_CTLR(from); + from = EDMA_CHAN_SLOT(from); - if (from >= edma_cc[ctlr]->num_slots) - return; - edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff); + if (from >= edma_cc[ctlr]->num_slots) + return; + edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff); } @@ -1242,15 +1242,15 @@ void edma_unlink(unsigned from) */ void edma_write_slot(unsigned slot, const struct edmacc_param *param) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); - if (slot >= edma_cc[ctlr]->num_slots) - return; - rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot)), param, - PARM_SIZE); + if (slot >= edma_cc[ctlr]->num_slots) + return; + rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot)), param, + PARM_SIZE); } @@ -1264,15 +1264,15 @@ void edma_write_slot(unsigned slot, const struct edmacc_param *param) */ void edma_read_slot(unsigned slot, struct edmacc_param *param) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); - if (slot >= edma_cc[ctlr]->num_slots) - return; - rt_memcpy(param, (void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot)), - PARM_SIZE); + if (slot >= edma_cc[ctlr]->num_slots) + return; + rt_memcpy(param, (void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot)), + PARM_SIZE); } @@ -1289,16 +1289,16 @@ void edma_read_slot(unsigned slot, struct edmacc_param *param) */ void edma_pause(unsigned channel) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(channel); - channel = EDMA_CHAN_SLOT(channel); + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); - if (channel < edma_cc[ctlr]->num_channels) { - unsigned int mask = BIT(channel & 0x1f); + if (channel < edma_cc[ctlr]->num_channels) { + unsigned int mask = BIT(channel & 0x1f); - edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask); - } + edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask); + } } @@ -1310,16 +1310,16 @@ void edma_pause(unsigned channel) */ void edma_resume(unsigned channel) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(channel); - channel = EDMA_CHAN_SLOT(channel); + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); - if (channel < edma_cc[ctlr]->num_channels) { - unsigned int mask = BIT(channel & 0x1f); + if (channel < edma_cc[ctlr]->num_channels) { + unsigned int mask = BIT(channel & 0x1f); - edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask); - } + edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask); + } } @@ -1336,38 +1336,38 @@ void edma_resume(unsigned channel) */ int edma_start(unsigned channel) { - unsigned ctlr; - - ctlr = EDMA_CTLR(channel); - channel = EDMA_CHAN_SLOT(channel); - - if (channel < edma_cc[ctlr]->num_channels) { - int j = channel >> 5; - unsigned int mask = BIT(channel & 0x1f); - - /* EDMA channels without event association */ - if (test_bit(channel, edma_cc[ctlr]->edma_unused)) { - edma_dbg("EDMA: ESR%d %08x\n", j, - edma_shadow0_read_array(ctlr, SH_ESR, j)); - edma_shadow0_write_array(ctlr, SH_ESR, j, mask); - return 0; - } - - /* EDMA channel with event association */ - edma_dbg("EDMA: ER%d %08x\n", j, - edma_shadow0_read_array(ctlr, SH_ER, j)); - /* Clear any pending event or error */ - edma_write_array(ctlr, EDMA_ECR, j, mask); - edma_write_array(ctlr, EDMA_EMCR, j, mask); - /* Clear any SER */ - edma_shadow0_write_array(ctlr, SH_SECR, j, mask); - edma_shadow0_write_array(ctlr, SH_EESR, j, mask); - edma_dbg("EDMA: EER%d %08x\n", j, - edma_shadow0_read_array(ctlr, SH_EER, j)); - return 0; - } - - return -RT_ERROR; + unsigned ctlr; + + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); + + if (channel < edma_cc[ctlr]->num_channels) { + int j = channel >> 5; + unsigned int mask = BIT(channel & 0x1f); + + /* EDMA channels without event association */ + if (test_bit(channel, edma_cc[ctlr]->edma_unused)) { + edma_dbg("EDMA: ESR%d %08x\n", j, + edma_shadow0_read_array(ctlr, SH_ESR, j)); + edma_shadow0_write_array(ctlr, SH_ESR, j, mask); + return 0; + } + + /* EDMA channel with event association */ + edma_dbg("EDMA: ER%d %08x\n", j, + edma_shadow0_read_array(ctlr, SH_ER, j)); + /* Clear any pending event or error */ + edma_write_array(ctlr, EDMA_ECR, j, mask); + edma_write_array(ctlr, EDMA_EMCR, j, mask); + /* Clear any SER */ + edma_shadow0_write_array(ctlr, SH_SECR, j, mask); + edma_shadow0_write_array(ctlr, SH_EESR, j, mask); + edma_dbg("EDMA: EER%d %08x\n", j, + edma_shadow0_read_array(ctlr, SH_EER, j)); + return 0; + } + + return -RT_ERROR; } @@ -1382,27 +1382,27 @@ int edma_start(unsigned channel) */ void edma_stop(unsigned channel) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(channel); - channel = EDMA_CHAN_SLOT(channel); + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); - if (channel < edma_cc[ctlr]->num_channels) { - int j = channel >> 5; - unsigned int mask = BIT(channel & 0x1f); + if (channel < edma_cc[ctlr]->num_channels) { + int j = channel >> 5; + unsigned int mask = BIT(channel & 0x1f); - edma_shadow0_write_array(ctlr, SH_EECR, j, mask); - edma_shadow0_write_array(ctlr, SH_ECR, j, mask); - edma_shadow0_write_array(ctlr, SH_SECR, j, mask); - edma_write_array(ctlr, EDMA_EMCR, j, mask); + edma_shadow0_write_array(ctlr, SH_EECR, j, mask); + edma_shadow0_write_array(ctlr, SH_ECR, j, mask); + edma_shadow0_write_array(ctlr, SH_SECR, j, mask); + edma_write_array(ctlr, EDMA_EMCR, j, mask); - edma_dbg("EDMA: EER%d %08x\n", j, - edma_shadow0_read_array(ctlr, SH_EER, j)); + edma_dbg("EDMA: EER%d %08x\n", j, + edma_shadow0_read_array(ctlr, SH_EER, j)); - /* REVISIT: consider guarding against inappropriate event - * chaining by overwriting with dummy_paramset. - */ - } + /* REVISIT: consider guarding against inappropriate event + * chaining by overwriting with dummy_paramset. + */ + } } @@ -1421,45 +1421,45 @@ void edma_stop(unsigned channel) void edma_clean_channel(unsigned channel) { - unsigned ctlr; - - ctlr = EDMA_CTLR(channel); - channel = EDMA_CHAN_SLOT(channel); - - if (channel < edma_cc[ctlr]->num_channels) { - int j = (channel >> 5); - unsigned int mask = BIT(channel & 0x1f); - - edma_dbg("EDMA: EMR%d %08x\n", j, - edma_read_array(ctlr, EDMA_EMR, j)); - edma_shadow0_write_array(ctlr, SH_ECR, j, mask); - /* Clear the corresponding EMR bits */ - edma_write_array(ctlr, EDMA_EMCR, j, mask); - /* Clear any SER */ - edma_shadow0_write_array(ctlr, SH_SECR, j, mask); - edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0)); - } + unsigned ctlr; + + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); + + if (channel < edma_cc[ctlr]->num_channels) { + int j = (channel >> 5); + unsigned int mask = BIT(channel & 0x1f); + + edma_dbg("EDMA: EMR%d %08x\n", j, + edma_read_array(ctlr, EDMA_EMR, j)); + edma_shadow0_write_array(ctlr, SH_ECR, j, mask); + /* Clear the corresponding EMR bits */ + edma_write_array(ctlr, EDMA_EMCR, j, mask); + /* Clear any SER */ + edma_shadow0_write_array(ctlr, SH_SECR, j, mask); + edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0)); + } } /* * edma_clear_event - clear an outstanding event on the DMA channel * Arguments: - * channel - channel number + * channel - channel number */ void edma_clear_event(unsigned channel) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(channel); - channel = EDMA_CHAN_SLOT(channel); + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); - if (channel >= edma_cc[ctlr]->num_channels) - return; - if (channel < 32) - edma_write(ctlr, EDMA_ECR, BIT(channel)); - else - edma_write(ctlr, EDMA_ECRH, BIT(channel - 32)); + if (channel >= edma_cc[ctlr]->num_channels) + return; + if (channel < 32) + edma_write(ctlr, EDMA_ECR, BIT(channel)); + else + edma_write(ctlr, EDMA_ECRH, BIT(channel - 32)); } @@ -1467,112 +1467,112 @@ void edma_clear_event(unsigned channel) int edma_init(struct edma_soc_info **info) { - //struct edma_soc_info **info = pdev->dev.platform_data; - const rt_int8_t (*queue_priority_mapping)[2]; - const rt_int8_t (*queue_tc_mapping)[2]; - int i, j, off, ln, found = 0; - int status = -1; - const rt_int16_t (*rsv_chans)[2]; - const rt_int16_t (*rsv_slots)[2]; - int irq[EDMA_MAX_CC] = {0, 0}; - int err_irq[EDMA_MAX_CC] = {0, 0}; - - RT_ASSERT(info != RT_NULL); - - psc_change_state(DAVINCI_DM365_LPSC_TPCC, PSC_ENABLE); - psc_change_state(DAVINCI_DM365_LPSC_TPTC0, PSC_ENABLE); - psc_change_state(DAVINCI_DM365_LPSC_TPTC1, PSC_ENABLE); - psc_change_state(DAVINCI_DM365_LPSC_TPTC2, PSC_ENABLE); - psc_change_state(DAVINCI_DM365_LPSC_TPTC3, PSC_ENABLE); - - edmacc_regs_base[0] = (void *)EDMA_CC0_BASE_REG; - - edma_cc[0] = rt_malloc(sizeof(struct edma)); - if (!edma_cc[0]) { - status = -RT_ENOMEM; - goto fail1; - } - rt_memset(edma_cc[0], 0, sizeof(struct edma)); - - edma_cc[0]->num_channels = min_t(unsigned, info[0]->n_channel, - EDMA_MAX_DMACH); - edma_cc[0]->num_slots = min_t(unsigned, info[0]->n_slot, - EDMA_MAX_PARAMENTRY); - edma_cc[0]->num_cc = min_t(unsigned, info[0]->n_cc, - EDMA_MAX_CC); - - edma_cc[0]->default_queue = info[0]->default_queue; - if (!edma_cc[0]->default_queue) - edma_cc[0]->default_queue = EVENTQ_1; - - edma_dbg("DMA REG BASE ADDR=%p\n", - edmacc_regs_base[j]); - - for (i = 0; i < edma_cc[0]->num_slots; i++) - rt_memcpy((void *)(edmacc_regs_base[0] + PARM_OFFSET(i)), - &dummy_paramset, PARM_SIZE); - - /* Mark all channels as unused */ - rt_memset(edma_cc[0]->edma_unused, 0xff, - sizeof(edma_cc[0]->edma_unused)); - - edma_cc[0]->irq_res_start = IRQ_CCINT0; - rt_hw_interrupt_install(IRQ_CCINT0, dma_irq_handler, RT_NULL, "edma"); - rt_hw_interrupt_umask(IRQ_CCINT0); - - edma_cc[0]->irq_res_end = IRQ_CCERRINT; - rt_hw_interrupt_install(IRQ_CCERRINT, dma_ccerr_handler, RT_NULL, "edma_error"); - rt_hw_interrupt_umask(IRQ_CCERRINT); - - /* Everything lives on transfer controller 1 until otherwise - * specified. This way, long transfers on the low priority queue - * started by the codec engine will not cause audio defects. - */ - for (i = 0; i < edma_cc[0]->num_channels; i++) - map_dmach_queue(0, i, EVENTQ_1); - - queue_tc_mapping = info[0]->queue_tc_mapping; - queue_priority_mapping = info[0]->queue_priority_mapping; - - /* Event queue to TC mapping */ - for (i = 0; queue_tc_mapping[i][0] != -1; i++) - map_queue_tc(0, queue_tc_mapping[i][0], - queue_tc_mapping[i][1]); - - /* Event queue priority mapping */ - for (i = 0; queue_priority_mapping[i][0] != -1; i++) - assign_priority_to_queue(0, - queue_priority_mapping[i][0], - queue_priority_mapping[i][1]); - - /* Map the channel to param entry if channel mapping logic - * exist - */ - if (edma_read(0, EDMA_CCCFG) & CHMAP_EXIST) - map_dmach_param(0); - - for (i = 0; i < info[0]->n_region; i++) { - edma_write_array2(0, EDMA_DRAE, i, 0, 0x0); - edma_write_array2(0, EDMA_DRAE, i, 1, 0x0); - edma_write_array(0, EDMA_QRAE, i, 0x0); - } - arch_num_cc++; - - if (tc_errs_handled) { - rt_hw_interrupt_install(IRQ_TCERRINT0, dma_tc0err_handler, "edma_tc0"); - rt_hw_interrupt_umask(IRQ_TCERRINT0); - rt_hw_interrupt_install(IRQ_TCERRINT, dma_tc1err_handler, "edma_tc1"); - rt_hw_interrupt_umask(IRQ_TCERRINT); - } - - return 0; + //struct edma_soc_info **info = pdev->dev.platform_data; + const rt_int8_t (*queue_priority_mapping)[2]; + const rt_int8_t (*queue_tc_mapping)[2]; + int i, j, off, ln, found = 0; + int status = -1; + const rt_int16_t (*rsv_chans)[2]; + const rt_int16_t (*rsv_slots)[2]; + int irq[EDMA_MAX_CC] = {0, 0}; + int err_irq[EDMA_MAX_CC] = {0, 0}; + + RT_ASSERT(info != RT_NULL); + + psc_change_state(DAVINCI_DM365_LPSC_TPCC, PSC_ENABLE); + psc_change_state(DAVINCI_DM365_LPSC_TPTC0, PSC_ENABLE); + psc_change_state(DAVINCI_DM365_LPSC_TPTC1, PSC_ENABLE); + psc_change_state(DAVINCI_DM365_LPSC_TPTC2, PSC_ENABLE); + psc_change_state(DAVINCI_DM365_LPSC_TPTC3, PSC_ENABLE); + + edmacc_regs_base[0] = (void *)EDMA_CC0_BASE_REG; + + edma_cc[0] = rt_malloc(sizeof(struct edma)); + if (!edma_cc[0]) { + status = -RT_ENOMEM; + goto fail1; + } + rt_memset(edma_cc[0], 0, sizeof(struct edma)); + + edma_cc[0]->num_channels = min_t(unsigned, info[0]->n_channel, + EDMA_MAX_DMACH); + edma_cc[0]->num_slots = min_t(unsigned, info[0]->n_slot, + EDMA_MAX_PARAMENTRY); + edma_cc[0]->num_cc = min_t(unsigned, info[0]->n_cc, + EDMA_MAX_CC); + + edma_cc[0]->default_queue = info[0]->default_queue; + if (!edma_cc[0]->default_queue) + edma_cc[0]->default_queue = EVENTQ_1; + + edma_dbg("DMA REG BASE ADDR=%p\n", + edmacc_regs_base[j]); + + for (i = 0; i < edma_cc[0]->num_slots; i++) + rt_memcpy((void *)(edmacc_regs_base[0] + PARM_OFFSET(i)), + &dummy_paramset, PARM_SIZE); + + /* Mark all channels as unused */ + rt_memset(edma_cc[0]->edma_unused, 0xff, + sizeof(edma_cc[0]->edma_unused)); + + edma_cc[0]->irq_res_start = IRQ_CCINT0; + rt_hw_interrupt_install(IRQ_CCINT0, dma_irq_handler, RT_NULL, "edma"); + rt_hw_interrupt_umask(IRQ_CCINT0); + + edma_cc[0]->irq_res_end = IRQ_CCERRINT; + rt_hw_interrupt_install(IRQ_CCERRINT, dma_ccerr_handler, RT_NULL, "edma_error"); + rt_hw_interrupt_umask(IRQ_CCERRINT); + + /* Everything lives on transfer controller 1 until otherwise + * specified. This way, long transfers on the low priority queue + * started by the codec engine will not cause audio defects. + */ + for (i = 0; i < edma_cc[0]->num_channels; i++) + map_dmach_queue(0, i, EVENTQ_1); + + queue_tc_mapping = info[0]->queue_tc_mapping; + queue_priority_mapping = info[0]->queue_priority_mapping; + + /* Event queue to TC mapping */ + for (i = 0; queue_tc_mapping[i][0] != -1; i++) + map_queue_tc(0, queue_tc_mapping[i][0], + queue_tc_mapping[i][1]); + + /* Event queue priority mapping */ + for (i = 0; queue_priority_mapping[i][0] != -1; i++) + assign_priority_to_queue(0, + queue_priority_mapping[i][0], + queue_priority_mapping[i][1]); + + /* Map the channel to param entry if channel mapping logic + * exist + */ + if (edma_read(0, EDMA_CCCFG) & CHMAP_EXIST) + map_dmach_param(0); + + for (i = 0; i < info[0]->n_region; i++) { + edma_write_array2(0, EDMA_DRAE, i, 0, 0x0); + edma_write_array2(0, EDMA_DRAE, i, 1, 0x0); + edma_write_array(0, EDMA_QRAE, i, 0x0); + } + arch_num_cc++; + + if (tc_errs_handled) { + rt_hw_interrupt_install(IRQ_TCERRINT0, dma_tc0err_handler, "edma_tc0"); + rt_hw_interrupt_umask(IRQ_TCERRINT0); + rt_hw_interrupt_install(IRQ_TCERRINT, dma_tc1err_handler, "edma_tc1"); + rt_hw_interrupt_umask(IRQ_TCERRINT); + } + + return 0; fail: fail1: - rt_free(edma_cc[0]); + rt_free(edma_cc[0]); - return status; + return status; } diff --git a/bsp/dm365/platform/edma.h b/bsp/dm365/platform/edma.h index 4264767318..57007f5bbb 100644 --- a/bsp/dm365/platform/edma.h +++ b/bsp/dm365/platform/edma.h @@ -4,22 +4,22 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ /* * This EDMA3 programming framework exposes two basic kinds of resource: * - * Channel Triggers transfers, usually from a hardware event but - * also manually or by "chaining" from DMA completions. - * Each channel is coupled to a Parameter RAM (PaRAM) slot. + * Channel Triggers transfers, usually from a hardware event but + * also manually or by "chaining" from DMA completions. + * Each channel is coupled to a Parameter RAM (PaRAM) slot. * - * Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM - * "set"), source and destination addresses, a link to a - * next PaRAM slot (if any), options for the transfer, and - * instructions for updating those addresses. There are - * more than twice as many slots as event channels. + * Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM + * "set"), source and destination addresses, a link to a + * next PaRAM slot (if any), options for the transfer, and + * instructions for updating those addresses. There are + * more than twice as many slots as event channels. * * Each PaRAM set describes a sequence of transfers, either for one large * buffer or for several discontiguous smaller buffers. An EDMA transfer @@ -52,14 +52,14 @@ /* PaRAM slots are laid out like this */ struct edmacc_param { - unsigned int opt; - unsigned int src; - unsigned int a_b_cnt; - unsigned int dst; - unsigned int src_dst_bidx; - unsigned int link_bcntrld; - unsigned int src_dst_cidx; - unsigned int ccnt; + unsigned int opt; + unsigned int src; + unsigned int a_b_cnt; + unsigned int dst; + unsigned int src_dst_bidx; + unsigned int link_bcntrld; + unsigned int src_dst_cidx; + unsigned int ccnt; }; #define CCINT0_INTERRUPT 16 @@ -68,110 +68,110 @@ struct edmacc_param { #define TCERRINT1_INTERRUPT 19 /* fields in edmacc_param.opt */ -#define SAM BIT(0) -#define DAM BIT(1) -#define SYNCDIM BIT(2) -#define STATIC BIT(3) -#define EDMA_FWID (0x07 << 8) -#define TCCMODE BIT(11) -#define EDMA_TCC(t) ((t) << 12) -#define TCINTEN BIT(20) -#define ITCINTEN BIT(21) -#define TCCHEN BIT(22) -#define ITCCHEN BIT(23) +#define SAM BIT(0) +#define DAM BIT(1) +#define SYNCDIM BIT(2) +#define STATIC BIT(3) +#define EDMA_FWID (0x07 << 8) +#define TCCMODE BIT(11) +#define EDMA_TCC(t) ((t) << 12) +#define TCINTEN BIT(20) +#define ITCINTEN BIT(21) +#define TCCHEN BIT(22) +#define ITCCHEN BIT(23) #define TRWORD (0x7<<2) #define PAENTRY (0x1ff<<5) /* DM365 specific EDMA3 Events Information */ enum dm365_edma_ch { - DM365_DMA_TIMER3_TINT6, - DM365_DMA_TIMER3_TINT7, - DM365_DMA_MCBSP_TX = 2, - DM365_DMA_VCIF_TX = 2, - DM365_DMA_MCBSP_RX = 3, - DM365_DMA_VCIF_RX = 3, - DM365_DMA_VPSS_EVT1, - DM365_DMA_VPSS_EVT2, - DM365_DMA_VPSS_EVT3, - DM365_DMA_VPSS_EVT4, - DM365_DMA_TIMER2_TINT4, - DM365_DMA_TIMER2_TINT5, - DM365_DMA_SPI2XEVT, - DM365_DMA_SPI2REVT, - DM365_DMA_IMCOP_IMX0INT = 12, - DM365_DMA_KALEIDO_ARMINT = 12, - DM365_DMA_IMCOP_SEQINT, - DM365_DMA_SPI1XEVT, - DM365_DMA_SPI1REVT, - DM365_DMA_SPI0XEVT, - DM365_DMA_SPI0REVT, - DM365_DMA_URXEVT0 = 18, - DM365_DMA_SPI3XEVT = 18, - DM365_DMA_UTXEVT0 = 19, - DM365_DMA_SPI3REVT = 19, - DM365_DMA_URXEVT1, - DM365_DMA_UTXEVT1, - DM365_DMA_TIMER4_TINT8, - DM365_DMA_TIMER4_TINT9, - DM365_DMA_RTOINT, - DM365_DMA_GPIONT9, - DM365_DMA_MMC0RXEVT = 26, - DM365_DMA_MEMSTK_MSEVT = 26, - DM365_DMA_MMC0TXEVT, - DM365_DMA_I2C_ICREVT, - DM365_DMA_I2C_ICXEVT, - DM365_DMA_MMC1RXEVT, - DM365_DMA_MMC1TXEVT, - DM365_DMA_GPIOINT0, - DM365_DMA_GPIOINT1, - DM365_DMA_GPIOINT2, - DM365_DMA_GPIOINT3, - DM365_DMA_GPIOINT4, - DM365_DMA_GPIOINT5, - DM365_DMA_GPIOINT6, - DM365_DMA_GPIOINT7, - DM365_DMA_GPIOINT10 = 40, - DM365_DMA_EMAC_RXTHREESH = 40, - DM365_DMA_GPIOINT11 = 41, - DM365_DMA_EMAC_RXPULSE = 41, - DM365_DMA_GPIOINT12 = 42, - DM365_DMA_EMAC_TXPULSE = 42, - DM365_DMA_GPIOINT13 = 43, - DM365_DMA_EMAC_MISCPULSE = 43, - DM365_DMA_GPIOINT14 = 44, - DM365_DMA_SPI4XEVT = 44, - DM365_DMA_GPIOINT15 = 45, - DM365_DMA_SPI4REVT = 45, - DM365_DMA_ADC_ADINT, - DM365_DMA_GPIOINT8, - DM365_DMA_TIMER0_TINT0, - DM365_DMA_TIMER0_TINT1, - DM365_DMA_TIMER1_TINT2, - DM365_DMA_TIMER1_TINT3, - DM365_DMA_PWM0, - DM365_DMA_PWM1 = 53, - DM365_DMA_IMCOP_IMX1INT = 53, - DM365_DMA_PWM2 = 54, - DM365_DMA_IMCOP_NSFINT = 54, - DM365_DMA_PWM3 = 55, - DM365_DMA_KALEIDO6_CP_UNDEF = 55, - DM365_DMA_IMCOP_VLCDINT = 56, - DM365_DMA_KALEIDO5_CP_ECDCMP = 56, - DM365_DMA_IMCOP_BIMINT = 57, - DM365_DMA_KALEIDO8_CP_ME = 57, - DM365_DMA_IMCOP_DCTINT = 58, - DM365_DMA_KALEIDO1_CP_CALC = 58, - DM365_DMA_IMCOP_QIQINT = 59, - DM365_DMA_KALEIDO7_CP_IPE = 59, - DM365_DMA_IMCOP_BPSINT = 60, - DM365_DMA_KALEIDO2_CP_BS = 60, - DM365_DMA_IMCOP_VLCDERRINT = 61, - DM365_DMA_KALEIDO0_CP_LPF = 61, - DM365_DMA_IMCOP_RCNTINT = 62, - DM365_DMA_KALEIDO3_CP_MC = 62, - DM365_DMA_IMCOP_COPCINT = 63, - DM365_DMA_KALEIDO4_CP_ECDEND = 63, + DM365_DMA_TIMER3_TINT6, + DM365_DMA_TIMER3_TINT7, + DM365_DMA_MCBSP_TX = 2, + DM365_DMA_VCIF_TX = 2, + DM365_DMA_MCBSP_RX = 3, + DM365_DMA_VCIF_RX = 3, + DM365_DMA_VPSS_EVT1, + DM365_DMA_VPSS_EVT2, + DM365_DMA_VPSS_EVT3, + DM365_DMA_VPSS_EVT4, + DM365_DMA_TIMER2_TINT4, + DM365_DMA_TIMER2_TINT5, + DM365_DMA_SPI2XEVT, + DM365_DMA_SPI2REVT, + DM365_DMA_IMCOP_IMX0INT = 12, + DM365_DMA_KALEIDO_ARMINT = 12, + DM365_DMA_IMCOP_SEQINT, + DM365_DMA_SPI1XEVT, + DM365_DMA_SPI1REVT, + DM365_DMA_SPI0XEVT, + DM365_DMA_SPI0REVT, + DM365_DMA_URXEVT0 = 18, + DM365_DMA_SPI3XEVT = 18, + DM365_DMA_UTXEVT0 = 19, + DM365_DMA_SPI3REVT = 19, + DM365_DMA_URXEVT1, + DM365_DMA_UTXEVT1, + DM365_DMA_TIMER4_TINT8, + DM365_DMA_TIMER4_TINT9, + DM365_DMA_RTOINT, + DM365_DMA_GPIONT9, + DM365_DMA_MMC0RXEVT = 26, + DM365_DMA_MEMSTK_MSEVT = 26, + DM365_DMA_MMC0TXEVT, + DM365_DMA_I2C_ICREVT, + DM365_DMA_I2C_ICXEVT, + DM365_DMA_MMC1RXEVT, + DM365_DMA_MMC1TXEVT, + DM365_DMA_GPIOINT0, + DM365_DMA_GPIOINT1, + DM365_DMA_GPIOINT2, + DM365_DMA_GPIOINT3, + DM365_DMA_GPIOINT4, + DM365_DMA_GPIOINT5, + DM365_DMA_GPIOINT6, + DM365_DMA_GPIOINT7, + DM365_DMA_GPIOINT10 = 40, + DM365_DMA_EMAC_RXTHREESH = 40, + DM365_DMA_GPIOINT11 = 41, + DM365_DMA_EMAC_RXPULSE = 41, + DM365_DMA_GPIOINT12 = 42, + DM365_DMA_EMAC_TXPULSE = 42, + DM365_DMA_GPIOINT13 = 43, + DM365_DMA_EMAC_MISCPULSE = 43, + DM365_DMA_GPIOINT14 = 44, + DM365_DMA_SPI4XEVT = 44, + DM365_DMA_GPIOINT15 = 45, + DM365_DMA_SPI4REVT = 45, + DM365_DMA_ADC_ADINT, + DM365_DMA_GPIOINT8, + DM365_DMA_TIMER0_TINT0, + DM365_DMA_TIMER0_TINT1, + DM365_DMA_TIMER1_TINT2, + DM365_DMA_TIMER1_TINT3, + DM365_DMA_PWM0, + DM365_DMA_PWM1 = 53, + DM365_DMA_IMCOP_IMX1INT = 53, + DM365_DMA_PWM2 = 54, + DM365_DMA_IMCOP_NSFINT = 54, + DM365_DMA_PWM3 = 55, + DM365_DMA_KALEIDO6_CP_UNDEF = 55, + DM365_DMA_IMCOP_VLCDINT = 56, + DM365_DMA_KALEIDO5_CP_ECDCMP = 56, + DM365_DMA_IMCOP_BIMINT = 57, + DM365_DMA_KALEIDO8_CP_ME = 57, + DM365_DMA_IMCOP_DCTINT = 58, + DM365_DMA_KALEIDO1_CP_CALC = 58, + DM365_DMA_IMCOP_QIQINT = 59, + DM365_DMA_KALEIDO7_CP_IPE = 59, + DM365_DMA_IMCOP_BPSINT = 60, + DM365_DMA_KALEIDO2_CP_BS = 60, + DM365_DMA_IMCOP_VLCDERRINT = 61, + DM365_DMA_KALEIDO0_CP_LPF = 61, + DM365_DMA_IMCOP_RCNTINT = 62, + DM365_DMA_KALEIDO3_CP_MC = 62, + DM365_DMA_IMCOP_COPCINT = 63, + DM365_DMA_KALEIDO4_CP_ECDEND = 63, }; /* end DM365 specific info */ @@ -183,48 +183,48 @@ enum dm365_edma_ch { #define DMA_TC2_ERROR 4 enum address_mode { - INCR = 0, - FIFO = 1 + INCR = 0, + FIFO = 1 }; enum fifo_width { - W8BIT = 0, - W16BIT = 1, - W32BIT = 2, - W64BIT = 3, - W128BIT = 4, - W256BIT = 5 + W8BIT = 0, + W16BIT = 1, + W32BIT = 2, + W64BIT = 3, + W128BIT = 4, + W256BIT = 5 }; enum dma_event_q { - EVENTQ_0 = 0, - EVENTQ_1 = 1, - EVENTQ_2 = 2, - EVENTQ_3 = 3, - EVENTQ_DEFAULT = -1 + EVENTQ_0 = 0, + EVENTQ_1 = 1, + EVENTQ_2 = 2, + EVENTQ_3 = 3, + EVENTQ_DEFAULT = -1 }; enum sync_dimension { - ASYNC = 0, - ABSYNC = 1 + ASYNC = 0, + ABSYNC = 1 }; -#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan)) -#define EDMA_CTLR(i) ((i) >> 16) -#define EDMA_CHAN_SLOT(i) ((i) & 0xffff) +#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan)) +#define EDMA_CTLR(i) ((i) >> 16) +#define EDMA_CHAN_SLOT(i) ((i) & 0xffff) -#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */ -#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */ -#define EDMA_CONT_PARAMS_ANY 1001 -#define EDMA_CONT_PARAMS_FIXED_EXACT 1002 +#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */ +#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */ +#define EDMA_CONT_PARAMS_ANY 1001 +#define EDMA_CONT_PARAMS_FIXED_EXACT 1002 #define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003 #define EDMA_MAX_CC 2 /* alloc/free DMA channels and their dedicated parameter RAM slots */ int edma_alloc_channel(int channel, - void (*callback)(unsigned channel, rt_uint16_t ch_status, void *data), - void *data, enum dma_event_q); + void (*callback)(unsigned channel, rt_uint16_t ch_status, void *data), + void *data, enum dma_event_q); void edma_free_channel(unsigned channel); /* alloc/free parameter RAM slots */ @@ -237,14 +237,14 @@ int edma_free_cont_slots(unsigned slot, int count); /* calls that operate on part of a parameter RAM slot */ void edma_set_src(unsigned slot, rt_uint32_t src_port, - enum address_mode mode, enum fifo_width); + enum address_mode mode, enum fifo_width); void edma_set_dest(unsigned slot, rt_uint32_t dest_port, - enum address_mode mode, enum fifo_width); + enum address_mode mode, enum fifo_width); void edma_get_position(unsigned slot, rt_uint32_t *src, rt_uint32_t *dst); void edma_set_src_index(unsigned slot, rt_int16_t src_bidx, rt_int16_t src_cidx); void edma_set_dest_index(unsigned slot, rt_int16_t dest_bidx, rt_int16_t dest_cidx); void edma_set_transfer_params(unsigned slot, rt_uint16_t acnt, rt_uint16_t bcnt, rt_uint16_t ccnt, - rt_uint16_t bcnt_rld, enum sync_dimension sync_mode); + rt_uint16_t bcnt_rld, enum sync_dimension sync_mode); void edma_link(unsigned from, unsigned to); void edma_unlink(unsigned from); @@ -263,26 +263,26 @@ void edma_resume(unsigned channel); struct edma_rsv_info { - const rt_int16_t (*rsv_chans)[2]; - const rt_int16_t (*rsv_slots)[2]; + const rt_int16_t (*rsv_chans)[2]; + const rt_int16_t (*rsv_slots)[2]; }; /* platform_data for EDMA driver */ struct edma_soc_info { - /* how many dma resources of each type */ - unsigned n_channel; - unsigned n_region; - unsigned n_slot; - unsigned n_tc; - unsigned n_cc; - enum dma_event_q default_queue; + /* how many dma resources of each type */ + unsigned n_channel; + unsigned n_region; + unsigned n_slot; + unsigned n_tc; + unsigned n_cc; + enum dma_event_q default_queue; - /* Resource reservation for other cores */ - struct edma_rsv_info *rsv; + /* Resource reservation for other cores */ + struct edma_rsv_info *rsv; - const rt_int8_t (*queue_tc_mapping)[2]; - const rt_int8_t (*queue_priority_mapping)[2]; + const rt_int8_t (*queue_tc_mapping)[2]; + const rt_int8_t (*queue_priority_mapping)[2]; }; int edma_init(struct edma_soc_info **info); diff --git a/bsp/dm365/platform/interrupt.c b/bsp/dm365/platform/interrupt.c index 72171990d0..6334072bcd 100644 --- a/bsp/dm365/platform/interrupt.c +++ b/bsp/dm365/platform/interrupt.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ @@ -13,7 +13,7 @@ #include #include "dm36x.h" -#define MAX_HANDLERS 64 +#define MAX_HANDLERS 64 extern rt_uint32_t rt_interrupt_nest; @@ -23,95 +23,95 @@ struct rt_irq_desc irq_desc[MAX_HANDLERS]; rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; rt_uint32_t rt_thread_switch_interrupt_flag; -#define IRQ_BIT(irq) ((irq) & 0x1f) +#define IRQ_BIT(irq) ((irq) & 0x1f) -#define FIQ_REG0_OFFSET 0x0000 -#define FIQ_REG1_OFFSET 0x0004 -#define IRQ_REG0_OFFSET 0x0008 -#define IRQ_REG1_OFFSET 0x000C -#define IRQ_ENT_REG0_OFFSET 0x0018 -#define IRQ_ENT_REG1_OFFSET 0x001C -#define IRQ_INCTL_REG_OFFSET 0x0020 -#define IRQ_EABASE_REG_OFFSET 0x0024 -#define IRQ_INTPRI0_REG_OFFSET 0x0030 -#define IRQ_INTPRI7_REG_OFFSET 0x004C +#define FIQ_REG0_OFFSET 0x0000 +#define FIQ_REG1_OFFSET 0x0004 +#define IRQ_REG0_OFFSET 0x0008 +#define IRQ_REG1_OFFSET 0x000C +#define IRQ_ENT_REG0_OFFSET 0x0018 +#define IRQ_ENT_REG1_OFFSET 0x001C +#define IRQ_INCTL_REG_OFFSET 0x0020 +#define IRQ_EABASE_REG_OFFSET 0x0024 +#define IRQ_INTPRI0_REG_OFFSET 0x0030 +#define IRQ_INTPRI7_REG_OFFSET 0x004C /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ static const rt_uint8_t dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = { - [IRQ_DM3XX_VPSSINT0] = 2, - [IRQ_DM3XX_VPSSINT1] = 6, - [IRQ_DM3XX_VPSSINT2] = 6, - [IRQ_DM3XX_VPSSINT3] = 6, - [IRQ_DM3XX_VPSSINT4] = 6, - [IRQ_DM3XX_VPSSINT5] = 6, - [IRQ_DM3XX_VPSSINT6] = 6, - [IRQ_DM3XX_VPSSINT7] = 7, - [IRQ_DM3XX_VPSSINT8] = 6, - [IRQ_ASQINT] = 6, - [IRQ_DM365_IMXINT0] = 6, - [IRQ_DM3XX_IMCOPINT] = 6, - [IRQ_USBINT] = 4, - [IRQ_DM3XX_RTOINT] = 4, - [IRQ_DM3XX_TINT5] = 7, - [IRQ_DM3XX_TINT6] = 7, - [IRQ_CCINT0] = 5, /* dma */ - [IRQ_DM3XX_SPINT1_0] = 5, /* dma */ - [IRQ_DM3XX_SPINT1_1] = 5, /* dma */ - [IRQ_DM3XX_SPINT2_0] = 5, /* dma */ - [IRQ_DM365_PSCINT] = 7, - [IRQ_DM3XX_SPINT2_1] = 7, - [IRQ_DM3XX_TINT7] = 4, - [IRQ_DM3XX_SDIOINT0] = 7, - [IRQ_DM365_MBXINT] = 7, - [IRQ_DM365_MBRINT] = 7, - [IRQ_DM3XX_MMCINT0] = 7, - [IRQ_DM3XX_MMCINT1] = 7, - [IRQ_DM3XX_PWMINT3] = 7, - [IRQ_DM365_DDRINT] = 7, - [IRQ_DM365_AEMIFINT] = 7, - [IRQ_DM3XX_SDIOINT1] = 4, - [IRQ_DM365_TINT0] = 2, /* clockevent */ - [IRQ_DM365_TINT1] = 2, /* clocksource */ - [IRQ_DM365_TINT2] = 7, /* DSP timer */ - [IRQ_DM365_TINT3] = 7, /* system tick */ - [IRQ_PWMINT0] = 7, - [IRQ_PWMINT1] = 7, - [IRQ_DM365_PWMINT2] = 7, - [IRQ_DM365_IICINT] = 3, - [IRQ_UARTINT0] = 3, - [IRQ_UARTINT1] = 3, - [IRQ_DM3XX_SPINT0_0] = 3, - [IRQ_DM3XX_SPINT0_1] = 3, - [IRQ_DM3XX_GPIO0] = 3, - [IRQ_DM3XX_GPIO1] = 7, - [IRQ_DM3XX_GPIO2] = 4, - [IRQ_DM3XX_GPIO3] = 4, - [IRQ_DM3XX_GPIO4] = 7, - [IRQ_DM3XX_GPIO5] = 7, - [IRQ_DM3XX_GPIO6] = 7, - [IRQ_DM3XX_GPIO7] = 7, - [IRQ_DM3XX_GPIO8] = 7, - [IRQ_DM3XX_GPIO9] = 7, - [IRQ_DM365_GPIO10] = 7, - [IRQ_DM365_GPIO11] = 7, - [IRQ_DM365_GPIO12] = 7, - [IRQ_DM365_GPIO13] = 7, - [IRQ_DM365_GPIO14] = 7, - [IRQ_DM365_GPIO15] = 7, - [IRQ_DM365_KEYINT] = 7, - [IRQ_DM365_COMMTX] = 7, - [IRQ_DM365_COMMRX] = 7, - [IRQ_EMUINT] = 7, + [IRQ_DM3XX_VPSSINT0] = 2, + [IRQ_DM3XX_VPSSINT1] = 6, + [IRQ_DM3XX_VPSSINT2] = 6, + [IRQ_DM3XX_VPSSINT3] = 6, + [IRQ_DM3XX_VPSSINT4] = 6, + [IRQ_DM3XX_VPSSINT5] = 6, + [IRQ_DM3XX_VPSSINT6] = 6, + [IRQ_DM3XX_VPSSINT7] = 7, + [IRQ_DM3XX_VPSSINT8] = 6, + [IRQ_ASQINT] = 6, + [IRQ_DM365_IMXINT0] = 6, + [IRQ_DM3XX_IMCOPINT] = 6, + [IRQ_USBINT] = 4, + [IRQ_DM3XX_RTOINT] = 4, + [IRQ_DM3XX_TINT5] = 7, + [IRQ_DM3XX_TINT6] = 7, + [IRQ_CCINT0] = 5, /* dma */ + [IRQ_DM3XX_SPINT1_0] = 5, /* dma */ + [IRQ_DM3XX_SPINT1_1] = 5, /* dma */ + [IRQ_DM3XX_SPINT2_0] = 5, /* dma */ + [IRQ_DM365_PSCINT] = 7, + [IRQ_DM3XX_SPINT2_1] = 7, + [IRQ_DM3XX_TINT7] = 4, + [IRQ_DM3XX_SDIOINT0] = 7, + [IRQ_DM365_MBXINT] = 7, + [IRQ_DM365_MBRINT] = 7, + [IRQ_DM3XX_MMCINT0] = 7, + [IRQ_DM3XX_MMCINT1] = 7, + [IRQ_DM3XX_PWMINT3] = 7, + [IRQ_DM365_DDRINT] = 7, + [IRQ_DM365_AEMIFINT] = 7, + [IRQ_DM3XX_SDIOINT1] = 4, + [IRQ_DM365_TINT0] = 2, /* clockevent */ + [IRQ_DM365_TINT1] = 2, /* clocksource */ + [IRQ_DM365_TINT2] = 7, /* DSP timer */ + [IRQ_DM365_TINT3] = 7, /* system tick */ + [IRQ_PWMINT0] = 7, + [IRQ_PWMINT1] = 7, + [IRQ_DM365_PWMINT2] = 7, + [IRQ_DM365_IICINT] = 3, + [IRQ_UARTINT0] = 3, + [IRQ_UARTINT1] = 3, + [IRQ_DM3XX_SPINT0_0] = 3, + [IRQ_DM3XX_SPINT0_1] = 3, + [IRQ_DM3XX_GPIO0] = 3, + [IRQ_DM3XX_GPIO1] = 7, + [IRQ_DM3XX_GPIO2] = 4, + [IRQ_DM3XX_GPIO3] = 4, + [IRQ_DM3XX_GPIO4] = 7, + [IRQ_DM3XX_GPIO5] = 7, + [IRQ_DM3XX_GPIO6] = 7, + [IRQ_DM3XX_GPIO7] = 7, + [IRQ_DM3XX_GPIO8] = 7, + [IRQ_DM3XX_GPIO9] = 7, + [IRQ_DM365_GPIO10] = 7, + [IRQ_DM365_GPIO11] = 7, + [IRQ_DM365_GPIO12] = 7, + [IRQ_DM365_GPIO13] = 7, + [IRQ_DM365_GPIO14] = 7, + [IRQ_DM365_GPIO15] = 7, + [IRQ_DM365_KEYINT] = 7, + [IRQ_DM365_COMMTX] = 7, + [IRQ_DM365_COMMRX] = 7, + [IRQ_EMUINT] = 7, }; static inline unsigned int davinci_irq_readl(int offset) { - return davinci_readl(DAVINCI_ARM_INTC_BASE + offset); + return davinci_readl(DAVINCI_ARM_INTC_BASE + offset); } static inline void davinci_irq_writel(unsigned long value, int offset) { - davinci_writel(value, DAVINCI_ARM_INTC_BASE + offset); + davinci_writel(value, DAVINCI_ARM_INTC_BASE + offset); } /** @@ -121,8 +121,8 @@ static inline void davinci_irq_writel(unsigned long value, int offset) rt_isr_handler_t rt_hw_interrupt_handle(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); - return RT_NULL; + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + return RT_NULL; } /** @@ -130,59 +130,59 @@ rt_isr_handler_t rt_hw_interrupt_handle(int vector, void *param) */ void rt_hw_interrupt_init(void) { - int i; - register rt_uint32_t idx; - const rt_uint8_t *priority; - priority = dm365_default_priorities; - - /* Clear all interrupt requests */ - davinci_irq_writel(~0x0, FIQ_REG0_OFFSET); - davinci_irq_writel(~0x0, FIQ_REG1_OFFSET); - davinci_irq_writel(~0x0, IRQ_REG0_OFFSET); - davinci_irq_writel(~0x0, IRQ_REG1_OFFSET); - - /* Disable all interrupts */ - davinci_irq_writel(0x0, IRQ_ENT_REG0_OFFSET); - davinci_irq_writel(0x0, IRQ_ENT_REG1_OFFSET); - - /* Interrupts disabled immediately, IRQ entry reflects all */ - davinci_irq_writel(0x0, IRQ_INCTL_REG_OFFSET); - - /* we don't use the hardware vector table, just its entry addresses */ - davinci_irq_writel(0, IRQ_EABASE_REG_OFFSET); - - /* Clear all interrupt requests */ - davinci_irq_writel(~0x0, FIQ_REG0_OFFSET); - davinci_irq_writel(~0x0, FIQ_REG1_OFFSET); - davinci_irq_writel(~0x0, IRQ_REG0_OFFSET); - davinci_irq_writel(~0x0, IRQ_REG1_OFFSET); - - for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) { - unsigned j; - rt_uint32_t pri; - - for (j = 0, pri = 0; j < 32; j += 4, priority++) - pri |= (*priority & 0x07) << j; - davinci_irq_writel(pri, i); - } - - /* init exceptions table */ - for(idx=0; idx < MAX_HANDLERS; idx++) - { - - irq_desc[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle; - irq_desc[idx].param = RT_NULL; - #ifdef RT_USING_INTERRUPT_INFO - rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, "default"); - irq_desc[idx].counter = 0; - #endif - } - - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + int i; + register rt_uint32_t idx; + const rt_uint8_t *priority; + priority = dm365_default_priorities; + + /* Clear all interrupt requests */ + davinci_irq_writel(~0x0, FIQ_REG0_OFFSET); + davinci_irq_writel(~0x0, FIQ_REG1_OFFSET); + davinci_irq_writel(~0x0, IRQ_REG0_OFFSET); + davinci_irq_writel(~0x0, IRQ_REG1_OFFSET); + + /* Disable all interrupts */ + davinci_irq_writel(0x0, IRQ_ENT_REG0_OFFSET); + davinci_irq_writel(0x0, IRQ_ENT_REG1_OFFSET); + + /* Interrupts disabled immediately, IRQ entry reflects all */ + davinci_irq_writel(0x0, IRQ_INCTL_REG_OFFSET); + + /* we don't use the hardware vector table, just its entry addresses */ + davinci_irq_writel(0, IRQ_EABASE_REG_OFFSET); + + /* Clear all interrupt requests */ + davinci_irq_writel(~0x0, FIQ_REG0_OFFSET); + davinci_irq_writel(~0x0, FIQ_REG1_OFFSET); + davinci_irq_writel(~0x0, IRQ_REG0_OFFSET); + davinci_irq_writel(~0x0, IRQ_REG1_OFFSET); + + for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) { + unsigned j; + rt_uint32_t pri; + + for (j = 0, pri = 0; j < 32; j += 4, priority++) + pri |= (*priority & 0x07) << j; + davinci_irq_writel(pri, i); + } + + /* init exceptions table */ + for(idx=0; idx < MAX_HANDLERS; idx++) + { + + irq_desc[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle; + irq_desc[idx].param = RT_NULL; + #ifdef RT_USING_INTERRUPT_INFO + rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, "default"); + irq_desc[idx].counter = 0; + #endif + } + + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; } /** @@ -191,20 +191,20 @@ void rt_hw_interrupt_init(void) */ void rt_hw_interrupt_mask(int irq) { - unsigned int mask; - rt_uint32_t l; - - mask = 1 << IRQ_BIT(irq); - - if (irq > 31) { - l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET); - l &= ~mask; - davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET); - } else { - l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET); - l &= ~mask; - davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET); - } + unsigned int mask; + rt_uint32_t l; + + mask = 1 << IRQ_BIT(irq); + + if (irq > 31) { + l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET); + l &= ~mask; + davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET); + } else { + l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET); + l &= ~mask; + davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET); + } } /** @@ -213,20 +213,20 @@ void rt_hw_interrupt_mask(int irq) */ void rt_hw_interrupt_umask(int irq) { - unsigned int mask; - rt_uint32_t l; - - mask = 1 << IRQ_BIT(irq); - - if (irq > 31) { - l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET); - l |= mask; - davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET); - } else { - l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET); - l |= mask; - davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET); - } + unsigned int mask; + rt_uint32_t l; + + mask = 1 << IRQ_BIT(irq); + + if (irq > 31) { + l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET); + l |= mask; + davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET); + } else { + l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET); + l |= mask; + davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET); + } } /** @@ -239,25 +239,25 @@ void rt_hw_interrupt_umask(int irq) */ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) + void *param, const char *name) { - rt_isr_handler_t old_handler = RT_NULL; - - if(vector < MAX_HANDLERS) - { - old_handler = irq_desc[vector].handler; - if (handler != RT_NULL) - { - irq_desc[vector].handler = (rt_isr_handler_t)handler; - irq_desc[vector].param = param; - #ifdef RT_USING_INTERRUPT_INFO - rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name); - irq_desc[vector].counter = 0; - #endif - } - } - - return old_handler; + rt_isr_handler_t old_handler = RT_NULL; + + if(vector < MAX_HANDLERS) + { + old_handler = irq_desc[vector].handler; + if (handler != RT_NULL) + { + irq_desc[vector].handler = (rt_isr_handler_t)handler; + irq_desc[vector].param = param; + #ifdef RT_USING_INTERRUPT_INFO + rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name); + irq_desc[vector].counter = 0; + #endif + } + } + + return old_handler; } @@ -265,16 +265,16 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, #ifdef RT_USING_INTERRUPT_INFO void list_irq(void) { - int irq; - - rt_kprintf("number\tcount\tname\n"); - for (irq = 0; irq < MAX_HANDLERS; irq++) - { - if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default"))) - { - rt_kprintf("%02ld: %10ld %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name); - } - } + int irq; + + rt_kprintf("number\tcount\tname\n"); + for (irq = 0; irq < MAX_HANDLERS; irq++) + { + if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default"))) + { + rt_kprintf("%02ld: %10ld %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name); + } + } } #include diff --git a/bsp/dm365/platform/irqs.h b/bsp/dm365/platform/irqs.h index 1588fc4b2f..b8c4ecc9e4 100644 --- a/bsp/dm365/platform/irqs.h +++ b/bsp/dm365/platform/irqs.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ #ifndef __DM36X_IRQS_H__ @@ -18,7 +18,7 @@ extern "C" { /* Base address */ #define DAVINCI_ARM_INTC_BASE 0x01C48000 -#define DAVINCI_N_AINTC_IRQ 64 +#define DAVINCI_N_AINTC_IRQ 64 /* Interrupt lines */ #define IRQ_VDINT0 0 @@ -88,100 +88,100 @@ extern "C" { /* * Base Interrupts common across DM355 and DM365 */ -#define IRQ_DM3XX_VPSSINT0 0 -#define IRQ_DM3XX_VPSSINT1 1 -#define IRQ_DM3XX_VPSSINT2 2 -#define IRQ_DM3XX_VPSSINT3 3 -#define IRQ_DM3XX_VPSSINT4 4 -#define IRQ_DM3XX_VPSSINT5 5 -#define IRQ_DM3XX_VPSSINT6 6 -#define IRQ_DM3XX_VPSSINT7 7 -#define IRQ_DM3XX_VPSSINT8 8 -#define IRQ_DM3XX_IMCOPINT 11 -#define IRQ_DM3XX_RTOINT 13 -#define IRQ_DM3XX_TINT4 13 -#define IRQ_DM3XX_TINT2_TINT12 13 -#define IRQ_DM3XX_TINT5 14 -#define IRQ_DM3XX_TINT2_TINT34 14 -#define IRQ_DM3XX_TINT6 15 -#define IRQ_DM3XX_TINT3_TINT12 15 -#define IRQ_DM3XX_SPINT1_0 17 -#define IRQ_DM3XX_SPINT1_1 18 -#define IRQ_DM3XX_SPINT2_0 19 -#define IRQ_DM3XX_SPINT2_1 21 -#define IRQ_DM3XX_TINT7 22 -#define IRQ_DM3XX_TINT3_TINT34 22 -#define IRQ_DM3XX_SDIOINT0 23 -#define IRQ_DM3XX_MMCINT0 26 -#define IRQ_DM3XX_MSINT 26 -#define IRQ_DM3XX_MMCINT1 27 -#define IRQ_DM3XX_PWMINT3 28 -#define IRQ_DM3XX_SDIOINT1 31 -#define IRQ_DM3XX_SPINT0_0 42 -#define IRQ_DM3XX_SPINT0_1 43 -#define IRQ_DM3XX_GPIO0 44 -#define IRQ_DM3XX_GPIO1 45 -#define IRQ_DM3XX_GPIO2 46 -#define IRQ_DM3XX_GPIO3 47 -#define IRQ_DM3XX_GPIO4 48 -#define IRQ_DM3XX_GPIO5 49 -#define IRQ_DM3XX_GPIO6 50 -#define IRQ_DM3XX_GPIO7 51 -#define IRQ_DM3XX_GPIO8 52 -#define IRQ_DM3XX_GPIO9 53 +#define IRQ_DM3XX_VPSSINT0 0 +#define IRQ_DM3XX_VPSSINT1 1 +#define IRQ_DM3XX_VPSSINT2 2 +#define IRQ_DM3XX_VPSSINT3 3 +#define IRQ_DM3XX_VPSSINT4 4 +#define IRQ_DM3XX_VPSSINT5 5 +#define IRQ_DM3XX_VPSSINT6 6 +#define IRQ_DM3XX_VPSSINT7 7 +#define IRQ_DM3XX_VPSSINT8 8 +#define IRQ_DM3XX_IMCOPINT 11 +#define IRQ_DM3XX_RTOINT 13 +#define IRQ_DM3XX_TINT4 13 +#define IRQ_DM3XX_TINT2_TINT12 13 +#define IRQ_DM3XX_TINT5 14 +#define IRQ_DM3XX_TINT2_TINT34 14 +#define IRQ_DM3XX_TINT6 15 +#define IRQ_DM3XX_TINT3_TINT12 15 +#define IRQ_DM3XX_SPINT1_0 17 +#define IRQ_DM3XX_SPINT1_1 18 +#define IRQ_DM3XX_SPINT2_0 19 +#define IRQ_DM3XX_SPINT2_1 21 +#define IRQ_DM3XX_TINT7 22 +#define IRQ_DM3XX_TINT3_TINT34 22 +#define IRQ_DM3XX_SDIOINT0 23 +#define IRQ_DM3XX_MMCINT0 26 +#define IRQ_DM3XX_MSINT 26 +#define IRQ_DM3XX_MMCINT1 27 +#define IRQ_DM3XX_PWMINT3 28 +#define IRQ_DM3XX_SDIOINT1 31 +#define IRQ_DM3XX_SPINT0_0 42 +#define IRQ_DM3XX_SPINT0_1 43 +#define IRQ_DM3XX_GPIO0 44 +#define IRQ_DM3XX_GPIO1 45 +#define IRQ_DM3XX_GPIO2 46 +#define IRQ_DM3XX_GPIO3 47 +#define IRQ_DM3XX_GPIO4 48 +#define IRQ_DM3XX_GPIO5 49 +#define IRQ_DM3XX_GPIO6 50 +#define IRQ_DM3XX_GPIO7 51 +#define IRQ_DM3XX_GPIO8 52 +#define IRQ_DM3XX_GPIO9 53 /* DaVinci DM365-specific Interrupts */ -#define IRQ_DM365_INSFINT 7 -#define IRQ_DM365_IMXINT1 8 -#define IRQ_DM365_IMXINT0 10 -#define IRQ_DM365_KLD_ARMINT 10 -#define IRQ_DM365_CCERRINT 17 -#define IRQ_DM365_TCERRINT0 18 -#define IRQ_DM365_SPINT2_0 19 -#define IRQ_DM365_PSCINT 20 -#define IRQ_DM365_TVINT 20 -#define IRQ_DM365_SPINT4_0 21 -#define IRQ_DM365_MBXINT 24 -#define IRQ_DM365_VCINT 24 -#define IRQ_DM365_MBRINT 25 -#define IRQ_DM365_TINT9 28 -#define IRQ_DM365_TINT4_TINT34 28 -#define IRQ_DM365_DDRINT 29 -#define IRQ_DM365_RTCINT 29 -#define IRQ_DM365_AEMIFINT 30 -#define IRQ_DM365_HPIINT 30 -#define IRQ_DM365_TINT0 32 -#define IRQ_DM365_TINT0_TINT12 32 -#define IRQ_DM365_TINT1 33 -#define IRQ_DM365_TINT0_TINT34 33 -#define IRQ_DM365_TINT2 34 -#define IRQ_DM365_TINT1_TINT12 34 -#define IRQ_DM365_TINT3 35 -#define IRQ_DM365_TINT1_TINT34 35 -#define IRQ_DM365_PWMINT2 38 -#define IRQ_DM365_TINT8 38 -#define IRQ_DM365_TINT4_TINT12 38 -#define IRQ_DM365_IICINT 39 -#define IRQ_DM365_SPINT3_0 43 -#define IRQ_DM365_EMAC_RXTHRESH 52 -#define IRQ_DM365_EMAC_RXPULSE 53 -#define IRQ_DM365_GPIO10 54 -#define IRQ_DM365_EMAC_TXPULSE 54 -#define IRQ_DM365_GPIO11 55 +#define IRQ_DM365_INSFINT 7 +#define IRQ_DM365_IMXINT1 8 +#define IRQ_DM365_IMXINT0 10 +#define IRQ_DM365_KLD_ARMINT 10 +#define IRQ_DM365_CCERRINT 17 +#define IRQ_DM365_TCERRINT0 18 +#define IRQ_DM365_SPINT2_0 19 +#define IRQ_DM365_PSCINT 20 +#define IRQ_DM365_TVINT 20 +#define IRQ_DM365_SPINT4_0 21 +#define IRQ_DM365_MBXINT 24 +#define IRQ_DM365_VCINT 24 +#define IRQ_DM365_MBRINT 25 +#define IRQ_DM365_TINT9 28 +#define IRQ_DM365_TINT4_TINT34 28 +#define IRQ_DM365_DDRINT 29 +#define IRQ_DM365_RTCINT 29 +#define IRQ_DM365_AEMIFINT 30 +#define IRQ_DM365_HPIINT 30 +#define IRQ_DM365_TINT0 32 +#define IRQ_DM365_TINT0_TINT12 32 +#define IRQ_DM365_TINT1 33 +#define IRQ_DM365_TINT0_TINT34 33 +#define IRQ_DM365_TINT2 34 +#define IRQ_DM365_TINT1_TINT12 34 +#define IRQ_DM365_TINT3 35 +#define IRQ_DM365_TINT1_TINT34 35 +#define IRQ_DM365_PWMINT2 38 +#define IRQ_DM365_TINT8 38 +#define IRQ_DM365_TINT4_TINT12 38 +#define IRQ_DM365_IICINT 39 +#define IRQ_DM365_SPINT3_0 43 +#define IRQ_DM365_EMAC_RXTHRESH 52 +#define IRQ_DM365_EMAC_RXPULSE 53 +#define IRQ_DM365_GPIO10 54 +#define IRQ_DM365_EMAC_TXPULSE 54 +#define IRQ_DM365_GPIO11 55 #define IRQ_DM365_EMAC_MISCPULSE 55 -#define IRQ_DM365_GPIO12 56 -#define IRQ_DM365_PWRGIO0 56 -#define IRQ_DM365_GPIO13 57 -#define IRQ_DM365_PWRGIO1 57 -#define IRQ_DM365_GPIO14 58 -#define IRQ_DM365_PWRGIO2 58 -#define IRQ_DM365_GPIO15 59 -#define IRQ_DM365_ADCINT 59 -#define IRQ_DM365_KEYINT 60 -#define IRQ_DM365_COMMTX 61 -#define IRQ_DM365_TCERRINT2 61 -#define IRQ_DM365_COMMRX 62 -#define IRQ_DM365_TCERRINT3 62 +#define IRQ_DM365_GPIO12 56 +#define IRQ_DM365_PWRGIO0 56 +#define IRQ_DM365_GPIO13 57 +#define IRQ_DM365_PWRGIO1 57 +#define IRQ_DM365_GPIO14 58 +#define IRQ_DM365_PWRGIO2 58 +#define IRQ_DM365_GPIO15 59 +#define IRQ_DM365_ADCINT 59 +#define IRQ_DM365_KEYINT 60 +#define IRQ_DM365_COMMTX 61 +#define IRQ_DM365_TCERRINT2 61 +#define IRQ_DM365_COMMRX 62 +#define IRQ_DM365_TCERRINT3 62 #ifdef __cplusplus diff --git a/bsp/dm365/platform/psc.c b/bsp/dm365/platform/psc.c index 52cab1f276..b2e0a90197 100644 --- a/bsp/dm365/platform/psc.c +++ b/bsp/dm365/platform/psc.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ #include "dm36x.h" @@ -19,13 +19,13 @@ * ------------------------------------------------------------------------ */ void psc_change_state(int id, int state) { - rt_uint32_t mdstat, mdctl; + rt_uint32_t mdstat, mdctl; - if (id > DAVINCI_DM365_LPSC_KALEIDO) - return; + if (id > DAVINCI_DM365_LPSC_KALEIDO) + return; - mdstat = PSC_MDSTAT_BASE + (id * 4); - mdctl = PSC_MDCTL_BASE + (id * 4); + mdstat = PSC_MDSTAT_BASE + (id * 4); + mdctl = PSC_MDCTL_BASE + (id * 4); /* * Step 0 - Ignore request if the state is already set as is diff --git a/bsp/dm365/platform/psc.h b/bsp/dm365/platform/psc.h index d918b488a0..116b7b2dd7 100644 --- a/bsp/dm365/platform/psc.h +++ b/bsp/dm365/platform/psc.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ #ifndef __DM36X_PSC_H @@ -17,69 +17,69 @@ extern "C" { /* PSC register offsets */ -#define EPCPR 0x070 -#define PTCMD 0x120 -#define PTSTAT 0x128 -#define PDSTAT 0x200 -#define PDCTL1 0x304 -#define MDSTAT(n) (0x800 + (n) * 4) -#define MDCTL(n) (0xA00 + (n) * 4) +#define EPCPR 0x070 +#define PTCMD 0x120 +#define PTSTAT 0x128 +#define PDSTAT 0x200 +#define PDCTL1 0x304 +#define MDSTAT(n) (0x800 + (n) * 4) +#define MDCTL(n) (0xA00 + (n) * 4) /* Power and Sleep Controller (PSC) Domains */ -#define DAVINCI_GPSC_ARMDOMAIN 0 -#define DAVINCI_GPSC_DSPDOMAIN 1 +#define DAVINCI_GPSC_ARMDOMAIN 0 +#define DAVINCI_GPSC_DSPDOMAIN 1 -#define DAVINCI_DM365_LPSC_TPCC 0 -#define DAVINCI_DM365_LPSC_TPTC0 1 -#define DAVINCI_DM365_LPSC_TPTC1 2 -#define DAVINCI_DM365_LPSC_TPTC2 3 -#define DAVINCI_DM365_LPSC_TPTC3 4 -#define DAVINCI_DM365_LPSC_TIMER3 5 -#define DAVINCI_DM365_LPSC_SPI1 6 -#define DAVINCI_DM365_LPSC_MMC_SD1 7 -#define DAVINCI_DM365_LPSC_McBSP 8 -#define DAVINCI_DM365_LPSC_USB 9 -#define DAVINCI_DM365_LPSC_PWM3 10 -#define DAVINCI_DM365_LPSC_SPI2 11 -#define DAVINCI_DM365_LPSC_RTO 12 -#define DAVINCI_DM365_LPSC_DDR_EMIF 13 -#define DAVINCI_DM365_LPSC_AEMIF 14 -#define DAVINCI_DM365_LPSC_MMC_SD 15 -#define DAVINCI_DM365_LPSC_MMC_SD0 15 -#define DAVINCI_DM365_LPSC_MEMSTICK 16 -#define DAVINCI_DM365_LPSC_TIMER4 17 -#define DAVINCI_DM365_LPSC_I2C 18 -#define DAVINCI_DM365_LPSC_UART0 19 -#define DAVINCI_DM365_LPSC_UART1 20 -#define DAVINCI_DM365_LPSC_UHPI 21 -#define DAVINCI_DM365_LPSC_SPI0 22 -#define DAVINCI_DM365_LPSC_PWM0 23 -#define DAVINCI_DM365_LPSC_PWM1 24 -#define DAVINCI_DM365_LPSC_PWM2 25 -#define DAVINCI_DM365_LPSC_GPIO 26 -#define DAVINCI_DM365_LPSC_TIMER0 27 -#define DAVINCI_DM365_LPSC_TIMER1 28 -#define DAVINCI_DM365_LPSC_TIMER2 29 +#define DAVINCI_DM365_LPSC_TPCC 0 +#define DAVINCI_DM365_LPSC_TPTC0 1 +#define DAVINCI_DM365_LPSC_TPTC1 2 +#define DAVINCI_DM365_LPSC_TPTC2 3 +#define DAVINCI_DM365_LPSC_TPTC3 4 +#define DAVINCI_DM365_LPSC_TIMER3 5 +#define DAVINCI_DM365_LPSC_SPI1 6 +#define DAVINCI_DM365_LPSC_MMC_SD1 7 +#define DAVINCI_DM365_LPSC_McBSP 8 +#define DAVINCI_DM365_LPSC_USB 9 +#define DAVINCI_DM365_LPSC_PWM3 10 +#define DAVINCI_DM365_LPSC_SPI2 11 +#define DAVINCI_DM365_LPSC_RTO 12 +#define DAVINCI_DM365_LPSC_DDR_EMIF 13 +#define DAVINCI_DM365_LPSC_AEMIF 14 +#define DAVINCI_DM365_LPSC_MMC_SD 15 +#define DAVINCI_DM365_LPSC_MMC_SD0 15 +#define DAVINCI_DM365_LPSC_MEMSTICK 16 +#define DAVINCI_DM365_LPSC_TIMER4 17 +#define DAVINCI_DM365_LPSC_I2C 18 +#define DAVINCI_DM365_LPSC_UART0 19 +#define DAVINCI_DM365_LPSC_UART1 20 +#define DAVINCI_DM365_LPSC_UHPI 21 +#define DAVINCI_DM365_LPSC_SPI0 22 +#define DAVINCI_DM365_LPSC_PWM0 23 +#define DAVINCI_DM365_LPSC_PWM1 24 +#define DAVINCI_DM365_LPSC_PWM2 25 +#define DAVINCI_DM365_LPSC_GPIO 26 +#define DAVINCI_DM365_LPSC_TIMER0 27 +#define DAVINCI_DM365_LPSC_TIMER1 28 +#define DAVINCI_DM365_LPSC_TIMER2 29 #define DAVINCI_DM365_LPSC_SYSTEM_SUBSYS 30 -#define DAVINCI_DM365_LPSC_ARM 31 -#define DAVINCI_DM365_LPSC_SCR0 33 -#define DAVINCI_DM365_LPSC_SCR1 34 -#define DAVINCI_DM365_LPSC_EMU 35 -#define DAVINCI_DM365_LPSC_CHIPDFT 36 -#define DAVINCI_DM365_LPSC_PBIST 37 -#define DAVINCI_DM365_LPSC_SPI3 38 -#define DAVINCI_DM365_LPSC_SPI4 39 -#define DAVINCI_DM365_LPSC_CPGMAC 40 -#define DAVINCI_DM365_LPSC_RTC 41 -#define DAVINCI_DM365_LPSC_KEYSCAN 42 -#define DAVINCI_DM365_LPSC_ADCIF 43 -#define DAVINCI_DM365_LPSC_VOICE_CODEC 44 -#define DAVINCI_DM365_LPSC_DAC_CLKRES 45 -#define DAVINCI_DM365_LPSC_DAC_CLK 46 -#define DAVINCI_DM365_LPSC_VPSSMSTR 47 -#define DAVINCI_DM365_LPSC_IMCOP 50 -#define DAVINCI_DM365_LPSC_KALEIDO 51 +#define DAVINCI_DM365_LPSC_ARM 31 +#define DAVINCI_DM365_LPSC_SCR0 33 +#define DAVINCI_DM365_LPSC_SCR1 34 +#define DAVINCI_DM365_LPSC_EMU 35 +#define DAVINCI_DM365_LPSC_CHIPDFT 36 +#define DAVINCI_DM365_LPSC_PBIST 37 +#define DAVINCI_DM365_LPSC_SPI3 38 +#define DAVINCI_DM365_LPSC_SPI4 39 +#define DAVINCI_DM365_LPSC_CPGMAC 40 +#define DAVINCI_DM365_LPSC_RTC 41 +#define DAVINCI_DM365_LPSC_KEYSCAN 42 +#define DAVINCI_DM365_LPSC_ADCIF 43 +#define DAVINCI_DM365_LPSC_VOICE_CODEC 44 +#define DAVINCI_DM365_LPSC_DAC_CLKRES 45 +#define DAVINCI_DM365_LPSC_DAC_CLK 46 +#define DAVINCI_DM365_LPSC_VPSSMSTR 47 +#define DAVINCI_DM365_LPSC_IMCOP 50 +#define DAVINCI_DM365_LPSC_KALEIDO 51 #define PSC_ENABLE 3 #define PSC_DISABLE 2 diff --git a/bsp/dm365/platform/reset.c b/bsp/dm365/platform/reset.c index 02ec9db4ae..dc80fac76e 100644 --- a/bsp/dm365/platform/reset.c +++ b/bsp/dm365/platform/reset.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ @@ -24,7 +24,7 @@ */ void machine_reset() { - reset_system(); + reset_system(); } /** @@ -44,14 +44,14 @@ FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_cpu_reset, reset, restart the system); #ifdef FINSH_USING_MSH int cmd_reset(int argc, char** argv) { - rt_hw_cpu_reset(); - return 0; + rt_hw_cpu_reset(); + return 0; } int cmd_shutdown(int argc, char** argv) { - rt_hw_cpu_shutdown(); - return 0; + rt_hw_cpu_shutdown(); + return 0; } FINSH_FUNCTION_EXPORT_ALIAS(cmd_reset, __cmd_reset, restart the system.); diff --git a/bsp/dm365/platform/system_clock.c b/bsp/dm365/platform/system_clock.c index 5d8bea4442..7d4c58874f 100644 --- a/bsp/dm365/platform/system_clock.c +++ b/bsp/dm365/platform/system_clock.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ @@ -19,6 +19,6 @@ extern int davinci_clk_init(void); */ void rt_hw_clock_init(void) { - davinci_clk_init(); + davinci_clk_init(); } diff --git a/bsp/dm365/platform/trap.c b/bsp/dm365/platform/trap.c index 8c067f9f3b..5c5f0272b3 100644 --- a/bsp/dm365/platform/trap.c +++ b/bsp/dm365/platform/trap.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ @@ -32,13 +32,13 @@ extern long list_thread(void); void rt_hw_show_register (struct rt_hw_register *regs) { - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); } /** @@ -51,15 +51,15 @@ void rt_hw_show_register (struct rt_hw_register *regs) */ void rt_hw_trap_udef(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("undefined instruction\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_kprintf("undefined instruction\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -73,10 +73,10 @@ void rt_hw_trap_udef(struct rt_hw_register *regs) */ void rt_hw_trap_swi(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("software interrupt\n"); - rt_hw_cpu_shutdown(); + rt_kprintf("software interrupt\n"); + rt_hw_cpu_shutdown(); } /** @@ -89,15 +89,15 @@ void rt_hw_trap_swi(struct rt_hw_register *regs) */ void rt_hw_trap_pabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("prefetch abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_kprintf("prefetch abort\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -110,30 +110,30 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs) */ void rt_hw_trap_dabt(struct rt_hw_register *regs) { - rt_uint32_t fault_addr; - rt_uint32_t fault_status; - asm volatile ("mrc p15, 0, %0, c6, c0, 0" - : - :"r"(fault_addr) - :"cc"); - rt_kprintf("unhandler access to 0x%08x\n", fault_addr); - - /* read DFSR */ - asm volatile ("MRC p15, 0, %0, c5, c0, 0" - : - :"r"(fault_status) - :"cc"); - rt_kprintf("fault status 0x%08x\n", fault_status); - - rt_hw_show_register(regs); - - rt_kprintf("data abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_uint32_t fault_addr; + rt_uint32_t fault_status; + asm volatile ("mrc p15, 0, %0, c6, c0, 0" + : + :"r"(fault_addr) + :"cc"); + rt_kprintf("unhandler access to 0x%08x\n", fault_addr); + + /* read DFSR */ + asm volatile ("MRC p15, 0, %0, c5, c0, 0" + : + :"r"(fault_status) + :"cc"); + rt_kprintf("fault status 0x%08x\n", fault_status); + + rt_hw_show_register(regs); + + rt_kprintf("data abort\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -145,9 +145,9 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs) */ void rt_hw_trap_resv(struct rt_hw_register *regs) { - rt_kprintf("not used\n"); - rt_hw_show_register(regs); - rt_hw_cpu_shutdown(); + rt_kprintf("not used\n"); + rt_hw_show_register(regs); + rt_hw_cpu_shutdown(); } extern struct rt_irq_desc irq_desc[]; @@ -155,32 +155,32 @@ extern struct rt_irq_desc irq_desc[]; void rt_hw_trap_irq() { - rt_isr_handler_t isr_func; - rt_uint32_t val, irq, mask; - void *param; - - /* get irq number */ - val = readl(DAVINCI_ARM_INTC_BASE+0x14) - readl(DAVINCI_ARM_INTC_BASE+0x24); - irq = (val >> 2) - 1; - /* clear pending register */ - mask = 1 << (irq & 0x1f); - if (irq > 31) - writel(mask, DAVINCI_ARM_INTC_BASE+0x0c); //IRQ1 - else - writel(mask, DAVINCI_ARM_INTC_BASE+0x08); //IRQ0 - - /* get interrupt service routine */ - isr_func = irq_desc[irq].handler; - param = irq_desc[irq].param; - - /* turn to interrupt service routine */ - isr_func(irq, param); - irq_desc[irq].counter++; + rt_isr_handler_t isr_func; + rt_uint32_t val, irq, mask; + void *param; + + /* get irq number */ + val = readl(DAVINCI_ARM_INTC_BASE+0x14) - readl(DAVINCI_ARM_INTC_BASE+0x24); + irq = (val >> 2) - 1; + /* clear pending register */ + mask = 1 << (irq & 0x1f); + if (irq > 31) + writel(mask, DAVINCI_ARM_INTC_BASE+0x0c); //IRQ1 + else + writel(mask, DAVINCI_ARM_INTC_BASE+0x08); //IRQ0 + + /* get interrupt service routine */ + isr_func = irq_desc[irq].handler; + param = irq_desc[irq].param; + + /* turn to interrupt service routine */ + isr_func(irq, param); + irq_desc[irq].counter++; } void rt_hw_trap_fiq() { - rt_kprintf("fast interrupt request\n"); + rt_kprintf("fast interrupt request\n"); } /*@}*/ diff --git a/bsp/efm32/application.c b/bsp/efm32/application.c index 12949a39c8..4ca58fe6ec 100644 --- a/bsp/efm32/application.c +++ b/bsp/efm32/application.c @@ -77,8 +77,8 @@ struct photo_event { struct rtgui_event_win win; rt_uint32_t cmd; - rt_uint8_t* path; - rt_uint8_t* format; + rt_uint8_t* path; + rt_uint8_t* format; }; /* Private defines -----------------------------------------------------------*/ @@ -95,10 +95,10 @@ volatile rt_uint32_t rt_system_status = 0; #if defined(RT_USING_RTGUI) static rt_bool_t pic_view_event_handler(rtgui_object_t *object, rtgui_event_t *event) { - rt_bool_t result; + rt_bool_t result; rt_bool_t load = RT_FALSE; - result = rtgui_container_event_handler(object, event); + result = rtgui_container_event_handler(object, event); switch(event->type) { @@ -108,27 +108,27 @@ static rt_bool_t pic_view_event_handler(rtgui_object_t *object, rtgui_event_t *e case RTGUI_EVENT_MOUSE_BUTTON: { - struct rtgui_event_mouse *mouse = (struct rtgui_event_mouse *)event; + struct rtgui_event_mouse *mouse = (struct rtgui_event_mouse *)event; - if (mouse->button == RTGUI_MOUSE_BUTTON_LEFT | RTGUI_MOUSE_BUTTON_UP) - { + if (mouse->button == RTGUI_MOUSE_BUTTON_LEFT | RTGUI_MOUSE_BUTTON_UP) + { rt_kprintf("APP: left click (%x)\n", mouse->button); - } + } } break; } if (load) - { - struct rtgui_dc* dc; - rtgui_rect_t rect; + { + struct rtgui_dc* dc; + rtgui_rect_t rect; rtgui_image_t* image; image = rtgui_image_create_from_file("jpg", "/test9.jpg", RT_FALSE); // image = rtgui_image_create_from_file("bmp", "/test_565.bmp", RT_FALSE); - dc = rtgui_dc_begin_drawing(RTGUI_WIDGET(object)); - if (dc == RT_NULL) + dc = rtgui_dc_begin_drawing(RTGUI_WIDGET(object)); + if (dc == RT_NULL) { return result; } @@ -138,9 +138,9 @@ static rt_bool_t pic_view_event_handler(rtgui_object_t *object, rtgui_event_t *e rect.x1 +=10; rect.y1 +=10; - if (image != RT_NULL) + if (image != RT_NULL) { - rtgui_image_blit(image, dc, &rect); + rtgui_image_blit(image, dc, &rect); rtgui_image_destroy(image); } else @@ -148,10 +148,10 @@ static rt_bool_t pic_view_event_handler(rtgui_object_t *object, rtgui_event_t *e rt_kprintf("APP err: no image found!\n"); } - rtgui_dc_end_drawing(dc, RT_TRUE); - } + rtgui_dc_end_drawing(dc, RT_TRUE); + } - return result; + return result; } static void app_main(void *parameter) @@ -169,21 +169,21 @@ static void app_main(void *parameter) lcd->control(lcd, RTGRAPHIC_CTRL_GET_INFO, (void *)&lcd_info); rt_kprintf("LCD size: %dX%d\n", lcd_info.width, lcd_info.height); - /* create application */ - struct rtgui_app *app; - app = rtgui_app_create("gui_app"); - if (app == RT_NULL) + /* create application */ + struct rtgui_app *app; + app = rtgui_app_create("gui_app"); + if (app == RT_NULL) { rt_kprintf("Create application \"gui_app\" failed!\n"); return; } - struct rtgui_rect rect1, rect2, rect3; + struct rtgui_rect rect1, rect2, rect3; struct rtgui_win *win_info, *win_main, *win_hello; - struct rtgui_container *container; + struct rtgui_container *container; struct rtgui_label* label; - rtgui_graphic_driver_get_rect(rtgui_graphic_driver_get_default(), &rect1); + rtgui_graphic_driver_get_rect(rtgui_graphic_driver_get_default(), &rect1); rect2.x1 = rect1.x1; rect2.y1 = 25; rect2.x2 = rect1.x2; @@ -191,106 +191,106 @@ static void app_main(void *parameter) rect1.y2 = 25; /* create info window */ - win_info = rtgui_win_create(RT_NULL, "info", + win_info = rtgui_win_create(RT_NULL, "info", &rect1, RTGUI_WIN_STYLE_NO_BORDER | RTGUI_WIN_STYLE_NO_TITLE); - if (win_info == RT_NULL) - { + if (win_info == RT_NULL) + { rt_kprintf("Create window \"info\" failed!\n"); - rtgui_app_destroy(app); + rtgui_app_destroy(app); return; - } + } /* create container in info window */ - container = rtgui_container_create(); - if (container == RT_NULL) - { + container = rtgui_container_create(); + if (container == RT_NULL) + { rt_kprintf("Create container failed!\n"); - return; - } - rtgui_widget_set_rect(RTGUI_WIDGET(container), &rect1); + return; + } + rtgui_widget_set_rect(RTGUI_WIDGET(container), &rect1); rtgui_container_add_child(RTGUI_CONTAINER(win_info), RTGUI_WIDGET(container)); /* create lable in info window */ - label = rtgui_label_create("RT-Thread & RTGUI"); + label = rtgui_label_create("RT-Thread & RTGUI"); if (label == RT_NULL) { rt_kprintf("Create lable failed!\n"); return; } - RTGUI_WIDGET_TEXTALIGN(RTGUI_WIDGET(label)) = RTGUI_ALIGN_LEFT; - RTGUI_WIDGET_BACKGROUND(RTGUI_WIDGET(label)) = red; + RTGUI_WIDGET_TEXTALIGN(RTGUI_WIDGET(label)) = RTGUI_ALIGN_LEFT; + RTGUI_WIDGET_BACKGROUND(RTGUI_WIDGET(label)) = red; RTGUI_WIDGET_FOREGROUND(RTGUI_WIDGET(label)) = white; - rect3.x1 = rect1.x1 + 5; - rect3.y1 = rect1.y1 + 5; - rect3.x2 = rect1.x2 - 5; - rect3.y2 = rect1.y2 - 5; - rtgui_widget_set_rect(RTGUI_WIDGET(label), &rect3); - rtgui_container_add_child(container, RTGUI_WIDGET(label)); + rect3.x1 = rect1.x1 + 5; + rect3.y1 = rect1.y1 + 5; + rect3.x2 = rect1.x2 - 5; + rect3.y2 = rect1.y2 - 5; + rtgui_widget_set_rect(RTGUI_WIDGET(label), &rect3); + rtgui_container_add_child(container, RTGUI_WIDGET(label)); /* create main window */ - win_main = rtgui_win_create(RT_NULL, "main", + win_main = rtgui_win_create(RT_NULL, "main", &rect2, RTGUI_WIN_STYLE_NO_BORDER | RTGUI_WIN_STYLE_NO_TITLE); - if (win_main == RT_NULL) - { + if (win_main == RT_NULL) + { rt_kprintf("Create window \"main\" failed!\n"); - rtgui_app_destroy(app); + rtgui_app_destroy(app); return; - } + } /* create container in main window */ - container = rtgui_container_create(); - if (container == RT_NULL) - { + container = rtgui_container_create(); + if (container == RT_NULL) + { rt_kprintf("Create container failed!\n"); - return; - } + return; + } - rtgui_widget_set_rect(RTGUI_WIDGET(container), &rect2); + rtgui_widget_set_rect(RTGUI_WIDGET(container), &rect2); rtgui_object_set_event_handler(RTGUI_OBJECT(container), pic_view_event_handler); rtgui_container_add_child(RTGUI_CONTAINER(win_main), RTGUI_WIDGET(container)); /* create lable in main window */ - label = rtgui_label_create("EFM32GG_DK3750 Kit"); + label = rtgui_label_create("EFM32GG_DK3750 Kit"); if (label == RT_NULL) { rt_kprintf("Create lable failed!\n"); return; } - RTGUI_WIDGET_TEXTALIGN(RTGUI_WIDGET(label)) = RTGUI_ALIGN_LEFT; - RTGUI_WIDGET_BACKGROUND(RTGUI_WIDGET(label)) = white; + RTGUI_WIDGET_TEXTALIGN(RTGUI_WIDGET(label)) = RTGUI_ALIGN_LEFT; + RTGUI_WIDGET_BACKGROUND(RTGUI_WIDGET(label)) = white; RTGUI_WIDGET_FOREGROUND(RTGUI_WIDGET(label)) = blue; - rect3.x1 = rect2.x1 + 5; - rect3.y1 = rect2.y1 + 5; - rect3.x2 = rect2.x2 - 5; - rect3.y2 = rect2.y1 + 20; - rtgui_widget_set_rect(RTGUI_WIDGET(label), &rect3); - rtgui_container_add_child(container, RTGUI_WIDGET(label)); + rect3.x1 = rect2.x1 + 5; + rect3.y1 = rect2.y1 + 5; + rect3.x2 = rect2.x2 - 5; + rect3.y2 = rect2.y1 + 20; + rtgui_widget_set_rect(RTGUI_WIDGET(label), &rect3); + rtgui_container_add_child(container, RTGUI_WIDGET(label)); /* create hello window */ - rect3.x1 = 80; - rect3.y1 = 50; - rect3.x2 = 320 - 80; - rect3.y2 = 240 - 50; - win_hello = rtgui_win_create(RT_NULL, "hello", + rect3.x1 = 80; + rect3.y1 = 50; + rect3.x2 = 320 - 80; + rect3.y2 = 240 - 50; + win_hello = rtgui_win_create(RT_NULL, "hello", &rect3, RTGUI_WIN_STYLE_DEFAULT); - if (win_hello == RT_NULL) - { + if (win_hello == RT_NULL) + { rt_kprintf("Create window \"hello\" failed!\n"); - rtgui_app_destroy(app); + rtgui_app_destroy(app); return; - } + } /* create a box */ rtgui_box_t *box = rtgui_box_create(RTGUI_VERTICAL, RT_NULL); - if(box == RT_NULL) + if(box == RT_NULL) { rt_kprintf("Create box failed!\n"); return; @@ -298,12 +298,12 @@ static void app_main(void *parameter) // rtgui_win_set_box(win_hello, box); label = rtgui_label_create("哈罗,盹胖!"); - if(label == RT_NULL) + if(label == RT_NULL) { rt_kprintf("Create lable failed!\n"); return; } - RTGUI_WIDGET_BACKGROUND(RTGUI_WIDGET(label)) = white; + RTGUI_WIDGET_BACKGROUND(RTGUI_WIDGET(label)) = white; RTGUI_WIDGET_FOREGROUND(RTGUI_WIDGET(label)) = black; RTGUI_WIDGET(label)->align = RTGUI_ALIGN_CENTER_HORIZONTAL | RTGUI_ALIGN_CENTER_VERTICAL; rtgui_widget_set_miniwidth(RTGUI_WIDGET(label),130); @@ -322,18 +322,18 @@ static void app_main(void *parameter) static rt_bool_t photo_view_event_handler(rtgui_object_t *object, rtgui_event_t *event) { - rt_bool_t result = RT_FALSE; + rt_bool_t result = RT_FALSE; struct photo_event *photo_event = (struct photo_event *)event; - result = rtgui_container_event_handler(object, event); + result = rtgui_container_event_handler(object, event); rt_kprintf("container event %x\n", event->type); - struct rtgui_event_win* wevent = (struct rtgui_event_win*)event; + struct rtgui_event_win* wevent = (struct rtgui_event_win*)event; rt_kprintf("wevent->wid %x\n", wevent->wid); if ((event->type == RTGUI_EVENT_COMMAND) && \ (photo_event->cmd == APP_CMD_PHOTO_FRAME)) - { + { rtgui_rect_t rect; rtgui_image_t* image; struct rtgui_dc* dc; @@ -361,25 +361,25 @@ static rt_bool_t photo_view_event_handler(rtgui_object_t *object, rtgui_event_t return RT_TRUE; } - return result; + return result; } static rt_bool_t photo_lable_event_handler(rtgui_object_t *object, rtgui_event_t *event) { - rt_bool_t result = RT_FALSE; + rt_bool_t result = RT_FALSE; - result = rtgui_label_event_handler(object, event); + result = rtgui_label_event_handler(object, event); rt_kprintf("lable event %x\n", event->type); if (event->type == RTGUI_EVENT_COMMAND) - { + { struct photo_event *photo = (struct photo_event *)event; rtgui_label_set_text((rtgui_label_t *)object, photo->path); rt_kprintf("path %s\n", photo->path); } - return result; + return result; } static void app_photo(void *parameter) @@ -399,64 +399,64 @@ static void app_photo(void *parameter) lcd->control(lcd, RTGRAPHIC_CTRL_GET_INFO, (void *)&lcd_info); rt_kprintf("LCD size: %dX%d\n", lcd_info.width, lcd_info.height); - /* create application */ - struct rtgui_app *app; - app = rtgui_app_create("pho_app"); - if (app == RT_NULL) + /* create application */ + struct rtgui_app *app; + app = rtgui_app_create("pho_app"); + if (app == RT_NULL) { rt_kprintf("Create application \"pho_app\" failed!\n"); return; } - struct rtgui_rect rect1, rect2; + struct rtgui_rect rect1, rect2; struct rtgui_win *window; - struct rtgui_container *container; + struct rtgui_container *container; struct rtgui_label* label; - rtgui_graphic_driver_get_rect(rtgui_graphic_driver_get_default(), &rect1); + rtgui_graphic_driver_get_rect(rtgui_graphic_driver_get_default(), &rect1); /* create window */ - window = rtgui_win_create(RT_NULL, "photo", + window = rtgui_win_create(RT_NULL, "photo", &rect1, RTGUI_WIN_STYLE_NO_BORDER | RTGUI_WIN_STYLE_NO_TITLE); - if (window == RT_NULL) - { + if (window == RT_NULL) + { rt_kprintf("Create window \"photo\" failed!\n"); - rtgui_app_destroy(app); + rtgui_app_destroy(app); return; - } + } event->win.wid = window; /* create container */ - container = rtgui_container_create(); - if (container == RT_NULL) - { + container = rtgui_container_create(); + if (container == RT_NULL) + { rt_kprintf("Create container failed!\n"); - return; - } - rtgui_widget_set_rect(RTGUI_WIDGET(container), &rect1); + return; + } + rtgui_widget_set_rect(RTGUI_WIDGET(container), &rect1); rtgui_object_set_event_handler(RTGUI_OBJECT(container), photo_view_event_handler); rtgui_container_add_child(RTGUI_CONTAINER(window), RTGUI_WIDGET(container)); /* create lable in info window */ - label = rtgui_label_create("Photo Frame Demo"); + label = rtgui_label_create("Photo Frame Demo"); if (label == RT_NULL) { rt_kprintf("Create lable failed!\n"); return; } - RTGUI_WIDGET_TEXTALIGN(RTGUI_WIDGET(label)) = RTGUI_ALIGN_LEFT; - RTGUI_WIDGET_BACKGROUND(RTGUI_WIDGET(label)) = white; + RTGUI_WIDGET_TEXTALIGN(RTGUI_WIDGET(label)) = RTGUI_ALIGN_LEFT; + RTGUI_WIDGET_BACKGROUND(RTGUI_WIDGET(label)) = white; RTGUI_WIDGET_FOREGROUND(RTGUI_WIDGET(label)) = blue; rect2.x1 = rect1.x1; rect2.y1 = rect1.y1; rect2.x2 = rect1.x2; rect2.y2 = 15; - rtgui_widget_set_rect(RTGUI_WIDGET(label), &rect2); + rtgui_widget_set_rect(RTGUI_WIDGET(label), &rect2); rtgui_object_set_event_handler(RTGUI_OBJECT(label), photo_lable_event_handler); - rtgui_container_add_child(container, RTGUI_WIDGET(label)); + rtgui_container_add_child(container, RTGUI_WIDGET(label)); rtgui_win_show(window, RT_FALSE); diff --git a/bsp/efm32/board.c b/bsp/efm32/board.c index cdd44767f1..ea8b0640d2 100644 --- a/bsp/efm32/board.c +++ b/bsp/efm32/board.c @@ -1,8 +1,8 @@ /***************************************************************************//** - * @file board.c - * @brief Board support of RT-Thread RTOS for EFM32 + * @file board.c + * @brief Board support of RT-Thread RTOS for EFM32 * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -10,12 +10,12 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes - * 2010-12-21 onelife Initial creation for EFM32 - * 2011-05-06 onelife Add EFM32 development kit and SPI Flash support - * 2011-07-12 onelife Add SWO output enable function - * 2011-12-08 onelife Add giant gecko development kit support - * 2011-12-09 onelife Add giant gecko support + * Date Author Notes + * 2010-12-21 onelife Initial creation for EFM32 + * 2011-05-06 onelife Add EFM32 development kit and SPI Flash support + * 2011-07-12 onelife Add SWO output enable function + * 2011-12-08 onelife Add giant gecko development kit support + * 2011-12-09 onelife Add giant gecko support * 2011-12-09 onelife Add LEUART module support * 2011-12-14 onelife Add LFXO enabling routine in driver initialization * function @@ -37,19 +37,19 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == RAM_MEM_BASE) || \ - ((VECTTAB) == FLASH_MEM_BASE)) -#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) +#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == RAM_MEM_BASE) || \ + ((VECTTAB) == FLASH_MEM_BASE)) +#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) /***************************************************************************//** * @addtogroup SysTick_clock_source * @{ ******************************************************************************/ #define SysTick_CLKSource_MASK ((rt_uint32_t)0x00000004) -#define SysTick_CLKSource_RTC ((rt_uint32_t)0x00000000) -#define SysTick_CLKSource_HFCORECLK ((rt_uint32_t)0x00000004) -#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_RTC) || \ - ((SOURCE) == SysTick_CLKSource_HFCORECLK)) +#define SysTick_CLKSource_RTC ((rt_uint32_t)0x00000000) +#define SysTick_CLKSource_HFCORECLK ((rt_uint32_t)0x00000004) +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_RTC) || \ + ((SOURCE) == SysTick_CLKSource_HFCORECLK)) /***************************************************************************//** * @} ******************************************************************************/ @@ -67,20 +67,20 @@ * @note * * @param[in] NVIC_VectTab - * Indicate the vector table is allocated in RAM or ROM + * Indicate the vector table is allocated in RAM or ROM * * @param[in] Offset * The vector table offset ******************************************************************************/ static void NVIC_SetVectorTable( - rt_uint32_t NVIC_VectTab, - rt_uint32_t Offset) + rt_uint32_t NVIC_VectTab, + rt_uint32_t Offset) { - /* Check the parameters */ - RT_ASSERT(IS_NVIC_VECTTAB(NVIC_VectTab)); - RT_ASSERT(IS_NVIC_OFFSET(Offset)); + /* Check the parameters */ + RT_ASSERT(IS_NVIC_VECTTAB(NVIC_VectTab)); + RT_ASSERT(IS_NVIC_OFFSET(Offset)); - SCB->VTOR = NVIC_VectTab | (Offset & (rt_uint32_t)0x1FFFFF80); + SCB->VTOR = NVIC_VectTab | (Offset & (rt_uint32_t)0x1FFFFF80); } /***************************************************************************//** @@ -95,19 +95,19 @@ static void NVIC_SetVectorTable( static void NVIC_Configuration(void) { #ifdef VECT_TAB_RAM - /* Set the vector table allocated at 0x20000000 */ - NVIC_SetVectorTable(RAM_MEM_BASE, 0x0); + /* Set the vector table allocated at 0x20000000 */ + NVIC_SetVectorTable(RAM_MEM_BASE, 0x0); #else /* VECT_TAB_FLASH */ - /* Set the vector table allocated at 0x00000000 */ - NVIC_SetVectorTable(FLASH_MEM_BASE, 0x0); + /* Set the vector table allocated at 0x00000000 */ + NVIC_SetVectorTable(FLASH_MEM_BASE, 0x0); #endif - /* Set NVIC Preemption Priority Bits: 0 bit for pre-emption, 4 bits for - subpriority */ - NVIC_SetPriorityGrouping(0x7UL); + /* Set NVIC Preemption Priority Bits: 0 bit for pre-emption, 4 bits for + subpriority */ + NVIC_SetPriorityGrouping(0x7UL); - /* Set Base Priority Mask Register */ - __set_BASEPRI(EFM32_BASE_PRI_DEFAULT); + /* Set Base Priority Mask Register */ + __set_BASEPRI(EFM32_BASE_PRI_DEFAULT); } /***************************************************************************//** @@ -119,13 +119,13 @@ static void NVIC_Configuration(void) * @note * * @param[in] SysTick_CLKSource - * Specifies the SysTick clock source. + * Specifies the SysTick clock source. * * @arg SysTick_CLKSource_HCLK_Div8 - * AHB clock divided by 8 selected as SysTick clock source. + * AHB clock divided by 8 selected as SysTick clock source. * * @arg SysTick_CLKSource_HCLK - * AHB clock selected as SysTick clock source. + * AHB clock selected as SysTick clock source. ******************************************************************************/ static void SysTick_CLKSourceConfig(rt_uint32_t SysTick_CLKSource) { @@ -184,14 +184,14 @@ static void SysTick_Configuration(void) /* Start LETIMER0 */ LETIMER_Init(LETIMER0, &letimerInit); #else - rt_uint32_t coreClk; - rt_uint32_t cnts; + rt_uint32_t coreClk; + rt_uint32_t cnts; - coreClk = SystemCoreClockGet(); - cnts = coreClk / RT_TICK_PER_SECOND; + coreClk = SystemCoreClockGet(); + cnts = coreClk / RT_TICK_PER_SECOND; - SysTick_Config(cnts); - SysTick_CLKSourceConfig(SysTick_CLKSource_HFCORECLK); + SysTick_Config(cnts); + SysTick_CLKSourceConfig(SysTick_CLKSource_HFCORECLK); #endif } @@ -206,9 +206,9 @@ static void SysTick_Configuration(void) ******************************************************************************/ void Swo_Configuration(void) { - rt_uint32_t *dwt_ctrl = (rt_uint32_t *) 0xE0001000; - rt_uint32_t *tpiu_prescaler = (rt_uint32_t *) 0xE0040010; - rt_uint32_t *tpiu_protocol = (rt_uint32_t *) 0xE00400F0; + rt_uint32_t *dwt_ctrl = (rt_uint32_t *) 0xE0001000; + rt_uint32_t *tpiu_prescaler = (rt_uint32_t *) 0xE0040010; + rt_uint32_t *tpiu_protocol = (rt_uint32_t *) 0xE00400F0; CMU->HFPERCLKEN0 |= CMU_HFPERCLKEN0_GPIO; /* Enable Serial wire output pin */ @@ -258,12 +258,12 @@ void Swo_Configuration(void) ******************************************************************************/ void rt_hw_board_init(void) { - /* Chip errata */ - CHIP_Init(); + /* Chip errata */ + CHIP_Init(); /* Initialize DVK board register access */ #if defined(EFM32_GXXX_DK) - DVK_init(); + DVK_init(); #elif defined(EFM32GG_DK3750) DVK_init(DVK_Init_EBI); @@ -272,12 +272,12 @@ void rt_hw_board_init(void) DVK_clearInterruptFlags(BC_INTFLAG_MASK); #endif - /* config NVIC Configuration */ - NVIC_Configuration(); + /* config NVIC Configuration */ + NVIC_Configuration(); #if defined(EFM32_USING_HFXO) - /* Configure external oscillator */ - SystemHFXOClockSet(EFM32_HFXO_FREQUENCY); + /* Configure external oscillator */ + SystemHFXOClockSet(EFM32_HFXO_FREQUENCY); /* Switching the CPU clock source to HFXO */ CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFXO); @@ -293,15 +293,15 @@ void rt_hw_board_init(void) #if defined(EFM32_SWO_ENABLE) /* Enable SWO */ - Swo_Configuration(); + Swo_Configuration(); #endif - /* Enable high frequency peripheral clock */ - CMU_ClockEnable(cmuClock_HFPER, true); - /* Enabling clock to the interface of the low energy modules */ - CMU_ClockEnable(cmuClock_CORELE, true); + /* Enable high frequency peripheral clock */ + CMU_ClockEnable(cmuClock_HFPER, true); + /* Enabling clock to the interface of the low energy modules */ + CMU_ClockEnable(cmuClock_CORELE, true); /* Enable GPIO clock */ - CMU_ClockEnable(cmuClock_GPIO, true); + CMU_ClockEnable(cmuClock_GPIO, true); /* Configure the SysTick */ SysTick_Configuration(); @@ -318,8 +318,8 @@ void rt_hw_board_init(void) ******************************************************************************/ void rt_hw_driver_init(void) { - /* Initialize DMA */ - rt_hw_dma_init(); + /* Initialize DMA */ + rt_hw_dma_init(); /* Select LFXO for specified module (and wait for it to stabilize) */ #if (!defined(EFM32_USING_LFXO) && defined(RT_USING_RTC)) @@ -331,11 +331,11 @@ void rt_hw_driver_init(void) #error "Low frequency clock source is needed for using LEUART" #endif - /* Initialize USART */ + /* Initialize USART */ #if (defined(RT_USING_USART0) || defined(RT_USING_USART1) || \ defined(RT_USING_USART2) || defined(RT_USING_UART0) || \ defined(RT_USING_UART1)) - rt_hw_usart_init(); + rt_hw_usart_init(); #endif /* Initialize LEUART */ @@ -343,7 +343,7 @@ void rt_hw_driver_init(void) rt_hw_leuart_init(); #endif - /* Setup Console */ + /* Setup Console */ #if defined(EFM32_GXXX_DK) DVK_enablePeripheral(DVK_RS232A); DVK_enablePeripheral(DVK_SPI); @@ -354,31 +354,31 @@ void rt_hw_driver_init(void) DVK_enablePeripheral(DVK_RS232_LEUART); #endif #endif - rt_console_set_device(CONSOLE_DEVICE); + rt_console_set_device(CONSOLE_DEVICE); - /* Initialize Timer */ + /* Initialize Timer */ #if (defined(RT_USING_TIMER0) || defined(RT_USING_TIMER1) || defined(RT_USING_TIMER2)) - rt_hw_timer_init(); + rt_hw_timer_init(); #endif - /* Initialize ADC */ + /* Initialize ADC */ #if defined(RT_USING_ADC0) - rt_hw_adc_init(); + rt_hw_adc_init(); #endif - /* Initialize ACMP */ + /* Initialize ACMP */ #if (defined(RT_USING_ACMP0) || defined(RT_USING_ACMP1)) - rt_hw_acmp_init(); + rt_hw_acmp_init(); #endif - /* Initialize IIC */ + /* Initialize IIC */ #if (defined(RT_USING_IIC0) || defined(RT_USING_IIC1)) - rt_hw_iic_init(); + rt_hw_iic_init(); #endif - /* Initialize RTC */ + /* Initialize RTC */ #if defined(RT_USING_RTC) - rt_hw_rtc_init(); + rt_hw_rtc_init(); #endif /* Enable SPI access to MicroSD card */ diff --git a/bsp/efm32/board.h b/bsp/efm32/board.h index a97b0d9bc0..b92e10194b 100644 --- a/bsp/efm32/board.h +++ b/bsp/efm32/board.h @@ -1,8 +1,8 @@ /***************************************************************************//** - * @file board.h - * @brief Board support of RT-Thread RTOS for EFM32 + * @file board.h + * @brief Board support of RT-Thread RTOS for EFM32 * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -10,18 +10,18 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes - * 2010-12-21 onelife Initial creation for EFM32 - * 2011-05-06 onelife Add EFM32 development kit and SPI Flash support - * 2011-07-12 onelife Add prototype for SWO output enable and interrupt + * Date Author Notes + * 2010-12-21 onelife Initial creation for EFM32 + * 2011-05-06 onelife Add EFM32 development kit and SPI Flash support + * 2011-07-12 onelife Add prototype for SWO output enable and interrupt * context check functions - * 2011-12-08 onelife Add giant gecko development kit support - * 2011-12-09 onelife Add giant gecko support + * 2011-12-08 onelife Add giant gecko development kit support + * 2011-12-09 onelife Add giant gecko support * 2011-12-09 onelife Add LEUART module support * 2011-12-14 onelife Add LFXO enabling routine in driver initialization * function * 2011-12-20 onelife Move SPI Auto-CS setting to "rtconfig.h" - * 2012-05-15 onelife Modified to compatible with CMSIS v3 + * 2012-05-15 onelife Modified to compatible with CMSIS v3 ******************************************************************************/ #ifndef __BOARD_H__ #define __BOARD_H__ @@ -72,15 +72,15 @@ extern volatile rt_uint32_t rt_system_status; #define EFM32_SWO_ENABLE #endif -#define EFM32_NO_DATA (0) -#define EFM32_NO_POINTER (RT_NULL) -#define EFM32_NO_OFFSET (-1) -#define EFM32_NO_DMA (-1) +#define EFM32_NO_DATA (0) +#define EFM32_NO_POINTER (RT_NULL) +#define EFM32_NO_OFFSET (-1) +#define EFM32_NO_DMA (-1) /* SECTION: SPI Flash */ #if defined(EFM32_USING_SFLASH) -#define SFLASH_CS_PORT (gpioPortC) -#define SFLASH_CS_PIN (8) +#define SFLASH_CS_PORT (gpioPortC) +#define SFLASH_CS_PIN (8) #endif /* SECTION: Micro SD */ @@ -114,9 +114,9 @@ extern volatile rt_uint32_t rt_system_status; #endif /* SECTION: SYSTEM */ -#define EFM32_SRAM_END (SRAM_BASE + SRAM_SIZE) -#define EFM32_BASE_PRI_DEFAULT (0x0UL << 5) -#define EFM32_IRQ_PRI_DEFAULT (0x4UL << 5) +#define EFM32_SRAM_END (SRAM_BASE + SRAM_SIZE) +#define EFM32_BASE_PRI_DEFAULT (0x0UL << 5) +#define EFM32_IRQ_PRI_DEFAULT (0x4UL << 5) /* SECTION: CLOCK */ #define EFM32_USING_HFXO @@ -125,9 +125,9 @@ extern volatile rt_uint32_t rt_system_status; #if (defined(EFM32_G8XX_STK) || defined(EFM32_GXXX_DK)) #define EFM32_HFXO_FREQUENCY (32000000) #elif defined(EFM32GG_DK3750) - #define EFM32_HFXO_FREQUENCY (48000000) + #define EFM32_HFXO_FREQUENCY (48000000) #else - #define EFM32_HFXO_FREQUENCY (00000000) + #define EFM32_HFXO_FREQUENCY (00000000) #endif #endif #if defined(EFM32_USING_LFXO) @@ -141,8 +141,8 @@ extern volatile rt_uint32_t rt_system_status; #endif /* SECTION: USART */ -#define USART_RX_BUFFER_SIZE (64) -#define LEUART_RX_BUFFER_SIZE (64) +#define USART_RX_BUFFER_SIZE (64) +#define LEUART_RX_BUFFER_SIZE (64) /* Location count (start from 0) */ #if defined(_EFM32_GECKO_FAMILY) #define EFM32_USART_LOCATION_COUNT (3) @@ -155,14 +155,14 @@ extern volatile rt_uint32_t rt_system_status; #endif /* SUBSECTION: UART */ -#define UART_BAUDRATE (115200) +#define UART_BAUDRATE (115200) /* SUBSECTION: SPI */ /* Max SPI clock: HFPERCLK/2 for master, HFPERCLK/8 for slave */ -#define SPI_BAUDRATE (4000000) +#define SPI_BAUDRATE (4000000) /* SECTION: I2C */ -#define IIC_RX_BUFFER_SIZE (32) +#define IIC_RX_BUFFER_SIZE (32) #if defined(_EFM32_GECKO_FAMILY) #define EFM32_IIC_LOCATION_COUNT (4) #elif defined(_EFM32_GIANT_FAMILY) @@ -170,61 +170,61 @@ extern volatile rt_uint32_t rt_system_status; #endif /* SECTION: ADC */ -#define ADC_CALI_REF (adcRef2V5) -#define ADC_CALI_CH (adcSingleInpCh5) -#define ADC_CONVERT_FREQUENCY (7000000) +#define ADC_CALI_REF (adcRef2V5) +#define ADC_CALI_CH (adcSingleInpCh5) +#define ADC_CONVERT_FREQUENCY (7000000) #if (RT_CONSOLE_DEVICE == EFM_USART0) -#define CONSOLE_DEVICE RT_USART0_NAME +#define CONSOLE_DEVICE RT_USART0_NAME #elif (RT_CONSOLE_DEVICE == EFM_USART1) -#define CONSOLE_DEVICE RT_USART1_NAME +#define CONSOLE_DEVICE RT_USART1_NAME #elif (RT_CONSOLE_DEVICE == EFM_USART2) -#define CONSOLE_DEVICE RT_USART2_NAME +#define CONSOLE_DEVICE RT_USART2_NAME #elif (RT_CONSOLE_DEVICE == EFM_UART0) -#define CONSOLE_DEVICE RT_UART0_NAME +#define CONSOLE_DEVICE RT_UART0_NAME #elif (RT_CONSOLE_DEVICE == EFM_UART1) -#define CONSOLE_DEVICE RT_UART1_NAME +#define CONSOLE_DEVICE RT_UART1_NAME #elif (RT_CONSOLE_DEVICE == EFM_LEUART0) -#define CONSOLE_DEVICE RT_LEUART0_NAME +#define CONSOLE_DEVICE RT_LEUART0_NAME #elif (RT_CONSOLE_DEVICE == EFM_LEUART1) -#define CONSOLE_DEVICE RT_LEUART1_NAME +#define CONSOLE_DEVICE RT_LEUART1_NAME #else -#define CONSOLE_DEVICE "NONE" +#define CONSOLE_DEVICE "NONE" #endif /* The following defines should be consistent with those in diskio.h */ -#define CTRL_SYNC 0 -#define GET_SECTOR_COUNT 1 -#define GET_SECTOR_SIZE 2 -#define GET_BLOCK_SIZE 3 -#define MMC_GET_TYPE 10 -#define MMC_GET_CSD 11 -#define MMC_GET_CID 12 -#define MMC_GET_OCR 13 -#define MMC_GET_SDSTAT 14 +#define CTRL_SYNC 0 +#define GET_SECTOR_COUNT 1 +#define GET_SECTOR_SIZE 2 +#define GET_BLOCK_SIZE 3 +#define MMC_GET_TYPE 10 +#define MMC_GET_CSD 11 +#define MMC_GET_CID 12 +#define MMC_GET_OCR 13 +#define MMC_GET_SDSTAT 14 /* The above defines should be consistent with those in diskio.h */ /* I/O control options */ -#define RT_DEVICE_CTRL_SD_SYNC CTRL_SYNC -#define RT_DEVICE_CTRL_SD_GET_SCOUNT GET_SECTOR_COUNT -#define RT_DEVICE_CTRL_SD_GET_SSIZE GET_SECTOR_SIZE -#define RT_DEVICE_CTRL_SD_GET_BSIZE GET_BLOCK_SIZE -#define RT_DEVICE_CTRL_SD_GET_TYPE MMC_GET_TYPE -#define RT_DEVICE_CTRL_SD_GET_CSD MMC_GET_CSD -#define RT_DEVICE_CTRL_SD_GET_CID MMC_GET_CID -#define RT_DEVICE_CTRL_SD_GET_OCR MMC_GET_OCR -#define RT_DEVICE_CTRL_SD_GET_SDSTAT MMC_GET_SDSTAT +#define RT_DEVICE_CTRL_SD_SYNC CTRL_SYNC +#define RT_DEVICE_CTRL_SD_GET_SCOUNT GET_SECTOR_COUNT +#define RT_DEVICE_CTRL_SD_GET_SSIZE GET_SECTOR_SIZE +#define RT_DEVICE_CTRL_SD_GET_BSIZE GET_BLOCK_SIZE +#define RT_DEVICE_CTRL_SD_GET_TYPE MMC_GET_TYPE +#define RT_DEVICE_CTRL_SD_GET_CSD MMC_GET_CSD +#define RT_DEVICE_CTRL_SD_GET_CID MMC_GET_CID +#define RT_DEVICE_CTRL_SD_GET_OCR MMC_GET_OCR +#define RT_DEVICE_CTRL_SD_GET_SDSTAT MMC_GET_SDSTAT /*! fixme: move the following define to Rtdef.h */ -#define RT_DEVICE_CTRL_USART_RBUFFER (0xF1) /*!< set USART/UART rx buffer */ -#define RT_DEVICE_CTRL_LEUART_RBUFFER (0xF2) /*!< set LEUART rx buffer */ -#define RT_DEVICE_CTRL_IIC_SETTING (0xF3) /*!< change IIC setting */ -#define RT_DEVICE_CTRL_TIMER_PERIOD (0xF4) /*!< set Timer timeout period */ -#define RT_DEVICE_CTRL_ADC_MODE (0xF5) /*!< change ADC mode */ -#define RT_DEVICE_CTRL_ADC_RESULT (0xF6) /*!< get ADC result */ -#define RT_DEVICE_CTRL_ACMP_INIT (0xF7) /*!< Initialize ACMP */ -#define RT_DEVICE_CTRL_ACMP_OUTPUT (0xF8) /*!< get ACMP output */ +#define RT_DEVICE_CTRL_USART_RBUFFER (0xF1) /*!< set USART/UART rx buffer */ +#define RT_DEVICE_CTRL_LEUART_RBUFFER (0xF2) /*!< set LEUART rx buffer */ +#define RT_DEVICE_CTRL_IIC_SETTING (0xF3) /*!< change IIC setting */ +#define RT_DEVICE_CTRL_TIMER_PERIOD (0xF4) /*!< set Timer timeout period */ +#define RT_DEVICE_CTRL_ADC_MODE (0xF5) /*!< change ADC mode */ +#define RT_DEVICE_CTRL_ADC_RESULT (0xF6) /*!< get ADC result */ +#define RT_DEVICE_CTRL_ACMP_INIT (0xF7) /*!< Initialize ACMP */ +#define RT_DEVICE_CTRL_ACMP_OUTPUT (0xF8) /*!< get ACMP output */ /* Exported functions ------------------------------------------------------- */ void rt_hw_board_init(void); diff --git a/bsp/efm32/copy_this_file_dfs_elm.c b/bsp/efm32/copy_this_file_dfs_elm.c index a6adbce114..8d36dd7c88 100644 --- a/bsp/efm32/copy_this_file_dfs_elm.c +++ b/bsp/efm32/copy_this_file_dfs_elm.c @@ -9,7 +9,7 @@ * 2011-10-08 Bernard fixed the block size in statfs. * 2011-11-23 Bernard fixed the rename issue. */ - + #include #include "ffconf.h" #include "ff.h" @@ -30,658 +30,658 @@ static rt_device_t disk[_VOLUMES] = {0}; static int elm_result_to_dfs(FRESULT result) { - int status = DFS_STATUS_OK; - - switch (result) - { - case FR_OK: - break; + int status = DFS_STATUS_OK; - case FR_NO_FILE: - case FR_NO_PATH: - case FR_NO_FILESYSTEM: - status = -DFS_STATUS_ENOENT; - break; - - case FR_INVALID_NAME: - status = -DFS_STATUS_EINVAL; - break; + switch (result) + { + case FR_OK: + break; + + case FR_NO_FILE: + case FR_NO_PATH: + case FR_NO_FILESYSTEM: + status = -DFS_STATUS_ENOENT; + break; + + case FR_INVALID_NAME: + status = -DFS_STATUS_EINVAL; + break; + + case FR_EXIST: + case FR_INVALID_OBJECT: + status = -DFS_STATUS_EEXIST; + break; + + case FR_DISK_ERR: + case FR_NOT_READY: + case FR_INT_ERR: + status = -DFS_STATUS_EIO; + break; + + case FR_WRITE_PROTECTED: + case FR_DENIED: + status = -DFS_STATUS_EROFS; + break; + + case FR_MKFS_ABORTED: + status = -DFS_STATUS_EINVAL; + break; + + default: + status = -1; + break; + } - case FR_EXIST: - case FR_INVALID_OBJECT: - status = -DFS_STATUS_EEXIST; - break; + return status; +} - case FR_DISK_ERR: - case FR_NOT_READY: - case FR_INT_ERR: - status = -DFS_STATUS_EIO; - break; +int dfs_elm_mount(struct dfs_filesystem *fs, unsigned long rwflag, const void *data) +{ + FATFS *fat; + FRESULT result; + rt_uint32_t index; - case FR_WRITE_PROTECTED: - case FR_DENIED: - status = -DFS_STATUS_EROFS; - break; + /* handle RT-Thread device routine */ + for (index = 0; index < _VOLUMES; index ++) + { + if (disk[index] == RT_NULL) + { + break; + } + } + if (index == _VOLUMES) + return -DFS_STATUS_ENOSPC; - case FR_MKFS_ABORTED: - status = -DFS_STATUS_EINVAL; - break; + /* get device */ + disk[index] = fs->dev_id; - default: - status = -1; - break; - } + fat = (FATFS *)rt_malloc(sizeof(FATFS)); + if (fat == RT_NULL) + { + return -1; + } - return status; -} + /* mount fatfs, always 0 logic driver */ + result = f_mount(index, fat); + if (result == FR_OK) + fs->data = fat; + else + { + rt_free(fat); + return elm_result_to_dfs(result); + } -int dfs_elm_mount(struct dfs_filesystem *fs, unsigned long rwflag, const void *data) -{ - FATFS *fat; - FRESULT result; - rt_uint32_t index; - - /* handle RT-Thread device routine */ - for (index = 0; index < _VOLUMES; index ++) - { - if (disk[index] == RT_NULL) - { - break; - } - } - if (index == _VOLUMES) - return -DFS_STATUS_ENOSPC; - - /* get device */ - disk[index] = fs->dev_id; - - fat = (FATFS *)rt_malloc(sizeof(FATFS)); - if (fat == RT_NULL) - { - return -1; - } - - /* mount fatfs, always 0 logic driver */ - result = f_mount(index, fat); - if (result == FR_OK) - fs->data = fat; - else - { - rt_free(fat); - return elm_result_to_dfs(result); - } - - return 0; + return 0; } int dfs_elm_unmount(struct dfs_filesystem *fs) { - FATFS *fat; - FRESULT result; - rt_uint32_t index; + FATFS *fat; + FRESULT result; + rt_uint32_t index; - fat = (FATFS *)fs->data; + fat = (FATFS *)fs->data; - RT_ASSERT(fat != RT_NULL); + RT_ASSERT(fat != RT_NULL); - /* find the device index and then umount it */ - for (index = 0; index < _VOLUMES; index ++) - { - if (disk[index] == fs->dev_id) - { - result = f_mount(index, RT_NULL); - - if (result == FR_OK) - { - fs->data = RT_NULL; - disk[index] = RT_NULL; - rt_free(fat); - return DFS_STATUS_OK; - } - } - } + /* find the device index and then umount it */ + for (index = 0; index < _VOLUMES; index ++) + { + if (disk[index] == fs->dev_id) + { + result = f_mount(index, RT_NULL); + + if (result == FR_OK) + { + fs->data = RT_NULL; + disk[index] = RT_NULL; + rt_free(fat); + return DFS_STATUS_OK; + } + } + } - return -DFS_STATUS_ENOENT; + return -DFS_STATUS_ENOENT; } int dfs_elm_mkfs(const char *device_name) { - BYTE drv; - rt_device_t dev; - FRESULT result; - - /* find device name */ - for (drv = 0; drv < _VOLUMES; drv ++) - { - dev = disk[drv]; - if (rt_strncmp(dev->parent.name, device_name, RT_NAME_MAX) == 0) - { - /* 1: no partition table */ - /* 0: auto selection of cluster size */ - result = f_mkfs(drv, 1, 0); - if (result != FR_OK) - { - rt_kprintf("format error\n"); - return elm_result_to_dfs(result); - } - - return DFS_STATUS_OK; - } - } - - /* can't find device driver */ - rt_kprintf("can not find device driver: %s\n", device_name); - return -DFS_STATUS_EIO; + BYTE drv; + rt_device_t dev; + FRESULT result; + + /* find device name */ + for (drv = 0; drv < _VOLUMES; drv ++) + { + dev = disk[drv]; + if (rt_strncmp(dev->parent.name, device_name, RT_NAME_MAX) == 0) + { + /* 1: no partition table */ + /* 0: auto selection of cluster size */ + result = f_mkfs(drv, 1, 0); + if (result != FR_OK) + { + rt_kprintf("format error\n"); + return elm_result_to_dfs(result); + } + + return DFS_STATUS_OK; + } + } + + /* can't find device driver */ + rt_kprintf("can not find device driver: %s\n", device_name); + return -DFS_STATUS_EIO; } int dfs_elm_statfs(struct dfs_filesystem *fs, struct statfs *buf) { - FATFS *f; - FRESULT res; - char driver[4]; - DWORD fre_clust, fre_sect, tot_sect; + FATFS *f; + FRESULT res; + char driver[4]; + DWORD fre_clust, fre_sect, tot_sect; - RT_ASSERT(fs != RT_NULL); - RT_ASSERT(buf != RT_NULL); + RT_ASSERT(fs != RT_NULL); + RT_ASSERT(buf != RT_NULL); - f = (FATFS *)fs->data; + f = (FATFS *)fs->data; - rt_snprintf(driver, sizeof(driver), "%d:", f->drv); - res = f_getfree(driver, &fre_clust, &f); - if (res) - return elm_result_to_dfs(res); + rt_snprintf(driver, sizeof(driver), "%d:", f->drv); + res = f_getfree(driver, &fre_clust, &f); + if (res) + return elm_result_to_dfs(res); - /* Get total sectors and free sectors */ - tot_sect = (f->n_fatent - 2) * f->csize; - fre_sect = fre_clust * f->csize; + /* Get total sectors and free sectors */ + tot_sect = (f->n_fatent - 2) * f->csize; + fre_sect = fre_clust * f->csize; - buf->f_bfree = fre_sect; - buf->f_blocks = tot_sect; + buf->f_bfree = fre_sect; + buf->f_blocks = tot_sect; #if _MAX_SS != 512 - buf->f_bsize = f->ssize; + buf->f_bsize = f->ssize; #else buf->f_bsize = 512; #endif - return 0; + return 0; } int dfs_elm_open(struct dfs_fd *file) { - FIL *fd; - BYTE mode; - FRESULT result; - char *drivers_fn; + FIL *fd; + BYTE mode; + FRESULT result; + char *drivers_fn; #if (_VOLUMES > 1) - int vol; - extern int elm_get_vol(FATFS *fat); - - /* add path for ELM FatFS driver support */ - vol = elm_get_vol((FATFS *)file->fs->data); - if (vol < 0) - return -DFS_STATUS_ENOENT; - drivers_fn = rt_malloc(256); - if (drivers_fn == RT_NULL) - return -DFS_STATUS_ENOMEM; - - rt_snprintf(drivers_fn, 256, "%d:%s", vol, file->path); + int vol; + extern int elm_get_vol(FATFS *fat); + + /* add path for ELM FatFS driver support */ + vol = elm_get_vol((FATFS *)file->fs->data); + if (vol < 0) + return -DFS_STATUS_ENOENT; + drivers_fn = rt_malloc(256); + if (drivers_fn == RT_NULL) + return -DFS_STATUS_ENOMEM; + + rt_snprintf(drivers_fn, 256, "%d:%s", vol, file->path); #else - drivers_fn = file->path; + drivers_fn = file->path; #endif - if (file->flags & DFS_O_DIRECTORY) - { - DIR *dir; + if (file->flags & DFS_O_DIRECTORY) + { + DIR *dir; - if (file->flags & DFS_O_CREAT) - { - result = f_mkdir(drivers_fn); - if (result != FR_OK) - { + if (file->flags & DFS_O_CREAT) + { + result = f_mkdir(drivers_fn); + if (result != FR_OK) + { #if _VOLUMES > 1 - rt_free(drivers_fn); + rt_free(drivers_fn); #endif - return elm_result_to_dfs(result); - } - } - - /* open directory */ - dir = (DIR *)rt_malloc(sizeof(DIR)); - if (dir == RT_NULL) - { + return elm_result_to_dfs(result); + } + } + + /* open directory */ + dir = (DIR *)rt_malloc(sizeof(DIR)); + if (dir == RT_NULL) + { #if _VOLUMES > 1 - rt_free(drivers_fn); + rt_free(drivers_fn); #endif - return -DFS_STATUS_ENOMEM; - } + return -DFS_STATUS_ENOMEM; + } - result = f_opendir(dir, drivers_fn); + result = f_opendir(dir, drivers_fn); #if _VOLUMES > 1 - rt_free(drivers_fn); + rt_free(drivers_fn); #endif - if (result != FR_OK) - { - rt_free(dir); - return elm_result_to_dfs(result); - } - - file->data = dir; - return DFS_STATUS_OK; - } - else - { - mode = FA_READ; - - if (file->flags & DFS_O_WRONLY) - mode |= FA_WRITE; - if ((file->flags & DFS_O_ACCMODE) & DFS_O_RDWR) - mode |= FA_WRITE; - /* Opens the file, if it is existing. If not, a new file is created. */ - if (file->flags & DFS_O_CREAT) - mode |= FA_OPEN_ALWAYS; - /* Creates a new file. If the file is existing, it is truncated and overwritten. */ - if (file->flags & DFS_O_TRUNC) - mode |= FA_CREATE_ALWAYS; - /* Creates a new file. The function fails if the file is already existing. */ - if (file->flags & DFS_O_EXCL) - mode |= FA_CREATE_NEW; - - /* allocate a fd */ - fd = (FIL *)rt_malloc(sizeof(FIL)); - if (fd == RT_NULL) - { - return -DFS_STATUS_ENOMEM; - } - - result = f_open(fd, drivers_fn, mode); + if (result != FR_OK) + { + rt_free(dir); + return elm_result_to_dfs(result); + } + + file->data = dir; + return DFS_STATUS_OK; + } + else + { + mode = FA_READ; + + if (file->flags & DFS_O_WRONLY) + mode |= FA_WRITE; + if ((file->flags & DFS_O_ACCMODE) & DFS_O_RDWR) + mode |= FA_WRITE; + /* Opens the file, if it is existing. If not, a new file is created. */ + if (file->flags & DFS_O_CREAT) + mode |= FA_OPEN_ALWAYS; + /* Creates a new file. If the file is existing, it is truncated and overwritten. */ + if (file->flags & DFS_O_TRUNC) + mode |= FA_CREATE_ALWAYS; + /* Creates a new file. The function fails if the file is already existing. */ + if (file->flags & DFS_O_EXCL) + mode |= FA_CREATE_NEW; + + /* allocate a fd */ + fd = (FIL *)rt_malloc(sizeof(FIL)); + if (fd == RT_NULL) + { + return -DFS_STATUS_ENOMEM; + } + + result = f_open(fd, drivers_fn, mode); #if _VOLUMES > 1 - rt_free(drivers_fn); + rt_free(drivers_fn); #endif - if (result == FR_OK) - { - file->pos = fd->fptr; - file->size = fd->fsize; - file->data = fd; - - if (file->flags & DFS_O_APPEND) - { - file->pos = f_lseek(fd, fd->fsize); - } - } - else - { - /* open failed, return */ - rt_free(fd); - return elm_result_to_dfs(result); - } - } - - return DFS_STATUS_OK; + if (result == FR_OK) + { + file->pos = fd->fptr; + file->size = fd->fsize; + file->data = fd; + + if (file->flags & DFS_O_APPEND) + { + file->pos = f_lseek(fd, fd->fsize); + } + } + else + { + /* open failed, return */ + rt_free(fd); + return elm_result_to_dfs(result); + } + } + + return DFS_STATUS_OK; } int dfs_elm_close(struct dfs_fd *file) { - FRESULT result; - - result = FR_OK; - if (file->type == FT_DIRECTORY) - { - DIR *dir; + FRESULT result; - dir = (DIR *)(file->data); - RT_ASSERT(dir != RT_NULL); + result = FR_OK; + if (file->type == FT_DIRECTORY) + { + DIR *dir; - /* release memory */ - rt_free(dir); - } - else if (file->type == FT_REGULAR) - { - FIL *fd; - fd = (FIL *)(file->data); - RT_ASSERT(fd != RT_NULL); + dir = (DIR *)(file->data); + RT_ASSERT(dir != RT_NULL); - result = f_close(fd); - if (result == FR_OK) - { - /* release memory */ - rt_free(fd); - } - } + /* release memory */ + rt_free(dir); + } + else if (file->type == FT_REGULAR) + { + FIL *fd; + fd = (FIL *)(file->data); + RT_ASSERT(fd != RT_NULL); + + result = f_close(fd); + if (result == FR_OK) + { + /* release memory */ + rt_free(fd); + } + } - return elm_result_to_dfs(result); + return elm_result_to_dfs(result); } -int dfs_elm_ioctl(struct dfs_fd *file, int cmd, void *args) +int dfs_elm_ioctl(struct dfs_fd *file, int cmd, void *args) { - return -DFS_STATUS_ENOSYS; + return -DFS_STATUS_ENOSYS; } int dfs_elm_read(struct dfs_fd *file, void *buf, rt_size_t len) { - FIL *fd; - FRESULT result; - UINT byte_read; + FIL *fd; + FRESULT result; + UINT byte_read; - if (file->type == FT_DIRECTORY) - { - return -DFS_STATUS_EISDIR; - } + if (file->type == FT_DIRECTORY) + { + return -DFS_STATUS_EISDIR; + } - fd = (FIL *)(file->data); - RT_ASSERT(fd != RT_NULL); + fd = (FIL *)(file->data); + RT_ASSERT(fd != RT_NULL); - result = f_read(fd, buf, len, &byte_read); - /* update position */ - file->pos = fd->fptr; - if (result == FR_OK) - return byte_read; + result = f_read(fd, buf, len, &byte_read); + /* update position */ + file->pos = fd->fptr; + if (result == FR_OK) + return byte_read; - return elm_result_to_dfs(result); + return elm_result_to_dfs(result); } int dfs_elm_write(struct dfs_fd *file, const void *buf, rt_size_t len) { - FIL *fd; - FRESULT result; - UINT byte_write; + FIL *fd; + FRESULT result; + UINT byte_write; - if (file->type == FT_DIRECTORY) - { - return -DFS_STATUS_EISDIR; - } + if (file->type == FT_DIRECTORY) + { + return -DFS_STATUS_EISDIR; + } - fd = (FIL *)(file->data); - RT_ASSERT(fd != RT_NULL); + fd = (FIL *)(file->data); + RT_ASSERT(fd != RT_NULL); - result = f_write(fd, buf, len, &byte_write); - /* update position and file size */ - file->pos = fd->fptr; - file->size = fd->fsize; - if (result == FR_OK) - return byte_write; + result = f_write(fd, buf, len, &byte_write); + /* update position and file size */ + file->pos = fd->fptr; + file->size = fd->fsize; + if (result == FR_OK) + return byte_write; - return elm_result_to_dfs(result); + return elm_result_to_dfs(result); } int dfs_elm_flush(struct dfs_fd *file) { - FIL *fd; - FRESULT result; + FIL *fd; + FRESULT result; - fd = (FIL *)(file->data); - RT_ASSERT(fd != RT_NULL); + fd = (FIL *)(file->data); + RT_ASSERT(fd != RT_NULL); - result = f_sync(fd); - return elm_result_to_dfs(result); + result = f_sync(fd); + return elm_result_to_dfs(result); } int dfs_elm_lseek(struct dfs_fd *file, rt_off_t offset) { - FRESULT result = FR_OK; - if (file->type == FT_REGULAR) - { - FIL *fd; - - /* regular file type */ - fd = (FIL *)(file->data); - RT_ASSERT(fd != RT_NULL); - - result = f_lseek(fd, offset); - if (result == FR_OK) - { - /* return current position */ - return fd->fptr; - } - } - else if (file->type == FT_DIRECTORY) - { - /* which is a directory */ - DIR *dir; - - dir = (DIR *)(file->data); - RT_ASSERT(dir != RT_NULL); - - result = f_seekdir(dir, offset / sizeof(struct dirent)); - if (result == FR_OK) - { - /* update file position */ - file->pos = offset; - return file->pos; - } - } - - return elm_result_to_dfs(result); + FRESULT result = FR_OK; + if (file->type == FT_REGULAR) + { + FIL *fd; + + /* regular file type */ + fd = (FIL *)(file->data); + RT_ASSERT(fd != RT_NULL); + + result = f_lseek(fd, offset); + if (result == FR_OK) + { + /* return current position */ + return fd->fptr; + } + } + else if (file->type == FT_DIRECTORY) + { + /* which is a directory */ + DIR *dir; + + dir = (DIR *)(file->data); + RT_ASSERT(dir != RT_NULL); + + result = f_seekdir(dir, offset / sizeof(struct dirent)); + if (result == FR_OK) + { + /* update file position */ + file->pos = offset; + return file->pos; + } + } + + return elm_result_to_dfs(result); } int dfs_elm_getdents(struct dfs_fd *file, struct dirent *dirp, rt_uint32_t count) { - DIR *dir; - FILINFO fno; - FRESULT result; - rt_uint32_t index; - struct dirent *d; + DIR *dir; + FILINFO fno; + FRESULT result; + rt_uint32_t index; + struct dirent *d; - dir = (DIR *)(file->data); - RT_ASSERT(dir != RT_NULL); + dir = (DIR *)(file->data); + RT_ASSERT(dir != RT_NULL); - /* make integer count */ - count = (count / sizeof(struct dirent)) * sizeof(struct dirent); - if (count == 0) - return -DFS_STATUS_EINVAL; + /* make integer count */ + count = (count / sizeof(struct dirent)) * sizeof(struct dirent); + if (count == 0) + return -DFS_STATUS_EINVAL; #if _USE_LFN - /* allocate long file name */ - fno.lfname = rt_malloc(256); - fno.lfsize = 256; + /* allocate long file name */ + fno.lfname = rt_malloc(256); + fno.lfsize = 256; #endif - index = 0; - while (1) - { - char *fn; + index = 0; + while (1) + { + char *fn; - d = dirp + index; + d = dirp + index; - result = f_readdir(dir, &fno); - if (result != FR_OK || fno.fname[0] == 0) - break; + result = f_readdir(dir, &fno); + if (result != FR_OK || fno.fname[0] == 0) + break; #if _USE_LFN - fn = *fno.lfname? fno.lfname : fno.fname; + fn = *fno.lfname? fno.lfname : fno.fname; #else - fn = fno.fname; + fn = fno.fname; #endif - d->d_type = DFS_DT_UNKNOWN; - if (fno.fattrib & AM_DIR) - d->d_type = DFS_DT_DIR; - else - d->d_type = DFS_DT_REG; + d->d_type = DFS_DT_UNKNOWN; + if (fno.fattrib & AM_DIR) + d->d_type = DFS_DT_DIR; + else + d->d_type = DFS_DT_REG; - d->d_namlen = rt_strlen(fn); - d->d_reclen = (rt_uint16_t)sizeof(struct dirent); - rt_strncpy(d->d_name, fn, rt_strlen(fn) + 1); + d->d_namlen = rt_strlen(fn); + d->d_reclen = (rt_uint16_t)sizeof(struct dirent); + rt_strncpy(d->d_name, fn, rt_strlen(fn) + 1); - index ++; - if (index * sizeof(struct dirent) >= count) - break; - } + index ++; + if (index * sizeof(struct dirent) >= count) + break; + } #if _USE_LFN - rt_free(fno.lfname); + rt_free(fno.lfname); #endif - if (index == 0) - return elm_result_to_dfs(result); + if (index == 0) + return elm_result_to_dfs(result); - file->pos += index * sizeof(struct dirent); + file->pos += index * sizeof(struct dirent); - return index * sizeof(struct dirent); + return index * sizeof(struct dirent); } int dfs_elm_unlink(struct dfs_filesystem *fs, const char *path) { - FRESULT result; + FRESULT result; #if _VOLUMES > 1 - int vol; - char *drivers_fn; - extern int elm_get_vol(FATFS *fat); - - /* add path for ELM FatFS driver support */ - vol = elm_get_vol((FATFS *)fs->data); - if (vol < 0) - return -DFS_STATUS_ENOENT; - drivers_fn = rt_malloc(256); - if (drivers_fn == RT_NULL) - return -DFS_STATUS_ENOMEM; - - rt_snprintf(drivers_fn, 256, "%d:%s", vol, path); + int vol; + char *drivers_fn; + extern int elm_get_vol(FATFS *fat); + + /* add path for ELM FatFS driver support */ + vol = elm_get_vol((FATFS *)fs->data); + if (vol < 0) + return -DFS_STATUS_ENOENT; + drivers_fn = rt_malloc(256); + if (drivers_fn == RT_NULL) + return -DFS_STATUS_ENOMEM; + + rt_snprintf(drivers_fn, 256, "%d:%s", vol, path); #else - const char *drivers_fn; - drivers_fn = path; + const char *drivers_fn; + drivers_fn = path; #endif - result = f_unlink(drivers_fn); + result = f_unlink(drivers_fn); #if _VOLUMES > 1 - rt_free(drivers_fn); + rt_free(drivers_fn); #endif - return elm_result_to_dfs(result); + return elm_result_to_dfs(result); } int dfs_elm_rename(struct dfs_filesystem *fs, const char *oldpath, const char *newpath) { - FRESULT result; + FRESULT result; #if _VOLUMES > 1 - char *drivers_oldfn; - const char *drivers_newfn; - int vol; - extern int elm_get_vol(FATFS *fat); - - /* add path for ELM FatFS driver support */ - vol = elm_get_vol((FATFS *)fs->data); - if (vol < 0) - return -DFS_STATUS_ENOENT; - - drivers_oldfn = rt_malloc(256); - if (drivers_oldfn == RT_NULL) - return -DFS_STATUS_ENOMEM; - drivers_newfn = newpath; - - rt_snprintf(drivers_oldfn, 256, "%d:%s", vol, oldpath); + char *drivers_oldfn; + const char *drivers_newfn; + int vol; + extern int elm_get_vol(FATFS *fat); + + /* add path for ELM FatFS driver support */ + vol = elm_get_vol((FATFS *)fs->data); + if (vol < 0) + return -DFS_STATUS_ENOENT; + + drivers_oldfn = rt_malloc(256); + if (drivers_oldfn == RT_NULL) + return -DFS_STATUS_ENOMEM; + drivers_newfn = newpath; + + rt_snprintf(drivers_oldfn, 256, "%d:%s", vol, oldpath); #else - const char *drivers_oldfn, *drivers_newfn; + const char *drivers_oldfn, *drivers_newfn; - drivers_oldfn = oldpath; - drivers_newfn = newpath; + drivers_oldfn = oldpath; + drivers_newfn = newpath; #endif - result = f_rename(drivers_oldfn, drivers_newfn); + result = f_rename(drivers_oldfn, drivers_newfn); #if _VOLUMES > 1 - rt_free(drivers_oldfn); + rt_free(drivers_oldfn); #endif - return elm_result_to_dfs(result); + return elm_result_to_dfs(result); } int dfs_elm_stat(struct dfs_filesystem *fs, const char *path, struct stat *st) { - FILINFO file_info; - FRESULT result; + FILINFO file_info; + FRESULT result; #if _VOLUMES > 1 - int vol; - char *drivers_fn; - extern int elm_get_vol(FATFS *fat); - - /* add path for ELM FatFS driver support */ - vol = elm_get_vol((FATFS *)fs->data); - if (vol < 0) - return -DFS_STATUS_ENOENT; - drivers_fn = rt_malloc(256); - if (drivers_fn == RT_NULL) - return -DFS_STATUS_ENOMEM; - - rt_snprintf(drivers_fn, 256, "%d:%s", vol, path); + int vol; + char *drivers_fn; + extern int elm_get_vol(FATFS *fat); + + /* add path for ELM FatFS driver support */ + vol = elm_get_vol((FATFS *)fs->data); + if (vol < 0) + return -DFS_STATUS_ENOENT; + drivers_fn = rt_malloc(256); + if (drivers_fn == RT_NULL) + return -DFS_STATUS_ENOMEM; + + rt_snprintf(drivers_fn, 256, "%d:%s", vol, path); #else - const char *drivers_fn; - drivers_fn = path; + const char *drivers_fn; + drivers_fn = path; #endif #if _USE_LFN - /* allocate long file name */ - file_info.lfname = rt_malloc(256); - file_info.lfsize = 256; + /* allocate long file name */ + file_info.lfname = rt_malloc(256); + file_info.lfsize = 256; #endif - result = f_stat(drivers_fn, &file_info); + result = f_stat(drivers_fn, &file_info); #if _VOLUMES > 1 - rt_free(drivers_fn); + rt_free(drivers_fn); #endif - if (result == FR_OK) - { - /* convert to dfs stat structure */ - st->st_dev = 0; - - st->st_mode = DFS_S_IFREG | DFS_S_IRUSR | DFS_S_IRGRP | DFS_S_IROTH | - DFS_S_IWUSR | DFS_S_IWGRP | DFS_S_IWOTH; - if (file_info.fattrib & AM_DIR) - { - st->st_mode &= ~DFS_S_IFREG; - st->st_mode |= DFS_S_IFDIR | DFS_S_IXUSR | DFS_S_IXGRP | DFS_S_IXOTH; - } - if (file_info.fattrib & AM_RDO) - st->st_mode &= ~(DFS_S_IWUSR | DFS_S_IWGRP | DFS_S_IWOTH); - - st->st_size = file_info.fsize; - st->st_mtime = file_info.ftime; - } + if (result == FR_OK) + { + /* convert to dfs stat structure */ + st->st_dev = 0; + + st->st_mode = DFS_S_IFREG | DFS_S_IRUSR | DFS_S_IRGRP | DFS_S_IROTH | + DFS_S_IWUSR | DFS_S_IWGRP | DFS_S_IWOTH; + if (file_info.fattrib & AM_DIR) + { + st->st_mode &= ~DFS_S_IFREG; + st->st_mode |= DFS_S_IFDIR | DFS_S_IXUSR | DFS_S_IXGRP | DFS_S_IXOTH; + } + if (file_info.fattrib & AM_RDO) + st->st_mode &= ~(DFS_S_IWUSR | DFS_S_IWGRP | DFS_S_IWOTH); + + st->st_size = file_info.fsize; + st->st_mtime = file_info.ftime; + } #if _USE_LFN - rt_free(file_info.lfname); + rt_free(file_info.lfname); #endif - return elm_result_to_dfs(result); + return elm_result_to_dfs(result); } static const struct dfs_filesystem_operation dfs_elm = { - "elm", - dfs_elm_mount, - dfs_elm_unmount, - dfs_elm_mkfs, - dfs_elm_statfs, - - dfs_elm_open, - dfs_elm_close, - dfs_elm_ioctl, - dfs_elm_read, - dfs_elm_write, - dfs_elm_flush, - dfs_elm_lseek, - dfs_elm_getdents, - dfs_elm_unlink, - dfs_elm_stat, - dfs_elm_rename, + "elm", + dfs_elm_mount, + dfs_elm_unmount, + dfs_elm_mkfs, + dfs_elm_statfs, + + dfs_elm_open, + dfs_elm_close, + dfs_elm_ioctl, + dfs_elm_read, + dfs_elm_write, + dfs_elm_flush, + dfs_elm_lseek, + dfs_elm_getdents, + dfs_elm_unlink, + dfs_elm_stat, + dfs_elm_rename, }; int elm_init(void) { #ifdef DFS_ELMFAT_INTERFACE_EFM - int i; + int i; - for (i = 0; i < _VOLUMES; i++) - { - diskStat[i] = STA_NOINIT; - } + for (i = 0; i < _VOLUMES; i++) + { + diskStat[i] = STA_NOINIT; + } #endif /* register fatfs file system */ dfs_register(&dfs_elm); - return 0; + return 0; } /* @@ -692,70 +692,70 @@ int elm_init(void) /* Initialize Disk Drive */ /*-----------------------------------------------------------------------*/ DSTATUS disk_initialize ( - BYTE drv /* Physical drive nmuber */ - ) + BYTE drv /* Physical drive nmuber */ + ) { - rt_device_t device = disk[drv]; + rt_device_t device = disk[drv]; - if (!device) - { - return RES_ERROR; - } - if (diskStat[drv] & STA_NODISK) - { - /* No card in the socket */ - return diskStat[drv]; - } + if (!device) + { + return RES_ERROR; + } + if (diskStat[drv] & STA_NODISK) + { + /* No card in the socket */ + return diskStat[drv]; + } - /* Initialize hardware: the actual operation is performed in dfs_mount() */ - diskStat[drv] &= ~STA_NOINIT; + /* Initialize hardware: the actual operation is performed in dfs_mount() */ + diskStat[drv] &= ~STA_NOINIT; - return diskStat[drv]; + return diskStat[drv]; } /*-----------------------------------------------------------------------*/ /* Get Disk Status */ /*-----------------------------------------------------------------------*/ DSTATUS disk_status ( - BYTE drv /* Physical drive nmuber */ - ) + BYTE drv /* Physical drive nmuber */ + ) { - return diskStat[drv]; + return diskStat[drv]; } /*-----------------------------------------------------------------------*/ /* Read Sector(s) */ /*-----------------------------------------------------------------------*/ DRESULT disk_read ( - BYTE drv, /* Physical drive nmuber */ - BYTE *buff, /* Pointer to the data buffer to store read data */ - DWORD sector, /* Start sector number (LBA) */ - BYTE count /* Sector count (1..255) */ - ) -{ - rt_device_t device = disk[drv]; - - if (!device) - { - return RES_ERROR; - } - if (!count) - { - return RES_PARERR; - } - if (diskStat[drv] & STA_NOINIT) - { - return RES_NOTRDY; - } - - if (rt_device_read(device, sector, buff, count) != count) - { - return RES_ERROR; - } - else - { - return RES_OK; - } + BYTE drv, /* Physical drive nmuber */ + BYTE *buff, /* Pointer to the data buffer to store read data */ + DWORD sector, /* Start sector number (LBA) */ + BYTE count /* Sector count (1..255) */ + ) +{ + rt_device_t device = disk[drv]; + + if (!device) + { + return RES_ERROR; + } + if (!count) + { + return RES_PARERR; + } + if (diskStat[drv] & STA_NOINIT) + { + return RES_NOTRDY; + } + + if (rt_device_read(device, sector, buff, count) != count) + { + return RES_ERROR; + } + else + { + return RES_OK; + } } /*-----------------------------------------------------------------------*/ @@ -763,39 +763,39 @@ DRESULT disk_read ( /*-----------------------------------------------------------------------*/ #if _READONLY == 0 DRESULT disk_write ( - BYTE drv, /* Physical drive nmuber */ - const BYTE *buff, /* Pointer to the data to be written */ - DWORD sector, /* Start sector number (LBA) */ - BYTE count /* Sector count (1..255) */ - ) -{ - rt_device_t device = disk[drv]; - - if (!device) - { - return RES_ERROR; - } - if (!count) - { - return RES_PARERR; - } - if (diskStat[drv] & STA_NOINIT) - { - return RES_NOTRDY; - } - if (diskStat[drv] & STA_PROTECT) - { - return RES_WRPRT; - } - - if (rt_device_write(device, sector, buff, count) != count) - { - return RES_ERROR; - } - else - { - return RES_OK; - } + BYTE drv, /* Physical drive nmuber */ + const BYTE *buff, /* Pointer to the data to be written */ + DWORD sector, /* Start sector number (LBA) */ + BYTE count /* Sector count (1..255) */ + ) +{ + rt_device_t device = disk[drv]; + + if (!device) + { + return RES_ERROR; + } + if (!count) + { + return RES_PARERR; + } + if (diskStat[drv] & STA_NOINIT) + { + return RES_NOTRDY; + } + if (diskStat[drv] & STA_PROTECT) + { + return RES_WRPRT; + } + + if (rt_device_write(device, sector, buff, count) != count) + { + return RES_ERROR; + } + else + { + return RES_OK; + } } #endif /* _READONLY */ @@ -803,30 +803,30 @@ DRESULT disk_write ( /* Miscellaneous Functions */ /*-----------------------------------------------------------------------*/ DRESULT disk_ioctl ( - BYTE drv, /* Physical drive nmuber */ - BYTE ctrl, /* Control code */ - void *buff /* Buffer to send/receive data block */ + BYTE drv, /* Physical drive nmuber */ + BYTE ctrl, /* Control code */ + void *buff /* Buffer to send/receive data block */ ) { - rt_device_t device = disk[drv]; - - if (!device) - { - return RES_ERROR; - } - if (diskStat[drv] & STA_NOINIT) - { - return RES_NOTRDY; - } - - if (rt_device_control(device, ctrl, buff) != RT_EOK) - { - return RES_ERROR; - } - else - { - return RES_OK; - } + rt_device_t device = disk[drv]; + + if (!device) + { + return RES_ERROR; + } + if (diskStat[drv] & STA_NOINIT) + { + return RES_NOTRDY; + } + + if (rt_device_control(device, ctrl, buff) != RT_EOK) + { + return RES_ERROR; + } + else + { + return RES_OK; + } } #else #include "diskio.h" @@ -834,90 +834,90 @@ DRESULT disk_ioctl ( /* Inidialize a Drive */ DSTATUS disk_initialize(BYTE drv) { - return 0; + return 0; } /* Return Disk Status */ DSTATUS disk_status(BYTE drv) { - return 0; + return 0; } /* Read Sector(s) */ DRESULT disk_read(BYTE drv, BYTE *buff, DWORD sector, BYTE count) { - rt_size_t result; - rt_device_t device = disk[drv]; + rt_size_t result; + rt_device_t device = disk[drv]; - result = rt_device_read(device, sector, buff, count); - if (result == count) - { - return RES_OK; - } + result = rt_device_read(device, sector, buff, count); + if (result == count) + { + return RES_OK; + } - return RES_ERROR; + return RES_ERROR; } /* Write Sector(s) */ DRESULT disk_write(BYTE drv, const BYTE *buff, DWORD sector, BYTE count) { - rt_size_t result; - rt_device_t device = disk[drv]; + rt_size_t result; + rt_device_t device = disk[drv]; - result = rt_device_write(device, sector, buff, count); - if (result == count) - { - return RES_OK; - } + result = rt_device_write(device, sector, buff, count); + if (result == count) + { + return RES_OK; + } - return RES_ERROR; + return RES_ERROR; } /* Miscellaneous Functions */ DRESULT disk_ioctl(BYTE drv, BYTE ctrl, void *buff) { - rt_device_t device = disk[drv]; + rt_device_t device = disk[drv]; - if (device == RT_NULL) - return RES_ERROR; + if (device == RT_NULL) + return RES_ERROR; - if (ctrl == GET_SECTOR_COUNT) - { - struct rt_device_blk_geometry geometry; + if (ctrl == GET_SECTOR_COUNT) + { + struct rt_device_blk_geometry geometry; - rt_memset(&geometry, 0, sizeof(geometry)); - rt_device_control(device, RT_DEVICE_CTRL_BLK_GETGEOME, &geometry); + rt_memset(&geometry, 0, sizeof(geometry)); + rt_device_control(device, RT_DEVICE_CTRL_BLK_GETGEOME, &geometry); - *(DWORD *)buff = geometry.sector_count; - if (geometry.sector_count == 0) - return RES_ERROR; - } - else if (ctrl == GET_SECTOR_SIZE) - { - struct rt_device_blk_geometry geometry; + *(DWORD *)buff = geometry.sector_count; + if (geometry.sector_count == 0) + return RES_ERROR; + } + else if (ctrl == GET_SECTOR_SIZE) + { + struct rt_device_blk_geometry geometry; - rt_memset(&geometry, 0, sizeof(geometry)); - rt_device_control(device, RT_DEVICE_CTRL_BLK_GETGEOME, &geometry); + rt_memset(&geometry, 0, sizeof(geometry)); + rt_device_control(device, RT_DEVICE_CTRL_BLK_GETGEOME, &geometry); - *(WORD *)buff = geometry.bytes_per_sector; - } - else if (ctrl == GET_BLOCK_SIZE) /* Get erase block size in unit of sectors (DWORD) */ - { - struct rt_device_blk_geometry geometry; + *(WORD *)buff = geometry.bytes_per_sector; + } + else if (ctrl == GET_BLOCK_SIZE) /* Get erase block size in unit of sectors (DWORD) */ + { + struct rt_device_blk_geometry geometry; - rt_memset(&geometry, 0, sizeof(geometry)); - rt_device_control(device, RT_DEVICE_CTRL_BLK_GETGEOME, &geometry); + rt_memset(&geometry, 0, sizeof(geometry)); + rt_device_control(device, RT_DEVICE_CTRL_BLK_GETGEOME, &geometry); - *(DWORD *)buff = geometry.block_size/geometry.bytes_per_sector; - } + *(DWORD *)buff = geometry.block_size/geometry.bytes_per_sector; + } - return RES_OK; + return RES_OK; } #endif rt_time_t get_fattime(void) { - return 0; + return 0; } #if _FS_REENTRANT @@ -947,14 +947,14 @@ int ff_del_syncobj(_SYNC_t m) int ff_req_grant(_SYNC_t m) { if (rt_mutex_take(m, _FS_TIMEOUT) == RT_EOK) - return RT_TRUE; + return RT_TRUE; return RT_FALSE; } void ff_rel_grant(_SYNC_t m) { - rt_mutex_release(m); + rt_mutex_release(m); } #endif diff --git a/bsp/efm32/copy_this_file_shell.c b/bsp/efm32/copy_this_file_shell.c index bb69519293..152c1d8e25 100644 --- a/bsp/efm32/copy_this_file_shell.c +++ b/bsp/efm32/copy_this_file_shell.c @@ -31,48 +31,48 @@ struct finsh_shell* shell; #if !defined (RT_USING_NEWLIB) && !defined (RT_USING_MINILIBC) int strcmp (const char *s1, const char *s2) { - while (*s1 && *s1 == *s2) s1++, s2++; + while (*s1 && *s1 == *s2) s1++, s2++; - return (*s1 - *s2); + return (*s1 - *s2); } #ifdef RT_USING_HEAP char *strdup(const char *s) { - size_t len = strlen(s) + 1; - char *tmp = (char *)rt_malloc(len); + size_t len = strlen(s) + 1; + char *tmp = (char *)rt_malloc(len); - if(!tmp) return NULL; + if(!tmp) return NULL; - rt_memcpy(tmp, s, len); - return tmp; + rt_memcpy(tmp, s, len); + return tmp; } #endif #if !defined(__CC_ARM) && !defined(__IAR_SYSTEMS_ICC__) int isalpha( int ch ) { - return (unsigned int)((ch | 0x20) - 'a') < 26u; + return (unsigned int)((ch | 0x20) - 'a') < 26u; } int atoi(const char* s) { - long int v=0; - int sign=1; - while ( *s == ' ' || (unsigned int)(*s - 9) < 5u) s++; - - switch (*s) - { - case '-': sign=-1; - case '+': ++s; - } - - while ((unsigned int) (*s - '0') < 10u) - { - v=v*10+*s-'0'; ++s; - } - - return sign==-1?-v:v; + long int v=0; + int sign=1; + while ( *s == ' ' || (unsigned int)(*s - 9) < 5u) s++; + + switch (*s) + { + case '-': sign=-1; + case '+': ++s; + } + + while ((unsigned int) (*s - '0') < 10u) + { + v=v*10+*s-'0'; ++s; + } + + return sign==-1?-v:v; } int isprint(unsigned char ch) @@ -86,25 +86,25 @@ int isprint(unsigned char ch) #include const char* finsh_get_prompt(void) { - #define _PROMPT "finsh " - static char finsh_prompt[RT_CONSOLEBUF_SIZE + 1] = {_PROMPT}; - - /* get current working directory */ - getcwd(&finsh_prompt[6], RT_CONSOLEBUF_SIZE - 8); - strcat(finsh_prompt, ">"); - - return finsh_prompt; + #define _PROMPT "finsh " + static char finsh_prompt[RT_CONSOLEBUF_SIZE + 1] = {_PROMPT}; + + /* get current working directory */ + getcwd(&finsh_prompt[6], RT_CONSOLEBUF_SIZE - 8); + strcat(finsh_prompt, ">"); + + return finsh_prompt; } #endif static rt_err_t finsh_rx_ind(rt_device_t dev, rt_size_t size) { - RT_ASSERT(shell != RT_NULL); + RT_ASSERT(shell != RT_NULL); - /* release semaphore to let finsh thread rx data */ - rt_sem_release(&shell->rx_sem); + /* release semaphore to let finsh thread rx data */ + rt_sem_release(&shell->rx_sem); - return RT_EOK; + return RT_EOK; } /** @@ -116,25 +116,25 @@ static rt_err_t finsh_rx_ind(rt_device_t dev, rt_size_t size) */ void finsh_set_device(const char* device_name) { - rt_device_t dev = RT_NULL; - - RT_ASSERT(shell != RT_NULL); - dev = rt_device_find(device_name); - if (dev != RT_NULL && rt_device_open(dev, RT_DEVICE_OFLAG_RDWR) == RT_EOK) - { - if (shell->device != RT_NULL) - { - /* close old finsh device */ - rt_device_close(shell->device); - } - - shell->device = dev; - rt_device_set_rx_indicate(dev, finsh_rx_ind); - } - else - { - rt_kprintf("finsh: can not find device:%s\n", device_name); - } + rt_device_t dev = RT_NULL; + + RT_ASSERT(shell != RT_NULL); + dev = rt_device_find(device_name); + if (dev != RT_NULL && rt_device_open(dev, RT_DEVICE_OFLAG_RDWR) == RT_EOK) + { + if (shell->device != RT_NULL) + { + /* close old finsh device */ + rt_device_close(shell->device); + } + + shell->device = dev; + rt_device_set_rx_indicate(dev, finsh_rx_ind); + } + else + { + rt_kprintf("finsh: can not find device:%s\n", device_name); + } } /** @@ -146,8 +146,8 @@ void finsh_set_device(const char* device_name) */ const char* finsh_get_device() { - RT_ASSERT(shell != RT_NULL); - return shell->device->parent.name; + RT_ASSERT(shell != RT_NULL); + return shell->device->parent.name; } /** @@ -161,8 +161,8 @@ const char* finsh_get_device() */ void finsh_set_echo(rt_uint32_t echo) { - RT_ASSERT(shell != RT_NULL); - shell->echo_mode = echo; + RT_ASSERT(shell != RT_NULL); + shell->echo_mode = echo; } /** @@ -174,59 +174,59 @@ void finsh_set_echo(rt_uint32_t echo) */ rt_uint32_t finsh_get_echo() { - RT_ASSERT(shell != RT_NULL); + RT_ASSERT(shell != RT_NULL); - return shell->echo_mode; + return shell->echo_mode; } void finsh_auto_complete(char* prefix) { - extern void list_prefix(char* prefix); + extern void list_prefix(char* prefix); - rt_kprintf("\n"); - list_prefix(prefix); - rt_kprintf("%s%s", FINSH_PROMPT, prefix); + rt_kprintf("\n"); + list_prefix(prefix); + rt_kprintf("%s%s", FINSH_PROMPT, prefix); } void finsh_run_line(struct finsh_parser* parser, const char *line) { - const char* err_str; - - rt_kprintf("\n"); - finsh_parser_run(parser, (unsigned char*)line); - - /* compile node root */ - if (finsh_errno() == 0) - { - finsh_compiler_run(parser->root); - } - else - { - err_str = finsh_error_string(finsh_errno()); - rt_kprintf("%s\n", err_str); - } - - /* run virtual machine */ - if (finsh_errno() == 0) - { - char ch; - finsh_vm_run(); - - ch = (unsigned char)finsh_stack_bottom(); - if (ch > 0x20 && ch < 0x7e) - { - rt_kprintf("\t'%c', %d, 0x%08x\n", - (unsigned char)finsh_stack_bottom(), - (unsigned int)finsh_stack_bottom(), - (unsigned int)finsh_stack_bottom()); - } - else - { - rt_kprintf("\t%d, 0x%08x\n", - (unsigned int)finsh_stack_bottom(), - (unsigned int)finsh_stack_bottom()); - } - } + const char* err_str; + + rt_kprintf("\n"); + finsh_parser_run(parser, (unsigned char*)line); + + /* compile node root */ + if (finsh_errno() == 0) + { + finsh_compiler_run(parser->root); + } + else + { + err_str = finsh_error_string(finsh_errno()); + rt_kprintf("%s\n", err_str); + } + + /* run virtual machine */ + if (finsh_errno() == 0) + { + char ch; + finsh_vm_run(); + + ch = (unsigned char)finsh_stack_bottom(); + if (ch > 0x20 && ch < 0x7e) + { + rt_kprintf("\t'%c', %d, 0x%08x\n", + (unsigned char)finsh_stack_bottom(), + (unsigned int)finsh_stack_bottom(), + (unsigned int)finsh_stack_bottom()); + } + else + { + rt_kprintf("\t%d, 0x%08x\n", + (unsigned int)finsh_stack_bottom(), + (unsigned int)finsh_stack_bottom()); + } + } finsh_flush(parser); } @@ -234,111 +234,111 @@ void finsh_run_line(struct finsh_parser* parser, const char *line) #ifdef FINSH_USING_HISTORY rt_bool_t finsh_handle_history(struct finsh_shell* shell, char ch) { - /* - * handle up and down key - * up key : 0x1b 0x5b 0x41 - * down key: 0x1b 0x5b 0x42 - */ - if (ch == 0x1b) - { - shell->stat = WAIT_SPEC_KEY; - return RT_TRUE; - } - - if ((shell->stat == WAIT_SPEC_KEY)) - { - if (ch == 0x5b) - { - shell->stat = WAIT_FUNC_KEY; - return RT_TRUE; - } - - shell->stat = WAIT_NORMAL; - return RT_FALSE; - } - - if (shell->stat == WAIT_FUNC_KEY) - { - shell->stat = WAIT_NORMAL; - - if (ch == 0x41) /* up key */ - { - /* prev history */ - if (shell->current_history > 0)shell->current_history --; - else - { - shell->current_history = 0; - return RT_TRUE; - } - - /* copy the history command */ - memcpy(shell->line, &shell->cmd_history[shell->current_history][0], - FINSH_CMD_SIZE); - shell->line_position = strlen(shell->line); - shell->use_history = 1; - } - else if (ch == 0x42) /* down key */ - { - /* next history */ - if (shell->current_history < shell->history_count - 1) - shell->current_history ++; - else - { - /* set to the end of history */ - if (shell->history_count != 0) - { - shell->current_history = shell->history_count - 1; - } - else return RT_TRUE; - } - - memcpy(shell->line, &shell->cmd_history[shell->current_history][0], - FINSH_CMD_SIZE); - shell->line_position = strlen(shell->line); - shell->use_history = 1; - } - - if (shell->use_history) - { - rt_kprintf("\033[2K\r"); - rt_kprintf("%s%s", FINSH_PROMPT, shell->line); - return RT_TRUE;; - } - } - - return RT_FALSE; + /* + * handle up and down key + * up key : 0x1b 0x5b 0x41 + * down key: 0x1b 0x5b 0x42 + */ + if (ch == 0x1b) + { + shell->stat = WAIT_SPEC_KEY; + return RT_TRUE; + } + + if ((shell->stat == WAIT_SPEC_KEY)) + { + if (ch == 0x5b) + { + shell->stat = WAIT_FUNC_KEY; + return RT_TRUE; + } + + shell->stat = WAIT_NORMAL; + return RT_FALSE; + } + + if (shell->stat == WAIT_FUNC_KEY) + { + shell->stat = WAIT_NORMAL; + + if (ch == 0x41) /* up key */ + { + /* prev history */ + if (shell->current_history > 0)shell->current_history --; + else + { + shell->current_history = 0; + return RT_TRUE; + } + + /* copy the history command */ + memcpy(shell->line, &shell->cmd_history[shell->current_history][0], + FINSH_CMD_SIZE); + shell->line_position = strlen(shell->line); + shell->use_history = 1; + } + else if (ch == 0x42) /* down key */ + { + /* next history */ + if (shell->current_history < shell->history_count - 1) + shell->current_history ++; + else + { + /* set to the end of history */ + if (shell->history_count != 0) + { + shell->current_history = shell->history_count - 1; + } + else return RT_TRUE; + } + + memcpy(shell->line, &shell->cmd_history[shell->current_history][0], + FINSH_CMD_SIZE); + shell->line_position = strlen(shell->line); + shell->use_history = 1; + } + + if (shell->use_history) + { + rt_kprintf("\033[2K\r"); + rt_kprintf("%s%s", FINSH_PROMPT, shell->line); + return RT_TRUE;; + } + } + + return RT_FALSE; } void finsh_push_history(struct finsh_shell* shell) { - if ((shell->use_history == 0) && (shell->line_position != 0)) - { - /* push history */ - if (shell->history_count >= FINSH_HISTORY_LINES) - { - /* move history */ - int index; - for (index = 0; index < FINSH_HISTORY_LINES - 1; index ++) - { - memcpy(&shell->cmd_history[index][0], - &shell->cmd_history[index + 1][0], FINSH_CMD_SIZE); - } - memset(&shell->cmd_history[index][0], 0, FINSH_CMD_SIZE); - memcpy(&shell->cmd_history[index][0], shell->line, shell->line_position); - - /* it's the maximum history */ - shell->history_count = FINSH_HISTORY_LINES; - } - else - { - memset(&shell->cmd_history[shell->history_count][0], 0, FINSH_CMD_SIZE); - memcpy(&shell->cmd_history[shell->history_count][0], shell->line, shell->line_position); - - /* increase count and set current history position */ - shell->history_count ++; - } - } - shell->current_history = shell->history_count; + if ((shell->use_history == 0) && (shell->line_position != 0)) + { + /* push history */ + if (shell->history_count >= FINSH_HISTORY_LINES) + { + /* move history */ + int index; + for (index = 0; index < FINSH_HISTORY_LINES - 1; index ++) + { + memcpy(&shell->cmd_history[index][0], + &shell->cmd_history[index + 1][0], FINSH_CMD_SIZE); + } + memset(&shell->cmd_history[index][0], 0, FINSH_CMD_SIZE); + memcpy(&shell->cmd_history[index][0], shell->line, shell->line_position); + + /* it's the maximum history */ + shell->history_count = FINSH_HISTORY_LINES; + } + else + { + memset(&shell->cmd_history[shell->history_count][0], 0, FINSH_CMD_SIZE); + memcpy(&shell->cmd_history[shell->history_count][0], shell->line, shell->line_position); + + /* increase count and set current history position */ + shell->history_count ++; + } + } + shell->current_history = shell->history_count; } #endif @@ -349,107 +349,107 @@ void finsh_thread_entry(void* parameter) { char ch; - /* test: for efm32 low power mode */ + /* test: for efm32 low power mode */ emu_all_disable(); - /* normal is echo mode */ - shell->echo_mode = 1; + /* normal is echo mode */ + shell->echo_mode = 1; finsh_init(&shell->parser); - rt_kprintf(FINSH_PROMPT); + rt_kprintf(FINSH_PROMPT); - while (1) - { - /* test: for efm32 low power mode */ + while (1) + { + /* test: for efm32 low power mode */ emu_em2_enable(); - /* wait receive */ - if (rt_sem_take(&shell->rx_sem, RT_WAITING_FOREVER) != RT_EOK) continue; + /* wait receive */ + if (rt_sem_take(&shell->rx_sem, RT_WAITING_FOREVER) != RT_EOK) continue; - /* test: for efm32 low power mode */ + /* test: for efm32 low power mode */ emu_em2_disable(); - /* read one character from device */ - while (rt_device_read(shell->device, 0, &ch, 1) == 1) - { - /* handle history key */ - #ifdef FINSH_USING_HISTORY - if (finsh_handle_history(shell, ch) == RT_TRUE) continue; - #endif - - /* handle CR key */ - if (ch == '\r') - { - char next; - - if (rt_device_read(shell->device, 0, &next, 1) == 1) - ch = next; - else ch = '\r'; - } - /* handle tab key */ - else if (ch == '\t') - { - /* auto complete */ - finsh_auto_complete(&shell->line[0]); - /* re-calculate position */ - shell->line_position = strlen(shell->line); - continue; - } - /* handle backspace key */ - else if (ch == 0x7f || ch == 0x08) - { - if (shell->line_position != 0) - { - rt_kprintf("%c %c", ch, ch); - } - if (shell->line_position <= 0) shell->line_position = 0; - else shell->line_position --; - shell->line[shell->line_position] = 0; - continue; - } - - /* handle end of line, break */ - if (ch == '\r' || ch == '\n') - { - /* change to ';' and break */ - shell->line[shell->line_position] = ';'; - - #ifdef FINSH_USING_HISTORY - finsh_push_history(shell); - #endif - - if (shell->line_position != 0) finsh_run_line(&shell->parser, shell->line); - else rt_kprintf("\n"); - - rt_kprintf(FINSH_PROMPT); - memset(shell->line, 0, sizeof(shell->line)); - shell->line_position = 0; - - break; - } - - /* it's a large line, discard it */ - if (shell->line_position >= FINSH_CMD_SIZE) shell->line_position = 0; - - /* normal character */ - shell->line[shell->line_position] = ch; ch = 0; - if (shell->echo_mode) rt_kprintf("%c", shell->line[shell->line_position]); - shell->line_position ++; - shell->use_history = 0; /* it's a new command */ - } /* end of device read */ - } + /* read one character from device */ + while (rt_device_read(shell->device, 0, &ch, 1) == 1) + { + /* handle history key */ + #ifdef FINSH_USING_HISTORY + if (finsh_handle_history(shell, ch) == RT_TRUE) continue; + #endif + + /* handle CR key */ + if (ch == '\r') + { + char next; + + if (rt_device_read(shell->device, 0, &next, 1) == 1) + ch = next; + else ch = '\r'; + } + /* handle tab key */ + else if (ch == '\t') + { + /* auto complete */ + finsh_auto_complete(&shell->line[0]); + /* re-calculate position */ + shell->line_position = strlen(shell->line); + continue; + } + /* handle backspace key */ + else if (ch == 0x7f || ch == 0x08) + { + if (shell->line_position != 0) + { + rt_kprintf("%c %c", ch, ch); + } + if (shell->line_position <= 0) shell->line_position = 0; + else shell->line_position --; + shell->line[shell->line_position] = 0; + continue; + } + + /* handle end of line, break */ + if (ch == '\r' || ch == '\n') + { + /* change to ';' and break */ + shell->line[shell->line_position] = ';'; + + #ifdef FINSH_USING_HISTORY + finsh_push_history(shell); + #endif + + if (shell->line_position != 0) finsh_run_line(&shell->parser, shell->line); + else rt_kprintf("\n"); + + rt_kprintf(FINSH_PROMPT); + memset(shell->line, 0, sizeof(shell->line)); + shell->line_position = 0; + + break; + } + + /* it's a large line, discard it */ + if (shell->line_position >= FINSH_CMD_SIZE) shell->line_position = 0; + + /* normal character */ + shell->line[shell->line_position] = ch; ch = 0; + if (shell->echo_mode) rt_kprintf("%c", shell->line[shell->line_position]); + shell->line_position ++; + shell->use_history = 0; /* it's a new command */ + } /* end of device read */ + } } void finsh_system_function_init(const void* begin, const void* end) { - _syscall_table_begin = (struct finsh_syscall*) begin; - _syscall_table_end = (struct finsh_syscall*) end; + _syscall_table_begin = (struct finsh_syscall*) begin; + _syscall_table_end = (struct finsh_syscall*) end; } void finsh_system_var_init(const void* begin, const void* end) { - _sysvar_table_begin = (struct finsh_sysvar*) begin; - _sysvar_table_end = (struct finsh_sysvar*) end; + _sysvar_table_begin = (struct finsh_sysvar*) begin; + _sysvar_table_end = (struct finsh_sysvar*) end; } #if defined(__ICCARM__) /* for IAR compiler */ @@ -466,7 +466,7 @@ void finsh_system_var_init(const void* begin, const void* end) */ int finsh_system_init(void) { - rt_err_t result; + rt_err_t result; #ifdef FINSH_USING_SYMTAB #ifdef __CC_ARM /* ARM C Compiler */ @@ -474,44 +474,44 @@ int finsh_system_init(void) extern const int FSymTab$$Limit; extern const int VSymTab$$Base; extern const int VSymTab$$Limit; - finsh_system_function_init(&FSymTab$$Base, &FSymTab$$Limit); - finsh_system_var_init(&VSymTab$$Base, &VSymTab$$Limit); + finsh_system_function_init(&FSymTab$$Base, &FSymTab$$Limit); + finsh_system_var_init(&VSymTab$$Base, &VSymTab$$Limit); #elif defined (__ICCARM__) /* for IAR Compiler */ finsh_system_function_init(__section_begin("FSymTab"), __section_end("FSymTab")); finsh_system_var_init(__section_begin("VSymTab"), __section_end("VSymTab")); #elif defined (__GNUC__) /* GNU GCC Compiler */ - extern const int __fsymtab_start; - extern const int __fsymtab_end; - extern const int __vsymtab_start; - extern const int __vsymtab_end; - finsh_system_function_init(&__fsymtab_start, &__fsymtab_end); - finsh_system_var_init(&__vsymtab_start, &__vsymtab_end); + extern const int __fsymtab_start; + extern const int __fsymtab_end; + extern const int __vsymtab_start; + extern const int __vsymtab_end; + finsh_system_function_init(&__fsymtab_start, &__fsymtab_end); + finsh_system_var_init(&__vsymtab_start, &__vsymtab_end); #endif #endif - /* create or set shell structure */ + /* create or set shell structure */ #ifdef RT_USING_HEAP - shell = (struct finsh_shell*)rt_malloc(sizeof(struct finsh_shell)); + shell = (struct finsh_shell*)rt_malloc(sizeof(struct finsh_shell)); #else - shell = &_shell; + shell = &_shell; #endif - if (shell == RT_NULL) - { - rt_kprintf("no memory for shell\n"); - return; - } - - memset(shell, 0, sizeof(struct finsh_shell)); - - rt_sem_init(&(shell->rx_sem), "shrx", 0, 0); - result = rt_thread_init(&finsh_thread, - "tshell", - finsh_thread_entry, RT_NULL, - &finsh_thread_stack[0], sizeof(finsh_thread_stack), - FINSH_THREAD_PRIORITY, 10); - - if (result == RT_EOK) - rt_thread_startup(&finsh_thread); + if (shell == RT_NULL) + { + rt_kprintf("no memory for shell\n"); + return; + } + + memset(shell, 0, sizeof(struct finsh_shell)); + + rt_sem_init(&(shell->rx_sem), "shrx", 0, 0); + result = rt_thread_init(&finsh_thread, + "tshell", + finsh_thread_entry, RT_NULL, + &finsh_thread_stack[0], sizeof(finsh_thread_stack), + FINSH_THREAD_PRIORITY, 10); + + if (result == RT_EOK) + rt_thread_startup(&finsh_thread); } diff --git a/bsp/efm32/dev_accel.c b/bsp/efm32/dev_accel.c index fb2c05174b..07fcc25ded 100644 --- a/bsp/efm32/dev_accel.c +++ b/bsp/efm32/dev_accel.c @@ -1,8 +1,8 @@ /***************************************************************************//** - * @file dev_accel.c - * @brief Accelerometer driver of RT-Thread RTOS for EFM32 + * @file dev_accel.c + * @brief Accelerometer driver of RT-Thread RTOS for EFM32 * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -10,10 +10,10 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes - * 2011-07-13 onelife Initial creation for using EFM32 ADC module to + * Date Author Notes + * 2011-07-13 onelife Initial creation for using EFM32 ADC module to * interface the Freescale MMA7361L - * 2011-08-02 onelife Add digital interface support of using EFM32 IIC + * 2011-08-02 onelife Add digital interface support of using EFM32 IIC * module for the Freescale MMA7455L ******************************************************************************/ @@ -38,23 +38,23 @@ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ #ifdef EFM32_ACCEL_DEBUG -#define accel_debug(format,args...) rt_kprintf(format, ##args) +#define accel_debug(format,args...) rt_kprintf(format, ##args) #else #define accel_debug(format,args...) #endif /* Private constants ---------------------------------------------------------*/ -static rt_device_t accel; +static rt_device_t accel; #if (EFM32_USING_ACCEL == EFM32_INTERFACE_ADC) -static struct efm32_adc_control_t control = \ - {ADC_MODE_SCAN, {3, ACCEL_USING_DMA}, {}}; -static struct efm32_accel_result_t accelOffset = {0}; +static struct efm32_adc_control_t control = \ + {ADC_MODE_SCAN, {3, ACCEL_USING_DMA}, {}}; +static struct efm32_accel_result_t accelOffset = {0}; #elif (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC) -static const struct efm32_iic_control_t control = \ - {IIC_STATE_MASTER, 0x0000}; +static const struct efm32_iic_control_t control = \ + {IIC_STATE_MASTER, 0x0000}; #endif -static rt_bool_t accelInTime = true; -static rt_uint32_t accelConfig = 0; +static rt_bool_t accelInTime = true; +static rt_uint32_t accelConfig = 0; /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -68,99 +68,99 @@ static rt_uint32_t accelConfig = 0; * @note * * @param[out] data - * Pointer to output buffer + * Pointer to output buffer * * @param[in] lowResolution - * Resolution selection + * Resolution selection * * @return - * Error code + * Error code ******************************************************************************/ rt_err_t efm_accel_get_data(struct efm32_accel_result_t *data, - rt_bool_t lowResolution) + rt_bool_t lowResolution) { - RT_ASSERT(accel != RT_NULL); + RT_ASSERT(accel != RT_NULL); - rt_err_t ret; + rt_err_t ret; - if (data == RT_NULL) - { - return -RT_ERROR; - } + if (data == RT_NULL) + { + return -RT_ERROR; + } - ret = RT_EOK; - do - { - /* --------- ADC interface --------- */ + ret = RT_EOK; + do + { + /* --------- ADC interface --------- */ #if (EFM32_USING_ACCEL == EFM32_INTERFACE_ADC) - struct efm32_adc_result_t result; - - result.mode = control.mode; - result.buffer = (void *)data; - if ((ret = accel->control(accel, RT_DEVICE_CTRL_RESUME, - (void *)&result)) != RT_EOK) - { - break; - } - if ((ret = accel->control(accel, RT_DEVICE_CTRL_ADC_RESULT, \ - (void *)&result)) != RT_EOK) - { - break; - } - - data->x += accelOffset.x - 0x800; - data->y += accelOffset.y - 0x800; - data->z += accelOffset.z - 0x800; - if (lowResolution) - { - data->x >>= 4; - data->y >>= 4; - data->z >>= 4; - } - - /* --------- IIC interface --------- */ + struct efm32_adc_result_t result; + + result.mode = control.mode; + result.buffer = (void *)data; + if ((ret = accel->control(accel, RT_DEVICE_CTRL_RESUME, + (void *)&result)) != RT_EOK) + { + break; + } + if ((ret = accel->control(accel, RT_DEVICE_CTRL_ADC_RESULT, \ + (void *)&result)) != RT_EOK) + { + break; + } + + data->x += accelOffset.x - 0x800; + data->y += accelOffset.y - 0x800; + data->z += accelOffset.z - 0x800; + if (lowResolution) + { + data->x >>= 4; + data->y >>= 4; + data->z >>= 4; + } + + /* --------- IIC interface --------- */ #elif (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC) - if (lowResolution || \ - ((accelConfig & ACCEL_MASK_RANGE) != MCTL_RANGE_8G)) - { - rt_int8_t buf[3]; - - buf[0] = XOUT8; - if (accel->read(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, \ - sizeof(buf)) == 0) - { - ret = -RT_ERROR; - break; - } - data->x = buf[0]; - data->y = buf[1]; - data->z = buf[2]; - } - else - { - rt_uint8_t buf[6]; - rt_uint16_t *temp = (rt_uint16_t *)&buf; - - buf[0] = XOUTL; - if (accel->read(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, \ - sizeof(buf)) == 0) - { - ret = -RT_ERROR; - break; - } - data->x = (*temp & 0x200) ? ((rt_uint32_t)*temp | ~0x3FF) : \ - ((rt_uint32_t)*temp & 0x3FF); - data->y = (*++temp & 0x200) ? ((rt_uint32_t)*temp | ~0x3FF) : \ - ((rt_uint32_t)*temp & 0x3FF); - data->z = (*++temp & 0x200) ? ((rt_uint32_t)*temp | ~0x3FF) : \ - ((rt_uint32_t)*temp & 0x3FF); - } + if (lowResolution || \ + ((accelConfig & ACCEL_MASK_RANGE) != MCTL_RANGE_8G)) + { + rt_int8_t buf[3]; + + buf[0] = XOUT8; + if (accel->read(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, \ + sizeof(buf)) == 0) + { + ret = -RT_ERROR; + break; + } + data->x = buf[0]; + data->y = buf[1]; + data->z = buf[2]; + } + else + { + rt_uint8_t buf[6]; + rt_uint16_t *temp = (rt_uint16_t *)&buf; + + buf[0] = XOUTL; + if (accel->read(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, \ + sizeof(buf)) == 0) + { + ret = -RT_ERROR; + break; + } + data->x = (*temp & 0x200) ? ((rt_uint32_t)*temp | ~0x3FF) : \ + ((rt_uint32_t)*temp & 0x3FF); + data->y = (*++temp & 0x200) ? ((rt_uint32_t)*temp | ~0x3FF) : \ + ((rt_uint32_t)*temp & 0x3FF); + data->z = (*++temp & 0x200) ? ((rt_uint32_t)*temp | ~0x3FF) : \ + ((rt_uint32_t)*temp & 0x3FF); + } #endif - return RT_EOK; - } while (0); + return RT_EOK; + } while (0); - accel_debug("Accel err: Get data failed!\n"); - return ret; + accel_debug("Accel err: Get data failed!\n"); + return ret; } /***************************************************************************//** @@ -172,357 +172,357 @@ rt_err_t efm_accel_get_data(struct efm32_accel_result_t *data, * @note * * @param[in] parameter - * Parameter + * Parameter ******************************************************************************/ static void efm_accel_timer(void* parameter) { - accelInTime = false; + accelInTime = false; } #if (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC) /***************************************************************************//** * @brief - * Accelerometer level and pulse detection interrupts handler + * Accelerometer level and pulse detection interrupts handler * * @details * * @note * * @param[in] device - * Pointer to device descriptor + * Pointer to device descriptor ******************************************************************************/ static void efm_accel_isr(rt_device_t device) { - rt_uint8_t buf[2]; - - if ((accelConfig & ACCEL_MASK_MODE) != ACCEL_MODE_MEASUREMENT) - { - /* Read detection source */ - buf[0] = DETSRC; - if (accel->read(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 1) != 1) - { - accel_debug("Accel: read error\n"); - return; - } - accel_debug("Accel: DETSRC %x\n", buf[0]); - - /* Reset the interrupt flags: Part 1 */ - buf[0] = INTRST; - buf[1] = INTRST_INT_1 | INTRST_INT_2; - accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2); - - /* Read status to waste some time */ - buf[0] = STATUS; - if (accel->read(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 1) != 1) - { - accel_debug("Accel: read error\n"); - return; - } - accel_debug("Accel: STATUS %x\n", buf[0]); - - /* Reset the interrupt flags: Part 2 */ - buf[0] = INTRST; - buf[1] = 0x00; - accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2); - } + rt_uint8_t buf[2]; + + if ((accelConfig & ACCEL_MASK_MODE) != ACCEL_MODE_MEASUREMENT) + { + /* Read detection source */ + buf[0] = DETSRC; + if (accel->read(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 1) != 1) + { + accel_debug("Accel: read error\n"); + return; + } + accel_debug("Accel: DETSRC %x\n", buf[0]); + + /* Reset the interrupt flags: Part 1 */ + buf[0] = INTRST; + buf[1] = INTRST_INT_1 | INTRST_INT_2; + accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2); + + /* Read status to waste some time */ + buf[0] = STATUS; + if (accel->read(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 1) != 1) + { + accel_debug("Accel: read error\n"); + return; + } + accel_debug("Accel: STATUS %x\n", buf[0]); + + /* Reset the interrupt flags: Part 2 */ + buf[0] = INTRST; + buf[1] = 0x00; + accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2); + } } /***************************************************************************//** * @brief - * Accelerometer configuration function + * Accelerometer configuration function * * @details * * @note * * @param[in] config - * Configuration options + * Configuration options * * @param[in] level_threshold - * Level detection threshold + * Level detection threshold * * @param[in] pulse_threshold - * Pulse detection threshold + * Pulse detection threshold * * @param[in] pulse_duration - * Time window for 1st pulse + * Time window for 1st pulse * * @param[in] pulse_latency - * Pulse latency Time + * Pulse latency Time * * @param[in] pulse_duration2 - * Time window for 2nd pulse + * Time window for 2nd pulse * * @return - * Error code + * Error code ******************************************************************************/ rt_err_t efm_accel_config(rt_uint32_t config, - rt_uint8_t level_threshold, - rt_uint8_t pulse_threshold, - rt_uint8_t pulse_duration, - rt_uint8_t pulse_latency, - rt_uint8_t pulse_duration2) + rt_uint8_t level_threshold, + rt_uint8_t pulse_threshold, + rt_uint8_t pulse_duration, + rt_uint8_t pulse_latency, + rt_uint8_t pulse_duration2) { - rt_err_t ret; - rt_uint8_t buf[2]; - rt_uint8_t mode, mctl_reg, ctl1_reg, ctl2_reg; - - ret = RT_EOK; - mctl_reg = 0; - ctl1_reg = 0; - ctl2_reg = 0; - - /* Modify MCTL */ - mode = config & ACCEL_MASK_MODE; - switch (mode) - { - case ACCEL_MODE_STANDBY: - mctl_reg |= MCTL_MODE_STANDBY; - break; - case ACCEL_MODE_MEASUREMENT: - mctl_reg |= MCTL_MODE_MEASUREMENT; - break; - case ACCEL_MODE_LEVEL: - mctl_reg |= MCTL_MODE_LEVEL; - break; - case ACCEL_MODE_PULSE: - mctl_reg |= MCTL_MODE_PULSE; - break; - default: - return -RT_ERROR; - } - - switch (config & ACCEL_MASK_RANGE) - { - case ACCEL_RANGE_8G: - mctl_reg |= MCTL_RANGE_8G; - break; - case ACCEL_RANGE_4G: - mctl_reg |= MCTL_RANGE_4G; - break; - case ACCEL_RANGE_2G: - mctl_reg |= MCTL_RANGE_2G; - break; - default: - return -RT_ERROR; - } - - if ((mode == ACCEL_MODE_LEVEL) || (mode == ACCEL_MODE_PULSE)) - { - mctl_reg |= MCTL_PIN_INT1; - } - - /* Modify CTL1 */ - if (config & ACCEL_INTPIN_INVERSE) - { - ctl1_reg |= CTL1_INTPIN_INVERSE; - } - - switch (config & ACCEL_MASK_INT) - { - case ACCEL_INT_LEVEL_PULSE: - ctl1_reg |= CTL1_INT_LEVEL_PULSE; - break; - case ACCEL_INT_PULSE_LEVEL: - ctl1_reg |= CTL1_INT_PULSE_LEVEL; - break; - case ACCEL_INT_SINGLE_DOUBLE: - ctl1_reg |= CTL1_INT_SINGLE_DOUBLE; - break; - default: - break; - } - - switch (config & ACCEL_MASK_DISABLE) - { - case ACCEL_DISABLE_X: - ctl1_reg |= CTL1_X_DISABLE; - break; - case ACCEL_DISABLE_Y: - ctl1_reg |= CTL1_Y_DISABLE; - break; - case ACCEL_DISABLE_Z: - ctl1_reg |= CTL1_Z_DISABLE; - break; - default: - break; - } - - if (config & ACCEL_THRESHOLD_INTEGER) - { - ctl1_reg |= CTL1_THRESHOLD_INTEGER; - } - - if (config & ACCEL_BANDWIDTH_125HZ) - { - ctl1_reg |= CTL1_BANDWIDTH_125HZ; - } - - /* Modify CTL2 */ - if (config & ACCEL_LEVEL_AND) - { - ctl2_reg |= CTL2_LEVEL_AND; - } - if (config & ACCEL_PULSE_AND) - { - ctl2_reg |= CTL2_PULSE_AND; - } - if (config & ACCEL_DRIVE_STRONG) - { - ctl2_reg |= CTL2_DRIVE_STRONG; - } - - do - { - /* Write registers */ - buf[0] = MCTL; - buf[1] = mctl_reg; - if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) - { - ret = -RT_ERROR; - break; - } - accel_debug("Accel: MCTL %x\n", mctl_reg); - - buf[0] = CTL1; - buf[1] = ctl1_reg; - if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) - { - ret = -RT_ERROR; - break; - } - accel_debug("Accel: CTL1 %x\n", ctl1_reg); - - buf[0] = CTL2; - buf[1] = ctl2_reg; - if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) - { - ret = -RT_ERROR; - break; - } - accel_debug("Accel: CTL2 %x\n", ctl2_reg); - accelConfig = config; - - if (mode == ACCEL_MODE_PULSE) - { - buf[0] = PDTH; - buf[1] = pulse_threshold; - if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) - { - ret = -RT_ERROR; - break; - } - accel_debug("Accel: PDTH %x\n", buf[1]); - - buf[0] = PW; - buf[1] = pulse_duration; - if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) - { - ret = -RT_ERROR; - break; - } - accel_debug("Accel: PW %x\n", buf[1]); - - buf[0] = LT; - buf[1] = pulse_latency; - if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) - { - ret = -RT_ERROR; - break; - } - accel_debug("Accel: LT %x\n", buf[1]); - - buf[0] = TW; - buf[1] = pulse_duration2; - if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) - { - ret = -RT_ERROR; - break; - } - accel_debug("Accel: TW %x\n", buf[1]); - } - - if ((mode == ACCEL_MODE_LEVEL) || (mode == ACCEL_MODE_PULSE)) - { - efm32_irq_hook_init_t hook; - - /* Reset the interrupt flags: Part 1 */ - buf[0] = INTRST; - buf[1] = INTRST_INT_1 | INTRST_INT_2; - if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) - { - ret = -RT_ERROR; - break; - } - - /* Set level detection threshold */ - buf[0] = LDTH; - if (config & ACCEL_THRESHOLD_INTEGER) - { - buf[1] = level_threshold; - } - else - { - buf[1] = level_threshold & 0x7f; - } - if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) - { - ret = -RT_ERROR; - break; - } - accel_debug("Accel: LDTH %x\n", buf[1]); - - /* Config interrupt */ - hook.type = efm32_irq_type_gpio; - hook.unit = ACCEL_INT1_PIN; - hook.cbFunc = efm_accel_isr; - hook.userPtr = RT_NULL; - efm32_irq_hook_register(&hook); - hook.unit = ACCEL_INT2_PIN; - efm32_irq_hook_register(&hook); - /* Clear pending interrupt */ - BITBAND_Peripheral(&(GPIO->IFC), ACCEL_INT1_PIN, 0x1UL); - BITBAND_Peripheral(&(GPIO->IFC), ACCEL_INT2_PIN, 0x1UL); - /* Set raising edge interrupt and clear/enable it */ - GPIO_IntConfig( - ACCEL_INT1_PORT, - ACCEL_INT1_PIN, - true, - false, - true); - GPIO_IntConfig( - ACCEL_INT2_PORT, - ACCEL_INT2_PIN, - true, - false, - true); - if (((rt_uint8_t)ACCEL_INT1_PORT % 2) || \ - ((rt_uint8_t)ACCEL_INT2_PORT % 2)) - { - NVIC_ClearPendingIRQ(GPIO_ODD_IRQn); - NVIC_SetPriority(GPIO_ODD_IRQn, EFM32_IRQ_PRI_DEFAULT); - NVIC_EnableIRQ(GPIO_ODD_IRQn); - } - if (!((rt_uint8_t)ACCEL_INT1_PORT % 2) || \ - !((rt_uint8_t)ACCEL_INT2_PORT % 2)) - { - NVIC_ClearPendingIRQ(GPIO_EVEN_IRQn); - NVIC_SetPriority(GPIO_EVEN_IRQn, EFM32_IRQ_PRI_DEFAULT); - NVIC_EnableIRQ(GPIO_EVEN_IRQn); - } - - /* Reset the interrupt flags: Part 2 */ - buf[0] = INTRST; - buf[1] = 0x00; - if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) - { - ret = -RT_ERROR; - break; - } - } - } while (0); - - return ret; + rt_err_t ret; + rt_uint8_t buf[2]; + rt_uint8_t mode, mctl_reg, ctl1_reg, ctl2_reg; + + ret = RT_EOK; + mctl_reg = 0; + ctl1_reg = 0; + ctl2_reg = 0; + + /* Modify MCTL */ + mode = config & ACCEL_MASK_MODE; + switch (mode) + { + case ACCEL_MODE_STANDBY: + mctl_reg |= MCTL_MODE_STANDBY; + break; + case ACCEL_MODE_MEASUREMENT: + mctl_reg |= MCTL_MODE_MEASUREMENT; + break; + case ACCEL_MODE_LEVEL: + mctl_reg |= MCTL_MODE_LEVEL; + break; + case ACCEL_MODE_PULSE: + mctl_reg |= MCTL_MODE_PULSE; + break; + default: + return -RT_ERROR; + } + + switch (config & ACCEL_MASK_RANGE) + { + case ACCEL_RANGE_8G: + mctl_reg |= MCTL_RANGE_8G; + break; + case ACCEL_RANGE_4G: + mctl_reg |= MCTL_RANGE_4G; + break; + case ACCEL_RANGE_2G: + mctl_reg |= MCTL_RANGE_2G; + break; + default: + return -RT_ERROR; + } + + if ((mode == ACCEL_MODE_LEVEL) || (mode == ACCEL_MODE_PULSE)) + { + mctl_reg |= MCTL_PIN_INT1; + } + + /* Modify CTL1 */ + if (config & ACCEL_INTPIN_INVERSE) + { + ctl1_reg |= CTL1_INTPIN_INVERSE; + } + + switch (config & ACCEL_MASK_INT) + { + case ACCEL_INT_LEVEL_PULSE: + ctl1_reg |= CTL1_INT_LEVEL_PULSE; + break; + case ACCEL_INT_PULSE_LEVEL: + ctl1_reg |= CTL1_INT_PULSE_LEVEL; + break; + case ACCEL_INT_SINGLE_DOUBLE: + ctl1_reg |= CTL1_INT_SINGLE_DOUBLE; + break; + default: + break; + } + + switch (config & ACCEL_MASK_DISABLE) + { + case ACCEL_DISABLE_X: + ctl1_reg |= CTL1_X_DISABLE; + break; + case ACCEL_DISABLE_Y: + ctl1_reg |= CTL1_Y_DISABLE; + break; + case ACCEL_DISABLE_Z: + ctl1_reg |= CTL1_Z_DISABLE; + break; + default: + break; + } + + if (config & ACCEL_THRESHOLD_INTEGER) + { + ctl1_reg |= CTL1_THRESHOLD_INTEGER; + } + + if (config & ACCEL_BANDWIDTH_125HZ) + { + ctl1_reg |= CTL1_BANDWIDTH_125HZ; + } + + /* Modify CTL2 */ + if (config & ACCEL_LEVEL_AND) + { + ctl2_reg |= CTL2_LEVEL_AND; + } + if (config & ACCEL_PULSE_AND) + { + ctl2_reg |= CTL2_PULSE_AND; + } + if (config & ACCEL_DRIVE_STRONG) + { + ctl2_reg |= CTL2_DRIVE_STRONG; + } + + do + { + /* Write registers */ + buf[0] = MCTL; + buf[1] = mctl_reg; + if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) + { + ret = -RT_ERROR; + break; + } + accel_debug("Accel: MCTL %x\n", mctl_reg); + + buf[0] = CTL1; + buf[1] = ctl1_reg; + if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) + { + ret = -RT_ERROR; + break; + } + accel_debug("Accel: CTL1 %x\n", ctl1_reg); + + buf[0] = CTL2; + buf[1] = ctl2_reg; + if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) + { + ret = -RT_ERROR; + break; + } + accel_debug("Accel: CTL2 %x\n", ctl2_reg); + accelConfig = config; + + if (mode == ACCEL_MODE_PULSE) + { + buf[0] = PDTH; + buf[1] = pulse_threshold; + if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) + { + ret = -RT_ERROR; + break; + } + accel_debug("Accel: PDTH %x\n", buf[1]); + + buf[0] = PW; + buf[1] = pulse_duration; + if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) + { + ret = -RT_ERROR; + break; + } + accel_debug("Accel: PW %x\n", buf[1]); + + buf[0] = LT; + buf[1] = pulse_latency; + if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) + { + ret = -RT_ERROR; + break; + } + accel_debug("Accel: LT %x\n", buf[1]); + + buf[0] = TW; + buf[1] = pulse_duration2; + if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) + { + ret = -RT_ERROR; + break; + } + accel_debug("Accel: TW %x\n", buf[1]); + } + + if ((mode == ACCEL_MODE_LEVEL) || (mode == ACCEL_MODE_PULSE)) + { + efm32_irq_hook_init_t hook; + + /* Reset the interrupt flags: Part 1 */ + buf[0] = INTRST; + buf[1] = INTRST_INT_1 | INTRST_INT_2; + if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) + { + ret = -RT_ERROR; + break; + } + + /* Set level detection threshold */ + buf[0] = LDTH; + if (config & ACCEL_THRESHOLD_INTEGER) + { + buf[1] = level_threshold; + } + else + { + buf[1] = level_threshold & 0x7f; + } + if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) + { + ret = -RT_ERROR; + break; + } + accel_debug("Accel: LDTH %x\n", buf[1]); + + /* Config interrupt */ + hook.type = efm32_irq_type_gpio; + hook.unit = ACCEL_INT1_PIN; + hook.cbFunc = efm_accel_isr; + hook.userPtr = RT_NULL; + efm32_irq_hook_register(&hook); + hook.unit = ACCEL_INT2_PIN; + efm32_irq_hook_register(&hook); + /* Clear pending interrupt */ + BITBAND_Peripheral(&(GPIO->IFC), ACCEL_INT1_PIN, 0x1UL); + BITBAND_Peripheral(&(GPIO->IFC), ACCEL_INT2_PIN, 0x1UL); + /* Set raising edge interrupt and clear/enable it */ + GPIO_IntConfig( + ACCEL_INT1_PORT, + ACCEL_INT1_PIN, + true, + false, + true); + GPIO_IntConfig( + ACCEL_INT2_PORT, + ACCEL_INT2_PIN, + true, + false, + true); + if (((rt_uint8_t)ACCEL_INT1_PORT % 2) || \ + ((rt_uint8_t)ACCEL_INT2_PORT % 2)) + { + NVIC_ClearPendingIRQ(GPIO_ODD_IRQn); + NVIC_SetPriority(GPIO_ODD_IRQn, EFM32_IRQ_PRI_DEFAULT); + NVIC_EnableIRQ(GPIO_ODD_IRQn); + } + if (!((rt_uint8_t)ACCEL_INT1_PORT % 2) || \ + !((rt_uint8_t)ACCEL_INT2_PORT % 2)) + { + NVIC_ClearPendingIRQ(GPIO_EVEN_IRQn); + NVIC_SetPriority(GPIO_EVEN_IRQn, EFM32_IRQ_PRI_DEFAULT); + NVIC_EnableIRQ(GPIO_EVEN_IRQn); + } + + /* Reset the interrupt flags: Part 2 */ + buf[0] = INTRST; + buf[1] = 0x00; + if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) + { + ret = -RT_ERROR; + break; + } + } + } while (0); + + return ret; } #endif @@ -536,203 +536,203 @@ rt_err_t efm_accel_config(rt_uint32_t config, * @note * * @param[in] mode - * 0, simple mode (assuming the device is placed on flat surface) - * 1, interaction method + * 0, simple mode (assuming the device is placed on flat surface) + * 1, interaction method * * @param[in] period - * Time period to perform auto-zero calibration + * Time period to perform auto-zero calibration * * @return - * Error code + * Error code ******************************************************************************/ rt_err_t efm_accel_auto_zero(rt_uint8_t mode, rt_tick_t period) { - RT_ASSERT(accel != RT_NULL); + RT_ASSERT(accel != RT_NULL); - rt_timer_t calTimer; - struct efm32_accel_result_t min = {0, 0, 0}; - struct efm32_accel_result_t max = {0, 0, 0}; - struct efm32_accel_result_t temp, sum; - rt_int32_t simpleOffset[] = ACCEL_CAL_1G_VALUE; - rt_uint8_t cmd[7] = {0}; - rt_uint8_t i, j; + rt_timer_t calTimer; + struct efm32_accel_result_t min = {0, 0, 0}; + struct efm32_accel_result_t max = {0, 0, 0}; + struct efm32_accel_result_t temp, sum; + rt_int32_t simpleOffset[] = ACCEL_CAL_1G_VALUE; + rt_uint8_t cmd[7] = {0}; + rt_uint8_t i, j; - /* Reset offset */ + /* Reset offset */ #if (EFM32_USING_ACCEL == EFM32_INTERFACE_ADC) - accelOffset.x = 0; - accelOffset.y = 0; - accelOffset.z = 0; + accelOffset.x = 0; + accelOffset.y = 0; + accelOffset.z = 0; #elif (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC) - cmd[0] = XOFFL; - if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, cmd, sizeof(cmd)) == 0) - { - return -RT_ERROR; - } + cmd[0] = XOFFL; + if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, cmd, sizeof(cmd)) == 0) + { + return -RT_ERROR; + } #endif - if (mode == ACCEL_CAL_SIMPLE) - { - /* Simple mode */ - for (j = 0; j < ACCEL_CAL_ROUND; j++) - { - sum.x = 0x0; - sum.y = 0x0; - sum.z = 0x0; - - for (i = 0; i < ACCEL_CAL_SAMPLES; i++) - { + if (mode == ACCEL_CAL_SIMPLE) + { + /* Simple mode */ + for (j = 0; j < ACCEL_CAL_ROUND; j++) + { + sum.x = 0x0; + sum.y = 0x0; + sum.z = 0x0; + + for (i = 0; i < ACCEL_CAL_SAMPLES; i++) + { #if (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC) - /* Waiting for data ready */ - while(!GPIO_PinInGet(ACCEL_INT1_PORT, ACCEL_INT1_PIN)); + /* Waiting for data ready */ + while(!GPIO_PinInGet(ACCEL_INT1_PORT, ACCEL_INT1_PIN)); #endif - if (efm_accel_get_data(&temp, false) != RT_EOK) - { - return -RT_ERROR; - } - sum.x += temp.x; - sum.y += temp.y; - sum.z += temp.z; - } + if (efm_accel_get_data(&temp, false) != RT_EOK) + { + return -RT_ERROR; + } + sum.x += temp.x; + sum.y += temp.y; + sum.z += temp.z; + } #if (EFM32_USING_ACCEL == EFM32_INTERFACE_ADC) - temp.x = sum.x / ACCEL_CAL_SAMPLES; - temp.y = sum.y / ACCEL_CAL_SAMPLES; - temp.z = sum.z / ACCEL_CAL_SAMPLES - simpleOffset[ACCEL_G_SELECT]; - if ((temp.x == 0) && (temp.y == 0) && \ - (temp.z == 0)) - { - accel_debug("Accel: Offset %+d %+d %+d\n", - accelOffset.x, accelOffset.y, accelOffset.z); - break; - } - accelOffset.x -= temp.x; - accelOffset.y -= temp.y; - accelOffset.z -= temp.z; + temp.x = sum.x / ACCEL_CAL_SAMPLES; + temp.y = sum.y / ACCEL_CAL_SAMPLES; + temp.z = sum.z / ACCEL_CAL_SAMPLES - simpleOffset[ACCEL_G_SELECT]; + if ((temp.x == 0) && (temp.y == 0) && \ + (temp.z == 0)) + { + accel_debug("Accel: Offset %+d %+d %+d\n", + accelOffset.x, accelOffset.y, accelOffset.z); + break; + } + accelOffset.x -= temp.x; + accelOffset.y -= temp.y; + accelOffset.z -= temp.z; #elif (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC) - temp.x = sum.x / (ACCEL_CAL_SAMPLES >> 1); - temp.y = sum.y / (ACCEL_CAL_SAMPLES >> 1); - temp.z = sum.z / (ACCEL_CAL_SAMPLES >> 1) \ - - (simpleOffset[ACCEL_G_SELECT] << 1); - if ((temp.x == 0) && (temp.y == 0) && \ - (temp.z == 0)) - { - break; - } - - /* Set offset drift registers */ - max.x -= temp.x; - max.y -= temp.y; - max.z -= temp.z; - *(rt_int16_t *)&cmd[1] = (rt_int16_t)max.x; - *(rt_int16_t *)&cmd[3] = (rt_int16_t)max.y; - *(rt_int16_t *)&cmd[5] = (rt_int16_t)max.z; - if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, cmd, sizeof(cmd)) == 0) - { - return -RT_ERROR; - } - accel_debug("Accel: Offset %+d %+d %+d\n", *(rt_int16_t *)&cmd[1], \ - *(rt_int16_t *)&cmd[3], *(rt_int16_t *)&cmd[5]); + temp.x = sum.x / (ACCEL_CAL_SAMPLES >> 1); + temp.y = sum.y / (ACCEL_CAL_SAMPLES >> 1); + temp.z = sum.z / (ACCEL_CAL_SAMPLES >> 1) \ + - (simpleOffset[ACCEL_G_SELECT] << 1); + if ((temp.x == 0) && (temp.y == 0) && \ + (temp.z == 0)) + { + break; + } + + /* Set offset drift registers */ + max.x -= temp.x; + max.y -= temp.y; + max.z -= temp.z; + *(rt_int16_t *)&cmd[1] = (rt_int16_t)max.x; + *(rt_int16_t *)&cmd[3] = (rt_int16_t)max.y; + *(rt_int16_t *)&cmd[5] = (rt_int16_t)max.z; + if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, cmd, sizeof(cmd)) == 0) + { + return -RT_ERROR; + } + accel_debug("Accel: Offset %+d %+d %+d\n", *(rt_int16_t *)&cmd[1], \ + *(rt_int16_t *)&cmd[3], *(rt_int16_t *)&cmd[5]); #endif - rt_thread_sleep(1); - } - } - else - { - /* Interact mode */ - if ((calTimer = rt_timer_create( - "cal_tmr", - efm_accel_timer, - RT_NULL, - period, - RT_TIMER_FLAG_ONE_SHOT)) == RT_NULL) - { - accel_debug("Accel err: Create timer failed!\n"); - return -RT_ERROR; - } - - accelInTime = true; - rt_timer_start(calTimer); - do - { - sum.x = 0x0; - sum.y = 0x0; - sum.z = 0x0; - - for (i = 0; i < ACCEL_CAL_SAMPLES; i++) - { + rt_thread_sleep(1); + } + } + else + { + /* Interact mode */ + if ((calTimer = rt_timer_create( + "cal_tmr", + efm_accel_timer, + RT_NULL, + period, + RT_TIMER_FLAG_ONE_SHOT)) == RT_NULL) + { + accel_debug("Accel err: Create timer failed!\n"); + return -RT_ERROR; + } + + accelInTime = true; + rt_timer_start(calTimer); + do + { + sum.x = 0x0; + sum.y = 0x0; + sum.z = 0x0; + + for (i = 0; i < ACCEL_CAL_SAMPLES; i++) + { #if (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC) - /* Waiting for data ready */ - while(!GPIO_PinInGet(ACCEL_INT1_PORT, ACCEL_INT1_PIN)); + /* Waiting for data ready */ + while(!GPIO_PinInGet(ACCEL_INT1_PORT, ACCEL_INT1_PIN)); #endif - if (efm_accel_get_data(&temp, false) != RT_EOK) - { - return -RT_ERROR; - } - sum.x += temp.x; - sum.y += temp.y; - sum.z += temp.z; - } - sum.x /= ACCEL_CAL_SAMPLES; - sum.y /= ACCEL_CAL_SAMPLES; - sum.z /= ACCEL_CAL_SAMPLES; - if (sum.x < min.x) - { - min.x = sum.x; - } - if (sum.y < min.y) - { - min.y = sum.y; - } - if (sum.z < min.z) - { - min.z = sum.z; - } - if (sum.x > max.x) - { - max.x = sum.x; - } - if (sum.y > max.y) - { - max.y = sum.y; - } - if (sum.z > max.z) - { - max.z = sum.z; - } - rt_thread_sleep(1); - } while (accelInTime); - - accel_debug("Accel: Min %+d %+d %+d, max %+d %+d %+d\n", - min.x, min.y, min.z, max.x, max.y, max.z); + if (efm_accel_get_data(&temp, false) != RT_EOK) + { + return -RT_ERROR; + } + sum.x += temp.x; + sum.y += temp.y; + sum.z += temp.z; + } + sum.x /= ACCEL_CAL_SAMPLES; + sum.y /= ACCEL_CAL_SAMPLES; + sum.z /= ACCEL_CAL_SAMPLES; + if (sum.x < min.x) + { + min.x = sum.x; + } + if (sum.y < min.y) + { + min.y = sum.y; + } + if (sum.z < min.z) + { + min.z = sum.z; + } + if (sum.x > max.x) + { + max.x = sum.x; + } + if (sum.y > max.y) + { + max.y = sum.y; + } + if (sum.z > max.z) + { + max.z = sum.z; + } + rt_thread_sleep(1); + } while (accelInTime); + + accel_debug("Accel: Min %+d %+d %+d, max %+d %+d %+d\n", + min.x, min.y, min.z, max.x, max.y, max.z); #if (EFM32_USING_ACCEL == EFM32_INTERFACE_ADC) - accelOffset.x = -((min.x + max.x) >> 1); - accelOffset.y = -((min.y + max.y) >> 1); - accelOffset.z = -((min.z + max.z) >> 1); + accelOffset.x = -((min.x + max.x) >> 1); + accelOffset.y = -((min.y + max.y) >> 1); + accelOffset.z = -((min.z + max.z) >> 1); - accel_debug("Accel: Offset %+d %+d %+d\n", - accelOffset.x, accelOffset.y, accelOffset.z); + accel_debug("Accel: Offset %+d %+d %+d\n", + accelOffset.x, accelOffset.y, accelOffset.z); #elif (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC) - /* Set offset drift registers */ - *(rt_int16_t *)&cmd[1] = (rt_int16_t)-(min.x + max.x); - *(rt_int16_t *)&cmd[3] = (rt_int16_t)-(min.y + max.y); - *(rt_int16_t *)&cmd[5] = (rt_int16_t)-(min.z + max.z); - if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, cmd, sizeof(cmd)) == 0) - { - return -RT_ERROR; - } - - accel_debug("Accel: Offset %+d %+d %+d\n", - *(rt_int16_t *)&cmd[1], *(rt_int16_t *)&cmd[3], *(rt_int16_t *)&cmd[5]); + /* Set offset drift registers */ + *(rt_int16_t *)&cmd[1] = (rt_int16_t)-(min.x + max.x); + *(rt_int16_t *)&cmd[3] = (rt_int16_t)-(min.y + max.y); + *(rt_int16_t *)&cmd[5] = (rt_int16_t)-(min.z + max.z); + if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, cmd, sizeof(cmd)) == 0) + { + return -RT_ERROR; + } + + accel_debug("Accel: Offset %+d %+d %+d\n", + *(rt_int16_t *)&cmd[1], *(rt_int16_t *)&cmd[3], *(rt_int16_t *)&cmd[5]); #endif - rt_timer_delete(calTimer); - } + rt_timer_delete(calTimer); + } - return RT_EOK; + return RT_EOK; } /***************************************************************************//** @@ -744,147 +744,147 @@ rt_err_t efm_accel_auto_zero(rt_uint8_t mode, rt_tick_t period) * @note * * @return - * Error code + * Error code ******************************************************************************/ rt_err_t efm_accel_init(void) { - rt_err_t ret; - - ret = RT_EOK; - do - { - /* Find ADC device */ - accel = rt_device_find(ACCEL_USING_DEVICE_NAME); - if (accel == RT_NULL) - { - accel_debug("Accel err: Can't find device: %s!\n", ACCEL_USING_DEVICE_NAME); - ret = -RT_ERROR; - break; - } - accel_debug("Accel: Find device %s\n", ACCEL_USING_DEVICE_NAME); - - /* --------- ADC interface --------- */ + rt_err_t ret; + + ret = RT_EOK; + do + { + /* Find ADC device */ + accel = rt_device_find(ACCEL_USING_DEVICE_NAME); + if (accel == RT_NULL) + { + accel_debug("Accel err: Can't find device: %s!\n", ACCEL_USING_DEVICE_NAME); + ret = -RT_ERROR; + break; + } + accel_debug("Accel: Find device %s\n", ACCEL_USING_DEVICE_NAME); + + /* --------- ADC interface --------- */ #if (EFM32_USING_ACCEL == EFM32_INTERFACE_ADC) - ADC_InitScan_TypeDef scanInit = ADC_INITSCAN_DEFAULT; + ADC_InitScan_TypeDef scanInit = ADC_INITSCAN_DEFAULT; #if defined(EFM32_GXXX_DK) - /* Enable accelerometer */ - DVK_enablePeripheral(DVK_ACCEL); - /* Select g-range */ + /* Enable accelerometer */ + DVK_enablePeripheral(DVK_ACCEL); + /* Select g-range */ #if (ACCEL_G_SELECT == 0) - DVK_disablePeripheral(DVK_ACCEL_GSEL); + DVK_disablePeripheral(DVK_ACCEL_GSEL); #elif (ACCEL_G_SELECT == 1) - DVK_enablePeripheral(DVK_ACCEL_GSEL); + DVK_enablePeripheral(DVK_ACCEL_GSEL); #else #error "Wrong value for ACCEL_G_SELECT" #endif #endif - /* Init ADC for scan mode */ - scanInit.reference = adcRefVDD; - scanInit.input = ACCEL_X_ADC_CH | ACCEL_Y_ADC_CH | ACCEL_Z_ADC_CH; - - control.scan.init = &scanInit; - if ((ret = accel->control(accel, RT_DEVICE_CTRL_ADC_MODE, \ - (void *)&control)) != RT_EOK) - { - break; - } - - /* --------- IIC interface --------- */ + /* Init ADC for scan mode */ + scanInit.reference = adcRefVDD; + scanInit.input = ACCEL_X_ADC_CH | ACCEL_Y_ADC_CH | ACCEL_Z_ADC_CH; + + control.scan.init = &scanInit; + if ((ret = accel->control(accel, RT_DEVICE_CTRL_ADC_MODE, \ + (void *)&control)) != RT_EOK) + { + break; + } + + /* --------- IIC interface --------- */ #elif (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC) - rt_uint8_t cmd[2]; - - /* Initialize */ - if ((ret = accel->control(accel, RT_DEVICE_CTRL_IIC_SETTING, \ - (void *)&control)) != RT_EOK) - { - break; - } - - if (efm_accel_config( - ACCEL_MODE_MEASUREMENT | ACCEL_RANGE_2G, - EFM32_NO_DATA, - EFM32_NO_DATA, - EFM32_NO_DATA, - EFM32_NO_DATA, - EFM32_NO_DATA) != RT_EOK) - { - break; - } - - /* Config interrupt pin1 */ - GPIO_PinModeSet(ACCEL_INT1_PORT, ACCEL_INT1_PIN, gpioModeInput, 0); - /* Config interrupt pin2 */ - GPIO_PinModeSet(ACCEL_INT2_PORT, ACCEL_INT2_PIN, gpioModeInput, 0); + rt_uint8_t cmd[2]; + + /* Initialize */ + if ((ret = accel->control(accel, RT_DEVICE_CTRL_IIC_SETTING, \ + (void *)&control)) != RT_EOK) + { + break; + } + + if (efm_accel_config( + ACCEL_MODE_MEASUREMENT | ACCEL_RANGE_2G, + EFM32_NO_DATA, + EFM32_NO_DATA, + EFM32_NO_DATA, + EFM32_NO_DATA, + EFM32_NO_DATA) != RT_EOK) + { + break; + } + + /* Config interrupt pin1 */ + GPIO_PinModeSet(ACCEL_INT1_PORT, ACCEL_INT1_PIN, gpioModeInput, 0); + /* Config interrupt pin2 */ + GPIO_PinModeSet(ACCEL_INT2_PORT, ACCEL_INT2_PIN, gpioModeInput, 0); #endif - accel_debug("Accel: Init OK\n"); - return RT_EOK; - } while (0); + accel_debug("Accel: Init OK\n"); + return RT_EOK; + } while (0); - accel_debug("Accel err: Init failed!\n"); - return -RT_ERROR; + accel_debug("Accel err: Init failed!\n"); + return -RT_ERROR; } /******************************************************************************* - * Export to FINSH + * Export to FINSH ******************************************************************************/ #ifdef RT_USING_FINSH #include void accel_cal(rt_uint8_t mode, rt_uint32_t second) { - if (efm_accel_auto_zero(mode, RT_TICK_PER_SECOND * second) != RT_EOK) - { - rt_kprintf("Error occurred."); - return; - } + if (efm_accel_auto_zero(mode, RT_TICK_PER_SECOND * second) != RT_EOK) + { + rt_kprintf("Error occurred."); + return; + } - rt_kprintf("Calibration done.\n"); + rt_kprintf("Calibration done.\n"); } FINSH_FUNCTION_EXPORT(accel_cal, auto-zero calibration.) void list_accel(void) { - struct efm32_accel_result_t data; + struct efm32_accel_result_t data; - efm_accel_get_data(&data, false); - rt_kprintf("X: %d, Y: %d, Z: %d\n", data.x, data.y, data.z); + efm_accel_get_data(&data, false); + rt_kprintf("X: %d, Y: %d, Z: %d\n", data.x, data.y, data.z); } FINSH_FUNCTION_EXPORT(list_accel, list accelerometer info.) void test_accel(rt_uint8_t mode) { - if (mode == 0) - { - if (efm_accel_config( - ACCEL_MODE_LEVEL | ACCEL_RANGE_8G | ACCEL_INT_LEVEL_PULSE | \ - ACCEL_SOURCE_LEVEL_X | ACCEL_SOURCE_LEVEL_Y, - 0x1f, - EFM32_NO_DATA, - EFM32_NO_DATA, - EFM32_NO_DATA, - EFM32_NO_DATA) != RT_EOK) - { - rt_kprintf("efm_accel_config(): error\n"); - return; - } - } - else - { - if (efm_accel_config( - ACCEL_MODE_PULSE | ACCEL_RANGE_8G | ACCEL_INT_SINGLE_DOUBLE | \ - ACCEL_SOURCE_PULSE_X | ACCEL_SOURCE_PULSE_Y, - 0x1f, - 0x1f, - 200, - 255, - 255) != RT_EOK) - { - rt_kprintf("efm_accel_config(): error\n"); - return; - } - } + if (mode == 0) + { + if (efm_accel_config( + ACCEL_MODE_LEVEL | ACCEL_RANGE_8G | ACCEL_INT_LEVEL_PULSE | \ + ACCEL_SOURCE_LEVEL_X | ACCEL_SOURCE_LEVEL_Y, + 0x1f, + EFM32_NO_DATA, + EFM32_NO_DATA, + EFM32_NO_DATA, + EFM32_NO_DATA) != RT_EOK) + { + rt_kprintf("efm_accel_config(): error\n"); + return; + } + } + else + { + if (efm_accel_config( + ACCEL_MODE_PULSE | ACCEL_RANGE_8G | ACCEL_INT_SINGLE_DOUBLE | \ + ACCEL_SOURCE_PULSE_X | ACCEL_SOURCE_PULSE_Y, + 0x1f, + 0x1f, + 200, + 255, + 255) != RT_EOK) + { + rt_kprintf("efm_accel_config(): error\n"); + return; + } + } } FINSH_FUNCTION_EXPORT(test_accel, list accelerometer info.) #endif diff --git a/bsp/efm32/dev_accel.h b/bsp/efm32/dev_accel.h index 2e12d797d3..cc75631834 100644 --- a/bsp/efm32/dev_accel.h +++ b/bsp/efm32/dev_accel.h @@ -1,8 +1,8 @@ /***************************************************************************//** - * @file dev_accel.h - * @brief Accelerometer driver of RT-Thread RTOS for EFM32 + * @file dev_accel.h + * @brief Accelerometer driver of RT-Thread RTOS for EFM32 * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -10,10 +10,10 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes - * 2011-07-13 onelife Initial creation for using EFM32 ADC module to + * Date Author Notes + * 2011-07-13 onelife Initial creation for using EFM32 ADC module to * interface the Freescale MMA7361L - * 2011-08-02 onelife Add digital interface support of using EFM32 IIC + * 2011-08-02 onelife Add digital interface support of using EFM32 IIC * module for the Freescale MMA7455L ******************************************************************************/ #ifndef __DEV_ACCEL_H__ @@ -27,95 +27,95 @@ /* Exported types ------------------------------------------------------------*/ struct efm32_accel_result_t { - rt_int32_t x; - rt_int32_t y; - rt_int32_t z; + rt_int32_t x; + rt_int32_t y; + rt_int32_t z; }; /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ -/* MMA7361LC - g-Select g-Range Sensitivity - 0 1.5 g 800 mV/g - 1 6 g 206 mV/g +/* MMA7361LC + g-Select g-Range Sensitivity + 0 1.5 g 800 mV/g + 1 6 g 206 mV/g - MMA7455L - g-Select g-Range Sensitivity - 0 2 g 64 LSB/g - 1 4 g 32 LSB/g - 2 8 g 16 LSB/g + MMA7455L + g-Select g-Range Sensitivity + 0 2 g 64 LSB/g + 1 4 g 32 LSB/g + 2 8 g 16 LSB/g */ -#define ACCEL_G_SELECT (0) +#define ACCEL_G_SELECT (0) -#define ACCEL_CAL_SAMPLES (4) /* Must be multiple of 2 */ -#define ACCEL_CAL_ROUND (50) -#define ACCEL_CAL_SIMPLE (0) -#define ACCEL_CAL_INTERACT (1) +#define ACCEL_CAL_SAMPLES (4) /* Must be multiple of 2 */ +#define ACCEL_CAL_ROUND (50) +#define ACCEL_CAL_SIMPLE (0) +#define ACCEL_CAL_INTERACT (1) #if (EFM32_USING_ACCEL == EFM32_INTERFACE_ADC) /* Reading_at_1g = Sensitivity * Max_reading / Refference_voltage */ -#define ACCEL_CAL_1G_VALUE {993, 256} +#define ACCEL_CAL_1G_VALUE {993, 256} -#define ACCEL_X_ADC_CH ADC_SCANCTRL_INPUTMASK_CH2 -#define ACCEL_Y_ADC_CH ADC_SCANCTRL_INPUTMASK_CH3 -#define ACCEL_Z_ADC_CH ADC_SCANCTRL_INPUTMASK_CH4 +#define ACCEL_X_ADC_CH ADC_SCANCTRL_INPUTMASK_CH2 +#define ACCEL_Y_ADC_CH ADC_SCANCTRL_INPUTMASK_CH3 +#define ACCEL_Z_ADC_CH ADC_SCANCTRL_INPUTMASK_CH4 #elif (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC) -#define ACCEL_CAL_1G_VALUE {0x3f, 0x1f, 0x0f} +#define ACCEL_CAL_1G_VALUE {0x3f, 0x1f, 0x0f} #define ACCEL_IIC_SLAVE_ADDRESS (0x1d) -#define ACCEL_INT1_PORT (gpioPortD) -#define ACCEL_INT1_PIN (13) -#define ACCEL_INT2_PORT (gpioPortD) -#define ACCEL_INT2_PIN (12) +#define ACCEL_INT1_PORT (gpioPortD) +#define ACCEL_INT1_PIN (13) +#define ACCEL_INT2_PORT (gpioPortD) +#define ACCEL_INT2_PIN (12) -#define ACCEL_MODE_STANDBY (1 << 0) -#define ACCEL_MODE_MEASUREMENT (1 << 1) -#define ACCEL_MODE_LEVEL (1 << 2) -#define ACCEL_MODE_PULSE (1 << 3) -#define ACCEL_RANGE_8G (1 << 4) -#define ACCEL_RANGE_4G (1 << 5) -#define ACCEL_RANGE_2G (1 << 6) -#define ACCEL_INTPIN_INVERSE (1 << 7) -#define ACCEL_INT_LEVEL_PULSE (1 << 8) -#define ACCEL_INT_PULSE_LEVEL (1 << 9) -#define ACCEL_INT_SINGLE_DOUBLE (1 << 10) -#define ACCEL_DISABLE_X (1 << 11) -#define ACCEL_DISABLE_Y (1 << 12) -#define ACCEL_DISABLE_Z (1 << 13) -#define ACCEL_THRESHOLD_INTEGER (1 << 14) /* For level detection only */ -#define ACCEL_BANDWIDTH_125HZ (1 << 15) -#define ACCEL_LEVEL_AND (1 << 16) -#define ACCEL_PULSE_AND (1 << 17) -#define ACCEL_DRIVE_STRONG (1 << 18) -#define ACCEL_SOURCE_LEVEL_X (1 << 19) -#define ACCEL_SOURCE_LEVEL_Y (1 << 20) -#define ACCEL_SOURCE_LEVEL_Z (1 << 21) -#define ACCEL_SOURCE_PULSE_X (1 << 22) -#define ACCEL_SOURCE_PULSE_Y (1 << 23) -#define ACCEL_SOURCE_PULSE_Z (1 << 24) +#define ACCEL_MODE_STANDBY (1 << 0) +#define ACCEL_MODE_MEASUREMENT (1 << 1) +#define ACCEL_MODE_LEVEL (1 << 2) +#define ACCEL_MODE_PULSE (1 << 3) +#define ACCEL_RANGE_8G (1 << 4) +#define ACCEL_RANGE_4G (1 << 5) +#define ACCEL_RANGE_2G (1 << 6) +#define ACCEL_INTPIN_INVERSE (1 << 7) +#define ACCEL_INT_LEVEL_PULSE (1 << 8) +#define ACCEL_INT_PULSE_LEVEL (1 << 9) +#define ACCEL_INT_SINGLE_DOUBLE (1 << 10) +#define ACCEL_DISABLE_X (1 << 11) +#define ACCEL_DISABLE_Y (1 << 12) +#define ACCEL_DISABLE_Z (1 << 13) +#define ACCEL_THRESHOLD_INTEGER (1 << 14) /* For level detection only */ +#define ACCEL_BANDWIDTH_125HZ (1 << 15) +#define ACCEL_LEVEL_AND (1 << 16) +#define ACCEL_PULSE_AND (1 << 17) +#define ACCEL_DRIVE_STRONG (1 << 18) +#define ACCEL_SOURCE_LEVEL_X (1 << 19) +#define ACCEL_SOURCE_LEVEL_Y (1 << 20) +#define ACCEL_SOURCE_LEVEL_Z (1 << 21) +#define ACCEL_SOURCE_PULSE_X (1 << 22) +#define ACCEL_SOURCE_PULSE_Y (1 << 23) +#define ACCEL_SOURCE_PULSE_Z (1 << 24) -#define ACCEL_SHIFT_MODE (0) -#define ACCEL_SHIFT_RANGE (4) -#define ACCEL_SHIFT_INT (8) -#define ACCEL_SHIFT_DISABLE (11) -#define ACCEL_SHIFT_SOURCE (19) +#define ACCEL_SHIFT_MODE (0) +#define ACCEL_SHIFT_RANGE (4) +#define ACCEL_SHIFT_INT (8) +#define ACCEL_SHIFT_DISABLE (11) +#define ACCEL_SHIFT_SOURCE (19) -#define ACCEL_MASK_MODE (0X0000000f << ACCEL_SHIFT_MODE) -#define ACCEL_MASK_RANGE (0X00000007 << ACCEL_SHIFT_RANGE) -#define ACCEL_MASK_INT (0X00000007 << ACCEL_SHIFT_INT) -#define ACCEL_MASK_DISABLE (0X00000007 << ACCEL_SHIFT_DISABLE) -#define ACCEL_MASK_SOURCE (0X0000003f << ACCEL_SHIFT_SOURCE) +#define ACCEL_MASK_MODE (0X0000000f << ACCEL_SHIFT_MODE) +#define ACCEL_MASK_RANGE (0X00000007 << ACCEL_SHIFT_RANGE) +#define ACCEL_MASK_INT (0X00000007 << ACCEL_SHIFT_INT) +#define ACCEL_MASK_DISABLE (0X00000007 << ACCEL_SHIFT_DISABLE) +#define ACCEL_MASK_SOURCE (0X0000003f << ACCEL_SHIFT_SOURCE) #endif /* Exported functions ------------------------------------------------------- */ rt_err_t efm_accel_get_data(struct efm32_accel_result_t *data, - rt_bool_t lowResolution); + rt_bool_t lowResolution); rt_err_t efm_accel_config(rt_uint32_t config, - rt_uint8_t level_threshold, - rt_uint8_t pulse_threshold, - rt_uint8_t pulse_duration, - rt_uint8_t pulse_latency, - rt_uint8_t pulse_duration2); + rt_uint8_t level_threshold, + rt_uint8_t pulse_threshold, + rt_uint8_t pulse_duration, + rt_uint8_t pulse_latency, + rt_uint8_t pulse_duration2); rt_err_t efm_accel_auto_zero(rt_uint8_t mode, rt_tick_t period); rt_err_t efm_accel_init(void); diff --git a/bsp/efm32/dev_keys.c b/bsp/efm32/dev_keys.c index a7a58ff20f..15d306b36b 100644 --- a/bsp/efm32/dev_keys.c +++ b/bsp/efm32/dev_keys.c @@ -1,8 +1,8 @@ /***************************************************************************//** - * @file dev_keys.c - * @brief Keys driver of RT-Thread RTOS for EFM32 + * @file dev_keys.c + * @brief Keys driver of RT-Thread RTOS for EFM32 * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -10,7 +10,7 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes + * Date Author Notes * 2011-12-29 onelife Initial creation for EFM32GG_DK3750 board ******************************************************************************/ @@ -48,14 +48,14 @@ static rt_bool_t click; /* Private functions ---------------------------------------------------------*/ /***************************************************************************//** * @brief - * Keys interrupt handler + * Keys interrupt handler * * @details * * @note * * @param[in] device - * Pointer to device descriptor + * Pointer to device descriptor ******************************************************************************/ static void efm32_keys_isr(rt_device_t dev) { @@ -158,18 +158,18 @@ static void efm32_keys_isr(rt_device_t dev) /***************************************************************************//** * @brief - * Keys timeout handler + * Keys timeout handler * * @details * * @note * * @param[in] param - * Parameter + * Parameter ******************************************************************************/ static void efm32_keys_timer_isr(void *param) { - rt_uint16_t joystick; + rt_uint16_t joystick; joystick = DVK_getJoystick(); @@ -277,11 +277,11 @@ void efm32_hw_keys_init(void) GPIO_IntConfig(KEYS_INT_PORT, KEYS_INT_PIN, true, true, true); efm32_irq_hook_init_t hook; - hook.type = efm32_irq_type_gpio; - hook.unit = KEYS_INT_PIN; - hook.cbFunc = efm32_keys_isr; - hook.userPtr = RT_NULL; - efm32_irq_hook_register(&hook); + hook.type = efm32_irq_type_gpio; + hook.unit = KEYS_INT_PIN; + hook.cbFunc = efm32_keys_isr; + hook.userPtr = RT_NULL; + efm32_irq_hook_register(&hook); if ((rt_uint8_t)KEYS_INT_PIN % 2) { @@ -299,12 +299,12 @@ void efm32_hw_keys_init(void) /* Enable DVK joystick interrupt */ DVK_enableInterrupt(BC_INTEN_JOYSTICK); - rt_timer_init(&joy.timer, - "joy_tmr", - efm32_keys_timer_isr, - RT_NULL, - KEYS_POLL_TIME, - RT_TIMER_FLAG_PERIODIC); + rt_timer_init(&joy.timer, + "joy_tmr", + efm32_keys_timer_isr, + RT_NULL, + KEYS_POLL_TIME, + RT_TIMER_FLAG_PERIODIC); joy_dev.init = efm32_keys_init; joy_dev.open = RT_NULL; diff --git a/bsp/efm32/dev_keys.h b/bsp/efm32/dev_keys.h index 6e66617331..87f8fe95fd 100644 --- a/bsp/efm32/dev_keys.h +++ b/bsp/efm32/dev_keys.h @@ -1,8 +1,8 @@ /***************************************************************************//** - * @file dev_keys.h - * @brief Keys driver of RT-Thread RTOS for EFM32 + * @file dev_keys.h + * @brief Keys driver of RT-Thread RTOS for EFM32 * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -10,7 +10,7 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes + * Date Author Notes * 2011-12-29 onelife Initial creation for EFM32GG_DK3750 board ******************************************************************************/ #ifndef __DEV_KEYS_H__ diff --git a/bsp/efm32/dev_lcd.c b/bsp/efm32/dev_lcd.c index 0a2d469d78..c4cbbcce21 100644 --- a/bsp/efm32/dev_lcd.c +++ b/bsp/efm32/dev_lcd.c @@ -1,8 +1,8 @@ /***************************************************************************//** - * @file dev_lcd.c - * @brief LCD driver of RT-Thread RTOS for EFM32 + * @file dev_lcd.c + * @brief LCD driver of RT-Thread RTOS for EFM32 * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -10,7 +10,7 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes + * Date Author Notes * 2011-12-16 onelife Initial creation of address mapped method (pixel * drive) for EFM32GG_DK3750 board * 2011-12-29 onelife Add direct drive method (frame buffer) support @@ -451,48 +451,48 @@ rt_err_t efm32_spiLcd_writeRegister(rt_uint8_t reg, rt_uint16_t data) /***************************************************************************//** * @brief - * Register LCD device + * Register LCD device * * @details * * @note * * @param[in] device - * Pointer to device descriptor + * Pointer to device descriptor * * @param[in] name - * Device name + * Device name * * @param[in] flag - * Configuration flags + * Configuration flags * * @param[in] iic - * Pointer to IIC device descriptor + * Pointer to IIC device descriptor * * @return - * Error code + * Error code ******************************************************************************/ rt_err_t efm32_spiLcd_register( - rt_device_t device, - const char *name, - rt_uint32_t flag, - void *data) + rt_device_t device, + const char *name, + rt_uint32_t flag, + void *data) { - RT_ASSERT(device != RT_NULL); - - device->type = RT_Device_Class_Graphic; - device->rx_indicate = RT_NULL; - device->tx_complete = RT_NULL; - device->init = RT_NULL; - device->open = RT_NULL; - device->close = RT_NULL; - device->read = RT_NULL; - device->write = RT_NULL; - device->control = efm32_spiLcd_control; - device->user_data = data; - - /* register a character device */ - return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); + RT_ASSERT(device != RT_NULL); + + device->type = RT_Device_Class_Graphic; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->init = RT_NULL; + device->open = RT_NULL; + device->close = RT_NULL; + device->read = RT_NULL; + device->write = RT_NULL; + device->control = efm32_spiLcd_control; + device->user_data = data; + + /* register a character device */ + return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); } /***************************************************************************//** @@ -511,18 +511,18 @@ void efm32_spiLcd_init(void) DMD_DisplayGeometry *geometry; rt_uint32_t ret; - do - { + do + { USART_InitSync_TypeDef init = USART_INITSYNC_DEFAULT; - /* Find SPI device */ - lcd = rt_device_find(LCD_USING_DEVICE_NAME); - if (lcd == RT_NULL) - { - lcd_debug("LCD err: Can't find %s!\n", LCD_USING_DEVICE_NAME); - break; - } - lcd_debug("LCD: Find device %s\n", LCD_USING_DEVICE_NAME); + /* Find SPI device */ + lcd = rt_device_find(LCD_USING_DEVICE_NAME); + if (lcd == RT_NULL) + { + lcd_debug("LCD err: Can't find %s!\n", LCD_USING_DEVICE_NAME); + break; + } + lcd_debug("LCD: Find device %s\n", LCD_USING_DEVICE_NAME); /* Config CS pin */ usart = (struct efm32_usart_device_t *)(lcd->user_data); @@ -647,7 +647,7 @@ void efm32_spiLcd_init(void) } /* Init LCD info */ - flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_DMA_TX; + flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_DMA_TX; lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P; lcd_info.bits_per_pixel = 16; lcd_info.width = geometry->xSize; diff --git a/bsp/efm32/dev_lcd.h b/bsp/efm32/dev_lcd.h index 075bed64ba..4c59286ef6 100644 --- a/bsp/efm32/dev_lcd.h +++ b/bsp/efm32/dev_lcd.h @@ -1,8 +1,8 @@ /***************************************************************************//** - * @file dev_lcd.h - * @brief LCD driver of RT-Thread RTOS for EFM32 + * @file dev_lcd.h + * @brief LCD driver of RT-Thread RTOS for EFM32 * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -10,7 +10,7 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes + * Date Author Notes * 2011-12-16 onelife Initial creation of address mapped method (pixel * drive) for EFM32GG_DK3750 board ******************************************************************************/ diff --git a/bsp/efm32/dev_sflash.h b/bsp/efm32/dev_sflash.h index ae72ec678a..b7d2860f0d 100644 --- a/bsp/efm32/dev_sflash.h +++ b/bsp/efm32/dev_sflash.h @@ -20,85 +20,85 @@ /* Exported types ------------------------------------------------------------*/ enum sflash_inst_type_t { - /* Instruction only */ - sflash_inst_wren = 0x00, - sflash_inst_wrdi, - sflash_inst_rdid_l, - sflash_inst_rdid_s, - sflash_inst_rdsr, - sflash_inst_wrsr, - sflash_inst_be, - sflash_inst_dp, - sflash_inst_rdp, - /* Instruction and address */ - sflash_inst_wrlr, - sflash_inst_rdlr, - sflash_inst_read, - sflash_inst_potp, - sflash_inst_pp, - sflash_inst_difp, - sflash_inst_sse, - sflash_inst_se, - /* Instruction, address and dummy read */ - sflash_inst_read_f, - sflash_inst_dofr, - sflash_inst_rotp + /* Instruction only */ + sflash_inst_wren = 0x00, + sflash_inst_wrdi, + sflash_inst_rdid_l, + sflash_inst_rdid_s, + sflash_inst_rdsr, + sflash_inst_wrsr, + sflash_inst_be, + sflash_inst_dp, + sflash_inst_rdp, + /* Instruction and address */ + sflash_inst_wrlr, + sflash_inst_rdlr, + sflash_inst_read, + sflash_inst_potp, + sflash_inst_pp, + sflash_inst_difp, + sflash_inst_sse, + sflash_inst_se, + /* Instruction, address and dummy read */ + sflash_inst_read_f, + sflash_inst_dofr, + sflash_inst_rotp }; /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ -#define SFLASH_SPI_COMMAND_SKIP (1) -#define SFLASH_SPI_READ_SKIP (2) +#define SFLASH_SPI_COMMAND_SKIP (1) +#define SFLASH_SPI_READ_SKIP (2) -#define SFLASH_INST_CODE_WREN (0x06) -#define SFLASH_INST_CODE_WRDI (0x04) -#define SFLASH_INST_CODE_RDID_L (0x9F) -#define SFLASH_INST_CODE_RDID_S (0x9E) -#define SFLASH_INST_CODE_RDSR (0x05) -#define SFLASH_INST_CODE_WRSR (0x01) -#define SFLASH_INST_CODE_WRLR (0xE5) -#define SFLASH_INST_CODE_RDLR (0xE8) -#define SFLASH_INST_CODE_READ (0x03) -#define SFLASH_INST_CODE_READ_F (0x0B) -#define SFLASH_INST_CODE_DOFR (0x3B) -#define SFLASH_INST_CODE_ROTP (0x4B) -#define SFLASH_INST_CODE_POTP (0x42) -#define SFLASH_INST_CODE_PP (0x02) -#define SFLASH_INST_CODE_DIFP (0xA2) -#define SFLASH_INST_CODE_SSE (0x20) -#define SFLASH_INST_CODE_SE (0xD8) -#define SFLASH_INST_CODE_BE (0xC7) -#define SFLASH_INST_CODE_DP (0xB9) -#define SFLASH_INST_CODE_RDP (0xAB) +#define SFLASH_INST_CODE_WREN (0x06) +#define SFLASH_INST_CODE_WRDI (0x04) +#define SFLASH_INST_CODE_RDID_L (0x9F) +#define SFLASH_INST_CODE_RDID_S (0x9E) +#define SFLASH_INST_CODE_RDSR (0x05) +#define SFLASH_INST_CODE_WRSR (0x01) +#define SFLASH_INST_CODE_WRLR (0xE5) +#define SFLASH_INST_CODE_RDLR (0xE8) +#define SFLASH_INST_CODE_READ (0x03) +#define SFLASH_INST_CODE_READ_F (0x0B) +#define SFLASH_INST_CODE_DOFR (0x3B) +#define SFLASH_INST_CODE_ROTP (0x4B) +#define SFLASH_INST_CODE_POTP (0x42) +#define SFLASH_INST_CODE_PP (0x02) +#define SFLASH_INST_CODE_DIFP (0xA2) +#define SFLASH_INST_CODE_SSE (0x20) +#define SFLASH_INST_CODE_SE (0xD8) +#define SFLASH_INST_CODE_BE (0xC7) +#define SFLASH_INST_CODE_DP (0xB9) +#define SFLASH_INST_CODE_RDP (0xAB) -#define SFLASH_REPLY_LEN_WREN (0) -#define SFLASH_REPLY_LEN_WRDI (0) -#define SFLASH_REPLY_LEN_RDID_L (20) -#define SFLASH_REPLY_LEN_RDID_S (3) -#define SFLASH_REPLY_LEN_RDSR (1) -#define SFLASH_REPLY_LEN_WRSR (1) -#define SFLASH_REPLY_LEN_WRLR (1) -#define SFLASH_REPLY_LEN_RDLR (1) -#define SFLASH_REPLY_LEN_READ (-1) -#define SFLASH_REPLY_LEN_READ_F (-1) -#define SFLASH_REPLY_LEN_DOFR (-1) -#define SFLASH_REPLY_LEN_ROTP (65) -#define SFLASH_REPLY_LEN_POTP (65) -#define SFLASH_REPLY_LEN_PP (256) -#define SFLASH_REPLY_LEN_DIFP (256) -#define SFLASH_REPLY_LEN_SSE (0) -#define SFLASH_REPLY_LEN_SE (0) -#define SFLASH_REPLY_LEN_BE (0) -#define SFLASH_REPLY_LEN_DP (0) -#define SFLASH_REPLY_LEN_RDP (0) +#define SFLASH_REPLY_LEN_WREN (0) +#define SFLASH_REPLY_LEN_WRDI (0) +#define SFLASH_REPLY_LEN_RDID_L (20) +#define SFLASH_REPLY_LEN_RDID_S (3) +#define SFLASH_REPLY_LEN_RDSR (1) +#define SFLASH_REPLY_LEN_WRSR (1) +#define SFLASH_REPLY_LEN_WRLR (1) +#define SFLASH_REPLY_LEN_RDLR (1) +#define SFLASH_REPLY_LEN_READ (-1) +#define SFLASH_REPLY_LEN_READ_F (-1) +#define SFLASH_REPLY_LEN_DOFR (-1) +#define SFLASH_REPLY_LEN_ROTP (65) +#define SFLASH_REPLY_LEN_POTP (65) +#define SFLASH_REPLY_LEN_PP (256) +#define SFLASH_REPLY_LEN_DIFP (256) +#define SFLASH_REPLY_LEN_SSE (0) +#define SFLASH_REPLY_LEN_SE (0) +#define SFLASH_REPLY_LEN_BE (0) +#define SFLASH_REPLY_LEN_DP (0) +#define SFLASH_REPLY_LEN_RDP (0) /* Exported functions ------------------------------------------------------- */ rt_err_t efm_spiFlash_init(void); rt_err_t efm_spiFlash_deinit(void); rt_uint32_t efm_spiFlash_cmd( - enum sflash_inst_type_t command, - rt_uint32_t address, - rt_uint8_t *buffer, - rt_uint32_t size); + enum sflash_inst_type_t command, + rt_uint32_t address, + rt_uint8_t *buffer, + rt_uint32_t size); #endif /* __DEV_SFLASH_H__ */ diff --git a/bsp/efm32/drv_acmp.c b/bsp/efm32/drv_acmp.c index 1961fc4695..b9d24e8ebd 100644 --- a/bsp/efm32/drv_acmp.c +++ b/bsp/efm32/drv_acmp.c @@ -30,18 +30,18 @@ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ #ifdef RT_ACMP_DEBUG -#define acmp_debug(format,args...) rt_kprintf(format, ##args) +#define acmp_debug(format,args...) rt_kprintf(format, ##args) #else #define acmp_debug(format,args...) #endif /* Private variables ---------------------------------------------------------*/ #ifdef RT_USING_ACMP0 - static struct rt_device acmp0_device; + static struct rt_device acmp0_device; #endif #ifdef RT_USING_ACMP1 - static struct rt_device acmp1_device; + static struct rt_device acmp1_device; #endif /* Private function prototypes -----------------------------------------------*/ @@ -64,169 +64,169 @@ ACMP_WarmTime_TypeDef efm32_acmp_WarmTimeCalc(rt_uint32_t hfperFreq); ******************************************************************************/ static rt_err_t rt_acmp_init(rt_device_t dev) { - RT_ASSERT(dev != RT_NULL); + RT_ASSERT(dev != RT_NULL); - struct efm32_acmp_device_t *acmp; + struct efm32_acmp_device_t *acmp; - acmp = (struct efm32_acmp_device_t *)(dev->user_data); + acmp = (struct efm32_acmp_device_t *)(dev->user_data); - acmp->hook.cbFunc = RT_NULL; - acmp->hook.userPtr = RT_NULL; + acmp->hook.cbFunc = RT_NULL; + acmp->hook.userPtr = RT_NULL; - return RT_EOK; + return RT_EOK; } /***************************************************************************//** * @brief - * Configure ACMP device + * Configure ACMP device * * @details * * @note * * @param[in] dev - * Pointer to device descriptor + * Pointer to device descriptor * * @param[in] cmd - * ACMP control command + * ACMP control command * * @param[in] args - * Arguments + * Arguments * * @return - * Error code + * Error code ******************************************************************************/ static rt_err_t rt_acmp_control( - rt_device_t dev, - rt_uint8_t cmd, - void *args) + rt_device_t dev, + rt_uint8_t cmd, + void *args) { - RT_ASSERT(dev != RT_NULL); - - struct efm32_acmp_device_t *acmp; - - acmp = (struct efm32_acmp_device_t *)(dev->user_data); - - switch (cmd) - { - case RT_DEVICE_CTRL_SUSPEND: - /* Suspend device */ - dev->flag |= RT_DEVICE_FLAG_SUSPENDED; - ACMP_Disable(acmp->acmp_device); - break; - - case RT_DEVICE_CTRL_RESUME: - /* Resume device */ - dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; - ACMP_Enable(acmp->acmp_device); - break; - - case RT_DEVICE_CTRL_ACMP_INIT: - { - rt_bool_t int_en = false; - struct efm32_acmp_control_t *control; - - control = (struct efm32_acmp_control_t *)args; - acmp_debug("ACMP: control -> init start\n"); - - /* Configure ACMPn */ - if (control->init == RT_NULL) - { - return -RT_ERROR; - } - ACMP_Init(acmp->acmp_device, control->init); - ACMP_ChannelSet(acmp->acmp_device, control->negInput, control->posInput); - if (control->output != RT_NULL) - { - ACMP_GPIOSetup( - acmp->acmp_device, - control->output->location, - control->output->enable, - control->output->invert); - int_en = true; - } - if (control->hook.cbFunc != RT_NULL) - { - acmp->hook.cbFunc = control->hook.cbFunc; - acmp->hook.userPtr = control->hook.userPtr; - int_en = true; - } - - if (int_en) - { - /* Enable edge interrupt */ - ACMP_IntEnable(acmp->acmp_device, ACMP_IEN_EDGE); - ACMP_IntClear(acmp->acmp_device, ACMP_IFC_EDGE); - - /* Enable ACMP0/1 interrupt vector in NVIC */ - NVIC_ClearPendingIRQ(ACMP0_IRQn); - NVIC_SetPriority(ACMP0_IRQn, EFM32_IRQ_PRI_DEFAULT); - NVIC_EnableIRQ(ACMP0_IRQn); - } - } - break; - - case RT_DEVICE_CTRL_ACMP_OUTPUT: - *((rt_bool_t *)args) = \ - (acmp->acmp_device->STATUS & ACMP_STATUS_ACMPOUT) ? true : false; - break; - - default: - return -RT_ERROR; - } - - return RT_EOK; + RT_ASSERT(dev != RT_NULL); + + struct efm32_acmp_device_t *acmp; + + acmp = (struct efm32_acmp_device_t *)(dev->user_data); + + switch (cmd) + { + case RT_DEVICE_CTRL_SUSPEND: + /* Suspend device */ + dev->flag |= RT_DEVICE_FLAG_SUSPENDED; + ACMP_Disable(acmp->acmp_device); + break; + + case RT_DEVICE_CTRL_RESUME: + /* Resume device */ + dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; + ACMP_Enable(acmp->acmp_device); + break; + + case RT_DEVICE_CTRL_ACMP_INIT: + { + rt_bool_t int_en = false; + struct efm32_acmp_control_t *control; + + control = (struct efm32_acmp_control_t *)args; + acmp_debug("ACMP: control -> init start\n"); + + /* Configure ACMPn */ + if (control->init == RT_NULL) + { + return -RT_ERROR; + } + ACMP_Init(acmp->acmp_device, control->init); + ACMP_ChannelSet(acmp->acmp_device, control->negInput, control->posInput); + if (control->output != RT_NULL) + { + ACMP_GPIOSetup( + acmp->acmp_device, + control->output->location, + control->output->enable, + control->output->invert); + int_en = true; + } + if (control->hook.cbFunc != RT_NULL) + { + acmp->hook.cbFunc = control->hook.cbFunc; + acmp->hook.userPtr = control->hook.userPtr; + int_en = true; + } + + if (int_en) + { + /* Enable edge interrupt */ + ACMP_IntEnable(acmp->acmp_device, ACMP_IEN_EDGE); + ACMP_IntClear(acmp->acmp_device, ACMP_IFC_EDGE); + + /* Enable ACMP0/1 interrupt vector in NVIC */ + NVIC_ClearPendingIRQ(ACMP0_IRQn); + NVIC_SetPriority(ACMP0_IRQn, EFM32_IRQ_PRI_DEFAULT); + NVIC_EnableIRQ(ACMP0_IRQn); + } + } + break; + + case RT_DEVICE_CTRL_ACMP_OUTPUT: + *((rt_bool_t *)args) = \ + (acmp->acmp_device->STATUS & ACMP_STATUS_ACMPOUT) ? true : false; + break; + + default: + return -RT_ERROR; + } + + return RT_EOK; } /***************************************************************************//** * @brief - * Register ACMP device + * Register ACMP device * * @details * * @note * * @param[in] device - * Pointer to device descriptor + * Pointer to device descriptor * * @param[in] name - * Device name + * Device name * * @param[in] flag - * Configuration flags + * Configuration flags * * @param[in] acmp - * Pointer to ACMP device descriptor + * Pointer to ACMP device descriptor * * @return - * Error code + * Error code ******************************************************************************/ rt_err_t rt_hw_acmp_register( - rt_device_t device, - const char *name, - rt_uint32_t flag, - struct efm32_acmp_device_t *acmp) + rt_device_t device, + const char *name, + rt_uint32_t flag, + struct efm32_acmp_device_t *acmp) { - RT_ASSERT(device != RT_NULL); - - device->type = RT_Device_Class_Char; /* fixme: should be acmp type */ - device->rx_indicate = RT_NULL; - device->tx_complete = RT_NULL; - device->init = rt_acmp_init; - device->open = RT_NULL; - device->close = RT_NULL; - device->read = RT_NULL; - device->write = RT_NULL; - device->control = rt_acmp_control; - device->user_data = acmp; - - /* register a character device */ - return rt_device_register(device, name, flag); + RT_ASSERT(device != RT_NULL); + + device->type = RT_Device_Class_Char; /* fixme: should be acmp type */ + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->init = rt_acmp_init; + device->open = RT_NULL; + device->close = RT_NULL; + device->read = RT_NULL; + device->write = RT_NULL; + device->control = rt_acmp_control; + device->user_data = acmp; + + /* register a character device */ + return rt_device_register(device, name, flag); } /***************************************************************************//** * @brief - * ACMP edge trigger interrupt handler + * ACMP edge trigger interrupt handler * * @details * @@ -234,96 +234,96 @@ rt_err_t rt_hw_acmp_register( ******************************************************************************/ void rt_hw_acmp_isr(rt_device_t dev) { - RT_ASSERT(dev != RT_NULL); + RT_ASSERT(dev != RT_NULL); - struct efm32_acmp_device_t *acmp; + struct efm32_acmp_device_t *acmp; - acmp = (struct efm32_acmp_device_t *)(dev->user_data); + acmp = (struct efm32_acmp_device_t *)(dev->user_data); - if (acmp->hook.cbFunc != RT_NULL) - { - (acmp->hook.cbFunc)(acmp->hook.userPtr); - } + if (acmp->hook.cbFunc != RT_NULL) + { + (acmp->hook.cbFunc)(acmp->hook.userPtr); + } } /***************************************************************************//** * @brief - * Initialize the specified ACMP unit + * Initialize the specified ACMP unit * * @details * * @note * * @param[in] device - * Pointer to device descriptor + * Pointer to device descriptor * * @param[in] unitNumber - * Unit number + * Unit number * * @return - * Pointer to ACMP device + * Pointer to ACMP device ******************************************************************************/ static struct efm32_acmp_device_t *rt_hw_acmp_unit_init( - rt_device_t device, - rt_uint8_t unitNumber) + rt_device_t device, + rt_uint8_t unitNumber) { - struct efm32_acmp_device_t *acmp; - efm32_irq_hook_init_t hook; - CMU_Clock_TypeDef acmpClock; - - do - { - /* Allocate device */ - acmp = rt_malloc(sizeof(struct efm32_acmp_device_t)); - if (acmp == RT_NULL) - { - acmp_debug("ACMP err: no mem for ACMP%d\n", unitNumber); - break; - } - - /* Initialization */ - if (unitNumber >= ACMP_COUNT) - { - break; - } - switch (unitNumber) - { - case 0: - acmp->acmp_device = ACMP0; - acmpClock = (CMU_Clock_TypeDef)cmuClock_ACMP0; - break; - - case 1: - acmp->acmp_device = ACMP1; - acmpClock = (CMU_Clock_TypeDef)cmuClock_ACMP1; - break; - - default: - break; - } - - /* Enable ACMP clock */ - CMU_ClockEnable(acmpClock, true); - - /* Reset */ - ACMP_Reset(acmp->acmp_device); - - /* Config interrupt and NVIC */ - hook.type = efm32_irq_type_acmp; - hook.unit = unitNumber; - hook.cbFunc = rt_hw_acmp_isr; - hook.userPtr = device; - efm32_irq_hook_register(&hook); - - return acmp; - } while(0); - - if (acmp) - { - rt_free(acmp); - } - rt_kprintf("ACMP: Init failed!\n"); - return RT_NULL; + struct efm32_acmp_device_t *acmp; + efm32_irq_hook_init_t hook; + CMU_Clock_TypeDef acmpClock; + + do + { + /* Allocate device */ + acmp = rt_malloc(sizeof(struct efm32_acmp_device_t)); + if (acmp == RT_NULL) + { + acmp_debug("ACMP err: no mem for ACMP%d\n", unitNumber); + break; + } + + /* Initialization */ + if (unitNumber >= ACMP_COUNT) + { + break; + } + switch (unitNumber) + { + case 0: + acmp->acmp_device = ACMP0; + acmpClock = (CMU_Clock_TypeDef)cmuClock_ACMP0; + break; + + case 1: + acmp->acmp_device = ACMP1; + acmpClock = (CMU_Clock_TypeDef)cmuClock_ACMP1; + break; + + default: + break; + } + + /* Enable ACMP clock */ + CMU_ClockEnable(acmpClock, true); + + /* Reset */ + ACMP_Reset(acmp->acmp_device); + + /* Config interrupt and NVIC */ + hook.type = efm32_irq_type_acmp; + hook.unit = unitNumber; + hook.cbFunc = rt_hw_acmp_isr; + hook.userPtr = device; + efm32_irq_hook_register(&hook); + + return acmp; + } while(0); + + if (acmp) + { + rt_free(acmp); + } + rt_kprintf("ACMP: Init failed!\n"); + return RT_NULL; } /***************************************************************************//** @@ -338,20 +338,20 @@ static struct efm32_acmp_device_t *rt_hw_acmp_unit_init( ******************************************************************************/ void rt_hw_acmp_init(void) { - struct efm32_acmp_device_t *acmp; + struct efm32_acmp_device_t *acmp; #ifdef RT_USING_ACMP0 - if ((acmp = rt_hw_acmp_unit_init(&acmp0_device, 0)) != RT_NULL) - { - rt_hw_acmp_register(&acmp0_device, RT_ACMP0_NAME, EFM32_NO_DATA, acmp); - } + if ((acmp = rt_hw_acmp_unit_init(&acmp0_device, 0)) != RT_NULL) + { + rt_hw_acmp_register(&acmp0_device, RT_ACMP0_NAME, EFM32_NO_DATA, acmp); + } #endif #ifdef RT_USING_ACMP1 - if ((acmp = rt_hw_acmp_unit_init(&acmp1_device, 1)) != RT_NULL) - { - rt_hw_acmp_register(&acmp1_device, RT_ACMP1_NAME, EFM32_NO_DATA, acmp); - } + if ((acmp = rt_hw_acmp_unit_init(&acmp1_device, 1)) != RT_NULL) + { + rt_hw_acmp_register(&acmp1_device, RT_ACMP1_NAME, EFM32_NO_DATA, acmp); + } #endif } @@ -369,50 +369,50 @@ void rt_hw_acmp_init(void) ******************************************************************************/ ACMP_WarmTime_TypeDef efm32_acmp_WarmTimeCalc(rt_uint32_t hfperFreq) { - if (!hfperFreq) - { - hfperFreq = CMU_ClockFreqGet(cmuClock_HFPER); - - /* Just in case, make sure we get non-zero freq for below calculation */ - if (!hfperFreq) - { - hfperFreq = 1; - } - } - - /* Determine number of HFPERCLK cycle >= 10us */ - if (4 * 1000000 / hfperFreq > 10) - { - return acmpWarmTime4; - } - else if (8 * 1000000 / hfperFreq > 10) - { - return acmpWarmTime8; - } - else if (16 * 1000000 / hfperFreq > 10) - { - return acmpWarmTime16; - } - else if (32 * 1000000 / hfperFreq > 10) - { - return acmpWarmTime32; - } - else if (64 * 1000000 / hfperFreq > 10) - { - return acmpWarmTime64; - } - else if (128 * 1000000 / hfperFreq > 10) - { - return acmpWarmTime128; - } - else if (256 * 1000000 / hfperFreq > 10) - { - return acmpWarmTime256; - } - else if (512 * 1000000 / hfperFreq > 10) - { - return acmpWarmTime512; - } + if (!hfperFreq) + { + hfperFreq = CMU_ClockFreqGet(cmuClock_HFPER); + + /* Just in case, make sure we get non-zero freq for below calculation */ + if (!hfperFreq) + { + hfperFreq = 1; + } + } + + /* Determine number of HFPERCLK cycle >= 10us */ + if (4 * 1000000 / hfperFreq > 10) + { + return acmpWarmTime4; + } + else if (8 * 1000000 / hfperFreq > 10) + { + return acmpWarmTime8; + } + else if (16 * 1000000 / hfperFreq > 10) + { + return acmpWarmTime16; + } + else if (32 * 1000000 / hfperFreq > 10) + { + return acmpWarmTime32; + } + else if (64 * 1000000 / hfperFreq > 10) + { + return acmpWarmTime64; + } + else if (128 * 1000000 / hfperFreq > 10) + { + return acmpWarmTime128; + } + else if (256 * 1000000 / hfperFreq > 10) + { + return acmpWarmTime256; + } + else if (512 * 1000000 / hfperFreq > 10) + { + return acmpWarmTime512; + } } #endif diff --git a/bsp/efm32/drv_acmp.h b/bsp/efm32/drv_acmp.h index 50b4738afc..fd7f858669 100644 --- a/bsp/efm32/drv_acmp.h +++ b/bsp/efm32/drv_acmp.h @@ -23,24 +23,24 @@ /* Exported types ------------------------------------------------------------*/ struct efm32_acmp_device_t { - ACMP_TypeDef *acmp_device; - efm32_irq_hook_t hook; + ACMP_TypeDef *acmp_device; + efm32_irq_hook_t hook; }; struct efm32_acmp_output_t { - rt_uint32_t location; - rt_bool_t enable; - rt_bool_t invert; + rt_uint32_t location; + rt_bool_t enable; + rt_bool_t invert; }; struct efm32_acmp_control_t { - ACMP_Init_TypeDef *init; - ACMP_Channel_TypeDef posInput; - ACMP_Channel_TypeDef negInput; - struct efm32_acmp_output_t *output; - efm32_irq_hook_t hook; + ACMP_Init_TypeDef *init; + ACMP_Channel_TypeDef posInput; + ACMP_Channel_TypeDef negInput; + struct efm32_acmp_output_t *output; + efm32_irq_hook_t hook; }; /* Exported constants --------------------------------------------------------*/ diff --git a/bsp/efm32/drv_adc.c b/bsp/efm32/drv_adc.c index e1eeafb36e..2a072507e0 100644 --- a/bsp/efm32/drv_adc.c +++ b/bsp/efm32/drv_adc.c @@ -1,8 +1,8 @@ /***************************************************************************//** - * @file drv_adc.c - * @brief ADC driver of RT-Thread RTOS for EFM32 + * @file drv_adc.c + * @brief ADC driver of RT-Thread RTOS for EFM32 * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -10,9 +10,9 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes - * 2011-02-21 onelife Initial creation for EFM32 - * 2011-07-14 onelife Add multiple channels support for scan mode + * Date Author Notes + * 2011-02-21 onelife Initial creation for EFM32 + * 2011-07-14 onelife Add multiple channels support for scan mode ******************************************************************************/ /***************************************************************************//** @@ -29,7 +29,7 @@ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ #ifdef RT_ADC_DEBUG -#define adc_debug(format,args...) rt_kprintf(format, ##args) +#define adc_debug(format,args...) rt_kprintf(format, ##args) #else #define adc_debug(format,args...) #endif @@ -71,132 +71,132 @@ static rt_uint32_t adcErrataShift = 0; * No need to load the calibration values after the function returns. ******************************************************************************/ rt_uint32_t efm32_adc_calibration( - ADC_TypeDef *adc, - ADC_Ref_TypeDef ref, - ADC_SingleInput_TypeDef input) + ADC_TypeDef *adc, + ADC_Ref_TypeDef ref, + ADC_SingleInput_TypeDef input) { - rt_uint32_t cal; - rt_int32_t sample; - rt_int8_t high, mid, low, tmp; - ADC_InitSingle_TypeDef singleInit = ADC_INITSINGLE_DEFAULT; - - /* Init for single conversion use, measure diff 0 with selected reference. */ - singleInit.reference = ref; - singleInit.input = adcSingleInpDiff0; - singleInit.acqTime = adcAcqTime32; - singleInit.diff = true; - /* Enable oversampling rate */ - singleInit.resolution = adcResOVS; - ADC_InitSingle(adc, &singleInit); - - /* ADC is now set up for offset calibration */ - /* Offset calibration register is a 7 bit signed 2's complement value. */ - /* Use unsigned indexes for binary search, and convert when calibration */ - /* register is written to. */ - high = 63; - low = -64; - - /* Do binary search for offset calibration*/ - while (low < high) - { - /* Calculate midpoint */ - mid = low + (high - low) / 2; - - /* Midpoint is converted to 2's complement and written to both scan and */ - /* single calibration registers */ - cal = adc->CAL & ~(_ADC_CAL_SINGLEOFFSET_MASK | _ADC_CAL_SCANOFFSET_MASK); - tmp = mid < 0 ? (((mid & 0x3F) ^ 0x3F) | 0x40) + 1 : mid; - cal |= tmp << _ADC_CAL_SINGLEOFFSET_SHIFT; - cal |= tmp << _ADC_CAL_SCANOFFSET_SHIFT; - adc_debug("adc->CAL = %x, cal = %x, tmp = %x\n", adc->CAL, cal, tmp); - adc->CAL = cal; - - /* Do a conversion */ - ADC_Start(adc, adcStartSingle); - - /* Wait while conversion is active */ - while (adc->STATUS & ADC_STATUS_SINGLEACT) ; - - /* Get ADC result */ - sample = ADC_DataSingleGet(adc); - - /* Check result and decide in which part of to repeat search */ - /* Calibration register has negative effect on result */ - if (sample < 0) - { - /* Repeat search in bottom half. */ - high = mid; - } - else if (sample > 0) - { - /* Repeat search in top half. */ - low = mid + 1; - } - else - { - /* Found it, exit while loop */ - break; - } - } - adc_debug("adc->CAL = %x\n", adc->CAL); - - /* Now do gain calibration, only input and diff settings needs to be changed */ - adc->SINGLECTRL &= ~(_ADC_SINGLECTRL_INPUTSEL_MASK | _ADC_SINGLECTRL_DIFF_MASK); - adc->SINGLECTRL |= (input << _ADC_SINGLECTRL_INPUTSEL_SHIFT); - adc->SINGLECTRL |= (false << _ADC_SINGLECTRL_DIFF_SHIFT); - - /* ADC is now set up for gain calibration */ - /* Gain calibration register is a 7 bit unsigned value. */ - high = 127; - low = 0; - - /* Do binary search for gain calibration */ - while (low < high) - { - /* Calculate midpoint and write to calibration register */ - mid = low + (high - low) / 2; - - /* Midpoint is converted to 2's complement */ - cal = adc->CAL & ~(_ADC_CAL_SINGLEGAIN_MASK | _ADC_CAL_SCANGAIN_MASK); - cal |= mid << _ADC_CAL_SINGLEGAIN_SHIFT; - cal |= mid << _ADC_CAL_SCANGAIN_SHIFT; - adc_debug("adc->CAL = %x, cal = %x, mid = %x\n", adc->CAL, cal, mid); - adc->CAL = cal; - - /* Do a conversion */ - ADC_Start(adc, adcStartSingle); - - /* Wait while conversion is active */ - while (adc->STATUS & ADC_STATUS_SINGLEACT) ; - - /* Get ADC result */ - sample = ADC_DataSingleGet(adc); - - /* Check result and decide in which part to repeat search */ - /* Compare with a value atleast one LSB's less than top to avoid overshooting */ - /* Since oversampling is used, the result is 16 bits, but a couple of lsb's */ - /* applies to the 12 bit result value, if 0xffe is the top value in 12 bit, this */ - /* is in turn 0xffe0 in the 16 bit result. */ - /* Calibration register has positive effect on result */ - if (sample > 0xffd0) - { - /* Repeat search in bottom half. */ - high = mid; - } - else if (sample < 0xffd0) - { - /* Repeat search in top half. */ - low = mid + 1; - } - else - { - /* Found it, exit while loop */ - break; - } - } - adc_debug("adc->CAL = %x\n", adc->CAL); - - return adc->CAL; + rt_uint32_t cal; + rt_int32_t sample; + rt_int8_t high, mid, low, tmp; + ADC_InitSingle_TypeDef singleInit = ADC_INITSINGLE_DEFAULT; + + /* Init for single conversion use, measure diff 0 with selected reference. */ + singleInit.reference = ref; + singleInit.input = adcSingleInpDiff0; + singleInit.acqTime = adcAcqTime32; + singleInit.diff = true; + /* Enable oversampling rate */ + singleInit.resolution = adcResOVS; + ADC_InitSingle(adc, &singleInit); + + /* ADC is now set up for offset calibration */ + /* Offset calibration register is a 7 bit signed 2's complement value. */ + /* Use unsigned indexes for binary search, and convert when calibration */ + /* register is written to. */ + high = 63; + low = -64; + + /* Do binary search for offset calibration*/ + while (low < high) + { + /* Calculate midpoint */ + mid = low + (high - low) / 2; + + /* Midpoint is converted to 2's complement and written to both scan and */ + /* single calibration registers */ + cal = adc->CAL & ~(_ADC_CAL_SINGLEOFFSET_MASK | _ADC_CAL_SCANOFFSET_MASK); + tmp = mid < 0 ? (((mid & 0x3F) ^ 0x3F) | 0x40) + 1 : mid; + cal |= tmp << _ADC_CAL_SINGLEOFFSET_SHIFT; + cal |= tmp << _ADC_CAL_SCANOFFSET_SHIFT; + adc_debug("adc->CAL = %x, cal = %x, tmp = %x\n", adc->CAL, cal, tmp); + adc->CAL = cal; + + /* Do a conversion */ + ADC_Start(adc, adcStartSingle); + + /* Wait while conversion is active */ + while (adc->STATUS & ADC_STATUS_SINGLEACT) ; + + /* Get ADC result */ + sample = ADC_DataSingleGet(adc); + + /* Check result and decide in which part of to repeat search */ + /* Calibration register has negative effect on result */ + if (sample < 0) + { + /* Repeat search in bottom half. */ + high = mid; + } + else if (sample > 0) + { + /* Repeat search in top half. */ + low = mid + 1; + } + else + { + /* Found it, exit while loop */ + break; + } + } + adc_debug("adc->CAL = %x\n", adc->CAL); + + /* Now do gain calibration, only input and diff settings needs to be changed */ + adc->SINGLECTRL &= ~(_ADC_SINGLECTRL_INPUTSEL_MASK | _ADC_SINGLECTRL_DIFF_MASK); + adc->SINGLECTRL |= (input << _ADC_SINGLECTRL_INPUTSEL_SHIFT); + adc->SINGLECTRL |= (false << _ADC_SINGLECTRL_DIFF_SHIFT); + + /* ADC is now set up for gain calibration */ + /* Gain calibration register is a 7 bit unsigned value. */ + high = 127; + low = 0; + + /* Do binary search for gain calibration */ + while (low < high) + { + /* Calculate midpoint and write to calibration register */ + mid = low + (high - low) / 2; + + /* Midpoint is converted to 2's complement */ + cal = adc->CAL & ~(_ADC_CAL_SINGLEGAIN_MASK | _ADC_CAL_SCANGAIN_MASK); + cal |= mid << _ADC_CAL_SINGLEGAIN_SHIFT; + cal |= mid << _ADC_CAL_SCANGAIN_SHIFT; + adc_debug("adc->CAL = %x, cal = %x, mid = %x\n", adc->CAL, cal, mid); + adc->CAL = cal; + + /* Do a conversion */ + ADC_Start(adc, adcStartSingle); + + /* Wait while conversion is active */ + while (adc->STATUS & ADC_STATUS_SINGLEACT) ; + + /* Get ADC result */ + sample = ADC_DataSingleGet(adc); + + /* Check result and decide in which part to repeat search */ + /* Compare with a value atleast one LSB's less than top to avoid overshooting */ + /* Since oversampling is used, the result is 16 bits, but a couple of lsb's */ + /* applies to the 12 bit result value, if 0xffe is the top value in 12 bit, this */ + /* is in turn 0xffe0 in the 16 bit result. */ + /* Calibration register has positive effect on result */ + if (sample > 0xffd0) + { + /* Repeat search in bottom half. */ + high = mid; + } + else if (sample < 0xffd0) + { + /* Repeat search in top half. */ + low = mid + 1; + } + else + { + /* Found it, exit while loop */ + break; + } + } + adc_debug("adc->CAL = %x\n", adc->CAL); + + return adc->CAL; } /***************************************************************************//** @@ -217,52 +217,52 @@ rt_uint32_t efm32_adc_calibration( * DMA channel ******************************************************************************/ void efm32_adc_cfg_dma( - ADC_TypeDef *adc_device, - rt_uint8_t mode, - rt_uint8_t channel) + ADC_TypeDef *adc_device, + rt_uint8_t mode, + rt_uint8_t channel) { - DMA_CfgChannel_TypeDef chnlCfg; - DMA_CfgDescr_TypeDef descrCfg; - - if (channel == (rt_uint8_t)EFM32_NO_DMA) - { - return; - } - - /* Set up DMA channel */ - chnlCfg.highPri = false; - chnlCfg.enableInt = false; - if (adc_device == ADC0) - { - switch (mode & ADC_MASK_MODE) - { - case ADC_MODE_SINGLE: - chnlCfg.select = DMAREQ_ADC0_SINGLE; - break; - - case ADC_MODE_SCAN: - chnlCfg.select = DMAREQ_ADC0_SCAN; - break; - - default: - return; - } - } - else - { - // TODO: Any other channel? - return; - } - chnlCfg.cb = RT_NULL; - DMA_CfgChannel((rt_uint32_t)channel, &chnlCfg); - - /* Setting up DMA channel descriptor */ - descrCfg.dstInc = dmaDataInc4; - descrCfg.srcInc = dmaDataIncNone; - descrCfg.size = dmaDataSize4; - descrCfg.arbRate = dmaArbitrate1; - descrCfg.hprot = 0; - DMA_CfgDescr((rt_uint32_t)channel, true, &descrCfg); + DMA_CfgChannel_TypeDef chnlCfg; + DMA_CfgDescr_TypeDef descrCfg; + + if (channel == (rt_uint8_t)EFM32_NO_DMA) + { + return; + } + + /* Set up DMA channel */ + chnlCfg.highPri = false; + chnlCfg.enableInt = false; + if (adc_device == ADC0) + { + switch (mode & ADC_MASK_MODE) + { + case ADC_MODE_SINGLE: + chnlCfg.select = DMAREQ_ADC0_SINGLE; + break; + + case ADC_MODE_SCAN: + chnlCfg.select = DMAREQ_ADC0_SCAN; + break; + + default: + return; + } + } + else + { + // TODO: Any other channel? + return; + } + chnlCfg.cb = RT_NULL; + DMA_CfgChannel((rt_uint32_t)channel, &chnlCfg); + + /* Setting up DMA channel descriptor */ + descrCfg.dstInc = dmaDataInc4; + descrCfg.srcInc = dmaDataIncNone; + descrCfg.size = dmaDataSize4; + descrCfg.arbRate = dmaArbitrate1; + descrCfg.hprot = 0; + DMA_CfgDescr((rt_uint32_t)channel, true, &descrCfg); } /***************************************************************************//** @@ -289,38 +289,38 @@ void efm32_adc_cfg_dma( * Pointer to ADC results buffer ******************************************************************************/ void efm32_adc_on_dma( - ADC_TypeDef *adc_device, - rt_uint8_t mode, - rt_uint8_t count, - rt_uint8_t channel, - void *buffer) + ADC_TypeDef *adc_device, + rt_uint8_t mode, + rt_uint8_t count, + rt_uint8_t channel, + void *buffer) { - switch (mode & ADC_MASK_MODE) - { - case ADC_MODE_SINGLE: - /* Activate DMA */ - DMA_ActivateBasic( - (rt_uint32_t)channel, - true, - false, - buffer, - (void *)&(adc_device->SINGLEDATA), - count - 1); - break; - - case ADC_MODE_SCAN: - DMA_ActivateBasic( - (rt_uint32_t)channel, - true, - false, - buffer, - (void *)&(adc_device->SCANDATA), - count - 1); - break; - - default: - return; - } + switch (mode & ADC_MASK_MODE) + { + case ADC_MODE_SINGLE: + /* Activate DMA */ + DMA_ActivateBasic( + (rt_uint32_t)channel, + true, + false, + buffer, + (void *)&(adc_device->SINGLEDATA), + count - 1); + break; + + case ADC_MODE_SCAN: + DMA_ActivateBasic( + (rt_uint32_t)channel, + true, + false, + buffer, + (void *)&(adc_device->SCANDATA), + count - 1); + break; + + default: + return; + } } /***************************************************************************//** @@ -339,468 +339,468 @@ void efm32_adc_on_dma( ******************************************************************************/ static rt_err_t rt_adc_init(rt_device_t dev) { - RT_ASSERT(dev != RT_NULL); + RT_ASSERT(dev != RT_NULL); - rt_uint32_t temp; + rt_uint32_t temp; - struct efm32_adc_device_t *adc; + struct efm32_adc_device_t *adc; - adc = (struct efm32_adc_device_t *)(dev->user_data); + adc = (struct efm32_adc_device_t *)(dev->user_data); - temp = efm32_adc_calibration(adc->adc_device, ADC_CALI_REF, ADC_CALI_CH); + temp = efm32_adc_calibration(adc->adc_device, ADC_CALI_REF, ADC_CALI_CH); - adc_debug("adc->CAL = %x\n", temp); - return RT_EOK; + adc_debug("adc->CAL = %x\n", temp); + return RT_EOK; } /***************************************************************************//** * @brief - * Configure ADC device + * Configure ADC device * * @details * * @note * * @param[in] dev - * Pointer to device descriptor + * Pointer to device descriptor * * @param[in] cmd - * ADC control command + * ADC control command * * @param[in] args - * Arguments + * Arguments * * @return - * Error code + * Error code ******************************************************************************/ static rt_err_t rt_adc_control( - rt_device_t dev, - rt_uint8_t cmd, - void *args) + rt_device_t dev, + rt_uint8_t cmd, + void *args) { - RT_ASSERT(dev != RT_NULL); - - struct efm32_adc_device_t *adc; - - adc = (struct efm32_adc_device_t *)(dev->user_data); - - switch (cmd) - { - case RT_DEVICE_CTRL_SUSPEND: - /* Suspend device */ - dev->flag |= RT_DEVICE_FLAG_SUSPENDED; - adc->adc_device->CMD = ADC_CMD_SINGLESTOP | ADC_CMD_SCANSTOP; - break; - - case RT_DEVICE_CTRL_RESUME: - { - /* Resume device */ - struct efm32_adc_result_t *control = \ - (struct efm32_adc_result_t *)args; - - dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; - - switch (control->mode) - { - case ADC_MODE_SINGLE: - if (adc->singleDmaChannel != (rt_uint8_t)EFM32_NO_DMA) - { - efm32_adc_on_dma( - adc->adc_device, - control->mode, - adc->singleCount, - adc->singleDmaChannel, - control->buffer); - } - ADC_Start(adc->adc_device, adcStartSingle); - break; - - case ADC_MODE_SCAN: - if (adc->scanDmaChannel != (rt_uint8_t)EFM32_NO_DMA) - { - efm32_adc_on_dma( - adc->adc_device, - control->mode, - adc->scanCount, - adc->scanDmaChannel, - control->buffer); - } - ADC_Start(adc->adc_device, adcStartScan); - break; - - case ADC_MODE_TAILGATE: - { - void *index = control->buffer; - - if (adc->scanDmaChannel != (rt_uint8_t)EFM32_NO_DMA) - { - efm32_adc_on_dma( - adc->adc_device, - control->mode, - adc->scanCount, - adc->scanDmaChannel, - index); - index += adc->scanCount; - } - if (adc->singleDmaChannel != (rt_uint8_t)EFM32_NO_DMA) - { - efm32_adc_on_dma( - adc->adc_device, - control->mode, - adc->singleCount, - adc->singleDmaChannel, - index); - index += adc->singleCount; - } - ADC_Start(adc->adc_device, adcStartScanAndSingle); - } - - break; - - default: - return -RT_ERROR; - } - } - break; - - case RT_DEVICE_CTRL_ADC_MODE: - { - /* change device setting */ - struct efm32_adc_control_t *control = \ - (struct efm32_adc_control_t *)args; - - switch (control->mode) - { - case ADC_MODE_SINGLE: - ADC_InitSingle(adc->adc_device, control->single.init); - break; - - case ADC_MODE_SCAN: - ADC_InitScan(adc->adc_device, control->scan.init); - break; - - case ADC_MODE_TAILGATE: - ADC_InitSingle(adc->adc_device, control->single.init); - ADC_InitScan(adc->adc_device, control->scan.init); - break; - - default: - return -RT_ERROR; - } - - if (control->mode == ADC_MODE_TAILGATE) - { - adc->mode = ADC_MODE_TAILGATE; - } - else - { - adc->mode &= ~(rt_uint8_t)ADC_MODE_TAILGATE; - adc->mode |= control->mode; - } - if ((control->mode == ADC_MODE_TAILGATE) || \ - (control->mode == ADC_MODE_SINGLE)) - { - if (control->single.init->rep) - { - adc->mode |= ADC_OP_SINGLE_REPEAT; - } - adc->singleCount = control->single.count; - adc->singleDmaChannel = control->single.dmaChannel; - efm32_adc_cfg_dma(adc->adc_device, control->mode, adc->singleDmaChannel); - } - if ((control->mode == ADC_MODE_TAILGATE) || \ - (control->mode == ADC_MODE_SCAN)) - { - if (control->scan.init->rep) - { - adc->mode |= ADC_OP_SCAN_REPEAT; - } - adc->scanCount = control->scan.count; - adc->scanDmaChannel = control->scan.dmaChannel; - efm32_adc_cfg_dma(adc->adc_device, control->mode, adc->scanDmaChannel); - } - } - break; - - case RT_DEVICE_CTRL_ADC_RESULT: - { - struct efm32_adc_result_t *control = \ - (struct efm32_adc_result_t *)args; - - switch (control->mode) - { - case ADC_MODE_SINGLE: - if (adc->singleDmaChannel != (rt_uint8_t)EFM32_NO_DMA) - { - if (adc->mode & ADC_OP_SINGLE_REPEAT) - { - if (!(DMA->IF & (1 << adc->singleDmaChannel))) - { - efm32_adc_on_dma( - adc->adc_device, - control->mode, - adc->singleCount, - adc->singleDmaChannel, - control->buffer); - } - while (!(DMA->IF & (1 << adc->singleDmaChannel))); - } - else - { - while (adc->adc_device->STATUS & ADC_STATUS_SINGLEACT); - } - } - else - { - while (adc->adc_device->STATUS & ADC_STATUS_SINGLEACT); - *((rt_uint32_t *)control->buffer) = \ - ADC_DataSingleGet(adc->adc_device) << adcErrataShift; - } - break; - - case ADC_MODE_SCAN: - if (adc->scanDmaChannel != (rt_uint8_t)EFM32_NO_DMA) - { - if (adc->mode & ADC_OP_SCAN_REPEAT) - { - if (!(DMA->IF & (1 << adc->scanDmaChannel))) - { - efm32_adc_on_dma( - adc->adc_device, - control->mode, - adc->scanCount, - adc->scanDmaChannel, - control->buffer); - } - while (!(DMA->IF & (1 << adc->scanDmaChannel))); - } - else - { - while (adc->adc_device->STATUS & ADC_STATUS_SCANACT); - } - } - else - { - while (adc->adc_device->STATUS & ADC_STATUS_SCANACT); - *((rt_uint32_t *)control->buffer) = \ - ADC_DataScanGet(adc->adc_device) << adcErrataShift; - } - break; - - case ADC_MODE_TAILGATE: - { - void *index = control->buffer; - - if ((adc->scanDmaChannel != (rt_uint8_t)EFM32_NO_DMA) && \ - !(adc->mode & ADC_OP_SCAN_REPEAT)) - { - index += adc->scanCount; - } - if ((adc->singleDmaChannel != (rt_uint8_t)EFM32_NO_DMA) && \ - !(adc->mode & ADC_OP_SINGLE_REPEAT)) - { - index += adc->singleCount; - } - - if (adc->scanDmaChannel != (rt_uint8_t)EFM32_NO_DMA) - { - if (adc->mode & ADC_OP_SCAN_REPEAT) - { - if (!(DMA->IF & (1 << adc->scanDmaChannel))) - { - efm32_adc_on_dma( - adc->adc_device, - control->mode, - adc->scanCount, - adc->scanDmaChannel, - index); - index += adc->scanCount; - } - while (!(DMA->IF & (1 << adc->scanDmaChannel))); - } - else - { - while (adc->adc_device->STATUS & ADC_STATUS_SCANACT); - } - } - else - { - while (adc->adc_device->STATUS & ADC_STATUS_SCANACT); - *(rt_uint32_t *)(index++) = \ - ADC_DataScanGet(adc->adc_device) << adcErrataShift; - } - if (adc->singleDmaChannel != (rt_uint8_t)EFM32_NO_DMA) - { - if (adc->mode & ADC_OP_SINGLE_REPEAT) - { - if (!(DMA->IF & (1 << adc->singleDmaChannel))) - { - efm32_adc_on_dma( - adc->adc_device, - control->mode, - adc->singleCount, - adc->singleDmaChannel, - index); - index += adc->singleCount; - } - while (!(DMA->IF & (1 << adc->singleDmaChannel))); - } - else - { - while (adc->adc_device->STATUS & ADC_STATUS_SINGLEACT); - } - } - else - { - while (adc->adc_device->STATUS & ADC_STATUS_SINGLEACT); - *(rt_uint32_t *)(index++) = \ - ADC_DataSingleGet(adc->adc_device) << adcErrataShift; - } - } - break; - - default: - return -RT_ERROR; - } - } - break; - - default: - return -RT_ERROR; - } - - return RT_EOK; + RT_ASSERT(dev != RT_NULL); + + struct efm32_adc_device_t *adc; + + adc = (struct efm32_adc_device_t *)(dev->user_data); + + switch (cmd) + { + case RT_DEVICE_CTRL_SUSPEND: + /* Suspend device */ + dev->flag |= RT_DEVICE_FLAG_SUSPENDED; + adc->adc_device->CMD = ADC_CMD_SINGLESTOP | ADC_CMD_SCANSTOP; + break; + + case RT_DEVICE_CTRL_RESUME: + { + /* Resume device */ + struct efm32_adc_result_t *control = \ + (struct efm32_adc_result_t *)args; + + dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; + + switch (control->mode) + { + case ADC_MODE_SINGLE: + if (adc->singleDmaChannel != (rt_uint8_t)EFM32_NO_DMA) + { + efm32_adc_on_dma( + adc->adc_device, + control->mode, + adc->singleCount, + adc->singleDmaChannel, + control->buffer); + } + ADC_Start(adc->adc_device, adcStartSingle); + break; + + case ADC_MODE_SCAN: + if (adc->scanDmaChannel != (rt_uint8_t)EFM32_NO_DMA) + { + efm32_adc_on_dma( + adc->adc_device, + control->mode, + adc->scanCount, + adc->scanDmaChannel, + control->buffer); + } + ADC_Start(adc->adc_device, adcStartScan); + break; + + case ADC_MODE_TAILGATE: + { + void *index = control->buffer; + + if (adc->scanDmaChannel != (rt_uint8_t)EFM32_NO_DMA) + { + efm32_adc_on_dma( + adc->adc_device, + control->mode, + adc->scanCount, + adc->scanDmaChannel, + index); + index += adc->scanCount; + } + if (adc->singleDmaChannel != (rt_uint8_t)EFM32_NO_DMA) + { + efm32_adc_on_dma( + adc->adc_device, + control->mode, + adc->singleCount, + adc->singleDmaChannel, + index); + index += adc->singleCount; + } + ADC_Start(adc->adc_device, adcStartScanAndSingle); + } + + break; + + default: + return -RT_ERROR; + } + } + break; + + case RT_DEVICE_CTRL_ADC_MODE: + { + /* change device setting */ + struct efm32_adc_control_t *control = \ + (struct efm32_adc_control_t *)args; + + switch (control->mode) + { + case ADC_MODE_SINGLE: + ADC_InitSingle(adc->adc_device, control->single.init); + break; + + case ADC_MODE_SCAN: + ADC_InitScan(adc->adc_device, control->scan.init); + break; + + case ADC_MODE_TAILGATE: + ADC_InitSingle(adc->adc_device, control->single.init); + ADC_InitScan(adc->adc_device, control->scan.init); + break; + + default: + return -RT_ERROR; + } + + if (control->mode == ADC_MODE_TAILGATE) + { + adc->mode = ADC_MODE_TAILGATE; + } + else + { + adc->mode &= ~(rt_uint8_t)ADC_MODE_TAILGATE; + adc->mode |= control->mode; + } + if ((control->mode == ADC_MODE_TAILGATE) || \ + (control->mode == ADC_MODE_SINGLE)) + { + if (control->single.init->rep) + { + adc->mode |= ADC_OP_SINGLE_REPEAT; + } + adc->singleCount = control->single.count; + adc->singleDmaChannel = control->single.dmaChannel; + efm32_adc_cfg_dma(adc->adc_device, control->mode, adc->singleDmaChannel); + } + if ((control->mode == ADC_MODE_TAILGATE) || \ + (control->mode == ADC_MODE_SCAN)) + { + if (control->scan.init->rep) + { + adc->mode |= ADC_OP_SCAN_REPEAT; + } + adc->scanCount = control->scan.count; + adc->scanDmaChannel = control->scan.dmaChannel; + efm32_adc_cfg_dma(adc->adc_device, control->mode, adc->scanDmaChannel); + } + } + break; + + case RT_DEVICE_CTRL_ADC_RESULT: + { + struct efm32_adc_result_t *control = \ + (struct efm32_adc_result_t *)args; + + switch (control->mode) + { + case ADC_MODE_SINGLE: + if (adc->singleDmaChannel != (rt_uint8_t)EFM32_NO_DMA) + { + if (adc->mode & ADC_OP_SINGLE_REPEAT) + { + if (!(DMA->IF & (1 << adc->singleDmaChannel))) + { + efm32_adc_on_dma( + adc->adc_device, + control->mode, + adc->singleCount, + adc->singleDmaChannel, + control->buffer); + } + while (!(DMA->IF & (1 << adc->singleDmaChannel))); + } + else + { + while (adc->adc_device->STATUS & ADC_STATUS_SINGLEACT); + } + } + else + { + while (adc->adc_device->STATUS & ADC_STATUS_SINGLEACT); + *((rt_uint32_t *)control->buffer) = \ + ADC_DataSingleGet(adc->adc_device) << adcErrataShift; + } + break; + + case ADC_MODE_SCAN: + if (adc->scanDmaChannel != (rt_uint8_t)EFM32_NO_DMA) + { + if (adc->mode & ADC_OP_SCAN_REPEAT) + { + if (!(DMA->IF & (1 << adc->scanDmaChannel))) + { + efm32_adc_on_dma( + adc->adc_device, + control->mode, + adc->scanCount, + adc->scanDmaChannel, + control->buffer); + } + while (!(DMA->IF & (1 << adc->scanDmaChannel))); + } + else + { + while (adc->adc_device->STATUS & ADC_STATUS_SCANACT); + } + } + else + { + while (adc->adc_device->STATUS & ADC_STATUS_SCANACT); + *((rt_uint32_t *)control->buffer) = \ + ADC_DataScanGet(adc->adc_device) << adcErrataShift; + } + break; + + case ADC_MODE_TAILGATE: + { + void *index = control->buffer; + + if ((adc->scanDmaChannel != (rt_uint8_t)EFM32_NO_DMA) && \ + !(adc->mode & ADC_OP_SCAN_REPEAT)) + { + index += adc->scanCount; + } + if ((adc->singleDmaChannel != (rt_uint8_t)EFM32_NO_DMA) && \ + !(adc->mode & ADC_OP_SINGLE_REPEAT)) + { + index += adc->singleCount; + } + + if (adc->scanDmaChannel != (rt_uint8_t)EFM32_NO_DMA) + { + if (adc->mode & ADC_OP_SCAN_REPEAT) + { + if (!(DMA->IF & (1 << adc->scanDmaChannel))) + { + efm32_adc_on_dma( + adc->adc_device, + control->mode, + adc->scanCount, + adc->scanDmaChannel, + index); + index += adc->scanCount; + } + while (!(DMA->IF & (1 << adc->scanDmaChannel))); + } + else + { + while (adc->adc_device->STATUS & ADC_STATUS_SCANACT); + } + } + else + { + while (adc->adc_device->STATUS & ADC_STATUS_SCANACT); + *(rt_uint32_t *)(index++) = \ + ADC_DataScanGet(adc->adc_device) << adcErrataShift; + } + if (adc->singleDmaChannel != (rt_uint8_t)EFM32_NO_DMA) + { + if (adc->mode & ADC_OP_SINGLE_REPEAT) + { + if (!(DMA->IF & (1 << adc->singleDmaChannel))) + { + efm32_adc_on_dma( + adc->adc_device, + control->mode, + adc->singleCount, + adc->singleDmaChannel, + index); + index += adc->singleCount; + } + while (!(DMA->IF & (1 << adc->singleDmaChannel))); + } + else + { + while (adc->adc_device->STATUS & ADC_STATUS_SINGLEACT); + } + } + else + { + while (adc->adc_device->STATUS & ADC_STATUS_SINGLEACT); + *(rt_uint32_t *)(index++) = \ + ADC_DataSingleGet(adc->adc_device) << adcErrataShift; + } + } + break; + + default: + return -RT_ERROR; + } + } + break; + + default: + return -RT_ERROR; + } + + return RT_EOK; } /***************************************************************************//** * @brief - * Register ADC device + * Register ADC device * * @details * * @note * * @param[in] device - * Pointer to device descriptor + * Pointer to device descriptor * * @param[in] name - * Device name + * Device name * * @param[in] flag - * Configuration flags + * Configuration flags * * @param[in] adc - * Pointer to ADC device descriptor + * Pointer to ADC device descriptor * * @return - * Error code + * Error code ******************************************************************************/ rt_err_t rt_hw_adc_register( - rt_device_t device, - const char *name, - rt_uint32_t flag, - struct efm32_adc_device_t *adc) + rt_device_t device, + const char *name, + rt_uint32_t flag, + struct efm32_adc_device_t *adc) { - RT_ASSERT(device != RT_NULL); - - device->type = RT_Device_Class_Char; /* fixme: should be adc type */ - device->rx_indicate = RT_NULL; - device->tx_complete = RT_NULL; - device->init = rt_adc_init; - device->open = RT_NULL; - device->close = RT_NULL; - device->read = RT_NULL; - device->write = RT_NULL; - device->control = rt_adc_control; - device->user_data = adc; - - /* register a character device */ - return rt_device_register(device, name, flag); + RT_ASSERT(device != RT_NULL); + + device->type = RT_Device_Class_Char; /* fixme: should be adc type */ + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->init = rt_adc_init; + device->open = RT_NULL; + device->close = RT_NULL; + device->read = RT_NULL; + device->write = RT_NULL; + device->control = rt_adc_control; + device->user_data = adc; + + /* register a character device */ + return rt_device_register(device, name, flag); } /***************************************************************************//** * @brief - * Initialize the specified ADC unit + * Initialize the specified ADC unit * * @details * * @note * * @param[in] device - * Pointer to device descriptor + * Pointer to device descriptor * * @param[in] unitNumber - * Unit number + * Unit number * * @return - * Pointer to ADC device + * Pointer to ADC device ******************************************************************************/ static struct efm32_adc_device_t *rt_hw_adc_unit_init( - rt_device_t device, - rt_uint8_t unitNumber) + rt_device_t device, + rt_uint8_t unitNumber) { - struct efm32_adc_device_t *adc; - CMU_Clock_TypeDef adcClock; - ADC_Init_TypeDef init = ADC_INIT_DEFAULT; - - do - { - /* Allocate device and set default value */ - adc = rt_malloc(sizeof(struct efm32_adc_device_t)); - if (adc == RT_NULL) - { - adc_debug("no memory for ADC%d driver\n", unitNumber); - break; - } - adc->mode = 0; - adc->singleCount = 0; - adc->singleDmaChannel = (rt_uint8_t)EFM32_NO_DMA; - adc->scanCount = 0; - adc->scanDmaChannel = (rt_uint8_t)EFM32_NO_DMA; - - /* Initialization */ - if (unitNumber >= ADC_COUNT) - { - break; - } - switch (unitNumber) - { - case 0: - adc->adc_device = ADC0; - adcClock = (CMU_Clock_TypeDef)cmuClock_ADC0; - break; - - default: - break; - } - - /* Enable ADC clock */ - CMU_ClockEnable(adcClock, true); - - /* Reset */ - ADC_Reset(adc->adc_device); - - /* Configure ADC */ - // TODO: Fixed oversampling rate? - init.ovsRateSel = adcOvsRateSel4096; - init.timebase = ADC_TimebaseCalc(0); - init.prescale = ADC_PrescaleCalc(ADC_CONVERT_FREQUENCY, 0); - ADC_Init(adc->adc_device, &init); - - return adc; - } while(0); - - if (adc) - { - rt_free(adc); - } - rt_kprintf("ADC: Init failed!\n"); - return RT_NULL; + struct efm32_adc_device_t *adc; + CMU_Clock_TypeDef adcClock; + ADC_Init_TypeDef init = ADC_INIT_DEFAULT; + + do + { + /* Allocate device and set default value */ + adc = rt_malloc(sizeof(struct efm32_adc_device_t)); + if (adc == RT_NULL) + { + adc_debug("no memory for ADC%d driver\n", unitNumber); + break; + } + adc->mode = 0; + adc->singleCount = 0; + adc->singleDmaChannel = (rt_uint8_t)EFM32_NO_DMA; + adc->scanCount = 0; + adc->scanDmaChannel = (rt_uint8_t)EFM32_NO_DMA; + + /* Initialization */ + if (unitNumber >= ADC_COUNT) + { + break; + } + switch (unitNumber) + { + case 0: + adc->adc_device = ADC0; + adcClock = (CMU_Clock_TypeDef)cmuClock_ADC0; + break; + + default: + break; + } + + /* Enable ADC clock */ + CMU_ClockEnable(adcClock, true); + + /* Reset */ + ADC_Reset(adc->adc_device); + + /* Configure ADC */ + // TODO: Fixed oversampling rate? + init.ovsRateSel = adcOvsRateSel4096; + init.timebase = ADC_TimebaseCalc(0); + init.prescale = ADC_PrescaleCalc(ADC_CONVERT_FREQUENCY, 0); + ADC_Init(adc->adc_device, &init); + + return adc; + } while(0); + + if (adc) + { + rt_free(adc); + } + rt_kprintf("ADC: Init failed!\n"); + return RT_NULL; } /***************************************************************************//** * @brief - * Initialize all ADC module related hardware and register ADC device to kernel + * Initialize all ADC module related hardware and register ADC device to kernel * * @details * @@ -809,23 +809,23 @@ static struct efm32_adc_device_t *rt_hw_adc_unit_init( ******************************************************************************/ void rt_hw_adc_init(void) { - SYSTEM_ChipRevision_TypeDef chipRev; - struct efm32_adc_device_t *adc; + SYSTEM_ChipRevision_TypeDef chipRev; + struct efm32_adc_device_t *adc; #ifdef RT_USING_ADC0 - if ((adc = rt_hw_adc_unit_init(&adc0_device, 0)) != RT_NULL) - { - rt_hw_adc_register(&adc0_device, RT_ADC0_NAME, EFM32_NO_DATA, adc); - } + if ((adc = rt_hw_adc_unit_init(&adc0_device, 0)) != RT_NULL) + { + rt_hw_adc_register(&adc0_device, RT_ADC0_NAME, EFM32_NO_DATA, adc); + } #endif - /* ADC errata for rev B when using VDD as reference, need to multiply */ - /* result by 2 */ - SYSTEM_ChipRevisionGet(&chipRev); - if ((chipRev.major == 0x01) && (chipRev.minor == 0x01)) - { - adcErrataShift = 1; - } + /* ADC errata for rev B when using VDD as reference, need to multiply */ + /* result by 2 */ + SYSTEM_ChipRevisionGet(&chipRev); + if ((chipRev.major == 0x01) && (chipRev.minor == 0x01)) + { + adcErrataShift = 1; + } } #endif diff --git a/bsp/efm32/drv_adc.h b/bsp/efm32/drv_adc.h index b3b81d94e1..f15d074835 100644 --- a/bsp/efm32/drv_adc.h +++ b/bsp/efm32/drv_adc.h @@ -1,8 +1,8 @@ /***************************************************************************//** - * @file drv_adc.h - * @brief ADC driver of RT-Thread RTOS for EFM32 + * @file drv_adc.h + * @brief ADC driver of RT-Thread RTOS for EFM32 * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -10,9 +10,9 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes - * 2011-02-21 onelife Initial creation for EFM32 - * 2011-07-14 onelife Add multiple channels support for scan mode + * Date Author Notes + * 2011-02-21 onelife Initial creation for EFM32 + * 2011-07-14 onelife Add multiple channels support for scan mode ******************************************************************************/ #ifndef __DRV_ADC_H__ #define __DRV_ADC_H__ @@ -21,50 +21,50 @@ /* Exported types ------------------------------------------------------------*/ struct efm32_adc_device_t { - ADC_TypeDef *adc_device; - rt_uint8_t mode; - rt_uint8_t singleCount; - rt_uint8_t singleDmaChannel; - rt_uint8_t scanCount; - rt_uint8_t scanDmaChannel; + ADC_TypeDef *adc_device; + rt_uint8_t mode; + rt_uint8_t singleCount; + rt_uint8_t singleDmaChannel; + rt_uint8_t scanCount; + rt_uint8_t scanDmaChannel; }; struct efm32_adc_control_single_t { - rt_uint8_t count; - rt_uint8_t dmaChannel; - ADC_InitSingle_TypeDef *init; + rt_uint8_t count; + rt_uint8_t dmaChannel; + ADC_InitSingle_TypeDef *init; }; struct efm32_adc_control_scan_t { - rt_uint8_t count; - rt_uint8_t dmaChannel; - ADC_InitScan_TypeDef *init; + rt_uint8_t count; + rt_uint8_t dmaChannel; + ADC_InitScan_TypeDef *init; }; struct efm32_adc_control_t { - rt_uint8_t mode; - struct efm32_adc_control_scan_t scan; - struct efm32_adc_control_single_t single; + rt_uint8_t mode; + struct efm32_adc_control_scan_t scan; + struct efm32_adc_control_single_t single; }; struct efm32_adc_result_t { - rt_uint8_t mode; - void *buffer; + rt_uint8_t mode; + void *buffer; }; /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ -#define ADC_MODE_SINGLE (0x01) -#define ADC_MODE_SCAN (0x02) -#define ADC_MODE_TAILGATE (0x04) -#define ADC_OP_SINGLE_REPEAT (0x10) -#define ADC_OP_SCAN_REPEAT (0x20) -#define ADC_MASK_MODE (0x0f) -#define ADC_MASK_OP (0xf0) +#define ADC_MODE_SINGLE (0x01) +#define ADC_MODE_SCAN (0x02) +#define ADC_MODE_TAILGATE (0x04) +#define ADC_OP_SINGLE_REPEAT (0x10) +#define ADC_OP_SCAN_REPEAT (0x20) +#define ADC_MASK_MODE (0x0f) +#define ADC_MASK_OP (0xf0) /* Exported functions ------------------------------------------------------- */ void rt_hw_adc_init(void); diff --git a/bsp/efm32/drv_emu.c b/bsp/efm32/drv_emu.c index 9a5fc8e97e..18eeca1a43 100644 --- a/bsp/efm32/drv_emu.c +++ b/bsp/efm32/drv_emu.c @@ -1,8 +1,8 @@ /***************************************************************************//** - * @file drv_emu.c - * @brief EMU driver of RT-Thread RTOS for EFM32 + * @file drv_emu.c + * @brief EMU driver of RT-Thread RTOS for EFM32 * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -10,8 +10,8 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes - * 2012-02-21 onelife Initial creation for EFM32 + * Date Author Notes + * 2012-02-21 onelife Initial creation for EFM32 ******************************************************************************/ /***************************************************************************//** @@ -27,7 +27,7 @@ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ #ifdef EFM32_EMU_DEBUG -#define emu_debug(format,args...) rt_kprintf(format, ##args) +#define emu_debug(format,args...) rt_kprintf(format, ##args) #else #define emu_debug(format,args...) #endif @@ -176,7 +176,7 @@ void emu_em4_enable(void) /***************************************************************************//** * @brief - * Initialize EMU module related hardware + * Initialize EMU module related hardware * * @details * @@ -213,22 +213,22 @@ void efm32_emu_init(void) break; } - /* init thread */ + /* init thread */ if (rt_thread_init( &emu_task.thread, "EMU", - emu_task_main_loop, (void *)&emu_task, + emu_task_main_loop, (void *)&emu_task, (void *)&emu_task.stack, sizeof(emu_task.stack), - RT_THREAD_PRIORITY_MAX - 2, RT_TICK_PER_SECOND) != RT_EOK) + RT_THREAD_PRIORITY_MAX - 2, RT_TICK_PER_SECOND) != RT_EOK) { break; } - /* startup */ - if (rt_thread_startup(&emu_task.thread) != RT_EOK) - { + /* startup */ + if (rt_thread_startup(&emu_task.thread) != RT_EOK) + { break; - } + } } while (0); rt_kprintf("EMU err: init failed!\n"); diff --git a/bsp/efm32/drv_emu.h b/bsp/efm32/drv_emu.h index 3e491665ba..df46264295 100644 --- a/bsp/efm32/drv_emu.h +++ b/bsp/efm32/drv_emu.h @@ -1,8 +1,8 @@ /***************************************************************************//** - * @file drv_emu.h - * @brief EMU driver of RT-Thread RTOS for EFM32 + * @file drv_emu.h + * @brief EMU driver of RT-Thread RTOS for EFM32 * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -10,9 +10,9 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes - * 2011-02-21 onelife Initial creation for EFM32 - * 2011-07-14 onelife Add multiple channels support for scan mode + * Date Author Notes + * 2011-02-21 onelife Initial creation for EFM32 + * 2011-07-14 onelife Add multiple channels support for scan mode ******************************************************************************/ #ifndef __DRV_EMU_H__ #define __DRV_EMU_H__ diff --git a/bsp/efm32/drv_ethernet.c b/bsp/efm32/drv_ethernet.c index e6bc25bbcc..db99de583a 100644 --- a/bsp/efm32/drv_ethernet.c +++ b/bsp/efm32/drv_ethernet.c @@ -1,11 +1,11 @@ /***************************************************************************//** - * @file drv_ethernet.c - * @brief Ethernet driver (SPI mode) of RT-Thread RTOS for using EFM32 USART + * @file drv_ethernet.c + * @brief Ethernet driver (SPI mode) of RT-Thread RTOS for using EFM32 USART * module - * This driver is tested by using the Microchip ENC28J60 stand-alone Ethernet + * This driver is tested by using the Microchip ENC28J60 stand-alone Ethernet * controller with SPI interface. * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -13,11 +13,11 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes - * 2011-06-22 onelife Initial creation for using EFM32 USART module - * 2011-07-25 onelife Add lock (semaphore) to prevent simultaneously + * Date Author Notes + * 2011-06-22 onelife Initial creation for using EFM32 USART module + * 2011-07-25 onelife Add lock (semaphore) to prevent simultaneously * access - * 2011-07-28 onelife Add get_ip() and update_ip() utilities + * 2011-07-28 onelife Add get_ip() and update_ip() utilities ******************************************************************************/ /***************************************************************************//** @@ -38,21 +38,21 @@ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ #ifdef EFM32_ETHERNET_DEBUG -#define eth_debug(format,args...) rt_kprintf(format, ##args) +#define eth_debug(format,args...) rt_kprintf(format, ##args) #else #define eth_debug(format,args...) #endif /* Private constants ---------------------------------------------------------*/ -static const rt_uint8_t eth_addr[ETH_ADDR_LEN] = ETH_ADDR_DEFAULT; +static const rt_uint8_t eth_addr[ETH_ADDR_LEN] = ETH_ADDR_DEFAULT; /* Private variables ---------------------------------------------------------*/ -static struct eth_device eth_dev; -static struct rt_semaphore ethLock; -static rt_uint8_t ethBank; -static rt_uint16_t ethNxtPkt; -static rt_device_t spi = RT_NULL; -static rt_bool_t ethAutoCs = true; +static struct eth_device eth_dev; +static struct rt_semaphore ethLock; +static rt_uint8_t ethBank; +static rt_uint16_t ethNxtPkt; +static rt_device_t spi = RT_NULL; +static rt_bool_t ethAutoCs = true; /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ @@ -69,17 +69,17 @@ static rt_bool_t ethAutoCs = true; ******************************************************************************/ static void efm_eth_cs(rt_uint8_t enable) { - if (!ethAutoCs) - { - if (enable) - { - GPIO_PinOutClear(ETH_CS_PORT, ETH_CS_PIN); - } - else - { - GPIO_PinOutSet(ETH_CS_PORT, ETH_CS_PIN); - } - } + if (!ethAutoCs) + { + if (enable) + { + GPIO_PinOutClear(ETH_CS_PORT, ETH_CS_PIN); + } + else + { + GPIO_PinOutSet(ETH_CS_PORT, ETH_CS_PIN); + } + } } /***************************************************************************//** @@ -103,93 +103,93 @@ static void efm_eth_cs(rt_uint8_t enable) * Error code ******************************************************************************/ static rt_err_t efm_eth_cmd( - rt_uint8_t cmd, - rt_uint8_t addr, - rt_uint8_t *data) + rt_uint8_t cmd, + rt_uint8_t addr, + rt_uint8_t *data) { - RT_ASSERT(spi != RT_NULL); - - rt_uint8_t buf_ins[6], buf_res[2]; - rt_uint8_t len_ins, len_res; - - len_ins = 0; - do - { - /* Build instruction buffer */ - /* Check if need to read back */ - if (cmd == ENC28J60_READ_CTRL_REG) - { - buf_ins[len_ins++] = 1; /* Instruction length */ - } - /* Byte 0: Check if no address section */ - if (cmd == ENC28J60_READ_BUF_MEM || cmd == ENC28J60_WRITE_BUF_MEM || \ - cmd == ENC28J60_SOFT_RESET) - { - buf_ins[len_ins++] = cmd; - } - else - { - buf_ins[len_ins++] = cmd | (addr & ADDR_MASK); - } - /* Byte 1: Check if data section is present */ - if (cmd == ENC28J60_WRITE_CTRL_REG || cmd == ENC28J60_BIT_FIELD_SET || \ - cmd == ENC28J60_BIT_FIELD_CLR || cmd == ENC28J60_WRITE_BUF_MEM) - { - buf_ins[len_ins++] = *data; - } - - /* Check if reading */ - if (cmd == ENC28J60_READ_CTRL_REG) - { - *(rt_uint8_t **)(&buf_ins[len_ins]) = buf_res; /* Pointer to RX buffer */ - len_ins += 4; - - /* Check if MAC or MII register */ - if (addr & SPRD_MASK) - { - len_res = 2; - } - else - { - len_res = 1; - } - - /* Send command and get response */ - efm_eth_cs(1); - if (spi->read(spi, ETH_SPI_RX_SKIP, buf_ins, len_res) == 0) - { - break; - } - *data = buf_res[len_res - 1]; -// eth_debug("ETH: read RX %x %x (%d)\n", buf_res[0], buf_res[1], len_res); -// eth_debug("ETH: ** read RX %x %x (%d)\n", -// buf_res[0], buf_res[1], buf_res[2], buf_res[3], buf_res[4], -// buf_res[5], buf_res[6], buf_res[7], buf_res[8], buf_res[9], -// len_res); - } - else - { -// eth_debug("ETH: ** write TX %x %x %x %x %x %x (%d) \n", buf_ins[0], -// buf_ins[1], buf_ins[2], buf_ins[3], buf_ins[4], buf_ins[5], -// len_ins); - /* Send command and get response */ - efm_eth_cs(1); - if (spi->write(spi, EFM32_NO_DATA, buf_ins, len_ins) == 0) - { - break; - } - } - - if (!(cmd == ENC28J60_READ_BUF_MEM || cmd == ENC28J60_WRITE_BUF_MEM)) - { - efm_eth_cs(0); - } - return RT_EOK; - } while(0); - - eth_debug("ETH: Send command failed!\n"); - efm_eth_cs(0); - return -RT_ERROR; + RT_ASSERT(spi != RT_NULL); + + rt_uint8_t buf_ins[6], buf_res[2]; + rt_uint8_t len_ins, len_res; + + len_ins = 0; + do + { + /* Build instruction buffer */ + /* Check if need to read back */ + if (cmd == ENC28J60_READ_CTRL_REG) + { + buf_ins[len_ins++] = 1; /* Instruction length */ + } + /* Byte 0: Check if no address section */ + if (cmd == ENC28J60_READ_BUF_MEM || cmd == ENC28J60_WRITE_BUF_MEM || \ + cmd == ENC28J60_SOFT_RESET) + { + buf_ins[len_ins++] = cmd; + } + else + { + buf_ins[len_ins++] = cmd | (addr & ADDR_MASK); + } + /* Byte 1: Check if data section is present */ + if (cmd == ENC28J60_WRITE_CTRL_REG || cmd == ENC28J60_BIT_FIELD_SET || \ + cmd == ENC28J60_BIT_FIELD_CLR || cmd == ENC28J60_WRITE_BUF_MEM) + { + buf_ins[len_ins++] = *data; + } + + /* Check if reading */ + if (cmd == ENC28J60_READ_CTRL_REG) + { + *(rt_uint8_t **)(&buf_ins[len_ins]) = buf_res; /* Pointer to RX buffer */ + len_ins += 4; + + /* Check if MAC or MII register */ + if (addr & SPRD_MASK) + { + len_res = 2; + } + else + { + len_res = 1; + } + + /* Send command and get response */ + efm_eth_cs(1); + if (spi->read(spi, ETH_SPI_RX_SKIP, buf_ins, len_res) == 0) + { + break; + } + *data = buf_res[len_res - 1]; +// eth_debug("ETH: read RX %x %x (%d)\n", buf_res[0], buf_res[1], len_res); +// eth_debug("ETH: ** read RX %x %x (%d)\n", +// buf_res[0], buf_res[1], buf_res[2], buf_res[3], buf_res[4], +// buf_res[5], buf_res[6], buf_res[7], buf_res[8], buf_res[9], +// len_res); + } + else + { +// eth_debug("ETH: ** write TX %x %x %x %x %x %x (%d) \n", buf_ins[0], +// buf_ins[1], buf_ins[2], buf_ins[3], buf_ins[4], buf_ins[5], +// len_ins); + /* Send command and get response */ + efm_eth_cs(1); + if (spi->write(spi, EFM32_NO_DATA, buf_ins, len_ins) == 0) + { + break; + } + } + + if (!(cmd == ENC28J60_READ_BUF_MEM || cmd == ENC28J60_WRITE_BUF_MEM)) + { + efm_eth_cs(0); + } + return RT_EOK; + } while(0); + + eth_debug("ETH: Send command failed!\n"); + efm_eth_cs(0); + return -RT_ERROR; } /***************************************************************************//** @@ -213,37 +213,37 @@ static rt_err_t efm_eth_cmd( * Error code ******************************************************************************/ static rt_err_t efm_eth_sendCmd( - rt_uint8_t cmd, - rt_uint8_t addr, - rt_uint8_t *data) + rt_uint8_t cmd, + rt_uint8_t addr, + rt_uint8_t *data) { - rt_err_t ret; - - eth_debug("ETH: Send command %x (%x %x)\n", cmd, addr, *data); - do - { - /* Change bank */ - if(((addr & BANK_MASK) != ethBank) && ((addr < EIE) || (addr > ECON1))) - { - rt_uint8_t temp; - - if ((ret = efm_eth_cmd(ENC28J60_READ_CTRL_REG, ECON1, &temp)) != RT_EOK) - { - break; - } - temp &= 0xFC; - ethBank = (addr & BANK_MASK); - temp |= ethBank >> BANK_SHIFT; - if ((ret = efm_eth_cmd(ENC28J60_WRITE_CTRL_REG, ECON1, &temp)) != RT_EOK) - { - break; - } - } - /* Send command */ - ret = efm_eth_cmd(cmd, addr, data); - } while(0); - - return ret; + rt_err_t ret; + + eth_debug("ETH: Send command %x (%x %x)\n", cmd, addr, *data); + do + { + /* Change bank */ + if(((addr & BANK_MASK) != ethBank) && ((addr < EIE) || (addr > ECON1))) + { + rt_uint8_t temp; + + if ((ret = efm_eth_cmd(ENC28J60_READ_CTRL_REG, ECON1, &temp)) != RT_EOK) + { + break; + } + temp &= 0xFC; + ethBank = (addr & BANK_MASK); + temp |= ethBank >> BANK_SHIFT; + if ((ret = efm_eth_cmd(ENC28J60_WRITE_CTRL_REG, ECON1, &temp)) != RT_EOK) + { + break; + } + } + /* Send command */ + ret = efm_eth_cmd(cmd, addr, data); + } while(0); + + return ret; } /***************************************************************************//** @@ -262,11 +262,11 @@ static rt_err_t efm_eth_sendCmd( ******************************************************************************/ static rt_uint8_t efm_eth_readReg(rt_uint8_t addr) { - rt_uint8_t data; + rt_uint8_t data; - efm_eth_sendCmd(ENC28J60_READ_CTRL_REG, addr, &data); + efm_eth_sendCmd(ENC28J60_READ_CTRL_REG, addr, &data); - return data; + return data; } /***************************************************************************//** @@ -285,7 +285,7 @@ static rt_uint8_t efm_eth_readReg(rt_uint8_t addr) ******************************************************************************/ static void efm_eth_writeReg(rt_uint8_t addr, rt_uint8_t data) { - efm_eth_sendCmd(ENC28J60_WRITE_CTRL_REG, addr, &data); + efm_eth_sendCmd(ENC28J60_WRITE_CTRL_REG, addr, &data); } /***************************************************************************//** @@ -304,25 +304,25 @@ static void efm_eth_writeReg(rt_uint8_t addr, rt_uint8_t data) ******************************************************************************/ static rt_uint16_t efm_eth_readPhy(rt_uint8_t addr) { - rt_uint16_t ret; + rt_uint16_t ret; - eth_debug("ETH: *** read PHY %x\n", addr); + eth_debug("ETH: *** read PHY %x\n", addr); - /* Set PHY register address */ - efm_eth_writeReg(MIREGADR, addr); + /* Set PHY register address */ + efm_eth_writeReg(MIREGADR, addr); - /* Start read operation */ - efm_eth_writeReg(MICMD, MICMD_MIIRD); - /* Waiting for at least 10.24 uS */ - while(efm_eth_readReg(MISTAT) & MISTAT_BUSY); + /* Start read operation */ + efm_eth_writeReg(MICMD, MICMD_MIIRD); + /* Waiting for at least 10.24 uS */ + while(efm_eth_readReg(MISTAT) & MISTAT_BUSY); - /* Stop read operation */ - efm_eth_writeReg(MICMD, 0x00); + /* Stop read operation */ + efm_eth_writeReg(MICMD, 0x00); - /* Get the result */ - ret = (rt_uint16_t)efm_eth_readReg(MIRDL); - ret |= (rt_uint16_t)efm_eth_readReg(MIRDH) << 8; - return ret; + /* Get the result */ + ret = (rt_uint16_t)efm_eth_readReg(MIRDL); + ret |= (rt_uint16_t)efm_eth_readReg(MIRDH) << 8; + return ret; } /***************************************************************************//** @@ -341,82 +341,82 @@ static rt_uint16_t efm_eth_readPhy(rt_uint8_t addr) ******************************************************************************/ static void efm_eth_writePhy(rt_uint8_t addr, rt_uint16_t data) { - eth_debug("ETH: *** write PHY %x (%x)\n", addr, data); + eth_debug("ETH: *** write PHY %x (%x)\n", addr, data); - /* Set PHY register address */ - efm_eth_writeReg(MIREGADR, addr); + /* Set PHY register address */ + efm_eth_writeReg(MIREGADR, addr); - /* Set data */ - efm_eth_writeReg(MIWRL, data); - efm_eth_writeReg(MIWRH, data >> 8); - /* Waiting for at least 10.24 uS */ - while(efm_eth_readReg(MISTAT) & MISTAT_BUSY); + /* Set data */ + efm_eth_writeReg(MIWRL, data); + efm_eth_writeReg(MIWRH, data >> 8); + /* Waiting for at least 10.24 uS */ + while(efm_eth_readReg(MISTAT) & MISTAT_BUSY); } /***************************************************************************//** * @brief - * Interrupt handler of Ethernet device + * Interrupt handler of Ethernet device * * @details * * @note * * @param[in] dev - * Pointer to device descriptor + * Pointer to device descriptor ******************************************************************************/ void efm_eth_isr(rt_device_t dev) { - rt_uint8_t reg_eir, data; - volatile rt_uint8_t cnt; - - /* Disable RX and other interrutps */ - data = EIE_PKTIE | EIE_INTIE; - efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIE, &data); - - /* Get interrupt flag */ - efm_eth_sendCmd(ENC28J60_READ_CTRL_REG, EIR, ®_eir); - - data = 0; - /* DMA completed */ - if (reg_eir & EIR_DMAIF) - { - data |= (rt_uint8_t)EIR_DMAIF; - } - /* Link Changed */ - if (reg_eir & EIR_LINKIF) - { - /* Read PHIR to clear the flag */ - efm_eth_readPhy(PHIR); - } - /* TX done */ - if (reg_eir & EIR_TXIF) - { - data |= (rt_uint8_t)EIR_TXIF; - } - /* TX error */ - if (reg_eir & EIR_TXERIF) - { - data |= (rt_uint8_t)EIR_TXERIF; - } - /* RX error */ - if (reg_eir & EIR_RXERIF) - { - data |= (rt_uint8_t)EIR_RXERIF; - } - /* Clear flags */ - efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIR, &data); - - /* Get packet counter (Errata 6) */ - efm_eth_sendCmd(ENC28J60_READ_CTRL_REG, EPKTCNT, (rt_uint8_t *)&cnt); - if (cnt) - { - /* Inform Ethernet thread */ - eth_device_ready(ð_dev); - } - - /* Enable other interrupts */ - data = EIE_INTIE; - efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, EIE, &data); + rt_uint8_t reg_eir, data; + volatile rt_uint8_t cnt; + + /* Disable RX and other interrutps */ + data = EIE_PKTIE | EIE_INTIE; + efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIE, &data); + + /* Get interrupt flag */ + efm_eth_sendCmd(ENC28J60_READ_CTRL_REG, EIR, ®_eir); + + data = 0; + /* DMA completed */ + if (reg_eir & EIR_DMAIF) + { + data |= (rt_uint8_t)EIR_DMAIF; + } + /* Link Changed */ + if (reg_eir & EIR_LINKIF) + { + /* Read PHIR to clear the flag */ + efm_eth_readPhy(PHIR); + } + /* TX done */ + if (reg_eir & EIR_TXIF) + { + data |= (rt_uint8_t)EIR_TXIF; + } + /* TX error */ + if (reg_eir & EIR_TXERIF) + { + data |= (rt_uint8_t)EIR_TXERIF; + } + /* RX error */ + if (reg_eir & EIR_RXERIF) + { + data |= (rt_uint8_t)EIR_RXERIF; + } + /* Clear flags */ + efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIR, &data); + + /* Get packet counter (Errata 6) */ + efm_eth_sendCmd(ENC28J60_READ_CTRL_REG, EPKTCNT, (rt_uint8_t *)&cnt); + if (cnt) + { + /* Inform Ethernet thread */ + eth_device_ready(ð_dev); + } + + /* Enable other interrupts */ + data = EIE_INTIE; + efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, EIE, &data); } /***************************************************************************//** @@ -435,119 +435,119 @@ void efm_eth_isr(rt_device_t dev) ******************************************************************************/ static rt_err_t efm_eth_init(rt_device_t dev) { - rt_uint16_t reg_phy; - rt_uint8_t data; - - /* Reset chip select */ - efm_eth_cs(0); - /* Software reset */ - efm_eth_sendCmd(ENC28J60_SOFT_RESET, EFM32_NO_DATA, EFM32_NO_POINTER); - /* Waiting for at least 1 ms (Errata 2) */ - rt_thread_delay(ETH_PERIOD_WAIT_INIT); - ethNxtPkt = RXSTART_INIT; - ethBank = 0; - - /* Init RX buffer */ - efm_eth_writeReg(ERXSTL, RXSTART_INIT & 0xFF); - efm_eth_writeReg(ERXSTH, RXSTART_INIT >> 8); - efm_eth_writeReg(ERXNDL, RXSTOP_INIT & 0xFF); - efm_eth_writeReg(ERXNDH, RXSTOP_INIT >> 8); - efm_eth_writeReg(ERXRDPTL, RXSTOP_INIT & 0xFF); - efm_eth_writeReg(ERXRDPTH, RXSTOP_INIT >> 8); - - /* Init TX buffer */ - efm_eth_writeReg(ETXSTL, TXSTART_INIT & 0xFF); - efm_eth_writeReg(ETXSTH, TXSTART_INIT >> 8); - efm_eth_writeReg(ETXNDL, TXSTOP_INIT & 0xFF); - efm_eth_writeReg(ETXNDH, TXSTOP_INIT >> 8); - efm_eth_writeReg(EWRPTL, TXSTART_INIT & 0xFF); - efm_eth_writeReg(EWRPTH, TXSTART_INIT >> 8); - - /* Init RX filters */ - /* For broadcast packets we allow only ARP packtets - All other packets should be unicast only for our mac (MAADR) - - The pattern to match on is therefore - Type ETH.DST - ARP BROADCAST - 06 08 -- -- -- -- -- -- ff ff ff ff ff ff - These poitions are: 11 0000 0011 1111 in binary and 30 3f in hex - Checksum for theses bytes is: f7 f9 */ - efm_eth_writeReg(EPMM0, 0x3f); - efm_eth_writeReg(EPMM1, 0x30); - efm_eth_writeReg(EPMCSL, 0xf9); - efm_eth_writeReg(EPMCSH, 0xf7); - efm_eth_writeReg(ERXFCON, ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_PMEN); - //efm_eth_writeReg(ERXFCON, ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_BCEN); - /* Waiting For OST: The OST does not expire until 7500 OSC1 clock cycles (300 uS) - pass after Power-on Reset or wake-up from Power-Down mode occurs */ - - /* Init MAC */ - /* Enable RX, IEEE defined flow control */ - efm_eth_writeReg(MACON1, MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS); - /* Enable padding to 60 bytes, CRC and frame length status reporting */ + rt_uint16_t reg_phy; + rt_uint8_t data; + + /* Reset chip select */ + efm_eth_cs(0); + /* Software reset */ + efm_eth_sendCmd(ENC28J60_SOFT_RESET, EFM32_NO_DATA, EFM32_NO_POINTER); + /* Waiting for at least 1 ms (Errata 2) */ + rt_thread_delay(ETH_PERIOD_WAIT_INIT); + ethNxtPkt = RXSTART_INIT; + ethBank = 0; + + /* Init RX buffer */ + efm_eth_writeReg(ERXSTL, RXSTART_INIT & 0xFF); + efm_eth_writeReg(ERXSTH, RXSTART_INIT >> 8); + efm_eth_writeReg(ERXNDL, RXSTOP_INIT & 0xFF); + efm_eth_writeReg(ERXNDH, RXSTOP_INIT >> 8); + efm_eth_writeReg(ERXRDPTL, RXSTOP_INIT & 0xFF); + efm_eth_writeReg(ERXRDPTH, RXSTOP_INIT >> 8); + + /* Init TX buffer */ + efm_eth_writeReg(ETXSTL, TXSTART_INIT & 0xFF); + efm_eth_writeReg(ETXSTH, TXSTART_INIT >> 8); + efm_eth_writeReg(ETXNDL, TXSTOP_INIT & 0xFF); + efm_eth_writeReg(ETXNDH, TXSTOP_INIT >> 8); + efm_eth_writeReg(EWRPTL, TXSTART_INIT & 0xFF); + efm_eth_writeReg(EWRPTH, TXSTART_INIT >> 8); + + /* Init RX filters */ + /* For broadcast packets we allow only ARP packtets + All other packets should be unicast only for our mac (MAADR) + + The pattern to match on is therefore + Type ETH.DST + ARP BROADCAST + 06 08 -- -- -- -- -- -- ff ff ff ff ff ff + These poitions are: 11 0000 0011 1111 in binary and 30 3f in hex + Checksum for theses bytes is: f7 f9 */ + efm_eth_writeReg(EPMM0, 0x3f); + efm_eth_writeReg(EPMM1, 0x30); + efm_eth_writeReg(EPMCSL, 0xf9); + efm_eth_writeReg(EPMCSH, 0xf7); + efm_eth_writeReg(ERXFCON, ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_PMEN); + //efm_eth_writeReg(ERXFCON, ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_BCEN); + /* Waiting For OST: The OST does not expire until 7500 OSC1 clock cycles (300 uS) + pass after Power-on Reset or wake-up from Power-Down mode occurs */ + + /* Init MAC */ + /* Enable RX, IEEE defined flow control */ + efm_eth_writeReg(MACON1, MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS); + /* Enable padding to 60 bytes, CRC and frame length status reporting */ #if defined(ETH_HALF_DUPLEX) - efm_eth_writeReg(MACON3, MACON3_PADCFG0 | MACON3_TXCRCEN | MACON3_FRMLNEN); - efm_eth_writeReg(MACON4, MACON4_DEFER); + efm_eth_writeReg(MACON3, MACON3_PADCFG0 | MACON3_TXCRCEN | MACON3_FRMLNEN); + efm_eth_writeReg(MACON4, MACON4_DEFER); #else - efm_eth_writeReg(MACON3, \ - MACON3_PADCFG0 | MACON3_TXCRCEN | MACON3_FRMLNEN | MACON3_FULDPX); + efm_eth_writeReg(MACON3, \ + MACON3_PADCFG0 | MACON3_TXCRCEN | MACON3_FRMLNEN | MACON3_FULDPX); #endif - /* Set the maximum packet length */ - efm_eth_writeReg(MAMXFLL, MAX_FRAMELEN & 0xFF); - efm_eth_writeReg(MAMXFLH, MAX_FRAMELEN >> 8); - /* Set inter-packet gap (back-to-back). Full-Duplex: 0x15, Half-Duplex: 0x12 */ + /* Set the maximum packet length */ + efm_eth_writeReg(MAMXFLL, MAX_FRAMELEN & 0xFF); + efm_eth_writeReg(MAMXFLH, MAX_FRAMELEN >> 8); + /* Set inter-packet gap (back-to-back). Full-Duplex: 0x15, Half-Duplex: 0x12 */ #if defined(ETH_HALF_DUPLEX) - efm_eth_writeReg(MABBIPG, 0x12); + efm_eth_writeReg(MABBIPG, 0x12); #else - efm_eth_writeReg(MABBIPG, 0x15); + efm_eth_writeReg(MABBIPG, 0x15); #endif - /* Set inter-packet gap (non-back-to-back). - Full-Duplex: 0x0012, Half-Duplex: 0x0C12 */ - efm_eth_writeReg(MAIPGL, 0x12); + /* Set inter-packet gap (non-back-to-back). + Full-Duplex: 0x0012, Half-Duplex: 0x0C12 */ + efm_eth_writeReg(MAIPGL, 0x12); #if defined(ETH_HALF_DUPLEX) - efm_eth_writeReg(MAIPGH, 0x0C); - /* Set retransmission and collision window */ - efm_eth_writeReg(MACLCON1, 0x0F); - efm_eth_writeReg(MACLCON2, 0x37); + efm_eth_writeReg(MAIPGH, 0x0C); + /* Set retransmission and collision window */ + efm_eth_writeReg(MACLCON1, 0x0F); + efm_eth_writeReg(MACLCON2, 0x37); #endif - /* Set MAC address - NOTE: MAC address in ENC28J60 is byte-backward */ - efm_eth_writeReg(MAADR1, eth_addr[0]); - efm_eth_writeReg(MAADR2, eth_addr[1]); - efm_eth_writeReg(MAADR3, eth_addr[2]); - efm_eth_writeReg(MAADR4, eth_addr[3]); - efm_eth_writeReg(MAADR5, eth_addr[4]); - efm_eth_writeReg(MAADR6, eth_addr[5]); - - /* Init PHY */ + /* Set MAC address + NOTE: MAC address in ENC28J60 is byte-backward */ + efm_eth_writeReg(MAADR1, eth_addr[0]); + efm_eth_writeReg(MAADR2, eth_addr[1]); + efm_eth_writeReg(MAADR3, eth_addr[2]); + efm_eth_writeReg(MAADR4, eth_addr[3]); + efm_eth_writeReg(MAADR5, eth_addr[4]); + efm_eth_writeReg(MAADR6, eth_addr[5]); + + /* Init PHY */ #if defined(ETH_HALF_DUPLEX) - reg_phy = efm_eth_readPhy(PHCON2); - efm_eth_writePhy(PHCON2, reg_phy | PHCON2_HDLDIS); + reg_phy = efm_eth_readPhy(PHCON2); + efm_eth_writePhy(PHCON2, reg_phy | PHCON2_HDLDIS); #else - reg_phy = efm_eth_readPhy(PHCON1); - efm_eth_writePhy(PHCON1, reg_phy | PHCON1_PDPXMD); + reg_phy = efm_eth_readPhy(PHCON1); + efm_eth_writePhy(PHCON1, reg_phy | PHCON1_PDPXMD); #endif - /* LEDA: Display link status; - LEDB: Display transmit and receive activity */ - reg_phy = efm_eth_readPhy(PHLCON); - efm_eth_writePhy(PHLCON, (reg_phy & 0xF00F) | 0x0470); - - /* Disable clock output */ - efm_eth_writeReg(ECOCON, 0x00); - - /* Clear interrutp flags */ - data = EIR_DMAIF | EIR_TXIF | EIR_TXERIF | EIR_RXERIF; - efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIR, &data); - /* Enable interrutps */ - data = EIE_INTIE | EIE_PKTIE | EIE_TXIE; - efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, EIE, &data); - /* Enable RX */ - data = ECON1_RXEN; - efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, ECON1, &data); - - eth_debug("ETH: Init OK\n"); - return RT_EOK; + /* LEDA: Display link status; + LEDB: Display transmit and receive activity */ + reg_phy = efm_eth_readPhy(PHLCON); + efm_eth_writePhy(PHLCON, (reg_phy & 0xF00F) | 0x0470); + + /* Disable clock output */ + efm_eth_writeReg(ECOCON, 0x00); + + /* Clear interrutp flags */ + data = EIR_DMAIF | EIR_TXIF | EIR_TXERIF | EIR_RXERIF; + efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIR, &data); + /* Enable interrutps */ + data = EIE_INTIE | EIE_PKTIE | EIE_TXIE; + efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, EIE, &data); + /* Enable RX */ + data = ECON1_RXEN; + efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, ECON1, &data); + + eth_debug("ETH: Init OK\n"); + return RT_EOK; } /***************************************************************************//** @@ -569,8 +569,8 @@ static rt_err_t efm_eth_init(rt_device_t dev) ******************************************************************************/ static rt_err_t efm_eth_open(rt_device_t dev, rt_uint16_t oflag) { - eth_debug("ETH: Open, flag %x\n", eth_dev.parent.flag); - return RT_EOK; + eth_debug("ETH: Open, flag %x\n", eth_dev.parent.flag); + return RT_EOK; } /***************************************************************************//** @@ -589,8 +589,8 @@ static rt_err_t efm_eth_open(rt_device_t dev, rt_uint16_t oflag) ******************************************************************************/ static rt_err_t efm_eth_close(rt_device_t dev) { - eth_debug("ETH: Close, flag %x\n", eth_dev.parent.flag); - return RT_EOK; + eth_debug("ETH: Close, flag %x\n", eth_dev.parent.flag); + return RT_EOK; } /***************************************************************************//** @@ -617,10 +617,10 @@ static rt_err_t efm_eth_close(rt_device_t dev) * Number of read bytes ******************************************************************************/ static rt_size_t efm_eth_read( - rt_device_t dev, - rt_off_t pos, - void *buffer, - rt_size_t size) + rt_device_t dev, + rt_off_t pos, + void *buffer, + rt_size_t size) { rt_set_errno(-RT_ENOSYS); return 0; @@ -650,10 +650,10 @@ static rt_size_t efm_eth_read( * Number of written bytes ******************************************************************************/ static rt_size_t efm_eth_write ( - rt_device_t dev, - rt_off_t pos, - const void *buffer, - rt_size_t size) + rt_device_t dev, + rt_off_t pos, + const void *buffer, + rt_size_t size) { rt_set_errno(-RT_ENOSYS); return 0; @@ -674,35 +674,35 @@ static rt_size_t efm_eth_write ( * Ethernet control command * * @param[in] args -* Arguments +* Arguments * * @return * Error code ******************************************************************************/ static rt_err_t efm_eth_control ( - rt_device_t dev, - rt_uint8_t cmd, - void *args) + rt_device_t dev, + rt_uint8_t cmd, + void *args) { - rt_err_t ret; - - ret = -RT_ERROR; - switch(cmd) - { - case NIOCTL_GADDR: - /* Get MAC address */ - if(args) - { - rt_memcpy(args, eth_addr, sizeof(eth_addr)); - ret = RT_EOK; - } - break; - - default : - break; - } - - return RT_EOK; + rt_err_t ret; + + ret = -RT_ERROR; + switch(cmd) + { + case NIOCTL_GADDR: + /* Get MAC address */ + if(args) + { + rt_memcpy(args, eth_addr, sizeof(eth_addr)); + ret = RT_EOK; + } + break; + + default : + break; + } + + return RT_EOK; } /***************************************************************************//** @@ -721,43 +721,43 @@ static rt_err_t efm_eth_control ( ******************************************************************************/ struct pbuf *efm_eth_rx(rt_device_t dev) { - rt_uint8_t buf_ins[5], buf_read[6]; - rt_uint8_t data, reg_eie; - rt_uint16_t len_rx, sta_rx; - struct pbuf* p; + rt_uint8_t buf_ins[5], buf_read[6]; + rt_uint8_t data, reg_eie; + rt_uint16_t len_rx, sta_rx; + struct pbuf* p; /* Lock device */ rt_sem_take(ðLock, RT_WAITING_FOREVER); /* Disable interrupts */ - data = EIE_INTIE; - efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIE, &data); + data = EIE_INTIE; + efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIE, &data); - p = RT_NULL; - reg_eie = 0; + p = RT_NULL; + reg_eie = 0; if (efm_eth_readReg(EPKTCNT)) { /* Set read pointer to the start of RX packet */ efm_eth_writeReg(ERDPTL, ethNxtPkt & 0xFF); efm_eth_writeReg(ERDPTH, ethNxtPkt >> 8); - /* Send read buffer command */ - efm_eth_sendCmd(ENC28J60_READ_BUF_MEM, EFM32_NO_DATA, EFM32_NO_POINTER); - /* Build instruction buffer */ - buf_ins[0] = 0x00; - *(rt_uint8_t **)(&buf_ins[1]) = buf_read; - /* Read packet header */ - if (spi->read(spi, EFM32_NO_DATA, buf_ins, sizeof(buf_read)) == 0) - { - eth_debug("ETH: RX header failed!\n"); - } - - ethNxtPkt = buf_read[0] | (buf_read[1] << 8); - len_rx = buf_read[2] | (buf_read[3] << 8); - sta_rx = buf_read[4] | (buf_read[5] << 8); - eth_debug("ETH: RX header ethNxtPkt %x, len_rx %x, sta_rx %x\n", - ethNxtPkt, len_rx, sta_rx); - /* Check if OK */ + /* Send read buffer command */ + efm_eth_sendCmd(ENC28J60_READ_BUF_MEM, EFM32_NO_DATA, EFM32_NO_POINTER); + /* Build instruction buffer */ + buf_ins[0] = 0x00; + *(rt_uint8_t **)(&buf_ins[1]) = buf_read; + /* Read packet header */ + if (spi->read(spi, EFM32_NO_DATA, buf_ins, sizeof(buf_read)) == 0) + { + eth_debug("ETH: RX header failed!\n"); + } + + ethNxtPkt = buf_read[0] | (buf_read[1] << 8); + len_rx = buf_read[2] | (buf_read[3] << 8); + sta_rx = buf_read[4] | (buf_read[5] << 8); + eth_debug("ETH: RX header ethNxtPkt %x, len_rx %x, sta_rx %x\n", + ethNxtPkt, len_rx, sta_rx); + /* Check if OK */ if (sta_rx & 0x80) { /* Allocate pbuf */ @@ -768,67 +768,67 @@ struct pbuf *efm_eth_rx(rt_device_t dev) for (q = p; q != RT_NULL; q= q->next) { - /* Build instruction buffer */ - buf_ins[0] = 0x00; - *(rt_uint8_t **)(&buf_ins[1]) = q->payload; - /* Read packet header */ - if (spi->read(spi, EFM32_NO_DATA, buf_ins, q->len) == 0) - { - eth_debug("ETH: RX payload failed!\n"); - } + /* Build instruction buffer */ + buf_ins[0] = 0x00; + *(rt_uint8_t **)(&buf_ins[1]) = q->payload; + /* Read packet header */ + if (spi->read(spi, EFM32_NO_DATA, buf_ins, q->len) == 0) + { + eth_debug("ETH: RX payload failed!\n"); + } #ifdef EFM32_ETHERNET_DEBUG - { - rt_uint8_t *temp = (rt_uint8_t *)q->payload; - rt_uint32_t i; - - eth_debug("ETH: ***** read RX (q->len %x) *****\n", q->len); - for (i = 0; i < q->len; i += 8) - { - eth_debug("%02x %02x %02x %02x %02x %02x %02x %02x | %c %c %c %c %c %c %c %c\n", - temp[i], temp[i + 1], temp[i + 2], temp[i + 3], - temp[i + 4], temp[i + 5], temp[i + 6], temp[i + 7], - temp[i], temp[i + 1], temp[i + 2], temp[i + 3], - temp[i + 4], temp[i + 5], temp[i + 6], temp[i + 7]); - } - } + { + rt_uint8_t *temp = (rt_uint8_t *)q->payload; + rt_uint32_t i; + + eth_debug("ETH: ***** read RX (q->len %x) *****\n", q->len); + for (i = 0; i < q->len; i += 8) + { + eth_debug("%02x %02x %02x %02x %02x %02x %02x %02x | %c %c %c %c %c %c %c %c\n", + temp[i], temp[i + 1], temp[i + 2], temp[i + 3], + temp[i + 4], temp[i + 5], temp[i + 6], temp[i + 7], + temp[i], temp[i + 1], temp[i + 2], temp[i + 3], + temp[i + 4], temp[i + 5], temp[i + 6], temp[i + 7]); + } + } #endif } } - else - { - eth_debug("ETH: No memory for pbuf!!!\n"); - } + else + { + eth_debug("ETH: No memory for pbuf!!!\n"); + } } - else - { + else + { eth_debug("ETH: Invalid CRC or symbol error occurred!\n"); } - efm_eth_cs(0); + efm_eth_cs(0); /* Free buffer */ efm_eth_writeReg(ERXRDPTL, ethNxtPkt & 0xFF); efm_eth_writeReg(ERXRDPTH, ethNxtPkt >> 8); /* Decrease counter */ - data = ECON2_PKTDEC; + data = ECON2_PKTDEC; efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, ECON2, &data); } - else - { - /* Enable RX */ - data = ECON1_RXEN; - efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, ECON1, &data); + else + { + /* Enable RX */ + data = ECON1_RXEN; + efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, ECON1, &data); - reg_eie |= EIE_PKTIE; - eth_debug("ETH: Enable RX interrupt\n"); - } - eth_debug("ETH: RX counter %x\n", efm_eth_readReg(EPKTCNT)); + reg_eie |= EIE_PKTIE; + eth_debug("ETH: Enable RX interrupt\n"); + } + eth_debug("ETH: RX counter %x\n", efm_eth_readReg(EPKTCNT)); /* Enable interrupts */ - reg_eie |= EIE_INTIE; - efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, EIE, ®_eie); + reg_eie |= EIE_INTIE; + efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, EIE, ®_eie); - /* Unlock device */ + /* Unlock device */ rt_sem_release(ðLock); return p; @@ -849,76 +849,76 @@ struct pbuf *efm_eth_rx(rt_device_t dev) * Pointer to packet buffer * * @return -* Error code +* Error code ******************************************************************************/ rt_err_t efm_eth_tx(rt_device_t dev, struct pbuf* p) { - rt_uint8_t data; - struct pbuf* q; + rt_uint8_t data; + struct pbuf* q; /* Lock device */ rt_sem_take(ðLock, RT_WAITING_FOREVER); /* Disable interrupts */ - data = EIE_INTIE; - efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIE, &data); - - /* Set write pointer to the start of TX buffer */ - efm_eth_writeReg(EWRPTL, TXSTART_INIT & 0xFF); - efm_eth_writeReg(EWRPTH, TXSTART_INIT >> 8); - /* Set buffer end pointer according to the packet size */ - efm_eth_writeReg(ETXNDL, (TXSTART_INIT + p->tot_len + 1) & 0xFF); - efm_eth_writeReg(ETXNDH, (TXSTART_INIT + p->tot_len + 1) >> 8); - - /* Send write buffer command */ - data = 0x00; /* Control byte */ - efm_eth_sendCmd(ENC28J60_WRITE_BUF_MEM, EFM32_NO_DATA, &data); - /* Send data */ - for (q = p; q != NULL; q = q->next) - { - if (spi->write(spi, EFM32_NO_DATA, q->payload, q->len) == 0) - { - eth_debug("ETH: TX failed!\n"); - return -RT_ERROR; - } + data = EIE_INTIE; + efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIE, &data); + + /* Set write pointer to the start of TX buffer */ + efm_eth_writeReg(EWRPTL, TXSTART_INIT & 0xFF); + efm_eth_writeReg(EWRPTH, TXSTART_INIT >> 8); + /* Set buffer end pointer according to the packet size */ + efm_eth_writeReg(ETXNDL, (TXSTART_INIT + p->tot_len + 1) & 0xFF); + efm_eth_writeReg(ETXNDH, (TXSTART_INIT + p->tot_len + 1) >> 8); + + /* Send write buffer command */ + data = 0x00; /* Control byte */ + efm_eth_sendCmd(ENC28J60_WRITE_BUF_MEM, EFM32_NO_DATA, &data); + /* Send data */ + for (q = p; q != NULL; q = q->next) + { + if (spi->write(spi, EFM32_NO_DATA, q->payload, q->len) == 0) + { + eth_debug("ETH: TX failed!\n"); + return -RT_ERROR; + } #ifdef EFM32_ETHERNET_DEBUG - { - rt_uint8_t *temp = (rt_uint8_t *)q->payload; - rt_uint32_t i; - - eth_debug("ETH: ***** write TX (len %d) *****\n", p->len); - for (i = 0; i < q->len; i += 8) - { - eth_debug("%02x %02x %02x %02x %02x %02x %02x %02x | %c %c %c %c %c %c %c %c\n", - temp[i], temp[i + 1], temp[i + 2], temp[i + 3], - temp[i + 4], temp[i + 5], temp[i + 6], temp[i + 7], - temp[i], temp[i + 1], temp[i + 2], temp[i + 3], - temp[i + 4], temp[i + 5], temp[i + 6], temp[i + 7]); - } - } + { + rt_uint8_t *temp = (rt_uint8_t *)q->payload; + rt_uint32_t i; + + eth_debug("ETH: ***** write TX (len %d) *****\n", p->len); + for (i = 0; i < q->len; i += 8) + { + eth_debug("%02x %02x %02x %02x %02x %02x %02x %02x | %c %c %c %c %c %c %c %c\n", + temp[i], temp[i + 1], temp[i + 2], temp[i + 3], + temp[i + 4], temp[i + 5], temp[i + 6], temp[i + 7], + temp[i], temp[i + 1], temp[i + 2], temp[i + 3], + temp[i + 4], temp[i + 5], temp[i + 6], temp[i + 7]); + } + } #endif - } - efm_eth_cs(0); - /* Start TX */ - data = ECON1_TXRTS; - efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, ECON1, &data); - /* Errata 12 */ - if (efm_eth_readReg(EIR) & EIR_TXERIF) - { - efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, ECON1, &data); - data = EIR_TXERIF; - efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIR, &data); - data = ECON1_TXRTS; - efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, ECON1, &data); - } - - /* Waiting for a while */ - rt_thread_delay(ETH_PERIOD_WAIT_INIT); + } + efm_eth_cs(0); + /* Start TX */ + data = ECON1_TXRTS; + efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, ECON1, &data); + /* Errata 12 */ + if (efm_eth_readReg(EIR) & EIR_TXERIF) + { + efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, ECON1, &data); + data = EIR_TXERIF; + efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIR, &data); + data = ECON1_TXRTS; + efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, ECON1, &data); + } + + /* Waiting for a while */ + rt_thread_delay(ETH_PERIOD_WAIT_INIT); /* Enable interrupts */ - data = EIE_INTIE; - efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, EIE, &data); + data = EIE_INTIE; + efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, EIE, &data); - /* Unlock device */ + /* Unlock device */ rt_sem_release(ðLock); return RT_EOK; @@ -926,164 +926,164 @@ rt_err_t efm_eth_tx(rt_device_t dev, struct pbuf* p) /***************************************************************************//** * @brief -* Initialize all Ethernet related hardware and register the device to kernel +* Initialize all Ethernet related hardware and register the device to kernel * * @details * * @note * * @return -* Error code +* Error code ******************************************************************************/ rt_err_t efm_hw_eth_init(void) { - struct efm32_usart_device_t *usart; - efm32_irq_hook_init_t hook; - - do - { - /* Find SPI device */ - spi = rt_device_find(ETH_USING_DEVICE_NAME); - if (spi == RT_NULL) - { - eth_debug("ETH: Can't find device %s!\n", - ETH_USING_DEVICE_NAME); - break; - } - eth_debug("ETH: Find device %s\n", ETH_USING_DEVICE_NAME); - - /* Config chip slect pin */ - usart = (struct efm32_usart_device_t *)(spi->user_data); - if (!(usart->state & USART_STATE_AUTOCS)) - { - GPIO_PinModeSet(ETH_CS_PORT, ETH_CS_PIN, gpioModePushPull, 1); - ethAutoCs = false; - } - /* Config reset pin */ - GPIO_PinModeSet(ETH_RESET_PORT, ETH_RESET_PIN, gpioModePushPull, 0); - /* Config interrupt pin */ - GPIO_PinModeSet(ETH_INT_PORT, ETH_INT_PIN, gpioModeInput, 1); - - /* Config interrupt */ - hook.type = efm32_irq_type_gpio; - hook.unit = ETH_INT_PIN; - hook.cbFunc = efm_eth_isr; - hook.userPtr = RT_NULL; - efm32_irq_hook_register(&hook); - /* Clear pending interrupt */ - BITBAND_Peripheral(&(GPIO->IFC), ETH_INT_PIN, 0x1UL); - /* Set falling edge interrupt and clear/enable it */ - GPIO_IntConfig( - ETH_INT_PORT, - ETH_INT_PIN, - false, - true, - true); - if ((rt_uint8_t)ETH_INT_PIN % 2) - { - NVIC_ClearPendingIRQ(GPIO_ODD_IRQn); - NVIC_SetPriority(GPIO_ODD_IRQn, EFM32_IRQ_PRI_DEFAULT); - NVIC_EnableIRQ(GPIO_ODD_IRQn); - } - else - { - NVIC_ClearPendingIRQ(GPIO_EVEN_IRQn); - NVIC_SetPriority(GPIO_EVEN_IRQn, EFM32_IRQ_PRI_DEFAULT); - NVIC_EnableIRQ(GPIO_EVEN_IRQn); - } - - /* Set SPI speed */ - USART_BaudrateSyncSet(usart->usart_device, 0, ETH_CLK_MAX); - - /* Initialize semaphore */ - rt_sem_init(ðLock, ETH_DEVICE_NAME, 1, RT_IPC_FLAG_FIFO); - - /* Register Ethernet device */ - eth_dev.parent.init = efm_eth_init; - eth_dev.parent.open = efm_eth_open; - eth_dev.parent.close = efm_eth_close; - eth_dev.parent.read = efm_eth_read; - eth_dev.parent.write = efm_eth_write; - eth_dev.parent.control = efm_eth_control; - eth_dev.eth_rx = efm_eth_rx; - eth_dev.eth_tx = efm_eth_tx; - eth_device_init(ð_dev, ETH_DEVICE_NAME); - - /* Start device */ - GPIO_PinOutSet(ETH_RESET_PORT, ETH_RESET_PIN); - - eth_debug("ETH: HW init OK\n"); - return RT_EOK; - } while (0); - - /* Release buffer */ - rt_kprintf("ETH: HW init failed!\n"); - return -RT_ERROR; + struct efm32_usart_device_t *usart; + efm32_irq_hook_init_t hook; + + do + { + /* Find SPI device */ + spi = rt_device_find(ETH_USING_DEVICE_NAME); + if (spi == RT_NULL) + { + eth_debug("ETH: Can't find device %s!\n", + ETH_USING_DEVICE_NAME); + break; + } + eth_debug("ETH: Find device %s\n", ETH_USING_DEVICE_NAME); + + /* Config chip slect pin */ + usart = (struct efm32_usart_device_t *)(spi->user_data); + if (!(usart->state & USART_STATE_AUTOCS)) + { + GPIO_PinModeSet(ETH_CS_PORT, ETH_CS_PIN, gpioModePushPull, 1); + ethAutoCs = false; + } + /* Config reset pin */ + GPIO_PinModeSet(ETH_RESET_PORT, ETH_RESET_PIN, gpioModePushPull, 0); + /* Config interrupt pin */ + GPIO_PinModeSet(ETH_INT_PORT, ETH_INT_PIN, gpioModeInput, 1); + + /* Config interrupt */ + hook.type = efm32_irq_type_gpio; + hook.unit = ETH_INT_PIN; + hook.cbFunc = efm_eth_isr; + hook.userPtr = RT_NULL; + efm32_irq_hook_register(&hook); + /* Clear pending interrupt */ + BITBAND_Peripheral(&(GPIO->IFC), ETH_INT_PIN, 0x1UL); + /* Set falling edge interrupt and clear/enable it */ + GPIO_IntConfig( + ETH_INT_PORT, + ETH_INT_PIN, + false, + true, + true); + if ((rt_uint8_t)ETH_INT_PIN % 2) + { + NVIC_ClearPendingIRQ(GPIO_ODD_IRQn); + NVIC_SetPriority(GPIO_ODD_IRQn, EFM32_IRQ_PRI_DEFAULT); + NVIC_EnableIRQ(GPIO_ODD_IRQn); + } + else + { + NVIC_ClearPendingIRQ(GPIO_EVEN_IRQn); + NVIC_SetPriority(GPIO_EVEN_IRQn, EFM32_IRQ_PRI_DEFAULT); + NVIC_EnableIRQ(GPIO_EVEN_IRQn); + } + + /* Set SPI speed */ + USART_BaudrateSyncSet(usart->usart_device, 0, ETH_CLK_MAX); + + /* Initialize semaphore */ + rt_sem_init(ðLock, ETH_DEVICE_NAME, 1, RT_IPC_FLAG_FIFO); + + /* Register Ethernet device */ + eth_dev.parent.init = efm_eth_init; + eth_dev.parent.open = efm_eth_open; + eth_dev.parent.close = efm_eth_close; + eth_dev.parent.read = efm_eth_read; + eth_dev.parent.write = efm_eth_write; + eth_dev.parent.control = efm_eth_control; + eth_dev.eth_rx = efm_eth_rx; + eth_dev.eth_tx = efm_eth_tx; + eth_device_init(ð_dev, ETH_DEVICE_NAME); + + /* Start device */ + GPIO_PinOutSet(ETH_RESET_PORT, ETH_RESET_PIN); + + eth_debug("ETH: HW init OK\n"); + return RT_EOK; + } while (0); + + /* Release buffer */ + rt_kprintf("ETH: HW init failed!\n"); + return -RT_ERROR; } /******************************************************************************* - * Export to FINSH + * Export to FINSH ******************************************************************************/ -#if defined(EFM32_USING_ETH_UTILS) +#if defined(EFM32_USING_ETH_UTILS) #ifdef RT_USING_FINSH #include void list_eth(void) { - rt_uint16_t reg_phy; - rt_uint8_t data; - - rt_kprintf(" ENC28J60 on %s\n", ETH_USING_DEVICE_NAME); - rt_kprintf(" ------------------------------\n"); - reg_phy = efm_eth_readPhy(PHSTAT2); - if (reg_phy & PHSTAT2_PLRITY) - { - rt_kprintf(" Cable polarity is reversed\n"); - } - else - { - rt_kprintf(" Cable polarity is correct\n"); - } - if (reg_phy & PHSTAT2_DPXSTAT) - { - rt_kprintf(" Full-duplex mode\n"); - } - else - { - rt_kprintf(" Half-duplex mode\n"); - } - if (reg_phy & PHSTAT2_LSTAT) - { - rt_kprintf(" Link is up\n"); - } - else - { - rt_kprintf(" Link is down\n"); - } - if (reg_phy & PHSTAT2_COLSTAT) - { - rt_kprintf(" Collision is occuring\n"); - } - else - { - rt_kprintf(" No collision\n"); - } - if (reg_phy & PHSTAT2_RXSTAT) - { - rt_kprintf(" RX is busy\n"); - } - else - { - rt_kprintf(" RX is idle\n"); - } - if (reg_phy & PHSTAT2_TXSTAT) - { - rt_kprintf(" TX is busy\n"); - } - else - { - rt_kprintf(" TX is idle\n"); - } + rt_uint16_t reg_phy; + rt_uint8_t data; + + rt_kprintf(" ENC28J60 on %s\n", ETH_USING_DEVICE_NAME); + rt_kprintf(" ------------------------------\n"); + reg_phy = efm_eth_readPhy(PHSTAT2); + if (reg_phy & PHSTAT2_PLRITY) + { + rt_kprintf(" Cable polarity is reversed\n"); + } + else + { + rt_kprintf(" Cable polarity is correct\n"); + } + if (reg_phy & PHSTAT2_DPXSTAT) + { + rt_kprintf(" Full-duplex mode\n"); + } + else + { + rt_kprintf(" Half-duplex mode\n"); + } + if (reg_phy & PHSTAT2_LSTAT) + { + rt_kprintf(" Link is up\n"); + } + else + { + rt_kprintf(" Link is down\n"); + } + if (reg_phy & PHSTAT2_COLSTAT) + { + rt_kprintf(" Collision is occuring\n"); + } + else + { + rt_kprintf(" No collision\n"); + } + if (reg_phy & PHSTAT2_RXSTAT) + { + rt_kprintf(" RX is busy\n"); + } + else + { + rt_kprintf(" RX is idle\n"); + } + if (reg_phy & PHSTAT2_TXSTAT) + { + rt_kprintf(" TX is busy\n"); + } + else + { + rt_kprintf(" TX is idle\n"); + } } FINSH_FUNCTION_EXPORT(list_eth, list the Ethernet device status.) @@ -1091,108 +1091,108 @@ FINSH_FUNCTION_EXPORT(list_eth, list the Ethernet device status.) rt_err_t get_ip(char *ip) { - err_t ret; - struct ip_addr server_ip; - struct netconn *conn; - struct netbuf *buf; - char *rq, *rq2; - u16_t len; - const char query[] = "GET / HTTP/1.0\r\nHOST: checkip.dyndns.com\r\n\r\n"; - const char find[] = "body"; - - do - { + err_t ret; + struct ip_addr server_ip; + struct netconn *conn; + struct netbuf *buf; + char *rq, *rq2; + u16_t len; + const char query[] = "GET / HTTP/1.0\r\nHOST: checkip.dyndns.com\r\n\r\n"; + const char find[] = "body"; + + do + { #if defined(RT_LWIP_DNS) - ret = netconn_gethostbyname("checkip.dyndns.com", &server_ip); - if (ret != ERR_OK) - { - break; - } + ret = netconn_gethostbyname("checkip.dyndns.com", &server_ip); + if (ret != ERR_OK) + { + break; + } #else - IP4_ADDR(&server_ip, 216,146,38,70); // IP address of "checkip.dyndns.com" + IP4_ADDR(&server_ip, 216,146,38,70); // IP address of "checkip.dyndns.com" #endif - conn = netconn_new(NETCONN_TCP); - if (conn == NULL) - { - break; - } - - ret = netconn_connect(conn, &server_ip, 80); - if (ret != ERR_OK) - { - break; - } - - /* Send the query */ - ret = netconn_write(conn, query, sizeof(query) - 1, 0); - if (ret != ERR_OK) - { - break; - } - - buf = netconn_recv(conn); - if (buf != NULL) - { - /* Get the response */ - ret = netbuf_data(buf, (void **)&rq, &len); - if (ret != ERR_OK) - { - break; - } - - /* Find the IP address */ - rq = rt_strstr(rq, find); - if (rq == RT_NULL) - { - break; - } - rq += 5; - rq2 = rq; - rq2 = rt_strstr(rq2, find); - if (rq2 == RT_NULL) - { - break; - } - rq2 -= 2; - *rq2 = 0x0; -// rt_kprintf("[%s]\n", rq); - } - else - { - break; - } - - /* Copy the IP address to buffer */ - if (ip != NULL) - { - while(*rq < '0' || *rq > '9') - { - rq++; - } - rt_memcpy(ip, rq, rq2 - rq + 1); - } - netconn_delete(conn); - netbuf_delete(buf); - return RT_EOK; - } while (0); - - netconn_delete(conn); - netbuf_delete(buf); - return -RT_ERROR; + conn = netconn_new(NETCONN_TCP); + if (conn == NULL) + { + break; + } + + ret = netconn_connect(conn, &server_ip, 80); + if (ret != ERR_OK) + { + break; + } + + /* Send the query */ + ret = netconn_write(conn, query, sizeof(query) - 1, 0); + if (ret != ERR_OK) + { + break; + } + + buf = netconn_recv(conn); + if (buf != NULL) + { + /* Get the response */ + ret = netbuf_data(buf, (void **)&rq, &len); + if (ret != ERR_OK) + { + break; + } + + /* Find the IP address */ + rq = rt_strstr(rq, find); + if (rq == RT_NULL) + { + break; + } + rq += 5; + rq2 = rq; + rq2 = rt_strstr(rq2, find); + if (rq2 == RT_NULL) + { + break; + } + rq2 -= 2; + *rq2 = 0x0; +// rt_kprintf("[%s]\n", rq); + } + else + { + break; + } + + /* Copy the IP address to buffer */ + if (ip != NULL) + { + while(*rq < '0' || *rq > '9') + { + rq++; + } + rt_memcpy(ip, rq, rq2 - rq + 1); + } + netconn_delete(conn); + netbuf_delete(buf); + return RT_EOK; + } while (0); + + netconn_delete(conn); + netbuf_delete(buf); + return -RT_ERROR; } void list_myip(void) { - rt_uint8_t ip[20]; + rt_uint8_t ip[20]; - if (get_ip(ip) != RT_EOK) - { - rt_kprintf("Get IP failed!\n"); - return; - } + if (get_ip(ip) != RT_EOK) + { + rt_kprintf("Get IP failed!\n"); + return; + } - rt_kprintf("Current IP: [%s]\n", ip); + rt_kprintf("Current IP: [%s]\n", ip); } FINSH_FUNCTION_EXPORT(list_myip, list the current IP address.) @@ -1202,122 +1202,122 @@ FINSH_FUNCTION_EXPORT(list_myip, list the current IP address.) rt_err_t update_ip(char *ip) { - err_t ret; - struct ip_addr server_ip; - struct netconn *conn; - struct netbuf *buf; - char *rq; - u16_t len, len2; - char query[200] = "GET /nic/update?hostname="; - const char query2[] = "&myip="; - const char query3[] = " HTTP/1.0\r\nHost: members.dyndns.org\r\nAuthorization: Basic "; - const char query4[] = "\r\nUser-Agent: onelife - EFM32 - 0.4\r\n\r\n"; - const char find[] = "good"; - - /* Make the query */ - len = rt_strlen(query); - len2 = sizeof(hostName) - 1; - rt_memcpy(&query[len], hostName, len2); - len += len2; - - len2 = sizeof(query2) - 1; - rt_memcpy(&query[len], query2, len2); - len += len2; - - len2 = rt_strlen(ip); - rt_memcpy(&query[len], ip, len2); - len += len2; - - len2 = sizeof(query3) - 1; - rt_memcpy(&query[len], query3, len2); - len += len2; - - len2 = sizeof(userPwdB64) - 1; - rt_memcpy(&query[len], userPwdB64, len2); - len += len2; - - len2 = sizeof(query4) - 1; - rt_memcpy(&query[len], query4, len2); - len += len2; - - query[len] = 0x0; -// rt_kprintf("Query: %s\n", &query[100]); - - do - { + err_t ret; + struct ip_addr server_ip; + struct netconn *conn; + struct netbuf *buf; + char *rq; + u16_t len, len2; + char query[200] = "GET /nic/update?hostname="; + const char query2[] = "&myip="; + const char query3[] = " HTTP/1.0\r\nHost: members.dyndns.org\r\nAuthorization: Basic "; + const char query4[] = "\r\nUser-Agent: onelife - EFM32 - 0.4\r\n\r\n"; + const char find[] = "good"; + + /* Make the query */ + len = rt_strlen(query); + len2 = sizeof(hostName) - 1; + rt_memcpy(&query[len], hostName, len2); + len += len2; + + len2 = sizeof(query2) - 1; + rt_memcpy(&query[len], query2, len2); + len += len2; + + len2 = rt_strlen(ip); + rt_memcpy(&query[len], ip, len2); + len += len2; + + len2 = sizeof(query3) - 1; + rt_memcpy(&query[len], query3, len2); + len += len2; + + len2 = sizeof(userPwdB64) - 1; + rt_memcpy(&query[len], userPwdB64, len2); + len += len2; + + len2 = sizeof(query4) - 1; + rt_memcpy(&query[len], query4, len2); + len += len2; + + query[len] = 0x0; +// rt_kprintf("Query: %s\n", &query[100]); + + do + { #if defined(RT_LWIP_DNS) - ret = netconn_gethostbyname("members.dyndns.org", &server_ip); - if (ret != ERR_OK) - { - break; - } + ret = netconn_gethostbyname("members.dyndns.org", &server_ip); + if (ret != ERR_OK) + { + break; + } #else - IP4_ADDR(&server_ip, 204,13,248,112); // IP address of "members.dyndns.org" + IP4_ADDR(&server_ip, 204,13,248,112); // IP address of "members.dyndns.org" #endif - conn = netconn_new(NETCONN_TCP); - if (conn == NULL) - { - break; - } - - ret = netconn_connect(conn, &server_ip, 80); - if (ret != ERR_OK) - { - break; - } - - /* Send the query */ - ret = netconn_write(conn, query, len, 0); - if (ret != ERR_OK) - { - break; - } - - /* Get the response */ - buf = netconn_recv(conn); - if (buf != NULL) - { - ret = netbuf_data(buf, (void **)&rq, &len); - if (ret != ERR_OK) - { - break; - } - - /* Find the result */ - rq = rt_strstr(rq, find); - if (rq == RT_NULL) - { - break; - } -// rt_kprintf("[%s]\n", rq); - } - else - { - break; - } - - netconn_delete(conn); - netbuf_delete(buf); - return RT_EOK; - } while (0); - - netconn_delete(conn); - netbuf_delete(buf); - return -RT_ERROR; + conn = netconn_new(NETCONN_TCP); + if (conn == NULL) + { + break; + } + + ret = netconn_connect(conn, &server_ip, 80); + if (ret != ERR_OK) + { + break; + } + + /* Send the query */ + ret = netconn_write(conn, query, len, 0); + if (ret != ERR_OK) + { + break; + } + + /* Get the response */ + buf = netconn_recv(conn); + if (buf != NULL) + { + ret = netbuf_data(buf, (void **)&rq, &len); + if (ret != ERR_OK) + { + break; + } + + /* Find the result */ + rq = rt_strstr(rq, find); + if (rq == RT_NULL) + { + break; + } +// rt_kprintf("[%s]\n", rq); + } + else + { + break; + } + + netconn_delete(conn); + netbuf_delete(buf); + return RT_EOK; + } while (0); + + netconn_delete(conn); + netbuf_delete(buf); + return -RT_ERROR; } void update_myip(char *ip) { - rt_kprintf("Update host, \"%s\", to new IP address %s: ", hostName, ip); + rt_kprintf("Update host, \"%s\", to new IP address %s: ", hostName, ip); - if (update_ip(ip) != RT_EOK) - { - rt_kprintf("failed!\n"); - return; - } + if (update_ip(ip) != RT_EOK) + { + rt_kprintf("failed!\n"); + return; + } - rt_kprintf("succeeded.\n", ip); + rt_kprintf("succeeded.\n", ip); } FINSH_FUNCTION_EXPORT(update_myip, update DDNS with specified IP address.) diff --git a/bsp/efm32/drv_ethernet.h b/bsp/efm32/drv_ethernet.h index 146182f86d..87e12493f6 100644 --- a/bsp/efm32/drv_ethernet.h +++ b/bsp/efm32/drv_ethernet.h @@ -1,11 +1,11 @@ /***************************************************************************//** - * @file drv_ethernet.h - * @brief Ethernet driver (SPI mode) of RT-Thread RTOS for using EFM32 USART + * @file drv_ethernet.h + * @brief Ethernet driver (SPI mode) of RT-Thread RTOS for using EFM32 USART * module - * This driver is tested by using the Microchip ENC28J60 stand-alone Ethernet + * This driver is tested by using the Microchip ENC28J60 stand-alone Ethernet * controller with SPI interface. * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -13,8 +13,8 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes - * 2011-06-22 onelife Initial creation for using EFM32 USART module + * Date Author Notes + * 2011-06-22 onelife Initial creation for using EFM32 USART module ******************************************************************************/ #ifndef __DEV_ETHERNET_H__ #define __DEV_ETHERNET_H__ @@ -25,18 +25,18 @@ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ -#define ETH_ADDR_LEN (6) -#define ETH_CLK_MAX (10000000) /* Should be more than 8 Mz (Errata 1) */ +#define ETH_ADDR_LEN (6) +#define ETH_CLK_MAX (10000000) /* Should be more than 8 Mz (Errata 1) */ //#define ETH_HALF_DUPLEX -#define ETH_PERIOD_WAIT_INIT (RT_TICK_PER_SECOND/100) -#define ETH_PERIOD_WAIT_TX (RT_TICK_PER_SECOND/100) -#define ETH_SPI_RX_SKIP (1) +#define ETH_PERIOD_WAIT_INIT (RT_TICK_PER_SECOND/100) +#define ETH_PERIOD_WAIT_TX (RT_TICK_PER_SECOND/100) +#define ETH_SPI_RX_SKIP (1) -#define ETH_RESET_PORT (gpioPortB) -#define ETH_RESET_PIN (9) -#define ETH_INT_PORT (gpioPortB) -#define ETH_INT_PIN (10) +#define ETH_RESET_PORT (gpioPortB) +#define ETH_RESET_PIN (9) +#define ETH_INT_PORT (gpioPortB) +#define ETH_INT_PIN (10) /* Exported functions ------------------------------------------------------- */ rt_err_t efm_hw_eth_init(void); diff --git a/bsp/efm32/drv_leuart.c b/bsp/efm32/drv_leuart.c index 23addb48a9..7422956003 100644 --- a/bsp/efm32/drv_leuart.c +++ b/bsp/efm32/drv_leuart.c @@ -1,8 +1,8 @@ /***************************************************************************//** - * @file drv_leuart.c - * @brief LEUART driver of RT-Thread RTOS for EFM32 + * @file drv_leuart.c + * @brief LEUART driver of RT-Thread RTOS for EFM32 * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -10,9 +10,9 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes - * 2011-12-09 onelife Initial creation for EFM32 - * 2011-12-27 onelife Utilize "LEUART_PRESENT" and "LEUART_COUNT" + * Date Author Notes + * 2011-12-09 onelife Initial creation for EFM32 + * 2011-12-27 onelife Utilize "LEUART_PRESENT" and "LEUART_COUNT" ******************************************************************************/ /***************************************************************************//** @@ -41,10 +41,10 @@ /* Private variables ---------------------------------------------------------*/ #if defined(RT_USING_LEUART0) #if (RT_USING_LEUART0 >= EFM32_LEUART_LOCATION_COUNT) - #error "Wrong location number" + #error "Wrong location number" #endif - struct rt_device leuart0_device; - static struct rt_semaphore leuart0_lock; + struct rt_device leuart0_device; + static struct rt_semaphore leuart0_lock; #endif #if defined(RT_USING_LEUART1) @@ -52,10 +52,10 @@ #error "Wrong unit number" #endif #if (RT_USING_LEUART1 >= EFM32_LEUART_LOCATION_COUNT) - #error "Wrong location number" + #error "Wrong location number" #endif - struct rt_device leuart1_device; - static struct rt_semaphore leuart1_lock; + struct rt_device leuart1_device; + static struct rt_semaphore leuart1_lock; #endif /* Private function prototypes -----------------------------------------------*/ @@ -76,37 +76,37 @@ ******************************************************************************/ static rt_err_t rt_leuart_init (rt_device_t dev) { - struct efm32_leuart_device_t *leuart; + struct efm32_leuart_device_t *leuart; - leuart = (struct efm32_leuart_device_t *)(dev->user_data); + leuart = (struct efm32_leuart_device_t *)(dev->user_data); - if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) - { - if (dev->flag & RT_DEVICE_FLAG_DMA_TX) - { - struct efm32_leuart_dma_mode_t *dma_tx; + if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) + { + if (dev->flag & RT_DEVICE_FLAG_DMA_TX) + { + struct efm32_leuart_dma_mode_t *dma_tx; - dma_tx = (struct efm32_leuart_dma_mode_t *)(leuart->tx_mode); + dma_tx = (struct efm32_leuart_dma_mode_t *)(leuart->tx_mode); - leuart->state |= LEUART_STATE_RX_BUSY; - } + leuart->state |= LEUART_STATE_RX_BUSY; + } - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - struct efm32_leuart_int_mode_t *int_rx; + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + struct efm32_leuart_int_mode_t *int_rx; - int_rx = (struct efm32_leuart_int_mode_t *)(leuart->rx_mode); + int_rx = (struct efm32_leuart_int_mode_t *)(leuart->rx_mode); - int_rx->data_ptr = RT_NULL; - } + int_rx->data_ptr = RT_NULL; + } - /* Enable LEUART */ - LEUART_Enable(leuart->leuart_device, leuartEnable); + /* Enable LEUART */ + LEUART_Enable(leuart->leuart_device, leuartEnable); - dev->flag |= RT_DEVICE_FLAG_ACTIVATED; - } + dev->flag |= RT_DEVICE_FLAG_ACTIVATED; + } - return RT_EOK; + return RT_EOK; } /***************************************************************************//** @@ -128,68 +128,68 @@ static rt_err_t rt_leuart_init (rt_device_t dev) ******************************************************************************/ static rt_err_t rt_leuart_open(rt_device_t dev, rt_uint16_t oflag) { - RT_ASSERT(dev != RT_NULL); + RT_ASSERT(dev != RT_NULL); - struct efm32_leuart_device_t *leuart; + struct efm32_leuart_device_t *leuart; - leuart = (struct efm32_leuart_device_t *)(dev->user_data); + leuart = (struct efm32_leuart_device_t *)(dev->user_data); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - IRQn_Type rxIrq; + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + IRQn_Type rxIrq; - //if (leuart->state & LEUART_STATE_CONSOLE) - { /* Allocate new RX buffer */ - struct efm32_leuart_int_mode_t *int_mode; + //if (leuart->state & LEUART_STATE_CONSOLE) + { /* Allocate new RX buffer */ + struct efm32_leuart_int_mode_t *int_mode; - int_mode = (struct efm32_leuart_int_mode_t *)(leuart->rx_mode); + int_mode = (struct efm32_leuart_int_mode_t *)(leuart->rx_mode); - if ((int_mode->data_ptr = rt_malloc(LEUART_RX_BUFFER_SIZE)) == RT_NULL) - { - leuart_debug("LEUART%d err: no mem for RX BUF\n", leuart->unit); - return -RT_ENOMEM; - } - rt_memset(int_mode->data_ptr, 0, LEUART_RX_BUFFER_SIZE); - int_mode->data_size = LEUART_RX_BUFFER_SIZE; - int_mode->read_index = 0; - int_mode->save_index = 0; - } + if ((int_mode->data_ptr = rt_malloc(LEUART_RX_BUFFER_SIZE)) == RT_NULL) + { + leuart_debug("LEUART%d err: no mem for RX BUF\n", leuart->unit); + return -RT_ENOMEM; + } + rt_memset(int_mode->data_ptr, 0, LEUART_RX_BUFFER_SIZE); + int_mode->data_size = LEUART_RX_BUFFER_SIZE; + int_mode->read_index = 0; + int_mode->save_index = 0; + } - /* Enable RX interrupt */ - leuart->leuart_device->IEN = LEUART_IEN_RXDATAV; + /* Enable RX interrupt */ + leuart->leuart_device->IEN = LEUART_IEN_RXDATAV; - /* Enable IRQ */ - switch (leuart->unit) - { - case 0: + /* Enable IRQ */ + switch (leuart->unit) + { + case 0: rxIrq = LEUART0_IRQn; - break; + break; #if (LEUART_COUNT > 1) - case 1: + case 1: rxIrq = LEUART1_IRQn; - break; + break; #endif } - if (oflag != RT_DEVICE_OFLAG_WRONLY) - { - NVIC_ClearPendingIRQ(rxIrq); - NVIC_SetPriority(rxIrq, EFM32_IRQ_PRI_DEFAULT); - NVIC_EnableIRQ(rxIrq); - } - } + if (oflag != RT_DEVICE_OFLAG_WRONLY) + { + NVIC_ClearPendingIRQ(rxIrq); + NVIC_SetPriority(rxIrq, EFM32_IRQ_PRI_DEFAULT); + NVIC_EnableIRQ(rxIrq); + } + } /* Clear Flag */ leuart->leuart_device->IFC = _LEUART_IFC_MASK; - if ((dev->flag & RT_DEVICE_FLAG_DMA_TX) && (oflag != RT_DEVICE_OFLAG_RDONLY)) - { - /* DMA IRQ is enabled by DMA_Init() */ - NVIC_SetPriority(DMA_IRQn, EFM32_IRQ_PRI_DEFAULT); - } + if ((dev->flag & RT_DEVICE_FLAG_DMA_TX) && (oflag != RT_DEVICE_OFLAG_RDONLY)) + { + /* DMA IRQ is enabled by DMA_Init() */ + NVIC_SetPriority(DMA_IRQn, EFM32_IRQ_PRI_DEFAULT); + } - leuart->counter++; - leuart_debug("LEUART%d: Open with flag %x\n", leuart->unit, oflag); - return RT_EOK; + leuart->counter++; + leuart_debug("LEUART%d: Open with flag %x\n", leuart->unit, oflag); + return RT_EOK; } /***************************************************************************//** @@ -208,26 +208,26 @@ static rt_err_t rt_leuart_open(rt_device_t dev, rt_uint16_t oflag) ******************************************************************************/ static rt_err_t rt_leuart_close(rt_device_t dev) { - RT_ASSERT(dev != RT_NULL); + RT_ASSERT(dev != RT_NULL); - struct efm32_leuart_device_t *leuart; + struct efm32_leuart_device_t *leuart; - leuart = (struct efm32_leuart_device_t *)(dev->user_data); + leuart = (struct efm32_leuart_device_t *)(dev->user_data); - if (--leuart->counter == 0) - { - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - struct efm32_leuart_int_mode_t *int_rx; + if (--leuart->counter == 0) + { + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + struct efm32_leuart_int_mode_t *int_rx; - int_rx = (struct efm32_leuart_int_mode_t *)leuart->rx_mode; + int_rx = (struct efm32_leuart_int_mode_t *)leuart->rx_mode; - rt_free(int_rx->data_ptr); - int_rx->data_ptr = RT_NULL; - } - } + rt_free(int_rx->data_ptr); + int_rx->data_ptr = RT_NULL; + } + } - return RT_EOK; + return RT_EOK; } /***************************************************************************//** @@ -254,105 +254,105 @@ static rt_err_t rt_leuart_close(rt_device_t dev) * Number of read bytes ******************************************************************************/ static rt_size_t rt_leuart_read ( - rt_device_t dev, - rt_off_t pos, - void *buffer, - rt_size_t size) + rt_device_t dev, + rt_off_t pos, + void *buffer, + rt_size_t size) { - struct efm32_leuart_device_t *leuart; - rt_uint8_t *ptr; - rt_err_t err_code; - rt_size_t read_len; - - leuart = (struct efm32_leuart_device_t *)(dev->user_data); - - /* Lock device */ - if (rt_hw_interrupt_check()) - { - err_code = rt_sem_take(leuart->lock, RT_WAITING_NO); - } - else - { - err_code = rt_sem_take(leuart->lock, RT_WAITING_FOREVER); - } - if (err_code != RT_EOK) - { - rt_set_errno(err_code); - return 0; - } - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - ptr = buffer; - - /* interrupt mode Rx */ - while (size) - { - rt_base_t level; - struct efm32_leuart_int_mode_t *int_rx; - - int_rx = (struct efm32_leuart_int_mode_t *)\ - (((struct efm32_leuart_device_t *)(dev->user_data))->rx_mode); - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - if (int_rx->read_index != int_rx->save_index) - { - /* read a character */ - *ptr++ = int_rx->data_ptr[int_rx->read_index]; - size--; - - /* move to next position */ - int_rx->read_index ++; - if (int_rx->read_index >= LEUART_RX_BUFFER_SIZE) - { - int_rx->read_index = 0; - } - } - else - { - /* set error code */ - err_code = -RT_EEMPTY; - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - break; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } - - read_len = (rt_uint32_t)ptr - (rt_uint32_t)buffer; - } - else - { - LEUART_TypeDef *leuart_device; - - leuart = (struct efm32_leuart_device_t *)(dev->user_data); - leuart_device = ((struct efm32_leuart_device_t *)(dev->user_data))->leuart_device; - ptr = buffer; - - /* polling mode */ - while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) - { - while (leuart_device->STATUS & LEUART_STATUS_RXDATAV) - { - *ptr = leuart_device->RXDATA & 0xff; - ptr ++; - } - } - - read_len = size; - } - - /* Unlock device */ - rt_sem_release(leuart->lock); - - /* set error code */ - rt_set_errno(err_code); - return read_len; + struct efm32_leuart_device_t *leuart; + rt_uint8_t *ptr; + rt_err_t err_code; + rt_size_t read_len; + + leuart = (struct efm32_leuart_device_t *)(dev->user_data); + + /* Lock device */ + if (rt_hw_interrupt_check()) + { + err_code = rt_sem_take(leuart->lock, RT_WAITING_NO); + } + else + { + err_code = rt_sem_take(leuart->lock, RT_WAITING_FOREVER); + } + if (err_code != RT_EOK) + { + rt_set_errno(err_code); + return 0; + } + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + ptr = buffer; + + /* interrupt mode Rx */ + while (size) + { + rt_base_t level; + struct efm32_leuart_int_mode_t *int_rx; + + int_rx = (struct efm32_leuart_int_mode_t *)\ + (((struct efm32_leuart_device_t *)(dev->user_data))->rx_mode); + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + if (int_rx->read_index != int_rx->save_index) + { + /* read a character */ + *ptr++ = int_rx->data_ptr[int_rx->read_index]; + size--; + + /* move to next position */ + int_rx->read_index ++; + if (int_rx->read_index >= LEUART_RX_BUFFER_SIZE) + { + int_rx->read_index = 0; + } + } + else + { + /* set error code */ + err_code = -RT_EEMPTY; + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + + read_len = (rt_uint32_t)ptr - (rt_uint32_t)buffer; + } + else + { + LEUART_TypeDef *leuart_device; + + leuart = (struct efm32_leuart_device_t *)(dev->user_data); + leuart_device = ((struct efm32_leuart_device_t *)(dev->user_data))->leuart_device; + ptr = buffer; + + /* polling mode */ + while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) + { + while (leuart_device->STATUS & LEUART_STATUS_RXDATAV) + { + *ptr = leuart_device->RXDATA & 0xff; + ptr ++; + } + } + + read_len = size; + } + + /* Unlock device */ + rt_sem_release(leuart->lock); + + /* set error code */ + rt_set_errno(err_code); + return read_len; } /***************************************************************************//** @@ -379,504 +379,504 @@ static rt_size_t rt_leuart_read ( * Number of written bytes ******************************************************************************/ static rt_size_t rt_leuart_write ( - rt_device_t dev, - rt_off_t pos, - const void* buffer, - rt_size_t size) + rt_device_t dev, + rt_off_t pos, + const void* buffer, + rt_size_t size) { - rt_err_t err_code; - rt_size_t write_size; - struct efm32_leuart_device_t* leuart; - - write_size = 0; - leuart = (struct efm32_leuart_device_t*)(dev->user_data); - - /* Lock device */ - if (rt_hw_interrupt_check()) - { - err_code = rt_sem_take(leuart->lock, RT_WAITING_NO); - } - else - { - err_code = rt_sem_take(leuart->lock, RT_WAITING_FOREVER); - } - if (err_code != RT_EOK) - { - rt_set_errno(err_code); - return 0; - } - - if ((dev->flag & RT_DEVICE_FLAG_DMA_TX) && (size > 2)) - { /* DMA mode Tx */ - struct efm32_leuart_dma_mode_t *dma_tx; - - if (dev->flag & RT_DEVICE_FLAG_STREAM) - { - if (*((rt_uint8_t *)buffer + size - 1) == '\n') - { - *((rt_uint8_t *)buffer + size - 1) = '\r'; - *((rt_uint8_t *)buffer + size++) = '\n'; - *((rt_uint8_t *)buffer + size) = 0; - } - } - - dma_tx = (struct efm32_leuart_dma_mode_t *)(leuart->tx_mode); - dma_tx->data_ptr = (rt_uint32_t *)buffer; - dma_tx->data_size = size; - - leuart->state |= LEUART_STATE_TX_BUSY; - - DMA_ActivateBasic( - dma_tx->dma_channel, - true, - false, - (void *)&(leuart->leuart_device->TXDATA), - (void *)buffer, - (rt_uint32_t)(size - 1)); - - /* Wait, otherwise the TX buffer is overwrite */ -// if (leuart->state & LEUART_STATE_CONSOLE) -// { - while(leuart->state & LEUART_STATE_TX_BUSY); -// } -// else -// { -// while(leuart->state & LEUART_STATE_TX_BUSY) -// { -// rt_thread_sleep(LEUART_WAIT_TIME_TX); -// } -// } + rt_err_t err_code; + rt_size_t write_size; + struct efm32_leuart_device_t* leuart; + + write_size = 0; + leuart = (struct efm32_leuart_device_t*)(dev->user_data); + + /* Lock device */ + if (rt_hw_interrupt_check()) + { + err_code = rt_sem_take(leuart->lock, RT_WAITING_NO); + } + else + { + err_code = rt_sem_take(leuart->lock, RT_WAITING_FOREVER); + } + if (err_code != RT_EOK) + { + rt_set_errno(err_code); + return 0; + } + + if ((dev->flag & RT_DEVICE_FLAG_DMA_TX) && (size > 2)) + { /* DMA mode Tx */ + struct efm32_leuart_dma_mode_t *dma_tx; + + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + if (*((rt_uint8_t *)buffer + size - 1) == '\n') + { + *((rt_uint8_t *)buffer + size - 1) = '\r'; + *((rt_uint8_t *)buffer + size++) = '\n'; + *((rt_uint8_t *)buffer + size) = 0; + } + } + + dma_tx = (struct efm32_leuart_dma_mode_t *)(leuart->tx_mode); + dma_tx->data_ptr = (rt_uint32_t *)buffer; + dma_tx->data_size = size; + + leuart->state |= LEUART_STATE_TX_BUSY; + + DMA_ActivateBasic( + dma_tx->dma_channel, + true, + false, + (void *)&(leuart->leuart_device->TXDATA), + (void *)buffer, + (rt_uint32_t)(size - 1)); + + /* Wait, otherwise the TX buffer is overwrite */ +// if (leuart->state & LEUART_STATE_CONSOLE) +// { + while(leuart->state & LEUART_STATE_TX_BUSY); +// } +// else +// { +// while(leuart->state & LEUART_STATE_TX_BUSY) +// { +// rt_thread_sleep(LEUART_WAIT_TIME_TX); +// } +// } // TODO: This function blocks the process - write_size = size; - } - else - { /* polling mode */ - rt_uint8_t *ptr = (rt_uint8_t *)buffer; - - if (dev->flag & RT_DEVICE_FLAG_STREAM) - { - /* stream mode */ - while (size) - { - if (*ptr == '\n') - { - while (!(leuart->leuart_device->STATUS & LEUART_STATUS_TXBL)); - leuart->leuart_device->TXDATA = '\r'; - } - - while (!(leuart->leuart_device->STATUS & LEUART_STATUS_TXBL)); - leuart->leuart_device->TXDATA = (rt_uint32_t)*ptr; - ++ptr; --size; - } - } - else - { - /* write data directly */ - while (size) - { - while (!(leuart->leuart_device->STATUS & LEUART_STATUS_TXBL)); - leuart->leuart_device->TXDATA = (rt_uint32_t)*ptr; - ++ptr; --size; - } - } - - write_size = (rt_size_t)ptr - (rt_size_t)buffer; - } - - /* Unlock device */ - rt_sem_release(leuart->lock); - - /* set error code */ - rt_set_errno(err_code); - return write_size; + write_size = size; + } + else + { /* polling mode */ + rt_uint8_t *ptr = (rt_uint8_t *)buffer; + + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* stream mode */ + while (size) + { + if (*ptr == '\n') + { + while (!(leuart->leuart_device->STATUS & LEUART_STATUS_TXBL)); + leuart->leuart_device->TXDATA = '\r'; + } + + while (!(leuart->leuart_device->STATUS & LEUART_STATUS_TXBL)); + leuart->leuart_device->TXDATA = (rt_uint32_t)*ptr; + ++ptr; --size; + } + } + else + { + /* write data directly */ + while (size) + { + while (!(leuart->leuart_device->STATUS & LEUART_STATUS_TXBL)); + leuart->leuart_device->TXDATA = (rt_uint32_t)*ptr; + ++ptr; --size; + } + } + + write_size = (rt_size_t)ptr - (rt_size_t)buffer; + } + + /* Unlock device */ + rt_sem_release(leuart->lock); + + /* set error code */ + rt_set_errno(err_code); + return write_size; } /***************************************************************************//** * @brief -* Configure LEUART device +* Configure LEUART device * * @details * * @note * * @param[in] dev -* Pointer to device descriptor +* Pointer to device descriptor * * @param[in] cmd -* IIC control command +* IIC control command * * @param[in] args -* Arguments +* Arguments * * @return -* Error code +* Error code ******************************************************************************/ static rt_err_t rt_leuart_control ( - rt_device_t dev, - rt_uint8_t cmd, - void *args) + rt_device_t dev, + rt_uint8_t cmd, + void *args) { - RT_ASSERT(dev != RT_NULL); - - rt_err_t err_code; - struct efm32_leuart_device_t *leuart; - - leuart = (struct efm32_leuart_device_t *)(dev->user_data); - - /* Lock device */ - if (rt_hw_interrupt_check()) - { - err_code = rt_sem_take(leuart->lock, RT_WAITING_NO); - } - else - { - err_code = rt_sem_take(leuart->lock, RT_WAITING_FOREVER); - } - if (err_code != RT_EOK) - { - return err_code; - } - - switch (cmd) - { - case RT_DEVICE_CTRL_SUSPEND: - /* Suspend device */ - dev->flag |= RT_DEVICE_FLAG_SUSPENDED; - LEUART_Enable(leuart->leuart_device, leuartDisable); - break; - - case RT_DEVICE_CTRL_RESUME: - /* Resume device */ - dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; - LEUART_Enable(leuart->leuart_device, leuartEnable); - break; - - case RT_DEVICE_CTRL_LEUART_RBUFFER: - /* Set RX buffer */ - { - struct efm32_leuart_int_mode_t *int_rx; - rt_uint8_t size; - - int_rx = (struct efm32_leuart_int_mode_t *)(leuart->rx_mode); - size = (rt_uint8_t)((rt_uint32_t)args & 0xFFUL); - - /* Free previous RX buffer */ - if (int_rx->data_ptr != RT_NULL) - { - if (size == 0) - { /* Free RX buffer */ - rt_free(int_rx->data_ptr); - int_rx->data_ptr = RT_NULL; - } - else if (size != int_rx->data_size) - { - /* Re-allocate RX buffer */ - if ((int_rx->data_ptr = rt_realloc(int_rx->data_ptr, size)) \ - == RT_NULL) - { - leuart_debug("LEUART%d err: no mem for RX BUF\n", leuart->unit); - err_code = -RT_ENOMEM; - break; - } - // TODO: Is the following line necessary? - //rt_memset(int_rx->data_ptr, 0, size); - } - } - else - { - /* Allocate new RX buffer */ - if ((int_rx->data_ptr = rt_malloc(size)) == RT_NULL) - { - leuart_debug("LEUART%d err: no mem for RX BUF\n", leuart->unit); - err_code = -RT_ENOMEM; - break; - } - } - int_rx->data_size = size; - int_rx->read_index = 0; - int_rx->save_index = 0; - } - break; - - } - - /* Unlock device */ - rt_sem_release(leuart->lock); - - return err_code; + RT_ASSERT(dev != RT_NULL); + + rt_err_t err_code; + struct efm32_leuart_device_t *leuart; + + leuart = (struct efm32_leuart_device_t *)(dev->user_data); + + /* Lock device */ + if (rt_hw_interrupt_check()) + { + err_code = rt_sem_take(leuart->lock, RT_WAITING_NO); + } + else + { + err_code = rt_sem_take(leuart->lock, RT_WAITING_FOREVER); + } + if (err_code != RT_EOK) + { + return err_code; + } + + switch (cmd) + { + case RT_DEVICE_CTRL_SUSPEND: + /* Suspend device */ + dev->flag |= RT_DEVICE_FLAG_SUSPENDED; + LEUART_Enable(leuart->leuart_device, leuartDisable); + break; + + case RT_DEVICE_CTRL_RESUME: + /* Resume device */ + dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; + LEUART_Enable(leuart->leuart_device, leuartEnable); + break; + + case RT_DEVICE_CTRL_LEUART_RBUFFER: + /* Set RX buffer */ + { + struct efm32_leuart_int_mode_t *int_rx; + rt_uint8_t size; + + int_rx = (struct efm32_leuart_int_mode_t *)(leuart->rx_mode); + size = (rt_uint8_t)((rt_uint32_t)args & 0xFFUL); + + /* Free previous RX buffer */ + if (int_rx->data_ptr != RT_NULL) + { + if (size == 0) + { /* Free RX buffer */ + rt_free(int_rx->data_ptr); + int_rx->data_ptr = RT_NULL; + } + else if (size != int_rx->data_size) + { + /* Re-allocate RX buffer */ + if ((int_rx->data_ptr = rt_realloc(int_rx->data_ptr, size)) \ + == RT_NULL) + { + leuart_debug("LEUART%d err: no mem for RX BUF\n", leuart->unit); + err_code = -RT_ENOMEM; + break; + } + // TODO: Is the following line necessary? + //rt_memset(int_rx->data_ptr, 0, size); + } + } + else + { + /* Allocate new RX buffer */ + if ((int_rx->data_ptr = rt_malloc(size)) == RT_NULL) + { + leuart_debug("LEUART%d err: no mem for RX BUF\n", leuart->unit); + err_code = -RT_ENOMEM; + break; + } + } + int_rx->data_size = size; + int_rx->read_index = 0; + int_rx->save_index = 0; + } + break; + + } + + /* Unlock device */ + rt_sem_release(leuart->lock); + + return err_code; } /***************************************************************************//** * @brief - * LEUART RX data valid interrupt handler + * LEUART RX data valid interrupt handler * * @details * * @note * * @param[in] dev - * Pointer to device descriptor + * Pointer to device descriptor ******************************************************************************/ void rt_hw_leuart_rx_isr(rt_device_t dev) { - struct efm32_leuart_device_t *leuart; - struct efm32_leuart_int_mode_t *int_rx; + struct efm32_leuart_device_t *leuart; + struct efm32_leuart_int_mode_t *int_rx; rt_uint32_t flag; - /* interrupt mode receive */ - RT_ASSERT(dev->flag & RT_DEVICE_FLAG_INT_RX); - - leuart = (struct efm32_leuart_device_t *)(dev->user_data); - int_rx = (struct efm32_leuart_int_mode_t *)(leuart->rx_mode); - - RT_ASSERT(int_rx->data_ptr != RT_NULL); - - /* Set status */ - leuart->state |= LEUART_STATE_RX_BUSY; - - /* save into rx buffer */ - while (leuart->leuart_device->STATUS & LEUART_STATUS_RXDATAV) - { - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - /* save character */ - int_rx->data_ptr[int_rx->save_index] = \ - (rt_uint8_t)(leuart->leuart_device->RXDATA & 0xFFUL); - int_rx->save_index ++; - if (int_rx->save_index >= LEUART_RX_BUFFER_SIZE) - int_rx->save_index = 0; - - /* if the next position is read index, discard this 'read char' */ - if (int_rx->save_index == int_rx->read_index) - { - int_rx->read_index ++; - if (int_rx->read_index >= LEUART_RX_BUFFER_SIZE) - { - int_rx->read_index = 0; - } - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } - - /* invoke callback */ - if (dev->rx_indicate != RT_NULL) - { - rt_size_t rx_length; - - /* get rx length */ - rx_length = int_rx->read_index > int_rx->save_index ? - LEUART_RX_BUFFER_SIZE - int_rx->read_index + int_rx->save_index : \ - int_rx->save_index - int_rx->read_index; - - dev->rx_indicate(dev, rx_length); - } + /* interrupt mode receive */ + RT_ASSERT(dev->flag & RT_DEVICE_FLAG_INT_RX); + + leuart = (struct efm32_leuart_device_t *)(dev->user_data); + int_rx = (struct efm32_leuart_int_mode_t *)(leuart->rx_mode); + + RT_ASSERT(int_rx->data_ptr != RT_NULL); + + /* Set status */ + leuart->state |= LEUART_STATE_RX_BUSY; + + /* save into rx buffer */ + while (leuart->leuart_device->STATUS & LEUART_STATUS_RXDATAV) + { + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + /* save character */ + int_rx->data_ptr[int_rx->save_index] = \ + (rt_uint8_t)(leuart->leuart_device->RXDATA & 0xFFUL); + int_rx->save_index ++; + if (int_rx->save_index >= LEUART_RX_BUFFER_SIZE) + int_rx->save_index = 0; + + /* if the next position is read index, discard this 'read char' */ + if (int_rx->save_index == int_rx->read_index) + { + int_rx->read_index ++; + if (int_rx->read_index >= LEUART_RX_BUFFER_SIZE) + { + int_rx->read_index = 0; + } + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + + /* invoke callback */ + if (dev->rx_indicate != RT_NULL) + { + rt_size_t rx_length; + + /* get rx length */ + rx_length = int_rx->read_index > int_rx->save_index ? + LEUART_RX_BUFFER_SIZE - int_rx->read_index + int_rx->save_index : \ + int_rx->save_index - int_rx->read_index; + + dev->rx_indicate(dev, rx_length); + } } /***************************************************************************//** * @brief - * DMA for LEUART TX interrupt handler + * DMA for LEUART TX interrupt handler * * @details * * @note * * @param[in] dev - * Pointer to device descriptor + * Pointer to device descriptor ******************************************************************************/ void rt_hw_leuart_dma_tx_isr(rt_device_t dev) { - /* DMA mode receive */ - struct efm32_leuart_device_t *leuart; - struct efm32_leuart_dma_mode_t *dma_tx; + /* DMA mode receive */ + struct efm32_leuart_device_t *leuart; + struct efm32_leuart_dma_mode_t *dma_tx; - RT_ASSERT(dev->flag & RT_DEVICE_FLAG_DMA_TX); + RT_ASSERT(dev->flag & RT_DEVICE_FLAG_DMA_TX); - leuart = (struct efm32_leuart_device_t *)(dev->user_data); - dma_tx = (struct efm32_leuart_dma_mode_t *)(leuart->tx_mode); + leuart = (struct efm32_leuart_device_t *)(dev->user_data); + dma_tx = (struct efm32_leuart_dma_mode_t *)(leuart->tx_mode); - /* invoke call to notify tx complete */ - if (dev->tx_complete != RT_NULL) - { - dev->tx_complete(dev, dma_tx->data_ptr); - } + /* invoke call to notify tx complete */ + if (dev->tx_complete != RT_NULL) + { + dev->tx_complete(dev, dma_tx->data_ptr); + } - /* Set status */ - leuart->state &= ~(rt_uint32_t)LEUART_STATE_TX_BUSY; + /* Set status */ + leuart->state &= ~(rt_uint32_t)LEUART_STATE_TX_BUSY; } /***************************************************************************//** * @brief -* Register LEUART device +* Register LEUART device * * @details * * @note * * @param[in] device -* Pointer to device descriptor +* Pointer to device descriptor * * @param[in] name -* Device name +* Device name * * @param[in] flag -* Configuration flags +* Configuration flags * * @param[in] leuart -* Pointer to LEUART device descriptor +* Pointer to LEUART device descriptor * * @return -* Error code +* Error code ******************************************************************************/ rt_err_t rt_hw_leuart_register( - rt_device_t device, - const char *name, - rt_uint32_t flag, - struct efm32_leuart_device_t *leuart) + rt_device_t device, + const char *name, + rt_uint32_t flag, + struct efm32_leuart_device_t *leuart) { - RT_ASSERT(device != RT_NULL); - - if ((flag & RT_DEVICE_FLAG_DMA_RX) || - (flag & RT_DEVICE_FLAG_INT_TX)) - { - RT_ASSERT(0); - } - - device->type = RT_Device_Class_Char; - device->rx_indicate = RT_NULL; - device->tx_complete = RT_NULL; - device->init = rt_leuart_init; - device->open = rt_leuart_open; - device->close = rt_leuart_close; - device->read = rt_leuart_read; - device->write = rt_leuart_write; - device->control = rt_leuart_control; - device->user_data = leuart; - - /* register a character device */ - return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); + RT_ASSERT(device != RT_NULL); + + if ((flag & RT_DEVICE_FLAG_DMA_RX) || + (flag & RT_DEVICE_FLAG_INT_TX)) + { + RT_ASSERT(0); + } + + device->type = RT_Device_Class_Char; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->init = rt_leuart_init; + device->open = rt_leuart_open; + device->close = rt_leuart_close; + device->read = rt_leuart_read; + device->write = rt_leuart_write; + device->control = rt_leuart_control; + device->user_data = leuart; + + /* register a character device */ + return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); } /***************************************************************************//** * @brief -* Initialize the specified LEUART unit +* Initialize the specified LEUART unit * * @details * * @note * * @param[in] device -* Pointer to device descriptor +* Pointer to device descriptor * * @param[in] unitNumber -* Unit number +* Unit number * * @param[in] location -* Pin location number +* Pin location number * * @param[in] flag -* Configuration flag +* Configuration flag * * @param[in] dmaChannel -* DMA channel number for TX +* DMA channel number for TX * * @param[in] console -* Indicate if using as console +* Indicate if using as console * * @return -* Pointer to LEUART device +* Pointer to LEUART device ******************************************************************************/ static struct efm32_leuart_device_t *rt_hw_leuart_unit_init( - rt_device_t device, - rt_uint8_t unitNumber, - rt_uint8_t location, - rt_uint32_t flag, - rt_uint32_t dmaChannel, - rt_uint8_t config) + rt_device_t device, + rt_uint8_t unitNumber, + rt_uint8_t location, + rt_uint32_t flag, + rt_uint32_t dmaChannel, + rt_uint8_t config) { - struct efm32_leuart_device_t *leuart; - struct efm32_leuart_dma_mode_t *dma_mode; - DMA_CB_TypeDef *callback; - CMU_Clock_TypeDef leuartClock; - rt_uint32_t txDmaSelect; - GPIO_Port_TypeDef port_tx, port_rx, port_clk, port_cs; - rt_uint32_t pin_tx, pin_rx, pin_clk, pin_cs; + struct efm32_leuart_device_t *leuart; + struct efm32_leuart_dma_mode_t *dma_mode; + DMA_CB_TypeDef *callback; + CMU_Clock_TypeDef leuartClock; + rt_uint32_t txDmaSelect; + GPIO_Port_TypeDef port_tx, port_rx, port_clk, port_cs; + rt_uint32_t pin_tx, pin_rx, pin_clk, pin_cs; LEUART_Init_TypeDef init = LEUART_INIT_DEFAULT; - efm32_irq_hook_init_t hook; - - do - { - /* Allocate device */ - leuart = rt_malloc(sizeof(struct efm32_leuart_device_t)); - if (leuart == RT_NULL) - { - leuart_debug("LEUART%d err: no mem\n", unitNumber); - break; - } - leuart->counter = 0; - leuart->unit = unitNumber; - leuart->state = config; - leuart->tx_mode = RT_NULL; - leuart->rx_mode = RT_NULL; - - /* Allocate TX */ - dma_mode = RT_NULL; - if (flag & RT_DEVICE_FLAG_DMA_TX) - { - leuart->tx_mode = dma_mode = rt_malloc(sizeof(struct efm32_leuart_dma_mode_t)); - if (dma_mode == RT_NULL) - { - leuart_debug("LEUART%d err: no mem for DMA TX\n", unitNumber); - break; - } - dma_mode->dma_channel = dmaChannel; - } - - /* Allocate RX */ - if (flag & RT_DEVICE_FLAG_INT_RX) - { - leuart->rx_mode = rt_malloc(sizeof(struct efm32_leuart_int_mode_t)); - if (leuart->rx_mode == RT_NULL) - { - leuart_debug("LEUART%d err: no mem for INT RX\n, unitNumber"); - break; - } - } - - /* Initialization */ - if (unitNumber >= LEUART_COUNT) - { - break; - } - switch (unitNumber) - { - case 0: - leuart->leuart_device = LEUART0; - leuartClock = (CMU_Clock_TypeDef)cmuClock_LEUART0; - txDmaSelect = DMAREQ_LEUART0_TXBL; - port_tx = AF_LEUART0_TX_PORT(location); - pin_tx = AF_LEUART0_TX_PIN(location); - port_rx = AF_LEUART0_RX_PORT(location); - pin_rx = AF_LEUART0_RX_PIN(location); - break; + efm32_irq_hook_init_t hook; + + do + { + /* Allocate device */ + leuart = rt_malloc(sizeof(struct efm32_leuart_device_t)); + if (leuart == RT_NULL) + { + leuart_debug("LEUART%d err: no mem\n", unitNumber); + break; + } + leuart->counter = 0; + leuart->unit = unitNumber; + leuart->state = config; + leuart->tx_mode = RT_NULL; + leuart->rx_mode = RT_NULL; + + /* Allocate TX */ + dma_mode = RT_NULL; + if (flag & RT_DEVICE_FLAG_DMA_TX) + { + leuart->tx_mode = dma_mode = rt_malloc(sizeof(struct efm32_leuart_dma_mode_t)); + if (dma_mode == RT_NULL) + { + leuart_debug("LEUART%d err: no mem for DMA TX\n", unitNumber); + break; + } + dma_mode->dma_channel = dmaChannel; + } + + /* Allocate RX */ + if (flag & RT_DEVICE_FLAG_INT_RX) + { + leuart->rx_mode = rt_malloc(sizeof(struct efm32_leuart_int_mode_t)); + if (leuart->rx_mode == RT_NULL) + { + leuart_debug("LEUART%d err: no mem for INT RX\n, unitNumber"); + break; + } + } + + /* Initialization */ + if (unitNumber >= LEUART_COUNT) + { + break; + } + switch (unitNumber) + { + case 0: + leuart->leuart_device = LEUART0; + leuartClock = (CMU_Clock_TypeDef)cmuClock_LEUART0; + txDmaSelect = DMAREQ_LEUART0_TXBL; + port_tx = AF_LEUART0_TX_PORT(location); + pin_tx = AF_LEUART0_TX_PIN(location); + port_rx = AF_LEUART0_RX_PORT(location); + pin_rx = AF_LEUART0_RX_PIN(location); + break; #if (LEUART_COUNT > 1) - case 1: - leuart->leuart_device = LEUART1; - leuartClock = (CMU_Clock_TypeDef)cmuClock_LEUART1; - txDmaSelect = DMAREQ_LEUART1_TXBL; - port_tx = AF_LEUART1_TX_PORT(location); - pin_tx = AF_LEUART1_TX_PIN(location); - port_rx = AF_LEUART1_RX_PORT(location); - pin_rx = AF_LEUART1_RX_PIN(location); - break; + case 1: + leuart->leuart_device = LEUART1; + leuartClock = (CMU_Clock_TypeDef)cmuClock_LEUART1; + txDmaSelect = DMAREQ_LEUART1_TXBL; + port_tx = AF_LEUART1_TX_PORT(location); + pin_tx = AF_LEUART1_TX_PIN(location); + port_rx = AF_LEUART1_RX_PORT(location); + pin_rx = AF_LEUART1_RX_PIN(location); + break; #endif - default: - break; - } + default: + break; + } /* Do not prescale clock */ CMU_ClockDivSet(leuartClock, cmuClkDiv_1); @@ -884,98 +884,98 @@ static struct efm32_leuart_device_t *rt_hw_leuart_unit_init( /* Enable LEUART clock */ CMU_ClockEnable(leuartClock, true); - /* Config GPIO */ - GPIO_PinModeSet( - port_tx, - pin_tx, - gpioModePushPull, - 0); - GPIO_PinModeSet( - port_rx, - pin_rx, - gpioModeInputPull, - 1); - - /* Config interrupt and NVIC */ - if (flag & RT_DEVICE_FLAG_INT_RX) - { - hook.type = efm32_irq_type_leuart; - hook.unit = unitNumber; - hook.cbFunc = rt_hw_leuart_rx_isr; - hook.userPtr = device; - efm32_irq_hook_register(&hook); - } - - /* Config DMA */ - if (flag & RT_DEVICE_FLAG_DMA_TX) - { - DMA_CfgChannel_TypeDef chnlCfg; - DMA_CfgDescr_TypeDef descrCfg; - - hook.type = efm32_irq_type_dma; - hook.unit = dmaChannel; - hook.cbFunc = rt_hw_leuart_dma_tx_isr; - hook.userPtr = device; - efm32_irq_hook_register(&hook); - - callback = (DMA_CB_TypeDef *)rt_malloc(sizeof(DMA_CB_TypeDef)); - if (callback == RT_NULL) - { - leuart_debug("LEUART%d err: no mem for callback\n", unitNumber); - break; - } - callback->cbFunc = DMA_IRQHandler_All; - callback->userPtr = RT_NULL; - callback->primary = 0; - - /* Setting up DMA channel */ - chnlCfg.highPri = false; /* Can't use with peripherals */ - chnlCfg.enableInt = true; /* Interrupt for callback function */ - chnlCfg.select = txDmaSelect; - chnlCfg.cb = callback; - DMA_CfgChannel(dmaChannel, &chnlCfg); - - /* Setting up DMA channel descriptor */ - descrCfg.dstInc = dmaDataIncNone; - descrCfg.srcInc = dmaDataInc1; - descrCfg.size = dmaDataSize1; - descrCfg.arbRate = dmaArbitrate1; - descrCfg.hprot = 0; - DMA_CfgDescr(dmaChannel, true, &descrCfg); - } - - /* Init specified LEUART unit */ + /* Config GPIO */ + GPIO_PinModeSet( + port_tx, + pin_tx, + gpioModePushPull, + 0); + GPIO_PinModeSet( + port_rx, + pin_rx, + gpioModeInputPull, + 1); + + /* Config interrupt and NVIC */ + if (flag & RT_DEVICE_FLAG_INT_RX) + { + hook.type = efm32_irq_type_leuart; + hook.unit = unitNumber; + hook.cbFunc = rt_hw_leuart_rx_isr; + hook.userPtr = device; + efm32_irq_hook_register(&hook); + } + + /* Config DMA */ + if (flag & RT_DEVICE_FLAG_DMA_TX) + { + DMA_CfgChannel_TypeDef chnlCfg; + DMA_CfgDescr_TypeDef descrCfg; + + hook.type = efm32_irq_type_dma; + hook.unit = dmaChannel; + hook.cbFunc = rt_hw_leuart_dma_tx_isr; + hook.userPtr = device; + efm32_irq_hook_register(&hook); + + callback = (DMA_CB_TypeDef *)rt_malloc(sizeof(DMA_CB_TypeDef)); + if (callback == RT_NULL) + { + leuart_debug("LEUART%d err: no mem for callback\n", unitNumber); + break; + } + callback->cbFunc = DMA_IRQHandler_All; + callback->userPtr = RT_NULL; + callback->primary = 0; + + /* Setting up DMA channel */ + chnlCfg.highPri = false; /* Can't use with peripherals */ + chnlCfg.enableInt = true; /* Interrupt for callback function */ + chnlCfg.select = txDmaSelect; + chnlCfg.cb = callback; + DMA_CfgChannel(dmaChannel, &chnlCfg); + + /* Setting up DMA channel descriptor */ + descrCfg.dstInc = dmaDataIncNone; + descrCfg.srcInc = dmaDataInc1; + descrCfg.size = dmaDataSize1; + descrCfg.arbRate = dmaArbitrate1; + descrCfg.hprot = 0; + DMA_CfgDescr(dmaChannel, true, &descrCfg); + } + + /* Init specified LEUART unit */ LEUART_Init(leuart->leuart_device, &init); - /* Enable RX and TX pins and set location */ - leuart->leuart_device->ROUTE = LEUART_ROUTE_RXPEN | LEUART_ROUTE_TXPEN | \ - (location << _LEUART_ROUTE_LOCATION_SHIFT); - - /* Clear RX/TX buffers */ - leuart->leuart_device->CMD = LEUART_CMD_CLEARRX | LEUART_CMD_CLEARTX; - - return leuart; - } while(0); - - if (leuart->rx_mode) - { - rt_free(leuart->rx_mode); - } - if (leuart->tx_mode) - { - rt_free(leuart->tx_mode); - } - if (leuart) - { - rt_free(leuart); - } - if (callback) - { - rt_free(leuart); - } + /* Enable RX and TX pins and set location */ + leuart->leuart_device->ROUTE = LEUART_ROUTE_RXPEN | LEUART_ROUTE_TXPEN | \ + (location << _LEUART_ROUTE_LOCATION_SHIFT); + + /* Clear RX/TX buffers */ + leuart->leuart_device->CMD = LEUART_CMD_CLEARRX | LEUART_CMD_CLEARTX; + + return leuart; + } while(0); + + if (leuart->rx_mode) + { + rt_free(leuart->rx_mode); + } + if (leuart->tx_mode) + { + rt_free(leuart->tx_mode); + } + if (leuart) + { + rt_free(leuart); + } + if (callback) + { + rt_free(leuart); + } leuart_debug("LEUART%d err: init failed!\n", unitNumber); - return RT_NULL; + return RT_NULL; } /***************************************************************************//** @@ -989,12 +989,12 @@ static struct efm32_leuart_device_t *rt_hw_leuart_unit_init( ******************************************************************************/ void rt_hw_leuart_init(void) { - struct efm32_leuart_device_t *leuart; - rt_uint32_t flag; - rt_uint8_t config; + struct efm32_leuart_device_t *leuart; + rt_uint32_t flag; + rt_uint8_t config; - do - { + do + { #ifdef RT_USING_LEUART0 config = 0; flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX; @@ -1073,11 +1073,11 @@ void rt_hw_leuart_init(void) } #endif - leuart_debug("LEUART: H/W init OK!\n"); - return; - } while (0); + leuart_debug("LEUART: H/W init OK!\n"); + return; + } while (0); - rt_kprintf("LEUART: H/W init failed!\n"); + rt_kprintf("LEUART: H/W init failed!\n"); } #endif /* (defined(RT_USING_LEUART0) || defined(RT_USING_LEUART1)) */ diff --git a/bsp/efm32/drv_leuart.h b/bsp/efm32/drv_leuart.h index 692ff0d520..b7c24bb025 100644 --- a/bsp/efm32/drv_leuart.h +++ b/bsp/efm32/drv_leuart.h @@ -1,8 +1,8 @@ /***************************************************************************//** - * @file drv_leuart.h - * @brief LEUART driver of RT-Thread RTOS for EFM32 + * @file drv_leuart.h + * @brief LEUART driver of RT-Thread RTOS for EFM32 * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -10,8 +10,8 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes - * 2011-12-09 onelife Initial creation for EFM32 + * Date Author Notes + * 2011-12-09 onelife Initial creation for EFM32 ******************************************************************************/ #ifndef __DRV_LEUSART_H__ #define __DRV_LEUSART_H__ @@ -20,37 +20,37 @@ /* Exported types ------------------------------------------------------------*/ struct efm32_leuart_int_mode_t { - rt_uint8_t *data_ptr; - rt_uint8_t data_size; - rt_uint32_t read_index, save_index; + rt_uint8_t *data_ptr; + rt_uint8_t data_size; + rt_uint32_t read_index, save_index; }; struct efm32_leuart_dma_mode_t { - /* DMA Channel */ - rt_uint32_t dma_channel; + /* DMA Channel */ + rt_uint32_t dma_channel; - /* buffer info */ - rt_uint32_t *data_ptr; - rt_uint8_t data_size; + /* buffer info */ + rt_uint32_t *data_ptr; + rt_uint8_t data_size; }; struct efm32_leuart_device_t { - /* Counter */ - rt_uint32_t counter; - /* Lock */ - struct rt_semaphore *lock; - /* Unit number */ - rt_uint8_t unit; - /* State */ - volatile rt_uint8_t state; - /* Pointer to LEUART device structure */ - LEUART_TypeDef *leuart_device; - /* Pointer to RX structure */ - void *rx_mode; - /* Pointer to TX structure */ - void *tx_mode; + /* Counter */ + rt_uint32_t counter; + /* Lock */ + struct rt_semaphore *lock; + /* Unit number */ + rt_uint8_t unit; + /* State */ + volatile rt_uint8_t state; + /* Pointer to LEUART device structure */ + LEUART_TypeDef *leuart_device; + /* Pointer to RX structure */ + void *rx_mode; + /* Pointer to TX structure */ + void *tx_mode; }; /* Exported constants --------------------------------------------------------*/ diff --git a/bsp/efm32/drv_rtc.c b/bsp/efm32/drv_rtc.c index 16604a3919..75713fe3b4 100644 --- a/bsp/efm32/drv_rtc.c +++ b/bsp/efm32/drv_rtc.c @@ -10,7 +10,7 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes + * Date Author Notes * 2009-01-05 Bernard the first version * 2010-12-27 onelife Modify for EFM32 * 2011-06-16 onelife Modify init function for efm32lib v2 upgrading @@ -33,7 +33,7 @@ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ #ifdef RT_RTC_DEBUG -#define rtc_debug(format,args...) rt_kprintf(format, ##args) +#define rtc_debug(format,args...) rt_kprintf(format, ##args) #else #define rtc_debug(format,args...) #endif @@ -55,10 +55,10 @@ static rt_err_t rt_rtc_open(rt_device_t dev, rt_uint16_t oflag) } static rt_size_t rt_rtc_read( - rt_device_t dev, - rt_off_t pos, - void* buffer, - rt_size_t size) + rt_device_t dev, + rt_off_t pos, + void* buffer, + rt_size_t size) { return 0; } @@ -91,16 +91,16 @@ static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args) { case RT_DEVICE_CTRL_RTC_GET_TIME: *(rt_uint32_t *)args = rtc_time + RTC_CounterGet(); - rtc_debug("RTC: get rtc_time %x + %x\n", rtc_time, RTC_CounterGet()); + rtc_debug("RTC: get rtc_time %x + %x\n", rtc_time, RTC_CounterGet()); break; case RT_DEVICE_CTRL_RTC_SET_TIME: { rtc_time = *(rt_uint32_t *)args; - rtc_debug("RTC: set rtc_time %x\n", rtc_time); + rtc_debug("RTC: set rtc_time %x\n", rtc_time); - /* Reset counter */ - RTC_CounterReset(); + /* Reset counter */ + RTC_CounterReset(); } break; } @@ -118,12 +118,12 @@ static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args) ******************************************************************************/ void rt_hw_rtc_isr(rt_device_t device) { - if (RTC->IF & RTC_IFC_OF) - { - rtc_time += _RTC_CNT_MASK; - } + if (RTC->IF & RTC_IFC_OF) + { + rtc_time += _RTC_CNT_MASK; + } - RTC->IFC = _RTC_IFC_MASK; + RTC->IFC = _RTC_IFC_MASK; } /***************************************************************************//** @@ -147,25 +147,25 @@ void rt_hw_rtc_isr(rt_device_t device) * Error code ******************************************************************************/ rt_err_t rt_hw_rtc_register( - rt_device_t device, - const char *name, - rt_uint32_t flag) + rt_device_t device, + const char *name, + rt_uint32_t flag) { - RT_ASSERT(device != RT_NULL); - - device->type = RT_Device_Class_RTC; - device->rx_indicate = RT_NULL; - device->tx_complete = RT_NULL; - device->init = RT_NULL; - device->open = rt_rtc_open; - device->close = RT_NULL; - device->read = rt_rtc_read; - device->write = RT_NULL; - device->control = rt_rtc_control; - device->user_data = RT_NULL; /* no private */ - - /* register a character device */ - return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); + RT_ASSERT(device != RT_NULL); + + device->type = RT_Device_Class_RTC; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->init = RT_NULL; + device->open = rt_rtc_open; + device->close = RT_NULL; + device->read = rt_rtc_read; + device->write = RT_NULL; + device->control = rt_rtc_control; + device->user_data = RT_NULL; /* no private */ + + /* register a character device */ + return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); } @@ -179,50 +179,50 @@ rt_err_t rt_hw_rtc_register( ******************************************************************************/ void rt_hw_rtc_init(void) { - rt_uint32_t reset; + rt_uint32_t reset; - reset = RMU_ResetCauseGet(); + reset = RMU_ResetCauseGet(); - // TODO: What is the current reset mode? - if (reset & RMU_RSTCAUSE_PORST || reset & RMU_RSTCAUSE_EXTRST) + // TODO: What is the current reset mode? + if (reset & RMU_RSTCAUSE_PORST || reset & RMU_RSTCAUSE_EXTRST) { - RTC_Init_TypeDef rtcInit; - efm32_irq_hook_init_t hook; + RTC_Init_TypeDef rtcInit; + efm32_irq_hook_init_t hook; - rtcInit.enable = true; - rtcInit.debugRun = false; - rtcInit.comp0Top = false; + rtcInit.enable = true; + rtcInit.debugRun = false; + rtcInit.comp0Top = false; - rtc_time = 0UL; + rtc_time = 0UL; rt_kprintf("rtc is not configured\n"); rt_kprintf("please configure with set_date and set_time\n"); - /* Configuring clock */ + /* Configuring clock */ CMU_ClockDivSet(cmuClock_RTC,cmuClkDiv_32768); CMU_ClockEnable(cmuClock_RTC, true); - /* Initialize and enable RTC */ - RTC_Reset(); - RTC_Init(&rtcInit); + /* Initialize and enable RTC */ + RTC_Reset(); + RTC_Init(&rtcInit); - hook.type = efm32_irq_type_rtc; - hook.unit = 0; - hook.cbFunc = rt_hw_rtc_isr; - hook.userPtr = RT_NULL; - efm32_irq_hook_register(&hook); + hook.type = efm32_irq_type_rtc; + hook.unit = 0; + hook.cbFunc = rt_hw_rtc_isr; + hook.userPtr = RT_NULL; + efm32_irq_hook_register(&hook); - /* Enabling Interrupt from RTC */ - RTC_IntEnable(RTC_IFC_OF); - RTC_IntClear(RTC_IFC_OF); + /* Enabling Interrupt from RTC */ + RTC_IntEnable(RTC_IFC_OF); + RTC_IntClear(RTC_IFC_OF); - NVIC_ClearPendingIRQ(RTC_IRQn); - NVIC_SetPriority(RTC_IRQn, EFM32_IRQ_PRI_DEFAULT); - NVIC_EnableIRQ(RTC_IRQn); + NVIC_ClearPendingIRQ(RTC_IRQn); + NVIC_SetPriority(RTC_IRQn, EFM32_IRQ_PRI_DEFAULT); + NVIC_EnableIRQ(RTC_IRQn); } /* register rtc device */ - rt_hw_rtc_register(&rtc, RT_RTC_NAME, EFM32_NO_DATA); + rt_hw_rtc_register(&rtc, RT_RTC_NAME, EFM32_NO_DATA); } #endif diff --git a/bsp/efm32/drv_rtc.h b/bsp/efm32/drv_rtc.h index 492fc59d56..7e33c03896 100644 --- a/bsp/efm32/drv_rtc.h +++ b/bsp/efm32/drv_rtc.h @@ -10,7 +10,7 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes + * Date Author Notes * 2009-01-05 Bernard the first version * 2010-12-27 onelife Modification for EFM32 *********************************************************************/ diff --git a/bsp/efm32/drv_sdcard.h b/bsp/efm32/drv_sdcard.h index 17c94209c9..2c9a1bfc39 100644 --- a/bsp/efm32/drv_sdcard.h +++ b/bsp/efm32/drv_sdcard.h @@ -1,9 +1,9 @@ /***************************************************************************//** - * @file drv_sdcard.h - * @brief Memory card driver (SPI mode) of RT-Thread RTOS for using EFM32 + * @file drv_sdcard.h + * @brief Memory card driver (SPI mode) of RT-Thread RTOS for using EFM32 * USART module * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -11,9 +11,9 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes - * 2011-05-13 onelife Initial creation for using EFM32 USART module - * 2011-07-07 onelife Modify initialization function to return error code + * Date Author Notes + * 2011-05-13 onelife Initial creation for using EFM32 USART module + * 2011-07-07 onelife Modify initialization function to return error code ******************************************************************************/ #ifndef __DEV_SDCARD_H__ #define __DEV_SDCARD_H__ @@ -33,43 +33,43 @@ #error "EFM32 SPI clock should not be more than (EFM32_HFXO_FREQUENCY/2)" #endif -#define SD_SPEED_LOW (0) -#define SD_SPEED_HIGH (1) -#define SD_WAIT_PERIOD (RT_TICK_PER_SECOND) +#define SD_SPEED_LOW (0) +#define SD_SPEED_HIGH (1) +#define SD_WAIT_PERIOD (RT_TICK_PER_SECOND) -#define SD_SECTOR_SIZE_SHIFT (9) -#define SD_SECTOR_SIZE (1 << SD_SECTOR_SIZE_SHIFT) -#define SD_BLOCK_SIZE_CSD (16) -#define SD_BLOCK_SIZE_CID (16) -#define SD_BLOCK_SIZE_OCR (4) -#define SD_BLOCK_SIZE_SDSTAT (64) +#define SD_SECTOR_SIZE_SHIFT (9) +#define SD_SECTOR_SIZE (1 << SD_SECTOR_SIZE_SHIFT) +#define SD_BLOCK_SIZE_CSD (16) +#define SD_BLOCK_SIZE_CID (16) +#define SD_BLOCK_SIZE_OCR (4) +#define SD_BLOCK_SIZE_SDSTAT (64) /* Card type definitions (CardType) */ -#define CT_MMC (0x01) -#define CT_SD1 (0x02) -#define CT_SD2 (0x04) -#define CT_SDC (CT_SD1|CT_SD2) -#define CT_BLOCK (0x08) +#define CT_MMC (0x01) +#define CT_SD1 (0x02) +#define CT_SD2 (0x04) +#define CT_SDC (CT_SD1|CT_SD2) +#define CT_BLOCK (0x08) /* Definitions for MMC/SDC command */ -#define CMD0 (0) /* GO_IDLE_STATE */ -#define CMD1 (1) /* SEND_OP_COND */ -#define ACMD41 (41|0x80) /* SEND_OP_COND (SDC) */ -#define CMD8 (8) /* SEND_IF_COND */ -#define CMD9 (9) /* SEND_CSD */ -#define CMD10 (10) /* SEND_CID */ -#define CMD12 (12) /* STOP_TRANSMISSION */ -#define ACMD13 (13|0x80) /* SD_STATUS (SDC) */ -#define CMD16 (16) /* SET_BLOCKLEN */ -#define CMD17 (17) /* READ_SINGLE_BLOCK */ -#define CMD18 (18) /* READ_MULTIPLE_BLOCK */ -#define CMD23 (23) /* SET_BLOCK_COUNT */ -#define ACMD23 (23|0x80) /* SET_WR_BLK_ERASE_COUNT (SDC) */ -#define CMD24 (24) /* WRITE_BLOCK */ -#define CMD25 (25) /* WRITE_MULTIPLE_BLOCK */ -#define CMD41 (41) /* SEND_OP_COND (ACMD) */ -#define CMD55 (55) /* APP_CMD */ -#define CMD58 (58) /* READ_OCR */ +#define CMD0 (0) /* GO_IDLE_STATE */ +#define CMD1 (1) /* SEND_OP_COND */ +#define ACMD41 (41|0x80) /* SEND_OP_COND (SDC) */ +#define CMD8 (8) /* SEND_IF_COND */ +#define CMD9 (9) /* SEND_CSD */ +#define CMD10 (10) /* SEND_CID */ +#define CMD12 (12) /* STOP_TRANSMISSION */ +#define ACMD13 (13|0x80) /* SD_STATUS (SDC) */ +#define CMD16 (16) /* SET_BLOCKLEN */ +#define CMD17 (17) /* READ_SINGLE_BLOCK */ +#define CMD18 (18) /* READ_MULTIPLE_BLOCK */ +#define CMD23 (23) /* SET_BLOCK_COUNT */ +#define ACMD23 (23|0x80) /* SET_WR_BLK_ERASE_COUNT (SDC) */ +#define CMD24 (24) /* WRITE_BLOCK */ +#define CMD25 (25) /* WRITE_MULTIPLE_BLOCK */ +#define CMD41 (41) /* SEND_OP_COND (ACMD) */ +#define CMD55 (55) /* APP_CMD */ +#define CMD58 (58) /* READ_OCR */ /* Exported functions ------------------------------------------------------- */ rt_err_t efm_spiSd_init(void); diff --git a/bsp/efm32/drv_timer.c b/bsp/efm32/drv_timer.c index ccfb96ab0e..12e347544c 100644 --- a/bsp/efm32/drv_timer.c +++ b/bsp/efm32/drv_timer.c @@ -10,7 +10,7 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes + * Date Author Notes * 2011-01-18 onelife Initial creation for EFM32 * 2011-06-17 onelife Modify init function for efm32lib v2 upgrading ******************************************************************************/ diff --git a/bsp/efm32/drv_usart.c b/bsp/efm32/drv_usart.c index 7cfb50b0a7..c511a31475 100644 --- a/bsp/efm32/drv_usart.c +++ b/bsp/efm32/drv_usart.c @@ -34,9 +34,9 @@ * 2011-12-20 onelife Add 9-bit SPI mode support * 2011-12-20 onelife Change SPI write format (same as SPI read) * 2011-12-20 onelife Change USART status format - * 2011-12-27 onelife Utilize "USART_PRESENT", "USART_COUNT", + * 2011-12-27 onelife Utilize "USART_PRESENT", "USART_COUNT", * "UART_PRESENT" and "UART_COUNT" - * 2012-05-16 onelife Fix a bug in rt_hw_usart_init() + * 2012-05-16 onelife Fix a bug in rt_hw_usart_init() ******************************************************************************/ /***************************************************************************//** diff --git a/bsp/efm32/enc28j60.h b/bsp/efm32/enc28j60.h index 4f9c7046fe..5955c603e7 100644 --- a/bsp/efm32/enc28j60.h +++ b/bsp/efm32/enc28j60.h @@ -193,9 +193,9 @@ #define MACON3_FRMLNEN 0x02 #define MACON3_FULDPX 0x01 // ENC28J60 MACON4 Register Bit Definitions -#define MACON4_DEFER (1<<6) -#define MACON4_BPEN (1<<5) -#define MACON4_NOBKOFF (1<<4) +#define MACON4_DEFER (1<<6) +#define MACON4_BPEN (1<<5) +#define MACON4_NOBKOFF (1<<4) // ENC28J60 MICMD Register Bit Definitions #define MICMD_MIISCAN 0x02 #define MICMD_MIIRD 0x01 @@ -214,12 +214,12 @@ #define PHSTAT1_LLSTAT 0x0004 #define PHSTAT1_JBSTAT 0x0002 /* ENC28J60 PHY PHSTAT2 Register Bit Definitions */ -#define PHSTAT2_TXSTAT (1 << 13) -#define PHSTAT2_RXSTAT (1 << 12) -#define PHSTAT2_COLSTAT (1 << 11) -#define PHSTAT2_LSTAT (1 << 10) -#define PHSTAT2_DPXSTAT (1 << 9) -#define PHSTAT2_PLRITY (1 << 5) +#define PHSTAT2_TXSTAT (1 << 13) +#define PHSTAT2_RXSTAT (1 << 12) +#define PHSTAT2_COLSTAT (1 << 11) +#define PHSTAT2_LSTAT (1 << 10) +#define PHSTAT2_DPXSTAT (1 << 9) +#define PHSTAT2_PLRITY (1 << 5) // ENC28J60 PHY PHCON2 Register Bit Definitions #define PHCON2_FRCLINK 0x4000 #define PHCON2_TXDIS 0x2000 @@ -278,13 +278,13 @@ #define RSV_GETBIT(x, y) (((x) & RSV_BITMASK(y)) ? 1 : 0) // SPI operation codes -#define ENC28J60_READ_CTRL_REG (0x00) -#define ENC28J60_READ_BUF_MEM (0x20 | 0x1A) -#define ENC28J60_WRITE_CTRL_REG (0x40) -#define ENC28J60_WRITE_BUF_MEM (0x60 | 0x1A) -#define ENC28J60_BIT_FIELD_SET (0x80) -#define ENC28J60_BIT_FIELD_CLR (0xA0) -#define ENC28J60_SOFT_RESET (0xE0 | 0x1F) +#define ENC28J60_READ_CTRL_REG (0x00) +#define ENC28J60_READ_BUF_MEM (0x20 | 0x1A) +#define ENC28J60_WRITE_CTRL_REG (0x40) +#define ENC28J60_WRITE_BUF_MEM (0x60 | 0x1A) +#define ENC28J60_BIT_FIELD_SET (0x80) +#define ENC28J60_BIT_FIELD_CLR (0xA0) +#define ENC28J60_SOFT_RESET (0xE0 | 0x1F) // The RXSTART_INIT should be zero. See Rev. B4 Silicon Errata // buffer boundaries applied to internal 8K ram @@ -292,17 +292,17 @@ // // start with recbuf at 0/ -#define RXSTART_INIT 0x0 +#define RXSTART_INIT 0x0 // receive buffer end -#define RXSTOP_INIT (0x1FFF - 0x0600 - 1) +#define RXSTOP_INIT (0x1FFF - 0x0600 - 1) // start TX buffer at 0x1FFF-0x0600, pace for one full ethernet frame (~1500 bytes) -#define TXSTART_INIT (0x1FFF - 0x0600) +#define TXSTART_INIT (0x1FFF - 0x0600) // stp TX buffer at end of mem -#define TXSTOP_INIT 0x1FFF +#define TXSTOP_INIT 0x1FFF // max frame length which the conroller will accept: -#define MAX_FRAMELEN 1518 +#define MAX_FRAMELEN 1518 void rt_hw_enc28j60_init(void); diff --git a/bsp/efm32/graphics/tftspi.h b/bsp/efm32/graphics/tftspi.h index 1399fc552e..27e8ce8078 100644 --- a/bsp/efm32/graphics/tftspi.h +++ b/bsp/efm32/graphics/tftspi.h @@ -1,8 +1,8 @@ /***************************************************************************//** - * @file tftspi.h - * @brief Stub functions of EFM32 LCD driver + * @file tftspi.h + * @brief Stub functions of EFM32 LCD driver * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -10,7 +10,7 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes + * Date Author Notes * 2011-12-20 onelife Initial creation for EFM32 ******************************************************************************/ #ifndef __TFTSPI_H__ diff --git a/bsp/efm32/hdl_interrupt.c b/bsp/efm32/hdl_interrupt.c index de91a9f9a0..8017414e55 100644 --- a/bsp/efm32/hdl_interrupt.c +++ b/bsp/efm32/hdl_interrupt.c @@ -13,10 +13,10 @@ * Date Author Notes * 2010-12-29 onelife Initial creation for EFM32 * 2011-07-12 onelife Disable interrupts in GPIO handler - * 2011-12-09 onelife Add giant gecko support + * 2011-12-09 onelife Add giant gecko support * 2011-12-09 onelife Add UART module support * 2011-12-09 onelife Add LEUART module support - * 2011-12-27 onelife Utilize "XXX_PRESENT" and "XXX_COUNT" + * 2011-12-27 onelife Utilize "XXX_PRESENT" and "XXX_COUNT" ******************************************************************************/ /* Includes ------------------------------------------------------------------*/ @@ -32,20 +32,20 @@ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ #ifdef RT_IRQHDL_DEBUG -#define hdl_debug(format,args...) rt_kprintf(format, ##args) +#define hdl_debug(format,args...) rt_kprintf(format, ##args) #else #define hdl_debug(format,args...) #endif /* Private variables ---------------------------------------------------------*/ -efm32_irq_hook_t dmaCbTable[DMA_CHAN_COUNT * 2] = {RT_NULL}; -efm32_irq_hook_t timerCbTable[TIMER_COUNT] = {RT_NULL}; +efm32_irq_hook_t dmaCbTable[DMA_CHAN_COUNT * 2] = {RT_NULL}; +efm32_irq_hook_t timerCbTable[TIMER_COUNT] = {RT_NULL}; #if defined(LETIMER_PRESENT) efm32_irq_hook_t letimerCbTable[LETIMER_COUNT] = {RT_NULL}; #endif -efm32_irq_hook_t rtcCbTable[RTC_COUNT] = {RT_NULL}; -efm32_irq_hook_t gpioCbTable[16] = {RT_NULL}; -efm32_irq_hook_t acmpCbTable[ACMP_COUNT] = {RT_NULL}; +efm32_irq_hook_t rtcCbTable[RTC_COUNT] = {RT_NULL}; +efm32_irq_hook_t gpioCbTable[16] = {RT_NULL}; +efm32_irq_hook_t acmpCbTable[ACMP_COUNT] = {RT_NULL}; #if defined(USART_PRESENT) #if defined(UART_PRESENT) efm32_irq_hook_t usartCbTable[USART_COUNT * 2 + UART_COUNT * 2] = {RT_NULL}; @@ -57,7 +57,7 @@ efm32_irq_hook_t usartCbTable[USART_COUNT * 2] = {RT_NULL}; efm32_irq_hook_t leuartCbTable[LEUART_COUNT] = {RT_NULL}; #endif #if defined(I2C_PRESENT) -efm32_irq_hook_t iicCbTable[I2C_COUNT] = {RT_NULL}; +efm32_irq_hook_t iicCbTable[I2C_COUNT] = {RT_NULL}; #endif /* Private function prototypes -----------------------------------------------*/ @@ -65,7 +65,7 @@ efm32_irq_hook_t iicCbTable[I2C_COUNT] = {RT_NULL}; /***************************************************************************//** * @brief - * NMI exception handler + * NMI exception handler * * @details * @@ -73,12 +73,12 @@ efm32_irq_hook_t iicCbTable[I2C_COUNT] = {RT_NULL}; ******************************************************************************/ void NMI_Handler(void) { - hdl_debug("[NMI_Handler: NOP]\n"); + hdl_debug("[NMI_Handler: NOP]\n"); } /***************************************************************************//** * @brief - * Memory manage exception handler + * Memory manage exception handler * * @details * @@ -86,13 +86,13 @@ void NMI_Handler(void) ******************************************************************************/ void MemManage_Handler(void) { - hdl_debug("[MemManage_Handler: infinite loop]\n"); - while (1); + hdl_debug("[MemManage_Handler: infinite loop]\n"); + while (1); } /***************************************************************************//** * @brief - * Bus fault exception handler + * Bus fault exception handler * * @details * @@ -100,13 +100,13 @@ void MemManage_Handler(void) ******************************************************************************/ void BusFault_Handler(void) { - hdl_debug("[BusFault_Handler: infinite loop]\n"); - while (1); + hdl_debug("[BusFault_Handler: infinite loop]\n"); + while (1); } /***************************************************************************//** * @brief - * Usage fault exception handler + * Usage fault exception handler * * @details * @@ -114,13 +114,13 @@ void BusFault_Handler(void) ******************************************************************************/ void UsageFault_Handler(void) { - hdl_debug("[UsageFault_Handler: infinite loop]\n"); - while (1); + hdl_debug("[UsageFault_Handler: infinite loop]\n"); + while (1); } /***************************************************************************//** * @brief - * Supervisor call exception handler + * Supervisor call exception handler * * @details * @@ -128,12 +128,12 @@ void UsageFault_Handler(void) ******************************************************************************/ void SVC_Handler(void) { - hdl_debug("[SVC_Handler: NOP]\n"); + hdl_debug("[SVC_Handler: NOP]\n"); } /***************************************************************************//** * @brief - * Debug monitor exception handler + * Debug monitor exception handler * * @details * @@ -141,12 +141,12 @@ void SVC_Handler(void) ******************************************************************************/ void DebugMon_Handler(void) { - hdl_debug("[DebugMon_Handler: NOP]\n"); + hdl_debug("[DebugMon_Handler: NOP]\n"); } /***************************************************************************//** * @brief - * System tick timer interrupt handler + * System tick timer interrupt handler * * @details * @@ -155,13 +155,13 @@ void DebugMon_Handler(void) ******************************************************************************/ void SysTick_Handler(void) { - /* enter interrupt */ - rt_interrupt_enter(); + /* enter interrupt */ + rt_interrupt_enter(); - rt_tick_increase(); + rt_tick_increase(); - /* leave interrupt */ - rt_interrupt_leave(); + /* leave interrupt */ + rt_interrupt_leave(); } /******************************************************************************* @@ -173,7 +173,7 @@ void SysTick_Handler(void) /***************************************************************************//** * @brief - * Common DMA interrupt handler + * Common DMA interrupt handler * * @details * @@ -185,11 +185,11 @@ void DMA_IRQHandler_All(rt_uint32_t channel, rt_bool_t primary, void *user) /* enter interrupt */ rt_interrupt_enter(); - /* invoke callback function */ - if (dmaCbTable[channel].cbFunc != RT_NULL) - { - (dmaCbTable[channel].cbFunc)(dmaCbTable[channel].userPtr); - } + /* invoke callback function */ + if (dmaCbTable[channel].cbFunc != RT_NULL) + { + (dmaCbTable[channel].cbFunc)(dmaCbTable[channel].userPtr); + } /* leave interrupt */ rt_interrupt_leave(); @@ -197,95 +197,95 @@ void DMA_IRQHandler_All(rt_uint32_t channel, rt_bool_t primary, void *user) /***************************************************************************//** * @brief - * Common Timer0 interrupt handler + * Common Timer0 interrupt handler * * @details - * This function handles Timer0 counter overflow interrupt request + * This function handles Timer0 counter overflow interrupt request * * @note * ******************************************************************************/ void TIMER0_IRQHandler(void) { - if (TIMER0->IF & TIMER_IF_OF) - { - /* invoke callback function */ - if (timerCbTable[0].cbFunc != RT_NULL) - { - (timerCbTable[0].cbFunc)(timerCbTable[0].userPtr); - } - - /* clear interrupt */ - BITBAND_Peripheral(&(TIMER0->IFC), _TIMER_IF_OF_SHIFT, 0x1UL); - } + if (TIMER0->IF & TIMER_IF_OF) + { + /* invoke callback function */ + if (timerCbTable[0].cbFunc != RT_NULL) + { + (timerCbTable[0].cbFunc)(timerCbTable[0].userPtr); + } + + /* clear interrupt */ + BITBAND_Peripheral(&(TIMER0->IFC), _TIMER_IF_OF_SHIFT, 0x1UL); + } } /***************************************************************************//** * @brief - * Common Timer1 interrupt handler + * Common Timer1 interrupt handler * * @details - * This function handles Timer1 counter overflow interrupt request + * This function handles Timer1 counter overflow interrupt request * * @note * ******************************************************************************/ void TIMER1_IRQHandler(void) { - if (TIMER1->IF & TIMER_IF_OF) - { - /* invoke callback function */ - if (timerCbTable[1].cbFunc != RT_NULL) - { - (timerCbTable[1].cbFunc)(timerCbTable[1].userPtr); - } - - /* clear interrupt */ - BITBAND_Peripheral(&(TIMER1->IFC), _TIMER_IF_OF_SHIFT, 0x1UL); - } + if (TIMER1->IF & TIMER_IF_OF) + { + /* invoke callback function */ + if (timerCbTable[1].cbFunc != RT_NULL) + { + (timerCbTable[1].cbFunc)(timerCbTable[1].userPtr); + } + + /* clear interrupt */ + BITBAND_Peripheral(&(TIMER1->IFC), _TIMER_IF_OF_SHIFT, 0x1UL); + } } /***************************************************************************//** * @brief - * Common Timer2 interrupt handler + * Common Timer2 interrupt handler * * @details - * This function handles Timer2 counter overflow interrupt request + * This function handles Timer2 counter overflow interrupt request * * @note * ******************************************************************************/ void TIMER2_IRQHandler(void) { - if (TIMER2->IF & TIMER_IF_OF) - { - /* invoke callback function */ - if (timerCbTable[2].cbFunc != RT_NULL) - { - (timerCbTable[2].cbFunc)(timerCbTable[2].userPtr); - } - - /* clear interrupt */ - BITBAND_Peripheral(&(TIMER2->IFC), _TIMER_IF_OF_SHIFT, 0x1UL); - } + if (TIMER2->IF & TIMER_IF_OF) + { + /* invoke callback function */ + if (timerCbTable[2].cbFunc != RT_NULL) + { + (timerCbTable[2].cbFunc)(timerCbTable[2].userPtr); + } + + /* clear interrupt */ + BITBAND_Peripheral(&(TIMER2->IFC), _TIMER_IF_OF_SHIFT, 0x1UL); + } } #if defined(LETIMER_PRESENT) /***************************************************************************//** * @brief - * Common Low Energy Timer0 interrupt handler + * Common Low Energy Timer0 interrupt handler * * @details - * This function handles Timer0 counter overflow interrupt request + * This function handles Timer0 counter overflow interrupt request * * @note * ******************************************************************************/ void LETIMER0_IRQHandler(void) { - if (LETIMER0->IF & LETIMER_IF_UF) - { + if (LETIMER0->IF & LETIMER_IF_UF) + { /* enter interrupt */ rt_interrupt_enter(); @@ -294,24 +294,24 @@ void LETIMER0_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); - /* invoke callback function */ -/* if (letimerCbTable[0].cbFunc != RT_NULL) - { - (letimerCbTable[0].cbFunc)(letimerCbTable[0].userPtr); - } + /* invoke callback function */ +/* if (letimerCbTable[0].cbFunc != RT_NULL) + { + (letimerCbTable[0].cbFunc)(letimerCbTable[0].userPtr); + } */ - /* clear interrupt */ - BITBAND_Peripheral(&(LETIMER0->IFC), _LETIMER_IF_UF_SHIFT, 0x1UL); - } + /* clear interrupt */ + BITBAND_Peripheral(&(LETIMER0->IFC), _LETIMER_IF_UF_SHIFT, 0x1UL); + } } #endif /***************************************************************************//** * @brief - * Common RTC interrupt handler + * Common RTC interrupt handler * * @details - * This function handles RTC counter overflow interrupt request + * This function handles RTC counter overflow interrupt request * * @note * @@ -321,14 +321,14 @@ void RTC_IRQHandler(void) /* enter interrupt */ rt_interrupt_enter(); - if (RTC->IF & RTC_IF_OF) - { - /* invoke callback function */ - if (rtcCbTable[0].cbFunc != RT_NULL) - { - (rtcCbTable[0].cbFunc)(rtcCbTable[0].userPtr); - } - } + if (RTC->IF & RTC_IF_OF) + { + /* invoke callback function */ + if (rtcCbTable[0].cbFunc != RT_NULL) + { + (rtcCbTable[0].cbFunc)(rtcCbTable[0].userPtr); + } + } /* leave interrupt */ rt_interrupt_leave(); @@ -336,7 +336,7 @@ void RTC_IRQHandler(void) /***************************************************************************//** * @brief - * Common even number GPIO interrupt handler + * Common even number GPIO interrupt handler * * @details * @@ -345,36 +345,36 @@ void RTC_IRQHandler(void) ******************************************************************************/ void GPIO_EVEN_IRQHandler(void) { - rt_uint16_t flag, n; - rt_base_t level; + rt_uint16_t flag, n; + rt_base_t level; - /* Disable interrupt */ - level = rt_hw_interrupt_disable(); + /* Disable interrupt */ + level = rt_hw_interrupt_disable(); /* Enter ISR */ rt_interrupt_enter(); - /* invoke callback function */ - flag = (rt_uint16_t)(GPIO->IF & 0xFFFF); - for ( n = 0; flag > 0; flag = flag >> 2, n = n + 2) - { - if ((flag & 0x0001) && (gpioCbTable[n].cbFunc != RT_NULL)) - { - (gpioCbTable[n].cbFunc)(gpioCbTable[n].userPtr); - } - } + /* invoke callback function */ + flag = (rt_uint16_t)(GPIO->IF & 0xFFFF); + for ( n = 0; flag > 0; flag = flag >> 2, n = n + 2) + { + if ((flag & 0x0001) && (gpioCbTable[n].cbFunc != RT_NULL)) + { + (gpioCbTable[n].cbFunc)(gpioCbTable[n].userPtr); + } + } - /* clear interrupt */ - GPIO->IFC = 0x5555UL; + /* clear interrupt */ + GPIO->IFC = 0x5555UL; /* Leave ISR */ - rt_interrupt_leave(); - /* Enable interrupt */ + rt_interrupt_leave(); + /* Enable interrupt */ rt_hw_interrupt_enable(level); } /***************************************************************************//** * @brief - * Common odd number GPIO interrupt handler + * Common odd number GPIO interrupt handler * * @details * @@ -383,39 +383,39 @@ void GPIO_EVEN_IRQHandler(void) ******************************************************************************/ void GPIO_ODD_IRQHandler(void) { - rt_uint16_t flag, n; - rt_base_t level; + rt_uint16_t flag, n; + rt_base_t level; - /* Disable interrupt */ - level = rt_hw_interrupt_disable(); - /* Enter ISR */ + /* Disable interrupt */ + level = rt_hw_interrupt_disable(); + /* Enter ISR */ rt_interrupt_enter(); - /* invoke callback function */ - flag = (rt_uint16_t)(GPIO->IF & 0xFFFF) >> 1; - for ( n = 1; flag > 0; flag = flag >> 2, n = n + 2) - { - if ((flag & 0x0001) && (gpioCbTable[n].cbFunc != RT_NULL)) - { - (gpioCbTable[n].cbFunc)(gpioCbTable[n].userPtr); - } - } + /* invoke callback function */ + flag = (rt_uint16_t)(GPIO->IF & 0xFFFF) >> 1; + for ( n = 1; flag > 0; flag = flag >> 2, n = n + 2) + { + if ((flag & 0x0001) && (gpioCbTable[n].cbFunc != RT_NULL)) + { + (gpioCbTable[n].cbFunc)(gpioCbTable[n].userPtr); + } + } - /* clear interrupt */ - GPIO->IFC = 0xAAAAUL; + /* clear interrupt */ + GPIO->IFC = 0xAAAAUL; /* Leave ISR */ - rt_interrupt_leave(); - /* Enable interrupt */ + rt_interrupt_leave(); + /* Enable interrupt */ rt_hw_interrupt_enable(level); } /***************************************************************************//** * @brief - * Common ACMP interrupt handler + * Common ACMP interrupt handler * * @details - * This function handles ACMP edge trigger interrupt request + * This function handles ACMP edge trigger interrupt request * * @note * @@ -425,29 +425,29 @@ void ACMP0_IRQHandler(void) /* enter interrupt */ rt_interrupt_enter(); - if (ACMP0->IF & ACMP_IF_EDGE) - { - /* invoke callback function */ - if (acmpCbTable[0].cbFunc != RT_NULL) - { - (acmpCbTable[0].cbFunc)(acmpCbTable[0].userPtr); - } - - /* clear interrupt */ - BITBAND_Peripheral(&(ACMP0->IFC), _ACMP_IF_EDGE_SHIFT, 0x1UL); - } - - if (ACMP1->IF & ACMP_IF_EDGE) - { - /* invoke callback function */ - if (acmpCbTable[1].cbFunc != RT_NULL) - { - (acmpCbTable[1].cbFunc)(acmpCbTable[1].userPtr); - } - - /* clear interrupt */ - BITBAND_Peripheral(&(ACMP1->IFC), _ACMP_IF_EDGE_SHIFT, 0x1UL); - } + if (ACMP0->IF & ACMP_IF_EDGE) + { + /* invoke callback function */ + if (acmpCbTable[0].cbFunc != RT_NULL) + { + (acmpCbTable[0].cbFunc)(acmpCbTable[0].userPtr); + } + + /* clear interrupt */ + BITBAND_Peripheral(&(ACMP0->IFC), _ACMP_IF_EDGE_SHIFT, 0x1UL); + } + + if (ACMP1->IF & ACMP_IF_EDGE) + { + /* invoke callback function */ + if (acmpCbTable[1].cbFunc != RT_NULL) + { + (acmpCbTable[1].cbFunc)(acmpCbTable[1].userPtr); + } + + /* clear interrupt */ + BITBAND_Peripheral(&(ACMP1->IFC), _ACMP_IF_EDGE_SHIFT, 0x1UL); + } /* leave interrupt */ rt_interrupt_leave(); @@ -456,10 +456,10 @@ void ACMP0_IRQHandler(void) #if defined(USART_PRESENT) /***************************************************************************//** * @brief - * Common USART0 TX interrupt handler + * Common USART0 TX interrupt handler * * @details - * This function handles USART0 TX complete interrupt request + * This function handles USART0 TX complete interrupt request * * @note * @@ -469,17 +469,17 @@ void USART0_TX_IRQHandler(void) /* enter interrupt */ rt_interrupt_enter(); - if (USART0->IF & USART_IF_TXC) - { - /* invoke callback function */ - if (usartCbTable[0].cbFunc != RT_NULL) - { - (usartCbTable[0].cbFunc)(usartCbTable[0].userPtr); - } + if (USART0->IF & USART_IF_TXC) + { + /* invoke callback function */ + if (usartCbTable[0].cbFunc != RT_NULL) + { + (usartCbTable[0].cbFunc)(usartCbTable[0].userPtr); + } - /* clear interrupt */ - BITBAND_Peripheral(&(USART0->IFC), _USART_IF_TXC_SHIFT, 0x1UL); - } + /* clear interrupt */ + BITBAND_Peripheral(&(USART0->IFC), _USART_IF_TXC_SHIFT, 0x1UL); + } /* leave interrupt */ rt_interrupt_leave(); @@ -487,34 +487,34 @@ void USART0_TX_IRQHandler(void) /***************************************************************************//** * @brief - * Common USART0 RX interrupt handler + * Common USART0 RX interrupt handler * * @details - * This function handles USART0 RX data valid interrupt request + * This function handles USART0 RX data valid interrupt request * * @note * ******************************************************************************/ void USART0_RX_IRQHandler(void) { - if (USART0->IF & USART_IF_RXDATAV) - { - /* invoke callback function */ - if (usartCbTable[1].cbFunc != RT_NULL) - { - (usartCbTable[1].cbFunc)(usartCbTable[1].userPtr); - } - } + if (USART0->IF & USART_IF_RXDATAV) + { + /* invoke callback function */ + if (usartCbTable[1].cbFunc != RT_NULL) + { + (usartCbTable[1].cbFunc)(usartCbTable[1].userPtr); + } + } } #endif #if (defined(USART_PRESENT) && (USART_COUNT > 1)) /***************************************************************************//** * @brief - * Common USART1 TX interrupt handler + * Common USART1 TX interrupt handler * * @details - * This function handles USART1 TX complete interrupt request + * This function handles USART1 TX complete interrupt request * * @note * @@ -524,17 +524,17 @@ void USART1_TX_IRQHandler(void) /* enter interrupt */ rt_interrupt_enter(); - if (USART1->IF & USART_IF_TXC) - { - /* invoke callback function */ - if (usartCbTable[2].cbFunc != RT_NULL) - { - (usartCbTable[2].cbFunc)(usartCbTable[2].userPtr); - } + if (USART1->IF & USART_IF_TXC) + { + /* invoke callback function */ + if (usartCbTable[2].cbFunc != RT_NULL) + { + (usartCbTable[2].cbFunc)(usartCbTable[2].userPtr); + } - /* clear interrupt */ - BITBAND_Peripheral(&(USART1->IFC), _USART_IF_TXC_SHIFT, 0x1UL); - } + /* clear interrupt */ + BITBAND_Peripheral(&(USART1->IFC), _USART_IF_TXC_SHIFT, 0x1UL); + } /* leave interrupt */ rt_interrupt_leave(); @@ -542,34 +542,34 @@ void USART1_TX_IRQHandler(void) /***************************************************************************//** * @brief - * Common USART1 RX interrupt handler + * Common USART1 RX interrupt handler * * @details - * This function handles USART1 RX data valid interrupt request + * This function handles USART1 RX data valid interrupt request * * @note * ******************************************************************************/ void USART1_RX_IRQHandler(void) { - if (USART1->IF & USART_IF_RXDATAV) - { - /* invoke callback function */ - if (usartCbTable[3].cbFunc != RT_NULL) - { - (usartCbTable[3].cbFunc)(usartCbTable[3].userPtr); - } - } + if (USART1->IF & USART_IF_RXDATAV) + { + /* invoke callback function */ + if (usartCbTable[3].cbFunc != RT_NULL) + { + (usartCbTable[3].cbFunc)(usartCbTable[3].userPtr); + } + } } #endif #if (defined(USART_PRESENT) && (USART_COUNT > 2)) /***************************************************************************//** * @brief - * Common USART2 TX interrupt handler + * Common USART2 TX interrupt handler * * @details - * This function handles USART2 TX complete interrupt request + * This function handles USART2 TX complete interrupt request * * @note * @@ -579,17 +579,17 @@ void USART2_TX_IRQHandler(void) /* enter interrupt */ rt_interrupt_enter(); - if (USART2->IF & USART_IF_TXC) - { - /* invoke callback function */ - if (usartCbTable[4].cbFunc != RT_NULL) - { - (usartCbTable[4].cbFunc)(usartCbTable[4].userPtr); - } + if (USART2->IF & USART_IF_TXC) + { + /* invoke callback function */ + if (usartCbTable[4].cbFunc != RT_NULL) + { + (usartCbTable[4].cbFunc)(usartCbTable[4].userPtr); + } - /* clear interrupt */ - BITBAND_Peripheral(&(USART2->IFC), _USART_IF_TXC_SHIFT, 0x1UL); - } + /* clear interrupt */ + BITBAND_Peripheral(&(USART2->IFC), _USART_IF_TXC_SHIFT, 0x1UL); + } /* leave interrupt */ rt_interrupt_leave(); @@ -597,34 +597,34 @@ void USART2_TX_IRQHandler(void) /***************************************************************************//** * @brief - * Common USART2 RX interrupt handler + * Common USART2 RX interrupt handler * * @details - * This function handles USART2 RX data valid interrupt request + * This function handles USART2 RX data valid interrupt request * * @note * ******************************************************************************/ void USART2_RX_IRQHandler(void) { - if (USART2->IF & USART_IF_RXDATAV) - { - /* invoke callback function */ - if (usartCbTable[5].cbFunc != RT_NULL) - { - (usartCbTable[5].cbFunc)(usartCbTable[5].userPtr); - } - } + if (USART2->IF & USART_IF_RXDATAV) + { + /* invoke callback function */ + if (usartCbTable[5].cbFunc != RT_NULL) + { + (usartCbTable[5].cbFunc)(usartCbTable[5].userPtr); + } + } } #endif #if defined(UART_PRESENT) /***************************************************************************//** * @brief - * Common UART0 TX interrupt handler + * Common UART0 TX interrupt handler * * @details - * This function handles UART0 TX complete interrupt request + * This function handles UART0 TX complete interrupt request * * @note * @@ -634,17 +634,17 @@ void UART0_TX_IRQHandler(void) /* enter interrupt */ rt_interrupt_enter(); - if (UART0->IF & UART_IF_TXC) - { - /* invoke callback function */ - if (usartCbTable[USART_COUNT * 2].cbFunc != RT_NULL) - { - (usartCbTable[USART_COUNT * 2].cbFunc)(usartCbTable[USART_COUNT * 2].userPtr); - } + if (UART0->IF & UART_IF_TXC) + { + /* invoke callback function */ + if (usartCbTable[USART_COUNT * 2].cbFunc != RT_NULL) + { + (usartCbTable[USART_COUNT * 2].cbFunc)(usartCbTable[USART_COUNT * 2].userPtr); + } - /* clear interrupt */ - BITBAND_Peripheral(&(UART0->IFC), _UART_IF_TXC_SHIFT, 0x1UL); - } + /* clear interrupt */ + BITBAND_Peripheral(&(UART0->IFC), _UART_IF_TXC_SHIFT, 0x1UL); + } /* leave interrupt */ rt_interrupt_leave(); @@ -652,34 +652,34 @@ void UART0_TX_IRQHandler(void) /***************************************************************************//** * @brief - * Common UART0 RX interrupt handler + * Common UART0 RX interrupt handler * * @details - * This function handles UART0 RX data valid interrupt request + * This function handles UART0 RX data valid interrupt request * * @note * ******************************************************************************/ void UART0_RX_IRQHandler(void) { - if (UART0->IF & UART_IF_RXDATAV) - { - /* invoke callback function */ - if (usartCbTable[USART_COUNT * 2 + 1].cbFunc != RT_NULL) - { - (usartCbTable[USART_COUNT * 2 + 1].cbFunc)(usartCbTable[USART_COUNT * 2 + 1].userPtr); - } - } + if (UART0->IF & UART_IF_RXDATAV) + { + /* invoke callback function */ + if (usartCbTable[USART_COUNT * 2 + 1].cbFunc != RT_NULL) + { + (usartCbTable[USART_COUNT * 2 + 1].cbFunc)(usartCbTable[USART_COUNT * 2 + 1].userPtr); + } + } } #endif #if (defined(UART_PRESENT) && (UART_COUNT > 1)) /***************************************************************************//** * @brief - * Common UART1 TX interrupt handler + * Common UART1 TX interrupt handler * * @details - * This function handles UART1 TX complete interrupt request + * This function handles UART1 TX complete interrupt request * * @note * @@ -689,17 +689,17 @@ void UART1_TX_IRQHandler(void) /* enter interrupt */ rt_interrupt_enter(); - if (UART1->IF & UART_IF_TXC) - { - /* invoke callback function */ - if (usartCbTable[USART_COUNT * 2 + 2].cbFunc != RT_NULL) - { - (usartCbTable[USART_COUNT * 2 + 2].cbFunc)(usartCbTable[USART_COUNT * 2 + 2].userPtr); - } + if (UART1->IF & UART_IF_TXC) + { + /* invoke callback function */ + if (usartCbTable[USART_COUNT * 2 + 2].cbFunc != RT_NULL) + { + (usartCbTable[USART_COUNT * 2 + 2].cbFunc)(usartCbTable[USART_COUNT * 2 + 2].userPtr); + } - /* clear interrupt */ - BITBAND_Peripheral(&(UART1->IFC), _UART_IF_TXC_SHIFT, 0x1UL); - } + /* clear interrupt */ + BITBAND_Peripheral(&(UART1->IFC), _UART_IF_TXC_SHIFT, 0x1UL); + } /* leave interrupt */ rt_interrupt_leave(); @@ -707,106 +707,106 @@ void UART1_TX_IRQHandler(void) /***************************************************************************//** * @brief - * Common UART1 RX interrupt handler + * Common UART1 RX interrupt handler * * @details - * This function handles UART1 RX data valid interrupt request + * This function handles UART1 RX data valid interrupt request * * @note * ******************************************************************************/ void UART1_RX_IRQHandler(void) { - if (UART1->IF & UART_IF_RXDATAV) - { - /* invoke callback function */ - if (usartCbTable[USART_COUNT * 2 + 3].cbFunc != RT_NULL) - { - (usartCbTable[USART_COUNT * 2 + 3].cbFunc)(usartCbTable[USART_COUNT * 2 + 3].userPtr); - } - } + if (UART1->IF & UART_IF_RXDATAV) + { + /* invoke callback function */ + if (usartCbTable[USART_COUNT * 2 + 3].cbFunc != RT_NULL) + { + (usartCbTable[USART_COUNT * 2 + 3].cbFunc)(usartCbTable[USART_COUNT * 2 + 3].userPtr); + } + } } #endif #if defined(LEUART_PRESENT) /***************************************************************************//** * @brief - * Common LEUART0 interrupt handler + * Common LEUART0 interrupt handler * * @details - * This function handles LEUART0 interrupt request + * This function handles LEUART0 interrupt request * * @note * ******************************************************************************/ void LEUART0_IRQHandler(void) { - if (LEUART0->IF & LEUART_IF_RXDATAV) - { - /* invoke callback function */ - if (leuartCbTable[0].cbFunc != RT_NULL) - { - (leuartCbTable[0].cbFunc)(leuartCbTable[0].userPtr); - } - } + if (LEUART0->IF & LEUART_IF_RXDATAV) + { + /* invoke callback function */ + if (leuartCbTable[0].cbFunc != RT_NULL) + { + (leuartCbTable[0].cbFunc)(leuartCbTable[0].userPtr); + } + } } #endif #if (defined(LEUART_PRESENT) && (LEUART_COUNT > 1)) /***************************************************************************//** * @brief - * Common LEUART1 interrupt handler + * Common LEUART1 interrupt handler * * @details - * This function handles LEUART1 interrupt request + * This function handles LEUART1 interrupt request * * @note * ******************************************************************************/ void LEUART1_IRQHandler(void) { - if (LEUART1->IF & LEUART_IF_RXDATAV) - { - /* invoke callback function */ - if (leuartCbTable[1].cbFunc != RT_NULL) - { - (leuartCbTable[1].cbFunc)(leuartCbTable[1].userPtr); - } - } + if (LEUART1->IF & LEUART_IF_RXDATAV) + { + /* invoke callback function */ + if (leuartCbTable[1].cbFunc != RT_NULL) + { + (leuartCbTable[1].cbFunc)(leuartCbTable[1].userPtr); + } + } } #endif #if defined(I2C_PRESENT) /***************************************************************************//** * @brief - * Common IIC0 interrupt handler + * Common IIC0 interrupt handler * * @details - * This function handles IIC0 slave mode interrupt requests + * This function handles IIC0 slave mode interrupt requests * * @note * ******************************************************************************/ void I2C0_IRQHandler(void) { - if ((I2C0->IF & I2C_IF_ADDR) || \ - (I2C0->IF & I2C_IF_RXDATAV) || \ - (I2C0->IF & I2C_IF_SSTOP)) - { - /* invoke callback function */ - if (iicCbTable[0].cbFunc != RT_NULL) - { - (iicCbTable[0].cbFunc)(iicCbTable[0].userPtr); - } - } - - I2C_IntClear(I2C0, I2C_IFC_ADDR | I2C_IFC_SSTOP); + if ((I2C0->IF & I2C_IF_ADDR) || \ + (I2C0->IF & I2C_IF_RXDATAV) || \ + (I2C0->IF & I2C_IF_SSTOP)) + { + /* invoke callback function */ + if (iicCbTable[0].cbFunc != RT_NULL) + { + (iicCbTable[0].cbFunc)(iicCbTable[0].userPtr); + } + } + + I2C_IntClear(I2C0, I2C_IFC_ADDR | I2C_IFC_SSTOP); } #endif /***************************************************************************//** * @brief - * EFM32 common interrupt handlers register function + * EFM32 common interrupt handlers register function * * @details * @@ -815,42 +815,42 @@ void I2C0_IRQHandler(void) ******************************************************************************/ void efm32_irq_hook_register(efm32_irq_hook_init_t *hook) { - switch (hook->type) - { - case efm32_irq_type_dma: - dmaCbTable[hook->unit].cbFunc = hook->cbFunc; - dmaCbTable[hook->unit].userPtr = hook->userPtr; - break; - - case efm32_irq_type_rtc: - rtcCbTable[hook->unit].cbFunc = hook->cbFunc; - rtcCbTable[hook->unit].userPtr = hook->userPtr; - break; - - case efm32_irq_type_timer: - timerCbTable[hook->unit].cbFunc = hook->cbFunc; - timerCbTable[hook->unit].userPtr = hook->userPtr; - break; - - case efm32_irq_type_letimer: - letimerCbTable[hook->unit].cbFunc = hook->cbFunc; - letimerCbTable[hook->unit].userPtr = hook->userPtr; - break; - - case efm32_irq_type_gpio: - gpioCbTable[hook->unit].cbFunc = hook->cbFunc; - gpioCbTable[hook->unit].userPtr = hook->userPtr; - break; - - case efm32_irq_type_acmp: - acmpCbTable[hook->unit].cbFunc = hook->cbFunc; - acmpCbTable[hook->unit].userPtr = hook->userPtr; - break; + switch (hook->type) + { + case efm32_irq_type_dma: + dmaCbTable[hook->unit].cbFunc = hook->cbFunc; + dmaCbTable[hook->unit].userPtr = hook->userPtr; + break; + + case efm32_irq_type_rtc: + rtcCbTable[hook->unit].cbFunc = hook->cbFunc; + rtcCbTable[hook->unit].userPtr = hook->userPtr; + break; + + case efm32_irq_type_timer: + timerCbTable[hook->unit].cbFunc = hook->cbFunc; + timerCbTable[hook->unit].userPtr = hook->userPtr; + break; + + case efm32_irq_type_letimer: + letimerCbTable[hook->unit].cbFunc = hook->cbFunc; + letimerCbTable[hook->unit].userPtr = hook->userPtr; + break; + + case efm32_irq_type_gpio: + gpioCbTable[hook->unit].cbFunc = hook->cbFunc; + gpioCbTable[hook->unit].userPtr = hook->userPtr; + break; + + case efm32_irq_type_acmp: + acmpCbTable[hook->unit].cbFunc = hook->cbFunc; + acmpCbTable[hook->unit].userPtr = hook->userPtr; + break; #if defined(USART_PRESENT) - case efm32_irq_type_usart: - usartCbTable[hook->unit].cbFunc = hook->cbFunc; - usartCbTable[hook->unit].userPtr = hook->userPtr; - break; + case efm32_irq_type_usart: + usartCbTable[hook->unit].cbFunc = hook->cbFunc; + usartCbTable[hook->unit].userPtr = hook->userPtr; + break; #endif #if defined(LEUART_PRESENT) case efm32_irq_type_leuart: @@ -859,17 +859,17 @@ void efm32_irq_hook_register(efm32_irq_hook_init_t *hook) break; #endif #if defined(I2C_PRESENT) - case efm32_irq_type_iic: - iicCbTable[hook->unit].cbFunc = hook->cbFunc; - iicCbTable[hook->unit].userPtr = hook->userPtr; - break; + case efm32_irq_type_iic: + iicCbTable[hook->unit].cbFunc = hook->cbFunc; + iicCbTable[hook->unit].userPtr = hook->userPtr; + break; #endif - default: - break; - } + default: + break; + } - hdl_debug("Hook Registered: type: %s, unit: %x, cbFunc: %x, userPtr: %x\n", \ - hook->type, hook->unit, hook->cbFunc, hook->userPtr); + hdl_debug("Hook Registered: type: %s, unit: %x, cbFunc: %x, userPtr: %x\n", \ + hook->type, hook->unit, hook->cbFunc, hook->userPtr); } /***************************************************************************//** diff --git a/bsp/efm32/hdl_interrupt.h b/bsp/efm32/hdl_interrupt.h index 01f7adf9f8..d2f73bda57 100644 --- a/bsp/efm32/hdl_interrupt.h +++ b/bsp/efm32/hdl_interrupt.h @@ -21,31 +21,31 @@ /* Exported types ------------------------------------------------------------*/ enum efm32_irq_hook_type_t { - efm32_irq_type_dma = 0, - efm32_irq_type_rtc, - efm32_irq_type_timer, + efm32_irq_type_dma = 0, + efm32_irq_type_rtc, + efm32_irq_type_timer, efm32_irq_type_letimer, - efm32_irq_type_gpio, - efm32_irq_type_acmp, - efm32_irq_type_usart, - efm32_irq_type_leuart, - efm32_irq_type_iic + efm32_irq_type_gpio, + efm32_irq_type_acmp, + efm32_irq_type_usart, + efm32_irq_type_leuart, + efm32_irq_type_iic }; typedef void (*efm32_irq_callback_t)(rt_device_t device); typedef struct { - enum efm32_irq_hook_type_t type; - rt_uint8_t unit; - efm32_irq_callback_t cbFunc; - void *userPtr; + enum efm32_irq_hook_type_t type; + rt_uint8_t unit; + efm32_irq_callback_t cbFunc; + void *userPtr; } efm32_irq_hook_init_t; typedef struct { - efm32_irq_callback_t cbFunc; - void *userPtr; + efm32_irq_callback_t cbFunc; + void *userPtr; } efm32_irq_hook_t; /* Exported constants --------------------------------------------------------*/ diff --git a/bsp/efm32/httpd.c b/bsp/efm32/httpd.c index c7094d509a..02c81be84d 100644 --- a/bsp/efm32/httpd.c +++ b/bsp/efm32/httpd.c @@ -1,8 +1,8 @@ /***************************************************************************//** - * @file httpd.c - * @brief Simple http server demo application + * @file httpd.c + * @brief Simple http server demo application * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -10,8 +10,8 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes - * 2011-07-04 onelife Derive from Energy Micro demo application + * Date Author Notes + * 2011-07-04 onelife Derive from Energy Micro demo application ******************************************************************************/ /**************************************************************************//** @@ -94,29 +94,29 @@ static int temp, vdd; static char indexdata[700]; static const char indexdata1[] = - "HTTP/1.0 200 OK\r\n\ - Content-type: text/html\r\n\ - Pragma: no-cache\r\n\ - Refresh: 5\r\n\ - \r\n\ - \ - EFM32 HTTPD DEMO\ - \ -

This is a simple http server

\ -

Ethernet controller: ENC28J60\ -

Refreshing timers: "; + "HTTP/1.0 200 OK\r\n\ + Content-type: text/html\r\n\ + Pragma: no-cache\r\n\ + Refresh: 5\r\n\ + \r\n\ + \ + EFM32 HTTPD DEMO\ + \ +

This is a simple http server

\ +

Ethernet controller: ENC28J60\ +

Refreshing timers: "; static const char indexdata2[] = - "

Current Vdd: "; + "

Current Vdd: "; static const char indexdata3[] = - " V\ -

Current temperature: "; + " V\ +

Current temperature: "; static const char indexdata4[] = - " C\ - \ - "; + " C\ + \ + "; /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ @@ -169,9 +169,9 @@ static err_t http_recv(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err counter++; } - vdd = rt_hw_get_vdd(); - rt_sprintf(&indexdata[counter], "%1d.%02d", vdd / 100, vdd % 100); - counter += 4; + vdd = rt_hw_get_vdd(); + rt_sprintf(&indexdata[counter], "%1d.%02d", vdd / 100, vdd % 100); + counter += 4; for (i = 0; i < sizeof(indexdata3) - 1; i++) { @@ -179,15 +179,15 @@ static err_t http_recv(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err counter++; } - temp = rt_hw_get_temp(); + temp = rt_hw_get_temp(); /*Set temperature sign*/ if (temp < 0) { indexdata[counter] = '-'; counter++; } - rt_sprintf(&indexdata[counter], "%02d.%02d\n", temp / 100, temp % 100); - counter += 5; + rt_sprintf(&indexdata[counter], "%02d.%02d\n", temp / 100, temp % 100); + counter += 5; for (i = 0; i < sizeof(indexdata4); i++) { diff --git a/bsp/efm32/mma7455l.h b/bsp/efm32/mma7455l.h index 2ea2cdf34e..c746fd45da 100644 --- a/bsp/efm32/mma7455l.h +++ b/bsp/efm32/mma7455l.h @@ -1,9 +1,9 @@ /***************************************************************************//** - * @file mma7455l.c - * @brief Header file of Freescale MMA7455L 3 axis Low-g digital output + * @file mma7455l.c + * @brief Header file of Freescale MMA7455L 3 axis Low-g digital output * accelerometer * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -11,101 +11,101 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes - * 2011-08-02 onelife Initial creation + * Date Author Notes + * 2011-08-02 onelife Initial creation ******************************************************************************/ #ifndef __MMA7455L_H__ #define __MMA7455L_H__ -#define XOUTL 0x00 //00 10 bits output value X LSB (Read only) -#define XOUTH 0x01 //01 10 bits output value X MSB (Read only) -#define YOUTL 0x02 //02 10 bits output value Y LSB (Read only) -#define YOUTH 0x03 //03 10 bits output value Y MSB (Read only) -#define ZOUTL 0x04 //04 10 bits output value Z LSB (Read only) -#define ZOUTH 0x05 //05 10 bits output value Z MSB (Read only) -#define XOUT8 0x06 //06 8 bits Output value X (Read only) -#define YOUT8 0x07 //07 8 bits Output value Y (Read only) -#define ZOUT8 0x08 //08 8 bits Output value Z (Read only) -#define STATUS 0x09 //09 Status registers (Read only) -#define DETSRC 0x0A //10 Detection source registers (Read only) -#define TOUT 0x0B //11 Temperature output value (Optional) -#define RESERVED1 0x0C //12 Reserved -#define I2CAD 0x0D //13 I2C device address (Bit[6:0]: Read only, Bit[7]: Read/Write) -#define USRINF 0x0E //14 User information (Optional, Read only) -#define WHOAMI 0x0F //15 Who am I value (Optional, Read only) -#define XOFFL 0x10 //16 Offset drift X value (LSB) (Read/Write) -#define XOFFH 0x11 //17 Offset drift X value (MSB) (Read/Write) -#define YOFFL 0x12 //18 Offset drift Y value (LSB) (Read/Write) -#define YOFFH 0x13 //19 Offset drift Y value (MSB) (Read/Write) -#define ZOFFL 0x14 //20 Offset drift Z value (LSB) (Read/Write) -#define ZOFFH 0x15 //21 Offset drift Z value (MSB) (Read/Write) -#define MCTL 0x16 //22 Mode control (Read/Write) -#define INTRST 0x17 //23 Interrupt latch reset (Read/Write) -#define CTL1 0x18 //24 Control 1 (Read/Write) -#define CTL2 0x19 //25 Control 2 (Read/Write) -#define LDTH 0x1A //26 Level detection threshold limit value (Read/Write) -#define PDTH 0x1B //27 Pulse detection threshold limit value (Read/Write) -#define PW 0x1C //28 Pulse duration value (Read/Write) -#define LT 0x1D //29 Latency time value (Read/Write) -#define TW 0x1E //30 Time window for second pulse value(Read/Write) -#define RESERVED2 0x1F //31 Reserved +#define XOUTL 0x00 //00 10 bits output value X LSB (Read only) +#define XOUTH 0x01 //01 10 bits output value X MSB (Read only) +#define YOUTL 0x02 //02 10 bits output value Y LSB (Read only) +#define YOUTH 0x03 //03 10 bits output value Y MSB (Read only) +#define ZOUTL 0x04 //04 10 bits output value Z LSB (Read only) +#define ZOUTH 0x05 //05 10 bits output value Z MSB (Read only) +#define XOUT8 0x06 //06 8 bits Output value X (Read only) +#define YOUT8 0x07 //07 8 bits Output value Y (Read only) +#define ZOUT8 0x08 //08 8 bits Output value Z (Read only) +#define STATUS 0x09 //09 Status registers (Read only) +#define DETSRC 0x0A //10 Detection source registers (Read only) +#define TOUT 0x0B //11 Temperature output value (Optional) +#define RESERVED1 0x0C //12 Reserved +#define I2CAD 0x0D //13 I2C device address (Bit[6:0]: Read only, Bit[7]: Read/Write) +#define USRINF 0x0E //14 User information (Optional, Read only) +#define WHOAMI 0x0F //15 Who am I value (Optional, Read only) +#define XOFFL 0x10 //16 Offset drift X value (LSB) (Read/Write) +#define XOFFH 0x11 //17 Offset drift X value (MSB) (Read/Write) +#define YOFFL 0x12 //18 Offset drift Y value (LSB) (Read/Write) +#define YOFFH 0x13 //19 Offset drift Y value (MSB) (Read/Write) +#define ZOFFL 0x14 //20 Offset drift Z value (LSB) (Read/Write) +#define ZOFFH 0x15 //21 Offset drift Z value (MSB) (Read/Write) +#define MCTL 0x16 //22 Mode control (Read/Write) +#define INTRST 0x17 //23 Interrupt latch reset (Read/Write) +#define CTL1 0x18 //24 Control 1 (Read/Write) +#define CTL2 0x19 //25 Control 2 (Read/Write) +#define LDTH 0x1A //26 Level detection threshold limit value (Read/Write) +#define PDTH 0x1B //27 Pulse detection threshold limit value (Read/Write) +#define PW 0x1C //28 Pulse duration value (Read/Write) +#define LT 0x1D //29 Latency time value (Read/Write) +#define TW 0x1E //30 Time window for second pulse value(Read/Write) +#define RESERVED2 0x1F //31 Reserved /* For DETSRC */ -#define DETSRC_INT_1 (0x01 << 0) -#define DETSRC_INT_2 (0x01 << 1) -#define DETSRC_PULSE_Z (0x01 << 2) -#define DETSRC_PULSE_Y (0x01 << 3) -#define DETSRC_PULSE_X (0x01 << 4) -#define DETSRC_LEVEL_Z (0x01 << 5) -#define DETSRC_LEVEL_Y (0x01 << 6) -#define DETSRC_LEVEL_X (0x01 << 7) +#define DETSRC_INT_1 (0x01 << 0) +#define DETSRC_INT_2 (0x01 << 1) +#define DETSRC_PULSE_Z (0x01 << 2) +#define DETSRC_PULSE_Y (0x01 << 3) +#define DETSRC_PULSE_X (0x01 << 4) +#define DETSRC_LEVEL_Z (0x01 << 5) +#define DETSRC_LEVEL_Y (0x01 << 6) +#define DETSRC_LEVEL_X (0x01 << 7) /* For MCTL */ -#define MCTL_SHIFT_MODE (0) -#define MCTL_SHIFT_G (2) -#define MCTL_MASK_MODE (0x03) -#define MCTL_MASK_G (0x0c) -#define MCTL_MODE_STANDBY (0x00 << MCTL_SHIFT_MODE) -#define MCTL_MODE_MEASUREMENT (0x01 << MCTL_SHIFT_MODE) -#define MCTL_MODE_LEVEL (0x02 << MCTL_SHIFT_MODE) -#define MCTL_MODE_PULSE (0x03 << MCTL_SHIFT_MODE) -#define MCTL_RANGE_8G (0x00 << MCTL_SHIFT_G) -#define MCTL_RANGE_4G (0x02 << MCTL_SHIFT_G) -#define MCTL_RANGE_2G (0x01 << MCTL_SHIFT_G) -#define MCTL_PIN_INT1 (0x01 << 6) +#define MCTL_SHIFT_MODE (0) +#define MCTL_SHIFT_G (2) +#define MCTL_MASK_MODE (0x03) +#define MCTL_MASK_G (0x0c) +#define MCTL_MODE_STANDBY (0x00 << MCTL_SHIFT_MODE) +#define MCTL_MODE_MEASUREMENT (0x01 << MCTL_SHIFT_MODE) +#define MCTL_MODE_LEVEL (0x02 << MCTL_SHIFT_MODE) +#define MCTL_MODE_PULSE (0x03 << MCTL_SHIFT_MODE) +#define MCTL_RANGE_8G (0x00 << MCTL_SHIFT_G) +#define MCTL_RANGE_4G (0x02 << MCTL_SHIFT_G) +#define MCTL_RANGE_2G (0x01 << MCTL_SHIFT_G) +#define MCTL_PIN_INT1 (0x01 << 6) /* For INTRST */ -#define INTRST_INT_1 (0x01 << 0) -#define INTRST_INT_2 (0x01 << 1) +#define INTRST_INT_1 (0x01 << 0) +#define INTRST_INT_2 (0x01 << 1) /* For CTL1 */ -#define CTL1_SHIFT_INTPIN (0) -#define CTL1_SHIFT_INT (1) -#define CTL1_SHIFT_AXES (3) -#define CTL1_SHIFT_THRESHOLD (6) -#define CTL1_SHIFT_BANDWIDTH (7) -#define CTL1_MASK_AXES (0x38) -#define CTL1_INTPIN_INVERSE (0x01 << CTL1_SHIFT_INTPIN) -#define CTL1_INT_LEVEL_PULSE (0x00 << CTL1_SHIFT_INT) -#define CTL1_INT_PULSE_LEVEL (0x01 << CTL1_SHIFT_INT) -#define CTL1_INT_SINGLE_DOUBLE (0x02 << CTL1_SHIFT_INT) -#define CTL1_X_DISABLE (0x01 << CTL1_SHIFT_AXES) -#define CTL1_Y_DISABLE (0x02 << CTL1_SHIFT_AXES) -#define CTL1_Z_DISABLE (0x04 << CTL1_SHIFT_AXES) -#define CTL1_THRESHOLD_ABSOLUTE (0x00 << CTL1_SHIFT_THRESHOLD) -#define CTL1_THRESHOLD_INTEGER (0x01 << CTL1_SHIFT_THRESHOLD) -#define CTL1_BANDWIDTH_62_5HZ (0x00 << CTL1_SHIFT_BANDWIDTH) -#define CTL1_BANDWIDTH_125HZ (0x01 << CTL1_SHIFT_BANDWIDTH) +#define CTL1_SHIFT_INTPIN (0) +#define CTL1_SHIFT_INT (1) +#define CTL1_SHIFT_AXES (3) +#define CTL1_SHIFT_THRESHOLD (6) +#define CTL1_SHIFT_BANDWIDTH (7) +#define CTL1_MASK_AXES (0x38) +#define CTL1_INTPIN_INVERSE (0x01 << CTL1_SHIFT_INTPIN) +#define CTL1_INT_LEVEL_PULSE (0x00 << CTL1_SHIFT_INT) +#define CTL1_INT_PULSE_LEVEL (0x01 << CTL1_SHIFT_INT) +#define CTL1_INT_SINGLE_DOUBLE (0x02 << CTL1_SHIFT_INT) +#define CTL1_X_DISABLE (0x01 << CTL1_SHIFT_AXES) +#define CTL1_Y_DISABLE (0x02 << CTL1_SHIFT_AXES) +#define CTL1_Z_DISABLE (0x04 << CTL1_SHIFT_AXES) +#define CTL1_THRESHOLD_ABSOLUTE (0x00 << CTL1_SHIFT_THRESHOLD) +#define CTL1_THRESHOLD_INTEGER (0x01 << CTL1_SHIFT_THRESHOLD) +#define CTL1_BANDWIDTH_62_5HZ (0x00 << CTL1_SHIFT_BANDWIDTH) +#define CTL1_BANDWIDTH_125HZ (0x01 << CTL1_SHIFT_BANDWIDTH) /* For CTL2 */ -#define CTL1_SHIFT_LEVEL (0) -#define CTL1_SHIFT_PULSE (1) -#define CTL1_SHIFT_DRIVE (2) -#define CTL2_LEVEL_OR (0x00 << CTL1_SHIFT_LEVEL) -#define CTL2_LEVEL_AND (0x01 << CTL1_SHIFT_LEVEL) -#define CTL2_PULSE_OR (0x00 << CTL1_SHIFT_PULSE) -#define CTL2_PULSE_AND (0x01 << CTL1_SHIFT_PULSE) -#define CTL2_DRIVE_STANDARD (0x00 << CTL1_SHIFT_DRIVE) -#define CTL2_DRIVE_STRONG (0x01 << CTL1_SHIFT_DRIVE) +#define CTL1_SHIFT_LEVEL (0) +#define CTL1_SHIFT_PULSE (1) +#define CTL1_SHIFT_DRIVE (2) +#define CTL2_LEVEL_OR (0x00 << CTL1_SHIFT_LEVEL) +#define CTL2_LEVEL_AND (0x01 << CTL1_SHIFT_LEVEL) +#define CTL2_PULSE_OR (0x00 << CTL1_SHIFT_PULSE) +#define CTL2_PULSE_AND (0x01 << CTL1_SHIFT_PULSE) +#define CTL2_DRIVE_STANDARD (0x00 << CTL1_SHIFT_DRIVE) +#define CTL2_DRIVE_STRONG (0x01 << CTL1_SHIFT_DRIVE) #endif /* __MMA7455L_H__ */ diff --git a/bsp/efm32/rtconfig.h b/bsp/efm32/rtconfig.h index 040f07fa02..6e12d1ff6b 100644 --- a/bsp/efm32/rtconfig.h +++ b/bsp/efm32/rtconfig.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file rtconfig.h * @brief RT-Thread config file - * COPYRIGHT (C) 2009, RT-Thread Development Team + * COPYRIGHT (C) 2009, RT-Thread Development Team * @author * @version 1.0 ******************************************************************************* @@ -22,23 +22,23 @@ #define EFM32GG_DK3750 /* RT_NAME_MAX */ -#define RT_NAME_MAX (8) +#define RT_NAME_MAX (8) /* RT_ALIGN_SIZE */ -#define RT_ALIGN_SIZE (4) +#define RT_ALIGN_SIZE (4) /* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX (32) +#define RT_THREAD_PRIORITY_MAX (32) /* Tick per Second */ -#define RT_TICK_PER_SECOND (100) +#define RT_TICK_PER_SECOND (100) /* SECTION: RT_DEBUG */ #define RT_DEBUG #define RT_DEBUG_COLOR -//#define RT_DEBUG_MEM (1) -//#define RT_DEBUG_SCHEDULER (1) -//#define RT_DEBUG_IPC (1) +//#define RT_DEBUG_MEM (1) +//#define RT_DEBUG_SCHEDULER (1) +//#define RT_DEBUG_IPC (1) //#define THREAD_DEBUG //#define IRQ_DEBUG #define RT_USING_OVERFLOW_CHECK @@ -69,9 +69,9 @@ /* Using Software Timer */ /* #define RT_USING_TIMER_SOFT */ -#define RT_TIMER_THREAD_PRIO (4) -#define RT_TIMER_THREAD_STACK_SIZE (512) -#define RT_TIMER_TICK_PER_SECOND (10) +#define RT_TIMER_THREAD_PRIO (4) +#define RT_TIMER_THREAD_STACK_SIZE (512) +#define RT_TIMER_TICK_PER_SECOND (10) /* SECTION: IPC */ /* Using Semaphore*/ @@ -134,10 +134,10 @@ #define EFM32_SPI_CLK_MODE(mode) (mode << 3) /* clock mode */ #if defined(EFM32_G8XX_STK) -//#define RT_USING_USART0 (0x0UL) -//#define RT_USART0_SYNC_MODE (EFM32_SPI_MASTER) -//#define RT_USART0_NAME "spi0" -//#define RT_USART0_USING_DMA (0x1UL) +//#define RT_USING_USART0 (0x0UL) +//#define RT_USART0_SYNC_MODE (EFM32_SPI_MASTER) +//#define RT_USART0_NAME "spi0" +//#define RT_USART0_USING_DMA (0x1UL) #elif defined(EFM32_GXXX_DK) #define RT_USING_USART0 (0x2UL) #define RT_USART0_SYNC_MODE (EFM32_SPI_MASTER | EFM32_SPI_AUTOCS | \ @@ -165,28 +165,28 @@ #endif /* SECTION: IIC options */ -//#define RT_USING_IIC0 0x3UL -#define RT_IIC0_NAME "iic0" +//#define RT_USING_IIC0 0x3UL +#define RT_IIC0_NAME "iic0" /* SECTION: ACMP options */ //#define RT_USING_ACMP0 -#define RT_ACMP0_NAME "acmp0" +#define RT_ACMP0_NAME "acmp0" /* SECTION: ADC options */ #define RT_USING_ADC0 -#define RT_ADC0_NAME "adc0" +#define RT_ADC0_NAME "adc0" #if defined(RT_USING_ADC0) #define RT_USING_MISC #endif /* SECTION: TIMER options */ -//#define RT_USING_TIMER2 (0x00) /* Continuous mode */ -#define RT_TIMER2_NAME "tmr2" +//#define RT_USING_TIMER2 (0x00) /* Continuous mode */ +#define RT_TIMER2_NAME "tmr2" /* SECTION: RTC options */ #if (defined(EFM32_G8XX_STK) || defined(EFM32_GXXX_DK) || defined(EFM32GG_DK3750)) #define RT_USING_RTC -#define RT_RTC_NAME "rtc" +#define RT_RTC_NAME "rtc" #endif /* SECTION: Serial options */ @@ -199,9 +199,9 @@ #define EFM_LEUART1 (0x21UL) #if defined(EFM32_G8XX_STK) -#define RT_CONSOLE_DEVICE (EFM_USART1) +#define RT_CONSOLE_DEVICE (EFM_USART1) #elif defined(EFM32_GXXX_DK) -#define RT_CONSOLE_DEVICE (EFM_USART1) +#define RT_CONSOLE_DEVICE (EFM_USART1) #elif defined(EFM32GG_DK3750) #if defined(EFM32GG_DK3750_USING_LEUART1) #define RT_CONSOLE_DEVICE (EFM_LEUART1) @@ -218,7 +218,7 @@ /* SECTION: Console options */ #define RT_USING_CONSOLE /* the buffer size of console*/ -#define RT_CONSOLEBUF_SIZE (128) +#define RT_CONSOLEBUF_SIZE (128) /* SECTION: finsh, a C-Express shell */ #define RT_USING_FINSH @@ -227,12 +227,12 @@ #define FINSH_USING_DESCRIPTION /* SECTION: Peripheral devices */ -#define EFM32_INTERFACE_ADC (0) -#define EFM32_INTERFACE_IIC (1) -#define EFM32_INTERFACE_SPI (2) +#define EFM32_INTERFACE_ADC (0) +#define EFM32_INTERFACE_IIC (1) +#define EFM32_INTERFACE_SPI (2) #if (defined(EFM32_GXXX_DK) || defined(EFM32GG_DK3750)) -//#define EFM32_USING_ACCEL EFM32_INTERFACE_IIC /* Three axis accelerometer */ -//#define EFM32_USING_SFLASH /* SPI Flash */ +//#define EFM32_USING_ACCEL EFM32_INTERFACE_IIC /* Three axis accelerometer */ +//#define EFM32_USING_SFLASH /* SPI Flash */ #define EFM32_USING_SPISD /* MicroSD card */ //#define EFM32_USING_ETHERNET /* Ethernet controller */ //#define EFM32_USING_LCD /* TFT LCD */ @@ -241,30 +241,30 @@ #if defined(EFM32_USING_ACCEL) #if (EFM32_USING_ACCEL == EFM32_INTERFACE_ADC) -#define ACCEL_USING_DEVICE_NAME RT_ADC0_NAME -#define ACCEL_USING_DMA (0x3UL) /* For multiple channels scan mode */ +#define ACCEL_USING_DEVICE_NAME RT_ADC0_NAME +#define ACCEL_USING_DMA (0x3UL) /* For multiple channels scan mode */ #elif (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC) -#define ACCEL_USING_DEVICE_NAME RT_IIC0_NAME +#define ACCEL_USING_DEVICE_NAME RT_IIC0_NAME #endif #endif #if defined(EFM32_USING_SFLASH) -#define SFLASH_USING_DEVICE_NAME RT_USART0_NAME +#define SFLASH_USING_DEVICE_NAME RT_USART0_NAME #endif #if defined(EFM32_USING_SPISD) -#define SPISD_USING_DEVICE_NAME RT_USART0_NAME -#define SPISD_DEVICE_NAME "spiSd" +#define SPISD_USING_DEVICE_NAME RT_USART0_NAME +#define SPISD_DEVICE_NAME "spiSd" #endif #if defined(EFM32_USING_ETHERNET) #if defined(EFM32_GXXX_DK) - #define ETH_USING_DEVICE_NAME RT_USART2_NAME + #define ETH_USING_DEVICE_NAME RT_USART2_NAME #elif defined(EFM32GG_DK3750) - #define ETH_USING_DEVICE_NAME RT_USART1_NAME + #define ETH_USING_DEVICE_NAME RT_USART1_NAME #endif -#define ETH_DEVICE_NAME "spiEth" -#define ETH_ADDR_DEFAULT {0x00, 0x01, 0x02, 0x03, 0x04, 0x05} +#define ETH_DEVICE_NAME "spiEth" +#define ETH_ADDR_DEFAULT {0x00, 0x01, 0x02, 0x03, 0x04, 0x05} #endif /* SECTION: device filesystem */ @@ -272,9 +272,9 @@ #define RT_USING_DFS /* the max number of mounted filesystem */ #define DFS_FILESYSTEMS_MAX (2) -/* the max number of opened files */ +/* the max number of opened files */ #define DFS_FD_MAX (4) -/* the max number of cached sector */ +/* the max number of cached sector */ #define DFS_CACHE_MAX_NUM (4) #endif /* defined(RT_USING_NEWLIB) || defined(EFM32_USING_SPISD) */ #if defined(EFM32_USING_SPISD) @@ -289,8 +289,8 @@ #if defined(EFM32_USING_ETHERNET) #define EFM32_USING_ETH_HTTPD //#define EFM32_USING_ETH_UTILS -//#define hostName "onelife.dyndns.org" -//#define userPwdB64 "dXNlcjpwYXNzd2Q=" +//#define hostName "onelife.dyndns.org" +//#define userPwdB64 "dXNlcjpwYXNzd2Q=" //#define RT_USING_LWIP //#define RT_USING_NETUTILS @@ -309,37 +309,37 @@ //#define RT_LWIP_DNS /* the number of simulatenously active TCP connections*/ -#define RT_LWIP_TCP_PCB_NUM (2) +#define RT_LWIP_TCP_PCB_NUM (2) /* ip address of target*/ -#define RT_LWIP_IPADDR0 (192) -#define RT_LWIP_IPADDR1 (168) -#define RT_LWIP_IPADDR2 (1) -#define RT_LWIP_IPADDR3 (118) +#define RT_LWIP_IPADDR0 (192) +#define RT_LWIP_IPADDR1 (168) +#define RT_LWIP_IPADDR2 (1) +#define RT_LWIP_IPADDR3 (118) /* gateway address of target*/ -#define RT_LWIP_GWADDR0 (192) -#define RT_LWIP_GWADDR1 (168) -#define RT_LWIP_GWADDR2 (1) -#define RT_LWIP_GWADDR3 (1) +#define RT_LWIP_GWADDR0 (192) +#define RT_LWIP_GWADDR1 (168) +#define RT_LWIP_GWADDR2 (1) +#define RT_LWIP_GWADDR3 (1) /* mask address of target*/ -#define RT_LWIP_MSKADDR0 (255) -#define RT_LWIP_MSKADDR1 (255) -#define RT_LWIP_MSKADDR2 (255) -#define RT_LWIP_MSKADDR3 (0) +#define RT_LWIP_MSKADDR0 (255) +#define RT_LWIP_MSKADDR1 (255) +#define RT_LWIP_MSKADDR2 (255) +#define RT_LWIP_MSKADDR3 (0) /* tcp thread options */ -#define RT_LWIP_TCPTHREAD_PRIORITY (12) -#define RT_LWIP_TCPTHREAD_MBOX_SIZE (4) -#define RT_LWIP_TCPTHREAD_STACKSIZE (1024) +#define RT_LWIP_TCPTHREAD_PRIORITY (12) +#define RT_LWIP_TCPTHREAD_MBOX_SIZE (4) +#define RT_LWIP_TCPTHREAD_STACKSIZE (1024) /* ethernet if thread options */ -#define RT_LWIP_ETHTHREAD_PRIORITY (15) -#define RT_LWIP_ETHTHREAD_MBOX_SIZE (4) -#define RT_LWIP_ETHTHREAD_STACKSIZE (512) +#define RT_LWIP_ETHTHREAD_PRIORITY (15) +#define RT_LWIP_ETHTHREAD_MBOX_SIZE (4) +#define RT_LWIP_ETHTHREAD_STACKSIZE (512) #endif /* defined(EFM32_USING_ETHERNET) */ /* SECTION: RTGUI support */ #if defined(EFM32_USING_LCD) -#define LCD_USING_DEVICE_NAME RT_USART1_NAME +#define LCD_USING_DEVICE_NAME RT_USART1_NAME #define LCD_DEVICE_NAME "lcd" /* using RTGUI support */ // #define RT_USING_RTGUI diff --git a/bsp/efm32/startup.c b/bsp/efm32/startup.c index f997c6aadd..b5af1d5833 100644 --- a/bsp/efm32/startup.c +++ b/bsp/efm32/startup.c @@ -10,12 +10,12 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes + * Date Author Notes * 2006-08-31 Bernard first implementation * 2010-12-29 onelife Modify for EFM32 * 2011-12-20 onelife Add RTGUI initialization routine * 2012-02-21 onelife Add energy management initialization routine - * 2012-05-15 onelife Modified to compatible with CMSIS v3 + * 2012-05-15 onelife Modified to compatible with CMSIS v3 ******************************************************************************/ /***************************************************************************//** diff --git a/bsp/frdm-k64f/applications/application.c b/bsp/frdm-k64f/applications/application.c index 3d4448e2a5..bf65b21627 100644 --- a/bsp/frdm-k64f/applications/application.c +++ b/bsp/frdm-k64f/applications/application.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/frdm-k64f/applications/startup.c b/bsp/frdm-k64f/applications/startup.c index 3627cb993b..68e99d3df4 100644 --- a/bsp/frdm-k64f/applications/startup.c +++ b/bsp/frdm-k64f/applications/startup.c @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * + * */ #include diff --git a/bsp/frdm-k64f/board/board.c b/bsp/frdm-k64f/board/board.c index 334f571d69..3e761beb0e 100644 --- a/bsp/frdm-k64f/board/board.c +++ b/bsp/frdm-k64f/board/board.c @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * + * */ #include @@ -69,7 +69,7 @@ void rt_hw_board_init() { /* NVIC Configuration */ NVIC_Configuration(); - + BOARD_BootClockRUN(); /* Configure the SysTick */ diff --git a/bsp/frdm-k64f/board/board.h b/bsp/frdm-k64f/board/board.h index 7610ade1fe..5d43d1e382 100644 --- a/bsp/frdm-k64f/board/board.h +++ b/bsp/frdm-k64f/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/frdm-k64f/board/drv_emac.c b/bsp/frdm-k64f/board/drv_emac.c index 606c141545..7003bbdd74 100644 --- a/bsp/frdm-k64f/board/drv_emac.c +++ b/bsp/frdm-k64f/board/drv_emac.c @@ -1,6 +1,6 @@ /* * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * * SPDX-License-Identifier: Apache-2.0 * Change Logs: * Date Author Notes @@ -33,7 +33,7 @@ #define DEBUG_PRINTF(...) #endif -#define MAX_ADDR_LEN 6 +#define MAX_ADDR_LEN 6 #define ENET_RX_RING_LEN (16) #define ENET_TX_RING_LEN (8) @@ -45,17 +45,17 @@ #define ENET_RXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN) #define ENET_TXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN) #define ENET_ETH_MAX_FLEN (1522) // recommended size for a VLAN frame - + struct emac_device { /* inherit from Ethernet device */ struct eth_device parent; - - ALIGN(64) enet_rx_bd_struct_t RxBuffDescrip[ENET_RX_RING_LEN]; - ALIGN(64) enet_tx_bd_struct_t TxBuffDescrip[ENET_TX_RING_LEN]; - ALIGN(64) uint8_t RxDataBuff[ENET_RX_RING_LEN * ENET_ALIGN(ENET_RXBUFF_SIZE)]; - ALIGN(64) uint8_t TxDataBuff[ENET_TX_RING_LEN * ENET_ALIGN(ENET_TXBUFF_SIZE)]; - + + ALIGN(64) enet_rx_bd_struct_t RxBuffDescrip[ENET_RX_RING_LEN]; + ALIGN(64) enet_tx_bd_struct_t TxBuffDescrip[ENET_TX_RING_LEN]; + ALIGN(64) uint8_t RxDataBuff[ENET_RX_RING_LEN * ENET_ALIGN(ENET_RXBUFF_SIZE)]; + ALIGN(64) uint8_t TxDataBuff[ENET_TX_RING_LEN * ENET_ALIGN(ENET_TXBUFF_SIZE)]; + enet_handle_t enet_handle; rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* MAC address */ struct rt_semaphore tx_wait; @@ -112,7 +112,7 @@ static void setup_enet_clock_init(void) { CLOCK_EnableClock(kCLOCK_PortC); CLOCK_EnableClock(kCLOCK_PortB); - + /* Select the Ethernet timestamp clock source */ CLOCK_SetEnetTime0Clock(0x2); } @@ -120,7 +120,7 @@ static void setup_enet_clock_init(void) static void enet_mac_rx_isr(struct emac_device* emac) { rt_err_t result; - + result = eth_device_ready(&(_emac.parent)); if( result != RT_EOK ) { @@ -136,7 +136,7 @@ static void enet_mac_tx_isr(struct emac_device* emac) static void ethernet_callback(ENET_Type *base, enet_handle_t *handle, enet_event_t event, void *param) { struct emac_device* emac = param; - + switch (event) { case kENET_RxEvent: @@ -154,7 +154,7 @@ static rt_err_t k64_emac_init(rt_device_t dev) { struct emac_device* emac = K64_EMAC_DEVICE(dev); enet_handle_t * enet_handle = &emac->enet_handle; - + bool link = false; uint32_t phyAddr = 0; phy_speed_t phy_speed; @@ -167,7 +167,7 @@ static rt_err_t k64_emac_init(rt_device_t dev) setup_enet_clock_init(); /* enable iomux and clock */ setup_k64_io_enet(); - + /* prepare the buffer configuration. */ buffCfg.rxBdNumber = ENET_RX_RING_LEN; /* Receive buffer descriptor number. */ buffCfg.txBdNumber = ENET_TX_RING_LEN; /* Transmit buffer descriptor number. */ @@ -177,12 +177,12 @@ static rt_err_t k64_emac_init(rt_device_t dev) buffCfg.txBdStartAddrAlign = emac->TxBuffDescrip; /* Aligned transmit buffer descriptor start address. */ buffCfg.rxBufferAlign = emac->RxDataBuff; /* Receive data buffer start address. */ buffCfg.txBufferAlign = emac->TxDataBuff; /* Transmit data buffer start address. */ - + sysClock = CLOCK_GetFreq(kCLOCK_CoreSysClk); DEBUG_PRINTF("sysClock: %d\n", sysClock); - + ENET_GetDefaultConfig(&config); - + PHY_Init(ENET, 0, CLOCK_GetFreq(kCLOCK_CoreSysClk)); if (PHY_GetLinkStatus(ENET, phyAddr, &link) == kStatus_Success) { @@ -191,7 +191,7 @@ static rt_err_t k64_emac_init(rt_device_t dev) DEBUG_PRINTF("phy link up\n"); /* Get link information from PHY */ PHY_GetLinkSpeedDuplex(ENET, phyAddr, &phy_speed, &phy_duplex); - + /* Change the MII speed and duplex for actual link status. */ config.miiSpeed = (enet_mii_speed_t)phy_speed; config.miiDuplex = (enet_mii_duplex_t)phy_duplex; @@ -205,7 +205,7 @@ static rt_err_t k64_emac_init(rt_device_t dev) config.macSpecialConfig = kENET_ControlFlowControlEnable; config.txAccelerConfig = 0; config.rxAccelerConfig = kENET_RxAccelMacCheckEnabled; - + ENET_Init(ENET, enet_handle, &config, &buffCfg, emac->dev_addr, sysClock); ENET_SetCallback(enet_handle, ethernet_callback, emac); ENET_ActiveRead(ENET); @@ -214,7 +214,7 @@ static rt_err_t k64_emac_init(rt_device_t dev) { DEBUG_PRINTF("read phy failed\n"); } - + return RT_EOK; } @@ -244,7 +244,7 @@ static rt_err_t k64_emac_control(rt_device_t dev, int cmd, void *args) { struct emac_device *emac; - DEBUG_PRINTF("k64_emac_control\n"); + DEBUG_PRINTF("k64_emac_control\n"); emac = K64_EMAC_DEVICE(dev); RT_ASSERT(emac != RT_NULL); @@ -270,14 +270,14 @@ static rt_err_t k64_emac_tx(rt_device_t dev, struct pbuf* p) struct emac_device *emac = K64_EMAC_DEVICE(dev); enet_handle_t * enet_handle = &emac->enet_handle; - + RT_ASSERT(p != NULL); - DEBUG_PRINTF("k64_emac_tx: %d\n", p->len); + DEBUG_PRINTF("k64_emac_tx: %d\n", p->len); emac = K64_EMAC_DEVICE(dev); RT_ASSERT(emac != RT_NULL); - + #ifdef DRV_EMAC_RX_DUMP { int i; @@ -290,10 +290,10 @@ static rt_err_t k64_emac_tx(rt_device_t dev, struct pbuf* p) DEBUG_PRINTF("\n"); } DEBUG_PRINTF("\n"); - } + } #endif - + do { result = ENET_SendFrame(ENET, enet_handle, p->payload, p->len); @@ -313,17 +313,17 @@ struct pbuf *k64_emac_rx(rt_device_t dev) uint32_t length = 0; status_t status; enet_data_error_stats_t eErrStatic; - + struct pbuf* p = RT_NULL; struct emac_device *emac = K64_EMAC_DEVICE(dev); enet_handle_t * enet_handle = &emac->enet_handle; RT_ASSERT(emac != RT_NULL); DEBUG_PRINTF("k64_emac_rx\n"); - + /* Get the Frame size */ status = ENET_GetRxFrameSize(enet_handle, &length); - + if (status == kStatus_ENET_RxFrameError) { /* Update the received buffer when error happened. */ @@ -331,19 +331,19 @@ struct pbuf *k64_emac_rx(rt_device_t dev) ENET_GetRxErrBeforeReadFrame(enet_handle, &eErrStatic); /* update the receive buffer. */ ENET_ReadFrame(ENET, enet_handle, NULL, 0); - + DEBUG_PRINTF("receive frame faild\n"); - + return p; } - + /* Call ENET_ReadFrame when there is a received frame. */ if (length != 0) { /* Received valid frame. Deliver the rx buffer with the size equal to length. */ p = pbuf_alloc(PBUF_RAW, length, PBUF_POOL); } - + if (p != NULL) { status = ENET_ReadFrame(ENET, enet_handle, p->payload, length); @@ -370,7 +370,7 @@ struct pbuf *k64_emac_rx(rt_device_t dev) pbuf_free(p); } } - + return p; } @@ -397,7 +397,7 @@ int drv_emac_hw_init(void) /* init tx semaphore */ rt_sem_init(&_emac.tx_wait, "tx_wait", ENET_TX_RING_LEN - 1, RT_IPC_FLAG_FIFO); - + /* register ETH device */ eth_device_init(&(_emac.parent), "e0"); @@ -409,15 +409,15 @@ INIT_DEVICE_EXPORT(drv_emac_hw_init); long k64_dump_tx_bd(void) { - int i; + int i; - enet_tx_bd_struct_t *txbd = _emac.TxBuffDescrip; + enet_tx_bd_struct_t *txbd = _emac.TxBuffDescrip; + + for (i = 0; i < ENET_RX_RING_LEN; i++) + { + DEBUG_PRINTF("status: %04X, length: %04X, data: %08X\n", txbd[i].control, txbd[i].length, (uint32_t)txbd[i].buffer); + } - for (i = 0; i < ENET_RX_RING_LEN; i++) - { - DEBUG_PRINTF("status: %04X, length: %04X, data: %08X\n", txbd[i].control, txbd[i].length, (uint32_t)txbd[i].buffer); - } - return 0; } FINSH_FUNCTION_EXPORT(k64_dump_tx_bd, dump all receive buffer descriptor); @@ -425,21 +425,21 @@ MSH_CMD_EXPORT(k64_dump_tx_bd, dump all receive buffer descriptor); long k64_dump_rx_bd(void) { - int i; - enet_rx_bd_struct_t *rxbd = _emac.RxBuffDescrip; - - for (i = 0; i < ENET_RX_RING_LEN; i++) - { - DEBUG_PRINTF("bd:%08X, ", (void *)&rxbd[i]); - //rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, (void *)&rxbd[i], sizeof(enet_rx_bd_struct_t)); - DEBUG_PRINTF("status:%04X, length:%04X, data:%08X ", rxbd[i].control, rxbd[i].length, (uint32_t)rxbd[i].buffer); + int i; + enet_rx_bd_struct_t *rxbd = _emac.RxBuffDescrip; + + for (i = 0; i < ENET_RX_RING_LEN; i++) + { + DEBUG_PRINTF("bd:%08X, ", (void *)&rxbd[i]); + //rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, (void *)&rxbd[i], sizeof(enet_rx_bd_struct_t)); + DEBUG_PRINTF("status:%04X, length:%04X, data:%08X ", rxbd[i].control, rxbd[i].length, (uint32_t)rxbd[i].buffer); #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - DEBUG_PRINTF("ce:%04X/%04X/%04X ", rxbd[i].controlExtend0, rxbd[i].controlExtend1, rxbd[i].controlExtend2); - DEBUG_PRINTF("crc:%04X, len:%04X, type:%04X, ts:%04X", rxbd[i].payloadCheckSum, rxbd[i].headerLength, rxbd[i].protocolTyte, rxbd[i].timestamp); + DEBUG_PRINTF("ce:%04X/%04X/%04X ", rxbd[i].controlExtend0, rxbd[i].controlExtend1, rxbd[i].controlExtend2); + DEBUG_PRINTF("crc:%04X, len:%04X, type:%04X, ts:%04X", rxbd[i].payloadCheckSum, rxbd[i].headerLength, rxbd[i].protocolTyte, rxbd[i].timestamp); #endif - DEBUG_PRINTF("\n"); - } - + DEBUG_PRINTF("\n"); + } + return 0; } FINSH_FUNCTION_EXPORT(k64_dump_rx_bd, dump all receive buffer descriptor); diff --git a/bsp/frdm-k64f/board/drv_emac.h b/bsp/frdm-k64f/board/drv_emac.h index e2d0ec8c8c..3a2e55e820 100644 --- a/bsp/frdm-k64f/board/drv_emac.h +++ b/bsp/frdm-k64f/board/drv_emac.h @@ -1,6 +1,6 @@ /* * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * * SPDX-License-Identifier: Apache-2.0 * Change Logs: * Date Author Notes diff --git a/bsp/frdm-k64f/board/drv_uart.c b/bsp/frdm-k64f/board/drv_uart.c index c4a1da1013..5e0ec5c2e2 100644 --- a/bsp/frdm-k64f/board/drv_uart.c +++ b/bsp/frdm-k64f/board/drv_uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -243,7 +243,7 @@ void rt_hw_uart_init(void) config.parity = PARITY_NONE; config.stop_bits = STOP_BITS_1; config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; + config.bufsz = RT_SERIAL_RB_BUFSZ; _k64_serial.ops = &_k64_ops; _k64_serial.config = config; diff --git a/bsp/frdm-k64f/board/drv_uart.h b/bsp/frdm-k64f/board/drv_uart.h index 7fd78c9a4e..4786d07e13 100644 --- a/bsp/frdm-k64f/board/drv_uart.h +++ b/bsp/frdm-k64f/board/drv_uart.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * + * */ #ifndef DRV_UART_H diff --git a/bsp/frdm-k64f/board/led.c b/bsp/frdm-k64f/board/led.c index aebea8bdce..e6951c8fdc 100644 --- a/bsp/frdm-k64f/board/led.c +++ b/bsp/frdm-k64f/board/led.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/frdm-k64f/board/led.h b/bsp/frdm-k64f/board/led.h index f1c62666d6..4e669e44c3 100644 --- a/bsp/frdm-k64f/board/led.h +++ b/bsp/frdm-k64f/board/led.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/frdm-k64f/rtconfig.h b/bsp/frdm-k64f/rtconfig.h index 6338b39edb..51afa56099 100644 --- a/bsp/frdm-k64f/rtconfig.h +++ b/bsp/frdm-k64f/rtconfig.h @@ -3,16 +3,16 @@ #define __RTTHREAD_CFG_H__ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 8 +#define RT_ALIGN_SIZE 8 /* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 32 +#define RT_THREAD_PRIORITY_MAX 32 /* Tick per Second */ -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 /* SECTION: RT_DEBUG */ /* Thread Debug */ @@ -28,9 +28,9 @@ /* Using Software Timer */ /* #define RT_USING_TIMER_SOFT */ -#define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 512 -#define RT_TIMER_TICK_PER_SECOND 10 +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_TICK_PER_SECOND 10 /* SECTION: IPC */ /* Using Semaphore*/ @@ -73,7 +73,7 @@ /* SECTION: Console options */ #define RT_USING_CONSOLE /* the buffer size of console*/ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 /* SECTION: finsh, a C-Express shell */ #define RT_USING_FINSH @@ -88,18 +88,18 @@ /* Reentrancy (thread safe) of the FatFs module. */ #define RT_DFS_ELM_REENTRANT /* Number of volumes (logical drives) to be used. */ -#define RT_DFS_ELM_DRIVES 2 -/* #define RT_DFS_ELM_USE_LFN 1 */ -#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +/* #define RT_DFS_ELM_USE_LFN 1 */ +#define RT_DFS_ELM_MAX_LFN 255 /* Maximum sector size to be handled. */ #define RT_DFS_ELM_MAX_SECTOR_SIZE 512 #define RT_USING_DFS_ROMFS /* the max number of mounted filesystem */ -#define DFS_FILESYSTEMS_MAX 2 -/* the max number of opened files */ -#define DFS_FD_MAX 4 +#define DFS_FILESYSTEMS_MAX 2 +/* the max number of opened files */ +#define DFS_FD_MAX 4 /* SECTION: lwip, a lighwight TCP/IP protocol stack */ #define RT_USING_LWIP @@ -115,7 +115,7 @@ #define RT_LWIP_DNS /* the number of simulatenously active TCP connections*/ -#define RT_LWIP_TCP_PCB_NUM 5 +#define RT_LWIP_TCP_PCB_NUM 5 /* ip address of target */ #define RT_LWIP_IPADDR "192.168.1.201" @@ -127,19 +127,19 @@ #define RT_LWIP_MSKADDR "255.255.255.0" /* tcp thread options */ -#define RT_LWIP_TCPTHREAD_PRIORITY 12 -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4 -#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4 +#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 /* ethernet if thread options */ -#define RT_LWIP_ETHTHREAD_PRIORITY 15 -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4 -#define RT_LWIP_ETHTHREAD_STACKSIZE 512 +#define RT_LWIP_ETHTHREAD_PRIORITY 15 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4 +#define RT_LWIP_ETHTHREAD_STACKSIZE 512 /* TCP sender buffer space */ -#define RT_LWIP_TCP_SND_BUF 8192 +#define RT_LWIP_TCP_SND_BUF 8192 /* TCP receive window. */ -#define RT_LWIP_TCP_WND 8192 +#define RT_LWIP_TCP_WND 8192 #define CHECKSUM_CHECK_TCP 0 #define CHECKSUM_CHECK_IP 0 diff --git a/bsp/gd32303e-eval/drivers/board.c b/bsp/gd32303e-eval/drivers/board.c index 3a6ed7cee7..5910ec4124 100644 --- a/bsp/gd32303e-eval/drivers/board.c +++ b/bsp/gd32303e-eval/drivers/board.c @@ -75,7 +75,7 @@ void rt_hw_board_init() rt_console_set_device(RT_CONSOLE_DEVICE_NAME); #endif -#ifdef RT_USING_HEAP +#ifdef RT_USING_HEAP rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END); #endif } diff --git a/bsp/gd32303e-eval/drivers/board.h b/bsp/gd32303e-eval/drivers/board.h index 190008d51b..208f3f4c6a 100644 --- a/bsp/gd32303e-eval/drivers/board.h +++ b/bsp/gd32303e-eval/drivers/board.h @@ -15,7 +15,7 @@ #include // Internal SRAM memory size[Kbytes] <8-64> -// Default: 64 +// Default: 64 #ifdef __ICCARM__ // Use *.icf ram symbal, to avoid hardcode. extern char __ICFEDIT_region_RAM_end__; diff --git a/bsp/gd32303e-eval/drivers/drv_gpio.c b/bsp/gd32303e-eval/drivers/drv_gpio.c index 2270ec1b89..a96cecc13e 100644 --- a/bsp/gd32303e-eval/drivers/drv_gpio.c +++ b/bsp/gd32303e-eval/drivers/drv_gpio.c @@ -257,7 +257,7 @@ void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) /* GPIO Periph clock enable */ rcu_periph_clock_enable(index->clk); pin_mode = GPIO_MODE_OUT_PP; - + switch(mode) { case PIN_MODE_OUTPUT: @@ -438,7 +438,7 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_ return RT_EINVAL; } irqmap = &pin_irq_map[hdr_index]; - + switch (pin_irq_hdr_tab[hdr_index].mode) { case PIN_IRQ_MODE_RISING: @@ -459,14 +459,14 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_ /* enable and set interrupt priority */ nvic_irq_enable(irqmap->irqno, 5U, 0U); - + /* connect EXTI line to GPIO pin */ gpio_exti_source_select(index->port_src, index->pin_src); /* configure EXTI line */ exti_init((exti_line_enum)(index->pin), EXTI_INTERRUPT, trigger_mode); exti_interrupt_flag_clear((exti_line_enum)(index->pin)); - + rt_hw_interrupt_enable(level); } else if (enabled == PIN_IRQ_DISABLE) @@ -501,7 +501,7 @@ int rt_hw_pin_init(void) int result; result = rt_device_pin_register("pin", &_gd32_pin_ops, RT_NULL); - + return result; } INIT_BOARD_EXPORT(rt_hw_pin_init); @@ -520,7 +520,7 @@ void GD32_GPIO_EXTI_IRQHandler(rt_int8_t exti_line) { pin_irq_hdr(exti_line); exti_interrupt_flag_clear((exti_line_enum)(1 << exti_line)); - } + } } void EXTI0_IRQHandler(void) { diff --git a/bsp/gd32303e-eval/drivers/drv_i2c.c b/bsp/gd32303e-eval/drivers/drv_i2c.c index 9f91bfc05e..e7587618fe 100644 --- a/bsp/gd32303e-eval/drivers/drv_i2c.c +++ b/bsp/gd32303e-eval/drivers/drv_i2c.c @@ -154,7 +154,7 @@ static int gd32_i2c_read(rt_uint32_t i2c_periph, rt_uint16_t slave_address, rt_u *p_buffer = i2c_data_receive(i2c_periph); /* point to the next location where the byte read will be saved */ - p_buffer++; + p_buffer++; /* decrement the read bytes counter */ data_byte--; @@ -263,7 +263,7 @@ static rt_size_t gd32_i2c_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg } } } - + ret = i; out: @@ -273,7 +273,7 @@ out: } static const struct rt_i2c_bus_device_ops i2c_ops = -{ +{ gd32_i2c_xfer, RT_NULL, RT_NULL @@ -310,7 +310,7 @@ int rt_hw_i2c_init(void) i2c_device.priv = (void *)&_i2c_bit_ops; rt_i2c_bit_add_bus(&i2c_device, I2C_BUS_NAME); - } + } #else /* register hardware I2C */ diff --git a/bsp/gd32303e-eval/drivers/drv_spi.c b/bsp/gd32303e-eval/drivers/drv_spi.c index 89d1964e17..96f53b5019 100644 --- a/bsp/gd32303e-eval/drivers/drv_spi.c +++ b/bsp/gd32303e-eval/drivers/drv_spi.c @@ -115,7 +115,7 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat spi_init_struct.prescale = SPI_PSC_256; } } /* baudrate */ - + switch(configuration->mode & RT_SPI_MODE_3) { case RT_SPI_MODE_0: @@ -131,7 +131,7 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE; break; } - + /* MSB or LSB */ if(configuration->mode & RT_SPI_MSB) { @@ -141,7 +141,7 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat { spi_init_struct.endian = SPI_ENDIAN_LSB; } - + spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX; spi_init_struct.device_mode = SPI_MASTER; spi_init_struct.nss = SPI_NSS_SOFT; @@ -177,7 +177,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes const rt_uint8_t * send_ptr = message->send_buf; rt_uint8_t * recv_ptr = message->recv_buf; rt_uint32_t size = message->length; - + DEBUG_PRINTF("spi poll transfer start: %d\n", size); while(size--) @@ -188,7 +188,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes { data = *send_ptr++; } - + // Todo: replace register read/write by gd32f3 lib //Wait until the transmit buffer is empty while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE)); @@ -263,8 +263,8 @@ int gd32_hw_spi_init(void) rcu_periph_clock_enable(RCU_SPI0); /* SPI0_SCK(PA5), SPI0_MISO(PA6) and SPI0_MOSI(PA7) GPIO pin configuration */ gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_5 | GPIO_PIN_7); - gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_6); - + gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_6); + #endif #ifdef RT_USING_SPI1 static struct rt_spi_bus spi_bus1; @@ -283,7 +283,7 @@ int gd32_hw_spi_init(void) static struct rt_spi_bus spi_bus2; spi_bus2.parent.user_data = (void *)SPI2; - result = rt_spi_bus_register(&spi_bus2, "spi2", &gd32_spi_ops); + result = rt_spi_bus_register(&spi_bus2, "spi2", &gd32_spi_ops); rcu_periph_clock_enable(RCU_SPI2); rcu_periph_clock_enable(RCU_GPIOB); diff --git a/bsp/gd32303e-eval/drivers/drv_spi_flash.c b/bsp/gd32303e-eval/drivers/drv_spi_flash.c index 28d2a0e5b6..64d4b32be3 100644 --- a/bsp/gd32303e-eval/drivers/drv_spi_flash.c +++ b/bsp/gd32303e-eval/drivers/drv_spi_flash.c @@ -26,7 +26,7 @@ static int rt_hw_gd25q40_init(void) static rt_base_t gd25q_cs_pin; /* SPI设备CS片选引脚 */ gd25q_cs_pin = GD25Q_SPI_CS_PIN; - + rt_pin_mode(GD25Q_SPI_CS_PIN, GPIO_MODE_OUT_PP); res = rt_spi_bus_attach_device(&spi_dev_gd25q, SPI_DEVICE_NAME, SPI_BUS_NAME, (void*)gd25q_cs_pin); diff --git a/bsp/gd32303e-eval/drivers/drv_usart.c b/bsp/gd32303e-eval/drivers/drv_usart.c index e12ead1e99..07077f5cba 100644 --- a/bsp/gd32303e-eval/drivers/drv_usart.c +++ b/bsp/gd32303e-eval/drivers/drv_usart.c @@ -40,7 +40,7 @@ struct gd32_uart uint32_t tx_port; uint16_t tx_pin; uint32_t rx_port; - uint16_t rx_pin; + uint16_t rx_pin; struct rt_serial_device * serial; char *device_name; @@ -139,7 +139,7 @@ static const struct gd32_uart uarts[] = { "uart0", }, #endif - + #ifdef RT_USING_USART1 { USART1, // uart peripheral index @@ -151,7 +151,7 @@ static const struct gd32_uart uarts[] = { "uart1", }, #endif - + #ifdef RT_USING_USART2 { USART2, // uart peripheral index @@ -163,7 +163,7 @@ static const struct gd32_uart uarts[] = { "uart2", }, #endif - + #ifdef RT_USING_UART3 { UART3, // uart peripheral index @@ -175,7 +175,7 @@ static const struct gd32_uart uarts[] = { "uart3", }, #endif - + #ifdef RT_USING_UART4 { UART4, // uart peripheral index @@ -224,9 +224,9 @@ static rt_err_t gd32_configure(struct rt_serial_device *serial, struct serial_co RT_ASSERT(cfg != RT_NULL); uart = (struct gd32_uart *)serial->parent.user_data; - + gd32_uart_gpio_init(uart); - + usart_baudrate_set(uart->uart_periph, cfg->baud_rate); switch (cfg->data_bits) @@ -306,7 +306,7 @@ static int gd32_putc(struct rt_serial_device *serial, char ch) usart_data_transmit(uart->uart_periph, ch); while((usart_flag_get(uart->uart_periph, USART_FLAG_TC) == RESET)); - + return 1; } diff --git a/bsp/gd32450z-eval/drivers/board.h b/bsp/gd32450z-eval/drivers/board.h index eae2923bc9..ea7dd83acd 100644 --- a/bsp/gd32450z-eval/drivers/board.h +++ b/bsp/gd32450z-eval/drivers/board.h @@ -18,7 +18,7 @@ #define EXT_SDRAM_END (EXT_SDRAM_BEGIN + (32U * 1024 * 1024)) /* the end address of external SDRAM */ // Internal SRAM memory size[Kbytes] <8-64> -// Default: 64 +// Default: 64 #ifdef __ICCARM__ // Use *.icf ram symbal, to avoid hardcode. extern char __ICFEDIT_region_RAM_end__; diff --git a/bsp/gd32450z-eval/drivers/drv_enet.c b/bsp/gd32450z-eval/drivers/drv_enet.c index 452fce1e8a..f461b50fba 100644 --- a/bsp/gd32450z-eval/drivers/drv_enet.c +++ b/bsp/gd32450z-eval/drivers/drv_enet.c @@ -31,16 +31,16 @@ //#define EMAC_TX_DUMP #ifdef EMAC_DEBUG -#define EMAC_TRACE rt_kprintf +#define EMAC_TRACE rt_kprintf #else #define EMAC_TRACE(...) #endif -#define EMAC_RXBUFNB 4 -#define EMAC_TXBUFNB 2 +#define EMAC_RXBUFNB 4 +#define EMAC_TXBUFNB 2 -#define EMAC_PHY_AUTO 0 -#define EMAC_PHY_10MBIT 1 +#define EMAC_PHY_AUTO 0 +#define EMAC_PHY_10MBIT 1 #define EMAC_PHY_100MBIT 2 #define MAX_ADDR_LEN 6 @@ -51,14 +51,14 @@ struct gd32_emac rt_uint8_t phy_mode; /* interface address info. */ - rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ struct rt_synopsys_eth * ETHERNET_MAC; IRQn_Type ETHER_MAC_IRQ; - + EMAC_DMADESCTypeDef *DMATxDescToSet; EMAC_DMADESCTypeDef *DMARxDescToGet; - + #pragma pack(4) EMAC_DMADESCTypeDef DMARxDscrTab[EMAC_RXBUFNB]; #pragma pack(4) @@ -67,7 +67,7 @@ struct gd32_emac rt_uint8_t Rx_Buff[EMAC_RXBUFNB][EMAC_MAX_PACKET_SIZE]; #pragma pack(4) rt_uint8_t Tx_Buff[EMAC_TXBUFNB][EMAC_MAX_PACKET_SIZE]; - + struct rt_semaphore tx_buf_free; }; @@ -544,14 +544,14 @@ static void enet_gpio_config(void) rcu_periph_clock_enable(RCU_GPIOG); rcu_periph_clock_enable(RCU_GPIOH); rcu_periph_clock_enable(RCU_GPIOI); - + gpio_af_set(GPIOA, GPIO_AF_0, GPIO_PIN_8); gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_8); gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_8); - + /* enable SYSCFG clock */ rcu_periph_clock_enable(RCU_SYSCFG); - + /* choose DIV2 to get 50MHz from 200MHz on CKOUT0 pin (PA8) to clock the PHY */ rcu_ckout0_config(RCU_CKOUT0SRC_PLLP, RCU_CKOUT0_DIV4); syscfg_enet_phy_interface_config(SYSCFG_ENET_PHY_RMII); @@ -559,31 +559,31 @@ static void enet_gpio_config(void) /* PA1: ETH_RMII_REF_CLK */ gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_1); gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_1); - + /* PA2: ETH_MDIO */ gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_2); gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_2); - + /* PA7: ETH_RMII_CRS_DV */ gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_7); - gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_7); - + gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_7); + gpio_af_set(GPIOA, GPIO_AF_11, GPIO_PIN_1); gpio_af_set(GPIOA, GPIO_AF_11, GPIO_PIN_2); gpio_af_set(GPIOA, GPIO_AF_11, GPIO_PIN_7); - + /* PB11: ETH_RMII_TX_EN */ gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_11); gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_11); - + /* PB12: ETH_RMII_TXD0 */ gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_12); gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_12); - + /* PB13: ETH_RMII_TXD1 */ gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_13); - gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_13); - + gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_13); + gpio_af_set(GPIOB, GPIO_AF_11, GPIO_PIN_11); gpio_af_set(GPIOB, GPIO_AF_11, GPIO_PIN_12); gpio_af_set(GPIOB, GPIO_AF_11, GPIO_PIN_13); @@ -595,11 +595,11 @@ static void enet_gpio_config(void) /* PC4: ETH_RMII_RXD0 */ gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_4); gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_4); - + /* PC5: ETH_RMII_RXD1 */ gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_5); - gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_5); - + gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_5); + gpio_af_set(GPIOC, GPIO_AF_11, GPIO_PIN_1); gpio_af_set(GPIOC, GPIO_AF_11, GPIO_PIN_4); gpio_af_set(GPIOC, GPIO_AF_11, GPIO_PIN_5); @@ -609,17 +609,17 @@ static void enet_gpio_config(void) int rt_hw_gd32_eth_init(void) { rt_kprintf("rt_gd32_eth_init...\n"); - + /* enable ethernet clock */ rcu_periph_clock_enable(RCU_ENET); rcu_periph_clock_enable(RCU_ENETTX); rcu_periph_clock_enable(RCU_ENETRX); - + nvic_configuration(); - + /* configure the GPIO ports for ethernet pins */ enet_gpio_config(); - + /* set autonegotiation mode */ gd32_emac_device0.phy_mode = EMAC_PHY_AUTO; gd32_emac_device0.ETHERNET_MAC = ETHERNET_MAC0; @@ -634,16 +634,16 @@ int rt_hw_gd32_eth_init(void) gd32_emac_device0.dev_addr[4] = 0x34; gd32_emac_device0.dev_addr[5] = 0x56; - gd32_emac_device0.parent.parent.init = gd32_emac_init; - gd32_emac_device0.parent.parent.open = gd32_emac_open; - gd32_emac_device0.parent.parent.close = gd32_emac_close; - gd32_emac_device0.parent.parent.read = gd32_emac_read; - gd32_emac_device0.parent.parent.write = gd32_emac_write; - gd32_emac_device0.parent.parent.control = gd32_emac_control; + gd32_emac_device0.parent.parent.init = gd32_emac_init; + gd32_emac_device0.parent.parent.open = gd32_emac_open; + gd32_emac_device0.parent.parent.close = gd32_emac_close; + gd32_emac_device0.parent.parent.read = gd32_emac_read; + gd32_emac_device0.parent.parent.write = gd32_emac_write; + gd32_emac_device0.parent.parent.control = gd32_emac_control; gd32_emac_device0.parent.parent.user_data = RT_NULL; - gd32_emac_device0.parent.eth_rx = gd32_emac_rx; - gd32_emac_device0.parent.eth_tx = gd32_emac_tx; + gd32_emac_device0.parent.eth_rx = gd32_emac_rx; + gd32_emac_device0.parent.eth_tx = gd32_emac_tx; /* init tx buffer free semaphore */ rt_sem_init(&gd32_emac_device0.tx_buf_free, "tx_buf0", EMAC_TXBUFNB, RT_IPC_FLAG_FIFO); diff --git a/bsp/gd32450z-eval/drivers/drv_lcd.c b/bsp/gd32450z-eval/drivers/drv_lcd.c index 714be9276c..3cbae2ac84 100644 --- a/bsp/gd32450z-eval/drivers/drv_lcd.c +++ b/bsp/gd32450z-eval/drivers/drv_lcd.c @@ -37,7 +37,7 @@ static struct rt_device_graphic_info _lcd_info; static struct rt_device lcd; /*! - \brief configure TLI GPIO + \brief configure TLI GPIO \param[in] none \param[out] none \retval none @@ -53,34 +53,34 @@ static void tli_gpio_config(void) rcu_periph_clock_enable(RCU_GPIOG); /* configure HSYNC(PC6), VSYNC(PA4), PCLK(PG7), DE(PF10) */ - /* configure LCD_R7(PG6), LCD_R6(PA8), LCD_R5(PA12), LCD_R4(PA11), LCD_R3(PB0), + /* configure LCD_R7(PG6), LCD_R6(PA8), LCD_R5(PA12), LCD_R4(PA11), LCD_R3(PB0), LCD_G7(PD3), LCD_G6(PC7), LCD_G5(PB11), LCD_G4(PB10), LCD_G3(PG10), LCD_G2(PA6), LCD_B7(PB9), LCD_B6(PB8), LCD_B5(PA3), LCD_B4(PG12), LCD_B3(PG11) */ - gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_3); + gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_3); gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_4); - gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_6); - gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_12); - gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_11); - gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_8); - - gpio_af_set(GPIOB,GPIO_AF_9,GPIO_PIN_0); - gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_10); + gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_6); + gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_12); + gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_11); + gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_8); + + gpio_af_set(GPIOB,GPIO_AF_9,GPIO_PIN_0); + gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_10); //gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_11); - gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_8); + gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_8); gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_9); - - gpio_af_set(GPIOC,GPIO_AF_14,GPIO_PIN_6); + + gpio_af_set(GPIOC,GPIO_AF_14,GPIO_PIN_6); gpio_af_set(GPIOC,GPIO_AF_14,GPIO_PIN_7); - - gpio_af_set(GPIOD,GPIO_AF_14,GPIO_PIN_3); - gpio_af_set(GPIOF,GPIO_AF_14,GPIO_PIN_10); - - gpio_af_set(GPIOG,GPIO_AF_14,GPIO_PIN_6); + gpio_af_set(GPIOD,GPIO_AF_14,GPIO_PIN_3); + + gpio_af_set(GPIOF,GPIO_AF_14,GPIO_PIN_10); + + gpio_af_set(GPIOG,GPIO_AF_14,GPIO_PIN_6); gpio_af_set(GPIOG,GPIO_AF_14,GPIO_PIN_7); gpio_af_set(GPIOG,GPIO_AF_9,GPIO_PIN_10); - gpio_af_set(GPIOG,GPIO_AF_14,GPIO_PIN_11); - gpio_af_set(GPIOG,GPIO_AF_9,GPIO_PIN_12); + gpio_af_set(GPIOG,GPIO_AF_14,GPIO_PIN_11); + gpio_af_set(GPIOG,GPIO_AF_9,GPIO_PIN_12); gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_4|GPIO_PIN_3|GPIO_PIN_6 |GPIO_PIN_8|GPIO_PIN_11|GPIO_PIN_12); @@ -119,15 +119,15 @@ static void lcd_config(void) lcd_ctrl_line_config(); lcd_disable(); lcd_enable(); - + /* configure the GPIO of TLI */ tli_gpio_config(); /* configure the LCD_SPI */ - lcd_spi_config(); + lcd_spi_config(); /* power on the LCD */ //lcd_power_on(); - lcd_power_on3(); //New Version 3.5" TFT RGB Hardware needs use this initilize funtion ---By xufei 2016.10.21 + lcd_power_on3(); //New Version 3.5" TFT RGB Hardware needs use this initilize funtion ---By xufei 2016.10.21 } /*! @@ -140,7 +140,7 @@ static void tli_config(void) { tli_parameter_struct tli_init_struct; tli_layer_parameter_struct tli_layer_init_struct; - + rcu_periph_clock_enable(RCU_TLI); /* configure the PLLSAI clock to generate lcd clock */ @@ -152,52 +152,52 @@ static void tli_config(void) if(ERROR == rcu_osci_stab_wait(RCU_PLLSAI_CK)){ while(1); } - + /* TLI initialization */ tli_init_struct.signalpolarity_hs = TLI_HSYN_ACTLIVE_LOW; tli_init_struct.signalpolarity_vs = TLI_VSYN_ACTLIVE_LOW; tli_init_struct.signalpolarity_de = TLI_DE_ACTLIVE_LOW; tli_init_struct.signalpolarity_pixelck = TLI_PIXEL_CLOCK_TLI; - + /* LCD display timing configuration */ tli_init_struct.synpsz_hpsz = LCD_480_320_HSYNC; tli_init_struct.synpsz_vpsz = LCD_480_320_VSYNC; - tli_init_struct.backpsz_hbpsz = LCD_480_320_HSYNC + LCD_480_320_HBP; - tli_init_struct.backpsz_vbpsz = LCD_480_320_VSYNC + LCD_480_320_VBP; + tli_init_struct.backpsz_hbpsz = LCD_480_320_HSYNC + LCD_480_320_HBP; + tli_init_struct.backpsz_vbpsz = LCD_480_320_VSYNC + LCD_480_320_VBP; tli_init_struct.activesz_hasz = RT_HW_LCD_WIDTH + LCD_480_320_HSYNC + LCD_480_320_HBP; tli_init_struct.activesz_vasz = RT_HW_LCD_HEIGHT + LCD_480_320_VSYNC + LCD_480_320_VBP; - tli_init_struct.totalsz_htsz = RT_HW_LCD_WIDTH + LCD_480_320_HSYNC + LCD_480_320_HBP + LCD_480_320_HFP; + tli_init_struct.totalsz_htsz = RT_HW_LCD_WIDTH + LCD_480_320_HSYNC + LCD_480_320_HBP + LCD_480_320_HFP; tli_init_struct.totalsz_vtsz = RT_HW_LCD_HEIGHT + LCD_480_320_VSYNC + LCD_480_320_VBP + LCD_480_320_VFP; - + /* LCD background color configure*/ tli_init_struct.backcolor_red = 0x00; tli_init_struct.backcolor_green = 0x00; - tli_init_struct.backcolor_blue = 0x00; + tli_init_struct.backcolor_blue = 0x00; tli_init(&tli_init_struct); - + lcd_framebuffer = rt_malloc(sizeof(rt_uint16_t) * RT_HW_LCD_HEIGHT * RT_HW_LCD_WIDTH); RT_ASSERT(lcd_framebuffer != NULL); rt_memset(lcd_framebuffer, 0, sizeof(rt_uint16_t) * RT_HW_LCD_WIDTH * RT_HW_LCD_HEIGHT); /* TLI layer0 configuration */ tli_layer_init_struct.layer_window_leftpos = tli_init_struct.backpsz_hbpsz + 1; - tli_layer_init_struct.layer_window_rightpos = tli_init_struct.backpsz_hbpsz + RT_HW_LCD_WIDTH; + tli_layer_init_struct.layer_window_rightpos = tli_init_struct.backpsz_hbpsz + RT_HW_LCD_WIDTH; tli_layer_init_struct.layer_window_toppos = tli_init_struct.backpsz_vbpsz + 1; tli_layer_init_struct.layer_window_bottompos = tli_init_struct.backpsz_vbpsz + RT_HW_LCD_HEIGHT; - + tli_layer_init_struct.layer_ppf = LAYER_PPF_RGB565; tli_layer_init_struct.layer_sa = 0xFF; - tli_layer_init_struct.layer_default_blue = 0x00; - tli_layer_init_struct.layer_default_green = 0x00; - tli_layer_init_struct.layer_default_red = 0x00; + tli_layer_init_struct.layer_default_blue = 0x00; + tli_layer_init_struct.layer_default_green = 0x00; + tli_layer_init_struct.layer_default_red = 0x00; tli_layer_init_struct.layer_default_alpha = 0x00; - tli_layer_init_struct.layer_acf1 = LAYER_ACF1_PASA; + tli_layer_init_struct.layer_acf1 = LAYER_ACF1_PASA; tli_layer_init_struct.layer_acf2 = LAYER_ACF2_PASA; - tli_layer_init_struct.layer_frame_bufaddr = (uint32_t)lcd_framebuffer; - tli_layer_init_struct.layer_frame_line_length = ((RT_HW_LCD_WIDTH * 2) + 3); + tli_layer_init_struct.layer_frame_bufaddr = (uint32_t)lcd_framebuffer; + tli_layer_init_struct.layer_frame_line_length = ((RT_HW_LCD_WIDTH * 2) + 3); tli_layer_init_struct.layer_frame_buf_stride_offset = (RT_HW_LCD_WIDTH * 2); - tli_layer_init_struct.layer_frame_total_line_number = RT_HW_LCD_HEIGHT; - + tli_layer_init_struct.layer_frame_total_line_number = RT_HW_LCD_HEIGHT; + tli_layer_init(LAYER0, &tli_layer_init_struct); } @@ -206,21 +206,21 @@ static rt_err_t rt_lcd_control(rt_device_t dev, int cmd, void *args) switch (cmd) { case RTGRAPHIC_CTRL_RECT_UPDATE: - { + { memcpy((void *)lcd_framebuffer, _rt_framebuffer, sizeof(rt_uint16_t)*RT_HW_LCD_HEIGHT * RT_HW_LCD_WIDTH); } break; - + case RTGRAPHIC_CTRL_POWERON: break; - + case RTGRAPHIC_CTRL_POWEROFF: break; - + case RTGRAPHIC_CTRL_GET_INFO: memcpy(args, &_lcd_info, sizeof(_lcd_info)); break; - + case RTGRAPHIC_CTRL_SET_MODE: break; } @@ -231,21 +231,21 @@ static rt_err_t rt_lcd_control(rt_device_t dev, int cmd, void *args) int gd32_hw_lcd_init(void) { _rt_framebuffer = rt_malloc_align(sizeof(rt_uint16_t) * RT_HW_LCD_WIDTH * RT_HW_LCD_HEIGHT, 32); - if (_rt_framebuffer == RT_NULL) + if (_rt_framebuffer == RT_NULL) return -1; /* no memory yet */ - + lcd_config(); tli_config(); - tli_layer_enable(LAYER0); + tli_layer_enable(LAYER0); tli_reload_config(TLI_FRAME_BLANK_RELOAD_EN); tli_enable(); - + _lcd_info.bits_per_pixel = LCD_BITS_PER_PIXEL; _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565; _lcd_info.framebuffer = (void *)_rt_framebuffer; _lcd_info.width = RT_HW_LCD_WIDTH; _lcd_info.height = RT_HW_LCD_HEIGHT; - + lcd.type = RT_Device_Class_Graphic; lcd.init = NULL; lcd.open = NULL; @@ -254,10 +254,10 @@ int gd32_hw_lcd_init(void) lcd.write = NULL; lcd.control = rt_lcd_control; lcd.user_data = (void *)&_lcd_info; - + /* register lcd device to RT-Thread */ rt_device_register(&lcd, "lcd", RT_DEVICE_FLAG_RDWR); - + return 0; } INIT_DEVICE_EXPORT(gd32_hw_lcd_init); diff --git a/bsp/gd32450z-eval/drivers/drv_spi.c b/bsp/gd32450z-eval/drivers/drv_spi.c index cb73a210e0..acd4f7198f 100644 --- a/bsp/gd32450z-eval/drivers/drv_spi.c +++ b/bsp/gd32450z-eval/drivers/drv_spi.c @@ -7,7 +7,7 @@ * Date Author Notes * 2017-06-05 tanek first implementation. */ - + #include "drv_spi.h" #include @@ -28,7 +28,7 @@ #ifdef DEBUG #define DEBUG_PRINTF(...) rt_kprintf(__VA_ARGS__) #else -#define DEBUG_PRINTF(...) +#define DEBUG_PRINTF(...) #endif /* private rt-thread spi ops function */ @@ -44,16 +44,16 @@ static struct rt_spi_ops gd32_spi_ops = static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration) { - struct rt_spi_bus * spi_bus = (struct rt_spi_bus *)device->bus; + struct rt_spi_bus * spi_bus = (struct rt_spi_bus *)device->bus; struct gd32f4_spi *f4_spi = (struct gd32f4_spi *)spi_bus->parent.user_data; - + spi_parameter_struct spi_init_struct; uint32_t spi_periph = f4_spi->spi_periph; - RT_ASSERT(device != RT_NULL); - RT_ASSERT(configuration != RT_NULL); + RT_ASSERT(device != RT_NULL); + RT_ASSERT(configuration != RT_NULL); /* data_width */ if(configuration->data_width <= 8) @@ -125,7 +125,7 @@ static rt_err_t configure(struct rt_spi_device* device, spi_init_struct.prescale = SPI_PSC_256; } } /* baudrate */ - + switch(configuration->mode & RT_SPI_MODE_3) { case RT_SPI_MODE_0: @@ -133,15 +133,15 @@ static rt_err_t configure(struct rt_spi_device* device, break; case RT_SPI_MODE_1: spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_2EDGE; - break; + break; case RT_SPI_MODE_2: spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_1EDGE; - break; + break; case RT_SPI_MODE_3: spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE; break; } - + /* MSB or LSB */ if(configuration->mode & RT_SPI_MSB) { @@ -151,18 +151,18 @@ static rt_err_t configure(struct rt_spi_device* device, { spi_init_struct.endian = SPI_ENDIAN_LSB; } - + spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX; spi_init_struct.device_mode = SPI_MASTER; spi_init_struct.nss = SPI_NSS_SOFT; - + spi_crc_off(spi_periph); /* init SPI */ spi_init(spi_periph, &spi_init_struct); /* Enable SPI_MASTER */ - spi_enable(spi_periph); - + spi_enable(spi_periph); + return RT_EOK; }; @@ -174,9 +174,9 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes struct gd32_spi_cs * gd32_spi_cs = device->parent.user_data; uint32_t spi_periph = f4_spi->spi_periph; - RT_ASSERT(device != NULL); - RT_ASSERT(message != NULL); - + RT_ASSERT(device != NULL); + RT_ASSERT(message != NULL); + /* take CS */ if(message->cs_take) { @@ -190,7 +190,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes const rt_uint8_t * send_ptr = message->send_buf; rt_uint8_t * recv_ptr = message->recv_buf; rt_uint32_t size = message->length; - + DEBUG_PRINTF("spi poll transfer start: %d\n", size); while(size--) @@ -201,12 +201,12 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes { data = *send_ptr++; } - + // Todo: replace register read/write by gd32f4 lib //Wait until the transmit buffer is empty while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE)); // Send the byte - spi_i2s_data_transmit(spi_periph, data); + spi_i2s_data_transmit(spi_periph, data); //Wait until a data is received while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE)); @@ -238,7 +238,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes //Wait until the transmit buffer is empty while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE)); // Send the byte - spi_i2s_data_transmit(spi_periph, data); + spi_i2s_data_transmit(spi_periph, data); //Wait until a data is received while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE)); @@ -256,7 +256,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes /* release CS */ if(message->cs_release) { - gpio_bit_set(gd32_spi_cs->GPIOx, gd32_spi_cs->GPIO_Pin); + gpio_bit_set(gd32_spi_cs->GPIOx, gd32_spi_cs->GPIO_Pin); DEBUG_PRINTF("spi release cs\n"); } @@ -270,7 +270,7 @@ static const struct gd32f4_spi spis[] = { #ifdef RT_USING_SPI0 {SPI0, RCU_SPI0, &spi_bus[0]}, #endif - + #ifdef RT_USING_SPI1 {SPI1, RCU_SPI1, &spi_bus[1]}, #endif @@ -282,11 +282,11 @@ static const struct gd32f4_spi spis[] = { #ifdef RT_USING_SPI3 {SPI3, RCU_SPI3, &spi_bus[3]}, #endif - + #ifdef RT_USING_SPI4 {SPI4, RCU_SPI4, &spi_bus[4]}, #endif - + #ifdef RT_USING_SPI5 {SPI5, RCU_SPI5, &spi_bus[5]}, #endif @@ -306,9 +306,9 @@ rt_err_t gd32_spi_bus_register(uint32_t spi_periph, const char * spi_bus_name) { int i; - + RT_ASSERT(spi_bus_name != RT_NULL); - + for (i = 0; i < ARR_LEN(spis); i++) { if (spi_periph == spis[i].spi_periph) @@ -319,7 +319,7 @@ rt_err_t gd32_spi_bus_register(uint32_t spi_periph, return RT_EOK; } } - + return RT_ERROR; } #endif diff --git a/bsp/gd32450z-eval/drivers/drv_spi.h b/bsp/gd32450z-eval/drivers/drv_spi.h index e9db6df080..51bae441ca 100644 --- a/bsp/gd32450z-eval/drivers/drv_spi.h +++ b/bsp/gd32450z-eval/drivers/drv_spi.h @@ -32,7 +32,7 @@ struct gd32_spi_cs /* public function */ rt_err_t gd32_spi_bus_register(uint32_t spi_periph, - //struct gd32_spi_bus * gd32_spi, - const char * spi_bus_name); + //struct gd32_spi_bus * gd32_spi, + const char * spi_bus_name); #endif // gd32F20X_40X_SPI_H_INCLUDED diff --git a/bsp/gd32450z-eval/drivers/drv_spi_flash.c b/bsp/gd32450z-eval/drivers/drv_spi_flash.c index ec9a3129d4..7f95d59314 100644 --- a/bsp/gd32450z-eval/drivers/drv_spi_flash.c +++ b/bsp/gd32450z-eval/drivers/drv_spi_flash.c @@ -28,8 +28,8 @@ static int rt_hw_spi5_init(void) { /* register spi bus */ { - rt_err_t result; - + rt_err_t result; + rcu_periph_clock_enable(RCU_GPIOG); rcu_periph_clock_enable(RCU_SPI5); @@ -38,36 +38,36 @@ static int rt_hw_spi5_init(void) gpio_mode_set(GPIOG, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_10|GPIO_PIN_11| GPIO_PIN_12|GPIO_PIN_13| GPIO_PIN_14); gpio_output_options_set(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ, GPIO_PIN_10|GPIO_PIN_11| GPIO_PIN_12|GPIO_PIN_13| GPIO_PIN_14); - result = gd32_spi_bus_register(SPI5, SPI_BUS_NAME); + result = gd32_spi_bus_register(SPI5, SPI_BUS_NAME); if (result != RT_EOK) - { - return result; - } + { + return result; + } } /* attach cs */ { static struct rt_spi_device spi_device; static struct gd32_spi_cs spi_cs; - rt_err_t result; - + rt_err_t result; + spi_cs.GPIOx = GPIOG; spi_cs.GPIO_Pin = GPIO_PIN_9; - + /* SPI5_CS(PG9) GPIO pin configuration */ gpio_mode_set(GPIOG, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO_PIN_9); gpio_output_options_set(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_9); - + gpio_bit_set(GPIOG,GPIO_PIN_9); result = rt_spi_bus_attach_device(&spi_device, SPI_FLASH_DEVICE_NAME, SPI_BUS_NAME, (void*)&spi_cs); - if (result != RT_EOK) - { - return result; - } + if (result != RT_EOK) + { + return result; + } } - return RT_EOK; + return RT_EOK; } INIT_DEVICE_EXPORT(rt_hw_spi5_init); @@ -79,7 +79,7 @@ static int rt_hw_spi_flash_with_sfud_init(void) return RT_ERROR; }; - return RT_EOK; + return RT_EOK; } INIT_COMPONENT_EXPORT(rt_hw_spi_flash_with_sfud_init) #endif diff --git a/bsp/gd32450z-eval/drivers/drv_usart.c b/bsp/gd32450z-eval/drivers/drv_usart.c index 216b022159..fa691a42b9 100644 --- a/bsp/gd32450z-eval/drivers/drv_usart.c +++ b/bsp/gd32450z-eval/drivers/drv_usart.c @@ -33,7 +33,7 @@ struct gd32_uart { uint32_t uart_periph; //Todo: 3bits - IRQn_Type irqn; //Todo: 7bits + IRQn_Type irqn; //Todo: 7bits rcu_periph_enum per_clk; //Todo: 5bits rcu_periph_enum tx_gpio_clk; //Todo: 5bits rcu_periph_enum rx_gpio_clk; //Todo: 5bits @@ -44,7 +44,7 @@ struct gd32_uart uint16_t rx_af; //Todo: 4bits uint16_t rx_pin; //Todo: 4bits - struct rt_serial_device * serial; + struct rt_serial_device * serial; char *device_name; }; @@ -189,7 +189,7 @@ static const struct gd32_uart uarts[] = { "uart0", }, #endif - + #ifdef BSP_USING_UART1 { USART1, // uart peripheral index @@ -201,7 +201,7 @@ static const struct gd32_uart uarts[] = { "uart1", }, #endif - + #ifdef BSP_USING_UART2 { USART2, // uart peripheral index @@ -213,7 +213,7 @@ static const struct gd32_uart uarts[] = { "uart2", }, #endif - + #ifdef BSP_USING_UART3 { UART3, // uart peripheral index @@ -225,7 +225,7 @@ static const struct gd32_uart uarts[] = { "uart3", }, #endif - + #ifdef BSP_USING_UART4 { UART4, // uart peripheral index @@ -249,7 +249,7 @@ static const struct gd32_uart uarts[] = { "uart5", }, #endif - + #ifdef BSP_USING_UART6 { UART6, // uart peripheral index @@ -305,7 +305,7 @@ void gd32_uart_gpio_init(struct gd32_uart *uart) /* configure USART Rx as alternate function push-pull */ gpio_mode_set(uart->rx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, uart->rx_pin); gpio_output_options_set(uart->rx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, uart->rx_pin); - + NVIC_SetPriority(uart->irqn, 0); NVIC_EnableIRQ(uart->irqn); } @@ -318,9 +318,9 @@ static rt_err_t gd32_configure(struct rt_serial_device *serial, struct serial_co RT_ASSERT(cfg != RT_NULL); uart = (struct gd32_uart *)serial->parent.user_data; - + gd32_uart_gpio_init(uart); - + usart_baudrate_set(uart->uart_periph, cfg->baud_rate); switch (cfg->data_bits) @@ -400,7 +400,7 @@ static int gd32_putc(struct rt_serial_device *serial, char ch) usart_data_transmit(uart->uart_periph, ch); while((usart_flag_get(uart->uart_periph, USART_FLAG_TC) == RESET)); - + return 1; } @@ -452,7 +452,7 @@ int gd32_hw_usart_init(void) struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; int i; - + for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++) { uarts[i].serial->ops = &gd32_uart_ops; diff --git a/bsp/gd32450z-eval/drivers/synopsys_emac.h b/bsp/gd32450z-eval/drivers/synopsys_emac.h index 87e03fa1b4..f6c303ce7f 100644 --- a/bsp/gd32450z-eval/drivers/synopsys_emac.h +++ b/bsp/gd32450z-eval/drivers/synopsys_emac.h @@ -8,7 +8,7 @@ #define __SYNOPSYS_EMAC_H__ #include - + /******************************************************************************/ /* Ethernet MAC Registers bits definitions */ @@ -34,8 +34,8 @@ #define EMAC_MACCR_RD ((rt_uint32_t)0x00000200) /* Retry disable */ #define EMAC_MACCR_APCS ((rt_uint32_t)0x00000080) /* Automatic Pad/CRC stripping */ #define EMAC_MACCR_BL ((rt_uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling - a transmission attempt during retries after a collision: 0 =< r <2^k */ -#define EMAC_MACCR_BL_10 ((rt_uint32_t)0x00000000) /* k = min (n, 10) */ + a transmission attempt during retries after a collision: 0 =< r <2^k */ +#define EMAC_MACCR_BL_10 ((rt_uint32_t)0x00000000) /* k = min (n, 10) */ #define EMAC_MACCR_BL_8 ((rt_uint32_t)0x00000020) /* k = min (n, 8) */ #define EMAC_MACCR_BL_4 ((rt_uint32_t)0x00000040) /* k = min (n, 4) */ #define EMAC_MACCR_BL_1 ((rt_uint32_t)0x00000060) /* k = min (n, 1) */ @@ -46,45 +46,45 @@ /* Bit definition for Ethernet MAC Frame Filter Register */ #define EMAC_MACFFR_RA ((rt_uint32_t)0x80000000) /* Receive all */ #define EMAC_MACFFR_HPF ((rt_uint32_t)0x00000400) /* Hash or perfect filter */ -#define EMAC_MACFFR_SAF ((rt_uint32_t)0x00000200) /* Source address filter enable */ +#define EMAC_MACFFR_SAF ((rt_uint32_t)0x00000200) /* Source address filter enable */ #define EMAC_MACFFR_SAIF ((rt_uint32_t)0x00000100) /* SA inverse filtering */ #define EMAC_MACFFR_PCF ((rt_uint32_t)0x000000C0) /* Pass control frames: 3 cases */ #define EMAC_MACFFR_PCF_BlockAll ((rt_uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ #define EMAC_MACFFR_PCF_ForwardAll ((rt_uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ #define EMAC_MACFFR_PCF_ForwardPassedAddrFilter ((rt_uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ #define EMAC_MACFFR_BFD ((rt_uint32_t)0x00000020) /* Broadcast frame disable */ -#define EMAC_MACFFR_PAM ((rt_uint32_t)0x00000010) /* Pass all mutlicast */ +#define EMAC_MACFFR_PAM ((rt_uint32_t)0x00000010) /* Pass all mutlicast */ #define EMAC_MACFFR_DAIF ((rt_uint32_t)0x00000008) /* DA Inverse filtering */ -#define EMAC_MACFFR_HM ((rt_uint32_t)0x00000004) /* Hash multicast */ -#define EMAC_MACFFR_HU ((rt_uint32_t)0x00000002) /* Hash unicast */ -#define EMAC_MACFFR_PM ((rt_uint32_t)0x00000001) /* Promiscuous mode */ +#define EMAC_MACFFR_HM ((rt_uint32_t)0x00000004) /* Hash multicast */ +#define EMAC_MACFFR_HU ((rt_uint32_t)0x00000002) /* Hash unicast */ +#define EMAC_MACFFR_PM ((rt_uint32_t)0x00000001) /* Promiscuous mode */ /* Bit definition for Ethernet MAC Hash Table High Register */ -#define EMAC_MACHTHR_HTH ((rt_uint32_t)0xFFFFFFFF) /* Hash table high */ +#define EMAC_MACHTHR_HTH ((rt_uint32_t)0xFFFFFFFF) /* Hash table high */ /* Bit definition for Ethernet MAC Hash Table Low Register */ -#define EMAC_MACHTLR_HTL ((rt_uint32_t)0xFFFFFFFF) /* Hash table low */ +#define EMAC_MACHTLR_HTL ((rt_uint32_t)0xFFFFFFFF) /* Hash table low */ /* Bit definition for Ethernet MAC MII Address Register */ -#define EMAC_MACMIIAR_PA ((rt_uint32_t)0x0000F800) /* Physical layer address */ -#define EMAC_MACMIIAR_MR ((rt_uint32_t)0x000007C0) /* MII register in the selected PHY */ -#define EMAC_MACMIIAR_CR ((rt_uint32_t)0x0000001C) /* CR clock range: 6 cases */ +#define EMAC_MACMIIAR_PA ((rt_uint32_t)0x0000F800) /* Physical layer address */ +#define EMAC_MACMIIAR_MR ((rt_uint32_t)0x000007C0) /* MII register in the selected PHY */ +#define EMAC_MACMIIAR_CR ((rt_uint32_t)0x0000001C) /* CR clock range: 6 cases */ #define EMAC_MACMIIAR_CR_Div42 ((rt_uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */ #define EMAC_MACMIIAR_CR_Div62 ((rt_uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */ #define EMAC_MACMIIAR_CR_Div16 ((rt_uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ #define EMAC_MACMIIAR_CR_Div26 ((rt_uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ #define EMAC_MACMIIAR_CR_Div102 ((rt_uint32_t)0x00000010) /* HCLK:150-250 MHz; MDC clock= HCLK/102 */ #define EMAC_MACMIIAR_CR_Div122 ((rt_uint32_t)0x00000014) /* HCLK:250-300 MHz; MDC clock= HCLK/122*/ -#define EMAC_MACMIIAR_MW ((rt_uint32_t)0x00000002) /* MII write */ -#define EMAC_MACMIIAR_MB ((rt_uint32_t)0x00000001) /* MII busy */ +#define EMAC_MACMIIAR_MW ((rt_uint32_t)0x00000002) /* MII write */ +#define EMAC_MACMIIAR_MB ((rt_uint32_t)0x00000001) /* MII busy */ /* Bit definition for Ethernet MAC MII Data Register */ -#define EMAC_MACMIIDR_MD ((rt_uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ +#define EMAC_MACMIIDR_MD ((rt_uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ /* Bit definition for Ethernet MAC Flow Control Register */ -#define EMAC_MACFCR_PT ((rt_uint32_t)0xFFFF0000) /* Pause time */ -#define EMAC_MACFCR_ZQPD ((rt_uint32_t)0x00000080) /* Zero-quanta pause disable */ -#define EMAC_MACFCR_PLT ((rt_uint32_t)0x00000030) /* Pause low threshold: 4 cases */ +#define EMAC_MACFCR_PT ((rt_uint32_t)0xFFFF0000) /* Pause time */ +#define EMAC_MACFCR_ZQPD ((rt_uint32_t)0x00000080) /* Zero-quanta pause disable */ +#define EMAC_MACFCR_PLT ((rt_uint32_t)0x00000030) /* Pause low threshold: 4 cases */ #define EMAC_MACFCR_PLT_Minus4 ((rt_uint32_t)0x00000000) /* Pause time minus 4 slot times */ #define EMAC_MACFCR_PLT_Minus28 ((rt_uint32_t)0x00000010) /* Pause time minus 28 slot times */ #define EMAC_MACFCR_PLT_Minus144 ((rt_uint32_t)0x00000020) /* Pause time minus 144 slot times */ @@ -427,7 +427,7 @@ #define EMAC_DMACHRBAR_HRBAP ((rt_uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */ //typedef enum { -// RESET = 0, SET = !RESET +// RESET = 0, SET = !RESET //} FlagStatus, ITStatus; //typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; @@ -436,165 +436,165 @@ */ typedef struct { - /** - * MAC - */ - rt_uint32_t EMAC_AutoNegotiation; /* Selects or not the AutoNegotiation mode for the external PHY - The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) - and the mode (half/full-duplex). - This parameter can be a value of @ref EMAC_AutoNegotiation */ + /** + * MAC + */ + rt_uint32_t EMAC_AutoNegotiation; /* Selects or not the AutoNegotiation mode for the external PHY + The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) + and the mode (half/full-duplex). + This parameter can be a value of @ref EMAC_AutoNegotiation */ - rt_uint32_t EMAC_Watchdog; /* Selects or not the Watchdog timer - When enabled, the MAC allows no more then 2048 bytes to be received. - When disabled, the MAC can receive up to 16384 bytes. - This parameter can be a value of @ref EMAC_watchdog */ + rt_uint32_t EMAC_Watchdog; /* Selects or not the Watchdog timer + When enabled, the MAC allows no more then 2048 bytes to be received. + When disabled, the MAC can receive up to 16384 bytes. + This parameter can be a value of @ref EMAC_watchdog */ - rt_uint32_t EMAC_Jabber; /* Selects or not Jabber timer - When enabled, the MAC allows no more then 2048 bytes to be sent. - When disabled, the MAC can send up to 16384 bytes. - This parameter can be a value of @ref EMAC_Jabber */ + rt_uint32_t EMAC_Jabber; /* Selects or not Jabber timer + When enabled, the MAC allows no more then 2048 bytes to be sent. + When disabled, the MAC can send up to 16384 bytes. + This parameter can be a value of @ref EMAC_Jabber */ - rt_uint32_t EMAC_InterFrameGap; /* Selects the minimum IFG between frames during transmission - This parameter can be a value of @ref EMAC_Inter_Frame_Gap */ + rt_uint32_t EMAC_InterFrameGap; /* Selects the minimum IFG between frames during transmission + This parameter can be a value of @ref EMAC_Inter_Frame_Gap */ - rt_uint32_t EMAC_CarrierSense; /* Selects or not the Carrier Sense - This parameter can be a value of @ref EMAC_Carrier_Sense */ + rt_uint32_t EMAC_CarrierSense; /* Selects or not the Carrier Sense + This parameter can be a value of @ref EMAC_Carrier_Sense */ - rt_uint32_t EMAC_Speed; /* Sets the Ethernet speed: 10/100 Mbps - This parameter can be a value of @ref EMAC_Speed */ + rt_uint32_t EMAC_Speed; /* Sets the Ethernet speed: 10/100 Mbps + This parameter can be a value of @ref EMAC_Speed */ - rt_uint32_t EMAC_ReceiveOwn; /* Selects or not the ReceiveOwn - ReceiveOwn allows the reception of frames when the TX_EN signal is asserted - in Half-Duplex mode - This parameter can be a value of @ref EMAC_Receive_Own */ + rt_uint32_t EMAC_ReceiveOwn; /* Selects or not the ReceiveOwn + ReceiveOwn allows the reception of frames when the TX_EN signal is asserted + in Half-Duplex mode + This parameter can be a value of @ref EMAC_Receive_Own */ - rt_uint32_t EMAC_LoopbackMode; /* Selects or not the internal MAC MII Loopback mode - This parameter can be a value of @ref EMAC_Loop_Back_Mode */ + rt_uint32_t EMAC_LoopbackMode; /* Selects or not the internal MAC MII Loopback mode + This parameter can be a value of @ref EMAC_Loop_Back_Mode */ - rt_uint32_t EMAC_Mode; /* Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode - This parameter can be a value of @ref EMAC_Duplex_Mode */ + rt_uint32_t EMAC_Mode; /* Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode + This parameter can be a value of @ref EMAC_Duplex_Mode */ - rt_uint32_t EMAC_ChecksumOffload; /* Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. - This parameter can be a value of @ref EMAC_Checksum_Offload */ + rt_uint32_t EMAC_ChecksumOffload; /* Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. + This parameter can be a value of @ref EMAC_Checksum_Offload */ - rt_uint32_t EMAC_RetryTransmission; /* Selects or not the MAC attempt retries transmission, based on the settings of BL, - when a colision occurs (Half-Duplex mode) - This parameter can be a value of @ref EMAC_Retry_Transmission */ + rt_uint32_t EMAC_RetryTransmission; /* Selects or not the MAC attempt retries transmission, based on the settings of BL, + when a colision occurs (Half-Duplex mode) + This parameter can be a value of @ref EMAC_Retry_Transmission */ - rt_uint32_t EMAC_AutomaticPadCRCStrip; /* Selects or not the Automatic MAC Pad/CRC Stripping - This parameter can be a value of @ref EMAC_Automatic_Pad_CRC_Strip */ + rt_uint32_t EMAC_AutomaticPadCRCStrip; /* Selects or not the Automatic MAC Pad/CRC Stripping + This parameter can be a value of @ref EMAC_Automatic_Pad_CRC_Strip */ - rt_uint32_t EMAC_BackOffLimit; /* Selects the BackOff limit value - This parameter can be a value of @ref EMAC_Back_Off_Limit */ + rt_uint32_t EMAC_BackOffLimit; /* Selects the BackOff limit value + This parameter can be a value of @ref EMAC_Back_Off_Limit */ - rt_uint32_t EMAC_DeferralCheck; /* Selects or not the deferral check function (Half-Duplex mode) - This parameter can be a value of @ref EMAC_Deferral_Check */ + rt_uint32_t EMAC_DeferralCheck; /* Selects or not the deferral check function (Half-Duplex mode) + This parameter can be a value of @ref EMAC_Deferral_Check */ - rt_uint32_t EMAC_ReceiveAll; /* Selects or not all frames reception by the MAC (No fitering) - This parameter can be a value of @ref EMAC_Receive_All */ + rt_uint32_t EMAC_ReceiveAll; /* Selects or not all frames reception by the MAC (No fitering) + This parameter can be a value of @ref EMAC_Receive_All */ - rt_uint32_t EMAC_SourceAddrFilter; /* Selects the Source Address Filter mode - This parameter can be a value of @ref EMAC_Source_Addr_Filter */ + rt_uint32_t EMAC_SourceAddrFilter; /* Selects the Source Address Filter mode + This parameter can be a value of @ref EMAC_Source_Addr_Filter */ - rt_uint32_t EMAC_PassControlFrames; /* Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) - This parameter can be a value of @ref EMAC_Pass_Control_Frames */ + rt_uint32_t EMAC_PassControlFrames; /* Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) + This parameter can be a value of @ref EMAC_Pass_Control_Frames */ - rt_uint32_t EMAC_BroadcastFramesReception; /* Selects or not the reception of Broadcast Frames - This parameter can be a value of @ref EMAC_Broadcast_Frames_Reception */ + rt_uint32_t EMAC_BroadcastFramesReception; /* Selects or not the reception of Broadcast Frames + This parameter can be a value of @ref EMAC_Broadcast_Frames_Reception */ - rt_uint32_t EMAC_DestinationAddrFilter; /* Sets the destination filter mode for both unicast and multicast frames - This parameter can be a value of @ref EMAC_Destination_Addr_Filter */ + rt_uint32_t EMAC_DestinationAddrFilter; /* Sets the destination filter mode for both unicast and multicast frames + This parameter can be a value of @ref EMAC_Destination_Addr_Filter */ - rt_uint32_t EMAC_PromiscuousMode; /* Selects or not the Promiscuous Mode - This parameter can be a value of @ref EMAC_Promiscuous_Mode */ + rt_uint32_t EMAC_PromiscuousMode; /* Selects or not the Promiscuous Mode + This parameter can be a value of @ref EMAC_Promiscuous_Mode */ - rt_uint32_t EMAC_MulticastFramesFilter; /* Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter - This parameter can be a value of @ref EMAC_Multicast_Frames_Filter */ + rt_uint32_t EMAC_MulticastFramesFilter; /* Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter + This parameter can be a value of @ref EMAC_Multicast_Frames_Filter */ - rt_uint32_t EMAC_UnicastFramesFilter; /* Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter - This parameter can be a value of @ref EMAC_Unicast_Frames_Filter */ + rt_uint32_t EMAC_UnicastFramesFilter; /* Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter + This parameter can be a value of @ref EMAC_Unicast_Frames_Filter */ - rt_uint32_t EMAC_HashTableHigh; /* This field holds the higher 32 bits of Hash table. */ + rt_uint32_t EMAC_HashTableHigh; /* This field holds the higher 32 bits of Hash table. */ - rt_uint32_t EMAC_HashTableLow; /* This field holds the lower 32 bits of Hash table. */ + rt_uint32_t EMAC_HashTableLow; /* This field holds the lower 32 bits of Hash table. */ - rt_uint32_t EMAC_PauseTime; /* This field holds the value to be used in the Pause Time field in the - transmit control frame */ + rt_uint32_t EMAC_PauseTime; /* This field holds the value to be used in the Pause Time field in the + transmit control frame */ - rt_uint32_t EMAC_ZeroQuantaPause; /* Selects or not the automatic generation of Zero-Quanta Pause Control frames - This parameter can be a value of @ref EMAC_Zero_Quanta_Pause */ + rt_uint32_t EMAC_ZeroQuantaPause; /* Selects or not the automatic generation of Zero-Quanta Pause Control frames + This parameter can be a value of @ref EMAC_Zero_Quanta_Pause */ - rt_uint32_t EMAC_PauseLowThreshold; /* This field configures the threshold of the PAUSE to be checked for - automatic retransmission of PAUSE Frame - This parameter can be a value of @ref EMAC_Pause_Low_Threshold */ + rt_uint32_t EMAC_PauseLowThreshold; /* This field configures the threshold of the PAUSE to be checked for + automatic retransmission of PAUSE Frame + This parameter can be a value of @ref EMAC_Pause_Low_Threshold */ - rt_uint32_t EMAC_UnicastPauseFrameDetect; /* Selects or not the MAC detection of the Pause frames (with MAC Address0 - unicast address and unique multicast address) - This parameter can be a value of @ref EMAC_Unicast_Pause_Frame_Detect */ + rt_uint32_t EMAC_UnicastPauseFrameDetect; /* Selects or not the MAC detection of the Pause frames (with MAC Address0 + unicast address and unique multicast address) + This parameter can be a value of @ref EMAC_Unicast_Pause_Frame_Detect */ - rt_uint32_t EMAC_ReceiveFlowControl; /* Enables or disables the MAC to decode the received Pause frame and - disable its transmitter for a specified time (Pause Time) - This parameter can be a value of @ref EMAC_Receive_Flow_Control */ + rt_uint32_t EMAC_ReceiveFlowControl; /* Enables or disables the MAC to decode the received Pause frame and + disable its transmitter for a specified time (Pause Time) + This parameter can be a value of @ref EMAC_Receive_Flow_Control */ - rt_uint32_t EMAC_TransmitFlowControl; /* Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) - or the MAC back-pressure operation (Half-Duplex mode) - This parameter can be a value of @ref EMAC_Transmit_Flow_Control */ + rt_uint32_t EMAC_TransmitFlowControl; /* Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) + or the MAC back-pressure operation (Half-Duplex mode) + This parameter can be a value of @ref EMAC_Transmit_Flow_Control */ - rt_uint32_t EMAC_VLANTagComparison; /* Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for - comparison and filtering - This parameter can be a value of @ref EMAC_VLAN_Tag_Comparison */ + rt_uint32_t EMAC_VLANTagComparison; /* Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for + comparison and filtering + This parameter can be a value of @ref EMAC_VLAN_Tag_Comparison */ - rt_uint32_t EMAC_VLANTagIdentifier; /* Holds the VLAN tag identifier for receive frames */ + rt_uint32_t EMAC_VLANTagIdentifier; /* Holds the VLAN tag identifier for receive frames */ - /** - * DMA - */ + /** + * DMA + */ - rt_uint32_t EMAC_DropTCPIPChecksumErrorFrame; /* Selects or not the Dropping of TCP/IP Checksum Error Frames - This parameter can be a value of @ref EMAC_Drop_TCP_IP_Checksum_Error_Frame */ + rt_uint32_t EMAC_DropTCPIPChecksumErrorFrame; /* Selects or not the Dropping of TCP/IP Checksum Error Frames + This parameter can be a value of @ref EMAC_Drop_TCP_IP_Checksum_Error_Frame */ - rt_uint32_t EMAC_ReceiveStoreForward; /* Enables or disables the Receive store and forward mode - This parameter can be a value of @ref EMAC_Receive_Store_Forward */ + rt_uint32_t EMAC_ReceiveStoreForward; /* Enables or disables the Receive store and forward mode + This parameter can be a value of @ref EMAC_Receive_Store_Forward */ - rt_uint32_t EMAC_FlushReceivedFrame; /* Enables or disables the flushing of received frames - This parameter can be a value of @ref EMAC_Flush_Received_Frame */ + rt_uint32_t EMAC_FlushReceivedFrame; /* Enables or disables the flushing of received frames + This parameter can be a value of @ref EMAC_Flush_Received_Frame */ - rt_uint32_t EMAC_TransmitStoreForward; /* Enables or disables Transmit store and forward mode - This parameter can be a value of @ref EMAC_Transmit_Store_Forward */ + rt_uint32_t EMAC_TransmitStoreForward; /* Enables or disables Transmit store and forward mode + This parameter can be a value of @ref EMAC_Transmit_Store_Forward */ - rt_uint32_t EMAC_TransmitThresholdControl; /* Selects or not the Transmit Threshold Control - This parameter can be a value of @ref EMAC_Transmit_Threshold_Control */ + rt_uint32_t EMAC_TransmitThresholdControl; /* Selects or not the Transmit Threshold Control + This parameter can be a value of @ref EMAC_Transmit_Threshold_Control */ - rt_uint32_t EMAC_ForwardErrorFrames; /* Selects or not the forward to the DMA of erroneous frames - This parameter can be a value of @ref EMAC_Forward_Error_Frames */ + rt_uint32_t EMAC_ForwardErrorFrames; /* Selects or not the forward to the DMA of erroneous frames + This parameter can be a value of @ref EMAC_Forward_Error_Frames */ - rt_uint32_t EMAC_ForwardUndersizedGoodFrames; /* Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error - and length less than 64 bytes) including pad-bytes and CRC) - This parameter can be a value of @ref EMAC_Forward_Undersized_Good_Frames */ + rt_uint32_t EMAC_ForwardUndersizedGoodFrames; /* Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error + and length less than 64 bytes) including pad-bytes and CRC) + This parameter can be a value of @ref EMAC_Forward_Undersized_Good_Frames */ - rt_uint32_t EMAC_ReceiveThresholdControl; /* Selects the threshold level of the Receive FIFO - This parameter can be a value of @ref EMAC_Receive_Threshold_Control */ + rt_uint32_t EMAC_ReceiveThresholdControl; /* Selects the threshold level of the Receive FIFO + This parameter can be a value of @ref EMAC_Receive_Threshold_Control */ - rt_uint32_t EMAC_SecondFrameOperate; /* Selects or not the Operate on second frame mode, which allows the DMA to process a second - frame of Transmit data even before obtaining the status for the first frame. - This parameter can be a value of @ref EMAC_Second_Frame_Operate */ + rt_uint32_t EMAC_SecondFrameOperate; /* Selects or not the Operate on second frame mode, which allows the DMA to process a second + frame of Transmit data even before obtaining the status for the first frame. + This parameter can be a value of @ref EMAC_Second_Frame_Operate */ - rt_uint32_t EMAC_AddressAlignedBeats; /* Enables or disables the Address Aligned Beats - This parameter can be a value of @ref EMAC_Address_Aligned_Beats */ + rt_uint32_t EMAC_AddressAlignedBeats; /* Enables or disables the Address Aligned Beats + This parameter can be a value of @ref EMAC_Address_Aligned_Beats */ - rt_uint32_t EMAC_FixedBurst; /* Enables or disables the AHB Master interface fixed burst transfers - This parameter can be a value of @ref EMAC_Fixed_Burst */ + rt_uint32_t EMAC_FixedBurst; /* Enables or disables the AHB Master interface fixed burst transfers + This parameter can be a value of @ref EMAC_Fixed_Burst */ - rt_uint32_t EMAC_RxDMABurstLength; /* Indicates the maximum number of beats to be transferred in one Rx DMA transaction - This parameter can be a value of @ref EMAC_Rx_DMA_Burst_Length */ + rt_uint32_t EMAC_RxDMABurstLength; /* Indicates the maximum number of beats to be transferred in one Rx DMA transaction + This parameter can be a value of @ref EMAC_Rx_DMA_Burst_Length */ - rt_uint32_t EMAC_TxDMABurstLength; /* Indicates sthe maximum number of beats to be transferred in one Tx DMA transaction - This parameter can be a value of @ref EMAC_Tx_DMA_Burst_Length */ + rt_uint32_t EMAC_TxDMABurstLength; /* Indicates sthe maximum number of beats to be transferred in one Tx DMA transaction + This parameter can be a value of @ref EMAC_Tx_DMA_Burst_Length */ - rt_uint32_t EMAC_DescriptorSkipLength; /* Specifies the number of word to skip between two unchained int (Ring mode) */ + rt_uint32_t EMAC_DescriptorSkipLength; /* Specifies the number of word to skip between two unchained int (Ring mode) */ - rt_uint32_t EMAC_DMAArbitration; /* Selects the DMA Tx/Rx arbitration - This parameter can be a value of @ref EMAC_DMA_Arbitration */ + rt_uint32_t EMAC_DMAArbitration; /* Selects the DMA Tx/Rx arbitration + This parameter can be a value of @ref EMAC_DMA_Arbitration */ } EMAC_InitTypeDef; /**--------------------------------------------------------------------------**/ @@ -608,10 +608,10 @@ typedef struct */ typedef struct { - rt_uint32_t Status; /* Status */ - rt_uint32_t ControlBufferSize; /* Control and Buffer1, Buffer2 lengths */ - rt_uint32_t Buffer1Addr; /* Buffer1 address pointer */ - rt_uint32_t Buffer2NextDescAddr; /* Buffer2 or next descriptor address pointer */ + rt_uint32_t Status; /* Status */ + rt_uint32_t ControlBufferSize; /* Control and Buffer1, Buffer2 lengths */ + rt_uint32_t Buffer1Addr; /* Buffer1 address pointer */ + rt_uint32_t Buffer2NextDescAddr; /* Buffer2 or next descriptor address pointer */ } EMAC_DMADESCTypeDef; /**--------------------------------------------------------------------------**/ @@ -620,14 +620,14 @@ typedef struct */ /**--------------------------------------------------------------------------**/ -#define EMAC_MAX_PACKET_SIZE 1520 /* EMAC_HEADER + EMAC_EXTRA + MAX_EMAC_PAYLOAD + EMAC_CRC */ -#define EMAC_HEADER 14 /* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ -#define EMAC_CRC 4 /* Ethernet CRC */ -#define EMAC_EXTRA 2 /* Extra bytes in some cases */ -#define VLAN_TAG 4 /* optional 802.1q VLAN Tag */ -#define MIN_EMAC_PAYLOAD 46 /* Minimum Ethernet payload size */ -#define MAX_EMAC_PAYLOAD 1500 /* Maximum Ethernet payload size */ -#define JUMBO_FRAME_PAYLOAD 9000 /* Jumbo frame payload size */ +#define EMAC_MAX_PACKET_SIZE 1520 /* EMAC_HEADER + EMAC_EXTRA + MAX_EMAC_PAYLOAD + EMAC_CRC */ +#define EMAC_HEADER 14 /* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ +#define EMAC_CRC 4 /* Ethernet CRC */ +#define EMAC_EXTRA 2 /* Extra bytes in some cases */ +#define VLAN_TAG 4 /* optional 802.1q VLAN Tag */ +#define MIN_EMAC_PAYLOAD 46 /* Minimum Ethernet payload size */ +#define MAX_EMAC_PAYLOAD 1500 /* Maximum Ethernet payload size */ +#define JUMBO_FRAME_PAYLOAD 9000 /* Jumbo frame payload size */ /**--------------------------------------------------------------------------**/ /** @@ -1084,7 +1084,7 @@ struct rt_synopsys_eth volatile rt_uint32_t FCR; volatile rt_uint32_t VTR; rt_uint8_t RESERVED0[8]; - + volatile rt_uint32_t RWFFR; volatile rt_uint32_t PMTR; volatile rt_uint32_t LPICSR; diff --git a/bsp/hifive1/applications/main.c b/bsp/hifive1/applications/main.c index ef6521a942..e3cd69f303 100644 --- a/bsp/hifive1/applications/main.c +++ b/bsp/hifive1/applications/main.c @@ -14,5 +14,5 @@ int main(void) { - return 0; + return 0; } diff --git a/bsp/hifive1/drivers/drv_usart.c b/bsp/hifive1/drivers/drv_usart.c index c7c88d6861..935d39105f 100644 --- a/bsp/hifive1/drivers/drv_usart.c +++ b/bsp/hifive1/drivers/drv_usart.c @@ -23,7 +23,7 @@ static rt_err_t usart_configure(struct rt_serial_device *serial, { RT_ASSERT(serial != RT_NULL); RT_ASSERT(cfg != RT_NULL); - + GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK; GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK; diff --git a/bsp/hifive1/drivers/interrupt.c b/bsp/hifive1/drivers/interrupt.c index 1d4ae50626..75e8e8ac59 100644 --- a/bsp/hifive1/drivers/interrupt.c +++ b/bsp/hifive1/drivers/interrupt.c @@ -48,13 +48,13 @@ rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector, void *param) void rt_hw_interrupt_init(void) { int idx; - + /* config interrupt vector*/ asm volatile( "la t0, trap_entry\n" "csrw mtvec, t0" ); - + /* enable global interrupt*/ PLIC_init(&g_plic, PLIC_CTRL_ADDR, @@ -72,8 +72,8 @@ void rt_hw_interrupt_init(void) irq_desc[idx].counter = 0; #endif } - - // enable machine external interrupt + + // enable machine external interrupt set_csr(mie, MIP_MEIP); } @@ -118,7 +118,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, } /** - * This function will be call when external machine-level + * This function will be call when external machine-level * interrupt from PLIC occurred. */ void handle_m_ext_interrupt(void) diff --git a/bsp/hifive1/drivers/interrupt.h b/bsp/hifive1/drivers/interrupt.h index aee7ded426..52d378233a 100644 --- a/bsp/hifive1/drivers/interrupt.h +++ b/bsp/hifive1/drivers/interrupt.h @@ -19,5 +19,5 @@ rt_uint32_t rt_hw_interrupt_get_active(rt_uint32_t fiq_irq); void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id); rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, void *param, const char *name); - + #endif diff --git a/bsp/imx6sx/cortex-a9/applications/main.c b/bsp/imx6sx/cortex-a9/applications/main.c index 9b0847fc8f..e32c9a1b4c 100644 --- a/bsp/imx6sx/cortex-a9/applications/main.c +++ b/bsp/imx6sx/cortex-a9/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imx6sx/cortex-a9/cpu/cpu.c b/bsp/imx6sx/cortex-a9/cpu/cpu.c index 2d78715011..5f82671c1b 100644 --- a/bsp/imx6sx/cortex-a9/cpu/cpu.c +++ b/bsp/imx6sx/cortex-a9/cpu/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,14 +20,14 @@ /** shutdown CPU */ void rt_hw_cpu_shutdown() { - rt_uint32_t level; - rt_kprintf("shutdown...\n"); + rt_uint32_t level; + rt_kprintf("shutdown...\n"); - level = rt_hw_interrupt_disable(); - while (level) - { - RT_ASSERT(0); - } + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } } /*@}*/ diff --git a/bsp/imx6sx/cortex-a9/cpu/interrupt.c b/bsp/imx6sx/cortex-a9/cpu/interrupt.c index fb6e3ff3e0..1781ce49b7 100644 --- a/bsp/imx6sx/cortex-a9/cpu/interrupt.c +++ b/bsp/imx6sx/cortex-a9/cpu/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imx6sx/cortex-a9/cpu/mmu.c b/bsp/imx6sx/cortex-a9/cpu/mmu.c index 58acdd8145..f4d6068099 100644 --- a/bsp/imx6sx/cortex-a9/cpu/mmu.c +++ b/bsp/imx6sx/cortex-a9/cpu/mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imx6sx/cortex-a9/cpu/pmu.c b/bsp/imx6sx/cortex-a9/cpu/pmu.c index 8ffc1dede6..2b9165cc8b 100644 --- a/bsp/imx6sx/cortex-a9/cpu/pmu.c +++ b/bsp/imx6sx/cortex-a9/cpu/pmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imx6sx/cortex-a9/cpu/stack.c b/bsp/imx6sx/cortex-a9/cpu/stack.c index 2bd3c36915..e58852218a 100644 --- a/bsp/imx6sx/cortex-a9/cpu/stack.c +++ b/bsp/imx6sx/cortex-a9/cpu/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -28,35 +28,35 @@ * @return stack address */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) + rt_uint8_t *stack_addr, void *texit) { - rt_uint32_t *stk; + rt_uint32_t *stk; - stk = (rt_uint32_t*)stack_addr; - *(stk) = (rt_uint32_t)tentry; /* entry point */ - *(--stk) = (rt_uint32_t)texit; /* lr */ - *(--stk) = 0; /* r12 */ - *(--stk) = 0; /* r11 */ - *(--stk) = 0; /* r10 */ - *(--stk) = 0; /* r9 */ - *(--stk) = 0; /* r8 */ - *(--stk) = 0; /* r7 */ - *(--stk) = 0; /* r6 */ - *(--stk) = 0; /* r5 */ - *(--stk) = 0; /* r4 */ - *(--stk) = 0; /* r3 */ - *(--stk) = 0; /* r2 */ - *(--stk) = 0; /* r1 */ - *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ + stk = (rt_uint32_t*)stack_addr; + *(stk) = (rt_uint32_t)tentry; /* entry point */ + *(--stk) = (rt_uint32_t)texit; /* lr */ + *(--stk) = 0; /* r12 */ + *(--stk) = 0; /* r11 */ + *(--stk) = 0; /* r10 */ + *(--stk) = 0; /* r9 */ + *(--stk) = 0; /* r8 */ + *(--stk) = 0; /* r7 */ + *(--stk) = 0; /* r6 */ + *(--stk) = 0; /* r5 */ + *(--stk) = 0; /* r4 */ + *(--stk) = 0; /* r3 */ + *(--stk) = 0; /* r2 */ + *(--stk) = 0; /* r1 */ + *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ - /* cpsr */ - if ((rt_uint32_t)tentry & 0x01) - *(--stk) = SVCMODE | 0x20; /* thumb mode */ - else - *(--stk) = SVCMODE; /* arm mode */ + /* cpsr */ + if ((rt_uint32_t)tentry & 0x01) + *(--stk) = SVCMODE | 0x20; /* thumb mode */ + else + *(--stk) = SVCMODE; /* arm mode */ - /* return task's current stack address */ - return (rt_uint8_t *)stk; + /* return task's current stack address */ + return (rt_uint8_t *)stk; } /*@}*/ diff --git a/bsp/imx6sx/cortex-a9/cpu/trap.c b/bsp/imx6sx/cortex-a9/cpu/trap.c index f3b2c26e6d..8393a27976 100644 --- a/bsp/imx6sx/cortex-a9/cpu/trap.c +++ b/bsp/imx6sx/cortex-a9/cpu/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imx6sx/cortex-a9/drivers/board.c b/bsp/imx6sx/cortex-a9/drivers/board.c index 7ff9d47a89..92e8fa351e 100644 --- a/bsp/imx6sx/cortex-a9/drivers/board.c +++ b/bsp/imx6sx/cortex-a9/drivers/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imx6sx/cortex-a9/drivers/board.h b/bsp/imx6sx/cortex-a9/drivers/board.h index 9ae9ae60c7..f52ef4f08e 100644 --- a/bsp/imx6sx/cortex-a9/drivers/board.h +++ b/bsp/imx6sx/cortex-a9/drivers/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imx6sx/cortex-a9/drivers/emac_drv.c b/bsp/imx6sx/cortex-a9/drivers/emac_drv.c index af5ca009cf..b51934eee1 100644 --- a/bsp/imx6sx/cortex-a9/drivers/emac_drv.c +++ b/bsp/imx6sx/cortex-a9/drivers/emac_drv.c @@ -1,6 +1,6 @@ /* * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * * SPDX-License-Identifier: Apache-2.0 * Change Logs: * Date Author Notes @@ -16,17 +16,17 @@ #include #include "emac_drv.h" -#define MAX_ADDR_LEN 6 -#define IMX_EMAC_DEVICE(eth) (struct emac_device*)(eth) +#define MAX_ADDR_LEN 6 +#define IMX_EMAC_DEVICE(eth) (struct emac_device*)(eth) struct emac_device { - /* inherit from Ethernet device */ - struct eth_device parent; + /* inherit from Ethernet device */ + struct eth_device parent; - imx_enet_priv_t enet_priv; - /* interface address info. */ - rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* MAC address */ + imx_enet_priv_t enet_priv; + /* interface address info. */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* MAC address */ }; static struct emac_device _emac; @@ -54,7 +54,7 @@ void init_enet(struct emac_device* emac) // Check PHY link status. if (!(emac->enet_priv.status & ENET_STATUS_LINK_ON)) { - rt_kprintf("ENET link status check fail\n"); + rt_kprintf("ENET link status check fail\n"); } imx_enet_start(&emac->enet_priv, emac->dev_addr); @@ -62,69 +62,69 @@ void init_enet(struct emac_device* emac) void imx_enet_isr(int vector, void *param) { - unsigned int value = 0; - imx_enet_priv_t * dev = &(_emac.enet_priv); - volatile hw_enet_t *enet_reg = dev->enet_reg; + unsigned int value = 0; + imx_enet_priv_t * dev = &(_emac.enet_priv); + volatile hw_enet_t *enet_reg = dev->enet_reg; value = enet_reg->EIR.U; enet_reg->EIR.U = value & (~ENET_EVENT_MII); if (value & ENET_EVENT_TX_ERR) - { + { dev->tx_busy = 0; } - else if (value & ENET_EVENT_TX) - { + else if (value & ENET_EVENT_TX) + { dev->tx_busy = 0; } if (value & ENET_EVENT_RX) - { - eth_device_ready(&(_emac.parent)); + { + eth_device_ready(&(_emac.parent)); } if (value & ENET_EVENT_HBERR) - { + { // printf("WARNGING[POLL]: Hearbeat error!\n"); } if (value & ENET_EVENT_EBERR) - { + { // printf("WARNING[POLL]: Ethernet Bus Error!\n"); } } static rt_err_t imx_emac_init(rt_device_t dev) { - struct emac_device *emac; + struct emac_device *emac; - emac = IMX_EMAC_DEVICE(dev); + emac = IMX_EMAC_DEVICE(dev); - /* initialize enet */ - init_enet(emac); - return RT_EOK; + /* initialize enet */ + init_enet(emac); + return RT_EOK; } static rt_err_t imx_emac_open(rt_device_t dev, rt_uint16_t oflag) { - return RT_EOK; + return RT_EOK; } static rt_err_t imx_emac_close(rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_size_t imx_emac_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_size_t imx_emac_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_err_t imx_emac_control(rt_device_t dev, int cmd, void *args) @@ -134,19 +134,19 @@ static rt_err_t imx_emac_control(rt_device_t dev, int cmd, void *args) emac = IMX_EMAC_DEVICE(dev); RT_ASSERT(emac != RT_NULL); - switch(cmd) - { - case NIOCTL_GADDR: - /* get MAC address */ - if(args) rt_memcpy(args, emac->dev_addr, 6); - else return -RT_ERROR; - break; - - default : - break; - } + switch(cmd) + { + case NIOCTL_GADDR: + /* get MAC address */ + if(args) rt_memcpy(args, emac->dev_addr, 6); + else return -RT_ERROR; + break; + + default : + break; + } - return RT_EOK; + return RT_EOK; } /* Ethernet device interface */ @@ -161,8 +161,8 @@ rt_err_t imx_emac_tx(rt_device_t dev, struct pbuf* p) /* copy pbuf to a whole ETH frame */ pbuf_copy_partial(p, s_pkt_send, p->tot_len, 0); - /* send to the enet */ - imx_enet_send(&emac->enet_priv, s_pkt_send, p->tot_len, 1); + /* send to the enet */ + imx_enet_send(&emac->enet_priv, s_pkt_send, p->tot_len, 1); return result; } @@ -170,23 +170,23 @@ rt_err_t imx_emac_tx(rt_device_t dev, struct pbuf* p) /* reception packet. */ struct pbuf *imx_emac_rx(rt_device_t dev) { - int len; + int len; struct pbuf* p = RT_NULL; struct emac_device *emac; emac = IMX_EMAC_DEVICE(dev); RT_ASSERT(emac != RT_NULL); - imx_enet_recv(&emac->enet_priv, s_pkt_recv, &len); - if (len > 0) - { - /* We allocate a pbuf chain of pbufs from the pool. */ - p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); - if (p != RT_NULL) - { - pbuf_take(p, s_pkt_recv, len); - } - } + imx_enet_recv(&emac->enet_priv, s_pkt_recv, &len); + if (len > 0) + { + /* We allocate a pbuf chain of pbufs from the pool. */ + p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); + if (p != RT_NULL) + { + pbuf_take(p, s_pkt_recv, len); + } + } return p; } @@ -194,27 +194,27 @@ struct pbuf *imx_emac_rx(rt_device_t dev) int imx_emac_hw_init(void) { /* test MAC address */ - _emac.dev_addr[0] = 0x00; - _emac.dev_addr[1] = 0x11; - _emac.dev_addr[2] = 0x22; - _emac.dev_addr[3] = 0x33; - _emac.dev_addr[4] = 0x44; - _emac.dev_addr[5] = 0x55; - - _emac.parent.parent.init = imx_emac_init; - _emac.parent.parent.open = imx_emac_open; - _emac.parent.parent.close = imx_emac_close; - _emac.parent.parent.read = imx_emac_read; - _emac.parent.parent.write = imx_emac_write; - _emac.parent.parent.control = imx_emac_control; - _emac.parent.parent.user_data = RT_NULL; - - _emac.parent.eth_rx = imx_emac_rx; - _emac.parent.eth_tx = imx_emac_tx; + _emac.dev_addr[0] = 0x00; + _emac.dev_addr[1] = 0x11; + _emac.dev_addr[2] = 0x22; + _emac.dev_addr[3] = 0x33; + _emac.dev_addr[4] = 0x44; + _emac.dev_addr[5] = 0x55; + + _emac.parent.parent.init = imx_emac_init; + _emac.parent.parent.open = imx_emac_open; + _emac.parent.parent.close = imx_emac_close; + _emac.parent.parent.read = imx_emac_read; + _emac.parent.parent.write = imx_emac_write; + _emac.parent.parent.control = imx_emac_control; + _emac.parent.parent.user_data = RT_NULL; + + _emac.parent.eth_rx = imx_emac_rx; + _emac.parent.eth_tx = imx_emac_tx; /* register ETH device */ eth_device_init(&(_emac.parent), "e0"); - return 0; + return 0; } INIT_DEVICE_EXPORT(imx_emac_hw_init); diff --git a/bsp/imx6sx/cortex-a9/drivers/emac_drv.h b/bsp/imx6sx/cortex-a9/drivers/emac_drv.h index face875283..b87f7ef00d 100644 --- a/bsp/imx6sx/cortex-a9/drivers/emac_drv.h +++ b/bsp/imx6sx/cortex-a9/drivers/emac_drv.h @@ -1,6 +1,6 @@ /* * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * * SPDX-License-Identifier: Apache-2.0 * Change Logs: * Date Author Notes diff --git a/bsp/imx6sx/cortex-a9/drivers/serial.c b/bsp/imx6sx/cortex-a9/drivers/serial.c index a2d4e2338a..df6e99e298 100644 --- a/bsp/imx6sx/cortex-a9/drivers/serial.c +++ b/bsp/imx6sx/cortex-a9/drivers/serial.c @@ -1,6 +1,6 @@ /* * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * * SPDX-License-Identifier: Apache-2.0 * Change Logs: * Date Author Notes diff --git a/bsp/imx6sx/cortex-a9/drivers/serial.h b/bsp/imx6sx/cortex-a9/drivers/serial.h index 00d464bde0..69139bb75b 100644 --- a/bsp/imx6sx/cortex-a9/drivers/serial.h +++ b/bsp/imx6sx/cortex-a9/drivers/serial.h @@ -1,6 +1,6 @@ /* * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * * SPDX-License-Identifier: Apache-2.0 * Change Logs: * Date Author Notes diff --git a/bsp/imx6ul/applications/application.c b/bsp/imx6ul/applications/application.c index 98fcbfc883..4664019d29 100644 --- a/bsp/imx6ul/applications/application.c +++ b/bsp/imx6ul/applications/application.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imx6ul/applications/startup.c b/bsp/imx6ul/applications/startup.c index 4c1f83619e..e69d46fde2 100644 --- a/bsp/imx6ul/applications/startup.c +++ b/bsp/imx6ul/applications/startup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imx6ul/drivers/board.c b/bsp/imx6ul/drivers/board.c index 015a3709c1..c5caebe54c 100644 --- a/bsp/imx6ul/drivers/board.c +++ b/bsp/imx6ul/drivers/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imx6ul/drivers/board.h b/bsp/imx6ul/drivers/board.h index 76593e2f08..4b5c5fb824 100644 --- a/bsp/imx6ul/drivers/board.h +++ b/bsp/imx6ul/drivers/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imx6ul/drivers/imx6ul.h b/bsp/imx6ul/drivers/imx6ul.h index 7f0db1354f..3f0d84aea4 100644 --- a/bsp/imx6ul/drivers/imx6ul.h +++ b/bsp/imx6ul/drivers/imx6ul.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/imxrt1052-atk-commander/applications/main.c b/bsp/imxrt/imxrt1052-atk-commander/applications/main.c index 928528af45..c5581d6e31 100644 --- a/bsp/imxrt/imxrt1052-atk-commander/applications/main.c +++ b/bsp/imxrt/imxrt1052-atk-commander/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/imxrt1052-atk-commander/board/board.c b/bsp/imxrt/imxrt1052-atk-commander/board/board.c index e50e511070..5a7e721098 100644 --- a/bsp/imxrt/imxrt1052-atk-commander/board/board.c +++ b/bsp/imxrt/imxrt1052-atk-commander/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/imxrt1052-atk-commander/board/board.h b/bsp/imxrt/imxrt1052-atk-commander/board/board.h index 100b932ebd..e7d411f546 100644 --- a/bsp/imxrt/imxrt1052-atk-commander/board/board.h +++ b/bsp/imxrt/imxrt1052-atk-commander/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/imxrt1052-atk-commander/board/ports/sdram_port.h b/bsp/imxrt/imxrt1052-atk-commander/board/ports/sdram_port.h index 477987b4e7..c6fa1258a5 100644 --- a/bsp/imxrt/imxrt1052-atk-commander/board/ports/sdram_port.h +++ b/bsp/imxrt/imxrt1052-atk-commander/board/ports/sdram_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/imxrt1052-atk-commander/board/ports/spi_flash_init.c b/bsp/imxrt/imxrt1052-atk-commander/board/ports/spi_flash_init.c index 8137c00f5e..16f1b1fa77 100644 --- a/bsp/imxrt/imxrt1052-atk-commander/board/ports/spi_flash_init.c +++ b/bsp/imxrt/imxrt1052-atk-commander/board/ports/spi_flash_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/imxrt1052-fire-pro/applications/main.c b/bsp/imxrt/imxrt1052-fire-pro/applications/main.c index 9240eb5265..03b5dfce2e 100644 --- a/bsp/imxrt/imxrt1052-fire-pro/applications/main.c +++ b/bsp/imxrt/imxrt1052-fire-pro/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/imxrt1052-fire-pro/board/board.c b/bsp/imxrt/imxrt1052-fire-pro/board/board.c index ee95ab47cb..44bd945113 100644 --- a/bsp/imxrt/imxrt1052-fire-pro/board/board.c +++ b/bsp/imxrt/imxrt1052-fire-pro/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/imxrt1052-fire-pro/board/board.h b/bsp/imxrt/imxrt1052-fire-pro/board/board.h index 100b932ebd..e7d411f546 100644 --- a/bsp/imxrt/imxrt1052-fire-pro/board/board.h +++ b/bsp/imxrt/imxrt1052-fire-pro/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/imxrt1052-nxp-evk/applications/main.c b/bsp/imxrt/imxrt1052-nxp-evk/applications/main.c index 09ba861d27..b84a167611 100644 --- a/bsp/imxrt/imxrt1052-nxp-evk/applications/main.c +++ b/bsp/imxrt/imxrt1052-nxp-evk/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/imxrt1052-nxp-evk/applications/mnt.c b/bsp/imxrt/imxrt1052-nxp-evk/applications/mnt.c index e690a296f7..a676a0daac 100644 --- a/bsp/imxrt/imxrt1052-nxp-evk/applications/mnt.c +++ b/bsp/imxrt/imxrt1052-nxp-evk/applications/mnt.c @@ -17,19 +17,19 @@ extern struct dfs_ramfs *dfs_ramfs_create(rt_uint8_t *pool, rt_size_t size); int mnt_init(void) { - rt_uint8_t *pool = RT_NULL; - rt_size_t size = 8*1024*1024; + rt_uint8_t *pool = RT_NULL; + rt_size_t size = 8*1024*1024; - pool = rt_malloc(size); - if (pool == RT_NULL) - return 0; + pool = rt_malloc(size); + if (pool == RT_NULL) + return 0; - if (dfs_mount(RT_NULL, "/", "ram", 0, (const void *)dfs_ramfs_create(pool, size)) == 0) - rt_kprintf("RAM file system initializated!\n"); - else - rt_kprintf("RAM file system initializate failed!\n"); + if (dfs_mount(RT_NULL, "/", "ram", 0, (const void *)dfs_ramfs_create(pool, size)) == 0) + rt_kprintf("RAM file system initializated!\n"); + else + rt_kprintf("RAM file system initializate failed!\n"); - return 0; + return 0; } INIT_ENV_EXPORT(mnt_init); #endif diff --git a/bsp/imxrt/imxrt1052-nxp-evk/board/board.c b/bsp/imxrt/imxrt1052-nxp-evk/board/board.c index 0566c21662..631cad8411 100644 --- a/bsp/imxrt/imxrt1052-nxp-evk/board/board.c +++ b/bsp/imxrt/imxrt1052-nxp-evk/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -259,8 +259,8 @@ void imxrt_enet_pins_init(void) CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */ IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ IOMUXC_SetPinMux( IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 is configured as GPIO1_IO10 */ 0U); diff --git a/bsp/imxrt/imxrt1052-nxp-evk/board/board.h b/bsp/imxrt/imxrt1052-nxp-evk/board/board.h index 1a14ad8737..8439778c00 100644 --- a/bsp/imxrt/imxrt1052-nxp-evk/board/board.h +++ b/bsp/imxrt/imxrt1052-nxp-evk/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/imxrt1052-nxp-evk/board/ports/sdram_port.h b/bsp/imxrt/imxrt1052-nxp-evk/board/ports/sdram_port.h index 477987b4e7..c6fa1258a5 100644 --- a/bsp/imxrt/imxrt1052-nxp-evk/board/ports/sdram_port.h +++ b/bsp/imxrt/imxrt1052-nxp-evk/board/ports/sdram_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/imxrt1064-nxp-evk/applications/main.c b/bsp/imxrt/imxrt1064-nxp-evk/applications/main.c index 12c9d0df52..bc04737db3 100644 --- a/bsp/imxrt/imxrt1064-nxp-evk/applications/main.c +++ b/bsp/imxrt/imxrt1064-nxp-evk/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/imxrt1064-nxp-evk/board/board.c b/bsp/imxrt/imxrt1064-nxp-evk/board/board.c index a56282ea00..71955bcae5 100644 --- a/bsp/imxrt/imxrt1064-nxp-evk/board/board.c +++ b/bsp/imxrt/imxrt1064-nxp-evk/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/imxrt1064-nxp-evk/board/board.h b/bsp/imxrt/imxrt1064-nxp-evk/board/board.h index 692569842b..ccd39d72df 100644 --- a/bsp/imxrt/imxrt1064-nxp-evk/board/board.h +++ b/bsp/imxrt/imxrt1064-nxp-evk/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_adc.c b/bsp/imxrt/libraries/drivers/drv_adc.c index 788ad08daf..3ddf69b465 100644 --- a/bsp/imxrt/libraries/drivers/drv_adc.c +++ b/bsp/imxrt/libraries/drivers/drv_adc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_adc.h b/bsp/imxrt/libraries/drivers/drv_adc.h index 0113b54f3e..412b5f3cd2 100644 --- a/bsp/imxrt/libraries/drivers/drv_adc.h +++ b/bsp/imxrt/libraries/drivers/drv_adc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_can.c b/bsp/imxrt/libraries/drivers/drv_can.c index 829060e2d7..377e36bcc7 100644 --- a/bsp/imxrt/libraries/drivers/drv_can.c +++ b/bsp/imxrt/libraries/drivers/drv_can.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -375,7 +375,7 @@ static int can_send(struct rt_can_device *can_dev, const void *buf, rt_uint32_t ret = RT_EBUSY; break; } - + return ret; } diff --git a/bsp/imxrt/libraries/drivers/drv_can.h b/bsp/imxrt/libraries/drivers/drv_can.h index d5d2b13f2e..1ea524e98c 100644 --- a/bsp/imxrt/libraries/drivers/drv_can.h +++ b/bsp/imxrt/libraries/drivers/drv_can.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2019-06-28 misonyo the first version. */ - + #ifndef DRV_CAN_H__ #define DRV_CAN_H__ diff --git a/bsp/imxrt/libraries/drivers/drv_eth.c b/bsp/imxrt/libraries/drivers/drv_eth.c index db919eb376..c10d7b76c6 100644 --- a/bsp/imxrt/libraries/drivers/drv_eth.c +++ b/bsp/imxrt/libraries/drivers/drv_eth.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -328,7 +328,7 @@ static status_t _ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const ui #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ pbuf_copy_partial((const struct pbuf *)data, (void *)address, length, 0); - + /* Set data length. */ curBuffDescrip->length = length; #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE @@ -433,7 +433,7 @@ static status_t _ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const ui address = (uint32_t)curBuffDescrip->buffer; #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ DCACHE_CleanByRange(address, handle->txBuffSizeAlign[0]); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ /* Active the transmit buffer descriptor. */ _ENET_ActiveSend(base, 0); @@ -453,8 +453,8 @@ static status_t _ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const ui /* transmit packet. */ rt_err_t rt_imxrt_eth_tx(rt_device_t dev, struct pbuf *p) { - rt_err_t result = RT_EOK; - enet_handle_t * enet_handle = &imxrt_eth_device.enet_handle; + rt_err_t result = RT_EOK; + enet_handle_t * enet_handle = &imxrt_eth_device.enet_handle; RT_ASSERT(p != NULL); RT_ASSERT(enet_handle != RT_NULL); diff --git a/bsp/imxrt/libraries/drivers/drv_gpio.c b/bsp/imxrt/libraries/drivers/drv_gpio.c index a2e9dda3d7..3e27a1e9c3 100644 --- a/bsp/imxrt/libraries/drivers/drv_gpio.c +++ b/bsp/imxrt/libraries/drivers/drv_gpio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -70,7 +70,7 @@ const struct pin_mask mask_tab[5] = #endif }; -const rt_int8_t reg_offset[] = +const rt_int8_t reg_offset[] = { #if defined(SOC_IMXRT1015_SERIES) 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 64, 65, 66, 67, 68, 69, diff --git a/bsp/imxrt/libraries/drivers/drv_gpio.h b/bsp/imxrt/libraries/drivers/drv_gpio.h index cf1a80ffbb..c2de77d933 100644 --- a/bsp/imxrt/libraries/drivers/drv_gpio.h +++ b/bsp/imxrt/libraries/drivers/drv_gpio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,12 +7,12 @@ * Date Author Notes * 2018-4-30 misonyo the first version. */ - + #ifndef DRV_GPIO_H__ #define DRV_GPIO_H__ -#include -#include +#include +#include #define GET_PIN(PORTx, PIN) (32 * (PORTx - 1) + (PIN & 31)) /* PORTx:1,2,3,4,5 */ diff --git a/bsp/imxrt/libraries/drivers/drv_hwtimer.c b/bsp/imxrt/libraries/drivers/drv_hwtimer.c index f29c4debbb..2d23a9c3c6 100644 --- a/bsp/imxrt/libraries/drivers/drv_hwtimer.c +++ b/bsp/imxrt/libraries/drivers/drv_hwtimer.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_hwtimer.h b/bsp/imxrt/libraries/drivers/drv_hwtimer.h index 441665c6e8..04d64d79e4 100644 --- a/bsp/imxrt/libraries/drivers/drv_hwtimer.h +++ b/bsp/imxrt/libraries/drivers/drv_hwtimer.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_i2c.c b/bsp/imxrt/libraries/drivers/drv_i2c.c index 117b29f3d3..d01ac4180d 100644 --- a/bsp/imxrt/libraries/drivers/drv_i2c.c +++ b/bsp/imxrt/libraries/drivers/drv_i2c.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_i2c.h b/bsp/imxrt/libraries/drivers/drv_i2c.h index df36d828d1..699a30f8a3 100644 --- a/bsp/imxrt/libraries/drivers/drv_i2c.h +++ b/bsp/imxrt/libraries/drivers/drv_i2c.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_lcd.c b/bsp/imxrt/libraries/drivers/drv_lcd.c index 96e231e479..edc3e541cf 100644 --- a/bsp/imxrt/libraries/drivers/drv_lcd.c +++ b/bsp/imxrt/libraries/drivers/drv_lcd.c @@ -8,7 +8,7 @@ * 2017-10-30 Tanek the first version * 2018-04-05 Liu2guang export LCD config parameters. */ - + #include #ifdef BSP_USING_LCD diff --git a/bsp/imxrt/libraries/drivers/drv_log.h b/bsp/imxrt/libraries/drivers/drv_log.h index 7e0bfee5b4..3fe511789b 100644 --- a/bsp/imxrt/libraries/drivers/drv_log.h +++ b/bsp/imxrt/libraries/drivers/drv_log.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_pwm.c b/bsp/imxrt/libraries/drivers/drv_pwm.c index fdfb8907f6..370b75431c 100644 --- a/bsp/imxrt/libraries/drivers/drv_pwm.c +++ b/bsp/imxrt/libraries/drivers/drv_pwm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_pwm.h b/bsp/imxrt/libraries/drivers/drv_pwm.h index 7260c0c587..47e50a435b 100644 --- a/bsp/imxrt/libraries/drivers/drv_pwm.h +++ b/bsp/imxrt/libraries/drivers/drv_pwm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_rtc.c b/bsp/imxrt/libraries/drivers/drv_rtc.c index 84e9e51074..a7750d2e8a 100644 --- a/bsp/imxrt/libraries/drivers/drv_rtc.c +++ b/bsp/imxrt/libraries/drivers/drv_rtc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_rtc.h b/bsp/imxrt/libraries/drivers/drv_rtc.h index 593c4872bf..ca3048198b 100644 --- a/bsp/imxrt/libraries/drivers/drv_rtc.h +++ b/bsp/imxrt/libraries/drivers/drv_rtc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_sdram.h b/bsp/imxrt/libraries/drivers/drv_sdram.h index f7956c6944..9eda46bcd5 100644 --- a/bsp/imxrt/libraries/drivers/drv_sdram.h +++ b/bsp/imxrt/libraries/drivers/drv_sdram.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-03-27 Liuguang the first version. */ - + #ifndef DRV_SDRAM_H__ #define DRV_SDRAM_H__ diff --git a/bsp/imxrt/libraries/drivers/drv_spi.c b/bsp/imxrt/libraries/drivers/drv_spi.c index e0375166a2..d37561ac54 100644 --- a/bsp/imxrt/libraries/drivers/drv_spi.c +++ b/bsp/imxrt/libraries/drivers/drv_spi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -11,10 +11,10 @@ #include #ifdef BSP_USING_SPI -#include "drv_spi.h" -#include "fsl_common.h" -#include "fsl_iomuxc.h" -#include "fsl_lpspi.h" +#include "drv_spi.h" +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "fsl_lpspi.h" #include "fsl_lpspi_edma.h" #include "fsl_dmamux.h" @@ -166,21 +166,21 @@ void edma_xfer_callback(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, st rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_uint32_t pin) { - rt_err_t ret = RT_EOK; - - struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); - RT_ASSERT(spi_device != RT_NULL); - - struct imxrt_sw_spi_cs *cs_pin = (struct imxrt_sw_spi_cs *)rt_malloc(sizeof(struct imxrt_sw_spi_cs)); + rt_err_t ret = RT_EOK; + + struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); + RT_ASSERT(spi_device != RT_NULL); + + struct imxrt_sw_spi_cs *cs_pin = (struct imxrt_sw_spi_cs *)rt_malloc(sizeof(struct imxrt_sw_spi_cs)); RT_ASSERT(cs_pin != RT_NULL); - + cs_pin->pin = pin; - rt_pin_mode(pin, PIN_MODE_OUTPUT); - rt_pin_write(pin, PIN_HIGH); - - ret = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); - - return ret; + rt_pin_mode(pin, PIN_MODE_OUTPUT); + rt_pin_write(pin, PIN_HIGH); + + ret = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); + + return ret; } static uint32_t imxrt_get_lpspi_freq(void) @@ -188,31 +188,31 @@ static uint32_t imxrt_get_lpspi_freq(void) uint32_t freq = 0; /* CLOCK_GetMux(kCLOCK_LpspiMux): - 00b: derive clock from PLL3 PFD1 720M - 01b: derive clock from PLL3 PFD0 720M - 10b: derive clock from PLL2 528M - 11b: derive clock from PLL2 PFD2 396M + 00b: derive clock from PLL3 PFD1 720M + 01b: derive clock from PLL3 PFD0 720M + 10b: derive clock from PLL2 528M + 11b: derive clock from PLL2 PFD2 396M */ switch(CLOCK_GetMux(kCLOCK_LpspiMux)) { case 0: - freq = CLOCK_GetFreq(kCLOCK_Usb1PllPfd1Clk); - break; - + freq = CLOCK_GetFreq(kCLOCK_Usb1PllPfd1Clk); + break; + case 1: - freq = CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk); - break; - + freq = CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk); + break; + case 2: - freq = CLOCK_GetFreq(kCLOCK_SysPllClk); - break; - + freq = CLOCK_GetFreq(kCLOCK_SysPllClk); + break; + case 3: - freq = CLOCK_GetFreq(kCLOCK_SysPllPfd2Clk); - break; + freq = CLOCK_GetFreq(kCLOCK_SysPllPfd2Clk); + break; } - - freq /= (CLOCK_GetDiv(kCLOCK_LpspiDiv) + 1U); + + freq /= (CLOCK_GetDiv(kCLOCK_LpspiDiv) + 1U); return freq; } @@ -228,7 +228,7 @@ static void lpspi_dma_config(struct imxrt_spi *spi) DMAMUX_SetSource(DMAMUX, spi->dma->tx_channel, spi->dma->tx_request); DMAMUX_EnableChannel(DMAMUX, spi->dma->tx_channel); EDMA_CreateHandle(&spi->dma->tx_edma, DMA0, spi->dma->tx_channel); - + LPSPI_MasterTransferCreateHandleEDMA(spi->base, &spi->dma->spi_edma, edma_xfer_callback, @@ -241,8 +241,8 @@ static void lpspi_dma_config(struct imxrt_spi *spi) static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg) { - lpspi_master_config_t masterConfig; - struct imxrt_spi *spi = RT_NULL; + lpspi_master_config_t masterConfig; + struct imxrt_spi *spi = RT_NULL; RT_ASSERT(cfg != RT_NULL); RT_ASSERT(device != RT_NULL); @@ -252,76 +252,76 @@ static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_config if(cfg->data_width != 8 && cfg->data_width != 16 && cfg->data_width != 32) { - return RT_EINVAL; + return RT_EINVAL; } - LPSPI_MasterGetDefaultConfig(&masterConfig); - + LPSPI_MasterGetDefaultConfig(&masterConfig); + if(cfg->max_hz > 40*1000*1000) { cfg->max_hz = 40*1000*1000; } - masterConfig.baudRate = cfg->max_hz; - masterConfig.bitsPerFrame = cfg->data_width; - + masterConfig.baudRate = cfg->max_hz; + masterConfig.bitsPerFrame = cfg->data_width; + if(cfg->mode & RT_SPI_MSB) { - masterConfig.direction = kLPSPI_MsbFirst; + masterConfig.direction = kLPSPI_MsbFirst; } else { - masterConfig.direction = kLPSPI_LsbFirst; + masterConfig.direction = kLPSPI_LsbFirst; } - + if(cfg->mode & RT_SPI_CPHA) { - masterConfig.cpha = kLPSPI_ClockPhaseSecondEdge; + masterConfig.cpha = kLPSPI_ClockPhaseSecondEdge; } else { - masterConfig.cpha = kLPSPI_ClockPhaseFirstEdge; + masterConfig.cpha = kLPSPI_ClockPhaseFirstEdge; } - + if(cfg->mode & RT_SPI_CPOL) { - masterConfig.cpol = kLPSPI_ClockPolarityActiveLow; + masterConfig.cpol = kLPSPI_ClockPolarityActiveLow; } else { - masterConfig.cpol = kLPSPI_ClockPolarityActiveHigh; + masterConfig.cpol = kLPSPI_ClockPolarityActiveHigh; } - masterConfig.pinCfg = kLPSPI_SdiInSdoOut; + masterConfig.pinCfg = kLPSPI_SdiInSdoOut; masterConfig.dataOutConfig = kLpspiDataOutTristate; - masterConfig.pcsToSckDelayInNanoSec = 1000000000 / masterConfig.baudRate; - masterConfig.lastSckToPcsDelayInNanoSec = 1000000000 / masterConfig.baudRate; - masterConfig.betweenTransferDelayInNanoSec = 1000000000 / masterConfig.baudRate; + masterConfig.pcsToSckDelayInNanoSec = 1000000000 / masterConfig.baudRate; + masterConfig.lastSckToPcsDelayInNanoSec = 1000000000 / masterConfig.baudRate; + masterConfig.betweenTransferDelayInNanoSec = 1000000000 / masterConfig.baudRate; - LPSPI_MasterInit(spi->base, &masterConfig, imxrt_get_lpspi_freq()); - spi->base->CFGR1 |= LPSPI_CFGR1_PCSCFG_MASK; + LPSPI_MasterInit(spi->base, &masterConfig, imxrt_get_lpspi_freq()); + spi->base->CFGR1 |= LPSPI_CFGR1_PCSCFG_MASK; return RT_EOK; } static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message) { - lpspi_transfer_t transfer; + lpspi_transfer_t transfer; status_t status; RT_ASSERT(device != RT_NULL); RT_ASSERT(device->bus != RT_NULL); RT_ASSERT(device->bus->parent.user_data != RT_NULL); - struct imxrt_spi *spi = (struct imxrt_spi *)(device->bus->parent.user_data); - struct imxrt_sw_spi_cs *cs = device->parent.user_data; + struct imxrt_spi *spi = (struct imxrt_spi *)(device->bus->parent.user_data); + struct imxrt_sw_spi_cs *cs = device->parent.user_data; if(message->cs_take) { rt_pin_write(cs->pin, PIN_LOW); } - transfer.dataSize = message->length; - transfer.rxData = (uint8_t *)(message->recv_buf); - transfer.txData = (uint8_t *)(message->send_buf); + transfer.dataSize = message->length; + transfer.rxData = (uint8_t *)(message->recv_buf); + transfer.txData = (uint8_t *)(message->send_buf); if(RT_FALSE == spi->dma_flag) { @@ -343,10 +343,10 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message * message->length = 0; } - return message->length; + return message->length; } -static struct rt_spi_ops imxrt_spi_ops = +static struct rt_spi_ops imxrt_spi_ops = { .configure = spi_configure, .xfer = spixfer @@ -371,8 +371,8 @@ int rt_hw_spi_bus_init(void) } } - return ret; + return ret; } -INIT_BOARD_EXPORT(rt_hw_spi_bus_init); +INIT_BOARD_EXPORT(rt_hw_spi_bus_init); #endif /* BSP_USING_SPI */ diff --git a/bsp/imxrt/libraries/drivers/drv_spi.h b/bsp/imxrt/libraries/drivers/drv_spi.h index 54f1744be0..4cd4c1a2bb 100644 --- a/bsp/imxrt/libraries/drivers/drv_spi.h +++ b/bsp/imxrt/libraries/drivers/drv_spi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-03-27 Liuguang the first version. */ - + #ifndef DRV_SPI_H__ #define DRV_SPI_H__ diff --git a/bsp/imxrt/libraries/drivers/drv_uart.c b/bsp/imxrt/libraries/drivers/drv_uart.c index d471f29dec..2873cf0df5 100644 --- a/bsp/imxrt/libraries/drivers/drv_uart.c +++ b/bsp/imxrt/libraries/drivers/drv_uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -461,7 +461,7 @@ void edma_rx_callback(struct _edma_handle *handle, void *userData, bool transfer recv_len = uart->serial.config.bufsz - uart->dma_rx->last_index; uart->dma_rx->last_index = 0; } - else + else { /* clear half interrupt */ EDMA_ClearChannelStatusFlags(DMA0, uart->dma_rx->channel,kEDMA_InterruptFlag); diff --git a/bsp/imxrt/libraries/drivers/drv_uart.h b/bsp/imxrt/libraries/drivers/drv_uart.h index efcbe15de5..8de414d21e 100644 --- a/bsp/imxrt/libraries/drivers/drv_uart.h +++ b/bsp/imxrt/libraries/drivers/drv_uart.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_wdt.c b/bsp/imxrt/libraries/drivers/drv_wdt.c index 0e18ddca29..2190b1f9ed 100644 --- a/bsp/imxrt/libraries/drivers/drv_wdt.c +++ b/bsp/imxrt/libraries/drivers/drv_wdt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_wdt.h b/bsp/imxrt/libraries/drivers/drv_wdt.h index 612009b453..4819f4958b 100644 --- a/bsp/imxrt/libraries/drivers/drv_wdt.h +++ b/bsp/imxrt/libraries/drivers/drv_wdt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/templates/imxrt1050xxx/applications/main.c b/bsp/imxrt/libraries/templates/imxrt1050xxx/applications/main.c index 4365059073..1f971ee64a 100644 --- a/bsp/imxrt/libraries/templates/imxrt1050xxx/applications/main.c +++ b/bsp/imxrt/libraries/templates/imxrt1050xxx/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/templates/imxrt1050xxx/board/board.c b/bsp/imxrt/libraries/templates/imxrt1050xxx/board/board.c index e50e511070..5a7e721098 100644 --- a/bsp/imxrt/libraries/templates/imxrt1050xxx/board/board.c +++ b/bsp/imxrt/libraries/templates/imxrt1050xxx/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/templates/imxrt1050xxx/board/board.h b/bsp/imxrt/libraries/templates/imxrt1050xxx/board/board.h index 100b932ebd..e7d411f546 100644 --- a/bsp/imxrt/libraries/templates/imxrt1050xxx/board/board.h +++ b/bsp/imxrt/libraries/templates/imxrt1050xxx/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/templates/imxrt1064xxx/applications/main.c b/bsp/imxrt/libraries/templates/imxrt1064xxx/applications/main.c index 12c9d0df52..bc04737db3 100644 --- a/bsp/imxrt/libraries/templates/imxrt1064xxx/applications/main.c +++ b/bsp/imxrt/libraries/templates/imxrt1064xxx/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/templates/imxrt1064xxx/board/board.c b/bsp/imxrt/libraries/templates/imxrt1064xxx/board/board.c index 44fb588f34..5c51454325 100644 --- a/bsp/imxrt/libraries/templates/imxrt1064xxx/board/board.c +++ b/bsp/imxrt/libraries/templates/imxrt1064xxx/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/templates/imxrt1064xxx/board/board.h b/bsp/imxrt/libraries/templates/imxrt1064xxx/board/board.h index 4dd28fd5dd..a934a2757a 100644 --- a/bsp/imxrt/libraries/templates/imxrt1064xxx/board/board.h +++ b/bsp/imxrt/libraries/templates/imxrt1064xxx/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lm3s8962/applications/application.c b/bsp/lm3s8962/applications/application.c index 97b8c67dba..504962eb66 100644 --- a/bsp/lm3s8962/applications/application.c +++ b/bsp/lm3s8962/applications/application.c @@ -33,45 +33,45 @@ void rt_init_thread_entry(void *parameter) { /* Filesystem Initialization */ #ifdef RT_USING_DFS - { - /* init the device filesystem */ - dfs_init(); + { + /* init the device filesystem */ + dfs_init(); #ifdef RT_USING_DFS_ELMFAT - /* init the elm chan FatFs filesystam*/ - elm_init(); + /* init the elm chan FatFs filesystam*/ + elm_init(); - /* mount sd card fat partition 1 as root directory */ - if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) - { - rt_kprintf("File System initialized!\n"); - } - else - rt_kprintf("File System initialzation failed!\n"); + /* mount sd card fat partition 1 as root directory */ + if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) + { + rt_kprintf("File System initialized!\n"); + } + else + rt_kprintf("File System initialzation failed!\n"); #endif - } + } #endif /* LwIP Initialization */ #ifdef RT_USING_LWIP - { - extern void lwip_sys_init(void); - - /* init lwip system */ - lwip_sys_init(); - rt_kprintf("TCP/IP initialized!\n"); - } + { + extern void lwip_sys_init(void); + + /* init lwip system */ + lwip_sys_init(); + rt_kprintf("TCP/IP initialized!\n"); + } #endif } int rt_application_init() { - rt_thread_t init_thread; + rt_thread_t init_thread; - init_thread = rt_thread_create("init", - rt_init_thread_entry, RT_NULL, - 1024, 21, 20); - rt_thread_startup(init_thread); + init_thread = rt_thread_create("init", + rt_init_thread_entry, RT_NULL, + 1024, 21, 20); + rt_thread_startup(init_thread); - return 0; + return 0; } /*@}*/ diff --git a/bsp/lm3s8962/applications/startup.c b/bsp/lm3s8962/applications/startup.c index d598ee8fc7..45f510a2aa 100644 --- a/bsp/lm3s8962/applications/startup.c +++ b/bsp/lm3s8962/applications/startup.c @@ -58,11 +58,11 @@ extern int __bss_end; *******************************************************************************/ void assert_failed(u8* file, u32 line) { - rt_kprintf("\n\r Wrong parameter value detected on\r\n"); - rt_kprintf(" file %s\r\n", file); - rt_kprintf(" line %d\r\n", line); + rt_kprintf("\n\r Wrong parameter value detected on\r\n"); + rt_kprintf(" file %s\r\n", file); + rt_kprintf(" line %d\r\n", line); - while (1) ; + while (1) ; } #endif @@ -71,82 +71,82 @@ void assert_failed(u8* file, u32 line) */ void rtthread_startup(void) { - /* init board */ - rt_hw_board_init(); + /* init board */ + rt_hw_board_init(); - /* show version */ - rt_show_version(); + /* show version */ + rt_show_version(); - /* init tick */ - rt_system_tick_init(); + /* init tick */ + rt_system_tick_init(); - /* init kernel object */ - rt_system_object_init(); + /* init kernel object */ + rt_system_object_init(); - /* init timer system */ - rt_system_timer_init(); + /* init timer system */ + rt_system_timer_init(); #ifdef RT_USING_HEAP #ifdef __CC_ARM - rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)LM3S_SRAM_END); + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)LM3S_SRAM_END); #elif __ICCARM__ - rt_system_heap_init(__segment_end("HEAP"), (void*)LM3S_SRAM_END); + rt_system_heap_init(__segment_end("HEAP"), (void*)LM3S_SRAM_END); #else - /* init memory system */ - rt_system_heap_init((void*)&__bss_end, (void*)LM3S_SRAM_END); + /* init memory system */ + rt_system_heap_init((void*)&__bss_end, (void*)LM3S_SRAM_END); #endif #endif -#ifdef RT_USING_MODULE - /* init module system */ - rt_system_module_init(); +#ifdef RT_USING_MODULE + /* init module system */ + rt_system_module_init(); #endif - /* init scheduler system */ - rt_system_scheduler_init(); + /* init scheduler system */ + rt_system_scheduler_init(); #ifdef RT_USING_LWIP - eth_system_device_init(); + eth_system_device_init(); - /* register ethernetif device */ - rt_hw_luminaryif_init(); + /* register ethernetif device */ + rt_hw_luminaryif_init(); #endif - /* init hardware serial device */ - rt_hw_serial_init(); + /* init hardware serial device */ + rt_hw_serial_init(); #ifdef RT_USING_DFS - /* init sd card device */ - rt_hw_sdcard_init(); + /* init sd card device */ + rt_hw_sdcard_init(); #endif - /* init application */ - rt_application_init(); + /* init application */ + rt_application_init(); #ifdef RT_USING_FINSH - /* init finsh */ - finsh_system_init(); + /* init finsh */ + finsh_system_init(); #ifdef RT_USING_DEVICE - finsh_set_device("uart1"); + finsh_set_device("uart1"); #endif #endif - /* init idle thread */ - rt_thread_idle_init(); + /* init idle thread */ + rt_thread_idle_init(); - /* start scheduler */ - rt_system_scheduler_start(); + /* start scheduler */ + rt_system_scheduler_start(); - /* never reach here */ - return ; + /* never reach here */ + return ; } int main(void) { - /* disable interrupt first */ - rt_hw_interrupt_disable(); - rtthread_startup(); - - return 0; + /* disable interrupt first */ + rt_hw_interrupt_disable(); + rtthread_startup(); + + return 0; } /*@}*/ diff --git a/bsp/lm3s8962/drivers/board.c b/bsp/lm3s8962/drivers/board.c index f7a75b0809..ca7e7d7818 100644 --- a/bsp/lm3s8962/drivers/board.c +++ b/bsp/lm3s8962/drivers/board.c @@ -37,23 +37,23 @@ static void rt_hw_console_init(void); extern void rt_hw_interrupt_thread_switch(void); /** * This is the timer interrupt service routine. - * + * */ void rt_hw_timer_handler(void) { - /* enter interrupt */ - rt_interrupt_enter(); - - rt_tick_increase(); - - /* leave interrupt */ - rt_interrupt_leave(); - rt_hw_interrupt_thread_switch(); + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); + rt_hw_interrupt_thread_switch(); } /** * This is the ethernet interrupt service routine. - * + * */ void rt_hw_eth_handler(void) { @@ -76,51 +76,51 @@ void rt_hw_eth_handler(void) */ void rt_hw_board_init() { - /* set ldo */ - SysCtlLDOSet(SYSCTL_LDO_2_50V); - /* set clock */ - SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | + /* set ldo */ + SysCtlLDOSet(SYSCTL_LDO_2_50V); + /* set clock */ + SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | LM3S_XTAL_TYPE); - /* init systick */ - SysTickDisable(); - SysTickPeriodSet(SysCtlClockGet()/RT_TICK_PER_SECOND); - SysTickIntEnable(); - SysTickEnable(); + /* init systick */ + SysTickDisable(); + SysTickPeriodSet(SysCtlClockGet()/RT_TICK_PER_SECOND); + SysTickIntEnable(); + SysTickEnable(); + + /* enable ssio */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); - /* enable ssio */ - SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); - - /* init console */ - rt_hw_console_init(); + /* init console */ + rt_hw_console_init(); - /* enable interrupt */ - IntMasterEnable(); + /* enable interrupt */ + IntMasterEnable(); } /* init console to support rt_kprintf */ static void rt_hw_console_init() { - /* Enable the UART0 peripherals */ - SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + /* Enable the UART0 peripherals */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); - /* Set GPIO A0 and A1 as UART pins. */ - GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); + /* Set GPIO A0 and A1 as UART pins. */ + GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); - /* Configure the UART for 115,200, 8-N-1 operation. */ - UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), 115200, - (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | - UART_CONFIG_PAR_NONE)); + /* Configure the UART for 115,200, 8-N-1 operation. */ + UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), 115200, + (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | + UART_CONFIG_PAR_NONE)); } /* write one character to serial, must not trigger interrupt */ static void rt_hw_console_putc(const char c) { - if (c == '\n') - while(UARTCharPutNonBlocking(UART0_BASE, '\r') == false); + if (c == '\n') + while(UARTCharPutNonBlocking(UART0_BASE, '\r') == false); - while(UARTCharPutNonBlocking(UART0_BASE, c) == false); + while(UARTCharPutNonBlocking(UART0_BASE, c) == false); } /** @@ -130,10 +130,10 @@ static void rt_hw_console_putc(const char c) */ void rt_hw_console_output(const char* str) { - while (*str) - { - rt_hw_console_putc (*str++); - } + while (*str) + { + rt_hw_console_putc (*str++); + } } /*@}*/ diff --git a/bsp/lm3s8962/drivers/board.h b/bsp/lm3s8962/drivers/board.h index f33af86d26..9b01d613e4 100644 --- a/bsp/lm3s8962/drivers/board.h +++ b/bsp/lm3s8962/drivers/board.h @@ -18,12 +18,12 @@ #define __BOARD_H__ // Internal SRAM memory size[Kbytes] <8-64> -// Default: 64 +// Default: 64 #define LM3S_SRAM_SIZE 64 #define LM3S_SRAM_END (0x20000000 + LM3S_SRAM_SIZE * 1024) // For lm3s8962, it should be SYSCTL_XTAL_8MHZ -#define LM3S_XTAL_TYPE SYSCTL_XTAL_8MHZ +#define LM3S_XTAL_TYPE SYSCTL_XTAL_8MHZ void rt_hw_board_led_on(int n); void rt_hw_board_led_off(int n); diff --git a/bsp/lm3s8962/drivers/serial.c b/bsp/lm3s8962/drivers/serial.c index 0df347cf4b..b283600ecf 100644 --- a/bsp/lm3s8962/drivers/serial.c +++ b/bsp/lm3s8962/drivers/serial.c @@ -29,15 +29,15 @@ extern void rt_hw_interrupt_thread_switch(void); /* LM3S serial device */ struct rt_lm3s_serial { - /* inherit from device */ - struct rt_device parent; + /* inherit from device */ + struct rt_device parent; - rt_uint32_t hw_base; - rt_uint32_t baudrate; + rt_uint32_t hw_base; + rt_uint32_t baudrate; - /* reception field */ - rt_uint16_t save_index, read_index; - rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; + /* reception field */ + rt_uint16_t save_index, read_index; + rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; }; #ifdef RT_USING_UART1 @@ -63,72 +63,72 @@ void rt_hw_uart_isr(struct rt_lm3s_serial* serial) if (device->flag & RT_DEVICE_FLAG_INT_RX) { char ch; - rt_base_t level; + rt_base_t level; while (UARTCharsAvail(serial->hw_base)) { ch = UARTCharGetNonBlocking(serial->hw_base); /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - /* read character */ - serial->rx_buffer[serial->save_index] = ch; - serial->save_index ++; - if (serial->save_index >= RT_UART_RX_BUFFER_SIZE) - serial->save_index = 0; - - /* if the next position is read index, discard this 'read char' */ - if (serial->save_index == serial->read_index) - { - serial->read_index ++; - if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) - serial->read_index = 0; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); + level = rt_hw_interrupt_disable(); + + /* read character */ + serial->rx_buffer[serial->save_index] = ch; + serial->save_index ++; + if (serial->save_index >= RT_UART_RX_BUFFER_SIZE) + serial->save_index = 0; + + /* if the next position is read index, discard this 'read char' */ + if (serial->save_index == serial->read_index) + { + serial->read_index ++; + if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) + serial->read_index = 0; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); } - /* invoke callback */ - if(device->rx_indicate != RT_NULL) - { - rt_int32_t length; + /* invoke callback */ + if(device->rx_indicate != RT_NULL) + { + rt_int32_t length; - length = serial->save_index - serial->read_index; - if (length < 0) length += RT_UART_RX_BUFFER_SIZE; + length = serial->save_index - serial->read_index; + if (length < 0) length += RT_UART_RX_BUFFER_SIZE; device->rx_indicate(device, length); - } + } } } #ifdef RT_USING_UART1 void rt_hw_uart_isr_1(int irqno) { - /* enter interrupt */ - rt_interrupt_enter(); + /* enter interrupt */ + rt_interrupt_enter(); - /* get serial device */ - rt_hw_uart_isr(&serial1); + /* get serial device */ + rt_hw_uart_isr(&serial1); - /* leave interrupt */ - rt_interrupt_leave(); - rt_hw_interrupt_thread_switch(); + /* leave interrupt */ + rt_interrupt_leave(); + rt_hw_interrupt_thread_switch(); } #endif #ifdef RT_USING_UART2 void rt_hw_uart_isr_2(int irqno) { - /* enter interrupt */ - rt_interrupt_enter(); + /* enter interrupt */ + rt_interrupt_enter(); - /* get serial device */ - rt_hw_uart_isr(&serial2); + /* get serial device */ + rt_hw_uart_isr(&serial2); - /* leave interrupt */ - rt_interrupt_leave(); - rt_hw_interrupt_thread_switch(); + /* leave interrupt */ + rt_interrupt_leave(); + rt_hw_interrupt_thread_switch(); } #endif @@ -139,15 +139,15 @@ void rt_hw_uart_isr_2(int irqno) static rt_err_t rt_serial_init (rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) { - struct rt_lm3s_serial* serial; - serial = (struct rt_lm3s_serial*) dev; + struct rt_lm3s_serial* serial; + serial = (struct rt_lm3s_serial*) dev; - RT_ASSERT(serial != RT_NULL); + RT_ASSERT(serial != RT_NULL); if (dev->flag & RT_DEVICE_FLAG_INT_RX) { @@ -160,198 +160,198 @@ static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) UARTIntEnable(serial->hw_base, UART_INT_RX | UART_INT_RT); } - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_close(rt_device_t dev) { - struct rt_lm3s_serial* serial; - serial = (struct rt_lm3s_serial*) dev; + struct rt_lm3s_serial* serial; + serial = (struct rt_lm3s_serial*) dev; - RT_ASSERT(serial != RT_NULL); + RT_ASSERT(serial != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* disable UART rx interrupt */ - UARTIntDisable(serial->hw_base, UART_INT_RX | UART_INT_RT); - } + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* disable UART rx interrupt */ + UARTIntDisable(serial->hw_base, UART_INT_RX | UART_INT_RT); + } - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_control(rt_device_t dev, int cmd, void *args) { - return RT_EOK; + return RT_EOK; } static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - struct rt_lm3s_serial *serial = (struct rt_lm3s_serial*)dev; - RT_ASSERT(serial != RT_NULL); - - /* point to buffer */ - ptr = (rt_uint8_t*) buffer; - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - while (size) - { - /* interrupt receive */ - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - if (serial->read_index != serial->save_index) - { - *ptr = serial->rx_buffer[serial->read_index]; - - serial->read_index ++; - if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) - serial->read_index = 0; - } - else - { - /* no data in rx buffer */ - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - break; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - - ptr ++; size --; - } - - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; - } - else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) - { - /* not support right now */ - RT_ASSERT(0); - } - - /* polling mode */ - while (size) - { - *ptr = UARTCharGetNonBlocking(serial->hw_base); - - ptr ++; size --; - } - - return (rt_size_t)ptr - (rt_size_t)buffer; + rt_uint8_t* ptr; + struct rt_lm3s_serial *serial = (struct rt_lm3s_serial*)dev; + RT_ASSERT(serial != RT_NULL); + + /* point to buffer */ + ptr = (rt_uint8_t*) buffer; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + while (size) + { + /* interrupt receive */ + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + if (serial->read_index != serial->save_index) + { + *ptr = serial->rx_buffer[serial->read_index]; + + serial->read_index ++; + if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) + serial->read_index = 0; + } + else + { + /* no data in rx buffer */ + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + ptr ++; size --; + } + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) + { + /* not support right now */ + RT_ASSERT(0); + } + + /* polling mode */ + while (size) + { + *ptr = UARTCharGetNonBlocking(serial->hw_base); + + ptr ++; size --; + } + + return (rt_size_t)ptr - (rt_size_t)buffer; } static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - struct rt_lm3s_serial* serial; - char *ptr; - - serial = (struct rt_lm3s_serial*) dev; - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - /* not support */ - RT_ASSERT(0); - } - else if (dev->flag & RT_DEVICE_FLAG_DMA_TX) - { - /* not support */ - RT_ASSERT(0); - } - - /* polling write */ - ptr = (char *)buffer; - - if (dev->flag & RT_DEVICE_FLAG_STREAM) - { - /* stream mode */ - while (size) - { - if (*ptr == '\n') - while (UARTCharPutNonBlocking(serial->hw_base, '\r') == false); - - while (UARTCharPutNonBlocking(serial->hw_base, *ptr) == false); - - ptr ++; - size --; - } - } - else - { - while (size) - { - while (UARTCharPutNonBlocking(serial->hw_base, *ptr) == false); - - ptr ++; - size --; - } - } - - return (rt_size_t) ptr - (rt_size_t) buffer; + struct rt_lm3s_serial* serial; + char *ptr; + + serial = (struct rt_lm3s_serial*) dev; + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* not support */ + RT_ASSERT(0); + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_TX) + { + /* not support */ + RT_ASSERT(0); + } + + /* polling write */ + ptr = (char *)buffer; + + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* stream mode */ + while (size) + { + if (*ptr == '\n') + while (UARTCharPutNonBlocking(serial->hw_base, '\r') == false); + + while (UARTCharPutNonBlocking(serial->hw_base, *ptr) == false); + + ptr ++; + size --; + } + } + else + { + while (size) + { + while (UARTCharPutNonBlocking(serial->hw_base, *ptr) == false); + + ptr ++; + size --; + } + } + + return (rt_size_t) ptr - (rt_size_t) buffer; } void rt_hw_serial_init(void) { - struct rt_lm3s_serial* serial; + struct rt_lm3s_serial* serial; #ifdef RT_USING_UART1 - serial = &serial1; + serial = &serial1; - serial->parent.type = RT_Device_Class_Char; + serial->parent.type = RT_Device_Class_Char; - serial->hw_base = UART0_BASE; - serial->baudrate = 115200; + serial->hw_base = UART0_BASE; + serial->baudrate = 115200; - rt_memset(serial->rx_buffer, 0, sizeof(serial->rx_buffer)); - serial->read_index = serial->save_index = 0; + rt_memset(serial->rx_buffer, 0, sizeof(serial->rx_buffer)); + serial->read_index = serial->save_index = 0; - /* enable UART0 clock */ + /* enable UART0 clock */ SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); - /* set UART0 pinmux */ + /* set UART0 pinmux */ GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); - /* Configure the UART for 115,200, 8-N-1 operation. */ - UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), serial->baudrate, + /* Configure the UART for 115,200, 8-N-1 operation. */ + UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), serial->baudrate, (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE)); - serial->parent.init = rt_serial_init; - serial->parent.open = rt_serial_open; - serial->parent.close = rt_serial_close; - serial->parent.read = rt_serial_read; - serial->parent.write = rt_serial_write; - serial->parent.control = rt_serial_control; - serial->parent.user_data = RT_NULL; + serial->parent.init = rt_serial_init; + serial->parent.open = rt_serial_open; + serial->parent.close = rt_serial_close; + serial->parent.read = rt_serial_read; + serial->parent.write = rt_serial_write; + serial->parent.control = rt_serial_control; + serial->parent.user_data = RT_NULL; - rt_device_register(&serial->parent, - "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); + rt_device_register(&serial->parent, + "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); #endif #ifdef RT_USING_UART2 - serial = &serial2; + serial = &serial2; - serial->parent.type = RT_Device_Class_Char; + serial->parent.type = RT_Device_Class_Char; - serial->hw_base = 0xE0010000; - serial->baudrate = 115200; + serial->hw_base = 0xE0010000; + serial->baudrate = 115200; - rt_memset(serial->rx_buffer, 0, sizeof(serial->rx_buffer)); - serial->read_index = serial->save_index = 0; + rt_memset(serial->rx_buffer, 0, sizeof(serial->rx_buffer)); + serial->read_index = serial->save_index = 0; - serial->parent.init = rt_serial_init; - serial->parent.open = rt_serial_open; - serial->parent.close = rt_serial_close; - serial->parent.read = rt_serial_read; - serial->parent.write = rt_serial_write; - serial->parent.control = rt_serial_control; - serial->parent.user_data = RT_NULL; + serial->parent.init = rt_serial_init; + serial->parent.open = rt_serial_open; + serial->parent.close = rt_serial_close; + serial->parent.read = rt_serial_read; + serial->parent.write = rt_serial_write; + serial->parent.control = rt_serial_control; + serial->parent.user_data = RT_NULL; - rt_device_register(&serial->parent, - "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); + rt_device_register(&serial->parent, + "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); #endif } diff --git a/bsp/lm3s8962/rtconfig.h b/bsp/lm3s8962/rtconfig.h index b154688a6d..a3f054b1c6 100644 --- a/bsp/lm3s8962/rtconfig.h +++ b/bsp/lm3s8962/rtconfig.h @@ -3,16 +3,16 @@ #define __RTTHREAD_CFG_H__ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX*/ -#define RT_THREAD_PRIORITY_MAX 32 +#define RT_THREAD_PRIORITY_MAX 32 /* Tick per Second*/ -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 /* SECTION: RT_DEBUG */ /* Thread Debug*/ @@ -66,7 +66,7 @@ /* SECTION: Console options */ #define RT_USING_CONSOLE /* the buffer size of console*/ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 /* SECTION: FinSH shell options */ /* Using FinSH as Shell*/ @@ -81,11 +81,11 @@ #define RT_DFS_ELM_WORD_ACCESS /* the max number of mounted filesystem */ -#define DFS_FILESYSTEMS_MAX 1 -/* the max number of opened files */ -#define DFS_FD_MAX 4 -/* the max number of cached sector */ -#define DFS_CACHE_MAX_NUM 4 +#define DFS_FILESYSTEMS_MAX 1 +/* the max number of opened files */ +#define DFS_FD_MAX 4 +/* the max number of cached sector */ +#define DFS_CACHE_MAX_NUM 4 /* SECTION: lwip, a lighwight TCP/IP protocol stack */ /* Using lighweight TCP/IP protocol stack*/ @@ -107,13 +107,13 @@ #define RT_LWIP_TCP /* the number of simulatenously active TCP connections*/ -#define RT_LWIP_TCP_PCB_NUM 5 +#define RT_LWIP_TCP_PCB_NUM 5 /* Ethernet padding size */ #define RT_LWIP_ETH_PAD_SIZE 2 /* TCP sender buffer space*/ -#define RT_LWIP_TCP_SND_BUF 1024*8 +#define RT_LWIP_TCP_SND_BUF 1024*8 /* Enable SNMP protocol*/ #define RT_LWIP_SNMP @@ -132,17 +132,17 @@ #define RT_LWIP_MSKADDR "255.255.255.0" /* tcp thread options */ -#define RT_LWIP_TCPTHREAD_PRIORITY 22 -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4 -#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 +#define RT_LWIP_TCPTHREAD_PRIORITY 22 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4 +#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 /* ethernet if thread options */ -#define RT_LWIP_ETHTHREAD_PRIORITY 23 -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4 -#define RT_LWIP_ETHTHREAD_STACKSIZE 512 +#define RT_LWIP_ETHTHREAD_PRIORITY 23 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4 +#define RT_LWIP_ETHTHREAD_STACKSIZE 512 /* the size of each pbuf in the pbuf pool. */ -#define RT_LWIP_PBUF_POOL_BUFSIZE 1500 +#define RT_LWIP_PBUF_POOL_BUFSIZE 1500 #define RT_USING_LIBC #define RT_USING_LWIP141 diff --git a/bsp/lm3s9b9x/applications/application.c b/bsp/lm3s9b9x/applications/application.c index c80c3047aa..bd383aefe6 100644 --- a/bsp/lm3s9b9x/applications/application.c +++ b/bsp/lm3s9b9x/applications/application.c @@ -35,45 +35,45 @@ void rt_init_thread_entry(void *parameter) { /* Filesystem Initialization */ #ifdef RT_USING_DFS - { - /* init the device filesystem */ - dfs_init(); + { + /* init the device filesystem */ + dfs_init(); #ifdef RT_USING_DFS_ELMFAT - /* init the elm chan FatFs filesystam*/ - elm_init(); + /* init the elm chan FatFs filesystam*/ + elm_init(); - /* mount sd card fat partition 1 as root directory */ - if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) - { - rt_kprintf("File System initialized!\n"); - } - else - rt_kprintf("File System initialzation failed!\n"); + /* mount sd card fat partition 1 as root directory */ + if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) + { + rt_kprintf("File System initialized!\n"); + } + else + rt_kprintf("File System initialzation failed!\n"); #endif - } + } #endif /* LwIP Initialization */ #ifdef RT_USING_LWIP - { - extern void lwip_sys_init(void); - - /* init lwip system */ - lwip_sys_init(); - rt_kprintf("TCP/IP initialized!\n"); - } + { + extern void lwip_sys_init(void); + + /* init lwip system */ + lwip_sys_init(); + rt_kprintf("TCP/IP initialized!\n"); + } #endif } int rt_application_init() { - rt_thread_t init_thread; + rt_thread_t init_thread; - init_thread = rt_thread_create("init", - rt_init_thread_entry, RT_NULL, - 1024, 21, 20); - rt_thread_startup(init_thread); + init_thread = rt_thread_create("init", + rt_init_thread_entry, RT_NULL, + 1024, 21, 20); + rt_thread_startup(init_thread); - return 0; + return 0; } /*@}*/ diff --git a/bsp/lm3s9b9x/applications/startup.c b/bsp/lm3s9b9x/applications/startup.c index 2e8ad05d7b..8694d2d36c 100644 --- a/bsp/lm3s9b9x/applications/startup.c +++ b/bsp/lm3s9b9x/applications/startup.c @@ -58,11 +58,11 @@ extern int __bss_end; *******************************************************************************/ void __error__(char* file, unsigned long line) { - rt_kprintf("\n\r Wrong parameter value detected on\r\n"); - rt_kprintf(" file %s\r\n", file); - rt_kprintf(" line %d\r\n", line); + rt_kprintf("\n\r Wrong parameter value detected on\r\n"); + rt_kprintf(" file %s\r\n", file); + rt_kprintf(" line %d\r\n", line); - while (1) ; + while (1) ; } #endif @@ -71,83 +71,83 @@ void __error__(char* file, unsigned long line) */ void rtthread_startup(void) { - /* init board */ - rt_hw_board_init(); + /* init board */ + rt_hw_board_init(); - /* show version */ - rt_show_version(); + /* show version */ + rt_show_version(); - /* init tick */ - rt_system_tick_init(); + /* init tick */ + rt_system_tick_init(); - /* init kernel object */ - rt_system_object_init(); + /* init kernel object */ + rt_system_object_init(); - /* init timer system */ - rt_system_timer_init(); + /* init timer system */ + rt_system_timer_init(); #ifdef RT_USING_HEAP #if LM3S_EXT_SRAM == 1 - /* init sdram */ - rt_system_heap_init((void*)LM3S_EXT_SRAM_BEGIN, (void*)LM3S_EXT_SRAM_END); + /* init sdram */ + rt_system_heap_init((void*)LM3S_EXT_SRAM_BEGIN, (void*)LM3S_EXT_SRAM_END); #else #ifdef __CC_ARM - rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)LM3S_SRAM_END); + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)LM3S_SRAM_END); #elif __ICCARM__ - rt_system_heap_init(__segment_end("HEAP"), (void*)LM3S_SRAM_END); + rt_system_heap_init(__segment_end("HEAP"), (void*)LM3S_SRAM_END); #else - /* init memory system */ - rt_system_heap_init((void*)&__bss_end, (void*)LM3S_SRAM_END); + /* init memory system */ + rt_system_heap_init((void*)&__bss_end, (void*)LM3S_SRAM_END); #endif #endif #endif - /* init scheduler system */ - rt_system_scheduler_init(); + /* init scheduler system */ + rt_system_scheduler_init(); #ifdef RT_USING_LWIP - eth_system_device_init(); + eth_system_device_init(); - /* register ethernetif device */ - rt_hw_luminaryif_init(); + /* register ethernetif device */ + rt_hw_luminaryif_init(); #endif - /* init hardware serial device */ - rt_hw_serial_init(); + /* init hardware serial device */ + rt_hw_serial_init(); #ifdef RT_USING_DFS - /* init sd card device */ - rt_hw_sdcard_init(); + /* init sd card device */ + rt_hw_sdcard_init(); #endif - /* init application */ - rt_application_init(); + /* init application */ + rt_application_init(); #ifdef RT_USING_FINSH - /* init finsh */ - finsh_system_init(); + /* init finsh */ + finsh_system_init(); #ifdef RT_USING_DEVICE - finsh_set_device("uart1"); + finsh_set_device("uart1"); #endif #endif - /* init idle thread */ - rt_thread_idle_init(); + /* init idle thread */ + rt_thread_idle_init(); - /* start scheduler */ - rt_system_scheduler_start(); + /* start scheduler */ + rt_system_scheduler_start(); - /* never reach here */ - return ; + /* never reach here */ + return ; } int main(void) { - /* disable interrupt first */ + /* disable interrupt first */ rt_hw_interrupt_disable(); - rtthread_startup(); + rtthread_startup(); - return 0; + return 0; } /*@}*/ diff --git a/bsp/lm3s9b9x/drivers/board.c b/bsp/lm3s9b9x/drivers/board.c index 58e820512e..fc79ef4d08 100644 --- a/bsp/lm3s9b9x/drivers/board.c +++ b/bsp/lm3s9b9x/drivers/board.c @@ -41,14 +41,14 @@ extern void rt_hw_interrupt_thread_switch(void); */ void rt_hw_timer_handler(void) { - /* enter interrupt */ - rt_interrupt_enter(); + /* enter interrupt */ + rt_interrupt_enter(); - rt_tick_increase(); + rt_tick_increase(); - /* leave interrupt */ - rt_interrupt_leave(); - rt_hw_interrupt_thread_switch(); + /* leave interrupt */ + rt_interrupt_leave(); + rt_hw_interrupt_thread_switch(); } /** @@ -76,52 +76,52 @@ void rt_hw_eth_handler(void) */ void rt_hw_board_init() { - // set sysclock to 80M + // set sysclock to 80M SysCtlClockSet(SYSCTL_SYSDIV_2_5 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_16MHZ); - /* init systick */ - SysTickDisable(); - SysTickPeriodSet(SysCtlClockGet()/RT_TICK_PER_SECOND); - SysTickIntEnable(); - SysTickEnable(); + /* init systick */ + SysTickDisable(); + SysTickPeriodSet(SysCtlClockGet()/RT_TICK_PER_SECOND); + SysTickIntEnable(); + SysTickEnable(); - /* enable ssio */ - //SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); + /* enable ssio */ + //SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); #if LM3S_EXT_SRAM == 1 - /* init SDRAM */ - rt_hw_sdram_init(); + /* init SDRAM */ + rt_hw_sdram_init(); #endif - /* init console */ - rt_hw_console_init(); + /* init console */ + rt_hw_console_init(); - /* enable interrupt */ - IntMasterEnable(); + /* enable interrupt */ + IntMasterEnable(); } /* init console to support rt_kprintf */ static void rt_hw_console_init() { - /* Enable the UART0 peripherals */ - SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + /* Enable the UART0 peripherals */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); - /* Set GPIO A0 and A1 as UART pins. */ - GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); + /* Set GPIO A0 and A1 as UART pins. */ + GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); - /* Configure the UART for 115,200, 8-N-1 operation. */ - UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), 115200, - (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | - UART_CONFIG_PAR_NONE)); + /* Configure the UART for 115,200, 8-N-1 operation. */ + UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), 115200, + (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | + UART_CONFIG_PAR_NONE)); } /* write one character to serial, must not trigger interrupt */ static void rt_hw_console_putc(const char c) { - if (c == '\n') - while(UARTCharPutNonBlocking(UART0_BASE, '\r') == false); + if (c == '\n') + while(UARTCharPutNonBlocking(UART0_BASE, '\r') == false); - while(UARTCharPutNonBlocking(UART0_BASE, c) == false); + while(UARTCharPutNonBlocking(UART0_BASE, c) == false); } /** @@ -131,10 +131,10 @@ static void rt_hw_console_putc(const char c) */ void rt_hw_console_output(const char* str) { - while (*str) - { - rt_hw_console_putc (*str++); - } + while (*str) + { + rt_hw_console_putc (*str++); + } } /*@}*/ diff --git a/bsp/lm3s9b9x/drivers/board.h b/bsp/lm3s9b9x/drivers/board.h index 2270dc8313..cbce994f69 100644 --- a/bsp/lm3s9b9x/drivers/board.h +++ b/bsp/lm3s9b9x/drivers/board.h @@ -19,23 +19,23 @@ /* whether use board external SRAM memory */ // Use external SRAM memory on the board -// Enable External SRAM memory +// Enable External SRAM memory #define LM3S_EXT_SRAM 1 -// Begin Address of External SRAM -// Default: 0x60000000 +// Begin Address of External SRAM +// Default: 0x60000000 #define LM3S_EXT_SRAM_BEGIN 0x60000000 /* the begining address of external SRAM */ -// End Address of External SRAM -// Default: 0x60000000 +// End Address of External SRAM +// Default: 0x60000000 #define LM3S_EXT_SRAM_END 0x607FFFFF /* the end address of external SRAM */ // // Internal SRAM memory size[Kbytes] <8-64> -// Default: 64 +// Default: 64 #define LM3S_SRAM_SIZE 96 #define LM3S_SRAM_END (0x20000000 + LM3S_SRAM_SIZE * 1024) // For lm3s9b9x, it should be SYSCTL_XTAL_16MHZ -#define LM3S_XTAL_TYPE SYSCTL_XTAL_168MHZ +#define LM3S_XTAL_TYPE SYSCTL_XTAL_168MHZ void rt_hw_board_led_on(int n); void rt_hw_board_led_off(int n); diff --git a/bsp/lm3s9b9x/drivers/serial.c b/bsp/lm3s9b9x/drivers/serial.c index 0df347cf4b..b283600ecf 100644 --- a/bsp/lm3s9b9x/drivers/serial.c +++ b/bsp/lm3s9b9x/drivers/serial.c @@ -29,15 +29,15 @@ extern void rt_hw_interrupt_thread_switch(void); /* LM3S serial device */ struct rt_lm3s_serial { - /* inherit from device */ - struct rt_device parent; + /* inherit from device */ + struct rt_device parent; - rt_uint32_t hw_base; - rt_uint32_t baudrate; + rt_uint32_t hw_base; + rt_uint32_t baudrate; - /* reception field */ - rt_uint16_t save_index, read_index; - rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; + /* reception field */ + rt_uint16_t save_index, read_index; + rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; }; #ifdef RT_USING_UART1 @@ -63,72 +63,72 @@ void rt_hw_uart_isr(struct rt_lm3s_serial* serial) if (device->flag & RT_DEVICE_FLAG_INT_RX) { char ch; - rt_base_t level; + rt_base_t level; while (UARTCharsAvail(serial->hw_base)) { ch = UARTCharGetNonBlocking(serial->hw_base); /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - /* read character */ - serial->rx_buffer[serial->save_index] = ch; - serial->save_index ++; - if (serial->save_index >= RT_UART_RX_BUFFER_SIZE) - serial->save_index = 0; - - /* if the next position is read index, discard this 'read char' */ - if (serial->save_index == serial->read_index) - { - serial->read_index ++; - if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) - serial->read_index = 0; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); + level = rt_hw_interrupt_disable(); + + /* read character */ + serial->rx_buffer[serial->save_index] = ch; + serial->save_index ++; + if (serial->save_index >= RT_UART_RX_BUFFER_SIZE) + serial->save_index = 0; + + /* if the next position is read index, discard this 'read char' */ + if (serial->save_index == serial->read_index) + { + serial->read_index ++; + if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) + serial->read_index = 0; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); } - /* invoke callback */ - if(device->rx_indicate != RT_NULL) - { - rt_int32_t length; + /* invoke callback */ + if(device->rx_indicate != RT_NULL) + { + rt_int32_t length; - length = serial->save_index - serial->read_index; - if (length < 0) length += RT_UART_RX_BUFFER_SIZE; + length = serial->save_index - serial->read_index; + if (length < 0) length += RT_UART_RX_BUFFER_SIZE; device->rx_indicate(device, length); - } + } } } #ifdef RT_USING_UART1 void rt_hw_uart_isr_1(int irqno) { - /* enter interrupt */ - rt_interrupt_enter(); + /* enter interrupt */ + rt_interrupt_enter(); - /* get serial device */ - rt_hw_uart_isr(&serial1); + /* get serial device */ + rt_hw_uart_isr(&serial1); - /* leave interrupt */ - rt_interrupt_leave(); - rt_hw_interrupt_thread_switch(); + /* leave interrupt */ + rt_interrupt_leave(); + rt_hw_interrupt_thread_switch(); } #endif #ifdef RT_USING_UART2 void rt_hw_uart_isr_2(int irqno) { - /* enter interrupt */ - rt_interrupt_enter(); + /* enter interrupt */ + rt_interrupt_enter(); - /* get serial device */ - rt_hw_uart_isr(&serial2); + /* get serial device */ + rt_hw_uart_isr(&serial2); - /* leave interrupt */ - rt_interrupt_leave(); - rt_hw_interrupt_thread_switch(); + /* leave interrupt */ + rt_interrupt_leave(); + rt_hw_interrupt_thread_switch(); } #endif @@ -139,15 +139,15 @@ void rt_hw_uart_isr_2(int irqno) static rt_err_t rt_serial_init (rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) { - struct rt_lm3s_serial* serial; - serial = (struct rt_lm3s_serial*) dev; + struct rt_lm3s_serial* serial; + serial = (struct rt_lm3s_serial*) dev; - RT_ASSERT(serial != RT_NULL); + RT_ASSERT(serial != RT_NULL); if (dev->flag & RT_DEVICE_FLAG_INT_RX) { @@ -160,198 +160,198 @@ static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) UARTIntEnable(serial->hw_base, UART_INT_RX | UART_INT_RT); } - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_close(rt_device_t dev) { - struct rt_lm3s_serial* serial; - serial = (struct rt_lm3s_serial*) dev; + struct rt_lm3s_serial* serial; + serial = (struct rt_lm3s_serial*) dev; - RT_ASSERT(serial != RT_NULL); + RT_ASSERT(serial != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* disable UART rx interrupt */ - UARTIntDisable(serial->hw_base, UART_INT_RX | UART_INT_RT); - } + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* disable UART rx interrupt */ + UARTIntDisable(serial->hw_base, UART_INT_RX | UART_INT_RT); + } - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_control(rt_device_t dev, int cmd, void *args) { - return RT_EOK; + return RT_EOK; } static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - struct rt_lm3s_serial *serial = (struct rt_lm3s_serial*)dev; - RT_ASSERT(serial != RT_NULL); - - /* point to buffer */ - ptr = (rt_uint8_t*) buffer; - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - while (size) - { - /* interrupt receive */ - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - if (serial->read_index != serial->save_index) - { - *ptr = serial->rx_buffer[serial->read_index]; - - serial->read_index ++; - if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) - serial->read_index = 0; - } - else - { - /* no data in rx buffer */ - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - break; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - - ptr ++; size --; - } - - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; - } - else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) - { - /* not support right now */ - RT_ASSERT(0); - } - - /* polling mode */ - while (size) - { - *ptr = UARTCharGetNonBlocking(serial->hw_base); - - ptr ++; size --; - } - - return (rt_size_t)ptr - (rt_size_t)buffer; + rt_uint8_t* ptr; + struct rt_lm3s_serial *serial = (struct rt_lm3s_serial*)dev; + RT_ASSERT(serial != RT_NULL); + + /* point to buffer */ + ptr = (rt_uint8_t*) buffer; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + while (size) + { + /* interrupt receive */ + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + if (serial->read_index != serial->save_index) + { + *ptr = serial->rx_buffer[serial->read_index]; + + serial->read_index ++; + if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) + serial->read_index = 0; + } + else + { + /* no data in rx buffer */ + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + ptr ++; size --; + } + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) + { + /* not support right now */ + RT_ASSERT(0); + } + + /* polling mode */ + while (size) + { + *ptr = UARTCharGetNonBlocking(serial->hw_base); + + ptr ++; size --; + } + + return (rt_size_t)ptr - (rt_size_t)buffer; } static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - struct rt_lm3s_serial* serial; - char *ptr; - - serial = (struct rt_lm3s_serial*) dev; - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - /* not support */ - RT_ASSERT(0); - } - else if (dev->flag & RT_DEVICE_FLAG_DMA_TX) - { - /* not support */ - RT_ASSERT(0); - } - - /* polling write */ - ptr = (char *)buffer; - - if (dev->flag & RT_DEVICE_FLAG_STREAM) - { - /* stream mode */ - while (size) - { - if (*ptr == '\n') - while (UARTCharPutNonBlocking(serial->hw_base, '\r') == false); - - while (UARTCharPutNonBlocking(serial->hw_base, *ptr) == false); - - ptr ++; - size --; - } - } - else - { - while (size) - { - while (UARTCharPutNonBlocking(serial->hw_base, *ptr) == false); - - ptr ++; - size --; - } - } - - return (rt_size_t) ptr - (rt_size_t) buffer; + struct rt_lm3s_serial* serial; + char *ptr; + + serial = (struct rt_lm3s_serial*) dev; + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* not support */ + RT_ASSERT(0); + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_TX) + { + /* not support */ + RT_ASSERT(0); + } + + /* polling write */ + ptr = (char *)buffer; + + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* stream mode */ + while (size) + { + if (*ptr == '\n') + while (UARTCharPutNonBlocking(serial->hw_base, '\r') == false); + + while (UARTCharPutNonBlocking(serial->hw_base, *ptr) == false); + + ptr ++; + size --; + } + } + else + { + while (size) + { + while (UARTCharPutNonBlocking(serial->hw_base, *ptr) == false); + + ptr ++; + size --; + } + } + + return (rt_size_t) ptr - (rt_size_t) buffer; } void rt_hw_serial_init(void) { - struct rt_lm3s_serial* serial; + struct rt_lm3s_serial* serial; #ifdef RT_USING_UART1 - serial = &serial1; + serial = &serial1; - serial->parent.type = RT_Device_Class_Char; + serial->parent.type = RT_Device_Class_Char; - serial->hw_base = UART0_BASE; - serial->baudrate = 115200; + serial->hw_base = UART0_BASE; + serial->baudrate = 115200; - rt_memset(serial->rx_buffer, 0, sizeof(serial->rx_buffer)); - serial->read_index = serial->save_index = 0; + rt_memset(serial->rx_buffer, 0, sizeof(serial->rx_buffer)); + serial->read_index = serial->save_index = 0; - /* enable UART0 clock */ + /* enable UART0 clock */ SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); - /* set UART0 pinmux */ + /* set UART0 pinmux */ GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); - /* Configure the UART for 115,200, 8-N-1 operation. */ - UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), serial->baudrate, + /* Configure the UART for 115,200, 8-N-1 operation. */ + UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), serial->baudrate, (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE)); - serial->parent.init = rt_serial_init; - serial->parent.open = rt_serial_open; - serial->parent.close = rt_serial_close; - serial->parent.read = rt_serial_read; - serial->parent.write = rt_serial_write; - serial->parent.control = rt_serial_control; - serial->parent.user_data = RT_NULL; + serial->parent.init = rt_serial_init; + serial->parent.open = rt_serial_open; + serial->parent.close = rt_serial_close; + serial->parent.read = rt_serial_read; + serial->parent.write = rt_serial_write; + serial->parent.control = rt_serial_control; + serial->parent.user_data = RT_NULL; - rt_device_register(&serial->parent, - "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); + rt_device_register(&serial->parent, + "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); #endif #ifdef RT_USING_UART2 - serial = &serial2; + serial = &serial2; - serial->parent.type = RT_Device_Class_Char; + serial->parent.type = RT_Device_Class_Char; - serial->hw_base = 0xE0010000; - serial->baudrate = 115200; + serial->hw_base = 0xE0010000; + serial->baudrate = 115200; - rt_memset(serial->rx_buffer, 0, sizeof(serial->rx_buffer)); - serial->read_index = serial->save_index = 0; + rt_memset(serial->rx_buffer, 0, sizeof(serial->rx_buffer)); + serial->read_index = serial->save_index = 0; - serial->parent.init = rt_serial_init; - serial->parent.open = rt_serial_open; - serial->parent.close = rt_serial_close; - serial->parent.read = rt_serial_read; - serial->parent.write = rt_serial_write; - serial->parent.control = rt_serial_control; - serial->parent.user_data = RT_NULL; + serial->parent.init = rt_serial_init; + serial->parent.open = rt_serial_open; + serial->parent.close = rt_serial_close; + serial->parent.read = rt_serial_read; + serial->parent.write = rt_serial_write; + serial->parent.control = rt_serial_control; + serial->parent.user_data = RT_NULL; - rt_device_register(&serial->parent, - "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); + rt_device_register(&serial->parent, + "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); #endif } diff --git a/bsp/lm3s9b9x/rtconfig.h b/bsp/lm3s9b9x/rtconfig.h index b961c26d6f..623ca8d2a5 100644 --- a/bsp/lm3s9b9x/rtconfig.h +++ b/bsp/lm3s9b9x/rtconfig.h @@ -3,16 +3,16 @@ #define __RTTHREAD_CFG_H__ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX*/ -#define RT_THREAD_PRIORITY_MAX 32 +#define RT_THREAD_PRIORITY_MAX 32 /* Tick per Second*/ -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 /* SECTION: RT_DEBUG */ /* Thread Debug*/ @@ -65,7 +65,7 @@ /* SECTION: Console options */ #define RT_USING_CONSOLE /* the buffer size of console*/ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 /* SECTION: FinSH shell options */ /* Using FinSH as Shell*/ @@ -80,11 +80,11 @@ #define RT_DFS_ELM_WORD_ACCESS /* the max number of mounted filesystem */ -#define DFS_FILESYSTEMS_MAX 1 -/* the max number of opened files */ -#define DFS_FD_MAX 4 -/* the max number of cached sector */ -#define DFS_CACHE_MAX_NUM 4 +#define DFS_FILESYSTEMS_MAX 1 +/* the max number of opened files */ +#define DFS_FD_MAX 4 +/* the max number of cached sector */ +#define DFS_CACHE_MAX_NUM 4 /* SECTION: lwip, a lighwight TCP/IP protocol stack */ /* Using lighweight TCP/IP protocol stack*/ @@ -106,7 +106,7 @@ #define RT_LWIP_TCP /* the number of simulatenously active TCP connections*/ -#define RT_LWIP_TCP_PCB_NUM 5 +#define RT_LWIP_TCP_PCB_NUM 5 /* Ethernet padding size */ #define RT_LWIP_ETH_PAD_SIZE 2 @@ -129,21 +129,21 @@ #define RT_LWIP_MSKADDR "255.255.255.0" /* tcp thread options */ -#define RT_LWIP_TCPTHREAD_PRIORITY 12 -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4 -#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4 +#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 /* ethernet if thread options */ -#define RT_LWIP_ETHTHREAD_PRIORITY 15 -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4 -#define RT_LWIP_ETHTHREAD_STACKSIZE 512 +#define RT_LWIP_ETHTHREAD_PRIORITY 15 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4 +#define RT_LWIP_ETHTHREAD_STACKSIZE 512 /* TCP sender buffer space */ -#define RT_LWIP_TCP_SND_BUF 8192 +#define RT_LWIP_TCP_SND_BUF 8192 /* TCP receive window. */ -#define RT_LWIP_TCP_WND 8192 +#define RT_LWIP_TCP_WND 8192 /* the size of each pbuf in the pbuf pool. */ -#define RT_LWIP_PBUF_POOL_BUFSIZE 1500 +#define RT_LWIP_PBUF_POOL_BUFSIZE 1500 #endif diff --git a/bsp/lm4f232/applications/application.c b/bsp/lm4f232/applications/application.c index c80c3047aa..bd383aefe6 100644 --- a/bsp/lm4f232/applications/application.c +++ b/bsp/lm4f232/applications/application.c @@ -35,45 +35,45 @@ void rt_init_thread_entry(void *parameter) { /* Filesystem Initialization */ #ifdef RT_USING_DFS - { - /* init the device filesystem */ - dfs_init(); + { + /* init the device filesystem */ + dfs_init(); #ifdef RT_USING_DFS_ELMFAT - /* init the elm chan FatFs filesystam*/ - elm_init(); + /* init the elm chan FatFs filesystam*/ + elm_init(); - /* mount sd card fat partition 1 as root directory */ - if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) - { - rt_kprintf("File System initialized!\n"); - } - else - rt_kprintf("File System initialzation failed!\n"); + /* mount sd card fat partition 1 as root directory */ + if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) + { + rt_kprintf("File System initialized!\n"); + } + else + rt_kprintf("File System initialzation failed!\n"); #endif - } + } #endif /* LwIP Initialization */ #ifdef RT_USING_LWIP - { - extern void lwip_sys_init(void); - - /* init lwip system */ - lwip_sys_init(); - rt_kprintf("TCP/IP initialized!\n"); - } + { + extern void lwip_sys_init(void); + + /* init lwip system */ + lwip_sys_init(); + rt_kprintf("TCP/IP initialized!\n"); + } #endif } int rt_application_init() { - rt_thread_t init_thread; + rt_thread_t init_thread; - init_thread = rt_thread_create("init", - rt_init_thread_entry, RT_NULL, - 1024, 21, 20); - rt_thread_startup(init_thread); + init_thread = rt_thread_create("init", + rt_init_thread_entry, RT_NULL, + 1024, 21, 20); + rt_thread_startup(init_thread); - return 0; + return 0; } /*@}*/ diff --git a/bsp/lm4f232/applications/startup.c b/bsp/lm4f232/applications/startup.c index e1f3b6efd1..e437c0adeb 100644 --- a/bsp/lm4f232/applications/startup.c +++ b/bsp/lm4f232/applications/startup.c @@ -58,11 +58,11 @@ extern int __bss_end; *******************************************************************************/ void __error__(char* file, unsigned long line) { - rt_kprintf("\n\r Wrong parameter value detected on\r\n"); - rt_kprintf(" file %s\r\n", file); - rt_kprintf(" line %d\r\n", line); + rt_kprintf("\n\r Wrong parameter value detected on\r\n"); + rt_kprintf(" file %s\r\n", file); + rt_kprintf(" line %d\r\n", line); - while (1) ; + while (1) ; } #endif @@ -71,83 +71,83 @@ void __error__(char* file, unsigned long line) */ void rtthread_startup(void) { - /* init board */ - rt_hw_board_init(); + /* init board */ + rt_hw_board_init(); - /* show version */ - rt_show_version(); + /* show version */ + rt_show_version(); - /* init tick */ - rt_system_tick_init(); + /* init tick */ + rt_system_tick_init(); - /* init kernel object */ - rt_system_object_init(); + /* init kernel object */ + rt_system_object_init(); - /* init timer system */ - rt_system_timer_init(); + /* init timer system */ + rt_system_timer_init(); #ifdef RT_USING_HEAP #if LM3S_EXT_SRAM == 1 - /* init sdram */ - rt_system_heap_init((void*)LM3S_EXT_SRAM_BEGIN, (void*)LM3S_EXT_SRAM_END); + /* init sdram */ + rt_system_heap_init((void*)LM3S_EXT_SRAM_BEGIN, (void*)LM3S_EXT_SRAM_END); #else #ifdef __CC_ARM - rt_system_heap_init((void*)&Image$$ER_ZI$$ZI$$Limit, (void*)LM3S_SRAM_END); + rt_system_heap_init((void*)&Image$$ER_ZI$$ZI$$Limit, (void*)LM3S_SRAM_END); #elif __ICCARM__ - rt_system_heap_init(__segment_end("HEAP"), (void*)LM3S_SRAM_END); + rt_system_heap_init(__segment_end("HEAP"), (void*)LM3S_SRAM_END); #else - /* init memory system */ - rt_system_heap_init((void*)&__bss_end, (void*)LM3S_SRAM_END); + /* init memory system */ + rt_system_heap_init((void*)&__bss_end, (void*)LM3S_SRAM_END); #endif #endif #endif - /* init scheduler system */ - rt_system_scheduler_init(); + /* init scheduler system */ + rt_system_scheduler_init(); #ifdef RT_USING_LWIP - eth_system_device_init(); + eth_system_device_init(); - /* register ethernetif device */ - rt_hw_luminaryif_init(); + /* register ethernetif device */ + rt_hw_luminaryif_init(); #endif - /* init hardware serial device */ - rt_hw_serial_init(); + /* init hardware serial device */ + rt_hw_serial_init(); #ifdef RT_USING_DFS - /* init sd card device */ - rt_hw_sdcard_init(); + /* init sd card device */ + rt_hw_sdcard_init(); #endif - /* init application */ - rt_application_init(); + /* init application */ + rt_application_init(); #ifdef RT_USING_FINSH - /* init finsh */ - finsh_system_init(); + /* init finsh */ + finsh_system_init(); #ifdef RT_USING_DEVICE - finsh_set_device("uart1"); + finsh_set_device("uart1"); #endif #endif - /* init idle thread */ - rt_thread_idle_init(); + /* init idle thread */ + rt_thread_idle_init(); - /* start scheduler */ - rt_system_scheduler_start(); + /* start scheduler */ + rt_system_scheduler_start(); - /* never reach here */ - return ; + /* never reach here */ + return ; } int main(void) { - /* disable interrupt first */ + /* disable interrupt first */ rt_hw_interrupt_disable(); - rtthread_startup(); + rtthread_startup(); - return 0; + return 0; } /*@}*/ diff --git a/bsp/lm4f232/drivers/board.c b/bsp/lm4f232/drivers/board.c index 1e4b53f110..84f74aebfe 100644 --- a/bsp/lm4f232/drivers/board.c +++ b/bsp/lm4f232/drivers/board.c @@ -41,14 +41,14 @@ extern void rt_hw_interrupt_thread_switch(void); */ void rt_hw_timer_handler(void) { - /* enter interrupt */ - rt_interrupt_enter(); + /* enter interrupt */ + rt_interrupt_enter(); - rt_tick_increase(); + rt_tick_increase(); - /* leave interrupt */ - rt_interrupt_leave(); - rt_hw_interrupt_thread_switch(); + /* leave interrupt */ + rt_interrupt_leave(); + rt_hw_interrupt_thread_switch(); } /** @@ -76,60 +76,60 @@ void rt_hw_eth_handler(void) */ void rt_hw_board_init() { - + // // Enable lazy stacking for interrupt handlers. This allows floating-point // instructions to be used within interrupt handlers, but at the expense of // extra stack usage. // FPULazyStackingEnable(); - - // set sysclock to 80M + + // set sysclock to 80M SysCtlClockSet(SYSCTL_SYSDIV_2_5 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_16MHZ); - /* init systick */ - SysTickDisable(); - SysTickPeriodSet(SysCtlClockGet()/RT_TICK_PER_SECOND); - SysTickIntEnable(); - SysTickEnable(); + /* init systick */ + SysTickDisable(); + SysTickPeriodSet(SysCtlClockGet()/RT_TICK_PER_SECOND); + SysTickIntEnable(); + SysTickEnable(); - /* enable ssio */ - //SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); + /* enable ssio */ + //SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); #if LM3S_EXT_SRAM == 1 - /* init SDRAM */ - rt_hw_sdram_init(); + /* init SDRAM */ + rt_hw_sdram_init(); #endif - /* init console */ - rt_hw_console_init(); + /* init console */ + rt_hw_console_init(); - /* enable interrupt */ - IntMasterEnable(); + /* enable interrupt */ + IntMasterEnable(); } /* init console to support rt_kprintf */ static void rt_hw_console_init() { - /* Enable the UART0 peripherals */ - SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + /* Enable the UART0 peripherals */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); - /* Set GPIO A0 and A1 as UART pins. */ - GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); + /* Set GPIO A0 and A1 as UART pins. */ + GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); - /* Configure the UART for 115,200, 8-N-1 operation. */ - UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), 115200, - (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | - UART_CONFIG_PAR_NONE)); + /* Configure the UART for 115,200, 8-N-1 operation. */ + UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), 115200, + (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | + UART_CONFIG_PAR_NONE)); } /* write one character to serial, must not trigger interrupt */ static void rt_hw_console_putc(const char c) { - if (c == '\n') - while(UARTCharPutNonBlocking(UART0_BASE, '\r') == false); + if (c == '\n') + while(UARTCharPutNonBlocking(UART0_BASE, '\r') == false); - while(UARTCharPutNonBlocking(UART0_BASE, c) == false); + while(UARTCharPutNonBlocking(UART0_BASE, c) == false); } /** @@ -139,10 +139,10 @@ static void rt_hw_console_putc(const char c) */ void rt_hw_console_output(const char* str) { - while (*str) - { - rt_hw_console_putc (*str++); - } + while (*str) + { + rt_hw_console_putc (*str++); + } } /*@}*/ diff --git a/bsp/lm4f232/drivers/board.h b/bsp/lm4f232/drivers/board.h index f2e6104e81..9f208170e4 100644 --- a/bsp/lm4f232/drivers/board.h +++ b/bsp/lm4f232/drivers/board.h @@ -19,26 +19,26 @@ /* whether use board external SRAM memory */ // Use external SRAM memory on the board -// Enable External SRAM memory +// Enable External SRAM memory #define LM3S_EXT_SRAM 0 -// Begin Address of External SRAM -// Default: 0x60000000 +// Begin Address of External SRAM +// Default: 0x60000000 #define LM3S_EXT_SRAM_BEGIN 0x60000000 /* the begining address of external SRAM */ -// End Address of External SRAM -// Default: 0x60000000 +// End Address of External SRAM +// Default: 0x60000000 #define LM3S_EXT_SRAM_END 0x607FFFFF /* the end address of external SRAM */ // // Internal SRAM memory size[Kbytes] <8-64> -// Default: 64 +// Default: 64 #define LM3S_SRAM_SIZE 32 #define LM3S_SRAM_END (0x20000000 + LM3S_SRAM_SIZE * 1024) // For lm3s9b9x, it should be SYSCTL_XTAL_16MHZ -#define LM3S_XTAL_TYPE SYSCTL_XTAL_168MHZ +#define LM3S_XTAL_TYPE SYSCTL_XTAL_168MHZ /* RT_USING_UART */ -#define RT_UART_RX_BUFFER_SIZE 64 +#define RT_UART_RX_BUFFER_SIZE 64 #define RT_USING_UART0 #define RT_USING_UART1 //#define RT_USING_UART2 diff --git a/bsp/lm4f232/drivers/serial.c b/bsp/lm4f232/drivers/serial.c index 0df347cf4b..b283600ecf 100644 --- a/bsp/lm4f232/drivers/serial.c +++ b/bsp/lm4f232/drivers/serial.c @@ -29,15 +29,15 @@ extern void rt_hw_interrupt_thread_switch(void); /* LM3S serial device */ struct rt_lm3s_serial { - /* inherit from device */ - struct rt_device parent; + /* inherit from device */ + struct rt_device parent; - rt_uint32_t hw_base; - rt_uint32_t baudrate; + rt_uint32_t hw_base; + rt_uint32_t baudrate; - /* reception field */ - rt_uint16_t save_index, read_index; - rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; + /* reception field */ + rt_uint16_t save_index, read_index; + rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; }; #ifdef RT_USING_UART1 @@ -63,72 +63,72 @@ void rt_hw_uart_isr(struct rt_lm3s_serial* serial) if (device->flag & RT_DEVICE_FLAG_INT_RX) { char ch; - rt_base_t level; + rt_base_t level; while (UARTCharsAvail(serial->hw_base)) { ch = UARTCharGetNonBlocking(serial->hw_base); /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - /* read character */ - serial->rx_buffer[serial->save_index] = ch; - serial->save_index ++; - if (serial->save_index >= RT_UART_RX_BUFFER_SIZE) - serial->save_index = 0; - - /* if the next position is read index, discard this 'read char' */ - if (serial->save_index == serial->read_index) - { - serial->read_index ++; - if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) - serial->read_index = 0; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); + level = rt_hw_interrupt_disable(); + + /* read character */ + serial->rx_buffer[serial->save_index] = ch; + serial->save_index ++; + if (serial->save_index >= RT_UART_RX_BUFFER_SIZE) + serial->save_index = 0; + + /* if the next position is read index, discard this 'read char' */ + if (serial->save_index == serial->read_index) + { + serial->read_index ++; + if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) + serial->read_index = 0; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); } - /* invoke callback */ - if(device->rx_indicate != RT_NULL) - { - rt_int32_t length; + /* invoke callback */ + if(device->rx_indicate != RT_NULL) + { + rt_int32_t length; - length = serial->save_index - serial->read_index; - if (length < 0) length += RT_UART_RX_BUFFER_SIZE; + length = serial->save_index - serial->read_index; + if (length < 0) length += RT_UART_RX_BUFFER_SIZE; device->rx_indicate(device, length); - } + } } } #ifdef RT_USING_UART1 void rt_hw_uart_isr_1(int irqno) { - /* enter interrupt */ - rt_interrupt_enter(); + /* enter interrupt */ + rt_interrupt_enter(); - /* get serial device */ - rt_hw_uart_isr(&serial1); + /* get serial device */ + rt_hw_uart_isr(&serial1); - /* leave interrupt */ - rt_interrupt_leave(); - rt_hw_interrupt_thread_switch(); + /* leave interrupt */ + rt_interrupt_leave(); + rt_hw_interrupt_thread_switch(); } #endif #ifdef RT_USING_UART2 void rt_hw_uart_isr_2(int irqno) { - /* enter interrupt */ - rt_interrupt_enter(); + /* enter interrupt */ + rt_interrupt_enter(); - /* get serial device */ - rt_hw_uart_isr(&serial2); + /* get serial device */ + rt_hw_uart_isr(&serial2); - /* leave interrupt */ - rt_interrupt_leave(); - rt_hw_interrupt_thread_switch(); + /* leave interrupt */ + rt_interrupt_leave(); + rt_hw_interrupt_thread_switch(); } #endif @@ -139,15 +139,15 @@ void rt_hw_uart_isr_2(int irqno) static rt_err_t rt_serial_init (rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) { - struct rt_lm3s_serial* serial; - serial = (struct rt_lm3s_serial*) dev; + struct rt_lm3s_serial* serial; + serial = (struct rt_lm3s_serial*) dev; - RT_ASSERT(serial != RT_NULL); + RT_ASSERT(serial != RT_NULL); if (dev->flag & RT_DEVICE_FLAG_INT_RX) { @@ -160,198 +160,198 @@ static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) UARTIntEnable(serial->hw_base, UART_INT_RX | UART_INT_RT); } - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_close(rt_device_t dev) { - struct rt_lm3s_serial* serial; - serial = (struct rt_lm3s_serial*) dev; + struct rt_lm3s_serial* serial; + serial = (struct rt_lm3s_serial*) dev; - RT_ASSERT(serial != RT_NULL); + RT_ASSERT(serial != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* disable UART rx interrupt */ - UARTIntDisable(serial->hw_base, UART_INT_RX | UART_INT_RT); - } + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* disable UART rx interrupt */ + UARTIntDisable(serial->hw_base, UART_INT_RX | UART_INT_RT); + } - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_control(rt_device_t dev, int cmd, void *args) { - return RT_EOK; + return RT_EOK; } static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - struct rt_lm3s_serial *serial = (struct rt_lm3s_serial*)dev; - RT_ASSERT(serial != RT_NULL); - - /* point to buffer */ - ptr = (rt_uint8_t*) buffer; - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - while (size) - { - /* interrupt receive */ - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - if (serial->read_index != serial->save_index) - { - *ptr = serial->rx_buffer[serial->read_index]; - - serial->read_index ++; - if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) - serial->read_index = 0; - } - else - { - /* no data in rx buffer */ - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - break; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - - ptr ++; size --; - } - - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; - } - else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) - { - /* not support right now */ - RT_ASSERT(0); - } - - /* polling mode */ - while (size) - { - *ptr = UARTCharGetNonBlocking(serial->hw_base); - - ptr ++; size --; - } - - return (rt_size_t)ptr - (rt_size_t)buffer; + rt_uint8_t* ptr; + struct rt_lm3s_serial *serial = (struct rt_lm3s_serial*)dev; + RT_ASSERT(serial != RT_NULL); + + /* point to buffer */ + ptr = (rt_uint8_t*) buffer; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + while (size) + { + /* interrupt receive */ + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + if (serial->read_index != serial->save_index) + { + *ptr = serial->rx_buffer[serial->read_index]; + + serial->read_index ++; + if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) + serial->read_index = 0; + } + else + { + /* no data in rx buffer */ + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + ptr ++; size --; + } + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) + { + /* not support right now */ + RT_ASSERT(0); + } + + /* polling mode */ + while (size) + { + *ptr = UARTCharGetNonBlocking(serial->hw_base); + + ptr ++; size --; + } + + return (rt_size_t)ptr - (rt_size_t)buffer; } static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - struct rt_lm3s_serial* serial; - char *ptr; - - serial = (struct rt_lm3s_serial*) dev; - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - /* not support */ - RT_ASSERT(0); - } - else if (dev->flag & RT_DEVICE_FLAG_DMA_TX) - { - /* not support */ - RT_ASSERT(0); - } - - /* polling write */ - ptr = (char *)buffer; - - if (dev->flag & RT_DEVICE_FLAG_STREAM) - { - /* stream mode */ - while (size) - { - if (*ptr == '\n') - while (UARTCharPutNonBlocking(serial->hw_base, '\r') == false); - - while (UARTCharPutNonBlocking(serial->hw_base, *ptr) == false); - - ptr ++; - size --; - } - } - else - { - while (size) - { - while (UARTCharPutNonBlocking(serial->hw_base, *ptr) == false); - - ptr ++; - size --; - } - } - - return (rt_size_t) ptr - (rt_size_t) buffer; + struct rt_lm3s_serial* serial; + char *ptr; + + serial = (struct rt_lm3s_serial*) dev; + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* not support */ + RT_ASSERT(0); + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_TX) + { + /* not support */ + RT_ASSERT(0); + } + + /* polling write */ + ptr = (char *)buffer; + + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* stream mode */ + while (size) + { + if (*ptr == '\n') + while (UARTCharPutNonBlocking(serial->hw_base, '\r') == false); + + while (UARTCharPutNonBlocking(serial->hw_base, *ptr) == false); + + ptr ++; + size --; + } + } + else + { + while (size) + { + while (UARTCharPutNonBlocking(serial->hw_base, *ptr) == false); + + ptr ++; + size --; + } + } + + return (rt_size_t) ptr - (rt_size_t) buffer; } void rt_hw_serial_init(void) { - struct rt_lm3s_serial* serial; + struct rt_lm3s_serial* serial; #ifdef RT_USING_UART1 - serial = &serial1; + serial = &serial1; - serial->parent.type = RT_Device_Class_Char; + serial->parent.type = RT_Device_Class_Char; - serial->hw_base = UART0_BASE; - serial->baudrate = 115200; + serial->hw_base = UART0_BASE; + serial->baudrate = 115200; - rt_memset(serial->rx_buffer, 0, sizeof(serial->rx_buffer)); - serial->read_index = serial->save_index = 0; + rt_memset(serial->rx_buffer, 0, sizeof(serial->rx_buffer)); + serial->read_index = serial->save_index = 0; - /* enable UART0 clock */ + /* enable UART0 clock */ SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); - /* set UART0 pinmux */ + /* set UART0 pinmux */ GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); - /* Configure the UART for 115,200, 8-N-1 operation. */ - UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), serial->baudrate, + /* Configure the UART for 115,200, 8-N-1 operation. */ + UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), serial->baudrate, (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE)); - serial->parent.init = rt_serial_init; - serial->parent.open = rt_serial_open; - serial->parent.close = rt_serial_close; - serial->parent.read = rt_serial_read; - serial->parent.write = rt_serial_write; - serial->parent.control = rt_serial_control; - serial->parent.user_data = RT_NULL; + serial->parent.init = rt_serial_init; + serial->parent.open = rt_serial_open; + serial->parent.close = rt_serial_close; + serial->parent.read = rt_serial_read; + serial->parent.write = rt_serial_write; + serial->parent.control = rt_serial_control; + serial->parent.user_data = RT_NULL; - rt_device_register(&serial->parent, - "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); + rt_device_register(&serial->parent, + "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); #endif #ifdef RT_USING_UART2 - serial = &serial2; + serial = &serial2; - serial->parent.type = RT_Device_Class_Char; + serial->parent.type = RT_Device_Class_Char; - serial->hw_base = 0xE0010000; - serial->baudrate = 115200; + serial->hw_base = 0xE0010000; + serial->baudrate = 115200; - rt_memset(serial->rx_buffer, 0, sizeof(serial->rx_buffer)); - serial->read_index = serial->save_index = 0; + rt_memset(serial->rx_buffer, 0, sizeof(serial->rx_buffer)); + serial->read_index = serial->save_index = 0; - serial->parent.init = rt_serial_init; - serial->parent.open = rt_serial_open; - serial->parent.close = rt_serial_close; - serial->parent.read = rt_serial_read; - serial->parent.write = rt_serial_write; - serial->parent.control = rt_serial_control; - serial->parent.user_data = RT_NULL; + serial->parent.init = rt_serial_init; + serial->parent.open = rt_serial_open; + serial->parent.close = rt_serial_close; + serial->parent.read = rt_serial_read; + serial->parent.write = rt_serial_write; + serial->parent.control = rt_serial_control; + serial->parent.user_data = RT_NULL; - rt_device_register(&serial->parent, - "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); + rt_device_register(&serial->parent, + "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); #endif } diff --git a/bsp/lm4f232/rtconfig.h b/bsp/lm4f232/rtconfig.h index 52844dc578..b9e846243d 100644 --- a/bsp/lm4f232/rtconfig.h +++ b/bsp/lm4f232/rtconfig.h @@ -3,16 +3,16 @@ #define __RTTHREAD_CFG_H__ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 8 +#define RT_ALIGN_SIZE 8 /* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 32 +#define RT_THREAD_PRIORITY_MAX 32 /* Tick per Second */ -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 /* SECTION: RT_DEBUG */ /* Thread Debug */ @@ -28,9 +28,9 @@ /* Using Software Timer */ /* #define RT_USING_TIMER_SOFT */ -#define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 512 -#define RT_TIMER_TICK_PER_SECOND 10 +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_TICK_PER_SECOND 10 /* SECTION: IPC */ /* Using Semaphore*/ @@ -65,7 +65,7 @@ /* SECTION: Console options */ #define RT_USING_CONSOLE /* the buffer size of console*/ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 /* SECTION: finsh, a C-Express shell */ #define RT_USING_FINSH @@ -80,18 +80,18 @@ /* Reentrancy (thread safe) of the FatFs module. */ #define RT_DFS_ELM_REENTRANT /* Number of volumes (logical drives) to be used. */ -#define RT_DFS_ELM_DRIVES 2 -/* #define RT_DFS_ELM_USE_LFN 1 */ -#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +/* #define RT_DFS_ELM_USE_LFN 1 */ +#define RT_DFS_ELM_MAX_LFN 255 /* Maximum sector size to be handled. */ #define RT_DFS_ELM_MAX_SECTOR_SIZE 512 #define RT_USING_DFS_ROMFS /* the max number of mounted filesystem */ -#define DFS_FILESYSTEMS_MAX 2 -/* the max number of opened files */ -#define DFS_FD_MAX 4 +#define DFS_FILESYSTEMS_MAX 2 +/* the max number of opened files */ +#define DFS_FD_MAX 4 /* SECTION: lwip, a lighwight TCP/IP protocol stack */ /* #define RT_USING_LWIP */ @@ -105,40 +105,40 @@ #define RT_LWIP_DNS /* the number of simulatenously active TCP connections*/ -#define RT_LWIP_TCP_PCB_NUM 5 +#define RT_LWIP_TCP_PCB_NUM 5 /* ip address of target*/ -#define RT_LWIP_IPADDR0 192 -#define RT_LWIP_IPADDR1 168 -#define RT_LWIP_IPADDR2 1 -#define RT_LWIP_IPADDR3 201 +#define RT_LWIP_IPADDR0 192 +#define RT_LWIP_IPADDR1 168 +#define RT_LWIP_IPADDR2 1 +#define RT_LWIP_IPADDR3 201 /* gateway address of target*/ -#define RT_LWIP_GWADDR0 192 -#define RT_LWIP_GWADDR1 168 -#define RT_LWIP_GWADDR2 1 -#define RT_LWIP_GWADDR3 1 +#define RT_LWIP_GWADDR0 192 +#define RT_LWIP_GWADDR1 168 +#define RT_LWIP_GWADDR2 1 +#define RT_LWIP_GWADDR3 1 /* mask address of target*/ -#define RT_LWIP_MSKADDR0 255 -#define RT_LWIP_MSKADDR1 255 -#define RT_LWIP_MSKADDR2 255 -#define RT_LWIP_MSKADDR3 0 +#define RT_LWIP_MSKADDR0 255 +#define RT_LWIP_MSKADDR1 255 +#define RT_LWIP_MSKADDR2 255 +#define RT_LWIP_MSKADDR3 0 /* tcp thread options */ -#define RT_LWIP_TCPTHREAD_PRIORITY 12 -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4 -#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4 +#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 /* ethernet if thread options */ -#define RT_LWIP_ETHTHREAD_PRIORITY 15 -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4 -#define RT_LWIP_ETHTHREAD_STACKSIZE 512 +#define RT_LWIP_ETHTHREAD_PRIORITY 15 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4 +#define RT_LWIP_ETHTHREAD_STACKSIZE 512 /* TCP sender buffer space */ -#define RT_LWIP_TCP_SND_BUF 8192 +#define RT_LWIP_TCP_SND_BUF 8192 /* TCP receive window. */ -#define RT_LWIP_TCP_WND 8192 +#define RT_LWIP_TCP_WND 8192 #define CHECKSUM_CHECK_TCP 0 #define CHECKSUM_CHECK_IP 0 diff --git a/bsp/lpc176x/applications/application.c b/bsp/lpc176x/applications/application.c index 9facb30aa8..173e2df1bb 100644 --- a/bsp/lpc176x/applications/application.c +++ b/bsp/lpc176x/applications/application.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -38,44 +38,44 @@ extern int lwip_system_init(void); /* thread phase init */ void rt_init_thread_entry(void *parameter) { - /* initialize platform */ - platform_init(); + /* initialize platform */ + platform_init(); #ifdef RT_USING_LWIP /* register Ethernet interface device */ lpc17xx_emac_hw_init(); /* initialize lwip stack */ - /* register ethernetif device */ - eth_system_device_init(); + /* register ethernetif device */ + eth_system_device_init(); - /* initialize lwip system */ - lwip_system_init(); - rt_kprintf("TCP/IP initialized!\n"); + /* initialize lwip system */ + lwip_system_init(); + rt_kprintf("TCP/IP initialized!\n"); #endif /* Filesystem Initialization */ #ifdef RT_USING_DFS rt_hw_sdcard_init(); - /* initialize the device file system */ - dfs_init(); + /* initialize the device file system */ + dfs_init(); #ifdef RT_USING_DFS_ELMFAT - /* initialize the elm chan FatFS file system*/ - elm_init(); + /* initialize the elm chan FatFS file system*/ + elm_init(); #endif /* mount sd card fat partition 1 as root directory */ if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) - rt_kprintf("File System initialized!\n"); + rt_kprintf("File System initialized!\n"); else - rt_kprintf("File System init failed!\n"); + rt_kprintf("File System init failed!\n"); #endif #ifdef RT_USING_FINSH - /* initialize finsh */ - finsh_system_init(); + /* initialize finsh */ + finsh_system_init(); #endif } @@ -84,8 +84,8 @@ int rt_application_init() rt_thread_t tid; tid = rt_thread_create("init", - rt_init_thread_entry, RT_NULL, - 2048, RT_THREAD_PRIORITY_MAX/3, 20); + rt_init_thread_entry, RT_NULL, + 2048, RT_THREAD_PRIORITY_MAX/3, 20); if (tid != RT_NULL) rt_thread_startup(tid); return 0; diff --git a/bsp/lpc176x/applications/platform.c b/bsp/lpc176x/applications/platform.c index 4bab858aa4..05ff436e8d 100644 --- a/bsp/lpc176x/applications/platform.c +++ b/bsp/lpc176x/applications/platform.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,11 +16,11 @@ static struct rt_memheap _memheap; void platform_init(void) { #ifdef RT_USING_MEMHEAP - /* create memory heap object on 0x2007 C000 - 0x2008 4000*/ + /* create memory heap object on 0x2007 C000 - 0x2008 4000*/ #ifdef RT_USING_LWIP - rt_memheap_init(&_memheap, "system", (void*)0x2007C000, 16*1024); + rt_memheap_init(&_memheap, "system", (void*)0x2007C000, 16*1024); #else - rt_memheap_init(&_memheap, "system", (void*)0x2007C000, 32*1024); + rt_memheap_init(&_memheap, "system", (void*)0x2007C000, 32*1024); #endif #endif } diff --git a/bsp/lpc176x/applications/platform.h b/bsp/lpc176x/applications/platform.h index e52e4066c2..25a97d8666 100644 --- a/bsp/lpc176x/applications/platform.h +++ b/bsp/lpc176x/applications/platform.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc176x/applications/startup.c b/bsp/lpc176x/applications/startup.c index 63d5b0f9a5..b9db54c429 100644 --- a/bsp/lpc176x/applications/startup.c +++ b/bsp/lpc176x/applications/startup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -33,28 +33,28 @@ extern int __bss_end; */ void rtthread_startup(void) { - /* initialize board */ - rt_hw_board_init(); + /* initialize board */ + rt_hw_board_init(); - /* show version */ - rt_show_version(); + /* show version */ + rt_show_version(); #ifdef RT_USING_HEAP - /* initialize memory system */ - #ifdef __CC_ARM - rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x10008000); - #elif __ICCARM__ - rt_system_heap_init(__segment_end("HEAP"), (void*)0x10008000); - #else - rt_system_heap_init((void*)&__bss_end, (void*)0x10008000); - #endif + /* initialize memory system */ + #ifdef __CC_ARM + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x10008000); + #elif __ICCARM__ + rt_system_heap_init(__segment_end("HEAP"), (void*)0x10008000); + #else + rt_system_heap_init((void*)&__bss_end, (void*)0x10008000); + #endif #endif - /* initialize scheduler system */ - rt_system_scheduler_init(); + /* initialize scheduler system */ + rt_system_scheduler_init(); - /* initialize application */ - rt_application_init(); + /* initialize application */ + rt_application_init(); /* initialize timer */ rt_system_timer_init(); @@ -62,25 +62,25 @@ void rtthread_startup(void) /* initialize timer thread */ rt_system_timer_thread_init(); - /* initialize idle thread */ - rt_thread_idle_init(); + /* initialize idle thread */ + rt_thread_idle_init(); - /* start scheduler */ - rt_system_scheduler_start(); + /* start scheduler */ + rt_system_scheduler_start(); - /* never reach here */ - return ; + /* never reach here */ + return ; } int main(void) { - /* disable interrupt first */ - rt_hw_interrupt_disable(); + /* disable interrupt first */ + rt_hw_interrupt_disable(); - /* startup RT-Thread RTOS */ - rtthread_startup(); + /* startup RT-Thread RTOS */ + rtthread_startup(); - return 0; + return 0; } /*@}*/ diff --git a/bsp/lpc176x/drivers/board.c b/bsp/lpc176x/drivers/board.c index c636462a2e..de3e476d55 100644 --- a/bsp/lpc176x/drivers/board.c +++ b/bsp/lpc176x/drivers/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -29,13 +29,13 @@ */ void rt_hw_timer_handler(void) { - /* enter interrupt */ - rt_interrupt_enter(); + /* enter interrupt */ + rt_interrupt_enter(); - rt_tick_increase(); + rt_tick_increase(); - /* leave interrupt */ - rt_interrupt_leave(); + /* leave interrupt */ + rt_interrupt_leave(); } void SysTick_Handler(void) @@ -48,24 +48,24 @@ void SysTick_Handler(void) */ void rt_hw_board_init() { - /* NVIC Configuration */ + /* NVIC Configuration */ #define NVIC_VTOR_MASK 0x3FFFFF80 #ifdef VECT_TAB_RAM - /* Set the Vector Table base location at 0x10000000 */ - SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK); + /* Set the Vector Table base location at 0x10000000 */ + SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK); #else /* VECT_TAB_FLASH */ - /* Set the Vector Table base location at 0x00000000 */ - SCB->VTOR = (0x00000000 & NVIC_VTOR_MASK); + /* Set the Vector Table base location at 0x00000000 */ + SCB->VTOR = (0x00000000 & NVIC_VTOR_MASK); #endif - /* initialize systick */ - SysTick_Config( SystemCoreClock/RT_TICK_PER_SECOND); - /* set pend exception priority */ - NVIC_SetPriority(PendSV_IRQn, (1<<__NVIC_PRIO_BITS) - 1); + /* initialize systick */ + SysTick_Config( SystemCoreClock/RT_TICK_PER_SECOND); + /* set pend exception priority */ + NVIC_SetPriority(PendSV_IRQn, (1<<__NVIC_PRIO_BITS) - 1); #ifdef RT_USING_UART0 - rt_hw_uart_init(); - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + rt_hw_uart_init(); + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); #endif } diff --git a/bsp/lpc176x/drivers/board.h b/bsp/lpc176x/drivers/board.h index 951a2c4cda..1e51e87615 100644 --- a/bsp/lpc176x/drivers/board.h +++ b/bsp/lpc176x/drivers/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc176x/drivers/emac.c b/bsp/lpc176x/drivers/emac.c index 27fc55397a..e4f0363626 100644 --- a/bsp/lpc176x/drivers/emac.c +++ b/bsp/lpc176x/drivers/emac.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -11,20 +11,20 @@ #include "lwipopts.h" #include -#define EMAC_PHY_AUTO 0 -#define EMAC_PHY_10MBIT 1 -#define EMAC_PHY_100MBIT 2 +#define EMAC_PHY_AUTO 0 +#define EMAC_PHY_10MBIT 1 +#define EMAC_PHY_100MBIT 2 #define MAX_ADDR_LEN 6 struct lpc17xx_emac { - /* inherit from ethernet device */ - struct eth_device parent; + /* inherit from ethernet device */ + struct eth_device parent; - rt_uint8_t phy_mode; + rt_uint8_t phy_mode; - /* interface address info. */ - rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ + /* interface address info. */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ }; static struct lpc17xx_emac lpc17xx_emac_device; static struct rt_semaphore sem_lock; @@ -36,40 +36,40 @@ static rt_uint16_t read_PHY (rt_uint8_t PhyReg) ; void ENET_IRQHandler(void) { - rt_uint32_t status; + rt_uint32_t status; /* enter interrupt */ rt_interrupt_enter(); - status = LPC_EMAC->IntStatus; - - if (status & INT_RX_DONE) - { - /* Disable EMAC RxDone interrupts. */ - LPC_EMAC->IntEnable = INT_TX_DONE; - - /* a frame has been received */ - eth_device_ready(&(lpc17xx_emac_device.parent)); - } - else if (status & INT_TX_DONE) - { - /* set event */ - rt_event_send(&tx_event, 0x01); - } - - if (status & INT_RX_OVERRUN) - { - rt_kprintf("rx overrun\n"); - } - - if (status & INT_TX_UNDERRUN) - { - rt_kprintf("tx underrun\n"); - } - - /* Clear the interrupt. */ - LPC_EMAC->IntClear = status; - + status = LPC_EMAC->IntStatus; + + if (status & INT_RX_DONE) + { + /* Disable EMAC RxDone interrupts. */ + LPC_EMAC->IntEnable = INT_TX_DONE; + + /* a frame has been received */ + eth_device_ready(&(lpc17xx_emac_device.parent)); + } + else if (status & INT_TX_DONE) + { + /* set event */ + rt_event_send(&tx_event, 0x01); + } + + if (status & INT_RX_OVERRUN) + { + rt_kprintf("rx overrun\n"); + } + + if (status & INT_TX_UNDERRUN) + { + rt_kprintf("tx underrun\n"); + } + + /* Clear the interrupt. */ + LPC_EMAC->IntClear = status; + /* leave interrupt */ rt_interrupt_leave(); } @@ -77,440 +77,440 @@ void ENET_IRQHandler(void) /* phy write */ static void write_PHY (rt_uint32_t PhyReg, rt_uint32_t Value) { - unsigned int tout; - - LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg; - LPC_EMAC->MWTD = Value; - - /* Wait utill operation completed */ - tout = 0; - for (tout = 0; tout < MII_WR_TOUT; tout++) - { - if ((LPC_EMAC->MIND & MIND_BUSY) == 0) - { - break; - } - } + unsigned int tout; + + LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg; + LPC_EMAC->MWTD = Value; + + /* Wait utill operation completed */ + tout = 0; + for (tout = 0; tout < MII_WR_TOUT; tout++) + { + if ((LPC_EMAC->MIND & MIND_BUSY) == 0) + { + break; + } + } } /* phy read */ static rt_uint16_t read_PHY (rt_uint8_t PhyReg) { - rt_uint32_t tout; - - LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg; - LPC_EMAC->MCMD = MCMD_READ; - - /* Wait until operation completed */ - tout = 0; - for (tout = 0; tout < MII_RD_TOUT; tout++) - { - if ((LPC_EMAC->MIND & MIND_BUSY) == 0) - { - break; - } - } - LPC_EMAC->MCMD = 0; - return (LPC_EMAC->MRDD); + rt_uint32_t tout; + + LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg; + LPC_EMAC->MCMD = MCMD_READ; + + /* Wait until operation completed */ + tout = 0; + for (tout = 0; tout < MII_RD_TOUT; tout++) + { + if ((LPC_EMAC->MIND & MIND_BUSY) == 0) + { + break; + } + } + LPC_EMAC->MCMD = 0; + return (LPC_EMAC->MRDD); } /* init rx descriptor */ rt_inline void rx_descr_init (void) { - rt_uint32_t i; - - for (i = 0; i < NUM_RX_FRAG; i++) - { - RX_DESC_PACKET(i) = RX_BUF(i); - RX_DESC_CTRL(i) = RCTRL_INT | (ETH_FRAG_SIZE-1); - RX_STAT_INFO(i) = 0; - RX_STAT_HASHCRC(i) = 0; - } - - /* Set EMAC Receive Descriptor Registers. */ - LPC_EMAC->RxDescriptor = RX_DESC_BASE; - LPC_EMAC->RxStatus = RX_STAT_BASE; - LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1; - - /* Rx Descriptors Point to 0 */ - LPC_EMAC->RxConsumeIndex = 0; + rt_uint32_t i; + + for (i = 0; i < NUM_RX_FRAG; i++) + { + RX_DESC_PACKET(i) = RX_BUF(i); + RX_DESC_CTRL(i) = RCTRL_INT | (ETH_FRAG_SIZE-1); + RX_STAT_INFO(i) = 0; + RX_STAT_HASHCRC(i) = 0; + } + + /* Set EMAC Receive Descriptor Registers. */ + LPC_EMAC->RxDescriptor = RX_DESC_BASE; + LPC_EMAC->RxStatus = RX_STAT_BASE; + LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1; + + /* Rx Descriptors Point to 0 */ + LPC_EMAC->RxConsumeIndex = 0; } /* init tx descriptor */ rt_inline void tx_descr_init (void) { - rt_uint32_t i; - - for (i = 0; i < NUM_TX_FRAG; i++) - { - TX_DESC_PACKET(i) = TX_BUF(i); - TX_DESC_CTRL(i) = (1ul<<31) | (1ul<<30) | (1ul<<29) | (1ul<<28) | (1ul<<26) | (ETH_FRAG_SIZE-1); - TX_STAT_INFO(i) = 0; - } - - /* Set EMAC Transmit Descriptor Registers. */ - LPC_EMAC->TxDescriptor = TX_DESC_BASE; - LPC_EMAC->TxStatus = TX_STAT_BASE; - LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1; - - /* Tx Descriptors Point to 0 */ - LPC_EMAC->TxProduceIndex = 0; + rt_uint32_t i; + + for (i = 0; i < NUM_TX_FRAG; i++) + { + TX_DESC_PACKET(i) = TX_BUF(i); + TX_DESC_CTRL(i) = (1ul<<31) | (1ul<<30) | (1ul<<29) | (1ul<<28) | (1ul<<26) | (ETH_FRAG_SIZE-1); + TX_STAT_INFO(i) = 0; + } + + /* Set EMAC Transmit Descriptor Registers. */ + LPC_EMAC->TxDescriptor = TX_DESC_BASE; + LPC_EMAC->TxStatus = TX_STAT_BASE; + LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1; + + /* Tx Descriptors Point to 0 */ + LPC_EMAC->TxProduceIndex = 0; } static rt_err_t lpc17xx_emac_init(rt_device_t dev) { - /* Initialize the EMAC ethernet controller. */ - rt_uint32_t regv, tout, id1, id2; - - /* Power Up the EMAC controller. */ - LPC_SC->PCONP |= 0x40000000; - - /* Enable P1 Ethernet Pins. */ - LPC_PINCON->PINSEL2 = 0x50150105; - LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005; - - /* Reset all EMAC internal modules. */ - LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | - MAC1_SIM_RES | MAC1_SOFT_RES; - LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES; - - /* A short delay after reset. */ - for (tout = 100; tout; tout--); - - /* Initialize MAC control registers. */ - LPC_EMAC->MAC1 = MAC1_PASS_ALL; - LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN; - LPC_EMAC->MAXF = ETH_MAX_FLEN; - LPC_EMAC->CLRT = CLRT_DEF; - LPC_EMAC->IPGR = IPGR_DEF; - - /* PCLK=18MHz, clock select=6, MDC=18/6=3MHz */ - /* Enable Reduced MII interface. */ - LPC_EMAC->MCFG = MCFG_CLK_DIV20 | MCFG_RES_MII; - for (tout = 100; tout; tout--); - LPC_EMAC->MCFG = MCFG_CLK_DIV20; - - /* Enable Reduced MII interface. */ - LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM | CR_PASS_RX_FILT; - - /* Reset Reduced MII Logic. */ - LPC_EMAC->SUPP = SUPP_RES_RMII | SUPP_SPEED; - for (tout = 100; tout; tout--); - LPC_EMAC->SUPP = SUPP_SPEED; - - /* Put the PHY in reset mode */ - write_PHY (PHY_REG_BMCR, 0x8000); - for (tout = 1000; tout; tout--); - - /* Wait for hardware reset to end. */ - for (tout = 0; tout < 10000; tout++) - { - regv = read_PHY (PHY_REG_BMCR); - if (!(regv & 0x8000)) - { - /* Reset complete */ - break; - } - } - if (tout >= 10000) - { - //return -RT_ERROR; /* reset failed */ - rt_kprintf("\tPHY Read PHY_REG_BMSR,Reset timeout,tout: %d.\n",tout); - } - - /* Check if this is a DP83848C PHY. */ - id1 = read_PHY (PHY_REG_IDR1); - id2 = read_PHY (PHY_REG_IDR2); - - if (((id1 << 16) | (id2 & 0xFFF0)) != DP83848C_ID) - { - // return -RT_ERROR; - rt_kprintf("\tPHY Read PHY_REG_IDRx,PHY chip isn't DP83848C,Chip ID is %d.\n",((id1 << 16) | (id2 & 0xFFF0))); - } - else - { - /* Configure the PHY device */ - /* Configure the PHY device */ - switch (lpc17xx_emac_device.phy_mode) - { - case EMAC_PHY_AUTO: - /* Use auto negotiation about the link speed. */ - write_PHY (PHY_REG_BMCR, PHY_AUTO_NEG); - /* Wait to complete Auto_Negotiation. */ - for (tout = 0; tout < 200000; tout++) - { - regv = read_PHY (PHY_REG_BMSR); - if (regv & 0x0020) - { - /* Auto negotiation Complete. */ - break; - } - } - if(tout >= 200000) - { - rt_kprintf("\tPHY Read PHY_REG_BMSR,Auto nego timeout,tout: %d.\n",tout); - } - break; - case EMAC_PHY_10MBIT: - /* Connect at 10MBit */ - write_PHY (PHY_REG_BMCR, PHY_FULLD_10M); - break; - case EMAC_PHY_100MBIT: - /* Connect at 100MBit */ - write_PHY (PHY_REG_BMCR, PHY_FULLD_100M); - break; - } - } - //if (tout >= 0x100000) return -RT_ERROR; // auto_neg failed - - /* Check the link status. */ - for (tout = 0; tout < 100; tout++) - { - regv = read_PHY (PHY_REG_STS); - if (regv & 0x0001) - { - /* Link is on. */ - break; - } - } - if (tout >= 100) - { - //return -RT_ERROR; - rt_kprintf("\tPHY Read PHY_REG_BMSR,Link on timeout,tout: %d.\n",tout); - } - /* Configure Full/Half Duplex mode. */ - if (regv & 0x0004) - { - /* Full duplex is enabled. */ - LPC_EMAC->MAC2 |= MAC2_FULL_DUP; - LPC_EMAC->Command |= CR_FULL_DUP; - LPC_EMAC->IPGT = IPGT_FULL_DUP; - } - else - { - /* Half duplex mode. */ - LPC_EMAC->IPGT = IPGT_HALF_DUP; - } - - /* Configure 100MBit/10MBit mode. */ - if (regv & 0x0002) - { - /* 10MBit mode. */ - LPC_EMAC->SUPP = 0; - } - else - { - /* 100MBit mode. */ - LPC_EMAC->SUPP = SUPP_SPEED; - } - - /* Set the Ethernet MAC Address registers */ - LPC_EMAC->SA0 = (lpc17xx_emac_device.dev_addr[1]<<8) | lpc17xx_emac_device.dev_addr[0]; - LPC_EMAC->SA1 = (lpc17xx_emac_device.dev_addr[3]<<8) | lpc17xx_emac_device.dev_addr[2]; - LPC_EMAC->SA2 = (lpc17xx_emac_device.dev_addr[5]<<8) | lpc17xx_emac_device.dev_addr[4]; - - /* Initialize Tx and Rx DMA Descriptors */ - rx_descr_init (); - tx_descr_init (); - - /* Receive Broadcast and Perfect Match Packets */ - LPC_EMAC->RxFilterCtrl = RFC_BCAST_EN | RFC_PERFECT_EN; - - /* Reset all interrupts */ - LPC_EMAC->IntClear = 0xFFFF; - - /* Enable EMAC interrupts. */ - LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; - - /* Enable receive and transmit mode of MAC Ethernet core */ - LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN); - LPC_EMAC->MAC1 |= MAC1_REC_EN; - - /* Enable the ENET Interrupt */ - NVIC_EnableIRQ(ENET_IRQn); - - return RT_EOK; + /* Initialize the EMAC ethernet controller. */ + rt_uint32_t regv, tout, id1, id2; + + /* Power Up the EMAC controller. */ + LPC_SC->PCONP |= 0x40000000; + + /* Enable P1 Ethernet Pins. */ + LPC_PINCON->PINSEL2 = 0x50150105; + LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005; + + /* Reset all EMAC internal modules. */ + LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | + MAC1_SIM_RES | MAC1_SOFT_RES; + LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES; + + /* A short delay after reset. */ + for (tout = 100; tout; tout--); + + /* Initialize MAC control registers. */ + LPC_EMAC->MAC1 = MAC1_PASS_ALL; + LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN; + LPC_EMAC->MAXF = ETH_MAX_FLEN; + LPC_EMAC->CLRT = CLRT_DEF; + LPC_EMAC->IPGR = IPGR_DEF; + + /* PCLK=18MHz, clock select=6, MDC=18/6=3MHz */ + /* Enable Reduced MII interface. */ + LPC_EMAC->MCFG = MCFG_CLK_DIV20 | MCFG_RES_MII; + for (tout = 100; tout; tout--); + LPC_EMAC->MCFG = MCFG_CLK_DIV20; + + /* Enable Reduced MII interface. */ + LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM | CR_PASS_RX_FILT; + + /* Reset Reduced MII Logic. */ + LPC_EMAC->SUPP = SUPP_RES_RMII | SUPP_SPEED; + for (tout = 100; tout; tout--); + LPC_EMAC->SUPP = SUPP_SPEED; + + /* Put the PHY in reset mode */ + write_PHY (PHY_REG_BMCR, 0x8000); + for (tout = 1000; tout; tout--); + + /* Wait for hardware reset to end. */ + for (tout = 0; tout < 10000; tout++) + { + regv = read_PHY (PHY_REG_BMCR); + if (!(regv & 0x8000)) + { + /* Reset complete */ + break; + } + } + if (tout >= 10000) + { + //return -RT_ERROR; /* reset failed */ + rt_kprintf("\tPHY Read PHY_REG_BMSR,Reset timeout,tout: %d.\n",tout); + } + + /* Check if this is a DP83848C PHY. */ + id1 = read_PHY (PHY_REG_IDR1); + id2 = read_PHY (PHY_REG_IDR2); + + if (((id1 << 16) | (id2 & 0xFFF0)) != DP83848C_ID) + { + // return -RT_ERROR; + rt_kprintf("\tPHY Read PHY_REG_IDRx,PHY chip isn't DP83848C,Chip ID is %d.\n",((id1 << 16) | (id2 & 0xFFF0))); + } + else + { + /* Configure the PHY device */ + /* Configure the PHY device */ + switch (lpc17xx_emac_device.phy_mode) + { + case EMAC_PHY_AUTO: + /* Use auto negotiation about the link speed. */ + write_PHY (PHY_REG_BMCR, PHY_AUTO_NEG); + /* Wait to complete Auto_Negotiation. */ + for (tout = 0; tout < 200000; tout++) + { + regv = read_PHY (PHY_REG_BMSR); + if (regv & 0x0020) + { + /* Auto negotiation Complete. */ + break; + } + } + if(tout >= 200000) + { + rt_kprintf("\tPHY Read PHY_REG_BMSR,Auto nego timeout,tout: %d.\n",tout); + } + break; + case EMAC_PHY_10MBIT: + /* Connect at 10MBit */ + write_PHY (PHY_REG_BMCR, PHY_FULLD_10M); + break; + case EMAC_PHY_100MBIT: + /* Connect at 100MBit */ + write_PHY (PHY_REG_BMCR, PHY_FULLD_100M); + break; + } + } + //if (tout >= 0x100000) return -RT_ERROR; // auto_neg failed + + /* Check the link status. */ + for (tout = 0; tout < 100; tout++) + { + regv = read_PHY (PHY_REG_STS); + if (regv & 0x0001) + { + /* Link is on. */ + break; + } + } + if (tout >= 100) + { + //return -RT_ERROR; + rt_kprintf("\tPHY Read PHY_REG_BMSR,Link on timeout,tout: %d.\n",tout); + } + /* Configure Full/Half Duplex mode. */ + if (regv & 0x0004) + { + /* Full duplex is enabled. */ + LPC_EMAC->MAC2 |= MAC2_FULL_DUP; + LPC_EMAC->Command |= CR_FULL_DUP; + LPC_EMAC->IPGT = IPGT_FULL_DUP; + } + else + { + /* Half duplex mode. */ + LPC_EMAC->IPGT = IPGT_HALF_DUP; + } + + /* Configure 100MBit/10MBit mode. */ + if (regv & 0x0002) + { + /* 10MBit mode. */ + LPC_EMAC->SUPP = 0; + } + else + { + /* 100MBit mode. */ + LPC_EMAC->SUPP = SUPP_SPEED; + } + + /* Set the Ethernet MAC Address registers */ + LPC_EMAC->SA0 = (lpc17xx_emac_device.dev_addr[1]<<8) | lpc17xx_emac_device.dev_addr[0]; + LPC_EMAC->SA1 = (lpc17xx_emac_device.dev_addr[3]<<8) | lpc17xx_emac_device.dev_addr[2]; + LPC_EMAC->SA2 = (lpc17xx_emac_device.dev_addr[5]<<8) | lpc17xx_emac_device.dev_addr[4]; + + /* Initialize Tx and Rx DMA Descriptors */ + rx_descr_init (); + tx_descr_init (); + + /* Receive Broadcast and Perfect Match Packets */ + LPC_EMAC->RxFilterCtrl = RFC_BCAST_EN | RFC_PERFECT_EN; + + /* Reset all interrupts */ + LPC_EMAC->IntClear = 0xFFFF; + + /* Enable EMAC interrupts. */ + LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; + + /* Enable receive and transmit mode of MAC Ethernet core */ + LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN); + LPC_EMAC->MAC1 |= MAC1_REC_EN; + + /* Enable the ENET Interrupt */ + NVIC_EnableIRQ(ENET_IRQn); + + return RT_EOK; } static rt_err_t lpc17xx_emac_open(rt_device_t dev, rt_uint16_t oflag) { - return RT_EOK; + return RT_EOK; } static rt_err_t lpc17xx_emac_close(rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_size_t lpc17xx_emac_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_size_t lpc17xx_emac_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_err_t lpc17xx_emac_control(rt_device_t dev, int cmd, void *args) { - switch (cmd) - { - case NIOCTL_GADDR: - /* get mac address */ - if (args) rt_memcpy(args, lpc17xx_emac_device.dev_addr, 6); - else return -RT_ERROR; - break; - - default : - break; - } - - return RT_EOK; + switch (cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if (args) rt_memcpy(args, lpc17xx_emac_device.dev_addr, 6); + else return -RT_ERROR; + break; + + default : + break; + } + + return RT_EOK; } /* EtherNet Device Interface */ /* transmit packet. */ rt_err_t lpc17xx_emac_tx( rt_device_t dev, struct pbuf* p) { - rt_uint32_t Index, IndexNext; - struct pbuf *q; - rt_uint8_t *ptr; - - /* calculate next index */ - IndexNext = LPC_EMAC->TxProduceIndex + 1; - if(IndexNext > LPC_EMAC->TxDescriptorNumber) IndexNext = 0; - - /* check whether block is full */ - while (IndexNext == LPC_EMAC->TxConsumeIndex) - { - rt_err_t result; - rt_uint32_t recved; - - /* there is no block yet, wait a flag */ - result = rt_event_recv(&tx_event, 0x01, - RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, &recved); - - RT_ASSERT(result == RT_EOK); - } - - /* lock EMAC device */ - rt_sem_take(&sem_lock, RT_WAITING_FOREVER); - - /* get produce index */ - Index = LPC_EMAC->TxProduceIndex; - - /* calculate next index */ - IndexNext = LPC_EMAC->TxProduceIndex + 1; - if(IndexNext > LPC_EMAC->TxDescriptorNumber) - IndexNext = 0; - - /* copy data to tx buffer */ - q = p; - ptr = (rt_uint8_t*)TX_BUF(Index); - while (q) - { - memcpy(ptr, q->payload, q->len); - ptr += q->len; - q = q->next; - } - - TX_DESC_CTRL(Index) &= ~0x7ff; - TX_DESC_CTRL(Index) |= (p->tot_len - 1) & 0x7ff; - - /* change index to the next */ - LPC_EMAC->TxProduceIndex = IndexNext; - - /* unlock EMAC device */ - rt_sem_release(&sem_lock); - - return RT_EOK; + rt_uint32_t Index, IndexNext; + struct pbuf *q; + rt_uint8_t *ptr; + + /* calculate next index */ + IndexNext = LPC_EMAC->TxProduceIndex + 1; + if(IndexNext > LPC_EMAC->TxDescriptorNumber) IndexNext = 0; + + /* check whether block is full */ + while (IndexNext == LPC_EMAC->TxConsumeIndex) + { + rt_err_t result; + rt_uint32_t recved; + + /* there is no block yet, wait a flag */ + result = rt_event_recv(&tx_event, 0x01, + RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, &recved); + + RT_ASSERT(result == RT_EOK); + } + + /* lock EMAC device */ + rt_sem_take(&sem_lock, RT_WAITING_FOREVER); + + /* get produce index */ + Index = LPC_EMAC->TxProduceIndex; + + /* calculate next index */ + IndexNext = LPC_EMAC->TxProduceIndex + 1; + if(IndexNext > LPC_EMAC->TxDescriptorNumber) + IndexNext = 0; + + /* copy data to tx buffer */ + q = p; + ptr = (rt_uint8_t*)TX_BUF(Index); + while (q) + { + memcpy(ptr, q->payload, q->len); + ptr += q->len; + q = q->next; + } + + TX_DESC_CTRL(Index) &= ~0x7ff; + TX_DESC_CTRL(Index) |= (p->tot_len - 1) & 0x7ff; + + /* change index to the next */ + LPC_EMAC->TxProduceIndex = IndexNext; + + /* unlock EMAC device */ + rt_sem_release(&sem_lock); + + return RT_EOK; } /* reception packet. */ struct pbuf *lpc17xx_emac_rx(rt_device_t dev) { - struct pbuf* p; - rt_uint32_t size; - rt_uint32_t Index; - - /* init p pointer */ - p = RT_NULL; - - /* lock EMAC device */ - rt_sem_take(&sem_lock, RT_WAITING_FOREVER); - - Index = LPC_EMAC->RxConsumeIndex; - if(Index != LPC_EMAC->RxProduceIndex) - { - size = (RX_STAT_INFO(Index) & 0x7ff)+1; - if (size > ETH_FRAG_SIZE) size = ETH_FRAG_SIZE; - - /* allocate buffer */ - p = pbuf_alloc(PBUF_LINK, size, PBUF_RAM); - if (p != RT_NULL) - { - struct pbuf* q; - rt_uint8_t *ptr; - - ptr = (rt_uint8_t*)RX_BUF(Index); - for (q = p; q != RT_NULL; q= q->next) - { - memcpy(q->payload, ptr, q->len); - ptr += q->len; - } - } - - /* move Index to the next */ - if(++Index > LPC_EMAC->RxDescriptorNumber) - Index = 0; - - /* set consume index */ - LPC_EMAC->RxConsumeIndex = Index; - } - else - { - /* Enable RxDone interrupt */ - LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; - } - - /* unlock EMAC device */ - rt_sem_release(&sem_lock); - - return p; + struct pbuf* p; + rt_uint32_t size; + rt_uint32_t Index; + + /* init p pointer */ + p = RT_NULL; + + /* lock EMAC device */ + rt_sem_take(&sem_lock, RT_WAITING_FOREVER); + + Index = LPC_EMAC->RxConsumeIndex; + if(Index != LPC_EMAC->RxProduceIndex) + { + size = (RX_STAT_INFO(Index) & 0x7ff)+1; + if (size > ETH_FRAG_SIZE) size = ETH_FRAG_SIZE; + + /* allocate buffer */ + p = pbuf_alloc(PBUF_LINK, size, PBUF_RAM); + if (p != RT_NULL) + { + struct pbuf* q; + rt_uint8_t *ptr; + + ptr = (rt_uint8_t*)RX_BUF(Index); + for (q = p; q != RT_NULL; q= q->next) + { + memcpy(q->payload, ptr, q->len); + ptr += q->len; + } + } + + /* move Index to the next */ + if(++Index > LPC_EMAC->RxDescriptorNumber) + Index = 0; + + /* set consume index */ + LPC_EMAC->RxConsumeIndex = Index; + } + else + { + /* Enable RxDone interrupt */ + LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; + } + + /* unlock EMAC device */ + rt_sem_release(&sem_lock); + + return p; } int lpc17xx_emac_hw_init(void) { - rt_event_init(&tx_event, "tx_event", RT_IPC_FLAG_FIFO); - rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO); - - /* set auto negotiation mode */ - lpc17xx_emac_device.phy_mode = EMAC_PHY_AUTO; - - // OUI 00-60-37 NXP Semiconductors - lpc17xx_emac_device.dev_addr[0] = 0x00; - lpc17xx_emac_device.dev_addr[1] = 0x60; - lpc17xx_emac_device.dev_addr[2] = 0x37; - /* set mac address: (only for test) */ - lpc17xx_emac_device.dev_addr[3] = 0x12; - lpc17xx_emac_device.dev_addr[4] = 0x34; - lpc17xx_emac_device.dev_addr[5] = 0x56; - - lpc17xx_emac_device.parent.parent.init = lpc17xx_emac_init; - lpc17xx_emac_device.parent.parent.open = lpc17xx_emac_open; - lpc17xx_emac_device.parent.parent.close = lpc17xx_emac_close; - lpc17xx_emac_device.parent.parent.read = lpc17xx_emac_read; - lpc17xx_emac_device.parent.parent.write = lpc17xx_emac_write; - lpc17xx_emac_device.parent.parent.control = lpc17xx_emac_control; - lpc17xx_emac_device.parent.parent.user_data = RT_NULL; - - lpc17xx_emac_device.parent.eth_rx = lpc17xx_emac_rx; - lpc17xx_emac_device.parent.eth_tx = lpc17xx_emac_tx; - - eth_device_init(&(lpc17xx_emac_device.parent), "e0"); - return 0; + rt_event_init(&tx_event, "tx_event", RT_IPC_FLAG_FIFO); + rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO); + + /* set auto negotiation mode */ + lpc17xx_emac_device.phy_mode = EMAC_PHY_AUTO; + + // OUI 00-60-37 NXP Semiconductors + lpc17xx_emac_device.dev_addr[0] = 0x00; + lpc17xx_emac_device.dev_addr[1] = 0x60; + lpc17xx_emac_device.dev_addr[2] = 0x37; + /* set mac address: (only for test) */ + lpc17xx_emac_device.dev_addr[3] = 0x12; + lpc17xx_emac_device.dev_addr[4] = 0x34; + lpc17xx_emac_device.dev_addr[5] = 0x56; + + lpc17xx_emac_device.parent.parent.init = lpc17xx_emac_init; + lpc17xx_emac_device.parent.parent.open = lpc17xx_emac_open; + lpc17xx_emac_device.parent.parent.close = lpc17xx_emac_close; + lpc17xx_emac_device.parent.parent.read = lpc17xx_emac_read; + lpc17xx_emac_device.parent.parent.write = lpc17xx_emac_write; + lpc17xx_emac_device.parent.parent.control = lpc17xx_emac_control; + lpc17xx_emac_device.parent.parent.user_data = RT_NULL; + + lpc17xx_emac_device.parent.eth_rx = lpc17xx_emac_rx; + lpc17xx_emac_device.parent.eth_tx = lpc17xx_emac_tx; + + eth_device_init(&(lpc17xx_emac_device.parent), "e0"); + return 0; } INIT_DEVICE_EXPORT(lpc17xx_emac_hw_init); diff --git a/bsp/lpc176x/drivers/led.h b/bsp/lpc176x/drivers/led.h index 658ed16d1c..92f6ff4ffd 100644 --- a/bsp/lpc176x/drivers/led.h +++ b/bsp/lpc176x/drivers/led.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc176x/drivers/sd.c b/bsp/lpc176x/drivers/sd.c index 61e34ba43a..53b57676de 100644 --- a/bsp/lpc176x/drivers/sd.c +++ b/bsp/lpc176x/drivers/sd.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -467,12 +467,12 @@ static rt_err_t rt_sdcard_control(rt_device_t dev, int cmd, void *args) if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME) { struct rt_device_blk_geometry *geometry; - + geometry = (struct rt_device_blk_geometry *)args; - + if (geometry == RT_NULL) return -RT_ERROR; if (dev->user_data == RT_NULL) return -RT_ERROR; - + geometry->bytes_per_sector = ((SDCFG *)dev->user_data)->sectorsize; geometry->block_size = ((SDCFG *)dev->user_data)->blocksize; geometry->sector_count = ((SDCFG *)dev->user_data)->sectorcnt; diff --git a/bsp/lpc176x/drivers/uart.c b/bsp/lpc176x/drivers/uart.c index 231eccb10a..a32952124b 100644 --- a/bsp/lpc176x/drivers/uart.c +++ b/bsp/lpc176x/drivers/uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -56,8 +56,8 @@ void UART0_IRQHandler(void) { rt_ubase_t level, iir; struct rt_uart_lpc *uart = &uart_device; - /* enter interrupt */ - rt_interrupt_enter(); + /* enter interrupt */ + rt_interrupt_enter(); /* read IIR and clear it */ iir = LPC_UART->IIR; @@ -91,8 +91,8 @@ void UART0_IRQHandler(void) { iir = LPC_UART->LSR; //oe pe fe oe read for clear interrupt } - /* leave interrupt */ - rt_interrupt_leave(); + /* leave interrupt */ + rt_interrupt_leave(); return; } diff --git a/bsp/lpc178x/applications/application.c b/bsp/lpc178x/applications/application.c index 9780d42154..b4f437405b 100644 --- a/bsp/lpc178x/applications/application.c +++ b/bsp/lpc178x/applications/application.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -75,33 +75,33 @@ void rt_init_thread_entry(void *parameter) #ifdef RT_USING_RTGUI { - extern void rtgui_system_server_init(void); - extern void application_init(void); + extern void rtgui_system_server_init(void); + extern void application_init(void); - rt_device_t lcd; + rt_device_t lcd; - /* init lcd */ - rt_hw_lcd_init(); + /* init lcd */ + rt_hw_lcd_init(); - /* find lcd device */ - lcd = rt_device_find("lcd"); - if (lcd != RT_NULL) - { - /* set lcd device as rtgui graphic driver */ - rtgui_graphic_set_device(lcd); + /* find lcd device */ + lcd = rt_device_find("lcd"); + if (lcd != RT_NULL) + { + /* set lcd device as rtgui graphic driver */ + rtgui_graphic_set_device(lcd); - /* init rtgui system server */ - rtgui_system_server_init(); + /* init rtgui system server */ + rtgui_system_server_init(); - /* startup rtgui in demo of RT-Thread/GUI examples */ - application_init(); - } + /* startup rtgui in demo of RT-Thread/GUI examples */ + application_init(); + } } #endif #ifdef RT_USING_FINSH - /* initialize finsh */ - finsh_system_init(); + /* initialize finsh */ + finsh_system_init(); #endif } @@ -143,22 +143,22 @@ static void rt_thread_entry_led(void* parameter) int rt_application_init(void) { - rt_thread_t tid; - - rt_thread_init(&thread_led, - "led", - rt_thread_entry_led, - RT_NULL, - &thread_led_stack[0], - sizeof(thread_led_stack),11,5); - rt_thread_startup(&thread_led); - - tid = rt_thread_create("init", - rt_init_thread_entry, RT_NULL, - 2048, RT_THREAD_PRIORITY_MAX/3, 20); - if (tid != RT_NULL) rt_thread_startup(tid); - - return 0; + rt_thread_t tid; + + rt_thread_init(&thread_led, + "led", + rt_thread_entry_led, + RT_NULL, + &thread_led_stack[0], + sizeof(thread_led_stack),11,5); + rt_thread_startup(&thread_led); + + tid = rt_thread_create("init", + rt_init_thread_entry, RT_NULL, + 2048, RT_THREAD_PRIORITY_MAX/3, 20); + if (tid != RT_NULL) rt_thread_startup(tid); + + return 0; } #if defined(RT_USING_RTGUI) && defined(RT_USING_FINSH) @@ -170,20 +170,20 @@ int rt_application_init(void) void key(rt_uint32_t key) { - struct rtgui_event_kbd ekbd; + struct rtgui_event_kbd ekbd; - RTGUI_EVENT_KBD_INIT(&ekbd); - ekbd.mod = RTGUI_KMOD_NONE; - ekbd.unicode = 0; - ekbd.key = key; + RTGUI_EVENT_KBD_INIT(&ekbd); + ekbd.mod = RTGUI_KMOD_NONE; + ekbd.unicode = 0; + ekbd.key = key; - ekbd.type = RTGUI_KEYDOWN; - rtgui_server_post_event((struct rtgui_event*)&ekbd, sizeof(ekbd)); + ekbd.type = RTGUI_KEYDOWN; + rtgui_server_post_event((struct rtgui_event*)&ekbd, sizeof(ekbd)); - rt_thread_delay(2); + rt_thread_delay(2); - ekbd.type = RTGUI_KEYUP; - rtgui_server_post_event((struct rtgui_event*)&ekbd, sizeof(ekbd)); + ekbd.type = RTGUI_KEYUP; + rtgui_server_post_event((struct rtgui_event*)&ekbd, sizeof(ekbd)); } FINSH_FUNCTION_EXPORT(key, send a key to gui server); #endif diff --git a/bsp/lpc178x/applications/startup.c b/bsp/lpc178x/applications/startup.c index 07698574b5..8b25e7d405 100644 --- a/bsp/lpc178x/applications/startup.c +++ b/bsp/lpc178x/applications/startup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -37,11 +37,11 @@ extern int __bss_end; *******************************************************************************/ void assert_failed(u8* file, u32 line) { - rt_kprintf("\n\r Wrong parameter value detected on\r\n"); - rt_kprintf(" file %s\r\n", file); - rt_kprintf(" line %d\r\n", line); + rt_kprintf("\n\r Wrong parameter value detected on\r\n"); + rt_kprintf(" file %s\r\n", file); + rt_kprintf(" line %d\r\n", line); - while (1) ; + while (1) ; } #endif @@ -50,28 +50,28 @@ void assert_failed(u8* file, u32 line) */ void rtthread_startup(void) { - /* initialize board */ - rt_hw_board_init(); + /* initialize board */ + rt_hw_board_init(); - /* show version */ - rt_show_version(); + /* show version */ + rt_show_version(); #ifdef RT_USING_HEAP - /* initialize memory system */ - #ifdef __CC_ARM - rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)(0x10000000 + 1024*64)); - #elif __ICCARM__ - rt_system_heap_init(__segment_end("HEAP"), (void*)(0x10000000 + 1024*64)); - #else - rt_system_heap_init((void*)&__bss_end, (void*)(0x10000000 + 1024*64)); - #endif + /* initialize memory system */ + #ifdef __CC_ARM + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)(0x10000000 + 1024*64)); + #elif __ICCARM__ + rt_system_heap_init(__segment_end("HEAP"), (void*)(0x10000000 + 1024*64)); + #else + rt_system_heap_init((void*)&__bss_end, (void*)(0x10000000 + 1024*64)); + #endif #endif - /* initialize scheduler system */ - rt_system_scheduler_init(); + /* initialize scheduler system */ + rt_system_scheduler_init(); - /* initialize application */ - rt_application_init(); + /* initialize application */ + rt_application_init(); /* initialize timer */ rt_system_timer_init(); @@ -79,23 +79,23 @@ void rtthread_startup(void) /* initialize timer thread */ rt_system_timer_thread_init(); - /* initialize idle thread */ - rt_thread_idle_init(); + /* initialize idle thread */ + rt_thread_idle_init(); - /* start scheduler */ - rt_system_scheduler_start(); + /* start scheduler */ + rt_system_scheduler_start(); - /* never reach here */ - return ; + /* never reach here */ + return ; } int main(void) { - /* disable interrupt first */ - rt_hw_interrupt_disable(); + /* disable interrupt first */ + rt_hw_interrupt_disable(); - /* startup RT-Thread RTOS */ - rtthread_startup(); + /* startup RT-Thread RTOS */ + rtthread_startup(); - return 0; + return 0; } diff --git a/bsp/lpc178x/drivers/board.c b/bsp/lpc178x/drivers/board.c index df06d7f2f8..c07150e525 100644 --- a/bsp/lpc178x/drivers/board.c +++ b/bsp/lpc178x/drivers/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc178x/drivers/board.h b/bsp/lpc178x/drivers/board.h index 1a6d82e4b7..3c0a7fad71 100644 --- a/bsp/lpc178x/drivers/board.h +++ b/bsp/lpc178x/drivers/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -31,7 +31,7 @@ //#define RT_USING_UART2 // -#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_CONSOLE_DEVICE_NAME "uart0" // diff --git a/bsp/lpc178x/drivers/emac.c b/bsp/lpc178x/drivers/emac.c index a16dc49770..ec48ea8833 100644 --- a/bsp/lpc178x/drivers/emac.c +++ b/bsp/lpc178x/drivers/emac.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,20 +14,20 @@ #include "lwipopts.h" #include -#define EMAC_PHY_AUTO 0 -#define EMAC_PHY_10MBIT 1 -#define EMAC_PHY_100MBIT 2 +#define EMAC_PHY_AUTO 0 +#define EMAC_PHY_10MBIT 1 +#define EMAC_PHY_100MBIT 2 #define MAX_ADDR_LEN 6 struct lpc17xx_emac { - /* inherit from ethernet device */ - struct eth_device parent; + /* inherit from ethernet device */ + struct eth_device parent; - rt_uint8_t phy_mode; + rt_uint8_t phy_mode; - /* interface address info. */ - rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ + /* interface address info. */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ }; static struct lpc17xx_emac lpc17xx_emac_device; static struct rt_semaphore sem_lock; @@ -39,39 +39,39 @@ static rt_uint16_t read_PHY (rt_uint8_t PhyReg) ; void ENET_IRQHandler(void) { - rt_uint32_t status; + rt_uint32_t status; /* enter interrupt */ rt_interrupt_enter(); - status = LPC_EMAC->IntStatus; + status = LPC_EMAC->IntStatus; - if (status & INT_RX_DONE) - { - /* Disable EMAC RxDone interrupts. */ - LPC_EMAC->IntEnable = INT_TX_DONE; + if (status & INT_RX_DONE) + { + /* Disable EMAC RxDone interrupts. */ + LPC_EMAC->IntEnable = INT_TX_DONE; - /* a frame has been received */ - eth_device_ready(&(lpc17xx_emac_device.parent)); - } - else if (status & INT_TX_DONE) - { - /* set event */ - rt_event_send(&tx_event, 0x01); - } + /* a frame has been received */ + eth_device_ready(&(lpc17xx_emac_device.parent)); + } + else if (status & INT_TX_DONE) + { + /* set event */ + rt_event_send(&tx_event, 0x01); + } - if (status & INT_RX_OVERRUN) - { - rt_kprintf("rx overrun\n"); - } + if (status & INT_RX_OVERRUN) + { + rt_kprintf("rx overrun\n"); + } - if (status & INT_TX_UNDERRUN) - { - rt_kprintf("tx underrun\n"); - } + if (status & INT_TX_UNDERRUN) + { + rt_kprintf("tx underrun\n"); + } - /* Clear the interrupt. */ - LPC_EMAC->IntClear = status; + /* Clear the interrupt. */ + LPC_EMAC->IntClear = status; /* leave interrupt */ rt_interrupt_leave(); @@ -80,84 +80,84 @@ void ENET_IRQHandler(void) /* phy write */ static void write_PHY (rt_uint32_t PhyReg, rt_uint32_t Value) { - unsigned int tout; - - LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg; - LPC_EMAC->MWTD = Value; - - /* Wait utill operation completed */ - tout = 0; - for (tout = 0; tout < MII_WR_TOUT; tout++) - { - if ((LPC_EMAC->MIND & MIND_BUSY) == 0) - { - break; - } - } + unsigned int tout; + + LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg; + LPC_EMAC->MWTD = Value; + + /* Wait utill operation completed */ + tout = 0; + for (tout = 0; tout < MII_WR_TOUT; tout++) + { + if ((LPC_EMAC->MIND & MIND_BUSY) == 0) + { + break; + } + } } /* phy read */ static rt_uint16_t read_PHY (rt_uint8_t PhyReg) { - rt_uint32_t tout; - - LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg; - LPC_EMAC->MCMD = MCMD_READ; - - /* Wait until operation completed */ - tout = 0; - for (tout = 0; tout < MII_RD_TOUT; tout++) - { - if ((LPC_EMAC->MIND & MIND_BUSY) == 0) - { - break; - } - } - LPC_EMAC->MCMD = 0; - return (LPC_EMAC->MRDD); + rt_uint32_t tout; + + LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg; + LPC_EMAC->MCMD = MCMD_READ; + + /* Wait until operation completed */ + tout = 0; + for (tout = 0; tout < MII_RD_TOUT; tout++) + { + if ((LPC_EMAC->MIND & MIND_BUSY) == 0) + { + break; + } + } + LPC_EMAC->MCMD = 0; + return (LPC_EMAC->MRDD); } /* init rx descriptor */ rt_inline void rx_descr_init (void) { - rt_uint32_t i; - - for (i = 0; i < NUM_RX_FRAG; i++) - { - RX_DESC_PACKET(i) = RX_BUF(i); - RX_DESC_CTRL(i) = RCTRL_INT | (ETH_FRAG_SIZE-1); - RX_STAT_INFO(i) = 0; - RX_STAT_HASHCRC(i) = 0; - } - - /* Set EMAC Receive Descriptor Registers. */ - LPC_EMAC->RxDescriptor = RX_DESC_BASE; - LPC_EMAC->RxStatus = RX_STAT_BASE; - LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1; - - /* Rx Descriptors Point to 0 */ - LPC_EMAC->RxConsumeIndex = 0; + rt_uint32_t i; + + for (i = 0; i < NUM_RX_FRAG; i++) + { + RX_DESC_PACKET(i) = RX_BUF(i); + RX_DESC_CTRL(i) = RCTRL_INT | (ETH_FRAG_SIZE-1); + RX_STAT_INFO(i) = 0; + RX_STAT_HASHCRC(i) = 0; + } + + /* Set EMAC Receive Descriptor Registers. */ + LPC_EMAC->RxDescriptor = RX_DESC_BASE; + LPC_EMAC->RxStatus = RX_STAT_BASE; + LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1; + + /* Rx Descriptors Point to 0 */ + LPC_EMAC->RxConsumeIndex = 0; } /* init tx descriptor */ rt_inline void tx_descr_init (void) { - rt_uint32_t i; - - for (i = 0; i < NUM_TX_FRAG; i++) - { - TX_DESC_PACKET(i) = TX_BUF(i); - TX_DESC_CTRL(i) = (1ul<<31) | (1ul<<30) | (1ul<<29) | (1ul<<28) | (1ul<<26) | (ETH_FRAG_SIZE-1); - TX_STAT_INFO(i) = 0; - } - - /* Set EMAC Transmit Descriptor Registers. */ - LPC_EMAC->TxDescriptor = TX_DESC_BASE; - LPC_EMAC->TxStatus = TX_STAT_BASE; - LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1; - - /* Tx Descriptors Point to 0 */ - LPC_EMAC->TxProduceIndex = 0; + rt_uint32_t i; + + for (i = 0; i < NUM_TX_FRAG; i++) + { + TX_DESC_PACKET(i) = TX_BUF(i); + TX_DESC_CTRL(i) = (1ul<<31) | (1ul<<30) | (1ul<<29) | (1ul<<28) | (1ul<<26) | (ETH_FRAG_SIZE-1); + TX_STAT_INFO(i) = 0; + } + + /* Set EMAC Transmit Descriptor Registers. */ + LPC_EMAC->TxDescriptor = TX_DESC_BASE; + LPC_EMAC->TxStatus = TX_STAT_BASE; + LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1; + + /* Tx Descriptors Point to 0 */ + LPC_EMAC->TxProduceIndex = 0; } /* @@ -178,375 +178,375 @@ REF_CLK P1_15 */ static rt_err_t lpc17xx_emac_init(rt_device_t dev) { - /* Initialize the EMAC ethernet controller. */ - rt_uint32_t regv, tout; - - /* Power Up the EMAC controller. */ - LPC_SC->PCONP |= (1UL<<30); - - /* config RESET */ - PINSEL_ConfigPin(3, 19, 0); - PINSEL_SetPinMode(3, 19, IOCON_MODE_PLAIN); - LPC_GPIO3->DIR |= 1<<19; - LPC_GPIO3->CLR = 1<<19; - - /* Enable P1 Ethernet Pins. */ - PINSEL_ConfigPin(1, 0, 1); /**< P1_0 ENET_TXD0 */ - PINSEL_ConfigPin(1, 1, 1); /**< P1_1 ENET_TXD1 */ - PINSEL_ConfigPin(1, 4, 1); /**< P1_4 ENET_TX_EN */ - PINSEL_ConfigPin(1, 8, 1); /**< P1_8 ENET_CRS_DV */ - PINSEL_ConfigPin(1, 9, 1); /**< P1_9 ENET_RXD0 */ - PINSEL_ConfigPin(1, 10, 1); /**< P1_10 ENET_RXD1 */ - PINSEL_ConfigPin(1, 14, 1); /**< P1_14 ENET_RX_ER */ - PINSEL_ConfigPin(1, 15, 1); /**< P1_15 ENET_REF_CLK */ - PINSEL_ConfigPin(1, 16, 1); /**< P1_16 ENET_MDC */ - PINSEL_ConfigPin(1, 17, 1); /**< P1_17 ENET_MDIO */ - - LPC_GPIO3->SET = 1<<19; - - /* Reset all EMAC internal modules. */ - LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | - MAC1_SIM_RES | MAC1_SOFT_RES; - LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES; - - /* A short delay after reset. */ - for (tout = 100; tout; tout--); - - /* Initialize MAC control registers. */ - LPC_EMAC->MAC1 = MAC1_PASS_ALL; - LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN; - LPC_EMAC->MAXF = ETH_MAX_FLEN; - LPC_EMAC->CLRT = CLRT_DEF; - LPC_EMAC->IPGR = IPGR_DEF; - - /* PCLK=18MHz, clock select=6, MDC=18/6=3MHz */ - /* Enable Reduced MII interface. */ - LPC_EMAC->MCFG = MCFG_CLK_DIV20 | MCFG_RES_MII; - for (tout = 100; tout; tout--); - LPC_EMAC->MCFG = MCFG_CLK_DIV20; - - /* Enable Reduced MII interface. */ - LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM | CR_PASS_RX_FILT; - - /* Reset Reduced MII Logic. */ - LPC_EMAC->SUPP = SUPP_RES_RMII | SUPP_SPEED; - for (tout = 100; tout; tout--); - LPC_EMAC->SUPP = SUPP_SPEED; - - /* Put the PHY in reset mode */ - write_PHY (PHY_REG_BMCR, 0x8000); - for (tout = 1000; tout; tout--); - -// /* Wait for hardware reset to end. */ -// for (tout = 0; tout < 0x100000; tout++) -// { -// regv = read_PHY (PHY_REG_BMCR); -// if (!(regv & 0x8000)) -// { -// /* Reset complete */ -// break; -// } -// } -// if (tout >= 0x100000) + /* Initialize the EMAC ethernet controller. */ + rt_uint32_t regv, tout; + + /* Power Up the EMAC controller. */ + LPC_SC->PCONP |= (1UL<<30); + + /* config RESET */ + PINSEL_ConfigPin(3, 19, 0); + PINSEL_SetPinMode(3, 19, IOCON_MODE_PLAIN); + LPC_GPIO3->DIR |= 1<<19; + LPC_GPIO3->CLR = 1<<19; + + /* Enable P1 Ethernet Pins. */ + PINSEL_ConfigPin(1, 0, 1); /**< P1_0 ENET_TXD0 */ + PINSEL_ConfigPin(1, 1, 1); /**< P1_1 ENET_TXD1 */ + PINSEL_ConfigPin(1, 4, 1); /**< P1_4 ENET_TX_EN */ + PINSEL_ConfigPin(1, 8, 1); /**< P1_8 ENET_CRS_DV */ + PINSEL_ConfigPin(1, 9, 1); /**< P1_9 ENET_RXD0 */ + PINSEL_ConfigPin(1, 10, 1); /**< P1_10 ENET_RXD1 */ + PINSEL_ConfigPin(1, 14, 1); /**< P1_14 ENET_RX_ER */ + PINSEL_ConfigPin(1, 15, 1); /**< P1_15 ENET_REF_CLK */ + PINSEL_ConfigPin(1, 16, 1); /**< P1_16 ENET_MDC */ + PINSEL_ConfigPin(1, 17, 1); /**< P1_17 ENET_MDIO */ + + LPC_GPIO3->SET = 1<<19; + + /* Reset all EMAC internal modules. */ + LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | + MAC1_SIM_RES | MAC1_SOFT_RES; + LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES; + + /* A short delay after reset. */ + for (tout = 100; tout; tout--); + + /* Initialize MAC control registers. */ + LPC_EMAC->MAC1 = MAC1_PASS_ALL; + LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN; + LPC_EMAC->MAXF = ETH_MAX_FLEN; + LPC_EMAC->CLRT = CLRT_DEF; + LPC_EMAC->IPGR = IPGR_DEF; + + /* PCLK=18MHz, clock select=6, MDC=18/6=3MHz */ + /* Enable Reduced MII interface. */ + LPC_EMAC->MCFG = MCFG_CLK_DIV20 | MCFG_RES_MII; + for (tout = 100; tout; tout--); + LPC_EMAC->MCFG = MCFG_CLK_DIV20; + + /* Enable Reduced MII interface. */ + LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM | CR_PASS_RX_FILT; + + /* Reset Reduced MII Logic. */ + LPC_EMAC->SUPP = SUPP_RES_RMII | SUPP_SPEED; + for (tout = 100; tout; tout--); + LPC_EMAC->SUPP = SUPP_SPEED; + + /* Put the PHY in reset mode */ + write_PHY (PHY_REG_BMCR, 0x8000); + for (tout = 1000; tout; tout--); + +// /* Wait for hardware reset to end. */ +// for (tout = 0; tout < 0x100000; tout++) +// { +// regv = read_PHY (PHY_REG_BMCR); +// if (!(regv & 0x8000)) +// { +// /* Reset complete */ +// break; +// } +// } +// if (tout >= 0x100000) // { // rt_kprintf("reset failed\r\n"); // return -RT_ERROR; /* reset failed */ // } -// /* Check if this is a DP83848C PHY. */ -// id1 = read_PHY (PHY_REG_IDR1); -// id2 = read_PHY (PHY_REG_IDR2); +// /* Check if this is a DP83848C PHY. */ +// id1 = read_PHY (PHY_REG_IDR1); +// id2 = read_PHY (PHY_REG_IDR2); // -// if (((id1 << 16) | (id2 & 0xFFF0)) != DP83848C_ID) -// return -RT_ERROR; - - /* Configure the PHY device */ - /* Configure the PHY device */ - switch (lpc17xx_emac_device.phy_mode) - { - case EMAC_PHY_AUTO: - /* Use autonegotiation about the link speed. */ - write_PHY (PHY_REG_BMCR, PHY_AUTO_NEG); - /* Wait to complete Auto_Negotiation. */ -// for (tout = 0; tout < 0x100000; tout++) -// { -// regv = read_PHY (PHY_REG_BMSR); -// if (regv & 0x0020) -// { -// /* Autonegotiation Complete. */ -// break; -// } -// } - break; - case EMAC_PHY_10MBIT: - /* Connect at 10MBit */ - write_PHY (PHY_REG_BMCR, PHY_FULLD_10M); - break; - case EMAC_PHY_100MBIT: - /* Connect at 100MBit */ - write_PHY (PHY_REG_BMCR, PHY_FULLD_100M); - break; - } - if (tout >= 0x100000) return -RT_ERROR; // auto_neg failed - -// /* Check the link status. */ -// for (tout = 0; tout < 0x10000; tout++) -// { -// regv = read_PHY (PHY_REG_STS); -// if (regv & 0x0001) -// { -// /* Link is on. */ -// break; -// } -// } -// if (tout >= 0x10000) return -RT_ERROR; - - regv = 0x0004; - /* Configure Full/Half Duplex mode. */ - if (regv & 0x0004) - { - /* Full duplex is enabled. */ - LPC_EMAC->MAC2 |= MAC2_FULL_DUP; - LPC_EMAC->Command |= CR_FULL_DUP; - LPC_EMAC->IPGT = IPGT_FULL_DUP; - } - else - { - /* Half duplex mode. */ - LPC_EMAC->IPGT = IPGT_HALF_DUP; - } - - /* Configure 100MBit/10MBit mode. */ - if (regv & 0x0002) - { - /* 10MBit mode. */ - LPC_EMAC->SUPP = 0; - } - else - { - /* 100MBit mode. */ - LPC_EMAC->SUPP = SUPP_SPEED; - } - - /* Set the Ethernet MAC Address registers */ - LPC_EMAC->SA0 = (lpc17xx_emac_device.dev_addr[1]<<8) | lpc17xx_emac_device.dev_addr[0]; - LPC_EMAC->SA1 = (lpc17xx_emac_device.dev_addr[3]<<8) | lpc17xx_emac_device.dev_addr[2]; - LPC_EMAC->SA2 = (lpc17xx_emac_device.dev_addr[5]<<8) | lpc17xx_emac_device.dev_addr[4]; - - /* Initialize Tx and Rx DMA Descriptors */ - rx_descr_init (); - tx_descr_init (); - - /* Receive Broadcast and Perfect Match Packets */ - LPC_EMAC->RxFilterCtrl = RFC_BCAST_EN | RFC_PERFECT_EN; - - /* Reset all interrupts */ - LPC_EMAC->IntClear = 0xFFFF; - - /* Enable EMAC interrupts. */ - LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; - - /* Enable receive and transmit mode of MAC Ethernet core */ - LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN); - LPC_EMAC->MAC1 |= MAC1_REC_EN; - - /* Enable the ENET Interrupt */ - NVIC_EnableIRQ(ENET_IRQn); - - return RT_EOK; +// if (((id1 << 16) | (id2 & 0xFFF0)) != DP83848C_ID) +// return -RT_ERROR; + + /* Configure the PHY device */ + /* Configure the PHY device */ + switch (lpc17xx_emac_device.phy_mode) + { + case EMAC_PHY_AUTO: + /* Use autonegotiation about the link speed. */ + write_PHY (PHY_REG_BMCR, PHY_AUTO_NEG); + /* Wait to complete Auto_Negotiation. */ +// for (tout = 0; tout < 0x100000; tout++) +// { +// regv = read_PHY (PHY_REG_BMSR); +// if (regv & 0x0020) +// { +// /* Autonegotiation Complete. */ +// break; +// } +// } + break; + case EMAC_PHY_10MBIT: + /* Connect at 10MBit */ + write_PHY (PHY_REG_BMCR, PHY_FULLD_10M); + break; + case EMAC_PHY_100MBIT: + /* Connect at 100MBit */ + write_PHY (PHY_REG_BMCR, PHY_FULLD_100M); + break; + } + if (tout >= 0x100000) return -RT_ERROR; // auto_neg failed + +// /* Check the link status. */ +// for (tout = 0; tout < 0x10000; tout++) +// { +// regv = read_PHY (PHY_REG_STS); +// if (regv & 0x0001) +// { +// /* Link is on. */ +// break; +// } +// } +// if (tout >= 0x10000) return -RT_ERROR; + + regv = 0x0004; + /* Configure Full/Half Duplex mode. */ + if (regv & 0x0004) + { + /* Full duplex is enabled. */ + LPC_EMAC->MAC2 |= MAC2_FULL_DUP; + LPC_EMAC->Command |= CR_FULL_DUP; + LPC_EMAC->IPGT = IPGT_FULL_DUP; + } + else + { + /* Half duplex mode. */ + LPC_EMAC->IPGT = IPGT_HALF_DUP; + } + + /* Configure 100MBit/10MBit mode. */ + if (regv & 0x0002) + { + /* 10MBit mode. */ + LPC_EMAC->SUPP = 0; + } + else + { + /* 100MBit mode. */ + LPC_EMAC->SUPP = SUPP_SPEED; + } + + /* Set the Ethernet MAC Address registers */ + LPC_EMAC->SA0 = (lpc17xx_emac_device.dev_addr[1]<<8) | lpc17xx_emac_device.dev_addr[0]; + LPC_EMAC->SA1 = (lpc17xx_emac_device.dev_addr[3]<<8) | lpc17xx_emac_device.dev_addr[2]; + LPC_EMAC->SA2 = (lpc17xx_emac_device.dev_addr[5]<<8) | lpc17xx_emac_device.dev_addr[4]; + + /* Initialize Tx and Rx DMA Descriptors */ + rx_descr_init (); + tx_descr_init (); + + /* Receive Broadcast and Perfect Match Packets */ + LPC_EMAC->RxFilterCtrl = RFC_BCAST_EN | RFC_PERFECT_EN; + + /* Reset all interrupts */ + LPC_EMAC->IntClear = 0xFFFF; + + /* Enable EMAC interrupts. */ + LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; + + /* Enable receive and transmit mode of MAC Ethernet core */ + LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN); + LPC_EMAC->MAC1 |= MAC1_REC_EN; + + /* Enable the ENET Interrupt */ + NVIC_EnableIRQ(ENET_IRQn); + + return RT_EOK; } static rt_err_t lpc17xx_emac_open(rt_device_t dev, rt_uint16_t oflag) { - return RT_EOK; + return RT_EOK; } static rt_err_t lpc17xx_emac_close(rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_size_t lpc17xx_emac_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_size_t lpc17xx_emac_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_err_t lpc17xx_emac_control(rt_device_t dev, int cmd, void *args) { - switch (cmd) - { - case NIOCTL_GADDR: - /* get mac address */ - if (args) rt_memcpy(args, lpc17xx_emac_device.dev_addr, 6); - else return -RT_ERROR; - break; - - default : - break; - } - - return RT_EOK; + switch (cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if (args) rt_memcpy(args, lpc17xx_emac_device.dev_addr, 6); + else return -RT_ERROR; + break; + + default : + break; + } + + return RT_EOK; } /* EtherNet Device Interface */ /* transmit packet. */ rt_err_t lpc17xx_emac_tx( rt_device_t dev, struct pbuf* p) { - rt_uint32_t Index, IndexNext; - struct pbuf *q; - rt_uint8_t *ptr; - - /* calculate next index */ - IndexNext = LPC_EMAC->TxProduceIndex + 1; - if(IndexNext > LPC_EMAC->TxDescriptorNumber) IndexNext = 0; - - /* check whether block is full */ - while (IndexNext == LPC_EMAC->TxConsumeIndex) - { - rt_err_t result; - rt_uint32_t recved; - - /* there is no block yet, wait a flag */ - result = rt_event_recv(&tx_event, 0x01, - RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, &recved); - - RT_ASSERT(result == RT_EOK); - } - - /* lock EMAC device */ - rt_sem_take(&sem_lock, RT_WAITING_FOREVER); - - /* get produce index */ - Index = LPC_EMAC->TxProduceIndex; - - /* calculate next index */ - IndexNext = LPC_EMAC->TxProduceIndex + 1; - if(IndexNext > LPC_EMAC->TxDescriptorNumber) - IndexNext = 0; - - /* copy data to tx buffer */ - q = p; - ptr = (rt_uint8_t*)TX_BUF(Index); - while (q) - { - memcpy(ptr, q->payload, q->len); - ptr += q->len; - q = q->next; - } - - TX_DESC_CTRL(Index) &= ~0x7ff; - TX_DESC_CTRL(Index) |= (p->tot_len - 1) & 0x7ff; - - /* change index to the next */ - LPC_EMAC->TxProduceIndex = IndexNext; - - /* unlock EMAC device */ - rt_sem_release(&sem_lock); - - return RT_EOK; + rt_uint32_t Index, IndexNext; + struct pbuf *q; + rt_uint8_t *ptr; + + /* calculate next index */ + IndexNext = LPC_EMAC->TxProduceIndex + 1; + if(IndexNext > LPC_EMAC->TxDescriptorNumber) IndexNext = 0; + + /* check whether block is full */ + while (IndexNext == LPC_EMAC->TxConsumeIndex) + { + rt_err_t result; + rt_uint32_t recved; + + /* there is no block yet, wait a flag */ + result = rt_event_recv(&tx_event, 0x01, + RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, &recved); + + RT_ASSERT(result == RT_EOK); + } + + /* lock EMAC device */ + rt_sem_take(&sem_lock, RT_WAITING_FOREVER); + + /* get produce index */ + Index = LPC_EMAC->TxProduceIndex; + + /* calculate next index */ + IndexNext = LPC_EMAC->TxProduceIndex + 1; + if(IndexNext > LPC_EMAC->TxDescriptorNumber) + IndexNext = 0; + + /* copy data to tx buffer */ + q = p; + ptr = (rt_uint8_t*)TX_BUF(Index); + while (q) + { + memcpy(ptr, q->payload, q->len); + ptr += q->len; + q = q->next; + } + + TX_DESC_CTRL(Index) &= ~0x7ff; + TX_DESC_CTRL(Index) |= (p->tot_len - 1) & 0x7ff; + + /* change index to the next */ + LPC_EMAC->TxProduceIndex = IndexNext; + + /* unlock EMAC device */ + rt_sem_release(&sem_lock); + + return RT_EOK; } /* reception packet. */ struct pbuf *lpc17xx_emac_rx(rt_device_t dev) { - struct pbuf* p; - rt_uint32_t size; - rt_uint32_t Index; - - /* init p pointer */ - p = RT_NULL; - - /* lock EMAC device */ - rt_sem_take(&sem_lock, RT_WAITING_FOREVER); - - Index = LPC_EMAC->RxConsumeIndex; - if(Index != LPC_EMAC->RxProduceIndex) - { - size = (RX_STAT_INFO(Index) & 0x7ff)+1; - if (size > ETH_FRAG_SIZE) size = ETH_FRAG_SIZE; - - /* allocate buffer */ - p = pbuf_alloc(PBUF_LINK, size, PBUF_RAM); - if (p != RT_NULL) - { - struct pbuf* q; - rt_uint8_t *ptr; - - ptr = (rt_uint8_t*)RX_BUF(Index); - for (q = p; q != RT_NULL; q= q->next) - { - memcpy(q->payload, ptr, q->len); - ptr += q->len; - } - } - - /* move Index to the next */ - if(++Index > LPC_EMAC->RxDescriptorNumber) - Index = 0; - - /* set consume index */ - LPC_EMAC->RxConsumeIndex = Index; - } - else - { - /* Enable RxDone interrupt */ - LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; - } - - /* unlock EMAC device */ - rt_sem_release(&sem_lock); - - return p; + struct pbuf* p; + rt_uint32_t size; + rt_uint32_t Index; + + /* init p pointer */ + p = RT_NULL; + + /* lock EMAC device */ + rt_sem_take(&sem_lock, RT_WAITING_FOREVER); + + Index = LPC_EMAC->RxConsumeIndex; + if(Index != LPC_EMAC->RxProduceIndex) + { + size = (RX_STAT_INFO(Index) & 0x7ff)+1; + if (size > ETH_FRAG_SIZE) size = ETH_FRAG_SIZE; + + /* allocate buffer */ + p = pbuf_alloc(PBUF_LINK, size, PBUF_RAM); + if (p != RT_NULL) + { + struct pbuf* q; + rt_uint8_t *ptr; + + ptr = (rt_uint8_t*)RX_BUF(Index); + for (q = p; q != RT_NULL; q= q->next) + { + memcpy(q->payload, ptr, q->len); + ptr += q->len; + } + } + + /* move Index to the next */ + if(++Index > LPC_EMAC->RxDescriptorNumber) + Index = 0; + + /* set consume index */ + LPC_EMAC->RxConsumeIndex = Index; + } + else + { + /* Enable RxDone interrupt */ + LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; + } + + /* unlock EMAC device */ + rt_sem_release(&sem_lock); + + return p; } void lpc17xx_emac_hw_init(void) { - rt_event_init(&tx_event, "tx_event", RT_IPC_FLAG_FIFO); - rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO); - - /* set autonegotiation mode */ - lpc17xx_emac_device.phy_mode = EMAC_PHY_AUTO; - - // OUI 00-60-37 NXP Semiconductors - lpc17xx_emac_device.dev_addr[0] = 0x00; - lpc17xx_emac_device.dev_addr[1] = 0x60; - lpc17xx_emac_device.dev_addr[2] = 0x37; - /* set mac address: (only for test) */ - lpc17xx_emac_device.dev_addr[3] = 0x12; - lpc17xx_emac_device.dev_addr[4] = 0x34; - lpc17xx_emac_device.dev_addr[5] = 0x56; - - lpc17xx_emac_device.parent.parent.init = lpc17xx_emac_init; - lpc17xx_emac_device.parent.parent.open = lpc17xx_emac_open; - lpc17xx_emac_device.parent.parent.close = lpc17xx_emac_close; - lpc17xx_emac_device.parent.parent.read = lpc17xx_emac_read; - lpc17xx_emac_device.parent.parent.write = lpc17xx_emac_write; - lpc17xx_emac_device.parent.parent.control = lpc17xx_emac_control; - lpc17xx_emac_device.parent.parent.user_data = RT_NULL; - - lpc17xx_emac_device.parent.eth_rx = lpc17xx_emac_rx; - lpc17xx_emac_device.parent.eth_tx = lpc17xx_emac_tx; - - eth_device_init(&(lpc17xx_emac_device.parent), "e0"); + rt_event_init(&tx_event, "tx_event", RT_IPC_FLAG_FIFO); + rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO); + + /* set autonegotiation mode */ + lpc17xx_emac_device.phy_mode = EMAC_PHY_AUTO; + + // OUI 00-60-37 NXP Semiconductors + lpc17xx_emac_device.dev_addr[0] = 0x00; + lpc17xx_emac_device.dev_addr[1] = 0x60; + lpc17xx_emac_device.dev_addr[2] = 0x37; + /* set mac address: (only for test) */ + lpc17xx_emac_device.dev_addr[3] = 0x12; + lpc17xx_emac_device.dev_addr[4] = 0x34; + lpc17xx_emac_device.dev_addr[5] = 0x56; + + lpc17xx_emac_device.parent.parent.init = lpc17xx_emac_init; + lpc17xx_emac_device.parent.parent.open = lpc17xx_emac_open; + lpc17xx_emac_device.parent.parent.close = lpc17xx_emac_close; + lpc17xx_emac_device.parent.parent.read = lpc17xx_emac_read; + lpc17xx_emac_device.parent.parent.write = lpc17xx_emac_write; + lpc17xx_emac_device.parent.parent.control = lpc17xx_emac_control; + lpc17xx_emac_device.parent.parent.user_data = RT_NULL; + + lpc17xx_emac_device.parent.eth_rx = lpc17xx_emac_rx; + lpc17xx_emac_device.parent.eth_tx = lpc17xx_emac_tx; + + eth_device_init(&(lpc17xx_emac_device.parent), "e0"); } #ifdef RT_USING_FINSH #include void emac_dump() { - rt_kprintf("Command : %08x\n", LPC_EMAC->Command); - rt_kprintf("Status : %08x\n", LPC_EMAC->Status); - rt_kprintf("RxStatus : %08x\n", LPC_EMAC->RxStatus); - rt_kprintf("TxStatus : %08x\n", LPC_EMAC->TxStatus); - rt_kprintf("IntEnable: %08x\n", LPC_EMAC->IntEnable); - rt_kprintf("IntStatus: %08x\n", LPC_EMAC->IntStatus); + rt_kprintf("Command : %08x\n", LPC_EMAC->Command); + rt_kprintf("Status : %08x\n", LPC_EMAC->Status); + rt_kprintf("RxStatus : %08x\n", LPC_EMAC->RxStatus); + rt_kprintf("TxStatus : %08x\n", LPC_EMAC->TxStatus); + rt_kprintf("IntEnable: %08x\n", LPC_EMAC->IntEnable); + rt_kprintf("IntStatus: %08x\n", LPC_EMAC->IntStatus); } FINSH_FUNCTION_EXPORT(emac_dump, dump emac register); #endif diff --git a/bsp/lpc178x/drivers/lpc17xx_lcd.c b/bsp/lpc178x/drivers/lpc17xx_lcd.c index cc488dfebb..f8f405a540 100644 --- a/bsp/lpc178x/drivers/lpc17xx_lcd.c +++ b/bsp/lpc178x/drivers/lpc17xx_lcd.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,8 +13,8 @@ #include "drv_glcd.h" -#define RT_HW_LCD_WIDTH 480 -#define RT_HW_LCD_HEIGHT 272 +#define RT_HW_LCD_WIDTH 480 +#define RT_HW_LCD_HEIGHT 272 static struct rt_device_graphic_info _lcd_info; static struct rt_device lcd; @@ -23,38 +23,38 @@ static struct rt_device lcd; static rt_err_t rt_lcd_init (rt_device_t dev) { PINSEL_ConfigPin(5, 4, 0); - LPC_GPIO5->DIR |= 1<<4; - LPC_GPIO5->CLR = 1<<4; - LPC_GPIO5->SET = 1<<4; - - /*Disable LCD controller*/ - GLCD_Ctrl (FALSE); - /*Init LCD and copy picture in video RAM*/ - GLCD_Init (_lcd_info.framebuffer); - /*Enable LCD*/ - GLCD_Ctrl (TRUE); - - return RT_EOK; + LPC_GPIO5->DIR |= 1<<4; + LPC_GPIO5->CLR = 1<<4; + LPC_GPIO5->SET = 1<<4; + + /*Disable LCD controller*/ + GLCD_Ctrl (FALSE); + /*Init LCD and copy picture in video RAM*/ + GLCD_Init (_lcd_info.framebuffer); + /*Enable LCD*/ + GLCD_Ctrl (TRUE); + + return RT_EOK; } static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args) { - switch (cmd) - { - case RTGRAPHIC_CTRL_RECT_UPDATE: - break; - case RTGRAPHIC_CTRL_POWERON: - break; - case RTGRAPHIC_CTRL_POWEROFF: - break; - case RTGRAPHIC_CTRL_GET_INFO: - rt_memcpy(args, &_lcd_info, sizeof(_lcd_info)); - break; - case RTGRAPHIC_CTRL_SET_MODE: - break; - } - - return RT_EOK; + switch (cmd) + { + case RTGRAPHIC_CTRL_RECT_UPDATE: + break; + case RTGRAPHIC_CTRL_POWERON: + break; + case RTGRAPHIC_CTRL_POWEROFF: + break; + case RTGRAPHIC_CTRL_GET_INFO: + rt_memcpy(args, &_lcd_info, sizeof(_lcd_info)); + break; + case RTGRAPHIC_CTRL_SET_MODE: + break; + } + + return RT_EOK; } @@ -63,27 +63,27 @@ void rt_hw_lcd_init(void) { rt_uint16_t * _rt_framebuffer = RT_NULL; - // _rt_framebuffer = rt_malloc_align(sizeof(rt_uint16_t)*RT_HW_LCD_HEIGHT*RT_HW_LCD_WIDTH, 8); - // if (_rt_framebuffer == RT_NULL) return; /* no memory yet */ + // _rt_framebuffer = rt_malloc_align(sizeof(rt_uint16_t)*RT_HW_LCD_HEIGHT*RT_HW_LCD_WIDTH, 8); + // if (_rt_framebuffer == RT_NULL) return; /* no memory yet */ - _rt_framebuffer = (rt_uint16_t *)0xA0000000; + _rt_framebuffer = (rt_uint16_t *)0xA0000000; - _lcd_info.bits_per_pixel = 16; - _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565; - _lcd_info.framebuffer = (void*)_rt_framebuffer; - _lcd_info.width = RT_HW_LCD_WIDTH; - _lcd_info.height = RT_HW_LCD_HEIGHT; + _lcd_info.bits_per_pixel = 16; + _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565; + _lcd_info.framebuffer = (void*)_rt_framebuffer; + _lcd_info.width = RT_HW_LCD_WIDTH; + _lcd_info.height = RT_HW_LCD_HEIGHT; - /* init device structure */ - lcd.type = RT_Device_Class_Graphic; - lcd.init = rt_lcd_init; - lcd.open = RT_NULL; - lcd.close = RT_NULL; - lcd.control = rt_lcd_control; - lcd.user_data = (void*)&_lcd_info; + /* init device structure */ + lcd.type = RT_Device_Class_Graphic; + lcd.init = rt_lcd_init; + lcd.open = RT_NULL; + lcd.close = RT_NULL; + lcd.control = rt_lcd_control; + lcd.user_data = (void*)&_lcd_info; - /* register lcd device to RT-Thread */ - rt_device_register(&lcd, "lcd", RT_DEVICE_FLAG_RDWR); + /* register lcd device to RT-Thread */ + rt_device_register(&lcd, "lcd", RT_DEVICE_FLAG_RDWR); } void lcd_fill(uint8_t * start, uint8_t * end, uint8_t pixel) diff --git a/bsp/lpc178x/drivers/uart.c b/bsp/lpc178x/drivers/uart.c index 0d92eb1fca..cb8e68d30c 100644 --- a/bsp/lpc178x/drivers/uart.c +++ b/bsp/lpc178x/drivers/uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -25,14 +25,14 @@ struct rt_uart_lpc { - struct rt_device parent; + struct rt_device parent; - LPC_UART_TypeDef * UART; - IRQn_Type UART_IRQn; + LPC_UART_TypeDef * UART; + IRQn_Type UART_IRQn; - /* buffer for reception */ - rt_uint8_t read_index, save_index; - rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; + /* buffer for reception */ + rt_uint8_t read_index, save_index; + rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; }; #ifdef RT_USING_UART0 @@ -45,96 +45,96 @@ struct rt_uart_lpc uart1_device; #ifdef RT_USING_UART0 void UART0_IRQHandler(void) { - rt_ubase_t level, iir; + rt_ubase_t level, iir; struct rt_uart_lpc* uart = &uart0_device; - /* enter interrupt */ - rt_interrupt_enter(); + /* enter interrupt */ + rt_interrupt_enter(); /* read IIR and clear it */ - iir = uart->UART->IIR; + iir = uart->UART->IIR; - if (iir == UART_IIR_INTID_RDA) /* Receive Data Available */ - { - /* Receive Data Available */ + if (iir == UART_IIR_INTID_RDA) /* Receive Data Available */ + { + /* Receive Data Available */ uart->rx_buffer[uart->save_index] = uart->UART->RBR; level = rt_hw_interrupt_disable(); - uart->save_index ++; + uart->save_index ++; if (uart->save_index >= RT_UART_RX_BUFFER_SIZE) uart->save_index = 0; rt_hw_interrupt_enable(level); - /* invoke callback */ - if(uart->parent.rx_indicate != RT_NULL) - { - rt_size_t length; - if (uart->read_index > uart->save_index) + /* invoke callback */ + if(uart->parent.rx_indicate != RT_NULL) + { + rt_size_t length; + if (uart->read_index > uart->save_index) length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index; else length = uart->save_index - uart->read_index; uart->parent.rx_indicate(&uart->parent, length); - } - } + } + } - /* leave interrupt */ - rt_interrupt_leave(); + /* leave interrupt */ + rt_interrupt_leave(); - return; + return; } #endif #ifdef RT_USING_UART1 void UART1_IRQHandler(void) { - rt_ubase_t level, iir; + rt_ubase_t level, iir; struct rt_uart_lpc* uart = &uart1_device; - /* enter interrupt */ - rt_interrupt_enter(); + /* enter interrupt */ + rt_interrupt_enter(); /* read IIR and clear it */ - iir = uart->UART->IIR; + iir = uart->UART->IIR; - if (iir == UART_IIR_INTID_RDA) /* Receive Data Available */ - { - /* Receive Data Available */ + if (iir == UART_IIR_INTID_RDA) /* Receive Data Available */ + { + /* Receive Data Available */ uart->rx_buffer[uart->save_index] = uart->UART->RBR; level = rt_hw_interrupt_disable(); - uart->save_index ++; + uart->save_index ++; if (uart->save_index >= RT_UART_RX_BUFFER_SIZE) uart->save_index = 0; rt_hw_interrupt_enable(level); - /* invoke callback */ - if(uart->parent.rx_indicate != RT_NULL) - { - rt_size_t length; - if (uart->read_index > uart->save_index) + /* invoke callback */ + if(uart->parent.rx_indicate != RT_NULL) + { + rt_size_t length; + if (uart->read_index > uart->save_index) length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index; else length = uart->save_index - uart->read_index; uart->parent.rx_indicate(&uart->parent, length); - } - } + } + } - /* leave interrupt */ - rt_interrupt_leave(); + /* leave interrupt */ + rt_interrupt_leave(); - return; + return; } #endif static rt_err_t rt_uart_init (rt_device_t dev) { - struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev; - UART_CFG_Type UART_ConfigStruct; + struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev; + UART_CFG_Type UART_ConfigStruct; #ifdef RT_USING_UART0 - if( uart->UART == LPC_UART0 ) + if( uart->UART == LPC_UART0 ) { /* * Initialize UART0 pin connect @@ -184,170 +184,170 @@ static rt_err_t rt_uart_init (rt_device_t dev) #endif #ifdef RT_USING_UART2 - if( uart->UART == LPC_UART2 ) + if( uart->UART == LPC_UART2 ) { } #endif - return RT_EOK; + return RT_EOK; } static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag) { struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev; - RT_ASSERT(dev != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* Enable the UART Interrupt */ - NVIC_EnableIRQ( uart->UART_IRQn ); - } + RT_ASSERT(dev != RT_NULL); + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* Enable the UART Interrupt */ + NVIC_EnableIRQ( uart->UART_IRQn ); + } - return RT_EOK; + return RT_EOK; } static rt_err_t rt_uart_close(rt_device_t dev) { struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev; - RT_ASSERT(dev != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* Disable the UART Interrupt */ - NVIC_DisableIRQ( uart->UART_IRQn ); - } + RT_ASSERT(dev != RT_NULL); + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* Disable the UART Interrupt */ + NVIC_DisableIRQ( uart->UART_IRQn ); + } - return RT_EOK; + return RT_EOK; } static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev; - RT_ASSERT(uart != RT_NULL); - - /* point to buffer */ - ptr = (rt_uint8_t*) buffer; - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - while (size) - { - /* interrupt receive */ - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - if (uart->read_index != uart->save_index) - { - *ptr = uart->rx_buffer[uart->read_index]; - - uart->read_index ++; - if (uart->read_index >= RT_UART_RX_BUFFER_SIZE) - uart->read_index = 0; - } - else - { - /* no data in rx buffer */ - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - break; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - - ptr ++; - size --; - } - - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; - } - - return 0; + rt_uint8_t* ptr; + struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev; + RT_ASSERT(uart != RT_NULL); + + /* point to buffer */ + ptr = (rt_uint8_t*) buffer; + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + while (size) + { + /* interrupt receive */ + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + if (uart->read_index != uart->save_index) + { + *ptr = uart->rx_buffer[uart->read_index]; + + uart->read_index ++; + if (uart->read_index >= RT_UART_RX_BUFFER_SIZE) + uart->read_index = 0; + } + else + { + /* no data in rx buffer */ + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + ptr ++; + size --; + } + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + } + + return 0; } static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev; - char *ptr; - ptr = (char*)buffer; - - if (dev->flag & RT_DEVICE_FLAG_STREAM) - { - /* stream mode */ - while (size) - { - if (*ptr == '\n') - { - while (!(uart->UART->LSR & UART_LSR_THRE)); + struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev; + char *ptr; + ptr = (char*)buffer; + + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* stream mode */ + while (size) + { + if (*ptr == '\n') + { + while (!(uart->UART->LSR & UART_LSR_THRE)); UART_SendByte( uart->UART,'\r'); - } - - while (!(uart->UART->LSR & UART_LSR_THRE)); - UART_SendByte( uart->UART,*ptr); - ptr ++; - size --; - } - } - else - { + } + + while (!(uart->UART->LSR & UART_LSR_THRE)); + UART_SendByte( uart->UART,*ptr); + ptr ++; + size --; + } + } + else + { UART_Send( uart->UART, (uint8_t *)buffer, size, BLOCKING); } - return (rt_size_t) ptr - (rt_size_t) buffer; + return (rt_size_t) ptr - (rt_size_t) buffer; } void rt_hw_uart_init(void) { - struct rt_uart_lpc* uart; + struct rt_uart_lpc* uart; #ifdef RT_USING_UART0 - /* get uart device */ - uart = &uart0_device; - uart0_device.UART = LPC_UART0; - uart0_device.UART_IRQn = UART0_IRQn; - - /* device initialization */ - uart->parent.type = RT_Device_Class_Char; - rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer)); - uart->read_index = uart->save_index = 0; - - /* device interface */ - uart->parent.init = rt_uart_init; - uart->parent.open = rt_uart_open; - uart->parent.close = rt_uart_close; - uart->parent.read = rt_uart_read; - uart->parent.write = rt_uart_write; - uart->parent.control = RT_NULL; - uart->parent.user_data = RT_NULL; - - rt_device_register(&uart->parent, - "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX); + /* get uart device */ + uart = &uart0_device; + uart0_device.UART = LPC_UART0; + uart0_device.UART_IRQn = UART0_IRQn; + + /* device initialization */ + uart->parent.type = RT_Device_Class_Char; + rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer)); + uart->read_index = uart->save_index = 0; + + /* device interface */ + uart->parent.init = rt_uart_init; + uart->parent.open = rt_uart_open; + uart->parent.close = rt_uart_close; + uart->parent.read = rt_uart_read; + uart->parent.write = rt_uart_write; + uart->parent.control = RT_NULL; + uart->parent.user_data = RT_NULL; + + rt_device_register(&uart->parent, + "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX); #endif #ifdef RT_USING_UART1 - /* get uart device */ - uart = &uart1_device; - uart1_device.UART = (LPC_UART_TypeDef *)LPC_UART1; - uart1_device.UART_IRQn = UART1_IRQn; - - /* device initialization */ - uart->parent.type = RT_Device_Class_Char; - rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer)); - uart->read_index = uart->save_index = 0; - - /* device interface */ - uart->parent.init = rt_uart_init; - uart->parent.open = rt_uart_open; - uart->parent.close = rt_uart_close; - uart->parent.read = rt_uart_read; - uart->parent.write = rt_uart_write; - uart->parent.control = RT_NULL; - uart->parent.user_data = RT_NULL; - - rt_device_register(&uart->parent, - "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX); + /* get uart device */ + uart = &uart1_device; + uart1_device.UART = (LPC_UART_TypeDef *)LPC_UART1; + uart1_device.UART_IRQn = UART1_IRQn; + + /* device initialization */ + uart->parent.type = RT_Device_Class_Char; + rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer)); + uart->read_index = uart->save_index = 0; + + /* device interface */ + uart->parent.init = rt_uart_init; + uart->parent.open = rt_uart_open; + uart->parent.close = rt_uart_close; + uart->parent.read = rt_uart_read; + uart->parent.write = rt_uart_write; + uart->parent.control = RT_NULL; + uart->parent.user_data = RT_NULL; + + rt_device_register(&uart->parent, + "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX); #endif } diff --git a/bsp/lpc178x/rtconfig.h b/bsp/lpc178x/rtconfig.h index 25f99888f7..ce51ba355f 100644 --- a/bsp/lpc178x/rtconfig.h +++ b/bsp/lpc178x/rtconfig.h @@ -5,17 +5,17 @@ // // -#define RT_NAME_MAX 6 +#define RT_NAME_MAX 6 // -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 // // 8 // 32 // 256 // -#define RT_THREAD_PRIORITY_MAX 32 +#define RT_THREAD_PRIORITY_MAX 32 // -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 //
#define RT_DEBUG #define RT_DEBUG_COLOR @@ -30,11 +30,11 @@ //
// #define RT_USING_TIMER_SOFT // -#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_PRIO 4 // -#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_THREAD_STACK_SIZE 512 // -#define RT_TIMER_TICK_PER_SECOND 10 +#define RT_TIMER_TICK_PER_SECOND 10 //
//
@@ -66,13 +66,13 @@ //
#define RT_USING_DEVICE // -#define RT_UART_RX_BUFFER_SIZE 64 +#define RT_UART_RX_BUFFER_SIZE 64 //
//
#define RT_USING_CONSOLE // -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 //
// @@ -84,7 +84,7 @@ // #define FINSH_USING_DESCRIPTION // -#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_THREAD_STACK_SIZE 4096 //
//
@@ -99,18 +99,18 @@ // // #define DFS_USING_WORKDIR // -#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEMS_MAX 2 // -#define DFS_FD_MAX 4 +#define DFS_FD_MAX 4 // #define RT_USING_DFS_ELMFAT // // 1 // 2 // -#define RT_DFS_ELM_USE_LFN 1 +#define RT_DFS_ELM_USE_LFN 1 // -#define RT_DFS_ELM_MAX_LFN 64 +#define RT_DFS_ELM_MAX_LFN 64 // // #define RT_USING_DFS_YAFFS2 // @@ -120,7 +120,7 @@ // // #define RT_USING_DFS_NFS // -#define RT_NFS_HOST_EXPORT "192.168.1.5:/" +#define RT_NFS_HOST_EXPORT "192.168.1.5:/" //
//
@@ -136,31 +136,31 @@ // #define RT_LWIP_DNS // -#define RT_LWIP_PBUF_NUM 4 +#define RT_LWIP_PBUF_NUM 4 // -#define RT_LWIP_TCP_PCB_NUM 3 +#define RT_LWIP_TCP_PCB_NUM 3 // -#define RT_LWIP_TCP_SND_BUF 2048 +#define RT_LWIP_TCP_SND_BUF 2048 // -#define RT_LWIP_TCP_WND 2048 +#define RT_LWIP_TCP_WND 2048 // // #define RT_LWIP_SNMP // // #define RT_LWIP_DHCP // -#define RT_LWIP_TCP_SEG_NUM 4 +#define RT_LWIP_TCP_SEG_NUM 4 // -#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 // -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 // -#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 +#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 // -#define RT_LWIP_ETHTHREAD_PRIORITY 14 +#define RT_LWIP_ETHTHREAD_PRIORITY 14 // -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 // -#define RT_LWIP_ETHTHREAD_STACKSIZE 512 +#define RT_LWIP_ETHTHREAD_STACKSIZE 512 // #define RT_LWIP_IPADDR0 192 #define RT_LWIP_IPADDR1 168 @@ -181,7 +181,7 @@ //
// #define RT_USING_RTGUI // -#define RTGUI_NAME_MAX 12 +#define RTGUI_NAME_MAX 12 // #define RTGUI_USING_SMALL_SIZE // @@ -191,7 +191,7 @@ // #define RTGUI_USING_FONTHZ // -#define RTGUI_DEFAULT_FONT_SIZE 16 +#define RTGUI_DEFAULT_FONT_SIZE 16 // // #define RTGUI_USING_DFS_FILERW // diff --git a/bsp/lpc2148/applications/application.c b/bsp/lpc2148/applications/application.c index fd07f22f05..731b30a510 100644 --- a/bsp/lpc2148/applications/application.c +++ b/bsp/lpc2148/applications/application.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc2148/applications/startup.c b/bsp/lpc2148/applications/startup.c index 5b699a8613..3b245604ee 100644 --- a/bsp/lpc2148/applications/startup.c +++ b/bsp/lpc2148/applications/startup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc2148/drivers/board.c b/bsp/lpc2148/drivers/board.c index 96a4aa62f4..757e1cb8f0 100644 --- a/bsp/lpc2148/drivers/board.c +++ b/bsp/lpc2148/drivers/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -25,13 +25,13 @@ */ void rt_hw_timer_handler(int vector, void *param) { - rt_tick_increase(); + rt_tick_increase(); - /* clear interrupt flag */ - T0IR |= 0x01; + /* clear interrupt flag */ + T0IR |= 0x01; - /* acknowledge Interrupt */ - VICVectAddr = 0; + /* acknowledge Interrupt */ + VICVectAddr = 0; } /** @@ -42,37 +42,37 @@ void rt_hw_timer_handler(int vector, void *param) */ void rt_hw_console_output(const char* str) { - while (*str) - { - if (*str=='\n') - { - while (!(U0LSR & 0x20)); - U0THR = '\r'; - } - - while (!(U0LSR & 0x20)); - U0THR = *str; - - str ++; - } + while (*str) + { + if (*str=='\n') + { + while (!(U0LSR & 0x20)); + U0THR = '\r'; + } + + while (!(U0LSR & 0x20)); + U0THR = *str; + + str ++; + } } -#define BAUD_RATE 115200 -#define U0PINS 0x05 +#define BAUD_RATE 115200 +#define U0PINS 0x05 void rt_hw_console_init() { - /* Enable RxD and TxD pins */ - PINSEL0 = U0PINS; + /* Enable RxD and TxD pins */ + PINSEL0 = U0PINS; - /* 8 bits, no Parity, 1 Stop bit */ - U0LCR = 0x83; + /* 8 bits, no Parity, 1 Stop bit */ + U0LCR = 0x83; - /* Setup Baudrate */ - U0DLL = (PCLK/16/BAUD_RATE) & 0xFF; - U0DLM = ((PCLK/16/BAUD_RATE) >> 8) & 0xFF; + /* Setup Baudrate */ + U0DLL = (PCLK/16/BAUD_RATE) & 0xFF; + U0DLM = ((PCLK/16/BAUD_RATE) >> 8) & 0xFF; - /* DLAB = 0 */ - U0LCR = 0x03; + /* DLAB = 0 */ + U0LCR = 0x03; } /** @@ -80,23 +80,23 @@ void rt_hw_console_init() */ void rt_hw_board_init(void) { - /* console init */ - rt_hw_console_init(); + /* console init */ + rt_hw_console_init(); - /* prescaler = 0*/ - T0PR = 0; - T0PC = 0; + /* prescaler = 0*/ + T0PR = 0; + T0PC = 0; - /* reset and enable MR0 interrupt */ - T0MCR = 0x3; - T0MR0 = PCLK / RT_TICK_PER_SECOND; + /* reset and enable MR0 interrupt */ + T0MCR = 0x3; + T0MR0 = PCLK / RT_TICK_PER_SECOND; - /* enable timer 0 */ - T0TCR = 1; + /* enable timer 0 */ + T0TCR = 1; - /* install timer handler */ - rt_hw_interrupt_install(TIMER0_INT, rt_hw_timer_handler, RT_NULL, "TIMER0"); - rt_hw_interrupt_umask(TIMER0_INT); + /* install timer handler */ + rt_hw_interrupt_install(TIMER0_INT, rt_hw_timer_handler, RT_NULL, "TIMER0"); + rt_hw_interrupt_umask(TIMER0_INT); } /*@}*/ diff --git a/bsp/lpc2148/drivers/board.h b/bsp/lpc2148/drivers/board.h index 346f10182f..957f360652 100644 --- a/bsp/lpc2148/drivers/board.h +++ b/bsp/lpc2148/drivers/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,13 +12,13 @@ #define __BOARD_H__ #include -#define CCLK 60000000 /* Fosc = 12MHz, M = 5 */ -#define PCLK 15000000 /* CCLK/4, use default */ +#define CCLK 60000000 /* Fosc = 12MHz, M = 5 */ +#define PCLK 15000000 /* CCLK/4, use default */ /* RT_USING_UART */ #define RT_USING_UART1 #define RT_USING_UART2 -#define RT_UART_RX_BUFFER_SIZE 64 +#define RT_UART_RX_BUFFER_SIZE 64 void rt_hw_board_init(void); diff --git a/bsp/lpc2148/drivers/dm9000.c b/bsp/lpc2148/drivers/dm9000.c index 169be59f12..9bc8d445f9 100644 --- a/bsp/lpc2148/drivers/dm9000.c +++ b/bsp/lpc2148/drivers/dm9000.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,11 +15,11 @@ #define MAX_ADDR_LEN 6 struct rt_dm9000_eth { - /* inherit from ethernet device */ - struct eth_device parent; + /* inherit from ethernet device */ + struct eth_device parent; - /* interface address info. */ - rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ + /* interface address info. */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ }; static struct rt_dm9000_eth dm9000_device; @@ -52,67 +52,67 @@ static rt_err_t rt_dm9000_init(rt_device_t dev) static rt_err_t rt_dm9000_open(rt_device_t dev, rt_uint16_t oflag) { - return RT_EOK; + return RT_EOK; } static rt_err_t rt_dm9000_close(rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_size_t rt_dm9000_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_size_t rt_dm9000_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_err_t rt_dm9000_control(rt_device_t dev, int cmd, void *args) { - switch(cmd) - { - case NIOCTL_GADDR: - /* get mac address */ - if(args) rt_memcpy(args, dm9000_device.dev_addr, 6); - else return -RT_ERROR; - break; - - default : - break; - } - - return RT_EOK; + switch(cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if(args) rt_memcpy(args, dm9000_device.dev_addr, 6); + else return -RT_ERROR; + break; + + default : + break; + } + + return RT_EOK; } /* ethernet device interface */ /* transmit packet. */ rt_err_t rt_dm9000_tx( rt_device_t dev, struct pbuf* p) { - struct pbuf* q; - rt_uint32_t len; - rt_uint8_t* ptr; + struct pbuf* q; + rt_uint32_t len; + rt_uint8_t* ptr; - for (q = p; q != NULL; q = q->next) - { - len = q->len; - ptr = q->payload; + for (q = p; q != NULL; q = q->next) + { + len = q->len; + ptr = q->payload; - /* write data to device */ - } + /* write data to device */ + } - return RT_EOK; + return RT_EOK; } /* reception packet. */ struct pbuf *rt_dm9000_rx(rt_device_t dev) { struct pbuf* p; - rt_uint32_t len; + rt_uint32_t len; /* init p pointer */ p = RT_NULL; @@ -149,17 +149,17 @@ struct pbuf *rt_dm9000_rx(rt_device_t dev) void rt_hw_dm9000_init() { - dm9000_device.parent.parent.init = rt_dm9000_init; - dm9000_device.parent.parent.open = rt_dm9000_open; - dm9000_device.parent.parent.close = rt_dm9000_close; - dm9000_device.parent.parent.read = rt_dm9000_read; - dm9000_device.parent.parent.write = rt_dm9000_write; - dm9000_device.parent.parent.control = rt_dm9000_control; - dm9000_device.parent.parent.user_data = RT_NULL; - - dm9000_device.parent.eth_rx = rt_dm9000_rx; - dm9000_device.parent.eth_tx = rt_dm9000_tx; - - rt_device_register((rt_device_t)&dm9000_device, - "E0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_INT_TX); + dm9000_device.parent.parent.init = rt_dm9000_init; + dm9000_device.parent.parent.open = rt_dm9000_open; + dm9000_device.parent.parent.close = rt_dm9000_close; + dm9000_device.parent.parent.read = rt_dm9000_read; + dm9000_device.parent.parent.write = rt_dm9000_write; + dm9000_device.parent.parent.control = rt_dm9000_control; + dm9000_device.parent.parent.user_data = RT_NULL; + + dm9000_device.parent.eth_rx = rt_dm9000_rx; + dm9000_device.parent.eth_tx = rt_dm9000_tx; + + rt_device_register((rt_device_t)&dm9000_device, + "E0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_INT_TX); } diff --git a/bsp/lpc2148/drivers/sd.c b/bsp/lpc2148/drivers/sd.c index d7b6769621..144c9f2ff5 100644 --- a/bsp/lpc2148/drivers/sd.c +++ b/bsp/lpc2148/drivers/sd.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,12 +22,12 @@ static rt_err_t rt_sdcard_init(rt_device_t dev) static rt_err_t rt_sdcard_open(rt_device_t dev, rt_uint16_t oflag) { - return RT_EOK; + return RT_EOK; } static rt_err_t rt_sdcard_close(rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) @@ -48,54 +48,54 @@ static rt_size_t rt_sdcard_write (rt_device_t dev, rt_off_t pos, const void* buf static rt_err_t rt_sdcard_control(rt_device_t dev, int cmd, void *args) { - return RT_EOK; + return RT_EOK; } void rt_hw_sdcard_init() { rt_size_t length; - rt_uint8_t* sector; + rt_uint8_t* sector; /* sdcard hardware init */ - sd.type = RT_Device_Class_Block; - sd.init = rt_sdcard_init; - sd.open = rt_sdcard_open; - sd.close = rt_sdcard_close; - sd.read = rt_sdcard_read; - sd.write = rt_sdcard_write; - sd.control = rt_sdcard_control; - sd.user_data = RT_NULL; - - /* get the first sector to read partition table */ - sector = (rt_uint8_t*) rt_malloc (512); - if (sector == RT_NULL) - { - rt_kprintf("allocate partition sector buffer failed\n"); - return; - } - - length = rt_sdcard_read((rt_device_t)&sd, 0, sector, 512); - if (length == 512) - { - rt_err_t status; - - /* get the first partition */ - status = dfs_filesystem_get_partition(&part, sector, 0); - if (status != RT_EOK) - { - /* there is no partition table */ - part.offset = 0; - part.size = 0; - } - } - else - { - /* there is no partition table */ - part.offset = 0; - part.size = 0; - } - - rt_device_register(&sd, - "sd", RT_DEVICE_FLAG_RDWR); + sd.type = RT_Device_Class_Block; + sd.init = rt_sdcard_init; + sd.open = rt_sdcard_open; + sd.close = rt_sdcard_close; + sd.read = rt_sdcard_read; + sd.write = rt_sdcard_write; + sd.control = rt_sdcard_control; + sd.user_data = RT_NULL; + + /* get the first sector to read partition table */ + sector = (rt_uint8_t*) rt_malloc (512); + if (sector == RT_NULL) + { + rt_kprintf("allocate partition sector buffer failed\n"); + return; + } + + length = rt_sdcard_read((rt_device_t)&sd, 0, sector, 512); + if (length == 512) + { + rt_err_t status; + + /* get the first partition */ + status = dfs_filesystem_get_partition(&part, sector, 0); + if (status != RT_EOK) + { + /* there is no partition table */ + part.offset = 0; + part.size = 0; + } + } + else + { + /* there is no partition table */ + part.offset = 0; + part.size = 0; + } + + rt_device_register(&sd, + "sd", RT_DEVICE_FLAG_RDWR); } diff --git a/bsp/lpc2148/drivers/serial.c b/bsp/lpc2148/drivers/serial.c index 0c78ecc026..36bbcbd608 100644 --- a/bsp/lpc2148/drivers/serial.c +++ b/bsp/lpc2148/drivers/serial.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,8 +15,8 @@ #include "board.h" /* serial hardware register */ -#define REG8(d) (*((volatile unsigned char *)(d))) -#define REG32(d) (*((volatile unsigned long *)(d))) +#define REG8(d) (*((volatile unsigned char *)(d))) +#define REG32(d) (*((volatile unsigned long *)(d))) #define UART_RBR(base) REG8(base + 0x00) #define UART_THR(base) REG8(base + 0x00) @@ -37,16 +37,16 @@ /* LPC serial device */ struct rt_lpcserial { - /* inherit from device */ - struct rt_device parent; + /* inherit from device */ + struct rt_device parent; - rt_uint32_t hw_base; - rt_uint32_t irqno; - rt_uint32_t baudrate; + rt_uint32_t hw_base; + rt_uint32_t irqno; + rt_uint32_t baudrate; - /* reception field */ - rt_uint16_t save_index, read_index; - rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; + /* reception field */ + rt_uint16_t save_index, read_index; + rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; }; #ifdef RT_USING_UART1 @@ -58,70 +58,70 @@ struct rt_lpcserial serial2; void rt_hw_serial_init(void); -#define U0PINS 0x00000005 +#define U0PINS 0x00000005 void rt_hw_uart_isr(struct rt_lpcserial* lpc_serial) { - RT_UNUSED rt_uint32_t iir; - - RT_ASSERT(lpc_serial != RT_NULL) - - if (UART_LSR(lpc_serial->hw_base) & 0x01) - { - rt_base_t level; - - while (UART_LSR(lpc_serial->hw_base) & 0x01) - { - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - /* read character */ - lpc_serial->rx_buffer[lpc_serial->save_index] = - UART_RBR(lpc_serial->hw_base); - lpc_serial->save_index ++; - if (lpc_serial->save_index >= RT_UART_RX_BUFFER_SIZE) - lpc_serial->save_index = 0; - - /* if the next position is read index, discard this 'read char' */ - if (lpc_serial->save_index == lpc_serial->read_index) - { - lpc_serial->read_index ++; - if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE) - lpc_serial->read_index = 0; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } - - /* invoke callback */ - if(lpc_serial->parent.rx_indicate != RT_NULL) - { - lpc_serial->parent.rx_indicate(&lpc_serial->parent, 1); - } - } - - /* clear interrupt source */ - iir = UART_IIR(lpc_serial->hw_base); - - /* acknowledge Interrupt */ - VICVectAddr = 0; + RT_UNUSED rt_uint32_t iir; + + RT_ASSERT(lpc_serial != RT_NULL) + + if (UART_LSR(lpc_serial->hw_base) & 0x01) + { + rt_base_t level; + + while (UART_LSR(lpc_serial->hw_base) & 0x01) + { + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + /* read character */ + lpc_serial->rx_buffer[lpc_serial->save_index] = + UART_RBR(lpc_serial->hw_base); + lpc_serial->save_index ++; + if (lpc_serial->save_index >= RT_UART_RX_BUFFER_SIZE) + lpc_serial->save_index = 0; + + /* if the next position is read index, discard this 'read char' */ + if (lpc_serial->save_index == lpc_serial->read_index) + { + lpc_serial->read_index ++; + if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE) + lpc_serial->read_index = 0; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + + /* invoke callback */ + if(lpc_serial->parent.rx_indicate != RT_NULL) + { + lpc_serial->parent.rx_indicate(&lpc_serial->parent, 1); + } + } + + /* clear interrupt source */ + iir = UART_IIR(lpc_serial->hw_base); + + /* acknowledge Interrupt */ + VICVectAddr = 0; } #ifdef RT_USING_UART1 void rt_hw_uart_isr_1(int irqno, void *param) { - /* get lpc serial device */ - rt_hw_uart_isr(&serial1); -} + /* get lpc serial device */ + rt_hw_uart_isr(&serial1); +} #endif #ifdef RT_USING_UART2 void rt_hw_uart_isr_2(int irqno, void *param) { - /* get lpc serial device */ - rt_hw_uart_isr(&serial2); -} + /* get lpc serial device */ + rt_hw_uart_isr(&serial2); +} #endif /** @@ -131,256 +131,256 @@ void rt_hw_uart_isr_2(int irqno, void *param) static rt_err_t rt_serial_init (rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) { - struct rt_lpcserial* lpc_serial; - lpc_serial = (struct rt_lpcserial*) dev; - - RT_ASSERT(lpc_serial != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* init UART rx interrupt */ - UART_IER(lpc_serial->hw_base) = 0x01; - - /* install ISR */ - if (lpc_serial->irqno == UART0_INT) - { + struct rt_lpcserial* lpc_serial; + lpc_serial = (struct rt_lpcserial*) dev; + + RT_ASSERT(lpc_serial != RT_NULL); + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* init UART rx interrupt */ + UART_IER(lpc_serial->hw_base) = 0x01; + + /* install ISR */ + if (lpc_serial->irqno == UART0_INT) + { #ifdef RT_USING_UART1 - rt_hw_interrupt_install(lpc_serial->irqno, + rt_hw_interrupt_install(lpc_serial->irqno, rt_hw_uart_isr_1, &serial1, "UART1"); #endif - } - else - { + } + else + { #ifdef RT_USING_UART2 - rt_hw_interrupt_install(lpc_serial->irqno, + rt_hw_interrupt_install(lpc_serial->irqno, rt_hw_uart_isr_2, &serial2, "UART2"); #endif - } + } - rt_hw_interrupt_umask(lpc_serial->irqno); - } + rt_hw_interrupt_umask(lpc_serial->irqno); + } - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_close(rt_device_t dev) { - struct rt_lpcserial* lpc_serial; - lpc_serial = (struct rt_lpcserial*) dev; + struct rt_lpcserial* lpc_serial; + lpc_serial = (struct rt_lpcserial*) dev; - RT_ASSERT(lpc_serial != RT_NULL); + RT_ASSERT(lpc_serial != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* disable UART rx interrupt */ - UART_IER(lpc_serial->hw_base) = 0x00; - } + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* disable UART rx interrupt */ + UART_IER(lpc_serial->hw_base) = 0x00; + } - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_control(rt_device_t dev, int cmd, void *args) { - return RT_EOK; + return RT_EOK; } static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - struct rt_lpcserial *lpc_serial = (struct rt_lpcserial*)dev; - RT_ASSERT(lpc_serial != RT_NULL); - - /* point to buffer */ - ptr = (rt_uint8_t*) buffer; - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - while (size) - { - /* interrupt receive */ - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - if (lpc_serial->read_index != lpc_serial->save_index) - { - *ptr = lpc_serial->rx_buffer[lpc_serial->read_index]; - - lpc_serial->read_index ++; - if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE) - lpc_serial->read_index = 0; - } - else - { - /* no data in rx buffer */ - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - break; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - - ptr ++; size --; - } - - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; - } - else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) - { - /* not support right now */ - RT_ASSERT(0); - } - - /* polling mode */ - while (size && (UART_LSR(lpc_serial->hw_base) & 0x01)) - { - /* Read Character */ - *ptr = UART_RBR(lpc_serial->hw_base); - - ptr ++; - size --; - } - - return (rt_size_t)ptr - (rt_size_t)buffer; + rt_uint8_t* ptr; + struct rt_lpcserial *lpc_serial = (struct rt_lpcserial*)dev; + RT_ASSERT(lpc_serial != RT_NULL); + + /* point to buffer */ + ptr = (rt_uint8_t*) buffer; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + while (size) + { + /* interrupt receive */ + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + if (lpc_serial->read_index != lpc_serial->save_index) + { + *ptr = lpc_serial->rx_buffer[lpc_serial->read_index]; + + lpc_serial->read_index ++; + if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE) + lpc_serial->read_index = 0; + } + else + { + /* no data in rx buffer */ + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + ptr ++; size --; + } + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) + { + /* not support right now */ + RT_ASSERT(0); + } + + /* polling mode */ + while (size && (UART_LSR(lpc_serial->hw_base) & 0x01)) + { + /* Read Character */ + *ptr = UART_RBR(lpc_serial->hw_base); + + ptr ++; + size --; + } + + return (rt_size_t)ptr - (rt_size_t)buffer; } static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - struct rt_lpcserial* lpc_serial; - char *ptr; - - lpc_serial = (struct rt_lpcserial*) dev; - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - /* not support */ - RT_ASSERT(0); - } - else if (dev->flag & RT_DEVICE_FLAG_DMA_TX) - { - /* not support */ - RT_ASSERT(0); - } - - /* polling write */ - ptr = (char *)buffer; - - if (dev->flag & RT_DEVICE_FLAG_STREAM) - { - /* stream mode */ - while (size) - { - if (*ptr == '\n') - { - while (!(UART_LSR(lpc_serial->hw_base) & 0x20)); - UART_THR(lpc_serial->hw_base) = '\r'; - } - - while (!(UART_LSR(lpc_serial->hw_base) & 0x20)); - UART_THR(lpc_serial->hw_base) = *ptr; - - ptr ++; - size --; - } - } - else - { - while (size) - { - while (!(UART_LSR(lpc_serial->hw_base) & 0x20)); - UART_THR(lpc_serial->hw_base) = *ptr; - - ptr ++; - size --; - } - } - - return (rt_size_t) ptr - (rt_size_t) buffer; + struct rt_lpcserial* lpc_serial; + char *ptr; + + lpc_serial = (struct rt_lpcserial*) dev; + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* not support */ + RT_ASSERT(0); + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_TX) + { + /* not support */ + RT_ASSERT(0); + } + + /* polling write */ + ptr = (char *)buffer; + + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* stream mode */ + while (size) + { + if (*ptr == '\n') + { + while (!(UART_LSR(lpc_serial->hw_base) & 0x20)); + UART_THR(lpc_serial->hw_base) = '\r'; + } + + while (!(UART_LSR(lpc_serial->hw_base) & 0x20)); + UART_THR(lpc_serial->hw_base) = *ptr; + + ptr ++; + size --; + } + } + else + { + while (size) + { + while (!(UART_LSR(lpc_serial->hw_base) & 0x20)); + UART_THR(lpc_serial->hw_base) = *ptr; + + ptr ++; + size --; + } + } + + return (rt_size_t) ptr - (rt_size_t) buffer; } void rt_hw_serial_init(void) { - struct rt_lpcserial* lpc_serial; + struct rt_lpcserial* lpc_serial; #ifdef RT_USING_UART1 - lpc_serial = &serial1; + lpc_serial = &serial1; - lpc_serial->parent.type = RT_Device_Class_Char; + lpc_serial->parent.type = RT_Device_Class_Char; - lpc_serial->hw_base = 0xE000C000; - lpc_serial->baudrate = 115200; - lpc_serial->irqno = UART0_INT; + lpc_serial->hw_base = 0xE000C000; + lpc_serial->baudrate = 115200; + lpc_serial->irqno = UART0_INT; - rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer)); - lpc_serial->read_index = lpc_serial->save_index = 0; + rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer)); + lpc_serial->read_index = lpc_serial->save_index = 0; - /* Enable UART0 RxD and TxD pins */ + /* Enable UART0 RxD and TxD pins */ PINSEL0 |= 0x05; - /* 8 bits, no Parity, 1 Stop bit */ - UART_LCR(lpc_serial->hw_base) = 0x83; + /* 8 bits, no Parity, 1 Stop bit */ + UART_LCR(lpc_serial->hw_base) = 0x83; - /* Setup Baudrate */ - UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF; - UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF; + /* Setup Baudrate */ + UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF; + UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF; - /* DLAB = 0 */ - UART_LCR(lpc_serial->hw_base) = 0x03; + /* DLAB = 0 */ + UART_LCR(lpc_serial->hw_base) = 0x03; - lpc_serial->parent.type = RT_Device_Class_Char; - lpc_serial->parent.init = rt_serial_init; - lpc_serial->parent.open = rt_serial_open; - lpc_serial->parent.close = rt_serial_close; - lpc_serial->parent.read = rt_serial_read; - lpc_serial->parent.write = rt_serial_write; - lpc_serial->parent.control = rt_serial_control; - lpc_serial->parent.user_data = RT_NULL; + lpc_serial->parent.type = RT_Device_Class_Char; + lpc_serial->parent.init = rt_serial_init; + lpc_serial->parent.open = rt_serial_open; + lpc_serial->parent.close = rt_serial_close; + lpc_serial->parent.read = rt_serial_read; + lpc_serial->parent.write = rt_serial_write; + lpc_serial->parent.control = rt_serial_control; + lpc_serial->parent.user_data = RT_NULL; - rt_device_register(&lpc_serial->parent, - "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); + rt_device_register(&lpc_serial->parent, + "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); #endif #ifdef RT_USING_UART2 - lpc_serial = &serial2; + lpc_serial = &serial2; - lpc_serial->parent.type = RT_Device_Class_Char; + lpc_serial->parent.type = RT_Device_Class_Char; - lpc_serial->hw_base = 0xE0010000; - lpc_serial->baudrate = 115200; - lpc_serial->irqno = UART1_INT; + lpc_serial->hw_base = 0xE0010000; + lpc_serial->baudrate = 115200; + lpc_serial->irqno = UART1_INT; - rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer)); - lpc_serial->read_index = lpc_serial->save_index = 0; + rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer)); + lpc_serial->read_index = lpc_serial->save_index = 0; - /* Enable UART1 RxD and TxD pins */ - PINSEL0 |= 0x05 << 16; + /* Enable UART1 RxD and TxD pins */ + PINSEL0 |= 0x05 << 16; - /* 8 bits, no Parity, 1 Stop bit */ - UART_LCR(lpc_serial->hw_base) = 0x83; + /* 8 bits, no Parity, 1 Stop bit */ + UART_LCR(lpc_serial->hw_base) = 0x83; - /* Setup Baudrate */ - UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF; - UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF; + /* Setup Baudrate */ + UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF; + UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF; - /* DLAB = 0 */ - UART_LCR(lpc_serial->hw_base) = 0x03; + /* DLAB = 0 */ + UART_LCR(lpc_serial->hw_base) = 0x03; - lpc_serial->parent.type = RT_Device_Class_Char; - lpc_serial->parent.init = rt_serial_init; - lpc_serial->parent.open = rt_serial_open; - lpc_serial->parent.close = rt_serial_close; - lpc_serial->parent.read = rt_serial_read; - lpc_serial->parent.write = rt_serial_write; - lpc_serial->parent.control = rt_serial_control; - lpc_serial->parent.user_data = RT_NULL; + lpc_serial->parent.type = RT_Device_Class_Char; + lpc_serial->parent.init = rt_serial_init; + lpc_serial->parent.open = rt_serial_open; + lpc_serial->parent.close = rt_serial_close; + lpc_serial->parent.read = rt_serial_read; + lpc_serial->parent.write = rt_serial_write; + lpc_serial->parent.control = rt_serial_control; + lpc_serial->parent.user_data = RT_NULL; - rt_device_register(&lpc_serial->parent, - "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); + rt_device_register(&lpc_serial->parent, + "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); #endif } diff --git a/bsp/lpc2148/rtconfig.h b/bsp/lpc2148/rtconfig.h index 70a6ef0325..a28e205a56 100644 --- a/bsp/lpc2148/rtconfig.h +++ b/bsp/lpc2148/rtconfig.h @@ -3,16 +3,16 @@ #define __RTTHREAD_CFG_H__ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX*/ -#define RT_THREAD_PRIORITY_MAX 32 +#define RT_THREAD_PRIORITY_MAX 32 /* Tick per Second*/ -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 /* SECTION: RT_DEBUG */ /* Thread Debug */ @@ -62,12 +62,12 @@ #define RT_USING_DEVICE #define RT_USING_UART1 #define RT_USING_UART2 -#define RT_UART_RX_BUFFER_SIZE 64 +#define RT_UART_RX_BUFFER_SIZE 64 /* SECTION: Console options */ #define RT_USING_CONSOLE /* the buffer size of console*/ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 /* SECTION: FinSH shell options */ /* Using FinSH as Shell*/ @@ -91,11 +91,11 @@ /* SECTION: DFS options */ /* #define RT_USING_DFS */ /* the max number of mounted filesystem */ -#define DFS_FILESYSTEMS_MAX 2 -/* the max number of opened files */ -#define DFS_FD_MAX 4 -/* the max number of cached sector */ -#define DFS_CACHE_MAX_NUM 8 +#define DFS_FILESYSTEMS_MAX 2 +/* the max number of opened files */ +#define DFS_FD_MAX 4 +/* the max number of cached sector */ +#define DFS_CACHE_MAX_NUM 8 /* SECTION: lwip, a lighwight TCP/IP protocol stack */ /* Using lighweight TCP/IP protocol stack*/ @@ -123,21 +123,21 @@ /* #define RT_LWIP_DHCP */ /* ip address of target*/ -#define RT_LWIP_IPADDR0 192 -#define RT_LWIP_IPADDR1 168 -#define RT_LWIP_IPADDR2 0 -#define RT_LWIP_IPADDR3 30 +#define RT_LWIP_IPADDR0 192 +#define RT_LWIP_IPADDR1 168 +#define RT_LWIP_IPADDR2 0 +#define RT_LWIP_IPADDR3 30 /* gateway address of target*/ -#define RT_LWIP_GWADDR0 192 -#define RT_LWIP_GWADDR1 168 -#define RT_LWIP_GWADDR2 0 -#define RT_LWIP_GWADDR3 1 +#define RT_LWIP_GWADDR0 192 +#define RT_LWIP_GWADDR1 168 +#define RT_LWIP_GWADDR2 0 +#define RT_LWIP_GWADDR3 1 /* mask address of target*/ -#define RT_LWIP_MSKADDR0 255 -#define RT_LWIP_MSKADDR1 255 -#define RT_LWIP_MSKADDR2 255 -#define RT_LWIP_MSKADDR3 0 +#define RT_LWIP_MSKADDR0 255 +#define RT_LWIP_MSKADDR1 255 +#define RT_LWIP_MSKADDR2 255 +#define RT_LWIP_MSKADDR3 0 #endif diff --git a/bsp/lpc2478/applications/application.c b/bsp/lpc2478/applications/application.c index 64dbf3c807..fa10f80d56 100644 --- a/bsp/lpc2478/applications/application.c +++ b/bsp/lpc2478/applications/application.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc2478/applications/startup.c b/bsp/lpc2478/applications/startup.c index 270312f7ae..c121e90990 100644 --- a/bsp/lpc2478/applications/startup.c +++ b/bsp/lpc2478/applications/startup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc2478/drivers/board.c b/bsp/lpc2478/drivers/board.c index 65ff918711..956ec5c03f 100644 --- a/bsp/lpc2478/drivers/board.c +++ b/bsp/lpc2478/drivers/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,7 +14,7 @@ #include #include "board.h" -#define DATA_COUNT 14400000/RT_TICK_PER_SECOND /* T0MR0 = delayInMs * (Fpclk / 1000); */ +#define DATA_COUNT 14400000/RT_TICK_PER_SECOND /* T0MR0 = delayInMs * (Fpclk / 1000); */ extern void rt_hw_serial_init(void); @@ -25,9 +25,9 @@ extern void rt_hw_serial_init(void); void rt_timer_handler(int vector, void* param) { - T0IR |= 0x01; /* clear interrupt flag */ - rt_tick_increase(); - VICVectAddr = 0; /* Acknowledge Interrupt */ + T0IR |= 0x01; /* clear interrupt flag */ + rt_tick_increase(); + VICVectAddr = 0; /* Acknowledge Interrupt */ } /** @@ -36,19 +36,19 @@ void rt_timer_handler(int vector, void* param) void rt_hw_board_init(void) { #if defined(RT_USING_DEVICE) && defined(RT_USING_UART1) - rt_hw_serial_init(); - rt_console_set_device("uart1"); + rt_hw_serial_init(); + rt_console_set_device("uart1"); #endif - T0IR = 0xff; - T0TC = 0; - T0MCR = 0x03; - T0MR0 = (DATA_COUNT); + T0IR = 0xff; + T0TC = 0; + T0MCR = 0x03; + T0MR0 = (DATA_COUNT); - rt_hw_interrupt_install(TIMER0_INT, rt_timer_handler, RT_NULL, "tick"); - rt_hw_interrupt_umask(TIMER0_INT); + rt_hw_interrupt_install(TIMER0_INT, rt_timer_handler, RT_NULL, "tick"); + rt_hw_interrupt_umask(TIMER0_INT); - T0TCR = 0x01; //enable timer0 counter + T0TCR = 0x01; //enable timer0 counter } /*@}*/ diff --git a/bsp/lpc2478/drivers/board.h b/bsp/lpc2478/drivers/board.h index 6386c19ba8..075fe354b8 100644 --- a/bsp/lpc2478/drivers/board.h +++ b/bsp/lpc2478/drivers/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,7 +14,7 @@ /* RT_USING_UART */ #define RT_USING_UART1 #define RT_USING_UART2 -#define RT_UART_RX_BUFFER_SIZE 64 +#define RT_UART_RX_BUFFER_SIZE 64 void rt_hw_board_init(void); void rt_hw_led_set(rt_uint32_t led); void rt_hw_led_flash(void); @@ -23,93 +23,93 @@ void rt_hw_led_flash(void); void rt_hw_finsh_init(void); #endif -#define USE_USB 0 +#define USE_USB 0 -#if USE_USB /* 1 is USB, 0 is non-USB related */ -#define PLL_MValue 11 -#define PLL_NValue 0 -#define CCLKDivValue 4 -#define USBCLKDivValue 5 +#if USE_USB /* 1 is USB, 0 is non-USB related */ +#define PLL_MValue 11 +#define PLL_NValue 0 +#define CCLKDivValue 4 +#define USBCLKDivValue 5 -#define Fosc 12000000 -#define Fcclk 57600000 -#define Fcco 288000000 +#define Fosc 12000000 +#define Fcclk 57600000 +#define Fcco 288000000 #else -#define PLL_MValue 12 -#define PLL_NValue 1 -#define CCLKDivValue 5 +#define PLL_MValue 12 +#define PLL_NValue 1 +#define CCLKDivValue 5 -#define Fosc 12000000 -#define Fcclk 72000000 -#define Fcco 360000000 +#define Fosc 12000000 +#define Fcclk 72000000 +#define Fcco 360000000 #endif #if USE_USB -#define Fpclk (Fcclk / 2) +#define Fpclk (Fcclk / 2) #else -#define Fpclk (Fcclk / 4) +#define Fpclk (Fcclk / 4) #endif /* IRQ define */ -#define SYS32Mode 0x1F -#define IRQ32Mode 0x12 -#define FIQ32Mode 0x11 - -#define HIGHEST_PRIORITY 0x01 -#define LOWEST_PRIORITY 0x0F - -#define WDT_INT 0 -#define SWI_INT 1 -#define ARM_CORE0_INT 2 -#define ARM_CORE1_INT 3 -#define TIMER0_INT 4 -#define TIMER1_INT 5 -#define UART0_INT 6 -#define UART1_INT 7 -#define PWM0_1_INT 8 -#define I2C0_INT 9 -#define SPI0_INT 10 /* SPI and SSP0 share VIC slot */ -#define SSP0_INT 10 -#define SSP1_INT 11 -#define PLL_INT 12 -#define RTC_INT 13 -#define EINT0_INT 14 -#define EINT1_INT 15 -#define EINT2_INT 16 -#define EINT3_INT 17 -#define ADC0_INT 18 -#define I2C1_INT 19 -#define BOD_INT 20 -#define EMAC_INT 21 -#define USB_INT 22 -#define CAN_INT 23 -#define MCI_INT 24 -#define GPDMA_INT 25 -#define TIMER2_INT 26 -#define TIMER3_INT 27 -#define UART2_INT 28 -#define UART3_INT 29 -#define I2C2_INT 30 -#define I2S_INT 31 - -#define VIC_SIZE 32 - -#define VECT_ADDR_INDEX 0x100 +#define SYS32Mode 0x1F +#define IRQ32Mode 0x12 +#define FIQ32Mode 0x11 + +#define HIGHEST_PRIORITY 0x01 +#define LOWEST_PRIORITY 0x0F + +#define WDT_INT 0 +#define SWI_INT 1 +#define ARM_CORE0_INT 2 +#define ARM_CORE1_INT 3 +#define TIMER0_INT 4 +#define TIMER1_INT 5 +#define UART0_INT 6 +#define UART1_INT 7 +#define PWM0_1_INT 8 +#define I2C0_INT 9 +#define SPI0_INT 10 /* SPI and SSP0 share VIC slot */ +#define SSP0_INT 10 +#define SSP1_INT 11 +#define PLL_INT 12 +#define RTC_INT 13 +#define EINT0_INT 14 +#define EINT1_INT 15 +#define EINT2_INT 16 +#define EINT3_INT 17 +#define ADC0_INT 18 +#define I2C1_INT 19 +#define BOD_INT 20 +#define EMAC_INT 21 +#define USB_INT 22 +#define CAN_INT 23 +#define MCI_INT 24 +#define GPDMA_INT 25 +#define TIMER2_INT 26 +#define TIMER3_INT 27 +#define UART2_INT 28 +#define UART3_INT 29 +#define I2C2_INT 30 +#define I2S_INT 31 + +#define VIC_SIZE 32 + +#define VECT_ADDR_INDEX 0x100 #define VECT_CNTL_INDEX 0x200 -#define CCLK 60000000 /* Fosc = 12MHz, M = 5 */ -#define PCLK 15000000 /* CCLK/4, use default */ +#define CCLK 60000000 /* Fosc = 12MHz, M = 5 */ +#define PCLK 15000000 /* CCLK/4, use default */ /****************************************************************************** -** Function name: TargetInit +** Function name: TargetInit ** -** Descriptions: Initialize the target board; it is called in a -** necessary place, change it as needed +** Descriptions: Initialize the target board; it is called in a +** necessary place, change it as needed ** -** parameters: None -** Returned value: None +** parameters: None +** Returned value: None ** ******************************************************************************/ extern void TargetInit(void); diff --git a/bsp/lpc2478/drivers/serial.c b/bsp/lpc2478/drivers/serial.c index dff575c7cc..8e1fe1f91f 100644 --- a/bsp/lpc2478/drivers/serial.c +++ b/bsp/lpc2478/drivers/serial.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,8 +15,8 @@ #include "board.h" /* serial hardware register */ -#define REG8(d) (*((volatile unsigned char *)(d))) -#define REG32(d) (*((volatile unsigned long *)(d))) +#define REG8(d) (*((volatile unsigned char *)(d))) +#define REG32(d) (*((volatile unsigned long *)(d))) #define UART_RBR(base) REG8(base + 0x00) #define UART_THR(base) REG8(base + 0x00) @@ -37,16 +37,16 @@ /* LPC serial device */ struct rt_lpcserial { - /* inherit from device */ - struct rt_device parent; + /* inherit from device */ + struct rt_device parent; - rt_uint32_t hw_base; - rt_uint32_t irqno; - rt_uint32_t baudrate; + rt_uint32_t hw_base; + rt_uint32_t irqno; + rt_uint32_t baudrate; - /* reception field */ - rt_uint16_t save_index, read_index; - rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; + /* reception field */ + rt_uint16_t save_index, read_index; + rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; }; #ifdef RT_USING_UART1 @@ -58,55 +58,55 @@ struct rt_lpcserial serial2; void rt_hw_serial_init(void); -#define U0PINS 0x00000005 +#define U0PINS 0x00000005 void rt_hw_uart_isr(int irqno, void *param) { - RT_UNUSED rt_uint32_t iir; - struct rt_lpcserial* lpc_serial = (struct rt_lpcserial*)param; - - RT_ASSERT(lpc_serial != RT_NULL) - - if (UART_LSR(lpc_serial->hw_base) & 0x01) - { - rt_base_t level; - - while (UART_LSR(lpc_serial->hw_base) & 0x01) - { - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - /* read character */ - lpc_serial->rx_buffer[lpc_serial->save_index] = - UART_RBR(lpc_serial->hw_base); - lpc_serial->save_index ++; - if (lpc_serial->save_index >= RT_UART_RX_BUFFER_SIZE) - lpc_serial->save_index = 0; - - /* if the next position is read index, discard this 'read char' */ - if (lpc_serial->save_index == lpc_serial->read_index) - { - lpc_serial->read_index ++; - if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE) - lpc_serial->read_index = 0; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } - - /* invoke callback */ - if(lpc_serial->parent.rx_indicate != RT_NULL) - { - lpc_serial->parent.rx_indicate(&lpc_serial->parent, 1); - } - } - - /* clear interrupt source */ - iir = UART_IIR(lpc_serial->hw_base); - - /* acknowledge Interrupt */ - VICVectAddr = 0; + RT_UNUSED rt_uint32_t iir; + struct rt_lpcserial* lpc_serial = (struct rt_lpcserial*)param; + + RT_ASSERT(lpc_serial != RT_NULL) + + if (UART_LSR(lpc_serial->hw_base) & 0x01) + { + rt_base_t level; + + while (UART_LSR(lpc_serial->hw_base) & 0x01) + { + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + /* read character */ + lpc_serial->rx_buffer[lpc_serial->save_index] = + UART_RBR(lpc_serial->hw_base); + lpc_serial->save_index ++; + if (lpc_serial->save_index >= RT_UART_RX_BUFFER_SIZE) + lpc_serial->save_index = 0; + + /* if the next position is read index, discard this 'read char' */ + if (lpc_serial->save_index == lpc_serial->read_index) + { + lpc_serial->read_index ++; + if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE) + lpc_serial->read_index = 0; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + + /* invoke callback */ + if(lpc_serial->parent.rx_indicate != RT_NULL) + { + lpc_serial->parent.rx_indicate(&lpc_serial->parent, 1); + } + } + + /* clear interrupt source */ + iir = UART_IIR(lpc_serial->hw_base); + + /* acknowledge Interrupt */ + VICVectAddr = 0; } @@ -117,243 +117,243 @@ void rt_hw_uart_isr(int irqno, void *param) static rt_err_t rt_serial_init (rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) { - struct rt_lpcserial* lpc_serial; - lpc_serial = (struct rt_lpcserial*) dev; - - RT_ASSERT(lpc_serial != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* init UART rx interrupt */ - UART_IER(lpc_serial->hw_base) = 0x01; - - /* install ISR */ - rt_hw_interrupt_install(lpc_serial->irqno, + struct rt_lpcserial* lpc_serial; + lpc_serial = (struct rt_lpcserial*) dev; + + RT_ASSERT(lpc_serial != RT_NULL); + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* init UART rx interrupt */ + UART_IER(lpc_serial->hw_base) = 0x01; + + /* install ISR */ + rt_hw_interrupt_install(lpc_serial->irqno, rt_hw_uart_isr, lpc_serial, RT_NULL); - rt_hw_interrupt_umask(lpc_serial->irqno); - } + rt_hw_interrupt_umask(lpc_serial->irqno); + } - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_close(rt_device_t dev) { - struct rt_lpcserial* lpc_serial; - lpc_serial = (struct rt_lpcserial*) dev; - - RT_ASSERT(lpc_serial != RT_NULL); - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* disable UART rx interrupt */ - UART_IER(lpc_serial->hw_base) = 0x00; - } - - return RT_EOK; + struct rt_lpcserial* lpc_serial; + lpc_serial = (struct rt_lpcserial*) dev; + + RT_ASSERT(lpc_serial != RT_NULL); + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* disable UART rx interrupt */ + UART_IER(lpc_serial->hw_base) = 0x00; + } + + return RT_EOK; } static rt_err_t rt_serial_control(rt_device_t dev, int cmd, void *args) { - return RT_EOK; + return RT_EOK; } static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - struct rt_lpcserial *lpc_serial = (struct rt_lpcserial*)dev; - RT_ASSERT(lpc_serial != RT_NULL); - - /* point to buffer */ - ptr = (rt_uint8_t*) buffer; - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - while (size) - { - /* interrupt receive */ - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - if (lpc_serial->read_index != lpc_serial->save_index) - { - *ptr = lpc_serial->rx_buffer[lpc_serial->read_index]; - - lpc_serial->read_index ++; - if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE) - lpc_serial->read_index = 0; - } - else - { - /* no data in rx buffer */ - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - break; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - - ptr ++; size --; - } - - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; - } - else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) - { - /* not support right now */ - RT_ASSERT(0); - } - - /* polling mode */ - while (size && (UART_LSR(lpc_serial->hw_base) & 0x01)) - { - /* Read Character */ - *ptr = UART_RBR(lpc_serial->hw_base); - - ptr ++; - size --; - } - - return (rt_size_t)ptr - (rt_size_t)buffer; + rt_uint8_t* ptr; + struct rt_lpcserial *lpc_serial = (struct rt_lpcserial*)dev; + RT_ASSERT(lpc_serial != RT_NULL); + + /* point to buffer */ + ptr = (rt_uint8_t*) buffer; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + while (size) + { + /* interrupt receive */ + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + if (lpc_serial->read_index != lpc_serial->save_index) + { + *ptr = lpc_serial->rx_buffer[lpc_serial->read_index]; + + lpc_serial->read_index ++; + if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE) + lpc_serial->read_index = 0; + } + else + { + /* no data in rx buffer */ + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + ptr ++; size --; + } + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) + { + /* not support right now */ + RT_ASSERT(0); + } + + /* polling mode */ + while (size && (UART_LSR(lpc_serial->hw_base) & 0x01)) + { + /* Read Character */ + *ptr = UART_RBR(lpc_serial->hw_base); + + ptr ++; + size --; + } + + return (rt_size_t)ptr - (rt_size_t)buffer; } static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - struct rt_lpcserial* lpc_serial; - char *ptr; - - lpc_serial = (struct rt_lpcserial*) dev; - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - /* not support */ - RT_ASSERT(0); - } - else if (dev->flag & RT_DEVICE_FLAG_DMA_TX) - { - /* not support */ - RT_ASSERT(0); - } - - /* polling write */ - ptr = (char *)buffer; - - if (dev->flag & RT_DEVICE_FLAG_STREAM) - { - /* stream mode */ - while (size) - { - if (*ptr == '\n') - { - while (!(UART_LSR(lpc_serial->hw_base) & 0x20)); - UART_THR(lpc_serial->hw_base) = '\r'; - } - - while (!(UART_LSR(lpc_serial->hw_base) & 0x20)); - UART_THR(lpc_serial->hw_base) = *ptr; - - ptr ++; - size --; - } - } - else - { - while (size) - { - while (!(UART_LSR(lpc_serial->hw_base) & 0x20)); - UART_THR(lpc_serial->hw_base) = *ptr; - - ptr ++; - size --; - } - } - - return (rt_size_t) ptr - (rt_size_t) buffer; + struct rt_lpcserial* lpc_serial; + char *ptr; + + lpc_serial = (struct rt_lpcserial*) dev; + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* not support */ + RT_ASSERT(0); + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_TX) + { + /* not support */ + RT_ASSERT(0); + } + + /* polling write */ + ptr = (char *)buffer; + + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* stream mode */ + while (size) + { + if (*ptr == '\n') + { + while (!(UART_LSR(lpc_serial->hw_base) & 0x20)); + UART_THR(lpc_serial->hw_base) = '\r'; + } + + while (!(UART_LSR(lpc_serial->hw_base) & 0x20)); + UART_THR(lpc_serial->hw_base) = *ptr; + + ptr ++; + size --; + } + } + else + { + while (size) + { + while (!(UART_LSR(lpc_serial->hw_base) & 0x20)); + UART_THR(lpc_serial->hw_base) = *ptr; + + ptr ++; + size --; + } + } + + return (rt_size_t) ptr - (rt_size_t) buffer; } void rt_hw_serial_init(void) { - struct rt_lpcserial* lpc_serial; - + struct rt_lpcserial* lpc_serial; + #ifdef RT_USING_UART1 - lpc_serial = &serial1; - - lpc_serial->parent.type = RT_Device_Class_Char; - - lpc_serial->hw_base = 0xE000C000; - lpc_serial->baudrate = 115200; - lpc_serial->irqno = UART0_INT; - - rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer)); - lpc_serial->read_index = lpc_serial->save_index = 0; - - /* Enable UART0 RxD and TxD pins */ - PINSEL0 |= 0x50; - - /* 8 bits, no Parity, 1 Stop bit */ - UART_LCR(lpc_serial->hw_base) = 0x83; - - /* Setup Baudrate */ - UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF; - UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF; - - /* DLAB = 0 */ - UART_LCR(lpc_serial->hw_base) = 0x03; - - lpc_serial->parent.type = RT_Device_Class_Char; - lpc_serial->parent.init = rt_serial_init; - lpc_serial->parent.open = rt_serial_open; - lpc_serial->parent.close = rt_serial_close; - lpc_serial->parent.read = rt_serial_read; - lpc_serial->parent.write = rt_serial_write; - lpc_serial->parent.control = rt_serial_control; - lpc_serial->parent.user_data = RT_NULL; - - rt_device_register(&lpc_serial->parent, - "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM); + lpc_serial = &serial1; + + lpc_serial->parent.type = RT_Device_Class_Char; + + lpc_serial->hw_base = 0xE000C000; + lpc_serial->baudrate = 115200; + lpc_serial->irqno = UART0_INT; + + rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer)); + lpc_serial->read_index = lpc_serial->save_index = 0; + + /* Enable UART0 RxD and TxD pins */ + PINSEL0 |= 0x50; + + /* 8 bits, no Parity, 1 Stop bit */ + UART_LCR(lpc_serial->hw_base) = 0x83; + + /* Setup Baudrate */ + UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF; + UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF; + + /* DLAB = 0 */ + UART_LCR(lpc_serial->hw_base) = 0x03; + + lpc_serial->parent.type = RT_Device_Class_Char; + lpc_serial->parent.init = rt_serial_init; + lpc_serial->parent.open = rt_serial_open; + lpc_serial->parent.close = rt_serial_close; + lpc_serial->parent.read = rt_serial_read; + lpc_serial->parent.write = rt_serial_write; + lpc_serial->parent.control = rt_serial_control; + lpc_serial->parent.user_data = RT_NULL; + + rt_device_register(&lpc_serial->parent, + "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM); #endif #ifdef RT_USING_UART2 - lpc_serial = &serial2; - - lpc_serial->parent.type = RT_Device_Class_Char; - - lpc_serial->hw_base = 0xE0010000; - lpc_serial->baudrate = 115200; - lpc_serial->irqno = UART1_INT; - - rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer)); - lpc_serial->read_index = lpc_serial->save_index = 0; - - /* Enable UART1 RxD and TxD pins */ - PINSEL0 |= 0x05 << 16; - - /* 8 bits, no Parity, 1 Stop bit */ - UART_LCR(lpc_serial->hw_base) = 0x83; - - /* Setup Baudrate */ - UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF; - UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF; - - /* DLAB = 0 */ - UART_LCR(lpc_serial->hw_base) = 0x03; - - lpc_serial->parent.type = RT_Device_Class_Char; - lpc_serial->parent.init = rt_serial_init; - lpc_serial->parent.open = rt_serial_open; - lpc_serial->parent.close = rt_serial_close; - lpc_serial->parent.read = rt_serial_read; - lpc_serial->parent.write = rt_serial_write; - lpc_serial->parent.control = rt_serial_control; - lpc_serial->parent.user_data = RT_NULL; - - rt_device_register(&lpc_serial->parent, - "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); + lpc_serial = &serial2; + + lpc_serial->parent.type = RT_Device_Class_Char; + + lpc_serial->hw_base = 0xE0010000; + lpc_serial->baudrate = 115200; + lpc_serial->irqno = UART1_INT; + + rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer)); + lpc_serial->read_index = lpc_serial->save_index = 0; + + /* Enable UART1 RxD and TxD pins */ + PINSEL0 |= 0x05 << 16; + + /* 8 bits, no Parity, 1 Stop bit */ + UART_LCR(lpc_serial->hw_base) = 0x83; + + /* Setup Baudrate */ + UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF; + UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF; + + /* DLAB = 0 */ + UART_LCR(lpc_serial->hw_base) = 0x03; + + lpc_serial->parent.type = RT_Device_Class_Char; + lpc_serial->parent.init = rt_serial_init; + lpc_serial->parent.open = rt_serial_open; + lpc_serial->parent.close = rt_serial_close; + lpc_serial->parent.read = rt_serial_read; + lpc_serial->parent.write = rt_serial_write; + lpc_serial->parent.control = rt_serial_control; + lpc_serial->parent.user_data = RT_NULL; + + rt_device_register(&lpc_serial->parent, + "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); #endif } diff --git a/bsp/lpc2478/rtconfig.h b/bsp/lpc2478/rtconfig.h index c35691aa80..d0c419d9ff 100644 --- a/bsp/lpc2478/rtconfig.h +++ b/bsp/lpc2478/rtconfig.h @@ -3,22 +3,22 @@ #define __RTTHREAD_CFG_H__ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX*/ -#define RT_THREAD_PRIORITY_MAX 256 +#define RT_THREAD_PRIORITY_MAX 256 /* Tick per Second*/ -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 -#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_THREAD_STACK_SIZE 512 #define RT_TIMER_THREAD_PRIO 1 /* Rate at which timer management task runs (Hz) */ -#define RT_TIMER_EX_TICKS_PER_SEC 10 +#define RT_TIMER_EX_TICKS_PER_SEC 10 /* SECTION: RT_DEBUG */ @@ -67,7 +67,7 @@ /* SECTION: Console options */ #define RT_USING_CONSOLE /* the buffer size of console*/ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 /* SECTION: FinSH shell options */ /* Using FinSH as Shell*/ @@ -102,21 +102,21 @@ /* #define RT_LWIP_DHCP */ /* ip address of target*/ -#define RT_LWIP_IPADDR0 192 -#define RT_LWIP_IPADDR1 168 -#define RT_LWIP_IPADDR2 0 -#define RT_LWIP_IPADDR3 30 +#define RT_LWIP_IPADDR0 192 +#define RT_LWIP_IPADDR1 168 +#define RT_LWIP_IPADDR2 0 +#define RT_LWIP_IPADDR3 30 /* gateway address of target*/ -#define RT_LWIP_GWADDR0 192 -#define RT_LWIP_GWADDR1 168 -#define RT_LWIP_GWADDR2 0 -#define RT_LWIP_GWADDR3 1 +#define RT_LWIP_GWADDR0 192 +#define RT_LWIP_GWADDR1 168 +#define RT_LWIP_GWADDR2 0 +#define RT_LWIP_GWADDR3 1 /* mask address of target*/ -#define RT_LWIP_MSKADDR0 255 -#define RT_LWIP_MSKADDR1 255 -#define RT_LWIP_MSKADDR2 255 -#define RT_LWIP_MSKADDR3 0 +#define RT_LWIP_MSKADDR0 255 +#define RT_LWIP_MSKADDR1 255 +#define RT_LWIP_MSKADDR2 255 +#define RT_LWIP_MSKADDR3 0 #endif diff --git a/bsp/lpc408x/drivers/board.c b/bsp/lpc408x/drivers/board.c index 8db9473876..23e0ec07ac 100644 --- a/bsp/lpc408x/drivers/board.c +++ b/bsp/lpc408x/drivers/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc408x/drivers/board.h b/bsp/lpc408x/drivers/board.h index 1cc74d0fd6..0b4946ced7 100644 --- a/bsp/lpc408x/drivers/board.h +++ b/bsp/lpc408x/drivers/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc408x/drivers/drv_emac.c b/bsp/lpc408x/drivers/drv_emac.c index 7ea47d52ed..0bae0f1456 100644 --- a/bsp/lpc408x/drivers/drv_emac.c +++ b/bsp/lpc408x/drivers/drv_emac.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc408x/drivers/drv_emac.h b/bsp/lpc408x/drivers/drv_emac.h index 7d67eae178..ce5ca7d9e3 100644 --- a/bsp/lpc408x/drivers/drv_emac.h +++ b/bsp/lpc408x/drivers/drv_emac.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc408x/drivers/drv_hwtimer.c b/bsp/lpc408x/drivers/drv_hwtimer.c index fa09f87d76..0357c2c1f9 100644 --- a/bsp/lpc408x/drivers/drv_hwtimer.c +++ b/bsp/lpc408x/drivers/drv_hwtimer.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc408x/drivers/drv_hwtimer.h b/bsp/lpc408x/drivers/drv_hwtimer.h index 21c5a25eeb..ca34816a77 100644 --- a/bsp/lpc408x/drivers/drv_hwtimer.h +++ b/bsp/lpc408x/drivers/drv_hwtimer.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc408x/drivers/drv_led.c b/bsp/lpc408x/drivers/drv_led.c index d7df12ba82..29c74af1af 100644 --- a/bsp/lpc408x/drivers/drv_led.c +++ b/bsp/lpc408x/drivers/drv_led.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc408x/drivers/drv_led.h b/bsp/lpc408x/drivers/drv_led.h index f3a958c9b5..d006ac7ee6 100644 --- a/bsp/lpc408x/drivers/drv_led.h +++ b/bsp/lpc408x/drivers/drv_led.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc408x/drivers/drv_sdram.c b/bsp/lpc408x/drivers/drv_sdram.c index 0bb9ec6eb3..a0473bae01 100644 --- a/bsp/lpc408x/drivers/drv_sdram.c +++ b/bsp/lpc408x/drivers/drv_sdram.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc408x/drivers/drv_sdram.h b/bsp/lpc408x/drivers/drv_sdram.h index 74ceab2d18..0722e02d9d 100644 --- a/bsp/lpc408x/drivers/drv_sdram.h +++ b/bsp/lpc408x/drivers/drv_sdram.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc408x/drivers/drv_uart.c b/bsp/lpc408x/drivers/drv_uart.c index 09a518f4ab..3b11a851db 100644 --- a/bsp/lpc408x/drivers/drv_uart.c +++ b/bsp/lpc408x/drivers/drv_uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc408x/drivers/drv_uart.h b/bsp/lpc408x/drivers/drv_uart.h index 6fbe0535a5..3d8988e3ac 100644 --- a/bsp/lpc408x/drivers/drv_uart.h +++ b/bsp/lpc408x/drivers/drv_uart.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc43xx/M0/applications/application.c b/bsp/lpc43xx/M0/applications/application.c index 2a9cec5103..1b14f82cd7 100644 --- a/bsp/lpc43xx/M0/applications/application.c +++ b/bsp/lpc43xx/M0/applications/application.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc43xx/M0/applications/board.c b/bsp/lpc43xx/M0/applications/board.c index cd1cf62df0..26d9cd404c 100644 --- a/bsp/lpc43xx/M0/applications/board.c +++ b/bsp/lpc43xx/M0/applications/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc43xx/M0/applications/board.h b/bsp/lpc43xx/M0/applications/board.h index 24dfee67d4..8462dad0f6 100644 --- a/bsp/lpc43xx/M0/applications/board.h +++ b/bsp/lpc43xx/M0/applications/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc43xx/M0/applications/startup.c b/bsp/lpc43xx/M0/applications/startup.c index df9cb7a211..65d430d64a 100644 --- a/bsp/lpc43xx/M0/applications/startup.c +++ b/bsp/lpc43xx/M0/applications/startup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc43xx/M0/applications/vbus_drv.c b/bsp/lpc43xx/M0/applications/vbus_drv.c index 88d5321b30..b52d22334a 100644 --- a/bsp/lpc43xx/M0/applications/vbus_drv.c +++ b/bsp/lpc43xx/M0/applications/vbus_drv.c @@ -1,6 +1,6 @@ /* * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * * SPDX-License-Identifier: Apache-2.0 * Change Logs: * Date Author Notes diff --git a/bsp/lpc43xx/M0/applications/vbus_hw.h b/bsp/lpc43xx/M0/applications/vbus_hw.h index 850466cc45..f1296f4c42 100644 --- a/bsp/lpc43xx/M0/applications/vbus_hw.h +++ b/bsp/lpc43xx/M0/applications/vbus_hw.h @@ -1,6 +1,6 @@ /* * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * * SPDX-License-Identifier: Apache-2.0 * Change Logs: * Date Author Notes diff --git a/bsp/lpc43xx/M4/applications/application.c b/bsp/lpc43xx/M4/applications/application.c index 1c31c9da73..ee689be0db 100644 --- a/bsp/lpc43xx/M4/applications/application.c +++ b/bsp/lpc43xx/M4/applications/application.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -32,10 +32,10 @@ static void _boot_M0(void) LPC_CREG->M0APPMEMMAP = (uint32_t)&_M0_CODE[0]; - // Release Slave from reset, first read status + // Release Slave from reset, first read status u32REG = LPC_RGU->RESET_ACTIVE_STATUS1; - // If the M0 is being held in reset, release it... + // If the M0 is being held in reset, release it... // 1 = no reset, 0 = reset while(!(u32REG & (1u << 24))) { diff --git a/bsp/lpc43xx/M4/applications/board.c b/bsp/lpc43xx/M4/applications/board.c index c6bfa10574..2f815060d5 100644 --- a/bsp/lpc43xx/M4/applications/board.c +++ b/bsp/lpc43xx/M4/applications/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc43xx/M4/applications/board.h b/bsp/lpc43xx/M4/applications/board.h index 0450724e53..faf2930854 100644 --- a/bsp/lpc43xx/M4/applications/board.h +++ b/bsp/lpc43xx/M4/applications/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc43xx/M4/applications/startup.c b/bsp/lpc43xx/M4/applications/startup.c index df9cb7a211..65d430d64a 100644 --- a/bsp/lpc43xx/M4/applications/startup.c +++ b/bsp/lpc43xx/M4/applications/startup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc43xx/M4/applications/vbus_drv.c b/bsp/lpc43xx/M4/applications/vbus_drv.c index bd3ae03adb..ae60af54cb 100644 --- a/bsp/lpc43xx/M4/applications/vbus_drv.c +++ b/bsp/lpc43xx/M4/applications/vbus_drv.c @@ -1,6 +1,6 @@ /* * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * * SPDX-License-Identifier: Apache-2.0 * Change Logs: * Date Author Notes diff --git a/bsp/lpc43xx/M4/applications/vbus_hw.h b/bsp/lpc43xx/M4/applications/vbus_hw.h index 850466cc45..f1296f4c42 100644 --- a/bsp/lpc43xx/M4/applications/vbus_hw.h +++ b/bsp/lpc43xx/M4/applications/vbus_hw.h @@ -1,6 +1,6 @@ /* * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * * SPDX-License-Identifier: Apache-2.0 * Change Logs: * Date Author Notes diff --git a/bsp/lpc43xx/drivers/drv_emac.c b/bsp/lpc43xx/drivers/drv_emac.c index d1f02af768..bf10357a05 100644 --- a/bsp/lpc43xx/drivers/drv_emac.c +++ b/bsp/lpc43xx/drivers/drv_emac.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc43xx/drivers/drv_emac.h b/bsp/lpc43xx/drivers/drv_emac.h index efaa0ac8e3..cde6d2742e 100644 --- a/bsp/lpc43xx/drivers/drv_emac.h +++ b/bsp/lpc43xx/drivers/drv_emac.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc43xx/drivers/drv_led.c b/bsp/lpc43xx/drivers/drv_led.c index 73128c243c..464ddb4f9f 100644 --- a/bsp/lpc43xx/drivers/drv_led.c +++ b/bsp/lpc43xx/drivers/drv_led.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc43xx/drivers/drv_uart.c b/bsp/lpc43xx/drivers/drv_uart.c index e1b203a359..f15f6fb760 100644 --- a/bsp/lpc43xx/drivers/drv_uart.c +++ b/bsp/lpc43xx/drivers/drv_uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -179,7 +179,7 @@ void rt_hw_uart_init(void) config.parity = PARITY_NONE; config.stop_bits = STOP_BITS_1; config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; + config.bufsz = RT_SERIAL_RB_BUFSZ; serial0.ops = &lpc_uart_ops; serial0.config = config; @@ -230,7 +230,7 @@ void rt_hw_uart_init(void) config.parity = PARITY_NONE; config.stop_bits = STOP_BITS_1; config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; + config.bufsz = RT_SERIAL_RB_BUFSZ; serial2.ops = &lpc_uart_ops; serial2.config = config; @@ -282,7 +282,7 @@ void rt_hw_uart_init(void) config.parity = PARITY_NONE; config.stop_bits = STOP_BITS_1; config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; + config.bufsz = RT_SERIAL_RB_BUFSZ; serial3.ops = &lpc_uart_ops; serial3.config = config; diff --git a/bsp/lpc5410x/applications/application.c b/bsp/lpc5410x/applications/application.c index bad0922693..b99155b09d 100644 --- a/bsp/lpc5410x/applications/application.c +++ b/bsp/lpc5410x/applications/application.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc5410x/applications/board.h b/bsp/lpc5410x/applications/board.h index 5bbf8bc235..03f6a284e7 100644 --- a/bsp/lpc5410x/applications/board.h +++ b/bsp/lpc5410x/applications/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc5410x/applications/demo_thread.c b/bsp/lpc5410x/applications/demo_thread.c index 6acb8ae0ef..0d7ce2d2b8 100644 --- a/bsp/lpc5410x/applications/demo_thread.c +++ b/bsp/lpc5410x/applications/demo_thread.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -10,47 +10,47 @@ #include "drv_led.h" #include "drv_uart.h" -static void thread1_entry(void* parameter) +static void thread1_entry(void* parameter) { while(1) { - Led_Control(0,1); - rt_thread_delay(RT_TICK_PER_SECOND); - Led_Control(0,0); - rt_thread_delay(RT_TICK_PER_SECOND); + Led_Control(0,1); + rt_thread_delay(RT_TICK_PER_SECOND); + Led_Control(0,0); + rt_thread_delay(RT_TICK_PER_SECOND); } } -static void thread2_entry(void* parameter) +static void thread2_entry(void* parameter) { while(1) { - Led_Control(1,1); - rt_thread_delay(RT_TICK_PER_SECOND); - Led_Control(1,0); - rt_thread_delay(RT_TICK_PER_SECOND); - } + Led_Control(1,1); + rt_thread_delay(RT_TICK_PER_SECOND); + Led_Control(1,0); + rt_thread_delay(RT_TICK_PER_SECOND); + } } int demo_init(void) { - rt_thread_t thread1 = RT_NULL; - rt_thread_t thread2 = RT_NULL; - - - rt_led_hw_init(); - - - thread1 = rt_thread_create("t1",thread1_entry, RT_NULL,512,10,5); - if (thread1 != RT_NULL) - rt_thread_startup(thread1); - - thread2 = rt_thread_create("t2",thread2_entry, RT_NULL,512,10,5); - if (thread2 != RT_NULL) - rt_thread_startup(thread2); - - - return 0; - + rt_thread_t thread1 = RT_NULL; + rt_thread_t thread2 = RT_NULL; + + + rt_led_hw_init(); + + + thread1 = rt_thread_create("t1",thread1_entry, RT_NULL,512,10,5); + if (thread1 != RT_NULL) + rt_thread_startup(thread1); + + thread2 = rt_thread_create("t2",thread2_entry, RT_NULL,512,10,5); + if (thread2 != RT_NULL) + rt_thread_startup(thread2); + + + return 0; + } diff --git a/bsp/lpc5410x/applications/startup.c b/bsp/lpc5410x/applications/startup.c index 6589dc6b46..9dba37f4d6 100644 --- a/bsp/lpc5410x/applications/startup.c +++ b/bsp/lpc5410x/applications/startup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc5410x/drivers/drv_led.c b/bsp/lpc5410x/drivers/drv_led.c index 8923e3fda4..108707aee1 100644 --- a/bsp/lpc5410x/drivers/drv_led.c +++ b/bsp/lpc5410x/drivers/drv_led.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc5410x/drivers/drv_uart.c b/bsp/lpc5410x/drivers/drv_uart.c index d348921740..826e659eb4 100644 --- a/bsp/lpc5410x/drivers/drv_uart.c +++ b/bsp/lpc5410x/drivers/drv_uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc5410x/rtconfig.h b/bsp/lpc5410x/rtconfig.h index 387f1e75e6..c45f7094f6 100644 --- a/bsp/lpc5410x/rtconfig.h +++ b/bsp/lpc5410x/rtconfig.h @@ -5,17 +5,17 @@ // // -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 // -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 // // 8 // 32 // 256 // -#define RT_THREAD_PRIORITY_MAX 32 +#define RT_THREAD_PRIORITY_MAX 32 // -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 //
#define RT_DEBUG #define RT_DEBUG_COLOR @@ -30,11 +30,11 @@ //
// #define RT_USING_TIMER_SOFT // -#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_PRIO 4 // -#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_THREAD_STACK_SIZE 512 // -#define RT_TIMER_TICK_PER_SECOND 10 +#define RT_TIMER_TICK_PER_SECOND 10 //
//
@@ -75,7 +75,7 @@ //
#define RT_USING_CONSOLE // -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 //
// @@ -87,7 +87,7 @@ // #define FINSH_USING_DESCRIPTION // -#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_THREAD_STACK_SIZE 4096 //
//
@@ -102,18 +102,18 @@ // // #define DFS_USING_WORKDIR // -#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEMS_MAX 2 // -#define DFS_FD_MAX 4 +#define DFS_FD_MAX 4 // #define RT_USING_DFS_ELMFAT // // 1 // 2 // -#define RT_DFS_ELM_USE_LFN 1 +#define RT_DFS_ELM_USE_LFN 1 // -#define RT_DFS_ELM_MAX_LFN 64 +#define RT_DFS_ELM_MAX_LFN 64 // // #define RT_USING_DFS_YAFFS2 // @@ -123,7 +123,7 @@ // // #define RT_USING_DFS_NFS // -#define RT_NFS_HOST_EXPORT "192.168.1.5:/" +#define RT_NFS_HOST_EXPORT "192.168.1.5:/" //
//
@@ -139,29 +139,29 @@ // #define RT_LWIP_DNS // -#define RT_LWIP_PBUF_NUM 4 +#define RT_LWIP_PBUF_NUM 4 // -#define RT_LWIP_TCP_PCB_NUM 3 +#define RT_LWIP_TCP_PCB_NUM 3 // -#define RT_LWIP_TCP_SND_BUF 2048 +#define RT_LWIP_TCP_SND_BUF 2048 // -#define RT_LWIP_TCP_WND 2048 +#define RT_LWIP_TCP_WND 2048 // // #define RT_LWIP_SNMP // // #define RT_LWIP_DHCP // -#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 // -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 // -#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 +#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 // -#define RT_LWIP_ETHTHREAD_PRIORITY 14 +#define RT_LWIP_ETHTHREAD_PRIORITY 14 // -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 // -#define RT_LWIP_ETHTHREAD_STACKSIZE 512 +#define RT_LWIP_ETHTHREAD_STACKSIZE 512 // #define RT_LWIP_IPADDR0 192 #define RT_LWIP_IPADDR1 168 @@ -182,7 +182,7 @@ //
// #define RT_USING_RTGUI // -#define RTGUI_NAME_MAX 12 +#define RTGUI_NAME_MAX 12 // #define RTGUI_USING_SMALL_SIZE // @@ -192,7 +192,7 @@ // #define RTGUI_USING_FONTHZ // -#define RTGUI_DEFAULT_FONT_SIZE 16 +#define RTGUI_DEFAULT_FONT_SIZE 16 // // #define RTGUI_USING_DFS_FILERW // diff --git a/bsp/lpc54114-lite/applications/main.c b/bsp/lpc54114-lite/applications/main.c index 5c13ff5166..f3490dd40b 100644 --- a/bsp/lpc54114-lite/applications/main.c +++ b/bsp/lpc54114-lite/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,9 +14,9 @@ int main(void) { - /* user app entry */ + /* user app entry */ rt_pin_mode(LED4_PIN, PIN_MODE_OUTPUT); - + while (1) { rt_pin_write(LED4_PIN, !rt_pin_read(LED4_PIN)); diff --git a/bsp/lpc54114-lite/applications/mnt.c b/bsp/lpc54114-lite/applications/mnt.c index 7942e159ed..49852b2025 100644 --- a/bsp/lpc54114-lite/applications/mnt.c +++ b/bsp/lpc54114-lite/applications/mnt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -24,15 +24,15 @@ int mnt_init(void) { rt_kprintf("spi flash mount '%s' failed.\n", BSP_FLASH_MOUNT_PATH); } -#endif - +#endif + #if defined(BSP_USING_SDCARD) if(dfs_mount("sd0", BSP_SDCARD_MOUNT_PATH, "elm", 0, 0) != 0) { rt_kprintf("sdcard mount '%s' failed.\n", BSP_SDCARD_MOUNT_PATH); } -#endif +#endif return 0; } -INIT_APP_EXPORT(mnt_init); +INIT_APP_EXPORT(mnt_init); diff --git a/bsp/lpc54114-lite/drivers/audio/drv_mic.c b/bsp/lpc54114-lite/drivers/audio/drv_mic.c index d8219b504d..37bab8e125 100644 --- a/bsp/lpc54114-lite/drivers/audio/drv_mic.c +++ b/bsp/lpc54114-lite/drivers/audio/drv_mic.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -160,4 +160,4 @@ int rt_hw_mic_init(void) return RT_EOK; } -INIT_DEVICE_EXPORT(rt_hw_mic_init); \ No newline at end of file +INIT_DEVICE_EXPORT(rt_hw_mic_init); diff --git a/bsp/lpc54114-lite/drivers/audio/drv_mic.h b/bsp/lpc54114-lite/drivers/audio/drv_mic.h index 1ce777d87d..7364999df5 100644 --- a/bsp/lpc54114-lite/drivers/audio/drv_mic.h +++ b/bsp/lpc54114-lite/drivers/audio/drv_mic.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc54114-lite/drivers/audio/drv_sound.c b/bsp/lpc54114-lite/drivers/audio/drv_sound.c index b6cf0ca2f0..409403facb 100644 --- a/bsp/lpc54114-lite/drivers/audio/drv_sound.c +++ b/bsp/lpc54114-lite/drivers/audio/drv_sound.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -358,4 +358,4 @@ int rt_hw_sound_init(void) rt_audio_register(&snd_dev.audio, "sound0", RT_DEVICE_FLAG_WRONLY, &snd_dev); return RT_EOK; } -INIT_DEVICE_EXPORT(rt_hw_sound_init); \ No newline at end of file +INIT_DEVICE_EXPORT(rt_hw_sound_init); diff --git a/bsp/lpc54114-lite/drivers/audio/drv_sound.h b/bsp/lpc54114-lite/drivers/audio/drv_sound.h index aa997983ae..b50fe66593 100644 --- a/bsp/lpc54114-lite/drivers/audio/drv_sound.h +++ b/bsp/lpc54114-lite/drivers/audio/drv_sound.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc54114-lite/drivers/board.c b/bsp/lpc54114-lite/drivers/board.c index 61652d1c78..f8dc23a34b 100644 --- a/bsp/lpc54114-lite/drivers/board.c +++ b/bsp/lpc54114-lite/drivers/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -57,15 +57,15 @@ void rt_hw_board_init() SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); /* set pend exception priority */ NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1); - + #ifdef RT_USING_HEAP rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); #endif #ifdef RT_USING_COMPONENTS_INIT /* initialization board with RT-Thread Components */ rt_components_board_init(); -#endif -#ifdef RT_USING_CONSOLE +#endif +#ifdef RT_USING_CONSOLE rt_console_set_device(RT_CONSOLE_DEVICE_NAME); #endif } diff --git a/bsp/lpc54114-lite/drivers/board.h b/bsp/lpc54114-lite/drivers/board.h index 78c6d7c8c3..4e07415919 100644 --- a/bsp/lpc54114-lite/drivers/board.h +++ b/bsp/lpc54114-lite/drivers/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc54114-lite/drivers/drv_gpio.c b/bsp/lpc54114-lite/drivers/drv_gpio.c index 2e1b4de609..d663ae189d 100644 --- a/bsp/lpc54114-lite/drivers/drv_gpio.c +++ b/bsp/lpc54114-lite/drivers/drv_gpio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -35,7 +35,7 @@ struct rt_pin_irq_hdr pin_irq_hdr_tab[] = {-1, 0, RT_NULL, RT_NULL}, {-1, 0, RT_NULL, RT_NULL}, {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, }; /* Configure pin mode. pin 0~63 means PIO0_0 ~ PIO1_31 */ @@ -43,46 +43,46 @@ static void lpc_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) { int portx, piny, dir; uint32_t pin_cfg; - + if(pin > PIN_MAX_VAL) return; - + portx = get_port(pin); - piny = get_pin(pin); - + piny = get_pin(pin); + switch(mode) { - case PIN_MODE_OUTPUT: + case PIN_MODE_OUTPUT: dir = kGPIO_DigitalOutput; pin_cfg = IOCON_FUNC0 | IOCON_DIGITAL_EN; break; case PIN_MODE_OUTPUT_OD: - dir = kGPIO_DigitalOutput; - pin_cfg = IOCON_FUNC0 | IOCON_OPENDRAIN_EN | IOCON_DIGITAL_EN; + dir = kGPIO_DigitalOutput; + pin_cfg = IOCON_FUNC0 | IOCON_OPENDRAIN_EN | IOCON_DIGITAL_EN; break; - - case PIN_MODE_INPUT: + + case PIN_MODE_INPUT: dir = kGPIO_DigitalInput; pin_cfg = IOCON_FUNC0 | IOCON_INPFILT_OFF | IOCON_DIGITAL_EN; - break; + break; case PIN_MODE_INPUT_PULLUP: - dir = kGPIO_DigitalInput; + dir = kGPIO_DigitalInput; pin_cfg = IOCON_FUNC0 | IOCON_INPFILT_OFF | IOCON_DIGITAL_EN | IOCON_MODE_PULLUP; break; - case PIN_MODE_INPUT_PULLDOWN: + case PIN_MODE_INPUT_PULLDOWN: dir = kGPIO_DigitalInput; - pin_cfg = IOCON_FUNC0 | IOCON_INPFILT_OFF | IOCON_DIGITAL_EN | IOCON_MODE_PULLDOWN; + pin_cfg = IOCON_FUNC0 | IOCON_INPFILT_OFF | IOCON_DIGITAL_EN | IOCON_MODE_PULLDOWN; break; default: break; - } - - CLOCK_EnableClock(kCLOCK_Iocon); - - IOCON_PinMuxSet(IOCON, portx, piny, pin_cfg); - GPIO_PortInit(GPIO, portx); - + } + + CLOCK_EnableClock(kCLOCK_Iocon); + + IOCON_PinMuxSet(IOCON, portx, piny, pin_cfg); + GPIO_PortInit(GPIO, portx); + gpio_pin_config_t pin_config = {(gpio_pin_direction_t)dir, 0}; - GPIO_PinInit(GPIO, portx, piny, &pin_config); + GPIO_PinInit(GPIO, portx, piny, &pin_config); CLOCK_DisableClock(kCLOCK_Iocon); } @@ -91,27 +91,27 @@ static void lpc_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) { int portx, piny; portx = get_port(pin); - piny = get_pin(pin); + piny = get_pin(pin); if(pin > PIN_MAX_VAL) return; - GPIO_PinWrite(GPIO, portx, piny, value); + GPIO_PinWrite(GPIO, portx, piny, value); } static int lpc_pin_read(rt_device_t dev, rt_base_t pin) { - int portx, piny, value; - + int portx, piny, value; + if(pin > PIN_MAX_VAL) - return RT_ERROR; - + return RT_ERROR; + portx = get_port(pin); - piny = get_pin(pin); - + piny = get_pin(pin); + value = (int)(GPIO_PinRead(GPIO, portx, piny)); - - return value; + + return value; } static void pin_irq_hdr(pint_pin_int_t pintr, uint32_t pmatch_status) @@ -124,10 +124,10 @@ static void pin_irq_hdr(pint_pin_int_t pintr, uint32_t pmatch_status) break; } } - + if(irqno >= IRQ_MAX_VAL) return; - + if (pin_irq_hdr_tab[irqno].hdr) { pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); @@ -142,14 +142,14 @@ void callback(pint_pin_int_t pintr, uint32_t pmatch_status) static rt_err_t lpc_pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args) { - int portx, piny, trigger_mode, pin_initx, pintsel, pin_cfg, i; - + int portx, piny, trigger_mode, pin_initx, pintsel, pin_cfg, i; + if(pin > PIN_MAX_VAL) - return RT_ERROR; - + return RT_ERROR; + portx = get_port(pin); - piny = get_pin(pin); - + piny = get_pin(pin); + switch (mode) { case PIN_IRQ_MODE_RISING: @@ -168,10 +168,10 @@ static rt_err_t lpc_pin_attach_irq(struct rt_device *device, rt_int32_t pin, trigger_mode = kPINT_PinIntEnableLowLevel; break; } - - /* Get inputmux_connection_t */ + + /* Get inputmux_connection_t */ pintsel = (pin + (0xC0U << 20)); - + for(i = 0; i < IRQ_MAX_VAL; i++) { if(pin_irq_hdr_tab[i].pin == -1) @@ -184,40 +184,40 @@ static rt_err_t lpc_pin_attach_irq(struct rt_device *device, rt_int32_t pin, break; } } - + if(i >= IRQ_MAX_VAL) return RT_ERROR; - + /* open clk */ CLOCK_EnableClock(kCLOCK_InputMux); CLOCK_EnableClock(kCLOCK_Iocon); - - /* AttachSignal */ + + /* AttachSignal */ INPUTMUX_AttachSignal(INPUTMUX, i, (inputmux_connection_t)pintsel); pin_cfg = ((IOCON->PIO[portx][piny] & (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK | IOCON_PIO_FILTEROFF_MASK))) /* Mask bits to zero which are setting */ | IOCON_PIO_FUNC(0) /* Selects pin function.: PORT18 (pin 28) is configured as PIO1_8 */ | IOCON_PIO_DIGIMODE(1) /* Select Analog/Digital mode.: Digital mode. */ | IOCON_PIO_FILTEROFF(0)); /* Controls input glitch filter.: Filter enabled. Noise pulses below approximately 10 ns are filtered out. */ - - IOCON_PinMuxSet(IOCON, portx, piny, pin_cfg); - + + IOCON_PinMuxSet(IOCON, portx, piny, pin_cfg); + /* PINT_PinInterruptConfig */ - PINT_PinInterruptConfig(PINT, (pint_pin_int_t)pin_initx, (pint_pin_enable_t)(pin_irq_hdr_tab[i].mode), callback); - + PINT_PinInterruptConfig(PINT, (pint_pin_int_t)pin_initx, (pint_pin_enable_t)(pin_irq_hdr_tab[i].mode), callback); + CLOCK_DisableClock(kCLOCK_InputMux); CLOCK_DisableClock(kCLOCK_Iocon); - + return RT_EOK; } static rt_err_t lpc_pin_detach_irq(struct rt_device *device, rt_int32_t pin) { - int i; - + int i; + if(pin > PIN_MAX_VAL) - return RT_ERROR; - + return RT_ERROR; + for(i = 0; i < IRQ_MAX_VAL; i++) { if(pin_irq_hdr_tab[i].pin == pin) @@ -228,18 +228,18 @@ static rt_err_t lpc_pin_detach_irq(struct rt_device *device, rt_int32_t pin) pin_irq_hdr_tab[i].args = RT_NULL; break; } - } + } return RT_EOK; } static rt_err_t lpc_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) -{ +{ int irqn_type, i; - + if(pin > PIN_MAX_VAL) - return RT_ERROR; - + return RT_ERROR; + for(i = 0; i < IRQ_MAX_VAL; i++) { if(pin_irq_hdr_tab[i].pin == pin) @@ -273,8 +273,8 @@ static rt_err_t lpc_pin_irq_enable(struct rt_device *device, rt_base_t pin, } break; } - } - + } + if(i >= IRQ_MAX_VAL) return RT_ERROR; @@ -288,7 +288,7 @@ const static struct rt_pin_ops _lpc_pin_ops = lpc_pin_read, lpc_pin_attach_irq, lpc_pin_detach_irq, - lpc_pin_irq_enable, + lpc_pin_irq_enable, }; int rt_hw_pin_init(void) diff --git a/bsp/lpc54114-lite/drivers/drv_gpio.h b/bsp/lpc54114-lite/drivers/drv_gpio.h index 0c98e82298..41e4c45724 100644 --- a/bsp/lpc54114-lite/drivers/drv_gpio.h +++ b/bsp/lpc54114-lite/drivers/drv_gpio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,4 +13,4 @@ extern int rt_hw_pin_init(void); -#endif +#endif diff --git a/bsp/lpc54114-lite/drivers/drv_i2c.c b/bsp/lpc54114-lite/drivers/drv_i2c.c index 81be945067..cba87c8aec 100644 --- a/bsp/lpc54114-lite/drivers/drv_i2c.c +++ b/bsp/lpc54114-lite/drivers/drv_i2c.c @@ -1,21 +1,21 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 */ - -#include "drv_i2c.h" -#include "fsl_common.h" +#include "drv_i2c.h" + +#include "fsl_common.h" #include "fsl_iocon.h" #include "fsl_i2c.h" struct lpc_i2c { - struct rt_i2c_bus_device bus; - + struct rt_i2c_bus_device bus; + I2C_Type *base; - + char *device_name; }; @@ -28,9 +28,9 @@ static uint32_t get_i2c_freq(I2C_Type *base) { freq = CLOCK_GetFreq(kCLOCK_Flexcomm4); } -#endif +#endif - return freq; + return freq; } static rt_size_t master_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num) @@ -43,7 +43,7 @@ static rt_size_t master_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg ms i2c_direction_t direction; status_t result = kStatus_Success; - RT_ASSERT(bus != RT_NULL); + RT_ASSERT(bus != RT_NULL); lpc_i2c = (struct lpc_i2c *)bus; @@ -94,13 +94,13 @@ static rt_err_t i2c_bus_control(struct rt_i2c_bus_device *bus, rt_uint32_t cmd, static const struct rt_i2c_bus_device_ops ops = { - master_xfer, + master_xfer, slave_xfer, i2c_bus_control, -}; +}; #if defined(BSP_USING_I2C4) -static struct lpc_i2c i2c4 = {0}; +static struct lpc_i2c i2c4 = {0}; #endif int rt_hw_i2c_init(void) @@ -110,11 +110,11 @@ int rt_hw_i2c_init(void) #if defined(BSP_USING_I2C4) CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4); RESET_PeripheralReset(kFC4_RST_SHIFT_RSTn); - + i2c4.base = I2C4; - i2c4.device_name = "i2c4"; - i2c4.bus.ops = &ops; - + i2c4.device_name = "i2c4"; + i2c4.bus.ops = &ops; + IOCON_PinMuxSet(IOCON, 1, 1, IOCON_MODE_PULLUP | IOCON_FUNC5 | IOCON_DIGITAL_EN | IOCON_INPFILT_OFF); IOCON_PinMuxSet(IOCON, 1, 2, IOCON_MODE_PULLUP | IOCON_FUNC5 | IOCON_DIGITAL_EN | IOCON_INPFILT_OFF); @@ -122,12 +122,12 @@ int rt_hw_i2c_init(void) I2C_MasterGetDefaultConfig(&masterConfig); masterConfig.baudRate_Bps = 100*1000U; - + I2C_MasterInit(I2C4, &masterConfig, get_i2c_freq(I2C4)); rt_i2c_bus_device_register(&i2c4.bus, i2c4.device_name); #endif - return RT_EOK; + return RT_EOK; } -INIT_BOARD_EXPORT(rt_hw_i2c_init); +INIT_BOARD_EXPORT(rt_hw_i2c_init); diff --git a/bsp/lpc54114-lite/drivers/drv_i2c.h b/bsp/lpc54114-lite/drivers/drv_i2c.h index 468ac3c0dc..c5073237a8 100644 --- a/bsp/lpc54114-lite/drivers/drv_i2c.h +++ b/bsp/lpc54114-lite/drivers/drv_i2c.h @@ -1,14 +1,14 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 */ - -#ifndef __DRV_I2C_H__ -#define __DRV_I2C_H__ -#include -#include +#ifndef __DRV_I2C_H__ +#define __DRV_I2C_H__ + +#include +#include int rt_hw_i2c_init(void); diff --git a/bsp/lpc54114-lite/drivers/drv_sdcard.c b/bsp/lpc54114-lite/drivers/drv_sdcard.c index 3ef5081aa7..7ca47a1932 100644 --- a/bsp/lpc54114-lite/drivers/drv_sdcard.c +++ b/bsp/lpc54114-lite/drivers/drv_sdcard.c @@ -1,27 +1,27 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 */ - + #include "drv_sdcard.h" -#include "drv_spi.h" +#include "drv_spi.h" #include "spi_msd.h" #define RT_SDCARD_CS_PIN (3) int rt_hw_sdcard_init(void) { - rt_err_t ret; - - ret = lpc_spi_bus_attach_device("spi2", "spi21", RT_SDCARD_CS_PIN); - if(ret != RT_EOK) + rt_err_t ret; + + ret = lpc_spi_bus_attach_device("spi2", "spi21", RT_SDCARD_CS_PIN); + if(ret != RT_EOK) { - return ret; + return ret; } - + ret = msd_init("sd0", "spi21"); - return ret; + return ret; } -INIT_DEVICE_EXPORT(rt_hw_sdcard_init); +INIT_DEVICE_EXPORT(rt_hw_sdcard_init); diff --git a/bsp/lpc54114-lite/drivers/drv_sdcard.h b/bsp/lpc54114-lite/drivers/drv_sdcard.h index 1ba77cf2b2..a225433b15 100644 --- a/bsp/lpc54114-lite/drivers/drv_sdcard.h +++ b/bsp/lpc54114-lite/drivers/drv_sdcard.h @@ -1,14 +1,14 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 */ - -#ifndef __DRV_SDCARD_H__ -#define __DRV_SDCARD_H__ -#include -#include +#ifndef __DRV_SDCARD_H__ +#define __DRV_SDCARD_H__ + +#include +#include int rt_hw_sdcard_init(void); diff --git a/bsp/lpc54114-lite/drivers/drv_spi.c b/bsp/lpc54114-lite/drivers/drv_spi.c index 0843e0baab..c83aaf03ee 100644 --- a/bsp/lpc54114-lite/drivers/drv_spi.c +++ b/bsp/lpc54114-lite/drivers/drv_spi.c @@ -1,12 +1,12 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 */ #include "drv_spi.h" -#include "fsl_common.h" +#include "fsl_common.h" #include "fsl_iocon.h" #include "fsl_spi.h" @@ -25,23 +25,23 @@ static uint32_t get_spi_freq(SPI_Type *base) { freq = CLOCK_GetFreq(kCLOCK_Flexcomm2); } -#endif +#endif - return freq; + return freq; } static rt_err_t spi_init(SPI_Type *base, struct rt_spi_configuration *cfg) { spi_master_config_t masterConfig = {0}; - RT_ASSERT(cfg != RT_NULL); + RT_ASSERT(cfg != RT_NULL); if(cfg->data_width != 8 && cfg->data_width != 16) { - return (-RT_EINVAL); + return (-RT_EINVAL); } - SPI_MasterGetDefaultConfig(&masterConfig); + SPI_MasterGetDefaultConfig(&masterConfig); if(cfg->max_hz > 12*1000*1000) { @@ -51,124 +51,124 @@ static rt_err_t spi_init(SPI_Type *base, struct rt_spi_configuration *cfg) if(cfg->data_width == 8) { - masterConfig.dataWidth = kSPI_Data8Bits; + masterConfig.dataWidth = kSPI_Data8Bits; } else if(cfg->data_width == 16) { - masterConfig.dataWidth = kSPI_Data16Bits; + masterConfig.dataWidth = kSPI_Data16Bits; } if(cfg->mode & RT_SPI_MSB) { - masterConfig.direction = kSPI_MsbFirst; + masterConfig.direction = kSPI_MsbFirst; } else { - masterConfig.direction = kSPI_LsbFirst; + masterConfig.direction = kSPI_LsbFirst; } if(cfg->mode & RT_SPI_CPHA) { - masterConfig.phase = kSPI_ClockPhaseSecondEdge; + masterConfig.phase = kSPI_ClockPhaseSecondEdge; } else { - masterConfig.phase = kSPI_ClockPhaseFirstEdge; + masterConfig.phase = kSPI_ClockPhaseFirstEdge; } if(cfg->mode & RT_SPI_CPOL) { - masterConfig.polarity = kSPI_ClockPolarityActiveLow; + masterConfig.polarity = kSPI_ClockPolarityActiveLow; } else { - masterConfig.polarity = kSPI_ClockPolarityActiveHigh; + masterConfig.polarity = kSPI_ClockPolarityActiveHigh; } - masterConfig.txWatermark = kSPI_TxFifo0, - masterConfig.rxWatermark = kSPI_RxFifo1, - - // masterConfig.sselNum = kSPI_Ssel3; - SPI_MasterInit(base, &masterConfig, get_spi_freq(base)); + masterConfig.txWatermark = kSPI_TxFifo0, + masterConfig.rxWatermark = kSPI_RxFifo1, + + // masterConfig.sselNum = kSPI_Ssel3; + SPI_MasterInit(base, &masterConfig, get_spi_freq(base)); - return RT_EOK; + return RT_EOK; } rt_err_t lpc_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin) { - rt_err_t ret = RT_EOK; - - struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); - RT_ASSERT(spi_device != RT_NULL); - - struct lpc_sw_spi_cs *cs_pin = (struct lpc_sw_spi_cs *)rt_malloc(sizeof(struct lpc_sw_spi_cs)); + rt_err_t ret = RT_EOK; + + struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); + RT_ASSERT(spi_device != RT_NULL); + + struct lpc_sw_spi_cs *cs_pin = (struct lpc_sw_spi_cs *)rt_malloc(sizeof(struct lpc_sw_spi_cs)); RT_ASSERT(cs_pin != RT_NULL); - + cs_pin->pin = pin; - rt_pin_mode(pin, PIN_MODE_OUTPUT); - rt_pin_write(pin, PIN_HIGH); - - ret = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); - - return ret; + rt_pin_mode(pin, PIN_MODE_OUTPUT); + rt_pin_write(pin, PIN_HIGH); + + ret = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); + + return ret; } static rt_err_t configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg) { - rt_err_t ret = RT_EOK; - struct lpc_spi *spi = RT_NULL; - + rt_err_t ret = RT_EOK; + struct lpc_spi *spi = RT_NULL; + RT_ASSERT(cfg != RT_NULL); RT_ASSERT(device != RT_NULL); - - spi = (struct lpc_spi *)(device->bus->parent.user_data); - spi->cfg = cfg; - ret = spi_init(spi->base, cfg); - + + spi = (struct lpc_spi *)(device->bus->parent.user_data); + spi->cfg = cfg; + ret = spi_init(spi->base, cfg); + return ret; } static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message) { - spi_transfer_t transfer = {0}; - + spi_transfer_t transfer = {0}; + RT_ASSERT(device != RT_NULL); RT_ASSERT(device->bus != RT_NULL); RT_ASSERT(device->bus->parent.user_data != RT_NULL); - - struct lpc_spi *spi = (struct lpc_spi *)(device->bus->parent.user_data); - struct lpc_sw_spi_cs *cs = device->parent.user_data; - + + struct lpc_spi *spi = (struct lpc_spi *)(device->bus->parent.user_data); + struct lpc_sw_spi_cs *cs = device->parent.user_data; + if(message->cs_take) { rt_pin_write(cs->pin, PIN_LOW); } - - transfer.dataSize = message->length; - transfer.rxData = (uint8_t *)(message->recv_buf); - transfer.txData = (uint8_t *)(message->send_buf); + + transfer.dataSize = message->length; + transfer.rxData = (uint8_t *)(message->recv_buf); + transfer.txData = (uint8_t *)(message->send_buf); transfer.configFlags |= kSPI_FrameAssert; - - SPI_MasterTransferBlocking(spi->base, &transfer); - + + SPI_MasterTransferBlocking(spi->base, &transfer); + if(message->cs_release) { rt_pin_write(cs->pin, PIN_HIGH); } - - return message->length; + + return message->length; } #if defined(BSP_USING_SPI2) -static struct lpc_spi spi2 = {0}; -static struct rt_spi_bus spi2_bus = {0}; +static struct lpc_spi spi2 = {0}; +static struct rt_spi_bus spi2_bus = {0}; #endif -static struct rt_spi_ops lpc_spi_ops = +static struct rt_spi_ops lpc_spi_ops = { - configure, + configure, spixfer -}; +}; int rt_hw_spi_init(void) { @@ -178,17 +178,17 @@ int rt_hw_spi_init(void) CLOCK_AttachClk(kFRO12M_to_FLEXCOMM2); RESET_PeripheralReset(kFC2_RST_SHIFT_RSTn); - spi2.base = SPI2; - spi2.cfg = RT_NULL; - spi2_bus.parent.user_data = &spi2; - + spi2.base = SPI2; + spi2.cfg = RT_NULL; + spi2_bus.parent.user_data = &spi2; + IOCON_PinMuxSet(IOCON, 0, 8, (IOCON_FUNC1 | IOCON_MODE_PULLUP | IOCON_GPIO_MODE | IOCON_DIGITAL_EN)); /* SPI2_MOSI */ IOCON_PinMuxSet(IOCON, 0, 9, (IOCON_FUNC1 | IOCON_MODE_PULLUP | IOCON_GPIO_MODE | IOCON_DIGITAL_EN)); /* SPI2_MISO */ IOCON_PinMuxSet(IOCON, 0, 10, (IOCON_FUNC1 | IOCON_MODE_PULLUP | IOCON_GPIO_MODE | IOCON_DIGITAL_EN)); /* SPI2_SCK */ - rt_spi_bus_register(&spi2_bus, "spi2", &lpc_spi_ops); + rt_spi_bus_register(&spi2_bus, "spi2", &lpc_spi_ops); #endif - return RT_EOK; + return RT_EOK; } -INIT_BOARD_EXPORT(rt_hw_spi_init); +INIT_BOARD_EXPORT(rt_hw_spi_init); diff --git a/bsp/lpc54114-lite/drivers/drv_spi.h b/bsp/lpc54114-lite/drivers/drv_spi.h index c269cb9892..2938716aa4 100644 --- a/bsp/lpc54114-lite/drivers/drv_spi.h +++ b/bsp/lpc54114-lite/drivers/drv_spi.h @@ -1,21 +1,21 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 */ - -#ifndef __DRV_SPI_H__ -#define __DRV_SPI_H__ -#include -#include +#ifndef __DRV_SPI_H__ +#define __DRV_SPI_H__ + +#include +#include struct lpc_sw_spi_cs { rt_uint32_t pin; -}; +}; int rt_hw_spi_init(void); -rt_err_t lpc_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin); +rt_err_t lpc_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin); #endif diff --git a/bsp/lpc54114-lite/drivers/drv_spi_flash.c b/bsp/lpc54114-lite/drivers/drv_spi_flash.c index 65433ce30c..11098636f9 100644 --- a/bsp/lpc54114-lite/drivers/drv_spi_flash.c +++ b/bsp/lpc54114-lite/drivers/drv_spi_flash.c @@ -1,14 +1,14 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 */ - -#include "drv_spi.h" + +#include "drv_spi.h" #include "drv_spi_flash.h" -#include "rtthread.h" -#include "rtdevice.h" +#include "rtthread.h" +#include "rtdevice.h" #include "spi_flash.h" #include "spi_flash_sfud.h" @@ -16,19 +16,19 @@ int rt_hw_flash_init(void) { - rt_err_t result; - - result = lpc_spi_bus_attach_device("spi2", "spi20", RT_SPI_FLASH_CS_PIN); - if(result != RT_EOK) + rt_err_t result; + + result = lpc_spi_bus_attach_device("spi2", "spi20", RT_SPI_FLASH_CS_PIN); + if(result != RT_EOK) { - return result; + return result; } - - if(rt_sfud_flash_probe("flash0", "spi20") == RT_NULL) + + if(rt_sfud_flash_probe("flash0", "spi20") == RT_NULL) { return RT_ERROR; } - return RT_EOK; + return RT_EOK; } -INIT_DEVICE_EXPORT(rt_hw_flash_init); +INIT_DEVICE_EXPORT(rt_hw_flash_init); diff --git a/bsp/lpc54114-lite/drivers/drv_spi_flash.h b/bsp/lpc54114-lite/drivers/drv_spi_flash.h index f3c71e06c2..50b941449e 100644 --- a/bsp/lpc54114-lite/drivers/drv_spi_flash.h +++ b/bsp/lpc54114-lite/drivers/drv_spi_flash.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -10,6 +10,6 @@ #ifndef __DRV_SPI_FLASH_H_ #define __DRV_SPI_FLASH_H_ -int rt_hw_w25qxx_init(void); +int rt_hw_w25qxx_init(void); #endif diff --git a/bsp/lpc54114-lite/drivers/drv_uart.c b/bsp/lpc54114-lite/drivers/drv_uart.c index fc0999d4a4..0ccce7632c 100644 --- a/bsp/lpc54114-lite/drivers/drv_uart.c +++ b/bsp/lpc54114-lite/drivers/drv_uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -42,14 +42,14 @@ static rt_err_t lpc_configure(struct rt_serial_device *serial, struct serial_con * config.enableRx = false; */ USART_GetDefaultConfig(&u0_config); - - u0_config.baudRate_Bps = cfg->baud_rate; + + u0_config.baudRate_Bps = cfg->baud_rate; u0_config.parityMode = kUSART_ParityDisabled, u0_config.stopBitCount = kUSART_OneStopBit, u0_config.bitCountPerChar = kUSART_8BitsPerChar, u0_config.loopback = false, u0_config.txWatermark = kUSART_TxFifo0, - u0_config.rxWatermark = kUSART_RxFifo1, + u0_config.rxWatermark = kUSART_RxFifo1, u0_config.enableTx = true; u0_config.enableRx = true; @@ -143,7 +143,7 @@ int rt_hw_uart_init(void) struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; #ifdef BSP_USING_UART0 - + uart = &uart0; serial0.ops = &lpc_uart_ops; @@ -152,40 +152,40 @@ int rt_hw_uart_init(void) /* attach 12 MHz clock to FLEXCOMM0 (debug console) */ CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0); - + /* reset FLEXCOMM for USART */ RESET_PeripheralReset(kFC0_RST_SHIFT_RSTn); - + /* Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.: 0x01u */ CLOCK_EnableClock(kCLOCK_Iocon); - + const uint32_t port0_pin0_config = ((IOCON->PIO[PORT0_IDX][PIN0_IDX] & - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ - | IOCON_PIO_FUNC(1) /* Selects pin function: PORT00 (pin 31) is configured as FC0_RXD_SDA_MOSI. */ - | IOCON_PIO_DIGIMODE(1)); /* Select Analog/Digital mode : Digital mode. */ - + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ + | IOCON_PIO_FUNC(1) /* Selects pin function: PORT00 (pin 31) is configured as FC0_RXD_SDA_MOSI. */ + | IOCON_PIO_DIGIMODE(1)); /* Select Analog/Digital mode : Digital mode. */ + IOCON_PinMuxSet(IOCON, PORT0_IDX, PIN0_IDX, port0_pin0_config); /* PORT0 PIN0 (coords: 31) is configured as FC0_RXD_SDA_MOSI */ - - const uint32_t port0_pin1_config = ((IOCON->PIO[PORT0_IDX][PIN1_IDX] & - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ - | IOCON_PIO_FUNC(1) /* Selects pin function: PORT01 (pin 32) is configured as FC0_TXD_SCL_MISO. */ + + const uint32_t port0_pin1_config = ((IOCON->PIO[PORT0_IDX][PIN1_IDX] & + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ + | IOCON_PIO_FUNC(1) /* Selects pin function: PORT01 (pin 32) is configured as FC0_TXD_SCL_MISO. */ | IOCON_PIO_DIGIMODE(1)); /* Select Analog/Digital mode : Digital mode. */ - + IOCON_PinMuxSet(IOCON, PORT0_IDX, PIN1_IDX, port0_pin1_config); /* PORT0 PIN1 (coords: 32) is configured as FC0_TXD_SCL_MISO */ - + /* Enable RX interrupt. */ USART_EnableInterrupts(uart->UART, kUSART_RxLevelInterruptEnable | kUSART_RxErrorInterruptEnable); EnableIRQ(uart->UART_IRQn); - - CLOCK_DisableClock(kCLOCK_Iocon); - + + CLOCK_DisableClock(kCLOCK_Iocon); + /* register UART0 device */ rt_hw_serial_register(&serial0, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, uart); -#endif - +#endif + return 0; } INIT_BOARD_EXPORT(rt_hw_uart_init); diff --git a/bsp/lpc54114-lite/drivers/drv_uart.h b/bsp/lpc54114-lite/drivers/drv_uart.h index e066448d24..1bef2e50a6 100644 --- a/bsp/lpc54114-lite/drivers/drv_uart.h +++ b/bsp/lpc54114-lite/drivers/drv_uart.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,4 +13,4 @@ extern int rt_hw_uart_init(void); -#endif +#endif diff --git a/bsp/lpc54608-LPCXpresso/applications/application.c b/bsp/lpc54608-LPCXpresso/applications/application.c index b85de95df6..bfb039472d 100644 --- a/bsp/lpc54608-LPCXpresso/applications/application.c +++ b/bsp/lpc54608-LPCXpresso/applications/application.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -47,10 +47,10 @@ void link_dump(void) extern unsigned int _sbss; extern unsigned int _ebss; - + #define DUMP_VAR(__VAR) \ rt_kprintf("%-20s %p\n", #__VAR, &__VAR) - + DUMP_VAR(_sdata); DUMP_VAR(_edata); DUMP_VAR(_sidata); @@ -62,10 +62,10 @@ void link_dump(void) int rt_application_init(void) { rt_thread_t tid; - + build_dump(); link_dump(); - + tid = rt_thread_create("init", rt_init_thread_entry, RT_NULL, 2048, RT_THREAD_PRIORITY_MAX / 3, 20); diff --git a/bsp/lpc54608-LPCXpresso/applications/mnt.c b/bsp/lpc54608-LPCXpresso/applications/mnt.c index dd1f862ea5..4a865340d9 100644 --- a/bsp/lpc54608-LPCXpresso/applications/mnt.c +++ b/bsp/lpc54608-LPCXpresso/applications/mnt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -33,7 +33,7 @@ int mnt_init(void) dfs_romfs_init(); /* mount rom file system */ - if (dfs_mount(RT_NULL, "/", "rom", 0, &(romfs_root)) == 0) + if (dfs_mount(RT_NULL, "/", "rom", 0, &(romfs_root)) == 0) { rt_kprintf("ROM file system initializated!\n"); } @@ -44,14 +44,14 @@ int mnt_init(void) mci_hw_init("sd0"); #endif -#ifdef RT_DFS_ELM_REENTRANT +#ifdef RT_DFS_ELM_REENTRANT /* mount sd card fat partition 1 as root directory */ if (dfs_mount("sd0", SD_ROOT, "elm", 0, 0) == 0) rt_kprintf("File System initialized!\n"); else rt_kprintf("File System init failed!\n"); #endif - + return 0; } INIT_ENV_EXPORT(mnt_init); diff --git a/bsp/lpc54608-LPCXpresso/applications/startup.c b/bsp/lpc54608-LPCXpresso/applications/startup.c index 687cc0f864..fcd836cdac 100644 --- a/bsp/lpc54608-LPCXpresso/applications/startup.c +++ b/bsp/lpc54608-LPCXpresso/applications/startup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -39,10 +39,10 @@ void rtthread_startup(void) /* initialize scheduler system */ rt_system_scheduler_init(); - + /* initialize system timer*/ rt_system_timer_init(); - + /* initialize application */ rt_application_init(); diff --git a/bsp/lpc54608-LPCXpresso/drivers/board.h b/bsp/lpc54608-LPCXpresso/drivers/board.h index 679f33682f..db2ac831c5 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/board.h +++ b/bsp/lpc54608-LPCXpresso/drivers/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc54608-LPCXpresso/drivers/drt_mpu.c b/bsp/lpc54608-LPCXpresso/drivers/drt_mpu.c index c6c5d114e4..7e220327cb 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drt_mpu.c +++ b/bsp/lpc54608-LPCXpresso/drivers/drt_mpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -26,9 +26,9 @@ int rt_hw_mpu_init(void) { uint32_t rbar; uint32_t rasr; - + MPU_PRINT("\nnumber of regions: %d\n", (MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos); - + /* Disable MPU */ ARM_MPU_Disable(); diff --git a/bsp/lpc54608-LPCXpresso/drivers/drt_mpu.h b/bsp/lpc54608-LPCXpresso/drivers/drt_mpu.h index ff34c225e7..782f6fce08 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drt_mpu.h +++ b/bsp/lpc54608-LPCXpresso/drivers/drt_mpu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_emac.c b/bsp/lpc54608-LPCXpresso/drivers/drv_emac.c index b432aea70e..394ad22cca 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drv_emac.c +++ b/bsp/lpc54608-LPCXpresso/drivers/drv_emac.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -73,14 +73,14 @@ struct lpc_emac /* inherit from ethernet device */ struct eth_device parent; struct rt_semaphore tx_wait; - + ENET_Type *base; enet_handle_t handle; - + /* interface address info. */ rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ uint32_t phyAddr; - + uint8_t RxBuffDescrip[ENET_RXBD_NUM * sizeof(enet_rx_bd_struct_t) + ENET_BUFF_ALIGNMENT]; uint8_t TxBuffDescrip[ENET_TXBD_NUM * sizeof(enet_tx_bd_struct_t) + ENET_BUFF_ALIGNMENT]; uint8_t RxDataBuff[ENET_RXBD_NUM * ENET_ALIGN(ENET_RXBUFF_SIZE) + ENET_BUFF_ALIGNMENT]; @@ -273,7 +273,7 @@ static rt_err_t lpc_emac_phy_init(phy_speed_t * speed, phy_duplex_t * duplex) { bool link = false; int32_t status; - + RT_ASSERT(speed != NULL); RT_ASSERT(duplex != NULL); @@ -284,9 +284,9 @@ static rt_err_t lpc_emac_phy_init(phy_speed_t * speed, phy_duplex_t * duplex) *duplex = kPHY_HalfDuplex; /* 10M speed. */ *speed = kPHY_Speed10M; - + eth_device_linkchange(&lpc_emac_device.parent, RT_FALSE); - + ETH_PRINTF("PHY_Init failed!\n"); return RT_ERROR; } @@ -305,7 +305,7 @@ static rt_err_t lpc_emac_phy_init(phy_speed_t * speed, phy_duplex_t * duplex) } PHY_GetLinkSpeedDuplex(lpc_emac_device.base, lpc_emac_device.phyAddr, speed, duplex); - + eth_device_linkchange(&lpc_emac_device.parent, RT_TRUE); return RT_EOK; @@ -338,19 +338,19 @@ static rt_err_t lpc_emac_init(rt_device_t dev) buffCfg.rxDescTailAddrAlign = get_rx_desc(ENET_RXBD_NUM); buffCfg.rxBufferStartAddr = rxBufferStartAddr; buffCfg.rxBuffSizeAlign = ENET_ALIGN(ENET_RXBUFF_SIZE); - + /* Get default configuration 100M RMII. */ ENET_GetDefaultConfig(&config); /* Use the actual speed and duplex when phy success to finish the autonegotiation. */ config.miiSpeed = (enet_mii_speed_t)speed; config.miiDuplex = (enet_mii_duplex_t)duplex; - + ETH_PRINTF("Auto negotiation, Speed: "); if (config.miiSpeed == kENET_MiiSpeed100M) ETH_PRINTF("100M"); else ETH_PRINTF("10M"); - + ETH_PRINTF(", Duplex: "); if (config.miiSpeed == kENET_MiiSpeed100M) ETH_PRINTF("Full\n"); @@ -363,10 +363,10 @@ static rt_err_t lpc_emac_init(rt_device_t dev) /* Enable the tx/rx interrupt. */ ENET_EnableInterrupts(lpc_emac_device.base, (kENET_DmaTx | kENET_DmaRx)); ENET_CreateHandler(lpc_emac_device.base, &lpc_emac_device.handle, &config, &buffCfg, ethernet_callback, NULL); - + /* Initialize Descriptor. */ ENET_DescriptorInit(lpc_emac_device.base, &config, &buffCfg); - + /* Active TX/RX. */ ENET_StartRxTx(lpc_emac_device.base, 1, 1); @@ -416,23 +416,23 @@ static rt_err_t lpc_emac_control(rt_device_t dev, int cmd, void *args) /* transmit packet. */ rt_err_t lpc_emac_tx(rt_device_t dev, struct pbuf *p) { - rt_err_t result = RT_EOK; - enet_handle_t * enet_handle = &lpc_emac_device.handle; + rt_err_t result = RT_EOK; + enet_handle_t * enet_handle = &lpc_emac_device.handle; ENET_Type *enet_base = lpc_emac_device.base; uint8_t * data; - - uint16_t len; - RT_ASSERT(p != NULL); + uint16_t len; + + RT_ASSERT(p != NULL); RT_ASSERT(enet_handle != RT_NULL); if (p->tot_len > ENET_TXBUFF_SIZE) { return RT_ERROR; } - + packet_dump("TX dump", p); - + /* get free tx buffer */ { rt_err_t result; @@ -442,18 +442,18 @@ rt_err_t lpc_emac_tx(rt_device_t dev, struct pbuf *p) return RT_ERROR; } } - - // fix RxDataBuff -> TxDataBuff, ENET_RXBUFF_SIZE -> ENET_TXBUFF_SIZE + + // fix RxDataBuff -> TxDataBuff, ENET_RXBUFF_SIZE -> ENET_TXBUFF_SIZE data = (uint8_t *)ENET_ALIGN(&lpc_emac_device.TxDataBuff[lpc_emac_device.txIdx * ENET_ALIGN(ENET_TXBUFF_SIZE)]); len = pbuf_copy_partial(p, data, p->tot_len, 0); lpc_emac_device.txIdx = (lpc_emac_device.txIdx + 1) / ENET_TXBD_NUM; - - // fix 'p->len' to 'len', avoid send wrong partial packet. + + // fix 'p->len' to 'len', avoid send wrong partial packet. result = ENET_SendFrame(enet_base, enet_handle, data, len); - + if ((result == kStatus_ENET_TxFrameFail) || (result == kStatus_ENET_TxFrameOverLen) || (result == kStatus_ENET_TxFrameBusy)) { - return RT_ERROR; + return RT_ERROR; } return RT_EOK; @@ -462,22 +462,22 @@ rt_err_t lpc_emac_tx(rt_device_t dev, struct pbuf *p) /* reception packet. */ struct pbuf *lpc_emac_rx(rt_device_t dev) { - uint32_t length = 0; - status_t status; - - struct pbuf* p = RT_NULL; - enet_handle_t * enet_handle = &lpc_emac_device.handle; + uint32_t length = 0; + status_t status; + + struct pbuf* p = RT_NULL; + enet_handle_t * enet_handle = &lpc_emac_device.handle; ENET_Type *enet_base = lpc_emac_device.base; - - /* Get the Frame size */ - status = ENET_GetRxFrameSize(enet_base, enet_handle, &length, 0); - - /* Call ENET_ReadFrame when there is a received frame. */ - if (length != 0) - { - /* Received valid frame. Deliver the rx buffer with the size equal to length. */ - p = pbuf_alloc(PBUF_RAW, length, PBUF_POOL); - + + /* Get the Frame size */ + status = ENET_GetRxFrameSize(enet_base, enet_handle, &length, 0); + + /* Call ENET_ReadFrame when there is a received frame. */ + if (length != 0) + { + /* Received valid frame. Deliver the rx buffer with the size equal to length. */ + p = pbuf_alloc(PBUF_RAW, length, PBUF_POOL); + if (p != NULL) { status = ENET_ReadFrame(enet_base, enet_handle, p->payload, length, 0); @@ -496,12 +496,12 @@ struct pbuf *lpc_emac_rx(rt_device_t dev) { ETH_PRINTF(" pbuf_alloc faild\n"); } - } - else if (status == kStatus_ENET_RxFrameError) - { - ETH_PRINTF("ENET_GetRxFrameSize: kStatus_ENET_RxFrameError\n"); - ENET_ReadFrame(enet_base, enet_handle, NULL, 0, 0); - } + } + else if (status == kStatus_ENET_RxFrameError) + { + ETH_PRINTF("ENET_GetRxFrameSize: kStatus_ENET_RxFrameError\n"); + ENET_ReadFrame(enet_base, enet_handle, NULL, 0, 0); + } return NULL; } @@ -510,11 +510,11 @@ int lpc_emac_hw_init(void) { /* init tx semaphore */ rt_sem_init(&lpc_emac_device.tx_wait, "tx_wait", ENET_TXBD_NUM, RT_IPC_FLAG_FIFO); - + lpc_emac_device.phyAddr = 0; lpc_emac_device.txIdx = 0; lpc_emac_device.base = ENET; - + // OUI 00-60-37 NXP Semiconductors lpc_emac_device.dev_addr[0] = 0x00; lpc_emac_device.dev_addr[1] = 0x60; @@ -536,7 +536,7 @@ int lpc_emac_hw_init(void) lpc_emac_device.parent.eth_tx = lpc_emac_tx; eth_device_init(&(lpc_emac_device.parent), "e0"); - + return 0; } INIT_DEVICE_EXPORT(lpc_emac_hw_init); @@ -546,7 +546,7 @@ int emac_stat(void) { rt_kprintf("enter rx isr coutner : %d\n", isr_rx_counter); rt_kprintf("enter tx isr coutner : %d\n", isr_tx_counter); - + return 0; } #endif @@ -556,14 +556,14 @@ void phy_dump(void) status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr); int i; - + for (i = 0; i < 31; i++) { status_t result = kStatus_Success; uint32_t reg; - + result = PHY_Read(lpc_emac_device.base, lpc_emac_device.phyAddr, i, ®); - + if (result == kStatus_Success) { rt_kprintf("%02d: %08d\n", i, reg); @@ -630,7 +630,7 @@ void emac_dump(void) DUMP_REG(DMA_SYSBUS_MODE); DUMP_REG(DMA_INTR_STAT); DUMP_REG(DMA_DBG_STAT); - + DUMP_REG(MTL_QUEUE[0].MTL_TXQX_OP_MODE); DUMP_REG(MTL_QUEUE[0].MTL_TXQX_UNDRFLW); DUMP_REG(MTL_QUEUE[0].MTL_TXQX_DBG); @@ -660,7 +660,7 @@ void emac_dump(void) DUMP_REG(MTL_QUEUE[1].MTL_RXQX_MISSPKT_OVRFLW_CNT); DUMP_REG(MTL_QUEUE[1].MTL_RXQX_DBG); DUMP_REG(MTL_QUEUE[1].MTL_RXQX_CTRL); - + DUMP_REG(DMA_CH[0].DMA_CHX_CTRL); DUMP_REG(DMA_CH[0].DMA_CHX_TX_CTRL); DUMP_REG(DMA_CH[0].DMA_CHX_RX_CTRL); @@ -678,7 +678,7 @@ void emac_dump(void) DUMP_REG(DMA_CH[0].DMA_CHX_CUR_HST_TXBUF); DUMP_REG(DMA_CH[0].DMA_CHX_CUR_HST_RXBUF); DUMP_REG(DMA_CH[0].DMA_CHX_STAT); - + DUMP_REG(DMA_CH[1].DMA_CHX_CTRL); DUMP_REG(DMA_CH[1].DMA_CHX_TX_CTRL); DUMP_REG(DMA_CH[1].DMA_CHX_RX_CTRL); @@ -701,23 +701,23 @@ void emac_dump(void) void emac_bd_dump(void) { int i; - + rt_kprintf("rx bd dump: \n"); for (i = 0; i < ENET_RXBD_NUM; i++) { enet_rx_bd_struct_t * rx_bd = get_rx_desc(i); - rt_kprintf("buf1: %p, buf2: %p, ctrl: %08x\n", - rx_bd->buff1Addr, + rt_kprintf("buf1: %p, buf2: %p, ctrl: %08x\n", + rx_bd->buff1Addr, rx_bd->buff2Addr, rx_bd->control); } - + rt_kprintf("tx bd dump: \n"); for (i = 0; i < ENET_TXBD_NUM; i++) { enet_tx_bd_struct_t * tx_bd = get_tx_desc(i); - rt_kprintf("buf1: %p, buf2: %p, len: %08x, ctrl: %08x\n", - tx_bd->buff1Addr, + rt_kprintf("buf1: %p, buf2: %p, len: %08x, ctrl: %08x\n", + tx_bd->buff1Addr, tx_bd->buff2Addr, tx_bd->buffLen, tx_bd->controlStat); diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_emac.h b/bsp/lpc54608-LPCXpresso/drivers/drv_emac.h index efaa0ac8e3..cde6d2742e 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drv_emac.h +++ b/bsp/lpc54608-LPCXpresso/drivers/drv_emac.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_ft5406.c b/bsp/lpc54608-LPCXpresso/drivers/drv_ft5406.c index fd46a199c0..c87d2039f3 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drv_ft5406.c +++ b/bsp/lpc54608-LPCXpresso/drivers/drv_ft5406.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2017-08-08 Yang the first version */ - + #include #include #include diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_i2c.c b/bsp/lpc54608-LPCXpresso/drivers/drv_i2c.c index 39e08af2d3..1a6b5ff3b8 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drv_i2c.c +++ b/bsp/lpc54608-LPCXpresso/drivers/drv_i2c.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2017-08-08 Yang the first version */ - + #include #include #include "board.h" diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_lcd.c b/bsp/lpc54608-LPCXpresso/drivers/drv_lcd.c index c1a6660819..260fb09f0e 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drv_lcd.c +++ b/bsp/lpc54608-LPCXpresso/drivers/drv_lcd.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2017-08-08 Yang the first version */ - + #include #include #include @@ -427,7 +427,7 @@ void rt_hw_lcd_init(void) _rt_framebuffer = rt_malloc_align(sizeof(rt_uint16_t) * RT_HW_LCD_HEIGHT * RT_HW_LCD_WIDTH, 32); if (_rt_framebuffer == RT_NULL) return; /* no memory yet */ _lcd_info.bits_per_pixel = LCD_BITS_PER_PIXEL; - _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565; // RTGRAPHIC_PIXEL_FORMAT_ARGB888 + _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565; // RTGRAPHIC_PIXEL_FORMAT_ARGB888 _lcd_info.framebuffer = (void *)_rt_framebuffer; _lcd_info.width = RT_HW_LCD_WIDTH; _lcd_info.height = RT_HW_LCD_HEIGHT; diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_sd.c b/bsp/lpc54608-LPCXpresso/drivers/drv_sd.c index e1239b7899..f5efc2a9d7 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drv_sd.c +++ b/bsp/lpc54608-LPCXpresso/drivers/drv_sd.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -394,22 +394,22 @@ rt_err_t mci_hw_init(const char *device_name) rt_kprintf("SD_Init failed!\n"); return -RT_ERROR; } - - /* - follow the page: https://community.nxp.com/thread/454769 - - The issue concerns sdmmc library bug (I finally solved) in SD_Init() in the file sdmmc/src/fsl_sd.c:SD_SelectBusTiming() - calls SD_SwitchFunction() which sets block size to 64bytes (512bits).Therefore SD_SetBlockSize(card, FSL_SDMMC_DEFAULT_BLOCK_SIZE) - should be called again before SD_Init() exits. - */ - - if (kStatus_Success != SDMMC_SetBlockSize(_mci_device->card.host.base, _mci_device->card.host.transfer, FSL_SDMMC_DEFAULT_BLOCK_SIZE)) - { + + /* + follow the page: https://community.nxp.com/thread/454769 + + The issue concerns sdmmc library bug (I finally solved) in SD_Init() in the file sdmmc/src/fsl_sd.c:SD_SelectBusTiming() + calls SD_SwitchFunction() which sets block size to 64bytes (512bits).Therefore SD_SetBlockSize(card, FSL_SDMMC_DEFAULT_BLOCK_SIZE) + should be called again before SD_Init() exits. + */ + + if (kStatus_Success != SDMMC_SetBlockSize(_mci_device->card.host.base, _mci_device->card.host.transfer, FSL_SDMMC_DEFAULT_BLOCK_SIZE)) + { SD_Deinit(&_mci_device->card); memset(&_mci_device->card, 0U, sizeof(_mci_device->card)); rt_kprintf("SD_Init failed!\n"); - return -RT_ERROR; - } + return -RT_ERROR; + } /* initialize mutex lock */ rt_mutex_init(&_mci_device->lock, device_name, RT_IPC_FLAG_FIFO); diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_sd.h b/bsp/lpc54608-LPCXpresso/drivers/drv_sd.h index d36134eaa4..1fc53a7459 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drv_sd.h +++ b/bsp/lpc54608-LPCXpresso/drivers/drv_sd.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -50,7 +50,7 @@ struct mci_device { struct rt_device parent; /**< RT-Thread device struct */ struct rt_device_blk_geometry geometry; /**< sector size, sector count */ - sd_card_t card; /**< Card descriptor */ + sd_card_t card; /**< Card descriptor */ rt_event_t finish_event; /**< data send finish event*/ rt_bool_t data_error; /**< data send error*/ struct rt_mutex lock; diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_sdram.h b/bsp/lpc54608-LPCXpresso/drivers/drv_sdram.h index 4de79410b0..1d9a9db4aa 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drv_sdram.h +++ b/bsp/lpc54608-LPCXpresso/drivers/drv_sdram.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_sram.c b/bsp/lpc54608-LPCXpresso/drivers/drv_sram.c index 81f4ba6e9c..4b27d23fa1 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drv_sram.c +++ b/bsp/lpc54608-LPCXpresso/drivers/drv_sram.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_sram.h b/bsp/lpc54608-LPCXpresso/drivers/drv_sram.h index 14c87054ff..7abc19420f 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drv_sram.h +++ b/bsp/lpc54608-LPCXpresso/drivers/drv_sram.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_uart.c b/bsp/lpc54608-LPCXpresso/drivers/drv_uart.c index 7c9bd9fc7f..ce9e48fdad 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drv_uart.c +++ b/bsp/lpc54608-LPCXpresso/drivers/drv_uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -146,7 +146,7 @@ void rt_hw_uart_init(void) struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; #ifdef RT_USING_UART0 - + uart = &uart0; serial0.ops = &lpc_uart_ops; @@ -188,5 +188,5 @@ void rt_hw_uart_init(void) rt_hw_serial_register(&serial0, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, uart); -#endif +#endif } diff --git a/bsp/lpc824/applications/application.c b/bsp/lpc824/applications/application.c index f8ef7f40e3..ed7972b4d2 100644 --- a/bsp/lpc824/applications/application.c +++ b/bsp/lpc824/applications/application.c @@ -1,12 +1,12 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2009-01-05 Bernard the first version - * 2014-04-27 Bernard make code cleanup. + * 2014-04-27 Bernard make code cleanup. */ #include @@ -29,26 +29,26 @@ static struct rt_thread led_thread; #endif void rt_init_thread_entry(void* parameter) -{ +{ /* initialization RT-Thread Components */ #ifdef RT_USING_COMPONENTS_INIT rt_components_init(); #endif - + } void rt_led_thread_entry(void *parameter) { /* Initialize GPIO */ - Chip_GPIO_Init(LPC_GPIO_PORT); + Chip_GPIO_Init(LPC_GPIO_PORT); Chip_GPIO_PinSetDIR(LPC_GPIO_PORT, 0, 7, 1); Chip_GPIO_PinSetState(LPC_GPIO_PORT, 0, 7, true); - + while (1) { Chip_GPIO_PinSetState(LPC_GPIO_PORT, 0, 7, true); rt_thread_delay(RT_TICK_PER_SECOND / 2); - + Chip_GPIO_PinSetState(LPC_GPIO_PORT, 0, 7, false); rt_thread_delay(RT_TICK_PER_SECOND / 2); } @@ -64,7 +64,7 @@ int rt_application_init() INIT_STACK_SIZE, RT_THREAD_PRIORITY_MAX/3, 20); #else { - + rt_err_t result; tid = &init_thread; @@ -75,14 +75,14 @@ int rt_application_init() #endif if (tid != RT_NULL) rt_thread_startup(tid); - + #ifdef RT_USING_HEAP tid = rt_thread_create("led", rt_led_thread_entry, RT_NULL, LED_STACK_SIZE, RT_THREAD_PRIORITY_MAX/3, 20); #else { - + rt_err_t result; tid = &led_thread; diff --git a/bsp/lpc824/applications/startup.c b/bsp/lpc824/applications/startup.c index 5e95382ba0..bedc10d9e4 100644 --- a/bsp/lpc824/applications/startup.c +++ b/bsp/lpc824/applications/startup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -64,7 +64,7 @@ void rtthread_startup(void) #ifdef RT_USING_HEAP rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END); #endif - + /* init scheduler system */ rt_system_scheduler_init(); diff --git a/bsp/lpc824/drivers/board.c b/bsp/lpc824/drivers/board.c index 51656718b8..0817a3b7e8 100644 --- a/bsp/lpc824/drivers/board.c +++ b/bsp/lpc824/drivers/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -62,7 +62,7 @@ void rt_hw_board_init() #ifdef RT_USING_COMPONENTS_INIT rt_components_board_init(); #endif - + #ifdef RT_USING_CONSOLE rt_console_set_device(RT_CONSOLE_DEVICE_NAME); #endif diff --git a/bsp/lpc824/drivers/board.h b/bsp/lpc824/drivers/board.h index c8d21d94b5..d86369ce31 100644 --- a/bsp/lpc824/drivers/board.h +++ b/bsp/lpc824/drivers/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc824/drivers/usart.c b/bsp/lpc824/drivers/usart.c index 5109164a9a..54a56501c9 100644 --- a/bsp/lpc824/drivers/usart.c +++ b/bsp/lpc824/drivers/usart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -28,7 +28,7 @@ struct lpc8xx_uart LPC_USART_T * uart_base; IRQn_Type uart_irq; rt_uint8_t rx_buffer[UART_RX_BUFSZ]; - + }; #ifdef RT_USING_UART0 struct lpc8xx_uart uart0_device; @@ -45,10 +45,10 @@ struct lpc8xx_uart uart2_device; void uart_irq_handler(struct lpc8xx_uart* uart) { uint32_t status; - + /* enter interrupt */ rt_interrupt_enter(); - + status = Chip_UART_GetStatus(uart->uart_base); if(status & UART_STAT_RXRDY) // RXIRQ { @@ -57,9 +57,9 @@ void uart_irq_handler(struct lpc8xx_uart* uart) if(uart->parent.rx_indicate != RT_NULL) { uart->parent.rx_indicate(&uart->parent, rt_ringbuffer_data_len(&uart->rx_rb)); - } + } } - + /* leave interrupt */ rt_interrupt_leave(); } @@ -88,15 +88,15 @@ void UART2_IRQHandler(void) static void uart1_io_init(LPC_USART_T * uart_base) { /* Enable the clock to the Switch Matrix */ - Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SWM); - + Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SWM); + Chip_Clock_SetUARTClockDiv(1); - + #ifdef RT_USING_UART0 if (uart_base == LPC_USART0) { - Chip_SWM_MovablePinAssign(SWM_U0_TXD_O, 4); - Chip_SWM_MovablePinAssign(SWM_U0_RXD_I, 0); + Chip_SWM_MovablePinAssign(SWM_U0_TXD_O, 4); + Chip_SWM_MovablePinAssign(SWM_U0_RXD_I, 0); } else #endif @@ -104,8 +104,8 @@ static void uart1_io_init(LPC_USART_T * uart_base) #ifdef RT_USING_UART1 if (uart_base == LPC_USART1) { - Chip_SWM_MovablePinAssign(SWM_U1_TXD_O, 4); - Chip_SWM_MovablePinAssign(SWM_U1_RXD_I, 0); + Chip_SWM_MovablePinAssign(SWM_U1_TXD_O, 4); + Chip_SWM_MovablePinAssign(SWM_U1_RXD_I, 0); } else #endif @@ -113,32 +113,32 @@ static void uart1_io_init(LPC_USART_T * uart_base) #ifdef RT_USING_UART2 if (uart_base == LPC_USART2) { - Chip_SWM_MovablePinAssign(SWM_U2_TXD_O, 4); - Chip_SWM_MovablePinAssign(SWM_U2_RXD_I, 0); + Chip_SWM_MovablePinAssign(SWM_U2_TXD_O, 4); + Chip_SWM_MovablePinAssign(SWM_U2_RXD_I, 0); } else #endif { RT_ASSERT((uart_base == USART0) || (uart_base == USART2) || (uart_base == USART2)); } - - /* Disable the clock to the Switch Matrix to save power */ - Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_SWM); + + /* Disable the clock to the Switch Matrix to save power */ + Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_SWM); } static void uart_ll_init(LPC_USART_T * uart) { Chip_UART_Init(uart); Chip_UART_ConfigData(uart, UART_CFG_DATALEN_8 | UART_CFG_PARITY_NONE | UART_CFG_STOPLEN_1); - Chip_Clock_SetUSARTNBaseClockRate((115200 * 6 * 16), true); - Chip_UART_SetBaud(uart, 115200); - Chip_UART_Enable(uart); - Chip_UART_TXEnable(uart); - - // we must NOT enable TX ready/idle IRQ before we want to write data - // otherwise the IRQs will happen as soon as Uart IRQ is enabled in NVIC - Chip_UART_IntDisable(uart, UART_INTEN_TXRDY | UART_INTEN_TXIDLE); - Chip_UART_IntEnable(uart, UART_INTEN_RXRDY); + Chip_Clock_SetUSARTNBaseClockRate((115200 * 6 * 16), true); + Chip_UART_SetBaud(uart, 115200); + Chip_UART_Enable(uart); + Chip_UART_TXEnable(uart); + + // we must NOT enable TX ready/idle IRQ before we want to write data + // otherwise the IRQs will happen as soon as Uart IRQ is enabled in NVIC + Chip_UART_IntDisable(uart, UART_INTEN_TXRDY | UART_INTEN_TXIDLE); + Chip_UART_IntEnable(uart, UART_INTEN_RXRDY); } static rt_err_t rt_uart_init (rt_device_t dev) @@ -146,7 +146,7 @@ static rt_err_t rt_uart_init (rt_device_t dev) struct lpc8xx_uart* uart; RT_ASSERT(dev != RT_NULL); uart = (struct lpc8xx_uart *)dev; - + uart1_io_init(uart->uart_base); uart_ll_init(uart->uart_base); @@ -220,11 +220,11 @@ static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer if (*ptr == '\n') { while (!(Chip_UART_GetStatus(uart->uart_base) & UART_STAT_TXRDY)); - Chip_UART_SendByte(uart->uart_base, '\r'); + Chip_UART_SendByte(uart->uart_base, '\r'); } while (!(Chip_UART_GetStatus(uart->uart_base) & UART_STAT_TXRDY)); - Chip_UART_SendByte(uart->uart_base, *ptr); + Chip_UART_SendByte(uart->uart_base, *ptr); ptr ++; size --; @@ -235,7 +235,7 @@ static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer while (size) { while (!(Chip_UART_GetStatus(uart->uart_base) & UART_STAT_TXRDY)); - Chip_UART_SendByte(uart->uart_base, *ptr); + Chip_UART_SendByte(uart->uart_base, *ptr); ptr++; size--; @@ -258,14 +258,14 @@ int rt_hw_usart_init(void) uart->parent.type = RT_Device_Class_Char; uart->uart_base = LPC_USART0; uart->uart_irq = UART0_IRQn; - + rt_ringbuffer_init(&(uart->rx_rb), uart->rx_buffer, sizeof(uart->rx_buffer)); /* device interface */ - uart->parent.init = rt_uart_init; - uart->parent.open = rt_uart_open; + uart->parent.init = rt_uart_init; + uart->parent.open = rt_uart_open; uart->parent.close = rt_uart_close; - uart->parent.read = rt_uart_read; + uart->parent.read = rt_uart_read; uart->parent.write = rt_uart_write; uart->parent.control = RT_NULL; uart->parent.user_data = RT_NULL; @@ -273,7 +273,7 @@ int rt_hw_usart_init(void) rt_device_register(&uart->parent, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); } #endif - + #ifdef RT_USING_UART1 { struct lpc8xx_uart* uart; @@ -285,14 +285,14 @@ int rt_hw_usart_init(void) uart->parent.type = RT_Device_Class_Char; uart->uart_base = LPC_USART1; uart->uart_irq = UART1_IRQn; - + rt_ringbuffer_init(&(uart->rx_rb), uart->rx_buffer, sizeof(uart->rx_buffer)); /* device interface */ - uart->parent.init = rt_uart_init; - uart->parent.open = rt_uart_open; + uart->parent.init = rt_uart_init; + uart->parent.open = rt_uart_open; uart->parent.close = rt_uart_close; - uart->parent.read = rt_uart_read; + uart->parent.read = rt_uart_read; uart->parent.write = rt_uart_write; uart->parent.control = RT_NULL; uart->parent.user_data = RT_NULL; @@ -315,10 +315,10 @@ int rt_hw_usart_init(void) rt_ringbuffer_init(&(uart->rx_rb), uart->rx_buffer, sizeof(uart->rx_buffer)); /* device interface */ - uart->parent.init = rt_uart_init; - uart->parent.open = rt_uart_open; + uart->parent.init = rt_uart_init; + uart->parent.open = rt_uart_open; uart->parent.close = rt_uart_close; - uart->parent.read = rt_uart_read; + uart->parent.read = rt_uart_read; uart->parent.write = rt_uart_write; uart->parent.control = RT_NULL; uart->parent.user_data = RT_NULL; diff --git a/bsp/lpc824/drivers/usart.h b/bsp/lpc824/drivers/usart.h index 1db28e9385..7298cdab8b 100644 --- a/bsp/lpc824/drivers/usart.h +++ b/bsp/lpc824/drivers/usart.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc824/rtconfig.h b/bsp/lpc824/rtconfig.h index e8a551c2a3..d7c9608e28 100644 --- a/bsp/lpc824/rtconfig.h +++ b/bsp/lpc824/rtconfig.h @@ -6,17 +6,17 @@ // <<< Use Configuration Wizard in Context Menu >>> // Basic Configuration // Maximal level of thread priority <8-256> -// Default: 32 +// Default: 32 #define RT_THREAD_PRIORITY_MAX 8 // OS tick per second // Default: 1000 (1ms) -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 // Alignment size for CPU architecture data access -// Default: 4 +// Default: 4 #define RT_ALIGN_SIZE 4 // the max length of object name<2-16> -// Default: 8 -#define RT_NAME_MAX 8 +// Default: 8 +#define RT_NAME_MAX 8 // Using RT-Thread components initialization // Using RT-Thread components initialization #define RT_USING_COMPONENTS_INIT @@ -26,7 +26,7 @@ //#define RT_USING_USER_MAIN // // the size of main thread<1-4086> -// Default: 512 +// Default: 512 #define RT_MAIN_THREAD_STACK_SIZE 256 // @@ -64,13 +64,13 @@ #endif // The priority level of timer thread <0-31> // Default: 4 -#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_PRIO 4 // The stack size of timer thread <0-8192> // Default: 512 -#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_THREAD_STACK_SIZE 512 // The soft-timer tick per second <0-1000> // Default: 100 -#define RT_TIMER_TICK_PER_SECOND 100 +#define RT_TIMER_TICK_PER_SECOND 100 // // IPC(Inter-process communication) Configuration @@ -164,7 +164,7 @@ // the history lines of finsh thread <1-32> // the history lines of finsh thread // Default: 5 -#define FINSH_HISTORY_LINES 1 +#define FINSH_HISTORY_LINES 1 // Using symbol table in finsh shell // Using symbol table in finsh shell #define FINSH_USING_SYMTAB diff --git a/bsp/ls1bdev/applications/application.c b/bsp/ls1bdev/applications/application.c index 5c665d3f7f..f531441fcb 100644 --- a/bsp/ls1bdev/applications/application.c +++ b/bsp/ls1bdev/applications/application.c @@ -20,36 +20,36 @@ extern void rt_hw_dc_init(void); void rt_init_thread_entry(void *parameter) { #ifdef RT_USING_RTGUI - { - rt_device_t dc; + { + rt_device_t dc; - /* init Display Controller */ - rt_hw_dc_init(); + /* init Display Controller */ + rt_hw_dc_init(); - /* find Display Controller device */ - dc = rt_device_find("dc"); + /* find Display Controller device */ + dc = rt_device_find("dc"); - /* set Display Controller device as rtgui graphic driver */ - rtgui_graphic_set_device(dc); - } + /* set Display Controller device as rtgui graphic driver */ + rtgui_graphic_set_device(dc); + } #endif #ifdef RT_USING_COMPONENTS_INIT - /* initialization RT-Thread Components */ - rt_components_init(); + /* initialization RT-Thread Components */ + rt_components_init(); #endif } int rt_application_init(void) { - rt_thread_t tid; + rt_thread_t tid; - /* create initialization thread */ - tid = rt_thread_create("init", - rt_init_thread_entry, RT_NULL, - 4096, 8, 20); - if (tid != RT_NULL) - rt_thread_startup(tid); + /* create initialization thread */ + tid = rt_thread_create("init", + rt_init_thread_entry, RT_NULL, + 4096, 8, 20); + if (tid != RT_NULL) + rt_thread_startup(tid); - return 0; + return 0; } diff --git a/bsp/ls1bdev/applications/startup.c b/bsp/ls1bdev/applications/startup.c index 1dd4b19361..9f0c46aa67 100644 --- a/bsp/ls1bdev/applications/startup.c +++ b/bsp/ls1bdev/applications/startup.c @@ -13,7 +13,7 @@ #include #include "board.h" -#define A_K0BASE 0x80000000 +#define A_K0BASE 0x80000000 /** * @addtogroup Loongson LS1B diff --git a/bsp/ls1bdev/drivers/board.c b/bsp/ls1bdev/drivers/board.c index 92bb2d5146..63a827be09 100644 --- a/bsp/ls1bdev/drivers/board.c +++ b/bsp/ls1bdev/drivers/board.c @@ -19,7 +19,7 @@ /** * @addtogroup Loongson LS1B */ - + /*@{*/ /** @@ -27,14 +27,14 @@ */ void rt_hw_timer_handler(void) { - unsigned int count; + unsigned int count; - count = read_c0_compare(); - write_c0_compare(count); - write_c0_count(0); + count = read_c0_compare(); + write_c0_compare(count); + write_c0_count(0); - /* increase a OS tick */ - rt_tick_increase(); + /* increase a OS tick */ + rt_tick_increase(); } /** @@ -42,8 +42,8 @@ void rt_hw_timer_handler(void) */ void rt_hw_timer_init(void) { - write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND); - write_c0_count(0); + write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND); + write_c0_count(0); } /** @@ -52,47 +52,47 @@ void rt_hw_timer_init(void) void rt_hw_board_init(void) { #ifdef RT_USING_UART - /* init hardware UART device */ - rt_hw_uart_init(); + /* init hardware UART device */ + rt_hw_uart_init(); #endif #ifdef RT_USING_CONSOLE - /* set console device */ - rt_console_set_device("uart0"); + /* set console device */ + rt_console_set_device("uart0"); #endif - /* init operating system timer */ - rt_hw_timer_init(); + /* init operating system timer */ + rt_hw_timer_init(); - rt_kprintf("current sr: 0x%08x\n", read_c0_status()); + rt_kprintf("current sr: 0x%08x\n", read_c0_status()); } #define __raw_out_put(unr) \ - while (*ptr) \ - { \ - if (*ptr == '\n') \ - { \ - /* FIFO status, contain valid data */ \ - while (!(UART_LSR(UART##unr##_BASE) & (UARTLSR_TE | UARTLSR_TFE))); \ - /* write data */ \ - UART_DAT(UART##unr##_BASE) = '\r'; \ - } \ - /* FIFO status, contain valid data */ \ - while (!(UART_LSR(UART##unr##_BASE) & (UARTLSR_TE | UARTLSR_TFE))); \ - /* write data */ \ - UART_DAT(UART##unr##_BASE) = *ptr; \ - ptr ++; \ - } + while (*ptr) \ + { \ + if (*ptr == '\n') \ + { \ + /* FIFO status, contain valid data */ \ + while (!(UART_LSR(UART##unr##_BASE) & (UARTLSR_TE | UARTLSR_TFE))); \ + /* write data */ \ + UART_DAT(UART##unr##_BASE) = '\r'; \ + } \ + /* FIFO status, contain valid data */ \ + while (!(UART_LSR(UART##unr##_BASE) & (UARTLSR_TE | UARTLSR_TFE))); \ + /* write data */ \ + UART_DAT(UART##unr##_BASE) = *ptr; \ + ptr ++; \ + } /* UART line status register value */ -#define UARTLSR_ERROR (1 << 7) -#define UARTLSR_TE (1 << 6) -#define UARTLSR_TFE (1 << 5) -#define UARTLSR_BI (1 << 4) -#define UARTLSR_FE (1 << 3) -#define UARTLSR_PE (1 << 2) -#define UARTLSR_OE (1 << 1) -#define UARTLSR_DR (1 << 0) +#define UARTLSR_ERROR (1 << 7) +#define UARTLSR_TE (1 << 6) +#define UARTLSR_TFE (1 << 5) +#define UARTLSR_BI (1 << 4) +#define UARTLSR_FE (1 << 3) +#define UARTLSR_PE (1 << 2) +#define UARTLSR_OE (1 << 1) +#define UARTLSR_DR (1 << 0) void rt_hw_console_output(const char *ptr) { #if defined(RT_USING_UART0) diff --git a/bsp/ls1bdev/drivers/board.h b/bsp/ls1bdev/drivers/board.h index 00929788f4..d1ee3dc9a9 100644 --- a/bsp/ls1bdev/drivers/board.h +++ b/bsp/ls1bdev/drivers/board.h @@ -15,7 +15,7 @@ void rt_hw_board_init(void); /* 64M SDRAM */ -#define RT_HW_HEAP_END (0x80000000 + 64 * 1024 * 1024) -#define CPU_HZ (125 * 1000000) +#define RT_HW_HEAP_END (0x80000000 + 64 * 1024 * 1024) +#define CPU_HZ (125 * 1000000) #endif diff --git a/bsp/ls1bdev/drivers/display_controller.c b/bsp/ls1bdev/drivers/display_controller.c index cc0d58e59f..5dba114b69 100644 --- a/bsp/ls1bdev/drivers/display_controller.c +++ b/bsp/ls1bdev/drivers/display_controller.c @@ -13,24 +13,24 @@ struct vga_struct vga_mode[] = { - {/*"640x480_70.00"*/ 28560, 640, 664, 728, 816, 480, 481, 484, 500, }, - {/*"640x640_60.00"*/ 33100, 640, 672, 736, 832, 640, 641, 644, 663, }, - {/*"640x768_60.00"*/ 39690, 640, 672, 736, 832, 768, 769, 772, 795, }, - {/*"640x800_60.00"*/ 42130, 640, 680, 744, 848, 800, 801, 804, 828, }, - {/*"800x480_70.00"*/ 35840, 800, 832, 912, 1024, 480, 481, 484, 500, }, - {/*"800x600_60.00"*/ 38220, 800, 832, 912, 1024, 600, 601, 604, 622, }, - {/*"800x640_60.00"*/ 40730, 800, 832, 912, 1024, 640, 641, 644, 663, }, - {/*"832x600_60.00"*/ 40010, 832, 864, 952, 1072, 600, 601, 604, 622, }, - {/*"832x608_60.00"*/ 40520, 832, 864, 952, 1072, 608, 609, 612, 630, }, - {/*"1024x480_60.00"*/ 38170, 1024, 1048, 1152, 1280, 480, 481, 484, 497, }, - {/*"1024x600_60.00"*/ 48960, 1024, 1064, 1168, 1312, 600, 601, 604, 622, }, - {/*"1024x640_60.00"*/ 52830, 1024, 1072, 1176, 1328, 640, 641, 644, 663, }, - {/*"1024x768_60.00"*/ 64110, 1024, 1080, 1184, 1344, 768, 769, 772, 795, }, - {/*"1152x764_60.00"*/ 71380, 1152, 1208, 1328, 1504, 764, 765, 768, 791, }, - {/*"1280x800_60.00"*/ 83460, 1280, 1344, 1480, 1680, 800, 801, 804, 828, }, - {/*"1280x1024_55.00"*/ 98600, 1280, 1352, 1488, 1696, 1024, 1025, 1028, 1057, }, - {/*"1440x800_60.00"*/ 93800, 1440, 1512, 1664, 1888, 800, 801, 804, 828, }, - {/*"1440x900_67.00"*/ 120280, 1440, 1528, 1680, 1920, 900, 901, 904, 935, }, + {/*"640x480_70.00"*/ 28560, 640, 664, 728, 816, 480, 481, 484, 500, }, + {/*"640x640_60.00"*/ 33100, 640, 672, 736, 832, 640, 641, 644, 663, }, + {/*"640x768_60.00"*/ 39690, 640, 672, 736, 832, 768, 769, 772, 795, }, + {/*"640x800_60.00"*/ 42130, 640, 680, 744, 848, 800, 801, 804, 828, }, + {/*"800x480_70.00"*/ 35840, 800, 832, 912, 1024, 480, 481, 484, 500, }, + {/*"800x600_60.00"*/ 38220, 800, 832, 912, 1024, 600, 601, 604, 622, }, + {/*"800x640_60.00"*/ 40730, 800, 832, 912, 1024, 640, 641, 644, 663, }, + {/*"832x600_60.00"*/ 40010, 832, 864, 952, 1072, 600, 601, 604, 622, }, + {/*"832x608_60.00"*/ 40520, 832, 864, 952, 1072, 608, 609, 612, 630, }, + {/*"1024x480_60.00"*/ 38170, 1024, 1048, 1152, 1280, 480, 481, 484, 497, }, + {/*"1024x600_60.00"*/ 48960, 1024, 1064, 1168, 1312, 600, 601, 604, 622, }, + {/*"1024x640_60.00"*/ 52830, 1024, 1072, 1176, 1328, 640, 641, 644, 663, }, + {/*"1024x768_60.00"*/ 64110, 1024, 1080, 1184, 1344, 768, 769, 772, 795, }, + {/*"1152x764_60.00"*/ 71380, 1152, 1208, 1328, 1504, 764, 765, 768, 791, }, + {/*"1280x800_60.00"*/ 83460, 1280, 1344, 1480, 1680, 800, 801, 804, 828, }, + {/*"1280x1024_55.00"*/ 98600, 1280, 1352, 1488, 1696, 1024, 1025, 1028, 1057, }, + {/*"1440x800_60.00"*/ 93800, 1440, 1512, 1664, 1888, 800, 801, 804, 828, }, + {/*"1440x900_67.00"*/ 120280, 1440, 1528, 1680, 1920, 900, 901, 904, 935, }, }; ALIGN(16) @@ -42,189 +42,189 @@ static struct rt_device_graphic_info _dc_info; int caclulate_freq(long long XIN, long long PCLK) { - int i; - long long clk, clk1; - int start, end; - int mi; - int pll,ctrl,div,div1,frac; - - pll = PLL_FREQ; - ctrl = PLL_DIV_PARAM; - rt_kprintf("pll=0x%x, ctrl=0x%x\n", pll, ctrl); -// rt_kprintf("cpu freq is %d\n", tgt_pipefreq()); - start = -1; - end = 1; - - for (i=start; i<=end; i++) - { - clk = (12+i+(pll&0x3f))*33333333/2; - div = clk/(long)PCLK/1000; - clk1 = (12+i+1+(pll&0x3f))*33333333/2; - div1 = clk1/(long)PCLK/1000; - if (div!=div1) - break; - } - - if (div!=div1) - { - frac = ((PCLK*1000*div1)*2*1024/33333333 - (12+i+(pll&0x3f))*1024)&0x3ff; - pll = (pll & ~0x3ff3f)|(frac<<8)|((pll&0x3f)+i); - ctrl = ctrl&~(0x1f<<26)|(div1<<26)|(1<<31); - } - else - { - clk = (12+start+(pll&0x3f))*33333333/2; - clk1 = (12+end+(pll&0x3f))*33333333/2; - if (abs((long)clk/div/1000-PCLK)type = RT_Device_Class_Graphic; - dc->init = rt_dc_init; - dc->open = RT_NULL; - dc->close = RT_NULL; - dc->control = rt_dc_control; - dc->user_data = (void*)&_dc_info; - - /* register Display Controller device to RT-Thread */ - rt_device_register(dc, "dc", RT_DEVICE_FLAG_RDWR); + rt_device_t dc = rt_malloc(sizeof(struct rt_device)); + if (dc == RT_NULL) + { + rt_kprintf("dc == RT_NULL\n"); + return; /* no memory yet */ + } + + _dc_info.bits_per_pixel = 16; + _dc_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P; + _dc_info.framebuffer = (rt_uint8_t*)HW_FB_ADDR; + _dc_info.width = FB_XSIZE; + _dc_info.height = FB_YSIZE; + + /* init device structure */ + dc->type = RT_Device_Class_Graphic; + dc->init = rt_dc_init; + dc->open = RT_NULL; + dc->close = RT_NULL; + dc->control = rt_dc_control; + dc->user_data = (void*)&_dc_info; + + /* register Display Controller device to RT-Thread */ + rt_device_register(dc, "dc", RT_DEVICE_FLAG_RDWR); } diff --git a/bsp/ls1bdev/drivers/display_controller.h b/bsp/ls1bdev/drivers/display_controller.h index 671acd45a5..1fa6243a72 100644 --- a/bsp/ls1bdev/drivers/display_controller.h +++ b/bsp/ls1bdev/drivers/display_controller.h @@ -7,48 +7,48 @@ * Date Author Notes * 2011-08-08 lgnq first version for LS1B */ - + #ifndef __DISPLAY_CONTROLLER_H__ #define __DISPLAY_CONTROLLER_H__ #include #include "ls1b.h" -#define DC_BASE 0xBC301240 //Display Controller +#define DC_BASE 0xBC301240 //Display Controller /* Frame Buffer registers */ -#define DC_FB_CONFIG __REG32(DC_BASE + 0x000) -#define DC_FB_BUFFER_ADDR0 __REG32(DC_BASE + 0x020) -#define DC_FB_BUFFER_STRIDE __REG32(DC_BASE + 0x040) -#define DC_FB_BUFFER_ORIGIN __REG32(DC_BASE + 0x060) -#define DC_DITHER_CONFIG __REG32(DC_BASE + 0x120) -#define DC_DITHER_TABLE_LOW __REG32(DC_BASE + 0x140) -#define DC_DITHER_TABLE_HIGH __REG32(DC_BASE + 0x160) -#define DC_PANEL_CONFIG __REG32(DC_BASE + 0x180) -#define DC_PANEL_TIMING __REG32(DC_BASE + 0x1A0) -#define DC_HDISPLAY __REG32(DC_BASE + 0x1C0) -#define DC_HSYNC __REG32(DC_BASE + 0x1E0) -#define DC_VDISPLAY __REG32(DC_BASE + 0x240) -#define DC_VSYNC __REG32(DC_BASE + 0x260) -#define DC_FB_BUFFER_ADDR1 __REG32(DC_BASE + 0x340) +#define DC_FB_CONFIG __REG32(DC_BASE + 0x000) +#define DC_FB_BUFFER_ADDR0 __REG32(DC_BASE + 0x020) +#define DC_FB_BUFFER_STRIDE __REG32(DC_BASE + 0x040) +#define DC_FB_BUFFER_ORIGIN __REG32(DC_BASE + 0x060) +#define DC_DITHER_CONFIG __REG32(DC_BASE + 0x120) +#define DC_DITHER_TABLE_LOW __REG32(DC_BASE + 0x140) +#define DC_DITHER_TABLE_HIGH __REG32(DC_BASE + 0x160) +#define DC_PANEL_CONFIG __REG32(DC_BASE + 0x180) +#define DC_PANEL_TIMING __REG32(DC_BASE + 0x1A0) +#define DC_HDISPLAY __REG32(DC_BASE + 0x1C0) +#define DC_HSYNC __REG32(DC_BASE + 0x1E0) +#define DC_VDISPLAY __REG32(DC_BASE + 0x240) +#define DC_VSYNC __REG32(DC_BASE + 0x260) +#define DC_FB_BUFFER_ADDR1 __REG32(DC_BASE + 0x340) /* Display Controller driver for 1024x768 16bit */ -#define FB_XSIZE 1024 -#define FB_YSIZE 768 +#define FB_XSIZE 1024 +#define FB_YSIZE 768 #define CONFIG_VIDEO_16BPP #define APB_CLK 33333333 -#define K1BASE 0xA0000000 -#define KSEG1(addr) ((void *)(K1BASE | (rt_uint32_t)(addr))) -#define HW_FB_ADDR KSEG1(_rt_framebuffer) -#define HW_FB_PIXEL(x, y) *(volatile rt_uint16_t*)((rt_uint8_t*)HW_FB_ADDR + (y * FB_XSIZE * 2) + x * 2) +#define K1BASE 0xA0000000 +#define KSEG1(addr) ((void *)(K1BASE | (rt_uint32_t)(addr))) +#define HW_FB_ADDR KSEG1(_rt_framebuffer) +#define HW_FB_PIXEL(x, y) *(volatile rt_uint16_t*)((rt_uint8_t*)HW_FB_ADDR + (y * FB_XSIZE * 2) + x * 2) struct vga_struct { - long pclk; - int hr,hss,hse,hfl; - int vr,vss,vse,vfl; + long pclk; + int hr,hss,hse,hfl; + int vr,vss,vse,vfl; }; #endif diff --git a/bsp/ls1bdev/drivers/uart.c b/bsp/ls1bdev/drivers/uart.c index deedc981c4..066acd9bcb 100644 --- a/bsp/ls1bdev/drivers/uart.c +++ b/bsp/ls1bdev/drivers/uart.c @@ -23,253 +23,253 @@ struct rt_uart_ls1b { - struct rt_device parent; + struct rt_device parent; - rt_uint32_t hw_base; - rt_uint32_t irq; + rt_uint32_t hw_base; + rt_uint32_t irq; - /* buffer for reception */ - rt_uint8_t read_index, save_index; - rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; + /* buffer for reception */ + rt_uint8_t read_index, save_index; + rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; }uart_device; static void rt_uart_irqhandler(int irqno, void *param) { - rt_ubase_t level; - rt_uint8_t isr; - struct rt_uart_ls1b *uart = &uart_device; - - /* read interrupt status and clear it */ - isr = UART_IIR(uart->hw_base); - isr = (isr >> 1) & 0x3; - - /* receive data available */ - if (isr & 0x02) - { - /* Receive Data Available */ - while (UART_LSR(uart->hw_base) & UARTLSR_DR) - { - uart->rx_buffer[uart->save_index] = UART_DAT(uart->hw_base); - - level = rt_hw_interrupt_disable(); - uart->save_index ++; - if (uart->save_index >= RT_UART_RX_BUFFER_SIZE) - uart->save_index = 0; - rt_hw_interrupt_enable(level); - } - - /* invoke callback */ - if (uart->parent.rx_indicate != RT_NULL) - { - rt_size_t length; - if (uart->read_index > uart->save_index) - length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index; - else - length = uart->save_index - uart->read_index; - - uart->parent.rx_indicate(&uart->parent, length); - } - } - - return; + rt_ubase_t level; + rt_uint8_t isr; + struct rt_uart_ls1b *uart = &uart_device; + + /* read interrupt status and clear it */ + isr = UART_IIR(uart->hw_base); + isr = (isr >> 1) & 0x3; + + /* receive data available */ + if (isr & 0x02) + { + /* Receive Data Available */ + while (UART_LSR(uart->hw_base) & UARTLSR_DR) + { + uart->rx_buffer[uart->save_index] = UART_DAT(uart->hw_base); + + level = rt_hw_interrupt_disable(); + uart->save_index ++; + if (uart->save_index >= RT_UART_RX_BUFFER_SIZE) + uart->save_index = 0; + rt_hw_interrupt_enable(level); + } + + /* invoke callback */ + if (uart->parent.rx_indicate != RT_NULL) + { + rt_size_t length; + if (uart->read_index > uart->save_index) + length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index; + else + length = uart->save_index - uart->read_index; + + uart->parent.rx_indicate(&uart->parent, length); + } + } + + return; } static rt_err_t rt_uart_init(rt_device_t dev) { - rt_uint32_t baud_div; - struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev; + rt_uint32_t baud_div; + struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev; - RT_ASSERT(uart != RT_NULL); + RT_ASSERT(uart != RT_NULL); #if 0 - /* init UART Hardware */ - UART_IER(uart->hw_base) = 0; /* clear interrupt */ - UART_FCR(uart->hw_base) = 0x60; /* reset UART Rx/Tx */ + /* init UART Hardware */ + UART_IER(uart->hw_base) = 0; /* clear interrupt */ + UART_FCR(uart->hw_base) = 0x60; /* reset UART Rx/Tx */ - /* enable UART clock */ - /* set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */ - UART_LCR(uart->hw_base) = 0x3; + /* enable UART clock */ + /* set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */ + UART_LCR(uart->hw_base) = 0x3; - /* set baudrate */ - baud_div = DEV_CLK / 16 / UART_BAUDRATE; - UART_LCR(uart->hw_base) |= UARTLCR_DLAB; + /* set baudrate */ + baud_div = DEV_CLK / 16 / UART_BAUDRATE; + UART_LCR(uart->hw_base) |= UARTLCR_DLAB; - UART_MSB(uart->hw_base) = (baud_div >> 8) & 0xff; - UART_LSB(uart->hw_base) = baud_div & 0xff; + UART_MSB(uart->hw_base) = (baud_div >> 8) & 0xff; + UART_LSB(uart->hw_base) = baud_div & 0xff; - UART_LCR(uart->hw_base) &= ~UARTLCR_DLAB; + UART_LCR(uart->hw_base) &= ~UARTLCR_DLAB; - /* Enable UART unit, enable and clear FIFO */ - UART_FCR(uart->hw_base) = UARTFCR_UUE | UARTFCR_FE | UARTFCR_TFLS | UARTFCR_RFLS; + /* Enable UART unit, enable and clear FIFO */ + UART_FCR(uart->hw_base) = UARTFCR_UUE | UARTFCR_FE | UARTFCR_TFLS | UARTFCR_RFLS; #endif - return RT_EOK; + return RT_EOK; } static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag) { - struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev; - - RT_ASSERT(uart != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* Enable the UART Interrupt */ - UART_IER(uart->hw_base) |= UARTIER_IRXE; - - /* install interrupt */ - rt_hw_interrupt_install(uart->irq, rt_uart_irqhandler, RT_NULL, "UART"); - rt_hw_interrupt_umask(uart->irq); - } - return RT_EOK; + struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev; + + RT_ASSERT(uart != RT_NULL); + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* Enable the UART Interrupt */ + UART_IER(uart->hw_base) |= UARTIER_IRXE; + + /* install interrupt */ + rt_hw_interrupt_install(uart->irq, rt_uart_irqhandler, RT_NULL, "UART"); + rt_hw_interrupt_umask(uart->irq); + } + return RT_EOK; } static rt_err_t rt_uart_close(rt_device_t dev) { - struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev; + struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev; - RT_ASSERT(uart != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* Disable the UART Interrupt */ - UART_IER(uart->hw_base) &= ~(UARTIER_IRXE); - } + RT_ASSERT(uart != RT_NULL); + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* Disable the UART Interrupt */ + UART_IER(uart->hw_base) &= ~(UARTIER_IRXE); + } - return RT_EOK; + return RT_EOK; } static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) { - rt_uint8_t *ptr; - struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev; - - RT_ASSERT(uart != RT_NULL); - - /* point to buffer */ - ptr = (rt_uint8_t *)buffer; - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - while (size) - { - /* interrupt receive */ - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - if (uart->read_index != uart->save_index) - { - *ptr = uart->rx_buffer[uart->read_index]; - - uart->read_index ++; - if (uart->read_index >= RT_UART_RX_BUFFER_SIZE) - uart->read_index = 0; - } - else - { - /* no data in rx buffer */ - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - break; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - - ptr ++; - size --; - } - - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; - } - - return 0; + rt_uint8_t *ptr; + struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev; + + RT_ASSERT(uart != RT_NULL); + + /* point to buffer */ + ptr = (rt_uint8_t *)buffer; + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + while (size) + { + /* interrupt receive */ + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + if (uart->read_index != uart->save_index) + { + *ptr = uart->rx_buffer[uart->read_index]; + + uart->read_index ++; + if (uart->read_index >= RT_UART_RX_BUFFER_SIZE) + uart->read_index = 0; + } + else + { + /* no data in rx buffer */ + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + ptr ++; + size --; + } + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + } + + return 0; } static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) { - char *ptr; - struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev; - - RT_ASSERT(uart != RT_NULL); - - ptr = (char *)buffer; - - if (dev->flag & RT_DEVICE_FLAG_STREAM) - { - /* stream mode */ - while (size) - { - if (*ptr == '\n') - { - /* FIFO status, contain valid data */ - while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE))); - /* write data */ - UART_DAT(uart->hw_base) = '\r'; - } - - /* FIFO status, contain valid data */ - while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE))); - /* write data */ - UART_DAT(uart->hw_base) = *ptr; - - ptr ++; - size --; - } - } - else - { - while (size != 0) - { - /* FIFO status, contain valid data */ - while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE))); - - /* write data */ - UART_DAT(uart->hw_base) = *ptr; - - ptr++; - size--; - } - } - - return (rt_size_t)ptr - (rt_size_t)buffer; + char *ptr; + struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev; + + RT_ASSERT(uart != RT_NULL); + + ptr = (char *)buffer; + + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* stream mode */ + while (size) + { + if (*ptr == '\n') + { + /* FIFO status, contain valid data */ + while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE))); + /* write data */ + UART_DAT(uart->hw_base) = '\r'; + } + + /* FIFO status, contain valid data */ + while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE))); + /* write data */ + UART_DAT(uart->hw_base) = *ptr; + + ptr ++; + size --; + } + } + else + { + while (size != 0) + { + /* FIFO status, contain valid data */ + while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE))); + + /* write data */ + UART_DAT(uart->hw_base) = *ptr; + + ptr++; + size--; + } + } + + return (rt_size_t)ptr - (rt_size_t)buffer; } void rt_hw_uart_init(void) { - struct rt_uart_ls1b *uart; + struct rt_uart_ls1b *uart; - /* get uart device */ - uart = &uart_device; + /* get uart device */ + uart = &uart_device; - /* device initialization */ - uart->parent.type = RT_Device_Class_Char; - rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer)); - uart->read_index = uart->save_index = 0; + /* device initialization */ + uart->parent.type = RT_Device_Class_Char; + rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer)); + uart->read_index = uart->save_index = 0; #if defined(RT_USING_UART0) - uart->hw_base = UART0_BASE; - uart->irq = LS1B_UART0_IRQ; + uart->hw_base = UART0_BASE; + uart->irq = LS1B_UART0_IRQ; #elif defined(RT_USING_UART1) - uart->hw_base = UART1_BASE; - uart->irq = LS1B_UART1_IRQ; + uart->hw_base = UART1_BASE; + uart->irq = LS1B_UART1_IRQ; #elif defined(RT_USING_UART3) - uart->hw_base = UART3_BASE; - uart->irq = LS1B_UART3_IRQ; + uart->hw_base = UART3_BASE; + uart->irq = LS1B_UART3_IRQ; #endif - /* device interface */ - uart->parent.init = rt_uart_init; - uart->parent.open = rt_uart_open; - uart->parent.close = rt_uart_close; - uart->parent.read = rt_uart_read; - uart->parent.write = rt_uart_write; - uart->parent.control = RT_NULL; - uart->parent.user_data = RT_NULL; - - rt_device_register(&uart->parent, "uart0", - RT_DEVICE_FLAG_RDWR | - RT_DEVICE_FLAG_STREAM | - RT_DEVICE_FLAG_INT_RX); + /* device interface */ + uart->parent.init = rt_uart_init; + uart->parent.open = rt_uart_open; + uart->parent.close = rt_uart_close; + uart->parent.read = rt_uart_read; + uart->parent.write = rt_uart_write; + uart->parent.control = RT_NULL; + uart->parent.user_data = RT_NULL; + + rt_device_register(&uart->parent, "uart0", + RT_DEVICE_FLAG_RDWR | + RT_DEVICE_FLAG_STREAM | + RT_DEVICE_FLAG_INT_RX); } #endif /* end of UART */ diff --git a/bsp/ls1bdev/drivers/uart.h b/bsp/ls1bdev/drivers/uart.h index 402b3eac88..0347b3db4d 100644 --- a/bsp/ls1bdev/drivers/uart.h +++ b/bsp/ls1bdev/drivers/uart.h @@ -13,81 +13,81 @@ #include "ls1b.h" -#define UART0_BASE 0xBFE40000 -#define UART0_1_BASE 0xBFE41000 -#define UART0_2_BASE 0xBFE42000 -#define UART0_3_BASE 0xBFE43000 -#define UART1_BASE 0xBFE44000 -#define UART1_1_BASE 0xBFE45000 -#define UART1_2_BASE 0xBFE46000 -#define UART1_3_BASE 0xBFE47000 -#define UART2_BASE 0xBFE48000 -#define UART3_BASE 0xBFE4C000 -#define UART4_BASE 0xBFE6C000 -#define UART5_BASE 0xBFE7C000 +#define UART0_BASE 0xBFE40000 +#define UART0_1_BASE 0xBFE41000 +#define UART0_2_BASE 0xBFE42000 +#define UART0_3_BASE 0xBFE43000 +#define UART1_BASE 0xBFE44000 +#define UART1_1_BASE 0xBFE45000 +#define UART1_2_BASE 0xBFE46000 +#define UART1_3_BASE 0xBFE47000 +#define UART2_BASE 0xBFE48000 +#define UART3_BASE 0xBFE4C000 +#define UART4_BASE 0xBFE6C000 +#define UART5_BASE 0xBFE7C000 /* UART registers */ -#define UART_DAT(base) __REG8(base + 0x00) -#define UART_IER(base) __REG8(base + 0x01) -#define UART_IIR(base) __REG8(base + 0x02) -#define UART_FCR(base) __REG8(base + 0x02) -#define UART_LCR(base) __REG8(base + 0x03) -#define UART_MCR(base) __REG8(base + 0x04) -#define UART_LSR(base) __REG8(base + 0x05) -#define UART_MSR(base) __REG8(base + 0x06) +#define UART_DAT(base) __REG8(base + 0x00) +#define UART_IER(base) __REG8(base + 0x01) +#define UART_IIR(base) __REG8(base + 0x02) +#define UART_FCR(base) __REG8(base + 0x02) +#define UART_LCR(base) __REG8(base + 0x03) +#define UART_MCR(base) __REG8(base + 0x04) +#define UART_LSR(base) __REG8(base + 0x05) +#define UART_MSR(base) __REG8(base + 0x06) -#define UART_LSB(base) __REG8(base + 0x00) -#define UART_MSB(base) __REG8(base + 0x01) +#define UART_LSB(base) __REG8(base + 0x00) +#define UART_MSB(base) __REG8(base + 0x01) /* UART0 registers */ -#define UART0_DAT __REG8(UART0_BASE + 0x00) -#define UART0_IER __REG8(UART0_BASE + 0x01) -#define UART0_IIR __REG8(UART0_BASE + 0x02) -#define UART0_FCR __REG8(UART0_BASE + 0x02) -#define UART0_LCR __REG8(UART0_BASE + 0x03) -#define UART0_MCR __REG8(UART0_BASE + 0x04) -#define UART0_LSR __REG8(UART0_BASE + 0x05) -#define UART0_MSR __REG8(UART0_BASE + 0x06) +#define UART0_DAT __REG8(UART0_BASE + 0x00) +#define UART0_IER __REG8(UART0_BASE + 0x01) +#define UART0_IIR __REG8(UART0_BASE + 0x02) +#define UART0_FCR __REG8(UART0_BASE + 0x02) +#define UART0_LCR __REG8(UART0_BASE + 0x03) +#define UART0_MCR __REG8(UART0_BASE + 0x04) +#define UART0_LSR __REG8(UART0_BASE + 0x05) +#define UART0_MSR __REG8(UART0_BASE + 0x06) -#define UART0_LSB __REG8(UART0_BASE + 0x00) -#define UART0_MSB __REG8(UART0_BASE + 0x01) +#define UART0_LSB __REG8(UART0_BASE + 0x00) +#define UART0_MSB __REG8(UART0_BASE + 0x01) /* UART1 registers */ -#define UART1_DAT __REG8(UART1_BASE + 0x00) -#define UART1_IER __REG8(UART1_BASE + 0x01) -#define UART1_IIR __REG8(UART1_BASE + 0x02) -#define UART1_FCR __REG8(UART1_BASE + 0x02) -#define UART1_LCR __REG8(UART1_BASE + 0x03) -#define UART1_MCR __REG8(UART1_BASE + 0x04) -#define UART1_LSR __REG8(UART1_BASE + 0x05) -#define UART1_MSR __REG8(UART1_BASE + 0x06) +#define UART1_DAT __REG8(UART1_BASE + 0x00) +#define UART1_IER __REG8(UART1_BASE + 0x01) +#define UART1_IIR __REG8(UART1_BASE + 0x02) +#define UART1_FCR __REG8(UART1_BASE + 0x02) +#define UART1_LCR __REG8(UART1_BASE + 0x03) +#define UART1_MCR __REG8(UART1_BASE + 0x04) +#define UART1_LSR __REG8(UART1_BASE + 0x05) +#define UART1_MSR __REG8(UART1_BASE + 0x06) -#define UART1_LSB __REG8(UART1_BASE + 0x00) -#define UART1_MSB __REG8(UART1_BASE + 0x01) +#define UART1_LSB __REG8(UART1_BASE + 0x00) +#define UART1_MSB __REG8(UART1_BASE + 0x01) /* UART interrupt enable register value */ -#define UARTIER_IME (1 << 3) -#define UARTIER_ILE (1 << 2) -#define UARTIER_ITXE (1 << 1) -#define UARTIER_IRXE (1 << 0) +#define UARTIER_IME (1 << 3) +#define UARTIER_ILE (1 << 2) +#define UARTIER_ITXE (1 << 1) +#define UARTIER_IRXE (1 << 0) /* UART line control register value */ -#define UARTLCR_DLAB (1 << 7) -#define UARTLCR_BCB (1 << 6) -#define UARTLCR_SPB (1 << 5) -#define UARTLCR_EPS (1 << 4) -#define UARTLCR_PE (1 << 3) -#define UARTLCR_SB (1 << 2) +#define UARTLCR_DLAB (1 << 7) +#define UARTLCR_BCB (1 << 6) +#define UARTLCR_SPB (1 << 5) +#define UARTLCR_EPS (1 << 4) +#define UARTLCR_PE (1 << 3) +#define UARTLCR_SB (1 << 2) /* UART line status register value */ -#define UARTLSR_ERROR (1 << 7) -#define UARTLSR_TE (1 << 6) -#define UARTLSR_TFE (1 << 5) -#define UARTLSR_BI (1 << 4) -#define UARTLSR_FE (1 << 3) -#define UARTLSR_PE (1 << 2) -#define UARTLSR_OE (1 << 1) -#define UARTLSR_DR (1 << 0) +#define UARTLSR_ERROR (1 << 7) +#define UARTLSR_TE (1 << 6) +#define UARTLSR_TFE (1 << 5) +#define UARTLSR_BI (1 << 4) +#define UARTLSR_FE (1 << 3) +#define UARTLSR_PE (1 << 2) +#define UARTLSR_OE (1 << 1) +#define UARTLSR_DR (1 << 0) void rt_hw_uart_init(void); diff --git a/bsp/ls1cdev/applications/main.c b/bsp/ls1cdev/applications/main.c index fac004d832..2b0792b6e2 100644 --- a/bsp/ls1cdev/applications/main.c +++ b/bsp/ls1cdev/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -11,7 +11,7 @@ #include int main(int argc, char** argv) -{ +{ return 0; } diff --git a/bsp/ls1cdev/drivers/board.c b/bsp/ls1cdev/drivers/board.c index b4b8403b49..5703a1baa6 100644 --- a/bsp/ls1cdev/drivers/board.c +++ b/bsp/ls1cdev/drivers/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,7 +17,7 @@ #include "drv_uart.h" #include "ls1c.h" -#define A_K0BASE 0x80000000 +#define A_K0BASE 0x80000000 extern unsigned char __bss_end; @@ -34,14 +34,14 @@ extern void invalidate_icache_all(void); */ void rt_hw_timer_handler(void) { - unsigned int count; + unsigned int count; - count = read_c0_compare(); - write_c0_compare(count); - write_c0_count(0); + count = read_c0_compare(); + write_c0_compare(count); + write_c0_count(0); - /* increase a OS tick */ - rt_tick_increase(); + /* increase a OS tick */ + rt_tick_increase(); } /** @@ -49,8 +49,8 @@ void rt_hw_timer_handler(void) */ void rt_hw_timer_init(void) { - write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND); - write_c0_count(0); + write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND); + write_c0_count(0); } @@ -83,35 +83,35 @@ void rt_hw_fpu_init(void) */ void rt_hw_board_init(void) { - /* init cache */ - rt_hw_cache_init(); - - /* init hardware interrupt */ - rt_hw_interrupt_init(); - - /* clear bev */ - write_c0_status(read_c0_status()&(~(1<<22))); - - /* copy vector */ - rt_memcpy((void *)A_K0BASE, tlb_refill_exception, 0x80); - rt_memcpy((void *)(A_K0BASE + 0x180), general_exception, 0x80); - rt_memcpy((void *)(A_K0BASE + 0x200), irq_exception, 0x80); - - invalidate_writeback_dcache_all(); - invalidate_icache_all(); - + /* init cache */ + rt_hw_cache_init(); + + /* init hardware interrupt */ + rt_hw_interrupt_init(); + + /* clear bev */ + write_c0_status(read_c0_status()&(~(1<<22))); + + /* copy vector */ + rt_memcpy((void *)A_K0BASE, tlb_refill_exception, 0x80); + rt_memcpy((void *)(A_K0BASE + 0x180), general_exception, 0x80); + rt_memcpy((void *)(A_K0BASE + 0x200), irq_exception, 0x80); + + invalidate_writeback_dcache_all(); + invalidate_icache_all(); + #ifdef RT_USING_HEAP - rt_system_heap_init((void*)&__bss_end, (void*)RT_HW_HEAP_END); + rt_system_heap_init((void*)&__bss_end, (void*)RT_HW_HEAP_END); #endif #ifdef RT_USING_SERIAL - /* init hardware UART device */ - rt_hw_uart_init(); + /* init hardware UART device */ + rt_hw_uart_init(); #endif #ifdef RT_USING_CONSOLE - /* set console device */ - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + /* set console device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); #endif /* init operating system timer */ rt_hw_timer_init(); diff --git a/bsp/ls1cdev/drivers/board.h b/bsp/ls1cdev/drivers/board.h index 35c53f2a06..c239e42386 100644 --- a/bsp/ls1cdev/drivers/board.h +++ b/bsp/ls1cdev/drivers/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/ls1cdev/drivers/display_controller.c b/bsp/ls1cdev/drivers/display_controller.c index 2a0bfcc619..2b6f1c543d 100644 --- a/bsp/ls1cdev/drivers/display_controller.c +++ b/bsp/ls1cdev/drivers/display_controller.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2011-08-09 lgnq first version for LS1B DC * 2015-07-06 chinesebear modified for loongson 1c - * 2018-01-06 sundm75 modified for smartloong + * 2018-01-06 sundm75 modified for smartloong */ #include @@ -78,13 +78,13 @@ int caclulate_freq(rt_uint32_t XIN, rt_uint32_t PCLK) pix_div = (pix_div>>24)&0xff; rt_kprintf("old pll_clk=%d, pix_div=%d\n", pll_clk, pix_div); - divider_int = pll_clk/(1000000) *PCLK/1000; + divider_int = pll_clk/(1000000) *PCLK/1000; if(divider_int%1000>=500) divider_int = divider_int/1000+1; else divider_int = divider_int/1000; rt_kprintf("divider_int = %d\n", divider_int); - + /* check whether divisor is too small. */ if (divider_int < 1) { rt_kprintf("Warning: clock source is too slow.Try smaller resolution\n"); @@ -102,9 +102,9 @@ int caclulate_freq(rt_uint32_t XIN, rt_uint32_t PCLK) regval &= ~0x80000030; //PIX_DIV_VALID PIX_SEL 置0 regval &= ~(0x3f<<24); //PIX_DIV 清零 regval |= divider_int << 24; - PLL_DIV_PARAM = regval; + PLL_DIV_PARAM = regval; regval |= 0x80000030; //PIX_DIV_VALID PIX_SEL 置1 - PLL_DIV_PARAM = regval; + PLL_DIV_PARAM = regval; } rt_kprintf("new PLL_FREQ=0x%x, PLL_DIV_PARAM=0x%x\n", PLL_FREQ, PLL_DIV_PARAM); rt_thread_delay(10); @@ -115,11 +115,11 @@ static rt_err_t rt_dc_init(rt_device_t dev) { int i, out, mode=-1; int val; - + rt_kprintf("PWM initied\n"); /* Set the back light PWM. */ pwminit(); - + for (i=0; iclose = RT_NULL; dc->control = rt_dc_control; dc->user_data = (void*)&_dc_info; - + /* register Display Controller device to RT-Thread */ rt_device_register(dc, "dc", RT_DEVICE_FLAG_RDWR); - + rt_device_init(dc); } @@ -250,7 +250,7 @@ int rtgui_lcd_init(void) pin_set_purpose(76, PIN_PURPOSE_OTHER); pin_set_remap(76, PIN_REMAP_DEFAULT); - + /* init Display Controller */ rt_hw_dc_init(); @@ -259,7 +259,7 @@ int rtgui_lcd_init(void) /* set Display Controller device as rtgui graphic driver */ rtgui_graphic_set_device(dc); - + return 0; } diff --git a/bsp/ls1cdev/drivers/display_controller.h b/bsp/ls1cdev/drivers/display_controller.h index 39f6ae8d52..a20d964047 100644 --- a/bsp/ls1cdev/drivers/display_controller.h +++ b/bsp/ls1cdev/drivers/display_controller.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,9 +7,9 @@ * Date Author Notes * 2011-08-08 lgnq first version for LS1B * 2015-07-06 chinesebear modified for loongson 1c - * 2018-01-06 sundm75 modified for smartloong + * 2018-01-06 sundm75 modified for smartloong */ - + #ifndef __DISPLAY_CONTROLLER_H__ #define __DISPLAY_CONTROLLER_H__ @@ -19,31 +19,31 @@ #define DC_BASE 0xBC301240 //Display Controller /* Frame Buffer registers */ -#define DC_FB_CONFIG __REG32(DC_BASE + 0x000) -#define DC_FB_BUFFER_ADDR0 __REG32(DC_BASE + 0x020) -#define DC_FB_BUFFER_STRIDE __REG32(DC_BASE + 0x040) -#define DC_FB_BUFFER_ORIGIN __REG32(DC_BASE + 0x060) -#define DC_DITHER_CONFIG __REG32(DC_BASE + 0x120) -#define DC_DITHER_TABLE_LOW __REG32(DC_BASE + 0x140) -#define DC_DITHER_TABLE_HIGH __REG32(DC_BASE + 0x160) -#define DC_PANEL_CONFIG __REG32(DC_BASE + 0x180) -#define DC_PANEL_TIMING __REG32(DC_BASE + 0x1A0) -#define DC_HDISPLAY __REG32(DC_BASE + 0x1C0) -#define DC_HSYNC __REG32(DC_BASE + 0x1E0) -#define DC_VDISPLAY __REG32(DC_BASE + 0x240) -#define DC_VSYNC __REG32(DC_BASE + 0x260) -#define DC_FB_BUFFER_ADDR1 __REG32(DC_BASE + 0x340) +#define DC_FB_CONFIG __REG32(DC_BASE + 0x000) +#define DC_FB_BUFFER_ADDR0 __REG32(DC_BASE + 0x020) +#define DC_FB_BUFFER_STRIDE __REG32(DC_BASE + 0x040) +#define DC_FB_BUFFER_ORIGIN __REG32(DC_BASE + 0x060) +#define DC_DITHER_CONFIG __REG32(DC_BASE + 0x120) +#define DC_DITHER_TABLE_LOW __REG32(DC_BASE + 0x140) +#define DC_DITHER_TABLE_HIGH __REG32(DC_BASE + 0x160) +#define DC_PANEL_CONFIG __REG32(DC_BASE + 0x180) +#define DC_PANEL_TIMING __REG32(DC_BASE + 0x1A0) +#define DC_HDISPLAY __REG32(DC_BASE + 0x1C0) +#define DC_HSYNC __REG32(DC_BASE + 0x1E0) +#define DC_VDISPLAY __REG32(DC_BASE + 0x240) +#define DC_VSYNC __REG32(DC_BASE + 0x260) +#define DC_FB_BUFFER_ADDR1 __REG32(DC_BASE + 0x340) /* Display Controller driver for 1024x768 16bit */ -#define FB_XSIZE 480 -#define FB_YSIZE 272 +#define FB_XSIZE 480 +#define FB_YSIZE 272 #define CONFIG_VIDEO_16BPP -#define OSC 24000000 /* Hz */ +#define OSC 24000000 /* Hz */ -#define K1BASE 0xA0000000 -#define KSEG1(addr) ((void *)(K1BASE | (rt_uint32_t)(addr))) -#define HW_FB_ADDR KSEG1(_rt_framebuffer) +#define K1BASE 0xA0000000 +#define KSEG1(addr) ((void *)(K1BASE | (rt_uint32_t)(addr))) +#define HW_FB_ADDR KSEG1(_rt_framebuffer) struct vga_struct { diff --git a/bsp/ls1cdev/drivers/drv_can.c b/bsp/ls1cdev/drivers/drv_can.c index 66388b4ea8..c82fd28657 100644 --- a/bsp/ls1cdev/drivers/drv_can.c +++ b/bsp/ls1cdev/drivers/drv_can.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -40,7 +40,7 @@ static rt_err_t bxmodifyfilter(struct ls1c_bxcan *pbxcan, struct rt_can_filter_i rt_int32_t hdr, fbase, foff; CAN_TypeDef* CANx; CANx = pbxcan->reg; - + /*pitem->mode 1-掩码模式; 0- 滤波器模式 SJA1000中使用以下方式*/ /*SJA1000中AFM 1-单滤波器模式; 0- 双滤波器模式 */ @@ -72,7 +72,7 @@ static rt_err_t bxmodifyfilter(struct ls1c_bxcan *pbxcan, struct rt_can_filter_i } CAN_FilterInitTypeDef CAN_FilterInitStruct; - unsigned char ide, rtr, id , idmask, mode; + unsigned char ide, rtr, id , idmask, mode; ide = (unsigned char) pitem->ide; rtr = (unsigned char) pitem->rtr; id = pitem->id; @@ -84,7 +84,7 @@ static rt_err_t bxmodifyfilter(struct ls1c_bxcan *pbxcan, struct rt_can_filter_i CAN_FilterInitStruct.IDMASK = idmask; CAN_FilterInitStruct.MODE = mode; CAN_FilterInit(CANx, &CAN_FilterInitStruct); - + return RT_EOK; } @@ -109,15 +109,15 @@ static rt_err_t setfilter(struct ls1c_bxcan *pbxcan, struct rt_can_filter_config static void bxcan0_filter_init(struct rt_can_device *can) { struct ls1c_bxcan *pbxcan; - pbxcan = (struct ls1c_bxcan *) can->parent.user_data; - + pbxcan = (struct ls1c_bxcan *) can->parent.user_data; + } static void bxcan1_filter_init(struct rt_can_device *can) { struct ls1c_bxcan *pbxcan; - pbxcan = (struct ls1c_bxcan *) can->parent.user_data; - + pbxcan = (struct ls1c_bxcan *) can->parent.user_data; + } static void bxcan_init(CAN_TypeDef *pcan, rt_uint32_t baud, rt_uint32_t mode) @@ -161,7 +161,7 @@ static void bxcan_init(CAN_TypeDef *pcan, rt_uint32_t baud, rt_uint32_t mode) break; case RT_CAN_MODE_LOOPBACK: CAN_InitStructure.CAN_Mode = CAN_Mode_STM; - + break; case RT_CAN_MODE_LOOPBACKANLISEN: CAN_InitStructure.CAN_Mode = CAN_Mode_STM|CAN_Mode_LOM; @@ -171,37 +171,37 @@ static void bxcan_init(CAN_TypeDef *pcan, rt_uint32_t baud, rt_uint32_t mode) switch (bps) { - case LS1C_CAN1MBaud: + case LS1C_CAN1MBaud: CAN_InitStructure.CAN_Prescaler = 9; CAN_InitStructure.CAN_BS1 = CAN_BS1_4tq; CAN_InitStructure.CAN_BS2 = CAN_BS2_2tq; break; - case LS1C_CAN800kBaud: + case LS1C_CAN800kBaud: CAN_InitStructure.CAN_Prescaler = 8; CAN_InitStructure.CAN_BS1 = CAN_BS1_7tq; CAN_InitStructure.CAN_BS2 = CAN_BS2_2tq; break; - case LS1C_CAN500kBaud: + case LS1C_CAN500kBaud: CAN_InitStructure.CAN_Prescaler = 9; CAN_InitStructure.CAN_BS1 = CAN_BS1_11tq; CAN_InitStructure.CAN_BS2 = CAN_BS2_2tq; break; - case LS1C_CAN250kBaud: + case LS1C_CAN250kBaud: CAN_InitStructure.CAN_Prescaler = 36; CAN_InitStructure.CAN_BS1 = CAN_BS1_4tq; CAN_InitStructure.CAN_BS2 = CAN_BS2_2tq; break; - case LS1C_CAN125kBaud: + case LS1C_CAN125kBaud: CAN_InitStructure.CAN_Prescaler = 36; CAN_InitStructure.CAN_BS1 = CAN_BS1_11tq; CAN_InitStructure.CAN_BS2 = CAN_BS2_2tq; break; - case LS1C_CAN100kBaud: + case LS1C_CAN100kBaud: CAN_InitStructure.CAN_Prescaler = 63; CAN_InitStructure.CAN_BS1 = CAN_BS1_7tq; CAN_InitStructure.CAN_BS2 = CAN_BS2_2tq; break; - case LS1C_CAN50kBaud: + case LS1C_CAN50kBaud: CAN_InitStructure.CAN_Prescaler = 63; CAN_InitStructure.CAN_BS1 = CAN_BS1_16tq; CAN_InitStructure.CAN_BS2 = CAN_BS2_3tq; @@ -244,14 +244,14 @@ static rt_err_t configure(struct rt_can_device *can, struct can_configure *cfg) if (pbxcan == CAN0) { #ifdef USING_BXCAN0 - bxcan0_hw_init(); + bxcan0_hw_init(); bxcan_init(pbxcan, cfg->baud_rate, cfg->mode); #endif } else if (pbxcan == CAN1) { #ifdef USING_BXCAN1 - bxcan1_hw_init(); + bxcan1_hw_init(); bxcan_init(pbxcan, cfg->baud_rate, cfg->mode); #endif } @@ -328,7 +328,7 @@ static rt_err_t control(struct rt_can_device *can, int cmd, void *arg) } break; case RT_CAN_CMD_GET_STATUS: - { + { rt_uint32_t errtype; errtype = pbxcan->reg->RXERR; @@ -380,7 +380,7 @@ static int recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno) pbxcan = ((struct ls1c_bxcan *) can->parent.user_data)->reg; - pmsg->ide = (rt_uint32_t) RxMessage.IDE; + pmsg->ide = (rt_uint32_t) RxMessage.IDE; if(RxMessage.IDE == 1) pmsg->id = RxMessage.ExtId; else @@ -405,37 +405,37 @@ static const struct rt_can_ops canops = #ifdef USING_BXCAN0 struct rt_can_device bxcan0; -void ls1c_can0_irqhandler(int irq, void *param) -{ +void ls1c_can0_irqhandler(int irq, void *param) +{ CAN_TypeDef* CANx; unsigned char status; CANx = CAN0; /*读寄存器清除中断*/ status = CANx->IR; - + /*接收中断*/ - if (( status & CAN_IR_RI) == CAN_IR_RI) + if (( status & CAN_IR_RI) == CAN_IR_RI) { /*清除RI 中断*/ CAN_Receive(CANx, &RxMessage); - CANx->CMR |= CAN_CMR_RRB; - CANx->CMR |= CAN_CMR_CDO; + CANx->CMR |= CAN_CMR_RRB; + CANx->CMR |= CAN_CMR_CDO; rt_hw_can_isr(&bxcan0, RT_CAN_EVENT_RX_IND); rt_kprintf("\r\nCan0 int RX happened!\r\n"); } /*发送中断*/ - else if (( status & CAN_IR_TI) == CAN_IR_TI) + else if (( status & CAN_IR_TI) == CAN_IR_TI) { rt_hw_can_isr(&bxcan0, RT_CAN_EVENT_TX_DONE | 0 << 8); rt_kprintf("\r\nCan0 int TX happened!\r\n"); } /*数据溢出中断*/ - else if (( status & CAN_IR_DOI) == CAN_IR_DOI) + else if (( status & CAN_IR_DOI) == CAN_IR_DOI) { rt_hw_can_isr(&bxcan0, RT_CAN_EVENT_RXOF_IND); rt_kprintf("\r\nCan0 int RX OF happened!\r\n"); } -} +} static struct ls1c_bxcan bxcan0data = { .reg = CAN0, @@ -445,37 +445,37 @@ static struct ls1c_bxcan bxcan0data = #ifdef USING_BXCAN1 struct rt_can_device bxcan1; -void ls1c_can1_irqhandler(int irq, void *param) -{ +void ls1c_can1_irqhandler(int irq, void *param) +{ CAN_TypeDef* CANx; unsigned char status; CANx = CAN1; /*读寄存器清除中断*/ status = CANx->IR; - + /*接收中断*/ - if (( status & CAN_IR_RI) == CAN_IR_RI) + if (( status & CAN_IR_RI) == CAN_IR_RI) { /*清除RI 中断*/ CAN_Receive(CANx, &RxMessage); - CANx->CMR |= CAN_CMR_RRB; - CANx->CMR |= CAN_CMR_CDO; + CANx->CMR |= CAN_CMR_RRB; + CANx->CMR |= CAN_CMR_CDO; rt_hw_can_isr(&bxcan1, RT_CAN_EVENT_RX_IND); rt_kprintf("\r\nCan1 int RX happened!\r\n"); } /*发送中断*/ - else if (( status & CAN_IR_TI) == CAN_IR_TI) + else if (( status & CAN_IR_TI) == CAN_IR_TI) { rt_hw_can_isr(&bxcan1, RT_CAN_EVENT_TX_DONE | 0 << 8); rt_kprintf("\r\nCan1 int TX happened!\r\n"); } /*数据溢出中断*/ - else if (( status & CAN_IR_DOI) == CAN_IR_DOI) + else if (( status & CAN_IR_DOI) == CAN_IR_DOI) { rt_hw_can_isr(&bxcan1, RT_CAN_EVENT_RXOF_IND); rt_kprintf("\r\nCan1 int RX OF happened!\r\n"); } -} +} static struct ls1c_bxcan bxcan1data = { .reg = CAN1, @@ -499,9 +499,9 @@ int ls1c_bxcan_init(void) #endif rt_hw_can_register(&bxcan0, "bxcan0", &canops, &bxcan0data); rt_kprintf("\r\ncan0 register! \r\n"); - - rt_hw_interrupt_install(LS1C_CAN0_IRQ,( rt_isr_handler_t)bxcan0data.irq , RT_NULL, "can0"); - rt_hw_interrupt_umask(LS1C_CAN0_IRQ); + + rt_hw_interrupt_install(LS1C_CAN0_IRQ,( rt_isr_handler_t)bxcan0data.irq , RT_NULL, "can0"); + rt_hw_interrupt_umask(LS1C_CAN0_IRQ); #endif #ifdef USING_BXCAN1 bxcan1.config.baud_rate = CAN250kBaud; @@ -515,9 +515,9 @@ int ls1c_bxcan_init(void) #endif rt_hw_can_register(&bxcan1, "bxcan1", &canops, &bxcan1data); rt_kprintf("\r\ncan1 register! \r\n"); - - rt_hw_interrupt_install(LS1C_CAN1_IRQ,( rt_isr_handler_t)bxcan1data.irq , RT_NULL, "can1"); - rt_hw_interrupt_umask(LS1C_CAN1_IRQ); + + rt_hw_interrupt_install(LS1C_CAN1_IRQ,( rt_isr_handler_t)bxcan1data.irq , RT_NULL, "can1"); + rt_hw_interrupt_umask(LS1C_CAN1_IRQ); #endif return RT_EOK; } diff --git a/bsp/ls1cdev/drivers/drv_can.h b/bsp/ls1cdev/drivers/drv_can.h index 7d5d1604d4..2d63b9a4f3 100644 --- a/bsp/ls1cdev/drivers/drv_can.h +++ b/bsp/ls1cdev/drivers/drv_can.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/ls1cdev/drivers/drv_gpio.c b/bsp/ls1cdev/drivers/drv_gpio.c index 2203db7775..8517740878 100644 --- a/bsp/ls1cdev/drivers/drv_gpio.c +++ b/bsp/ls1cdev/drivers/drv_gpio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -90,7 +90,7 @@ rt_err_t ls1c_pin_attach_irq(struct rt_device *device, rt_int32_t pin, break; } gpio_set_irq_type(gpio, type); - + rt_sprintf(irq_name, "PIN_%d", gpio); rt_hw_interrupt_install(LS1C_GPIO_TO_IRQ(gpio), (rt_isr_handler_t)hdr, args, irq_name); diff --git a/bsp/ls1cdev/drivers/drv_gpio.h b/bsp/ls1cdev/drivers/drv_gpio.h index 33fc0f18ed..0f4a640fea 100644 --- a/bsp/ls1cdev/drivers/drv_gpio.h +++ b/bsp/ls1cdev/drivers/drv_gpio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/ls1cdev/drivers/drv_i2c.c b/bsp/ls1cdev/drivers/drv_i2c.c index 374b625c70..66fad68638 100644 --- a/bsp/ls1cdev/drivers/drv_i2c.c +++ b/bsp/ls1cdev/drivers/drv_i2c.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/ls1cdev/drivers/drv_i2c.h b/bsp/ls1cdev/drivers/drv_i2c.h index cbacdbb0f5..5f9a8dd412 100644 --- a/bsp/ls1cdev/drivers/drv_i2c.h +++ b/bsp/ls1cdev/drivers/drv_i2c.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/ls1cdev/drivers/drv_pwm.c b/bsp/ls1cdev/drivers/drv_pwm.c index 779a7e52b9..c097ff362c 100644 --- a/bsp/ls1cdev/drivers/drv_pwm.c +++ b/bsp/ls1cdev/drivers/drv_pwm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -59,17 +59,17 @@ static rt_err_t get(struct rt_device_pwm *device, struct rt_pwm_configuration *c { rt_err_t result = RT_EOK; struct rt_ls1c_pwm *ls1c_pwm_device = (struct rt_ls1c_pwm *)device; - + if (configuration->channel > (PWM_CHANNEL_MAX - 1)) { result = -RT_EIO; goto _exit; } - + configuration->period = ls1c_pwm_device->period[configuration->channel]; configuration->pulse = ls1c_pwm_device->pulse[configuration->channel]; rt_kprintf("drv_pwm.c get channel %d: period: %d, pulse: %d\n", configuration->channel, configuration->period, configuration->pulse); - + _exit: return result; } @@ -84,7 +84,7 @@ static rt_err_t control(struct rt_device_pwm *device, int cmd, void *arg) if (cmd == PWM_CMD_ENABLE) { rt_kprintf("PWM_CMD_ENABLE\n"); - + pwm_info_t pwm_info; switch ( configuration->channel) { @@ -107,9 +107,9 @@ static rt_err_t control(struct rt_device_pwm *device, int cmd, void *arg) default: break; } - pwm_info.mode = PWM_MODE_NORMAL; - pwm_info.duty = ( (float)configuration->pulse ) / ((float)configuration->period ); - pwm_info.period_ns = configuration->period; + pwm_info.mode = PWM_MODE_NORMAL; + pwm_info.duty = ( (float)configuration->pulse ) / ((float)configuration->period ); + pwm_info.period_ns = configuration->period; pwm_init(&pwm_info); pwm_enable(&pwm_info); } @@ -138,9 +138,9 @@ static rt_err_t control(struct rt_device_pwm *device, int cmd, void *arg) default: break; } - pwm_info.mode = PWM_MODE_NORMAL; - pwm_info.duty = ( (float)configuration->pulse ) / ((float)configuration->period ); - pwm_info.period_ns = configuration->period; + pwm_info.mode = PWM_MODE_NORMAL; + pwm_info.duty = ( (float)configuration->pulse ) / ((float)configuration->period ); + pwm_info.period_ns = configuration->period; pwm_init(&pwm_info); pwm_disable(&pwm_info); } diff --git a/bsp/ls1cdev/drivers/drv_pwm.h b/bsp/ls1cdev/drivers/drv_pwm.h index 427ba0c619..b367a55c49 100644 --- a/bsp/ls1cdev/drivers/drv_pwm.h +++ b/bsp/ls1cdev/drivers/drv_pwm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/ls1cdev/drivers/drv_rtc.c b/bsp/ls1cdev/drivers/drv_rtc.c index 0569992c61..ca26b97e8b 100644 --- a/bsp/ls1cdev/drivers/drv_rtc.c +++ b/bsp/ls1cdev/drivers/drv_rtc.c @@ -1,10 +1,10 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes + * Date Author Notes * 2018-05-05 sundm75 first version */ @@ -20,29 +20,29 @@ #if defined(RT_USING_RTC) #ifdef RT_RTC_DEBUG -#define rtc_debug(format,args...) rt_kprintf(format, ##args) +#define rtc_debug(format,args...) rt_kprintf(format, ##args) #else #define rtc_debug(format,args...) #endif static struct rt_device rtc; -RTC_TypeDef * RTC_Handler; +RTC_TypeDef * RTC_Handler; -static time_t get_timestamp(void) +static time_t get_timestamp(void) { - struct tm tm_new = {0}; - RTC_TimeTypeDef rtcDate; - - RTC_GetTime(RTC_Handler, &rtcDate); - - tm_new.tm_sec = rtcDate.Seconds; - tm_new.tm_min = rtcDate.Minutes; + struct tm tm_new = {0}; + RTC_TimeTypeDef rtcDate; + + RTC_GetTime(RTC_Handler, &rtcDate); + + tm_new.tm_sec = rtcDate.Seconds; + tm_new.tm_min = rtcDate.Minutes; tm_new.tm_hour = rtcDate.Hours; - - tm_new.tm_mday = rtcDate.Date; - tm_new.tm_mon = rtcDate.Month- 1; - tm_new.tm_year = rtcDate.Year + 2000 - 1900; + + tm_new.tm_mday = rtcDate.Date; + tm_new.tm_mon = rtcDate.Month- 1; + tm_new.tm_year = rtcDate.Year + 2000 - 1900; return mktime(&tm_new); } @@ -50,26 +50,26 @@ static time_t get_timestamp(void) static int set_timestamp(time_t timestamp) { struct tm *p_tm; - RTC_TimeTypeDef rtcDate; - + RTC_TimeTypeDef rtcDate; + p_tm = localtime(×tamp); - - rtcDate.Seconds= p_tm->tm_sec ; - rtcDate.Minutes= p_tm->tm_min ; - rtcDate.Hours= p_tm->tm_hour; - - rtcDate.Date= p_tm->tm_mday; - rtcDate.Month= p_tm->tm_mon + 1; - rtcDate.Year= p_tm->tm_year + 1900 - 2000; - - RTC_SetTime(RTC_Handler, &rtcDate); + + rtcDate.Seconds= p_tm->tm_sec ; + rtcDate.Minutes= p_tm->tm_min ; + rtcDate.Hours= p_tm->tm_hour; + + rtcDate.Date= p_tm->tm_mday; + rtcDate.Month= p_tm->tm_mon + 1; + rtcDate.Year= p_tm->tm_year + 1900 - 2000; + + RTC_SetTime(RTC_Handler, &rtcDate); rt_kprintf("\r\nrtcDate is %d.%d.%d - %d:%d:%d",rtcDate.Year, rtcDate.Month, rtcDate.Date, rtcDate.Hours, rtcDate.Minutes, rtcDate.Seconds); return RT_EOK; } rt_uint8_t RTC_Init(void) -{ - RTC_Handler = RTC; +{ + RTC_Handler = RTC; return 0; } @@ -89,7 +89,7 @@ static rt_size_t rt_rtc_read( void* buffer, rt_size_t size) { - + return 0; } @@ -108,7 +108,7 @@ static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args) switch (cmd) { case RT_DEVICE_CTRL_RTC_GET_TIME: - + *(rt_uint32_t *)args = get_timestamp(); rtc_debug("RTC: get rtc_time %x\n", *(rt_uint32_t *)args); break; diff --git a/bsp/ls1cdev/drivers/drv_rtc.h b/bsp/ls1cdev/drivers/drv_rtc.h index cea8ebe633..c742a9d68a 100644 --- a/bsp/ls1cdev/drivers/drv_rtc.h +++ b/bsp/ls1cdev/drivers/drv_rtc.h @@ -1,18 +1,18 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes + * Date Author Notes * 2018-05-05 sundm75 first version */ - + #ifndef __DRV_RTC_H__ #define __DRV_RTC_H__ -#include -#include +#include +#include int rt_hw_rtc_init(void); diff --git a/bsp/ls1cdev/drivers/drv_spi.h b/bsp/ls1cdev/drivers/drv_spi.h index 8b1aa315be..91e5be69df 100644 --- a/bsp/ls1cdev/drivers/drv_spi.h +++ b/bsp/ls1cdev/drivers/drv_spi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -32,7 +32,7 @@ struct ls1c_spi_cs * 初始化并注册龙芯1c的spi总线 * @SPI SPI总线，比如LS1C_SPI_0， LS1C_SPI_1 * @spi_bus_name 总线名字 - * @ret + * @ret */ rt_err_t ls1c_spi_bus_register(rt_uint8_t SPI, const char *spi_bus_name); diff --git a/bsp/ls1cdev/drivers/drv_touch.c b/bsp/ls1cdev/drivers/drv_touch.c index 092260aaed..1f7b3f060d 100644 --- a/bsp/ls1cdev/drivers/drv_touch.c +++ b/bsp/ls1cdev/drivers/drv_touch.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -9,7 +9,7 @@ * 2018-10-29 XY * 2019-04-11 sundm75 modify for ls1c300 & RTGUI */ - + #include "drv_touch.h" #define TOUCH_I2C_NAME "i2c1" diff --git a/bsp/ls1cdev/drivers/drv_touch.h b/bsp/ls1cdev/drivers/drv_touch.h index 1ae4c71549..f930faf49a 100644 --- a/bsp/ls1cdev/drivers/drv_touch.h +++ b/bsp/ls1cdev/drivers/drv_touch.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -8,7 +8,7 @@ * 2018-02-08 Zhangyihong the first version * 2018-10-29 XY */ - + #ifndef __DRV_TOUCH_H__ #define __DRV_TOUCH_H__ diff --git a/bsp/ls1cdev/drivers/drv_touch_gt9xx.c b/bsp/ls1cdev/drivers/drv_touch_gt9xx.c index 801ec762cb..90389e3696 100644 --- a/bsp/ls1cdev/drivers/drv_touch_gt9xx.c +++ b/bsp/ls1cdev/drivers/drv_touch_gt9xx.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/ls1cdev/drivers/drv_uart.c b/bsp/ls1cdev/drivers/drv_uart.c index 0578eea4fc..7ac3ddba01 100644 --- a/bsp/ls1cdev/drivers/drv_uart.c +++ b/bsp/ls1cdev/drivers/drv_uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/ls1cdev/drivers/drv_uart.h b/bsp/ls1cdev/drivers/drv_uart.h index 4e3fb63194..bebba0d82d 100644 --- a/bsp/ls1cdev/drivers/drv_uart.h +++ b/bsp/ls1cdev/drivers/drv_uart.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/ls1cdev/drivers/drv_wdt.c b/bsp/ls1cdev/drivers/drv_wdt.c index 4a42220000..d40bef33bb 100644 --- a/bsp/ls1cdev/drivers/drv_wdt.c +++ b/bsp/ls1cdev/drivers/drv_wdt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -161,15 +161,15 @@ static rt_err_t watchdog_ctrl(rt_watchdog_t *wdt, int cmd, void *arg) return RT_EOK; } -struct rt_watchdog_ops watchdog_ops = +struct rt_watchdog_ops watchdog_ops = { - .init = &watchdog_init, + .init = &watchdog_init, .control = &watchdog_ctrl, }; -int wdt_exit(void *priv_data) -{ - return 0; +int wdt_exit(void *priv_data) +{ + return 0; } int rt_hw_wdt_init(void) diff --git a/bsp/ls1cdev/drivers/drv_wdt.h b/bsp/ls1cdev/drivers/drv_wdt.h index a017edb19a..18ca69d506 100644 --- a/bsp/ls1cdev/drivers/drv_wdt.h +++ b/bsp/ls1cdev/drivers/drv_wdt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/ls1cdev/drivers/hw_i2c.c b/bsp/ls1cdev/drivers/hw_i2c.c index 1f63df1ab9..a64b42b5e1 100644 --- a/bsp/ls1cdev/drivers/hw_i2c.c +++ b/bsp/ls1cdev/drivers/hw_i2c.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -10,7 +10,7 @@ #include #include -#include "ls1c_i2c.h" +#include "ls1c_i2c.h" #include "../libraries/ls1c_pin.h" #ifdef RT_USING_I2C @@ -26,30 +26,30 @@ rt_size_t rt_i2c_master_xfer(struct rt_i2c_bus_device *bus, rt_uint32_t num) { struct ls1c_i2c_bus * i2c_bus = (struct ls1c_i2c_bus *)bus; - ls1c_i2c_info_t i2c_info; + ls1c_i2c_info_t i2c_info; struct rt_i2c_msg *msg; int i; rt_int32_t ret = RT_EOK; - i2c_info.clock = 50000; // 50kb/s + i2c_info.clock = 50000; // 50kb/s i2c_info.I2Cx = i2c_bus->u32Module; i2c_init(&i2c_info); - + for (i = 0; i < num; i++) { msg = &msgs[i]; if (msg->flags == RT_I2C_RD) { - i2c_send_start_and_addr(&i2c_info, msg->addr, LS1C_I2C_DIRECTION_READ); - i2c_receive_ack(&i2c_info); - i2c_receive_data(&i2c_info, (rt_uint8_t *)msg->buf, msg->len); - i2c_send_stop(&i2c_info); + i2c_send_start_and_addr(&i2c_info, msg->addr, LS1C_I2C_DIRECTION_READ); + i2c_receive_ack(&i2c_info); + i2c_receive_data(&i2c_info, (rt_uint8_t *)msg->buf, msg->len); + i2c_send_stop(&i2c_info); } else if(msg->flags == RT_I2C_WR) { - i2c_send_start_and_addr(&i2c_info, msg->addr, LS1C_I2C_DIRECTION_WRITE); - i2c_receive_ack(&i2c_info); - i2c_send_data(&i2c_info, (rt_uint8_t *)msg->buf, msg->len); - i2c_send_stop(&i2c_info); + i2c_send_start_and_addr(&i2c_info, msg->addr, LS1C_I2C_DIRECTION_WRITE); + i2c_receive_ack(&i2c_info); + i2c_send_data(&i2c_info, (rt_uint8_t *)msg->buf, msg->len); + i2c_send_stop(&i2c_info); } ret++; } @@ -85,7 +85,7 @@ static const struct rt_i2c_bus_device_ops ls1c_i2c_ops = #ifdef RT_USING_I2C0 -static struct ls1c_i2c_bus ls1c_i2c_bus_0 = +static struct ls1c_i2c_bus ls1c_i2c_bus_0 = { {1}, LS1C_I2C_0, @@ -93,7 +93,7 @@ static struct ls1c_i2c_bus ls1c_i2c_bus_0 = #endif #ifdef RT_USING_I2C1 -static struct ls1c_i2c_bus ls1c_i2c_bus_1 = +static struct ls1c_i2c_bus ls1c_i2c_bus_1 = { {1}, LS1C_I2C_1, @@ -101,7 +101,7 @@ static struct ls1c_i2c_bus ls1c_i2c_bus_1 = #endif #ifdef RT_USING_I2C2 -static struct ls1c_i2c_bus ls1c_i2c_bus_2 = +static struct ls1c_i2c_bus ls1c_i2c_bus_2 = { {1}, LS1C_I2C_2, diff --git a/bsp/ls1cdev/drivers/hw_i2c.h b/bsp/ls1cdev/drivers/hw_i2c.h index cc3e25506f..f4926f8e23 100644 --- a/bsp/ls1cdev/drivers/hw_i2c.h +++ b/bsp/ls1cdev/drivers/hw_i2c.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,4 +15,4 @@ int rt_i2c_init(void); -#endif +#endif diff --git a/bsp/ls1cdev/drivers/net/mii.c b/bsp/ls1cdev/drivers/net/mii.c index 43ade097cf..0e92f091d6 100644 --- a/bsp/ls1cdev/drivers/net/mii.c +++ b/bsp/ls1cdev/drivers/net/mii.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,123 +14,123 @@ static inline unsigned int mii_nway_result (unsigned int negotiated) { - unsigned int ret; - - if (negotiated & LPA_100FULL) - ret = LPA_100FULL; - else if (negotiated & LPA_100BASE4) - ret = LPA_100BASE4; - else if (negotiated & LPA_100HALF) - ret = LPA_100HALF; - else if (negotiated & LPA_10FULL) - ret = LPA_10FULL; - else - ret = LPA_10HALF; - - return ret; + unsigned int ret; + + if (negotiated & LPA_100FULL) + ret = LPA_100FULL; + else if (negotiated & LPA_100BASE4) + ret = LPA_100BASE4; + else if (negotiated & LPA_100HALF) + ret = LPA_100HALF; + else if (negotiated & LPA_10FULL) + ret = LPA_10FULL; + else + ret = LPA_10HALF; + + return ret; } static int mii_check_gmii_support(struct mii_if_info *mii) { - int reg; + int reg; - reg = mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR); - if (reg & BMSR_ESTATEN) { - reg = mii->mdio_read(mii->dev, mii->phy_id, MII_ESTATUS); - if (reg & (ESTATUS_1000_TFULL | ESTATUS_1000_THALF)) - return 1; - } + reg = mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR); + if (reg & BMSR_ESTATEN) { + reg = mii->mdio_read(mii->dev, mii->phy_id, MII_ESTATUS); + if (reg & (ESTATUS_1000_TFULL | ESTATUS_1000_THALF)) + return 1; + } - return 0; + return 0; } static int mii_ethtool_gset(struct mii_if_info *mii, struct ethtool_cmd *ecmd) { - struct synopGMACNetworkAdapter * dev = mii->dev; - u32 advert, bmcr, lpa, nego; - u32 advert2 = 0, bmcr2 = 0, lpa2 = 0; - - ecmd->supported = - (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | - SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | - SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII); - if (mii->supports_gmii) - ecmd->supported |= SUPPORTED_1000baseT_Half | - SUPPORTED_1000baseT_Full; - - /* only supports twisted-pair */ - ecmd->port = PORT_MII; - - /* only supports internal transceiver */ - ecmd->transceiver = XCVR_INTERNAL; - - /* this isn't fully supported at higher layers */ - ecmd->phy_address = mii->phy_id; - - ecmd->advertising = ADVERTISED_TP | ADVERTISED_MII; - advert = mii->mdio_read(dev, mii->phy_id, MII_ADVERTISE); - if (mii->supports_gmii) - advert2 = mii->mdio_read(dev, mii->phy_id, MII_CTRL1000); - - if (advert & ADVERTISE_10HALF) - ecmd->advertising |= ADVERTISED_10baseT_Half; - if (advert & ADVERTISE_10FULL) - ecmd->advertising |= ADVERTISED_10baseT_Full; - if (advert & ADVERTISE_100HALF) - ecmd->advertising |= ADVERTISED_100baseT_Half; - if (advert & ADVERTISE_100FULL) - ecmd->advertising |= ADVERTISED_100baseT_Full; - if (advert2 & ADVERTISE_1000HALF) - ecmd->advertising |= ADVERTISED_1000baseT_Half; - if (advert2 & ADVERTISE_1000FULL) - ecmd->advertising |= ADVERTISED_1000baseT_Full; - - bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR); - lpa = mii->mdio_read(dev, mii->phy_id, MII_LPA); - if (mii->supports_gmii) { - bmcr2 = mii->mdio_read(dev, mii->phy_id, MII_CTRL1000); - lpa2 = mii->mdio_read(dev, mii->phy_id, MII_STAT1000); - } - if (bmcr & BMCR_ANENABLE) { - ecmd->advertising |= ADVERTISED_Autoneg; - ecmd->autoneg = AUTONEG_ENABLE; - - nego = mii_nway_result(advert & lpa); - if ((bmcr2 & (ADVERTISE_1000HALF | ADVERTISE_1000FULL)) & - (lpa2 >> 2)) - ecmd->speed = SPEED_1000; - else if (nego == LPA_100FULL || nego == LPA_100HALF) - ecmd->speed = SPEED_100; - else - ecmd->speed = SPEED_10; - if ((lpa2 & LPA_1000FULL) || nego == LPA_100FULL || - nego == LPA_10FULL) { - ecmd->duplex = DUPLEX_FULL; - mii->full_duplex = 1; - } else { - ecmd->duplex = DUPLEX_HALF; - mii->full_duplex = 0; - } - } else { - ecmd->autoneg = AUTONEG_DISABLE; - - ecmd->speed = ((bmcr & BMCR_SPEED1000 && - (bmcr & BMCR_SPEED100) == 0) ? SPEED_1000 : - (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10); - ecmd->duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF; - } - - /* ignore maxtxpkt, maxrxpkt for now */ - - return 0; + struct synopGMACNetworkAdapter * dev = mii->dev; + u32 advert, bmcr, lpa, nego; + u32 advert2 = 0, bmcr2 = 0, lpa2 = 0; + + ecmd->supported = + (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | + SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | + SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII); + if (mii->supports_gmii) + ecmd->supported |= SUPPORTED_1000baseT_Half | + SUPPORTED_1000baseT_Full; + + /* only supports twisted-pair */ + ecmd->port = PORT_MII; + + /* only supports internal transceiver */ + ecmd->transceiver = XCVR_INTERNAL; + + /* this isn't fully supported at higher layers */ + ecmd->phy_address = mii->phy_id; + + ecmd->advertising = ADVERTISED_TP | ADVERTISED_MII; + advert = mii->mdio_read(dev, mii->phy_id, MII_ADVERTISE); + if (mii->supports_gmii) + advert2 = mii->mdio_read(dev, mii->phy_id, MII_CTRL1000); + + if (advert & ADVERTISE_10HALF) + ecmd->advertising |= ADVERTISED_10baseT_Half; + if (advert & ADVERTISE_10FULL) + ecmd->advertising |= ADVERTISED_10baseT_Full; + if (advert & ADVERTISE_100HALF) + ecmd->advertising |= ADVERTISED_100baseT_Half; + if (advert & ADVERTISE_100FULL) + ecmd->advertising |= ADVERTISED_100baseT_Full; + if (advert2 & ADVERTISE_1000HALF) + ecmd->advertising |= ADVERTISED_1000baseT_Half; + if (advert2 & ADVERTISE_1000FULL) + ecmd->advertising |= ADVERTISED_1000baseT_Full; + + bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR); + lpa = mii->mdio_read(dev, mii->phy_id, MII_LPA); + if (mii->supports_gmii) { + bmcr2 = mii->mdio_read(dev, mii->phy_id, MII_CTRL1000); + lpa2 = mii->mdio_read(dev, mii->phy_id, MII_STAT1000); + } + if (bmcr & BMCR_ANENABLE) { + ecmd->advertising |= ADVERTISED_Autoneg; + ecmd->autoneg = AUTONEG_ENABLE; + + nego = mii_nway_result(advert & lpa); + if ((bmcr2 & (ADVERTISE_1000HALF | ADVERTISE_1000FULL)) & + (lpa2 >> 2)) + ecmd->speed = SPEED_1000; + else if (nego == LPA_100FULL || nego == LPA_100HALF) + ecmd->speed = SPEED_100; + else + ecmd->speed = SPEED_10; + if ((lpa2 & LPA_1000FULL) || nego == LPA_100FULL || + nego == LPA_10FULL) { + ecmd->duplex = DUPLEX_FULL; + mii->full_duplex = 1; + } else { + ecmd->duplex = DUPLEX_HALF; + mii->full_duplex = 0; + } + } else { + ecmd->autoneg = AUTONEG_DISABLE; + + ecmd->speed = ((bmcr & BMCR_SPEED1000 && + (bmcr & BMCR_SPEED100) == 0) ? SPEED_1000 : + (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10); + ecmd->duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF; + } + + /* ignore maxtxpkt, maxrxpkt for now */ + + return 0; } static int mii_link_ok (struct mii_if_info *mii) { - /* first, a dummy read, needed to latch some MII phys */ - mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR); - if (mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR) & BMSR_LSTATUS) - return 1; - return 0; + /* first, a dummy read, needed to latch some MII phys */ + mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR); + if (mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR) & BMSR_LSTATUS) + return 1; + return 0; } diff --git a/bsp/ls1cdev/drivers/net/mii.h b/bsp/ls1cdev/drivers/net/mii.h index 24563834ec..f96c8ff816 100644 --- a/bsp/ls1cdev/drivers/net/mii.h +++ b/bsp/ls1cdev/drivers/net/mii.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -24,7 +24,7 @@ #define MII_EXPANSION 0x06 /* Expansion register */ #define MII_CTRL1000 0x09 /* 1000BASE-T control */ #define MII_STAT1000 0x0a /* 1000BASE-T status */ -#define MII_ESTATUS 0x0f /* Extended Status */ +#define MII_ESTATUS 0x0f /* Extended Status */ #define MII_DCOUNTER 0x12 /* Disconnect counter */ #define MII_FCSCOUNTER 0x13 /* False carrier counter */ #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ @@ -39,7 +39,7 @@ /* Basic mode control register. */ #define BMCR_RESV 0x003f /* Unused... */ -#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ +#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ #define BMCR_CTST 0x0080 /* Collision test */ #define BMCR_FULLDPLX 0x0100 /* Full duplex */ #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ @@ -58,9 +58,9 @@ #define BMSR_RFAULT 0x0010 /* Remote fault detected */ #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ #define BMSR_RESV 0x00c0 /* Unused... */ -#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ -#define BMSR_100FULL2 0x0200 /* Can do 100BASE-T2 HDX */ -#define BMSR_100HALF2 0x0400 /* Can do 100BASE-T2 FDX */ +#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ +#define BMSR_100FULL2 0x0200 /* Can do 100BASE-T2 HDX */ +#define BMSR_100HALF2 0x0400 /* Can do 100BASE-T2 FDX */ #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ #define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ @@ -87,26 +87,26 @@ #define ADVERTISE_NPAGE 0x8000 /* Next page bit */ #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ - ADVERTISE_CSMA) + ADVERTISE_CSMA) #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ ADVERTISE_100HALF | ADVERTISE_100FULL) /* Indicates what features are advertised by the interface. */ -#define ADVERTISED_10baseT_Half (1 << 0) -#define ADVERTISED_10baseT_Full (1 << 1) -#define ADVERTISED_100baseT_Half (1 << 2) -#define ADVERTISED_100baseT_Full (1 << 3) -#define ADVERTISED_1000baseT_Half (1 << 4) -#define ADVERTISED_1000baseT_Full (1 << 5) -#define ADVERTISED_Autoneg (1 << 6) -#define ADVERTISED_TP (1 << 7) -#define ADVERTISED_AUI (1 << 8) -#define ADVERTISED_MII (1 << 9) -#define ADVERTISED_FIBRE (1 << 10) -#define ADVERTISED_BNC (1 << 11) -#define ADVERTISED_10000baseT_Full (1 << 12) -#define ADVERTISED_Pause (1 << 13) -#define ADVERTISED_Asym_Pause (1 << 14) +#define ADVERTISED_10baseT_Half (1 << 0) +#define ADVERTISED_10baseT_Full (1 << 1) +#define ADVERTISED_100baseT_Half (1 << 2) +#define ADVERTISED_100baseT_Full (1 << 3) +#define ADVERTISED_1000baseT_Half (1 << 4) +#define ADVERTISED_1000baseT_Full (1 << 5) +#define ADVERTISED_Autoneg (1 << 6) +#define ADVERTISED_TP (1 << 7) +#define ADVERTISED_AUI (1 << 8) +#define ADVERTISED_MII (1 << 9) +#define ADVERTISED_FIBRE (1 << 10) +#define ADVERTISED_BNC (1 << 11) +#define ADVERTISED_10000baseT_Full (1 << 12) +#define ADVERTISED_Pause (1 << 13) +#define ADVERTISED_Asym_Pause (1 << 14) /* Link partner ability register. */ #define LPA_SLCT 0x001f /* Same as advertise selector */ @@ -126,8 +126,8 @@ #define LPA_LPACK 0x4000 /* Link partner acked us */ #define LPA_NPAGE 0x8000 /* Next page bit */ -#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) -#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) +#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) +#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) /* Expansion register for auto-negotiation. */ #define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */ @@ -137,8 +137,8 @@ #define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ #define EXPANSION_RESV 0xffe0 /* Unused... */ -#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ -#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ +#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ +#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ /* N-way test register. */ #define NWAYTEST_RESV1 0x00ff /* Unused... */ @@ -154,78 +154,78 @@ #define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */ #define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */ -#define SUPPORTED_10baseT_Half (1 << 0) -#define SUPPORTED_10baseT_Full (1 << 1) -#define SUPPORTED_100baseT_Half (1 << 2) -#define SUPPORTED_100baseT_Full (1 << 3) -#define SUPPORTED_1000baseT_Half (1 << 4) -#define SUPPORTED_1000baseT_Full (1 << 5) -#define SUPPORTED_Autoneg (1 << 6) -#define SUPPORTED_TP (1 << 7) -#define SUPPORTED_AUI (1 << 8) -#define SUPPORTED_MII (1 << 9) -#define SUPPORTED_FIBRE (1 << 10) -#define SUPPORTED_BNC (1 << 11) -#define SUPPORTED_10000baseT_Full (1 << 12) -#define SUPPORTED_Pause (1 << 13) -#define SUPPORTED_Asym_Pause (1 << 14) +#define SUPPORTED_10baseT_Half (1 << 0) +#define SUPPORTED_10baseT_Full (1 << 1) +#define SUPPORTED_100baseT_Half (1 << 2) +#define SUPPORTED_100baseT_Full (1 << 3) +#define SUPPORTED_1000baseT_Half (1 << 4) +#define SUPPORTED_1000baseT_Full (1 << 5) +#define SUPPORTED_Autoneg (1 << 6) +#define SUPPORTED_TP (1 << 7) +#define SUPPORTED_AUI (1 << 8) +#define SUPPORTED_MII (1 << 9) +#define SUPPORTED_FIBRE (1 << 10) +#define SUPPORTED_BNC (1 << 11) +#define SUPPORTED_10000baseT_Full (1 << 12) +#define SUPPORTED_Pause (1 << 13) +#define SUPPORTED_Asym_Pause (1 << 14) /* Which connector port. */ #define PORT_TP 0x00 #define PORT_AUI 0x01 -#define PORT_MII 0x02 +#define PORT_MII 0x02 #define PORT_FIBRE 0x03 #define PORT_BNC 0x04 /* Which transceiver to use. */ #define XCVR_INTERNAL 0x00 #define XCVR_EXTERNAL 0x01 -#define XCVR_DUMMY1 0x02 -#define XCVR_DUMMY2 0x03 +#define XCVR_DUMMY1 0x02 +#define XCVR_DUMMY2 0x03 #define XCVR_DUMMY3 0x04 -#define AUTONEG_DISABLE 0x00 -#define AUTONEG_ENABLE 0x01 +#define AUTONEG_DISABLE 0x00 +#define AUTONEG_ENABLE 0x01 -#define SPEED_10 10 -#define SPEED_100 100 -#define SPEED_1000 1000 -#define SPEED_2500 2500 -#define SPEED_10000 10000 +#define SPEED_10 10 +#define SPEED_100 100 +#define SPEED_1000 1000 +#define SPEED_2500 2500 +#define SPEED_10000 10000 -#define DUPLEX_HALF 0x00 -#define DUPLEX_FULL 0x01 +#define DUPLEX_HALF 0x00 +#define DUPLEX_FULL 0x01 struct ethtool_cmd { - u32 cmd; - u32 supported; /* Features this interface supports */ - u32 advertising; /* Features this interface advertises */ - u16 speed; /* The forced speed, 10Mb, 100Mb, gigabit */ - u8 duplex; /* Duplex, half or full */ - u8 port; /* Which connector port */ - u8 phy_address; - u8 transceiver; /* Which transceiver to use */ - u8 autoneg; /* Enable or disable autonegotiation */ - u32 maxtxpkt; /* Tx pkts before generating tx int */ - u32 maxrxpkt; /* Rx pkts before generating rx int */ - u32 reserved[4]; + u32 cmd; + u32 supported; /* Features this interface supports */ + u32 advertising; /* Features this interface advertises */ + u16 speed; /* The forced speed, 10Mb, 100Mb, gigabit */ + u8 duplex; /* Duplex, half or full */ + u8 port; /* Which connector port */ + u8 phy_address; + u8 transceiver; /* Which transceiver to use */ + u8 autoneg; /* Enable or disable autonegotiation */ + u32 maxtxpkt; /* Tx pkts before generating tx int */ + u32 maxrxpkt; /* Rx pkts before generating rx int */ + u32 reserved[4]; }; struct mii_if_info { - int phy_id; - int advertising; - int phy_id_mask; - int reg_num_mask; - - unsigned int full_duplex : 1; /* is full duplex? */ - unsigned int force_media : 1; /* is autoneg. disabled? */ - unsigned int supports_gmii : 1; /* are GMII registers supported? */ - - struct synopGMACNetworkAdapter *dev; - int (*mdio_read) (struct synopGMACNetworkAdapter *dev, int phy_id, int location); - void (*mdio_write) (struct synopGMACNetworkAdapter *dev, int phy_id, int location, int val); + int phy_id; + int advertising; + int phy_id_mask; + int reg_num_mask; + + unsigned int full_duplex : 1; /* is full duplex? */ + unsigned int force_media : 1; /* is autoneg. disabled? */ + unsigned int supports_gmii : 1; /* are GMII registers supported? */ + + struct synopGMACNetworkAdapter *dev; + int (*mdio_read) (struct synopGMACNetworkAdapter *dev, int phy_id, int location); + void (*mdio_write) (struct synopGMACNetworkAdapter *dev, int phy_id, int location, int val); }; #endif diff --git a/bsp/ls1cdev/drivers/net/synopGMAC.c b/bsp/ls1cdev/drivers/net/synopGMAC.c index da8c3c89fb..c73176e018 100644 --- a/bsp/ls1cdev/drivers/net/synopGMAC.c +++ b/bsp/ls1cdev/drivers/net/synopGMAC.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -579,7 +579,7 @@ struct pbuf *rt_eth_rx(rt_device_t device) if (synopGMAC_is_rx_desc_valid(status) || SYNOP_PHY_LOOPBACK) { dma_addr1 = plat_dma_map_single(gmacdev, (void *)data1, RX_BUF_SIZE); - len = synopGMAC_get_rx_desc_frame_length(status)-4; //Not interested in Ethernet CRC bytes + len = synopGMAC_get_rx_desc_frame_length(status)-4; //Not interested in Ethernet CRC bytes pbuf = pbuf_alloc(PBUF_LINK, len, PBUF_RAM); if (pbuf == 0) rt_kprintf("===error in pbuf_alloc\n"); rt_memcpy(pbuf->payload, (char *)data1, len); diff --git a/bsp/ls1cdev/drivers/net/synopGMAC.h b/bsp/ls1cdev/drivers/net/synopGMAC.h index e244c14892..574e16d7dc 100644 --- a/bsp/ls1cdev/drivers/net/synopGMAC.h +++ b/bsp/ls1cdev/drivers/net/synopGMAC.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,4 +20,4 @@ int rt_hw_eth_init(void); -#endif /*__SYNOPGMAC__H*/ +#endif /*__SYNOPGMAC__H*/ diff --git a/bsp/ls1cdev/drivers/net/synopGMAC_Dev.c b/bsp/ls1cdev/drivers/net/synopGMAC_Dev.c index a41038f35c..3a31c9af70 100644 --- a/bsp/ls1cdev/drivers/net/synopGMAC_Dev.c +++ b/bsp/ls1cdev/drivers/net/synopGMAC_Dev.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,13 +7,13 @@ * Date Author Notes * 2017-08-24 chinesebear first version */ - + #include "synopGMAC_Dev.h" #include #include -#define UNUSED 1 +#define UNUSED 1 /** * Function to set the MDC clock for mdio transactiona @@ -24,12 +24,12 @@ */ s32 synopGMAC_set_mdc_clk_div(synopGMACdevice *gmacdev,u32 clk_div_val) { - u32 orig_data; - orig_data = synopGMACReadReg(gmacdev->MacBase,GmacGmiiAddr); //set the mdc clock to the user defined value - orig_data &= (~ GmiiCsrClkMask); - orig_data |= clk_div_val; - synopGMACWriteReg(gmacdev->MacBase, GmacGmiiAddr ,orig_data); - return 0; + u32 orig_data; + orig_data = synopGMACReadReg(gmacdev->MacBase,GmacGmiiAddr); //set the mdc clock to the user defined value + orig_data &= (~ GmiiCsrClkMask); + orig_data |= clk_div_val; + synopGMACWriteReg(gmacdev->MacBase, GmacGmiiAddr ,orig_data); + return 0; } /** @@ -41,10 +41,10 @@ s32 synopGMAC_set_mdc_clk_div(synopGMACdevice *gmacdev,u32 clk_div_val) */ u32 synopGMAC_get_mdc_clk_div(synopGMACdevice *gmacdev) { - u32 data; - data = synopGMACReadReg(gmacdev->MacBase,GmacGmiiAddr); - data &= GmiiCsrClkMask; - return data; + u32 data; + data = synopGMACReadReg(gmacdev->MacBase,GmacGmiiAddr); + data &= GmiiCsrClkMask; + return data; } @@ -59,34 +59,34 @@ u32 synopGMAC_get_mdc_clk_div(synopGMACdevice *gmacdev) */ s32 synopGMAC_read_phy_reg(u32 RegBase,u32 PhyBase, u32 RegOffset, u16 * data ) { - u32 addr; - u32 loop_variable; - addr = ((PhyBase << GmiiDevShift) & GmiiDevMask) | ((RegOffset << GmiiRegShift) & GmiiRegMask) - | GmiiCsrClk3; //sw: add GmiiCsrClk - addr = addr | GmiiBusy ; //Gmii busy bit - - synopGMACWriteReg(RegBase,GmacGmiiAddr,addr); - //write the address from where the data to be read in GmiiGmiiAddr register of synopGMAC ip - - for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ - //Wait till the busy bit gets cleared within a certain amount of time - if (!(synopGMACReadReg(RegBase,GmacGmiiAddr) & GmiiBusy)){ - break; - } - plat_delay(DEFAULT_DELAY_VARIABLE); - } - if(loop_variable < DEFAULT_LOOP_VARIABLE) - * data = (u16)(synopGMACReadReg(RegBase,GmacGmiiData) & 0xFFFF); - else{ - TR("Error::: PHY not responding Busy bit didnot get cleared !!!!!!\n"); - return -ESYNOPGMACPHYERR; - } - //sw + u32 addr; + u32 loop_variable; + addr = ((PhyBase << GmiiDevShift) & GmiiDevMask) | ((RegOffset << GmiiRegShift) & GmiiRegMask) + | GmiiCsrClk3; //sw: add GmiiCsrClk + addr = addr | GmiiBusy ; //Gmii busy bit + + synopGMACWriteReg(RegBase,GmacGmiiAddr,addr); + //write the address from where the data to be read in GmiiGmiiAddr register of synopGMAC ip + + for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ + //Wait till the busy bit gets cleared within a certain amount of time + if (!(synopGMACReadReg(RegBase,GmacGmiiAddr) & GmiiBusy)){ + break; + } + plat_delay(DEFAULT_DELAY_VARIABLE); + } + if(loop_variable < DEFAULT_LOOP_VARIABLE) + * data = (u16)(synopGMACReadReg(RegBase,GmacGmiiData) & 0xFFFF); + else{ + TR("Error::: PHY not responding Busy bit didnot get cleared !!!!!!\n"); + return -ESYNOPGMACPHYERR; + } + //sw #if SYNOP_REG_DEBUG - printf("read phy reg: offset = 0x%x\tdata = 0x%x\n",RegOffset,*data); + printf("read phy reg: offset = 0x%x\tdata = 0x%x\n",RegOffset,*data); #endif - return -ESYNOPGMACNOERR; + return -ESYNOPGMACNOERR; } /** @@ -105,14 +105,14 @@ s32 synopGMAC_write_phy_reg(u32 RegBase, u32 PhyBase, u32 RegOffset, u16 data) synopGMACWriteReg(RegBase,GmacGmiiData,data); // write the data in to GmacGmiiData register of synopGMAC ip - addr = ((PhyBase << GmiiDevShift) & GmiiDevMask) | ((RegOffset << GmiiRegShift) & GmiiRegMask) | GmiiWrite | GmiiCsrClk3; //sw: add GmiiCsrclk + addr = ((PhyBase << GmiiDevShift) & GmiiDevMask) | ((RegOffset << GmiiRegShift) & GmiiRegMask) | GmiiWrite | GmiiCsrClk3; //sw: add GmiiCsrclk addr = addr | GmiiBusy ; //set Gmii clk to 20-35 Mhz and Gmii busy bit synopGMACWriteReg(RegBase,GmacGmiiAddr,addr); for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ if (!(synopGMACReadReg(RegBase,GmacGmiiAddr) & GmiiBusy)){ - break; + break; } plat_delay(DEFAULT_DELAY_VARIABLE); } @@ -130,12 +130,12 @@ s32 synopGMAC_write_phy_reg(u32 RegBase, u32 PhyBase, u32 RegOffset, u16 data) } /** - * Function to configure the phy in loopback mode. + * Function to configure the phy in loopback mode. * * @param[in] pointer to synopGMACdevice. * @param[in] enable or disable the loopback. * \return 0 on success else return the error status. - * \note Don't get confused with mac loop-back synopGMAC_loopback_on(synopGMACdevice *) + * \note Don't get confused with mac loop-back synopGMAC_loopback_on(synopGMACdevice *) * and synopGMAC_loopback_off(synopGMACdevice *) functions. */ #if UNUSED @@ -143,13 +143,13 @@ s32 synopGMAC_phy_loopback(synopGMACdevice *gmacdev, bool loopback) { s32 status = -ESYNOPGMACNOERR; u16 *temp; - status = synopGMAC_read_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, PHY_CONTROL_REG,temp); + status = synopGMAC_read_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, PHY_CONTROL_REG,temp); if(loopback) - *temp |= 0x4000; + *temp |= 0x4000; else - *temp = *temp; + *temp = *temp; - status = synopGMAC_write_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, PHY_CONTROL_REG, *temp); + status = synopGMAC_write_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, PHY_CONTROL_REG, *temp); return status; } @@ -162,36 +162,36 @@ return status; * \return Always return 0. */ -s32 synopGMAC_read_version (synopGMACdevice * gmacdev) -{ - u32 data = 0; - data = synopGMACReadReg(gmacdev->MacBase, GmacVersion ); - gmacdev->Version = data; - return 0; +s32 synopGMAC_read_version (synopGMACdevice * gmacdev) +{ + u32 data = 0; + data = synopGMACReadReg(gmacdev->MacBase, GmacVersion ); + gmacdev->Version = data; + return 0; } /** - * Function to reset the GMAC core. + * Function to reset the GMAC core. * This reests the DMA and GMAC core. After reset all the registers holds their respective reset value * @param[in] pointer to synopGMACdevice. * \return 0 on success else return the error status. */ -s32 synopGMAC_reset (synopGMACdevice * gmacdev) -{ - u32 data = 0; - synopGMACWriteReg(gmacdev->DmaBase, DmaBusMode ,DmaResetOn); +s32 synopGMAC_reset (synopGMACdevice * gmacdev) +{ + u32 data = 0; + synopGMACWriteReg(gmacdev->DmaBase, DmaBusMode ,DmaResetOn); plat_delay(DEFAULT_LOOP_VARIABLE); - data = synopGMACReadReg(gmacdev->DmaBase, DmaBusMode); - TR("DATA after Reset = %08x\n",data); - - return 0; + data = synopGMACReadReg(gmacdev->DmaBase, DmaBusMode); + TR("DATA after Reset = %08x\n",data); + + return 0; } /** - * Function to program DMA bus mode register. - * + * Function to program DMA bus mode register. + * * The Bus Mode register is programmed with the value given. The bits to be set are * bit wise or'ed and sent as the second argument to this function. * @param[in] pointer to synopGMACdevice. @@ -200,14 +200,14 @@ s32 synopGMAC_reset (synopGMACdevice * gmacdev) */ s32 synopGMAC_dma_bus_mode_init(synopGMACdevice * gmacdev, u32 init_value ) { - synopGMACWriteReg(gmacdev->DmaBase, DmaBusMode ,init_value ); - return 0; + synopGMACWriteReg(gmacdev->DmaBase, DmaBusMode ,init_value ); + return 0; } /** - * Function to program DMA Control register. - * + * Function to program DMA Control register. + * * The Dma Control register is programmed with the value given. The bits to be set are * bit wise or'ed and sent as the second argument to this function. * @param[in] pointer to synopGMACdevice. @@ -216,15 +216,15 @@ s32 synopGMAC_dma_bus_mode_init(synopGMACdevice * gmacdev, u32 init_value ) */ s32 synopGMAC_dma_control_init(synopGMACdevice * gmacdev, u32 init_value ) { - synopGMACWriteReg(gmacdev->DmaBase, DmaControl, init_value); - return 0; + synopGMACWriteReg(gmacdev->DmaBase, DmaControl, init_value); + return 0; } /*Gmac configuration functions*/ /** - * Enable the watchdog timer on the receiver. + * Enable the watchdog timer on the receiver. * When enabled, Gmac enables Watchdog timer, and GMAC allows no more than * 2048 bytes of data (10,240 if Jumbo frame enabled). * @param[in] pointer to synopGMACdevice. @@ -232,11 +232,11 @@ s32 synopGMAC_dma_control_init(synopGMACdevice * gmacdev, u32 init_value ) */ void synopGMAC_wd_enable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacWatchdog); - return; + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacWatchdog); + return; } /** - * Disable the watchdog timer on the receiver. + * Disable the watchdog timer on the receiver. * When disabled, Gmac disabled watchdog timer, and can receive frames up to * 16,384 bytes. * @param[in] pointer to synopGMACdevice. @@ -245,24 +245,24 @@ void synopGMAC_wd_enable(synopGMACdevice * gmacdev) void synopGMAC_wd_disable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacWatchdog); - return; + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacWatchdog); + return; } /** - * Enables the Jabber frame support. + * Enables the Jabber frame support. * When enabled, GMAC disabled the jabber timer, and can transfer 16,384 byte frames. * @param[in] pointer to synopGMACdevice. * \return returns void. */ void synopGMAC_jab_enable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacJabber); - return; + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacJabber); + return; } /** - * Disables the Jabber frame support. - * When disabled, GMAC enables jabber timer. It cuts of transmitter if application + * Disables the Jabber frame support. + * When disabled, GMAC enables jabber timer. It cuts of transmitter if application * sends more than 2048 bytes of data (10240 if Jumbo frame enabled). * @param[in] pointer to synopGMACdevice. * \return returns void. @@ -270,13 +270,13 @@ void synopGMAC_jab_enable(synopGMACdevice * gmacdev) #if UNUSED void synopGMAC_jab_disable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacJabber); - return; + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacJabber); + return; } #endif /** - * Enables Frame bursting (Only in Half Duplex Mode). + * Enables Frame bursting (Only in Half Duplex Mode). * When enabled, GMAC allows frame bursting in GMII Half Duplex mode. * Reserved in 10/100 and Full-Duplex configurations. * @param[in] pointer to synopGMACdevice. @@ -284,11 +284,11 @@ void synopGMAC_jab_disable(synopGMACdevice * gmacdev) */ void synopGMAC_frame_burst_enable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacFrameBurst); - return; + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacFrameBurst); + return; } /** - * Disables Frame bursting. + * Disables Frame bursting. * When Disabled, frame bursting is not supported. * @param[in] pointer to synopGMACdevice. * \return returns void. @@ -296,13 +296,13 @@ void synopGMAC_frame_burst_enable(synopGMACdevice * gmacdev) #if UNUSED void synopGMAC_frame_burst_disable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacFrameBurst); - return; + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacFrameBurst); + return; } #endif /** - * Enable Jumbo frame support. + * Enable Jumbo frame support. * When Enabled GMAC supports jumbo frames of 9018/9022(VLAN tagged). * Giant frame error is not reported in receive frame status. * @param[in] pointer to synopGMACdevice. @@ -311,12 +311,12 @@ void synopGMAC_frame_burst_disable(synopGMACdevice * gmacdev) #if UNUSED void synopGMAC_jumbo_frame_enable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacJumboFrame); - return; + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacJumboFrame); + return; } #endif /** - * Disable Jumbo frame support. + * Disable Jumbo frame support. * When Disabled GMAC does not supports jumbo frames. * Giant frame error is reported in receive frame status. * @param[in] pointer to synopGMACdevice. @@ -324,12 +324,12 @@ void synopGMAC_jumbo_frame_enable(synopGMACdevice * gmacdev) */ void synopGMAC_jumbo_frame_disable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacJumboFrame); - return; + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacJumboFrame); + return; } /** - * Disable Carrier sense. + * Disable Carrier sense. * When Disabled GMAC ignores CRS signal during frame transmission * in half duplex mode. * @param[in] pointer to synopGMACdevice. @@ -339,49 +339,49 @@ void synopGMAC_jumbo_frame_disable(synopGMACdevice * gmacdev) #if UNUSED void synopGMAC_disable_crs(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacDisableCrs); - return; + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacDisableCrs); + return; } #endif /** - * Selects the GMII port. + * Selects the GMII port. * When called GMII (1000Mbps) port is selected (programmable only in 10/100/1000 Mbps configuration). * @param[in] pointer to synopGMACdevice. * \return returns void. */ void synopGMAC_select_gmii(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacMiiGmii); - return; + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacMiiGmii); + return; } /** - * Selects the MII port. + * Selects the MII port. * When called MII (10/100Mbps) port is selected (programmable only in 10/100/1000 Mbps configuration). * @param[in] pointer to synopGMACdevice. * \return returns void. */ void synopGMAC_select_mii(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacMiiGmii); - return; + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacMiiGmii); + return; } /** - * Enables Receive Own bit (Only in Half Duplex Mode). + * Enables Receive Own bit (Only in Half Duplex Mode). * When enaled GMAC receives all the packets given by phy while transmitting. * @param[in] pointer to synopGMACdevice. * \return returns void. */ void synopGMAC_rx_own_enable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacRxOwn); - return; + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacRxOwn); + return; } /** - * Disables Receive Own bit (Only in Half Duplex Mode). + * Disables Receive Own bit (Only in Half Duplex Mode). * When enaled GMAC disables the reception of frames when gmii_txen_o is asserted. * @param[in] pointer to synopGMACdevice. * \return returns void. @@ -389,13 +389,13 @@ void synopGMAC_rx_own_enable(synopGMACdevice * gmacdev) #if UNUSED void synopGMAC_rx_own_disable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacRxOwn); - return; + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacRxOwn); + return; } #endif /** - * Sets the GMAC in loopback mode. + * Sets the GMAC in loopback mode. * When on GMAC operates in loop-back mode at GMII/MII. * @param[in] pointer to synopGMACdevice. * \return returns void. @@ -404,66 +404,66 @@ void synopGMAC_rx_own_disable(synopGMACdevice * gmacdev) */ void synopGMAC_loopback_on(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacLoopback); - return; + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacLoopback); + return; } /** - * Sets the GMAC in Normal mode. + * Sets the GMAC in Normal mode. * @param[in] pointer to synopGMACdevice. * \return returns void. */ void synopGMAC_loopback_off(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacLoopback); - return; + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacLoopback); + return; } /** - * Sets the GMAC core in Full-Duplex mode. + * Sets the GMAC core in Full-Duplex mode. * @param[in] pointer to synopGMACdevice. * \return returns void. */ void synopGMAC_set_full_duplex(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacDuplex); - return; + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacDuplex); + return; } /** - * Sets the GMAC core in Half-Duplex mode. + * Sets the GMAC core in Half-Duplex mode. * @param[in] pointer to synopGMACdevice. * \return returns void. */ void synopGMAC_set_half_duplex(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacDuplex); - return; + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacDuplex); + return; } /** * GMAC tries retransmission (Only in Half Duplex mode). - * If collision occurs on the GMII/MII, GMAC attempt retries based on the - * back off limit configured. + * If collision occurs on the GMII/MII, GMAC attempt retries based on the + * back off limit configured. * @param[in] pointer to synopGMACdevice. * \return returns void. * \note This function is tightly coupled with synopGMAC_back_off_limit(synopGMACdev *, u32). */ void synopGMAC_retry_enable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacRetry); - return; + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacRetry); + return; } /** * GMAC tries only one transmission (Only in Half Duplex mode). * If collision occurs on the GMII/MII, GMAC will ignore the current frami - * transmission and report a frame abort with excessive collision in tranmit frame status. + * transmission and report a frame abort with excessive collision in tranmit frame status. * @param[in] pointer to synopGMACdevice. * \return returns void. */ #if UNUSED void synopGMAC_retry_disable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacRetry); - return; + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacRetry); + return; } #endif @@ -471,29 +471,29 @@ void synopGMAC_retry_disable(synopGMACdevice * gmacdev) * GMAC strips the Pad/FCS field of incoming frames. * This is true only if the length field value is less than or equal to * 1500 bytes. All received frames with length field greater than or equal to - * 1501 bytes are passed to the application without stripping the Pad/FCS field. + * 1501 bytes are passed to the application without stripping the Pad/FCS field. * @param[in] pointer to synopGMACdevice. * \return returns void. */ #if UNUSED void synopGMAC_pad_crc_strip_enable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacPadCrcStrip); - return; + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacPadCrcStrip); + return; } #endif /** * GMAC doesnot strips the Pad/FCS field of incoming frames. - * GMAC will pass all the incoming frames to Host unmodified. + * GMAC will pass all the incoming frames to Host unmodified. * @param[in] pointer to synopGMACdevice. * \return returns void. */ void synopGMAC_pad_crc_strip_disable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacPadCrcStrip); - u32 status = synopGMACReadReg(gmacdev->MacBase, GmacConfig); - DEBUG_MES("strips status : %u\n", status & GmacPadCrcStrip); - return; + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacPadCrcStrip); + u32 status = synopGMACReadReg(gmacdev->MacBase, GmacConfig); + DEBUG_MES("strips status : %u\n", status & GmacPadCrcStrip); + return; } /** * GMAC programmed with the back off limit value. @@ -503,30 +503,30 @@ void synopGMAC_pad_crc_strip_disable(synopGMACdevice * gmacdev) */ void synopGMAC_back_off_limit(synopGMACdevice * gmacdev, u32 value) { - u32 data; - data = synopGMACReadReg(gmacdev->MacBase, GmacConfig); - data &= (~GmacBackoffLimit); - data |= value; - synopGMACWriteReg(gmacdev->MacBase, GmacConfig,data); - return; + u32 data; + data = synopGMACReadReg(gmacdev->MacBase, GmacConfig); + data &= (~GmacBackoffLimit); + data |= value; + synopGMACWriteReg(gmacdev->MacBase, GmacConfig,data); + return; } /** * Enables the Deferral check in GMAC (Only in Half Duplex mode) - * GMAC issues a Frame Abort Status, along with the excessive deferral error bit set in the + * GMAC issues a Frame Abort Status, along with the excessive deferral error bit set in the * transmit frame status when transmit state machine is deferred for more than - * - 24,288 bit times in 10/100Mbps mode - * - 155,680 bit times in 1000Mbps mode or Jumbo frame mode in 10/100Mbps operation. + * - 24,288 bit times in 10/100Mbps mode + * - 155,680 bit times in 1000Mbps mode or Jumbo frame mode in 10/100Mbps operation. * @param[in] pointer to synopGMACdevice. * \return returns void. * \note Deferral begins when transmitter is ready to transmit, but is prevented because of - * an active CRS (carrier sense) + * an active CRS (carrier sense) */ #if UNUSED void synopGMAC_deferral_check_enable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacDeferralCheck); - return; + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacDeferralCheck); + return; } #endif /** @@ -537,8 +537,8 @@ void synopGMAC_deferral_check_enable(synopGMACdevice * gmacdev) */ void synopGMAC_deferral_check_disable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacDeferralCheck); - return; + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacDeferralCheck); + return; } /** * Enable the reception of frames on GMII/MII. @@ -547,8 +547,8 @@ void synopGMAC_deferral_check_disable(synopGMACdevice * gmacdev) */ void synopGMAC_rx_enable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacRx); - return; + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacRx); + return; } /** * Disable the reception of frames on GMII/MII. @@ -559,8 +559,8 @@ void synopGMAC_rx_enable(synopGMACdevice * gmacdev) #if UNUSED void synopGMAC_rx_disable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacRx); - return; + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacRx); + return; } #endif /** @@ -570,8 +570,8 @@ void synopGMAC_rx_disable(synopGMACdevice * gmacdev) */ void synopGMAC_tx_enable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacTx); - return; + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacTx); + return; } /** * Disable the transmission of frames on GMII/MII. @@ -582,8 +582,8 @@ void synopGMAC_tx_enable(synopGMACdevice * gmacdev) #if UNUSED void synopGMAC_tx_disable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacTx); - return; + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacTx); + return; } #endif @@ -599,20 +599,20 @@ void synopGMAC_tx_disable(synopGMACdevice * gmacdev) */ void synopGMAC_frame_filter_enable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacFilter); - return; + synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacFilter); + return; } /** * Disables reception of all the frames to application. - * GMAC passes only those received frames to application which + * GMAC passes only those received frames to application which * pass SA/DA address filtering. * @param[in] pointer to synopGMACdevice. - * \return void. + * \return void. */ void synopGMAC_frame_filter_disable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacFilter); - return; + synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacFilter); + return; } /** @@ -620,13 +620,13 @@ void synopGMAC_frame_filter_disable(synopGMACdevice * gmacdev) * This function is called when the Hash filtering is to be enabled. * @param[in] pointer to synopGMACdevice. * @param[in] data to be written to hash table high register. - * \return void. + * \return void. */ #if UNUSED void synopGMAC_write_hash_table_high(synopGMACdevice * gmacdev, u32 data) { - synopGMACWriteReg(gmacdev->MacBase,GmacHashHigh,data); - return; + synopGMACWriteReg(gmacdev->MacBase,GmacHashHigh,data); + return; } #endif @@ -635,71 +635,71 @@ void synopGMAC_write_hash_table_high(synopGMACdevice * gmacdev, u32 data) * This function is called when the Hash filtering is to be enabled. * @param[in] pointer to synopGMACdevice. * @param[in] data to be written to hash table low register. - * \return void. + * \return void. */ #if UNUSED void synopGMAC_write_hash_table_low(synopGMACdevice * gmacdev, u32 data) { - synopGMACWriteReg(gmacdev->MacBase,GmacHashLow,data); - return; + synopGMACWriteReg(gmacdev->MacBase,GmacHashLow,data); + return; } #endif /** * Enables Hash or Perfect filter (only if Hash filter is enabled in H/W). - * Only frames matching either perfect filtering or Hash Filtering as per HMC and HUC + * Only frames matching either perfect filtering or Hash Filtering as per HMC and HUC * configuration are sent to application. * @param[in] pointer to synopGMACdevice. - * \return void. + * \return void. */ #if UNUSED void synopGMAC_hash_perfect_filter_enable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacHashPerfectFilter); - return; + synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacHashPerfectFilter); + return; } #endif /** * Enables only Hash(only if Hash filter is enabled in H/W). - * Only frames matching Hash Filtering as per HMC and HUC + * Only frames matching Hash Filtering as per HMC and HUC * configuration are sent to application. * @param[in] pointer to synopGMACdevice. - * \return void. + * \return void. */ #if UNUSED void synopGMAC_Hash_filter_only_enable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacHashPerfectFilter); - return; + synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacHashPerfectFilter); + return; } #endif /** * Enables Source address filtering. - * When enabled source address filtering is performed. Only frames matching SA filtering are passed to application with - * SAMatch bit of RxStatus is set. GMAC drops failed frames. + * When enabled source address filtering is performed. Only frames matching SA filtering are passed to application with + * SAMatch bit of RxStatus is set. GMAC drops failed frames. * @param[in] pointer to synopGMACdevice. * \return void. - * \note This function is overriden by synopGMAC_frame_filter_disable(synopGMACdevice *) + * \note This function is overriden by synopGMAC_frame_filter_disable(synopGMACdevice *) */ #if UNUSED void synopGMAC_src_addr_filter_enable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacSrcAddrFilter); - return; + synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacSrcAddrFilter); + return; } #endif /** * Disables Source address filtering. - * When disabled GMAC forwards the received frames with updated SAMatch bit in RxStatus. + * When disabled GMAC forwards the received frames with updated SAMatch bit in RxStatus. * @param[in] pointer to synopGMACdevice. * \return void. */ void synopGMAC_src_addr_filter_disable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacSrcAddrFilter); - return; + synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacSrcAddrFilter); + return; } /** * Enables Inverse Destination address filtering. @@ -709,8 +709,8 @@ void synopGMAC_src_addr_filter_disable(synopGMACdevice * gmacdev) #if UNUSED void synopGMAC_dst_addr_filter_inverse(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacDestAddrFilterNor); - return; + synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacDestAddrFilterNor); + return; } #endif /** @@ -720,8 +720,8 @@ void synopGMAC_dst_addr_filter_inverse(synopGMACdevice * gmacdev) */ void synopGMAC_dst_addr_filter_normal(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacDestAddrFilterNor); - return; + synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacDestAddrFilterNor); + return; } /** @@ -732,13 +732,13 @@ void synopGMAC_dst_addr_filter_normal(synopGMACdevice * gmacdev) * \note Depends on RFE of FlowControlRegister[2] */ void synopGMAC_set_pass_control(synopGMACdevice * gmacdev,u32 passcontrol) -{ - u32 data; - data = synopGMACReadReg(gmacdev->MacBase, GmacFrameFilter); - data &= (~GmacPassControl); - data |= passcontrol; - synopGMACWriteReg(gmacdev->MacBase,GmacFrameFilter,data); - return; +{ + u32 data; + data = synopGMACReadReg(gmacdev->MacBase, GmacFrameFilter); + data &= (~GmacPassControl); + data |= passcontrol; + synopGMACWriteReg(gmacdev->MacBase,GmacFrameFilter,data); + return; } /** @@ -749,8 +749,8 @@ void synopGMAC_set_pass_control(synopGMACdevice * gmacdev,u32 passcontrol) */ void synopGMAC_broadcast_enable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacBroadcast ); - return; + synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacBroadcast ); + return; } /** * Disable Broadcast frames. @@ -761,8 +761,8 @@ void synopGMAC_broadcast_enable(synopGMACdevice * gmacdev) #if UNUSED void synopGMAC_broadcast_disable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacBroadcast); - return; + synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacBroadcast); + return; } #endif @@ -775,8 +775,8 @@ void synopGMAC_broadcast_disable(synopGMACdevice * gmacdev) #if UNUSED void synopGMAC_multicast_enable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacMulticastFilter); - return; + synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacMulticastFilter); + return; } #endif /** @@ -787,8 +787,8 @@ void synopGMAC_multicast_enable(synopGMACdevice * gmacdev) */ void synopGMAC_multicast_disable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacMulticastFilter); - return; + synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacMulticastFilter); + return; } /** @@ -800,21 +800,21 @@ void synopGMAC_multicast_disable(synopGMACdevice * gmacdev) #if UNUSED void synopGMAC_multicast_hash_filter_enable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacMcastHashFilter); - return; + synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacMcastHashFilter); + return; } #endif /** * Disables multicast hash filtering. - * When disabled GMAC performs perfect destination address filtering for multicast frames, it compares + * When disabled GMAC performs perfect destination address filtering for multicast frames, it compares * DA field with the value programmed in DA register. * @param[in] pointer to synopGMACdevice. * \return void. */ void synopGMAC_multicast_hash_filter_disable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacMcastHashFilter); - return; + synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacMcastHashFilter); + return; } /** @@ -827,8 +827,8 @@ void synopGMAC_multicast_hash_filter_disable(synopGMACdevice * gmacdev) #if UNUSED void synopGMAC_promisc_enable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacPromiscuousMode); - return; + synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacPromiscuousMode); + return; } #endif /** @@ -839,8 +839,8 @@ void synopGMAC_promisc_enable(synopGMACdevice * gmacdev) */ void synopGMAC_promisc_disable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacPromiscuousMode); - return; + synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacPromiscuousMode); + return; } @@ -853,23 +853,23 @@ void synopGMAC_promisc_disable(synopGMACdevice * gmacdev) #if UNUSED void synopGMAC_unicast_hash_filter_enable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacUcastHashFilter); - return; + synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacUcastHashFilter); + return; } #endif /** * Disables multicast hash filtering. - * When disabled GMAC performs perfect destination address filtering for unicast frames, it compares + * When disabled GMAC performs perfect destination address filtering for unicast frames, it compares * DA field with the value programmed in DA register. * @param[in] pointer to synopGMACdevice. * \return void. */ void synopGMAC_unicast_hash_filter_disable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacUcastHashFilter); - return; + synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacUcastHashFilter); + return; } - + /*Flow control configuration functions*/ /** @@ -882,8 +882,8 @@ void synopGMAC_unicast_hash_filter_disable(synopGMACdevice * gmacdev) #if UNUSED void synopGMAC_unicast_pause_frame_detect_enable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacFlowControl, GmacUnicastPauseFrame); - return; + synopGMACSetBits(gmacdev->MacBase, GmacFlowControl, GmacUnicastPauseFrame); + return; } #endif /** @@ -894,8 +894,8 @@ void synopGMAC_unicast_pause_frame_detect_enable(synopGMACdevice * gmacdev) */ void synopGMAC_unicast_pause_frame_detect_disable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacFlowControl, GmacUnicastPauseFrame); - return; + synopGMACClearBits(gmacdev->MacBase, GmacFlowControl, GmacUnicastPauseFrame); + return; } /** * Rx flow control enable. @@ -905,8 +905,8 @@ void synopGMAC_unicast_pause_frame_detect_disable(synopGMACdevice * gmacdev) */ void synopGMAC_rx_flow_control_enable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacFlowControl, GmacRxFlowControl); - return; + synopGMACSetBits(gmacdev->MacBase, GmacFlowControl, GmacRxFlowControl); + return; } /** * Rx flow control disable. @@ -916,60 +916,60 @@ void synopGMAC_rx_flow_control_enable(synopGMACdevice * gmacdev) */ void synopGMAC_rx_flow_control_disable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacFlowControl, GmacRxFlowControl); - return; + synopGMACClearBits(gmacdev->MacBase, GmacFlowControl, GmacRxFlowControl); + return; } /** * Tx flow control enable. - * When Enabled - * - In full duplex GMAC enables flow control operation to transmit pause frames. - * - In Half duplex GMAC enables the back pressure operation + * When Enabled + * - In full duplex GMAC enables flow control operation to transmit pause frames. + * - In Half duplex GMAC enables the back pressure operation * @param[in] pointer to synopGMACdevice. * \return void. */ void synopGMAC_tx_flow_control_enable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacFlowControl, GmacTxFlowControl); - return; + synopGMACSetBits(gmacdev->MacBase, GmacFlowControl, GmacTxFlowControl); + return; } /** * Tx flow control disable. - * When Disabled - * - In full duplex GMAC will not transmit any pause frames. - * - In Half duplex GMAC disables the back pressure feature. + * When Disabled + * - In full duplex GMAC will not transmit any pause frames. + * - In Half duplex GMAC disables the back pressure feature. * @param[in] pointer to synopGMACdevice. * \return void. */ void synopGMAC_tx_flow_control_disable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacFlowControl, GmacTxFlowControl); - return; + synopGMACClearBits(gmacdev->MacBase, GmacFlowControl, GmacTxFlowControl); + return; } /** * Initiate Flowcontrol operation. * When Set - * - In full duplex GMAC initiates pause control frame. - * - In Half duplex GMAC initiates back pressure function. + * - In full duplex GMAC initiates pause control frame. + * - In Half duplex GMAC initiates back pressure function. * @param[in] pointer to synopGMACdevice. * \return void. */ #if UNUSED void synopGMAC_tx_activate_flow_control(synopGMACdevice * gmacdev) { - //In case of full duplex check for this bit to b'0. if it is read as b'1 indicates that + //In case of full duplex check for this bit to b'0. if it is read as b'1 indicates that //control frame transmission is in progress. - if(gmacdev->Speed == FULLDUPLEX){ - if(!synopGMACCheckBits(gmacdev->MacBase, GmacFlowControl, GmacFlowControlBackPressure)) - synopGMACSetBits(gmacdev->MacBase, GmacFlowControl, GmacFlowControlBackPressure); - } - else{ //if half duplex mode - - synopGMACSetBits(gmacdev->MacBase, GmacFlowControl, GmacFlowControlBackPressure); - } + if(gmacdev->Speed == FULLDUPLEX){ + if(!synopGMACCheckBits(gmacdev->MacBase, GmacFlowControl, GmacFlowControlBackPressure)) + synopGMACSetBits(gmacdev->MacBase, GmacFlowControl, GmacFlowControlBackPressure); + } + else{ //if half duplex mode + + synopGMACSetBits(gmacdev->MacBase, GmacFlowControl, GmacFlowControlBackPressure); + } - return; + return; } #endif @@ -981,11 +981,11 @@ void synopGMAC_tx_activate_flow_control(synopGMACdevice * gmacdev) #if UNUSED void synopGMAC_tx_deactivate_flow_control(synopGMACdevice * gmacdev) { - //In full duplex this bit is automatically cleared after transmitting a pause control frame. - if(gmacdev->Speed == HALFDUPLEX){ - synopGMACSetBits(gmacdev->MacBase, GmacFlowControl, GmacFlowControlBackPressure); - } - return; + //In full duplex this bit is automatically cleared after transmitting a pause control frame. + if(gmacdev->Speed == HALFDUPLEX){ + synopGMACSetBits(gmacdev->MacBase, GmacFlowControl, GmacFlowControlBackPressure); + } + return; } #endif @@ -998,17 +998,17 @@ void synopGMAC_tx_deactivate_flow_control(synopGMACdevice * gmacdev) */ void synopGMAC_pause_control(synopGMACdevice *gmacdev) { - u32 omr_reg; - u32 mac_flow_control_reg; - omr_reg = synopGMACReadReg(gmacdev->DmaBase,DmaControl); - omr_reg |= DmaRxFlowCtrlAct4K | DmaRxFlowCtrlDeact5K |DmaEnHwFlowCtrl; - synopGMACWriteReg(gmacdev->DmaBase, DmaControl, omr_reg); + u32 omr_reg; + u32 mac_flow_control_reg; + omr_reg = synopGMACReadReg(gmacdev->DmaBase,DmaControl); + omr_reg |= DmaRxFlowCtrlAct4K | DmaRxFlowCtrlDeact5K |DmaEnHwFlowCtrl; + synopGMACWriteReg(gmacdev->DmaBase, DmaControl, omr_reg); - mac_flow_control_reg = synopGMACReadReg(gmacdev->MacBase,GmacFlowControl); - mac_flow_control_reg |= GmacRxFlowControl | GmacTxFlowControl | 0xFFFF0000; - synopGMACWriteReg(gmacdev->MacBase,GmacFlowControl,mac_flow_control_reg); + mac_flow_control_reg = synopGMACReadReg(gmacdev->MacBase,GmacFlowControl); + mac_flow_control_reg |= GmacRxFlowControl | GmacTxFlowControl | 0xFFFF0000; + synopGMACWriteReg(gmacdev->MacBase,GmacFlowControl,mac_flow_control_reg); - return; + return; } @@ -1021,126 +1021,126 @@ void synopGMAC_pause_control(synopGMACdevice *gmacdev) */ s32 synopGMAC_mac_init(synopGMACdevice * gmacdev) { - u32 PHYreg; - - if(gmacdev->DuplexMode == FULLDUPLEX){ - TR("\n===phy FULLDUPLEX MODE\n"); //sw: debug - synopGMAC_wd_enable(gmacdev); - synopGMAC_jab_enable(gmacdev); - synopGMAC_frame_burst_enable(gmacdev); - synopGMAC_jumbo_frame_disable(gmacdev); - synopGMAC_rx_own_enable(gmacdev); + u32 PHYreg; + + if(gmacdev->DuplexMode == FULLDUPLEX){ + TR("\n===phy FULLDUPLEX MODE\n"); //sw: debug + synopGMAC_wd_enable(gmacdev); + synopGMAC_jab_enable(gmacdev); + synopGMAC_frame_burst_enable(gmacdev); + synopGMAC_jumbo_frame_disable(gmacdev); + synopGMAC_rx_own_enable(gmacdev); #if SYNOP_LOOPBACK_MODE - synopGMAC_loopback_on(gmacdev); + synopGMAC_loopback_on(gmacdev); #else - synopGMAC_loopback_off(gmacdev); -#endif - synopGMAC_set_full_duplex(gmacdev); //1 - synopGMAC_retry_enable(gmacdev); - synopGMAC_pad_crc_strip_disable(gmacdev); - synopGMAC_back_off_limit(gmacdev,GmacBackoffLimit0); - synopGMAC_deferral_check_disable(gmacdev); - - synopGMAC_tx_enable(gmacdev); //according to Tang Dan's commitment - synopGMAC_rx_enable(gmacdev); - - synopGMACSetBits(gmacdev->DmaBase,DmaControl, DmaStoreAndForward );//3 - synopGMACSetBits(gmacdev->DmaBase,DmaControl, DmaFwdErrorFrames ); - if(gmacdev->Speed == SPEED1000) - synopGMAC_select_gmii(gmacdev); - else{ - synopGMAC_select_mii(gmacdev); - if(gmacdev->Speed == SPEED100) - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacFESpeed100); - else - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacFESpeed10); - } - - - /*Frame Filter Configuration*/ - synopGMAC_frame_filter_enable(gmacdev); //2 - //synopGMAC_frame_filter_disable(gmacdev); //2 - synopGMAC_set_pass_control(gmacdev,GmacPassControl0); - synopGMAC_broadcast_enable(gmacdev); - synopGMAC_src_addr_filter_disable(gmacdev); - synopGMAC_multicast_disable(gmacdev); - //synopGMAC_dst_addr_filter_normal(gmacdev); //scl - synopGMAC_dst_addr_filter_inverse(gmacdev); - synopGMAC_multicast_hash_filter_disable(gmacdev); - synopGMAC_promisc_disable(gmacdev); - synopGMAC_unicast_hash_filter_disable(gmacdev); - - /*Flow Control Configuration*/ - synopGMAC_unicast_pause_frame_detect_disable(gmacdev); - synopGMAC_rx_flow_control_enable(gmacdev); - synopGMAC_tx_flow_control_enable(gmacdev); - } - else{//for Half Duplex configuration - - TR("\n===phy HALFDUPLEX MODE\n"); //sw: debug - synopGMAC_wd_enable(gmacdev ); - synopGMAC_jab_enable(gmacdev); - synopGMAC_frame_burst_enable(gmacdev); - synopGMAC_jumbo_frame_disable(gmacdev); - synopGMAC_rx_own_enable(gmacdev); + synopGMAC_loopback_off(gmacdev); +#endif + synopGMAC_set_full_duplex(gmacdev); //1 + synopGMAC_retry_enable(gmacdev); + synopGMAC_pad_crc_strip_disable(gmacdev); + synopGMAC_back_off_limit(gmacdev,GmacBackoffLimit0); + synopGMAC_deferral_check_disable(gmacdev); + + synopGMAC_tx_enable(gmacdev); //according to Tang Dan's commitment + synopGMAC_rx_enable(gmacdev); + + synopGMACSetBits(gmacdev->DmaBase,DmaControl, DmaStoreAndForward );//3 + synopGMACSetBits(gmacdev->DmaBase,DmaControl, DmaFwdErrorFrames ); + if(gmacdev->Speed == SPEED1000) + synopGMAC_select_gmii(gmacdev); + else{ + synopGMAC_select_mii(gmacdev); + if(gmacdev->Speed == SPEED100) + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacFESpeed100); + else + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacFESpeed10); + } + + + /*Frame Filter Configuration*/ + synopGMAC_frame_filter_enable(gmacdev); //2 + //synopGMAC_frame_filter_disable(gmacdev); //2 + synopGMAC_set_pass_control(gmacdev,GmacPassControl0); + synopGMAC_broadcast_enable(gmacdev); + synopGMAC_src_addr_filter_disable(gmacdev); + synopGMAC_multicast_disable(gmacdev); + //synopGMAC_dst_addr_filter_normal(gmacdev); //scl + synopGMAC_dst_addr_filter_inverse(gmacdev); + synopGMAC_multicast_hash_filter_disable(gmacdev); + synopGMAC_promisc_disable(gmacdev); + synopGMAC_unicast_hash_filter_disable(gmacdev); + + /*Flow Control Configuration*/ + synopGMAC_unicast_pause_frame_detect_disable(gmacdev); + synopGMAC_rx_flow_control_enable(gmacdev); + synopGMAC_tx_flow_control_enable(gmacdev); + } + else{//for Half Duplex configuration + + TR("\n===phy HALFDUPLEX MODE\n"); //sw: debug + synopGMAC_wd_enable(gmacdev ); + synopGMAC_jab_enable(gmacdev); + synopGMAC_frame_burst_enable(gmacdev); + synopGMAC_jumbo_frame_disable(gmacdev); + synopGMAC_rx_own_enable(gmacdev); #if SYNOP_LOOPBACK_MODE - synopGMAC_loopback_on(gmacdev); + synopGMAC_loopback_on(gmacdev); #else - synopGMAC_loopback_off(gmacdev); + synopGMAC_loopback_off(gmacdev); #endif - synopGMAC_set_half_duplex(gmacdev); - synopGMAC_retry_enable(gmacdev); - synopGMAC_pad_crc_strip_disable(gmacdev); - synopGMAC_back_off_limit(gmacdev,GmacBackoffLimit0); - synopGMAC_deferral_check_disable(gmacdev); + synopGMAC_set_half_duplex(gmacdev); + synopGMAC_retry_enable(gmacdev); + synopGMAC_pad_crc_strip_disable(gmacdev); + synopGMAC_back_off_limit(gmacdev,GmacBackoffLimit0); + synopGMAC_deferral_check_disable(gmacdev); //sw: set efe & tsf - synopGMACSetBits(gmacdev->DmaBase,DmaControl, DmaStoreAndForward ); - synopGMACSetBits(gmacdev->DmaBase,DmaControl, DmaFwdErrorFrames ); + synopGMACSetBits(gmacdev->DmaBase,DmaControl, DmaStoreAndForward ); + synopGMACSetBits(gmacdev->DmaBase,DmaControl, DmaFwdErrorFrames ); //sw: put it in the end - synopGMAC_tx_enable(gmacdev); - synopGMAC_rx_enable(gmacdev); - - - if(gmacdev->Speed == SPEED1000) - synopGMAC_select_gmii(gmacdev); - else{ - synopGMAC_select_mii(gmacdev ); - if(gmacdev->Speed == SPEED100) - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacFESpeed100 ); - else - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacFESpeed10 ); - } - -// synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacDisableCrs); -// synopGMAC_select_gmii(gmacdev); - - /*Frame Filter Configuration*/ - synopGMAC_frame_filter_enable(gmacdev); -// synopGMAC_frame_filter_disable(gmacdev); - - synopGMAC_set_pass_control(gmacdev,GmacPassControl0); - synopGMAC_broadcast_enable(gmacdev); - synopGMAC_src_addr_filter_disable(gmacdev); - synopGMAC_multicast_disable(gmacdev); - synopGMAC_dst_addr_filter_normal(gmacdev); - synopGMAC_multicast_hash_filter_disable(gmacdev); - - synopGMAC_promisc_disable(gmacdev); -// synopGMAC_promisc_enable(gmacdev); - synopGMAC_unicast_hash_filter_disable(gmacdev); - + synopGMAC_tx_enable(gmacdev); + synopGMAC_rx_enable(gmacdev); + + + if(gmacdev->Speed == SPEED1000) + synopGMAC_select_gmii(gmacdev); + else{ + synopGMAC_select_mii(gmacdev ); + if(gmacdev->Speed == SPEED100) + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacFESpeed100 ); + else + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacFESpeed10 ); + } + +// synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacDisableCrs); +// synopGMAC_select_gmii(gmacdev); + + /*Frame Filter Configuration*/ + synopGMAC_frame_filter_enable(gmacdev); +// synopGMAC_frame_filter_disable(gmacdev); + + synopGMAC_set_pass_control(gmacdev,GmacPassControl0); + synopGMAC_broadcast_enable(gmacdev); + synopGMAC_src_addr_filter_disable(gmacdev); + synopGMAC_multicast_disable(gmacdev); + synopGMAC_dst_addr_filter_normal(gmacdev); + synopGMAC_multicast_hash_filter_disable(gmacdev); + + synopGMAC_promisc_disable(gmacdev); +// synopGMAC_promisc_enable(gmacdev); + synopGMAC_unicast_hash_filter_disable(gmacdev); + //sw: loopback mode -// synopGMAC_loopback_on(gmacdev); - - /*Flow Control Configuration*/ - synopGMAC_unicast_pause_frame_detect_disable(gmacdev); - synopGMAC_rx_flow_control_disable(gmacdev); - synopGMAC_tx_flow_control_disable(gmacdev); +// synopGMAC_loopback_on(gmacdev); + + /*Flow Control Configuration*/ + synopGMAC_unicast_pause_frame_detect_disable(gmacdev); + synopGMAC_rx_flow_control_disable(gmacdev); + synopGMAC_tx_flow_control_disable(gmacdev); - /*To set PHY register to enable CRS on Transmit*/ - } - return 0; + /*To set PHY register to enable CRS on Transmit*/ + } + return 0; } @@ -1155,14 +1155,14 @@ s32 synopGMAC_mac_init(synopGMACdevice * gmacdev) */ s32 synopGMAC_set_mac_addr(synopGMACdevice *gmacdev, u32 MacHigh, u32 MacLow, u8 *MacAddr) { - u32 data; + u32 data; - data = (MacAddr[5] << 8) | MacAddr[4]; - synopGMACWriteReg(gmacdev->MacBase,MacHigh,data); - data = (MacAddr[3] << 24) | (MacAddr[2] << 16) | (MacAddr[1] << 8) | MacAddr[0] ; - synopGMACWriteReg(gmacdev->MacBase,MacLow,data); + data = (MacAddr[5] << 8) | MacAddr[4]; + synopGMACWriteReg(gmacdev->MacBase,MacHigh,data); + data = (MacAddr[3] << 24) | (MacAddr[2] << 16) | (MacAddr[1] << 8) | MacAddr[0] ; + synopGMACWriteReg(gmacdev->MacBase,MacLow,data); - return 0; + return 0; } @@ -1177,21 +1177,21 @@ s32 synopGMAC_set_mac_addr(synopGMACdevice *gmacdev, u32 MacHigh, u32 MacLow, u8 */ s32 synopGMAC_get_mac_addr(synopGMACdevice *gmacdev, u32 MacHigh, u32 MacLow, u8 *MacAddr) { - u32 data; - - data = synopGMACReadReg(gmacdev->MacBase,MacHigh); - MacAddr[5] = (data >> 8) & 0xff; - MacAddr[4] = (data) & 0xff; + u32 data; + + data = synopGMACReadReg(gmacdev->MacBase,MacHigh); + MacAddr[5] = (data >> 8) & 0xff; + MacAddr[4] = (data) & 0xff; - data = synopGMACReadReg(gmacdev->MacBase,MacLow); - MacAddr[3] = (data >> 24) & 0xff; - MacAddr[2] = (data >> 16) & 0xff; - MacAddr[1] = (data >> 8 ) & 0xff; - MacAddr[0] = (data ) & 0xff; + data = synopGMACReadReg(gmacdev->MacBase,MacLow); + MacAddr[3] = (data >> 24) & 0xff; + MacAddr[2] = (data >> 16) & 0xff; + MacAddr[1] = (data >> 8 ) & 0xff; + MacAddr[0] = (data ) & 0xff; -// rt_kprintf("MacAddr = 0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\n",MacAddr[0],MacAddr[1],MacAddr[2],MacAddr[3],MacAddr[4],MacAddr[5]); +// rt_kprintf("MacAddr = 0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\n",MacAddr[0],MacAddr[1],MacAddr[2],MacAddr[3],MacAddr[4],MacAddr[5]); - return 0; + return 0; } @@ -1203,42 +1203,42 @@ s32 synopGMAC_get_mac_addr(synopGMACdevice *gmacdev, u32 MacHigh, u32 MacLow, u8 * @param[in] GMAC IP dma base address. * @param[in] GMAC IP phy base address. * \return 0 upon success. Error code upon failure. - * \note This is important function. No kernel api provided by Synopsys + * \note This is important function. No kernel api provided by Synopsys */ s32 synopGMAC_attach (synopGMACdevice * gmacdev, u32 macBase, u32 dmaBase, u32 phyBase,u8 *mac_addr) { - /*Make sure the Device data strucure is cleared before we proceed further*/ - rt_memset((void *) gmacdev,0,sizeof(synopGMACdevice)); - /*Populate the mac and dma base addresses*/ - gmacdev->MacBase = macBase; - gmacdev->DmaBase = dmaBase; - gmacdev->PhyBase = phyBase; -// rt_kprintf("gmacdev->DmaBase = 0x%x\n", gmacdev->DmaBase); -// rt_kprintf("dmaBase = 0x%x\n", dmaBase); - { - int i,j; - u16 data; - for (i = phyBase,j=0;j<32;i=(i+1)&0x1f,j++) - { - synopGMAC_read_phy_reg(gmacdev->MacBase,i,2,&data); - if(data != 0 && data != 0xffff) break; - synopGMAC_read_phy_reg(gmacdev->MacBase,i,3,&data); - if(data != 0 && data != 0xffff) break; - } + /*Make sure the Device data strucure is cleared before we proceed further*/ + rt_memset((void *) gmacdev,0,sizeof(synopGMACdevice)); + /*Populate the mac and dma base addresses*/ + gmacdev->MacBase = macBase; + gmacdev->DmaBase = dmaBase; + gmacdev->PhyBase = phyBase; +// rt_kprintf("gmacdev->DmaBase = 0x%x\n", gmacdev->DmaBase); +// rt_kprintf("dmaBase = 0x%x\n", dmaBase); + { + int i,j; + u16 data; + for (i = phyBase,j=0;j<32;i=(i+1)&0x1f,j++) + { + synopGMAC_read_phy_reg(gmacdev->MacBase,i,2,&data); + if(data != 0 && data != 0xffff) break; + synopGMAC_read_phy_reg(gmacdev->MacBase,i,3,&data); + if(data != 0 && data != 0xffff) break; + } - if(j==32) { - rt_kprintf("phy_detect: can't find PHY!\n"); - } - gmacdev->PhyBase = i; - } + if(j==32) { + rt_kprintf("phy_detect: can't find PHY!\n"); + } + gmacdev->PhyBase = i; + } -// synopGMAC_get_mac_addr(gmacdev, GmacAddr0High, GmacAddr0Low, mac_addr); +// synopGMAC_get_mac_addr(gmacdev, GmacAddr0High, GmacAddr0Low, mac_addr); - /* Program/flash in the station/IP's Mac address */ - synopGMAC_set_mac_addr(gmacdev,GmacAddr0High,GmacAddr0Low, mac_addr); + /* Program/flash in the station/IP's Mac address */ + synopGMAC_set_mac_addr(gmacdev,GmacAddr0High,GmacAddr0Low, mac_addr); - return 0; + return 0; } @@ -1246,10 +1246,10 @@ s32 synopGMAC_attach (synopGMACdevice * gmacdev, u32 macBase, u32 dmaBase, u32 p /** * Initialize the rx descriptors for ring or chain mode operation. - * - Status field is initialized to 0. - * - EndOfRing set for the last descriptor. - * - buffer1 and buffer2 set to 0 for ring mode of operation. (note) - * - data1 and data2 set to 0. (note) + * - Status field is initialized to 0. + * - EndOfRing set for the last descriptor. + * - buffer1 and buffer2 set to 0 for ring mode of operation. (note) + * - data1 and data2 set to 0. (note) * @param[in] pointer to DmaDesc structure. * @param[in] whether end of ring * \return void. @@ -1258,36 +1258,36 @@ s32 synopGMAC_attach (synopGMACdevice * gmacdev, u32 macBase, u32 dmaBase, u32 p */ void synopGMAC_rx_desc_init_ring(DmaDesc *desc, bool last_ring_desc) { - desc->status = 0; - desc->length = last_ring_desc ? RxDescEndOfRing : 0; - desc->buffer1 = 0; - desc->buffer2 = 0; - desc->data1 = 0; - desc->data2 = 0; - desc->dummy1 = 0; - desc->dummy2 = 0; + desc->status = 0; + desc->length = last_ring_desc ? RxDescEndOfRing : 0; + desc->buffer1 = 0; + desc->buffer2 = 0; + desc->data1 = 0; + desc->data2 = 0; + desc->dummy1 = 0; + desc->dummy2 = 0; - return; + return; } void synopGMAC_rx_desc_recycle(DmaDesc *desc, bool last_ring_desc) { - desc->status = DescOwnByDma; - desc->length = last_ring_desc ? RxDescEndOfRing : 0; - //desc->buffer1 = 0; - //desc->buffer2 = 0; - //desc->data1 = 0; - //desc->data2 = 0; - desc->dummy1 = 0; - desc->dummy2 = 0; + desc->status = DescOwnByDma; + desc->length = last_ring_desc ? RxDescEndOfRing : 0; + //desc->buffer1 = 0; + //desc->buffer2 = 0; + //desc->data1 = 0; + //desc->data2 = 0; + desc->dummy1 = 0; + desc->dummy2 = 0; - return; + return; } /** * Initialize the tx descriptors for ring or chain mode operation. - * - Status field is initialized to 0. - * - EndOfRing set for the last descriptor. - * - buffer1 and buffer2 set to 0 for ring mode of operation. (note) - * - data1 and data2 set to 0. (note) + * - Status field is initialized to 0. + * - EndOfRing set for the last descriptor. + * - buffer1 and buffer2 set to 0 for ring mode of operation. (note) + * - data1 and data2 set to 0. (note) * @param[in] pointer to DmaDesc structure. * @param[in] whether end of ring * \return void. @@ -1296,32 +1296,32 @@ void synopGMAC_rx_desc_recycle(DmaDesc *desc, bool last_ring_desc) */ void synopGMAC_tx_desc_init_ring(DmaDesc *desc, bool last_ring_desc) { - #ifdef ENH_DESC - desc->status = last_ring_desc? TxDescEndOfRing : 0; - desc->length = 0; - #else - desc->length = last_ring_desc? TxDescEndOfRing : 0; - #endif -//sw - desc->status = 0; + #ifdef ENH_DESC + desc->status = last_ring_desc? TxDescEndOfRing : 0; + desc->length = 0; + #else + desc->length = last_ring_desc? TxDescEndOfRing : 0; + #endif +//sw + desc->status = 0; - desc->buffer1 = 0; - desc->buffer2 = 0; - desc->data1 = 0; - desc->data2 = 0; - desc->dummy1 = 0; - desc->dummy2 = 0; - return; + desc->buffer1 = 0; + desc->buffer2 = 0; + desc->data1 = 0; + desc->data2 = 0; + desc->dummy1 = 0; + desc->dummy2 = 0; + return; } /** * Initialize the rx descriptors for chain mode of operation. - * - Status field is initialized to 0. - * - EndOfRing set for the last descriptor. - * - buffer1 and buffer2 set to 0. - * - data1 and data2 set to 0. + * - Status field is initialized to 0. + * - EndOfRing set for the last descriptor. + * - buffer1 and buffer2 set to 0. + * - data1 and data2 set to 0. * @param[in] pointer to DmaDesc structure. * @param[in] whether end of ring * \return void. @@ -1329,86 +1329,86 @@ void synopGMAC_tx_desc_init_ring(DmaDesc *desc, bool last_ring_desc) void synopGMAC_rx_desc_init_chain(DmaDesc * desc) { - desc->status = 0; - desc->length = RxDescChain; - desc->buffer1 = 0; - desc->data1 = 0; - return; + desc->status = 0; + desc->length = RxDescChain; + desc->buffer1 = 0; + desc->data1 = 0; + return; } /** * Initialize the rx descriptors for chain mode of operation. - * - Status field is initialized to 0. - * - EndOfRing set for the last descriptor. - * - buffer1 and buffer2 set to 0. - * - data1 and data2 set to 0. + * - Status field is initialized to 0. + * - EndOfRing set for the last descriptor. + * - buffer1 and buffer2 set to 0. + * - data1 and data2 set to 0. * @param[in] pointer to DmaDesc structure. * @param[in] whether end of ring * \return void. */ void synopGMAC_tx_desc_init_chain(DmaDesc * desc) { - #ifdef ENH_DESC - desc->status = TxDescChain; - desc->length = 0; - #else - desc->length = TxDescChain; - #endif - desc->buffer1 = 0; - desc->data1 = 0; - return; + #ifdef ENH_DESC + desc->status = TxDescChain; + desc->length = 0; + #else + desc->length = TxDescChain; + #endif + desc->buffer1 = 0; + desc->data1 = 0; + return; } s32 synopGMAC_init_tx_rx_desc_queue(synopGMACdevice *gmacdev) { - s32 i; - for(i =0; i < gmacdev -> TxDescCount; i++){ - synopGMAC_tx_desc_init_ring(gmacdev->TxDesc + i, i == gmacdev->TxDescCount-1); - } - TR("At line %d\n",__LINE__); - for(i =0; i < gmacdev -> RxDescCount; i++){ - synopGMAC_rx_desc_init_ring(gmacdev->RxDesc + i, i == gmacdev->RxDescCount-1); - } - - gmacdev->TxNext = 0; - gmacdev->TxBusy = 0; - gmacdev->RxNext = 0; - gmacdev->RxBusy = 0; - - return -ESYNOPGMACNOERR; + s32 i; + for(i =0; i < gmacdev -> TxDescCount; i++){ + synopGMAC_tx_desc_init_ring(gmacdev->TxDesc + i, i == gmacdev->TxDescCount-1); + } + TR("At line %d\n",__LINE__); + for(i =0; i < gmacdev -> RxDescCount; i++){ + synopGMAC_rx_desc_init_ring(gmacdev->RxDesc + i, i == gmacdev->RxDescCount-1); + } + + gmacdev->TxNext = 0; + gmacdev->TxBusy = 0; + gmacdev->RxNext = 0; + gmacdev->RxBusy = 0; + + return -ESYNOPGMACNOERR; } /** * Programs the DmaRxBaseAddress with the Rx descriptor base address. - * Rx Descriptor's base address is available in the gmacdev structure. This function progrms the + * Rx Descriptor's base address is available in the gmacdev structure. This function progrms the * Dma Rx Base address with the starting address of the descriptor ring or chain. * @param[in] pointer to synopGMACdevice. * \return returns void. */ void synopGMAC_init_rx_desc_base(synopGMACdevice *gmacdev) { - DEBUG_MES("gmacdev->RxDescDma = %08x\n", gmacdev->RxDescDma); - synopGMACWriteReg(gmacdev->DmaBase,DmaRxBaseAddr,(u32)gmacdev->RxDescDma ); - return; + DEBUG_MES("gmacdev->RxDescDma = %08x\n", gmacdev->RxDescDma); + synopGMACWriteReg(gmacdev->DmaBase,DmaRxBaseAddr,(u32)gmacdev->RxDescDma ); + return; } /** * Programs the DmaTxBaseAddress with the Tx descriptor base address. - * Tx Descriptor's base address is available in the gmacdev structure. This function progrms the + * Tx Descriptor's base address is available in the gmacdev structure. This function progrms the * Dma Tx Base address with the starting address of the descriptor ring or chain. * @param[in] pointer to synopGMACdevice. * \return returns void. */ void synopGMAC_init_tx_desc_base(synopGMACdevice *gmacdev) { - synopGMACWriteReg(gmacdev->DmaBase,DmaTxBaseAddr,(u32)gmacdev->TxDescDma); - return; + synopGMACWriteReg(gmacdev->DmaBase,DmaTxBaseAddr,(u32)gmacdev->TxDescDma); + return; } -/** +/** * Makes the Dma as owner for this descriptor. * This function sets the own bit of status field of the DMA descriptor, - * indicating the DMA is the owner for this descriptor. + * indicating the DMA is the owner for this descriptor. * @param[in] pointer to DmaDesc structure. * \return returns void. */ @@ -1417,7 +1417,7 @@ void synopGMAC_set_owner_dma(DmaDesc *desc) desc->status |= DescOwnByDma; } -/** +/** * set tx descriptor to indicate SOF. * This Descriptor contains the start of ethernet frame. * @param[in] pointer to DmaDesc structure. @@ -1433,7 +1433,7 @@ desc->length |= DescTxFirst; } -/** +/** * set tx descriptor to indicate EOF. * This descriptor contains the End of ethernet frame. * @param[in] pointer to DmaDesc structure. @@ -1449,51 +1449,51 @@ desc->length |= DescTxLast; } -/** +/** * checks whether this descriptor contains start of frame. - * This function is to check whether the descriptor's data buffer + * This function is to check whether the descriptor's data buffer * contains a fresh ethernet frame? * @param[in] pointer to DmaDesc structure. * \return returns true if SOF in current descriptor, else returns fail. */ bool synopGMAC_is_sof_in_rx_desc(DmaDesc *desc) { -return ((desc->status & DescRxFirst) == DescRxFirst); +return ((desc->status & DescRxFirst) == DescRxFirst); } -/** +/** * checks whether this descriptor contains end of frame. - * This function is to check whether the descriptor's data buffer + * This function is to check whether the descriptor's data buffer * contains end of ethernet frame? * @param[in] pointer to DmaDesc structure. * \return returns true if SOF in current descriptor, else returns fail. */ bool synopGMAC_is_eof_in_rx_desc(DmaDesc *desc) { -return ((desc->status & DescRxLast) == DescRxLast); +return ((desc->status & DescRxLast) == DescRxLast); } -/** +/** * checks whether destination address filter failed in the rx frame. * @param[in] pointer to DmaDesc structure. * \return returns true if Failed, false if not. */ bool synopGMAC_is_da_filter_failed(DmaDesc *desc) { -return ((desc->status & DescDAFilterFail) == DescDAFilterFail); +return ((desc->status & DescDAFilterFail) == DescDAFilterFail); } -/** +/** * checks whether source address filter failed in the rx frame. * @param[in] pointer to DmaDesc structure. * \return returns true if Failed, false if not. */ bool synopGMAC_is_sa_filter_failed(DmaDesc *desc) { -return ((desc->status & DescSAFilterFail) == DescSAFilterFail); +return ((desc->status & DescSAFilterFail) == DescSAFilterFail); } -/** +/** * Checks whether the descriptor is owned by DMA. * If descriptor is owned by DMA then the OWN bit is set to 1. This API is same for both ring and chain mode. * @param[in] pointer to DmaDesc structure. @@ -1512,7 +1512,7 @@ return ((desc->status & DescOwnByDma) == DescOwnByDma ); */ u32 synopGMAC_get_rx_desc_frame_length(u32 status) { - return ((status & DescFrameLengthMask) >> DescFrameLengthShift); + return ((status & DescFrameLengthMask) >> DescFrameLengthShift); } /** @@ -1524,7 +1524,7 @@ u32 synopGMAC_get_rx_desc_frame_length(u32 status) */ bool synopGMAC_is_desc_valid(u32 status) { - return ((status & DescError) == 0); + return ((status & DescError) == 0); } /** @@ -1536,8 +1536,8 @@ bool synopGMAC_is_desc_valid(u32 status) */ bool synopGMAC_is_desc_empty(DmaDesc *desc) { - //if both the buffer1 length and buffer2 length are zero desc is empty - return(((desc->length & DescSize1Mask) == 0) && ((desc->length & DescSize2Mask) == 0) ); + //if both the buffer1 length and buffer2 length are zero desc is empty + return(((desc->length & DescSize1Mask) == 0) && ((desc->length & DescSize2Mask) == 0) ); } @@ -1549,7 +1549,7 @@ bool synopGMAC_is_desc_empty(DmaDesc *desc) */ bool synopGMAC_is_rx_desc_valid(u32 status) { - return ((status & DescError) == 0) && ((status & DescRxFirst) == DescRxFirst) && ((status & DescRxLast) == DescRxLast); + return ((status & DescError) == 0) && ((status & DescRxFirst) == DescRxFirst) && ((status & DescRxLast) == DescRxLast); } /** @@ -1559,7 +1559,7 @@ bool synopGMAC_is_rx_desc_valid(u32 status) */ bool synopGMAC_is_tx_aborted(u32 status) { - return (((status & DescTxLateCollision) == DescTxLateCollision) | ((status & DescTxExcCollisions) == DescTxExcCollisions)); + return (((status & DescTxLateCollision) == DescTxLateCollision) | ((status & DescTxExcCollisions) == DescTxExcCollisions)); } @@ -1570,7 +1570,7 @@ bool synopGMAC_is_tx_aborted(u32 status) */ bool synopGMAC_is_tx_carrier_error(u32 status) { - return (((status & DescTxLostCarrier) == DescTxLostCarrier) | ((status & DescTxNoCarrier) == DescTxNoCarrier)); + return (((status & DescTxLostCarrier) == DescTxLostCarrier) | ((status & DescTxNoCarrier) == DescTxNoCarrier)); } @@ -1583,11 +1583,11 @@ bool synopGMAC_is_tx_carrier_error(u32 status) */ u32 synopGMAC_get_tx_collision_count(u32 status) { - return ((status & DescTxCollMask) >> DescTxCollShift); + return ((status & DescTxCollMask) >> DescTxCollShift); } u32 synopGMAC_is_exc_tx_collisions(u32 status) { - return ((status & DescTxExcCollisions) == DescTxExcCollisions); + return ((status & DescTxExcCollisions) == DescTxExcCollisions); } @@ -1600,7 +1600,7 @@ u32 synopGMAC_is_exc_tx_collisions(u32 status) bool synopGMAC_is_rx_frame_damaged(u32 status) { //bool synopGMAC_dma_rx_collisions(u32 status) - return (((status & DescRxDamaged) == DescRxDamaged) | ((status & DescRxCollision) == DescRxCollision)); + return (((status & DescRxDamaged) == DescRxDamaged) | ((status & DescRxCollision) == DescRxCollision)); } /** @@ -1612,7 +1612,7 @@ bool synopGMAC_is_rx_frame_damaged(u32 status) bool synopGMAC_is_rx_frame_collision(u32 status) { //bool synopGMAC_dma_rx_collisions(u32 status) - return ((status & DescRxCollision) == DescRxCollision); + return ((status & DescRxCollision) == DescRxCollision); } /** @@ -1624,7 +1624,7 @@ bool synopGMAC_is_rx_frame_collision(u32 status) bool synopGMAC_is_rx_crc(u32 status) { //u32 synopGMAC_dma_rx_crc(u32 status) - return ((status & DescRxCrc) == DescRxCrc); + return ((status & DescRxCrc) == DescRxCrc); } /** @@ -1636,7 +1636,7 @@ bool synopGMAC_is_rx_crc(u32 status) bool synopGMAC_is_frame_dribbling_errors(u32 status) { //u32 synopGMAC_dma_rx_frame_errors(u32 status) - return ((status & DescRxDribbling) == DescRxDribbling); + return ((status & DescRxDribbling) == DescRxDribbling); } /** @@ -1648,7 +1648,7 @@ bool synopGMAC_is_frame_dribbling_errors(u32 status) bool synopGMAC_is_rx_frame_length_errors(u32 status) { //u32 synopGMAC_dma_rx_length_errors(u32 status) - return((status & DescRxLengthError) == DescRxLengthError); + return((status & DescRxLengthError) == DescRxLengthError); } /** @@ -1677,9 +1677,9 @@ bool synopGMAC_is_last_tx_desc(synopGMACdevice * gmacdev,DmaDesc *desc) { //bool synopGMAC_is_last_desc(DmaDesc *desc) #ifdef ENH_DESC - return (((desc->status & TxDescEndOfRing) == TxDescEndOfRing) || ((u32)gmacdev->TxDesc == desc->data2)); + return (((desc->status & TxDescEndOfRing) == TxDescEndOfRing) || ((u32)gmacdev->TxDesc == desc->data2)); #else - return (((desc->length & TxDescEndOfRing) == TxDescEndOfRing) || ((u32)gmacdev->TxDesc == desc->data2)); + return (((desc->length & TxDescEndOfRing) == TxDescEndOfRing) || ((u32)gmacdev->TxDesc == desc->data2)); #endif } @@ -1691,7 +1691,7 @@ bool synopGMAC_is_last_tx_desc(synopGMACdevice * gmacdev,DmaDesc *desc) */ bool synopGMAC_is_rx_desc_chained(DmaDesc * desc) { - return((desc->length & RxDescChain) == RxDescChain); + return((desc->length & RxDescChain) == RxDescChain); } /** @@ -1703,9 +1703,9 @@ bool synopGMAC_is_rx_desc_chained(DmaDesc * desc) bool synopGMAC_is_tx_desc_chained(DmaDesc * desc) { #ifdef ENH_DESC - return((desc->status & TxDescChain) == TxDescChain); + return((desc->status & TxDescChain) == TxDescChain); #else - return((desc->length & TxDescChain) == TxDescChain); + return((desc->length & TxDescChain) == TxDescChain); #endif } @@ -1726,24 +1726,24 @@ bool synopGMAC_is_tx_desc_chained(DmaDesc * desc) void synopGMAC_get_desc_data(DmaDesc * desc, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2) { - if(Status != 0) - *Status = desc->status; + if(Status != 0) + *Status = desc->status; - if(Buffer1 != 0) - *Buffer1 = desc->buffer1; - if(Length1 != 0) - *Length1 = (desc->length & DescSize1Mask) >> DescSize1Shift; - if(Data1 != 0) - *Data1 = desc->data1; + if(Buffer1 != 0) + *Buffer1 = desc->buffer1; + if(Length1 != 0) + *Length1 = (desc->length & DescSize1Mask) >> DescSize1Shift; + if(Data1 != 0) + *Data1 = desc->data1; - if(Buffer2 != 0) - *Buffer2 = desc->buffer2; - if(Length2 != 0) - *Length2 = (desc->length & DescSize2Mask) >> DescSize2Shift; - if(Data1 != 0) - *Data2 = desc->data2; - - return; + if(Buffer2 != 0) + *Buffer2 = desc->buffer2; + if(Length2 != 0) + *Length2 = (desc->length & DescSize2Mask) >> DescSize2Shift; + if(Data1 != 0) + *Data2 = desc->data2; + + return; } @@ -1752,7 +1752,7 @@ void synopGMAC_get_desc_data(DmaDesc * desc, u32 * Status, u32 * Buffer1, u32 * * This function is defined two times. Once when the code is compiled for ENHANCED DESCRIPTOR SUPPORT and Once for Normal descriptor * Get the index and address of Tx desc. * This api is same for both ring mode and chain mode. - * This function tracks the tx descriptor the DMA just closed after the transmission of data from this descriptor is + * This function tracks the tx descriptor the DMA just closed after the transmission of data from this descriptor is * over. This returns the descriptor fields to the caller. * @param[in] pointer to synopGMACdevice. * @param[out] status field of the descriptor. @@ -1768,60 +1768,60 @@ void synopGMAC_get_desc_data(DmaDesc * desc, u32 * Status, u32 * Buffer1, u32 * s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2, u32 * Ext_Status, u32 * Time_Stamp_High, u32 * Time_Stamp_Low) { - u32 txover = gmacdev->TxBusy; - DmaDesc * txdesc = gmacdev->TxBusyDesc; - - if(synopGMAC_is_desc_owned_by_dma(txdesc)) - return -1; - if(synopGMAC_is_desc_empty(txdesc)) - return -1; + u32 txover = gmacdev->TxBusy; + DmaDesc * txdesc = gmacdev->TxBusyDesc; + + if(synopGMAC_is_desc_owned_by_dma(txdesc)) + return -1; + if(synopGMAC_is_desc_empty(txdesc)) + return -1; - (gmacdev->BusyTxDesc)--; //busy tx descriptor is reduced by one as it will be handed over to Processor now + (gmacdev->BusyTxDesc)--; //busy tx descriptor is reduced by one as it will be handed over to Processor now - if(Status != 0) - *Status = txdesc->status; + if(Status != 0) + *Status = txdesc->status; - if(Ext_Status != 0) - *Ext_Status = txdesc->extstatus; + if(Ext_Status != 0) + *Ext_Status = txdesc->extstatus; if(Time_Stamp_High != 0) - *Time_Stamp_High = txdesc->timestamphigh; + *Time_Stamp_High = txdesc->timestamphigh; if(Time_Stamp_Low != 0) - *Time_Stamp_High = txdesc->timestamplow; - - if(Buffer1 != 0) - *Buffer1 = txdesc->buffer1; - if(Length1 != 0) - *Length1 = (txdesc->length & DescSize1Mask) >> DescSize1Shift; - if(Data1 != 0) - *Data1 = txdesc->data1; - - if(Buffer2 != 0) - *Buffer2 = txdesc->buffer2; - if(Length2 != 0) - *Length2 = (txdesc->length & DescSize2Mask) >> DescSize2Shift; - if(Data1 != 0) - *Data2 = txdesc->data2; - - gmacdev->TxBusy = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txover + 1; - - if(synopGMAC_is_tx_desc_chained(txdesc)){ - gmacdev->TxBusyDesc = (DmaDesc *)txdesc->data2; - synopGMAC_tx_desc_init_chain(txdesc); - } - else{ - gmacdev->TxBusyDesc = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? gmacdev->TxDesc : (txdesc + 1); - synopGMAC_tx_desc_init_ring(txdesc, synopGMAC_is_last_tx_desc(gmacdev,txdesc)); - } - TR("%02d %08x %08x %08x %08x %08x %08x %08x\n",txover,(u32)txdesc,txdesc->status,txdesc->length,txdesc->buffer1,txdesc->buffer2,txdesc->data1,txdesc->data2); - - return txover; + *Time_Stamp_High = txdesc->timestamplow; + + if(Buffer1 != 0) + *Buffer1 = txdesc->buffer1; + if(Length1 != 0) + *Length1 = (txdesc->length & DescSize1Mask) >> DescSize1Shift; + if(Data1 != 0) + *Data1 = txdesc->data1; + + if(Buffer2 != 0) + *Buffer2 = txdesc->buffer2; + if(Length2 != 0) + *Length2 = (txdesc->length & DescSize2Mask) >> DescSize2Shift; + if(Data1 != 0) + *Data2 = txdesc->data2; + + gmacdev->TxBusy = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txover + 1; + + if(synopGMAC_is_tx_desc_chained(txdesc)){ + gmacdev->TxBusyDesc = (DmaDesc *)txdesc->data2; + synopGMAC_tx_desc_init_chain(txdesc); + } + else{ + gmacdev->TxBusyDesc = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? gmacdev->TxDesc : (txdesc + 1); + synopGMAC_tx_desc_init_ring(txdesc, synopGMAC_is_last_tx_desc(gmacdev,txdesc)); + } + TR("%02d %08x %08x %08x %08x %08x %08x %08x\n",txover,(u32)txdesc,txdesc->status,txdesc->length,txdesc->buffer1,txdesc->buffer2,txdesc->data1,txdesc->data2); + + return txover; } #else /** * Get the index and address of Tx desc. * This api is same for both ring mode and chain mode. - * This function tracks the tx descriptor the DMA just closed after the transmission of data from this descriptor is + * This function tracks the tx descriptor the DMA just closed after the transmission of data from this descriptor is * over. This returns the descriptor fields to the caller. * @param[in] pointer to synopGMACdevice. * @param[out] status field of the descriptor. @@ -1836,74 +1836,74 @@ s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1 */ s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2 ) { - u32 txover = gmacdev->TxBusy; - DmaDesc * txdesc = gmacdev->TxBusyDesc; - int i; - + u32 txover = gmacdev->TxBusy; + DmaDesc * txdesc = gmacdev->TxBusyDesc; + int i; + //sw: dbg - - //pci_sync_cache(0, (vm_offset_t)txdesc, 64, SYNC_R); - //pci_sync_cache(0, (vm_offset_t)txdesc, 64, SYNC_W); + + //pci_sync_cache(0, (vm_offset_t)txdesc, 64, SYNC_R); + //pci_sync_cache(0, (vm_offset_t)txdesc, 64, SYNC_W); #if SYNOP_TX_DEBUG - printf("Cache sync before get a used tx dma desc!\n"); - printf("\n==%02d %08x %08x %08x %08x %08x %08x %08x\n",txover,(u32)txdesc,txdesc->status,txdesc->length,txdesc->buffer1,txdesc->buffer2,txdesc->data1,txdesc->data2); -#endif - if(synopGMAC_is_desc_owned_by_dma(txdesc)) - { - return -1; - } -// gmacdev->TxBusy = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txover + 1; -// gmacdev->TxBusyDesc = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? gmacdev->TxDesc : (txdesc + 1); - if(synopGMAC_is_desc_empty(txdesc)) - { - return -1; - } - (gmacdev->BusyTxDesc)--; //busy tx descriptor is reduced by one as it will be handed over to Processor now - - if(Status != 0) - *Status = txdesc->status; - - if(Buffer1 != 0) - *Buffer1 = txdesc->buffer1; - if(Length1 != 0) - *Length1 = (txdesc->length & DescSize1Mask) >> DescSize1Shift; - if(Data1 != 0) - *Data1 = txdesc->data1; - - if(Buffer2 != 0) - *Buffer2 = txdesc->buffer2; - if(Length2 != 0) - *Length2 = (txdesc->length & DescSize2Mask) >> DescSize2Shift; - if(Data1 != 0) - *Data2 = txdesc->data2; - - gmacdev->TxBusy = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txover + 1; - - if(synopGMAC_is_tx_desc_chained(txdesc)){ - gmacdev->TxBusyDesc = (DmaDesc *)txdesc->data2; - synopGMAC_tx_desc_init_chain(txdesc); - } - else{ - gmacdev->TxBusyDesc = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? gmacdev->TxDesc : (txdesc + 1); - synopGMAC_tx_desc_init_ring(txdesc, synopGMAC_is_last_tx_desc(gmacdev,txdesc)); - } - //printf("%02d %08x %08x %08x %08x %08x %08x %08x\n",txover,(u32)txdesc,txdesc->status,txdesc->length,txdesc->buffer1,txdesc->buffer2,txdesc->data1,txdesc->data2); - //pci_sync_cache(0, (vm_offset_t)txdesc, 64, SYNC_W); + printf("Cache sync before get a used tx dma desc!\n"); + printf("\n==%02d %08x %08x %08x %08x %08x %08x %08x\n",txover,(u32)txdesc,txdesc->status,txdesc->length,txdesc->buffer1,txdesc->buffer2,txdesc->data1,txdesc->data2); +#endif + if(synopGMAC_is_desc_owned_by_dma(txdesc)) + { + return -1; + } +// gmacdev->TxBusy = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txover + 1; +// gmacdev->TxBusyDesc = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? gmacdev->TxDesc : (txdesc + 1); + if(synopGMAC_is_desc_empty(txdesc)) + { + return -1; + } + (gmacdev->BusyTxDesc)--; //busy tx descriptor is reduced by one as it will be handed over to Processor now + + if(Status != 0) + *Status = txdesc->status; + + if(Buffer1 != 0) + *Buffer1 = txdesc->buffer1; + if(Length1 != 0) + *Length1 = (txdesc->length & DescSize1Mask) >> DescSize1Shift; + if(Data1 != 0) + *Data1 = txdesc->data1; + + if(Buffer2 != 0) + *Buffer2 = txdesc->buffer2; + if(Length2 != 0) + *Length2 = (txdesc->length & DescSize2Mask) >> DescSize2Shift; + if(Data1 != 0) + *Data2 = txdesc->data2; + + gmacdev->TxBusy = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txover + 1; + + if(synopGMAC_is_tx_desc_chained(txdesc)){ + gmacdev->TxBusyDesc = (DmaDesc *)txdesc->data2; + synopGMAC_tx_desc_init_chain(txdesc); + } + else{ + gmacdev->TxBusyDesc = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? gmacdev->TxDesc : (txdesc + 1); + synopGMAC_tx_desc_init_ring(txdesc, synopGMAC_is_last_tx_desc(gmacdev,txdesc)); + } + //printf("%02d %08x %08x %08x %08x %08x %08x %08x\n",txover,(u32)txdesc,txdesc->status,txdesc->length,txdesc->buffer1,txdesc->buffer2,txdesc->data1,txdesc->data2); + //pci_sync_cache(0, (vm_offset_t)txdesc, 64, SYNC_W); #if SYNOP_TX_DEBUG - printf("Cache sync after re-init a tx dma desc!\n"); + printf("Cache sync after re-init a tx dma desc!\n"); #endif - return txover; + return txover; } #endif /** * Populate the tx desc structure with the buffer address. - * Once the driver has a packet ready to be transmitted, this function is called with the + * Once the driver has a packet ready to be transmitted, this function is called with the * valid dma-able buffer addresses and their lengths. This function populates the descriptor * and make the DMA the owner for the descriptor. This function also controls whetther Checksum - * offloading to be done in hardware or not. + * offloading to be done in hardware or not. * This api is same for both ring mode and chain mode. * @param[in] pointer to synopGMACdevice. * @param[in] Dma-able buffer1 pointer. @@ -1919,98 +1919,98 @@ s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1 u32 len; s32 synopGMAC_set_tx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u32 Data1, u32 Buffer2, u32 Length2, u32 Data2,u32 offload_needed,u32 * index, DmaDesc * Dpr) { - u32 txnext = gmacdev->TxNext; - DmaDesc * txdesc = gmacdev->TxNextDesc; - - *index = txnext; - Dpr = txdesc; - - if(!synopGMAC_is_desc_empty(txdesc)) - { - TR("set tx qptr: desc empty!\n"); - return -1; - } - - (gmacdev->BusyTxDesc)++; //busy tx descriptor is reduced by one as it will be handed over to Processor now - - if(synopGMAC_is_tx_desc_chained(txdesc)){ - txdesc->length |= ((Length1 <status |= (DescTxFirst | DescTxLast | DescTxIntEnable); //ENH_DESC - #else - txdesc->length |= (DescTxFirst | DescTxLast | DescTxIntEnable); //Its always assumed that complete data will fit in to one descriptor - #endif - - txdesc->buffer1 = Buffer1; - txdesc->data1 = Data1; - - if(offload_needed){ - /* - Make sure that the OS you are running supports the IP and TCP checkusm offloaidng, - before calling any of the functions given below. - */ - synopGMAC_tx_checksum_offload_ipv4hdr(gmacdev, txdesc); - synopGMAC_tx_checksum_offload_tcponly(gmacdev, txdesc); -// synopGMAC_tx_checksum_offload_tcp_pseudo(gmacdev, txdesc); - } - #ifdef ENH_DESC - txdesc->status |= DescOwnByDma;//ENH_DESC - #else - txdesc->status = DescOwnByDma; - #endif - - gmacdev->TxNext = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txnext + 1; - gmacdev->TxNextDesc = (DmaDesc *)txdesc->data2; - } - else{ -// printf("synopGMAC_set_tx_qptr:in ring mode\n"); - txdesc->length |= (((Length1 <status |= (DescTxFirst | DescTxLast | DescTxIntEnable); //ENH_DESC - #else - txdesc->length |= (DescTxFirst | DescTxLast | DescTxIntEnable); //Its always assumed that complete data will fit in to one descriptor - #endif - - txdesc->buffer1 = Buffer1; - txdesc->data1 = Data1; - - txdesc->buffer2 = Buffer2; - txdesc->data2 = Data2; - - if(offload_needed){ - /* - Make sure that the OS you are running supports the IP and TCP checkusm offloaidng, - before calling any of the functions given below. - */ + u32 txnext = gmacdev->TxNext; + DmaDesc * txdesc = gmacdev->TxNextDesc; + + *index = txnext; + Dpr = txdesc; + + if(!synopGMAC_is_desc_empty(txdesc)) + { + TR("set tx qptr: desc empty!\n"); + return -1; + } + + (gmacdev->BusyTxDesc)++; //busy tx descriptor is reduced by one as it will be handed over to Processor now + + if(synopGMAC_is_tx_desc_chained(txdesc)){ + txdesc->length |= ((Length1 <status |= (DescTxFirst | DescTxLast | DescTxIntEnable); //ENH_DESC + #else + txdesc->length |= (DescTxFirst | DescTxLast | DescTxIntEnable); //Its always assumed that complete data will fit in to one descriptor + #endif + + txdesc->buffer1 = Buffer1; + txdesc->data1 = Data1; + + if(offload_needed){ + /* + Make sure that the OS you are running supports the IP and TCP checkusm offloaidng, + before calling any of the functions given below. + */ + synopGMAC_tx_checksum_offload_ipv4hdr(gmacdev, txdesc); + synopGMAC_tx_checksum_offload_tcponly(gmacdev, txdesc); +// synopGMAC_tx_checksum_offload_tcp_pseudo(gmacdev, txdesc); + } + #ifdef ENH_DESC + txdesc->status |= DescOwnByDma;//ENH_DESC + #else + txdesc->status = DescOwnByDma; + #endif + + gmacdev->TxNext = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txnext + 1; + gmacdev->TxNextDesc = (DmaDesc *)txdesc->data2; + } + else{ +// printf("synopGMAC_set_tx_qptr:in ring mode\n"); + txdesc->length |= (((Length1 <status |= (DescTxFirst | DescTxLast | DescTxIntEnable); //ENH_DESC + #else + txdesc->length |= (DescTxFirst | DescTxLast | DescTxIntEnable); //Its always assumed that complete data will fit in to one descriptor + #endif + + txdesc->buffer1 = Buffer1; + txdesc->data1 = Data1; + + txdesc->buffer2 = Buffer2; + txdesc->data2 = Data2; + + if(offload_needed){ + /* + Make sure that the OS you are running supports the IP and TCP checkusm offloaidng, + before calling any of the functions given below. + */ //sw: i am not sure about the checksum.so i omit it in the outside - synopGMAC_tx_checksum_offload_ipv4hdr(gmacdev, txdesc); - synopGMAC_tx_checksum_offload_tcponly(gmacdev, txdesc); -// synopGMAC_tx_checksum_offload_tcp_pseudo(gmacdev, txdesc); - } - #ifdef ENH_DESC - txdesc->status |= DescOwnByDma;//ENH_DESC - #else -// printf("synopGMAC_set_tx_qptr:give the tx descroptor to dma\n"); - txdesc->status = DescOwnByDma; - #endif - - gmacdev->TxNext = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txnext + 1; - gmacdev->TxNextDesc = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? gmacdev->TxDesc : (txdesc + 1); - } + synopGMAC_tx_checksum_offload_ipv4hdr(gmacdev, txdesc); + synopGMAC_tx_checksum_offload_tcponly(gmacdev, txdesc); +// synopGMAC_tx_checksum_offload_tcp_pseudo(gmacdev, txdesc); + } + #ifdef ENH_DESC + txdesc->status |= DescOwnByDma;//ENH_DESC + #else +// printf("synopGMAC_set_tx_qptr:give the tx descroptor to dma\n"); + txdesc->status = DescOwnByDma; + #endif + + gmacdev->TxNext = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txnext + 1; + gmacdev->TxNextDesc = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? gmacdev->TxDesc : (txdesc + 1); + } #if SYNOP_TX_DEBUG - printf("%02d %08x %08x %08x %08x %08x %08x %08x\n",txnext,(u32)txdesc,txdesc->status,txdesc->length,txdesc->buffer1,txdesc->buffer2,txdesc->data1,txdesc->data2); + printf("%02d %08x %08x %08x %08x %08x %08x %08x\n",txnext,(u32)txdesc,txdesc->status,txdesc->length,txdesc->buffer1,txdesc->buffer2,txdesc->data1,txdesc->data2); #endif - //pci_sync_cache(0, (vm_offset_t)txdesc, 64, SYNC_W); + //pci_sync_cache(0, (vm_offset_t)txdesc, 64, SYNC_W); #if SYNOP_TX_DEBUG - printf("Cache sync to set a tx desc!\n"); + printf("Cache sync to set a tx desc!\n"); #endif - //pci_sync_cache(0, (vm_offset_t)(txdesc->data1), 32, SYNC_W); + //pci_sync_cache(0, (vm_offset_t)(txdesc->data1), 32, SYNC_W); #if SYNOP_TX_DEBUG - //printf("Cache sync for data in the buf of the tx desc!\n"); + //printf("Cache sync for data in the buf of the tx desc!\n"); #endif - return txnext; + return txnext; } #ifdef ENH_DESC_8W /** @@ -2027,62 +2027,62 @@ s32 synopGMAC_set_tx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u * @param[in] u32 data indicating whether the descriptor is in ring mode or chain mode. * \return returns present rx descriptor index on success. Negative value if error. */ -// dma_addr RX_BUF_SIZE skb +// dma_addr RX_BUF_SIZE skb s32 synopGMAC_set_rx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u32 Data1, u32 Buffer2, u32 Length2, u32 Data2) { - u32 rxnext = gmacdev->RxNext; - DmaDesc * rxdesc = gmacdev->RxNextDesc; + u32 rxnext = gmacdev->RxNext; + DmaDesc * rxdesc = gmacdev->RxNextDesc; - if(!synopGMAC_is_desc_empty(rxdesc)) - return -1; + if(!synopGMAC_is_desc_empty(rxdesc)) + return -1; - if(synopGMAC_is_rx_desc_chained(rxdesc)){ - rxdesc->length |= ((Length1 <length |= ((Length1 <buffer1 = Buffer1; - rxdesc->data1 = Data1; + rxdesc->buffer1 = Buffer1; + rxdesc->data1 = Data1; - rxdesc->extstatus = 0; - rxdesc->reserved1 = 0; - rxdesc->timestamplow = 0; - rxdesc->timestamphigh = 0; + rxdesc->extstatus = 0; + rxdesc->reserved1 = 0; + rxdesc->timestamplow = 0; + rxdesc->timestamphigh = 0; - if((rxnext % MODULO_INTERRUPT) !=0) - rxdesc->length |= RxDisIntCompl; - - rxdesc->status = DescOwnByDma; + if((rxnext % MODULO_INTERRUPT) !=0) + rxdesc->length |= RxDisIntCompl; - gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; - gmacdev->RxNextDesc = (DmaDesc *)rxdesc->data2; - } - else{ - rxdesc->length |= (((Length1 <status = DescOwnByDma; - rxdesc->buffer1 = Buffer1; - rxdesc->data1 = Data1; + gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; + gmacdev->RxNextDesc = (DmaDesc *)rxdesc->data2; + } + else{ + rxdesc->length |= (((Length1 <extstatus = 0; - rxdesc->reserved1 = 0; - rxdesc->timestamplow = 0; - rxdesc->timestamphigh = 0; + rxdesc->buffer1 = Buffer1; + rxdesc->data1 = Data1; - rxdesc->buffer2 = Buffer2; - rxdesc->data2 = Data2; - - if((rxnext % MODULO_INTERRUPT) !=0) - rxdesc->length |= RxDisIntCompl; + rxdesc->extstatus = 0; + rxdesc->reserved1 = 0; + rxdesc->timestamplow = 0; + rxdesc->timestamphigh = 0; - rxdesc->status = DescOwnByDma; - gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; - gmacdev->RxNextDesc = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? gmacdev->RxDesc : (rxdesc + 1); - } + rxdesc->buffer2 = Buffer2; + rxdesc->data2 = Data2; + + if((rxnext % MODULO_INTERRUPT) !=0) + rxdesc->length |= RxDisIntCompl; + + rxdesc->status = DescOwnByDma; + gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; + gmacdev->RxNextDesc = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? gmacdev->RxDesc : (rxdesc + 1); + } #if SYNOP_RX_DEBUG - TR("%02d %08x %08x %08x %08x %08x %08x %08x %08x %08x\n",rxnext,(u32)rxdesc,rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2,rxdesc->dummy1,rxdesc->dummy2); + TR("%02d %08x %08x %08x %08x %08x %08x %08x %08x %08x\n",rxnext,(u32)rxdesc,rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2,rxdesc->dummy1,rxdesc->dummy2); #endif - (gmacdev->BusyRxDesc)++; //One descriptor will be given to Hardware. So busy count incremented by one - //pci_sync_cache(0, (vm_offset_t)rxdesc,64, SYNC_W); - return rxnext; + (gmacdev->BusyRxDesc)++; //One descriptor will be given to Hardware. So busy count incremented by one + //pci_sync_cache(0, (vm_offset_t)rxdesc,64, SYNC_W); + return rxnext; } #else @@ -2102,100 +2102,100 @@ s32 synopGMAC_set_rx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u */ s32 synopGMAC_set_rx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u32 Data1, u32 Buffer2, u32 Length2, u32 Data2) { - u32 rxnext = gmacdev->RxNext; - DmaDesc * rxdesc = gmacdev->RxNextDesc; + u32 rxnext = gmacdev->RxNext; + DmaDesc * rxdesc = gmacdev->RxNextDesc; - if(!synopGMAC_is_desc_empty(rxdesc)) - return -1; + if(!synopGMAC_is_desc_empty(rxdesc)) + return -1; - if(synopGMAC_is_rx_desc_chained(rxdesc)){ - rxdesc->length |= ((Length1 <length |= ((Length1 <buffer1 = Buffer1; - rxdesc->data1 = Data1; + rxdesc->buffer1 = Buffer1; + rxdesc->data1 = Data1; - if((rxnext % MODULO_INTERRUPT) !=0) - rxdesc->length |= RxDisIntCompl; + if((rxnext % MODULO_INTERRUPT) !=0) + rxdesc->length |= RxDisIntCompl; - rxdesc->status = DescOwnByDma; + rxdesc->status = DescOwnByDma; - gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; - gmacdev->RxNextDesc = (DmaDesc *)rxdesc->data2; - } - else{ - rxdesc->length |= (((Length1 <RxNext = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; + gmacdev->RxNextDesc = (DmaDesc *)rxdesc->data2; + } + else{ + rxdesc->length |= (((Length1 <buffer1 = Buffer1; + rxdesc->data1 = Data1; - rxdesc->buffer1 = Buffer1; - rxdesc->data1 = Data1; + rxdesc->buffer2 = Buffer2; + rxdesc->data2 = Data2; - rxdesc->buffer2 = Buffer2; - rxdesc->data2 = Data2; - - if((rxnext % MODULO_INTERRUPT) !=0) - rxdesc->length |= RxDisIntCompl; + if((rxnext % MODULO_INTERRUPT) !=0) + rxdesc->length |= RxDisIntCompl; - rxdesc->status = DescOwnByDma; + rxdesc->status = DescOwnByDma; - gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; - gmacdev->RxNextDesc = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? gmacdev->RxDesc : (rxdesc + 1); - } + gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; + gmacdev->RxNextDesc = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? gmacdev->RxDesc : (rxdesc + 1); + } #if SYNOP_RX_DEBUG - TR("%02d %08x %08x %08x %08x %08x %08x %08x\n",rxnext,(u32)rxdesc,rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2); + TR("%02d %08x %08x %08x %08x %08x %08x %08x\n",rxnext,(u32)rxdesc,rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2); #endif - (gmacdev->BusyRxDesc)++; //One descriptor will be given to Hardware. So busy count incremented by one + (gmacdev->BusyRxDesc)++; //One descriptor will be given to Hardware. So busy count incremented by one - return rxnext; + return rxnext; } s32 synopGMAC_set_rx_qptr_init(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u32 Data1, u32 Buffer2, u32 Length2, u32 Data2) { - u32 rxnext = gmacdev->RxNext; - DmaDesc * rxdesc = gmacdev->RxNextDesc; + u32 rxnext = gmacdev->RxNext; + DmaDesc * rxdesc = gmacdev->RxNextDesc; -/* sw - if(synopGMAC_is_desc_owned_by_dma(rxdesc)) - return -1; +/* sw + if(synopGMAC_is_desc_owned_by_dma(rxdesc)) + return -1; */ - if(!synopGMAC_is_desc_empty(rxdesc)) - return -1; + if(!synopGMAC_is_desc_empty(rxdesc)) + return -1; + + if(synopGMAC_is_rx_desc_chained(rxdesc)){ + rxdesc->length |= ((Length1 <length |= ((Length1 <buffer1 = Buffer1; + rxdesc->data1 = Data1; - rxdesc->buffer1 = Buffer1; - rxdesc->data1 = Data1; + if((rxnext % MODULO_INTERRUPT) !=0) + rxdesc->length |= RxDisIntCompl; - if((rxnext % MODULO_INTERRUPT) !=0) - rxdesc->length |= RxDisIntCompl; + rxdesc->status = DescOwnByDma; + rxdesc->status = 0; - rxdesc->status = DescOwnByDma; - rxdesc->status = 0; + gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; + gmacdev->RxNextDesc = (DmaDesc *)rxdesc->data2; + } + else{ + rxdesc->length |= (((Length1 <RxNext = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; - gmacdev->RxNextDesc = (DmaDesc *)rxdesc->data2; - } - else{ - rxdesc->length |= (((Length1 <buffer1 = Buffer1; + rxdesc->data1 = Data1; - rxdesc->buffer1 = Buffer1; - rxdesc->data1 = Data1; + rxdesc->buffer2 = Buffer2; + rxdesc->data2 = Data2; - rxdesc->buffer2 = Buffer2; - rxdesc->data2 = Data2; - - if((rxnext % MODULO_INTERRUPT) !=0) - rxdesc->length |= RxDisIntCompl; + if((rxnext % MODULO_INTERRUPT) !=0) + rxdesc->length |= RxDisIntCompl; - rxdesc->status = DescOwnByDma; - rxdesc->status = 0; + rxdesc->status = DescOwnByDma; + rxdesc->status = 0; - gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; - gmacdev->RxNextDesc = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? gmacdev->RxDesc : (rxdesc + 1); - } - TR("%02d %08x %08x %08x %08x %08x %08x %08x\n",rxnext,(u32)rxdesc,rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2); - (gmacdev->BusyRxDesc)++; //One descriptor will be given to Hardware. So busy count incremented by one - return rxnext; + gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; + gmacdev->RxNextDesc = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? gmacdev->RxDesc : (rxdesc + 1); + } + TR("%02d %08x %08x %08x %08x %08x %08x %08x\n",rxnext,(u32)rxdesc,rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2); + (gmacdev->BusyRxDesc)++; //One descriptor will be given to Hardware. So busy count incremented by one + return rxnext; } #endif #ifdef ENH_DESC_8W @@ -2204,7 +2204,7 @@ s32 synopGMAC_set_rx_qptr_init(synopGMACdevice * gmacdev, u32 Buffer1, u32 Lengt * Get back the descriptor from DMA after data has been received. * When the DMA indicates that the data is received (interrupt is generated), this function should be * called to get the descriptor and hence the data buffers received. With successful return from this - * function caller gets the descriptor fields for processing. check the parameters to understand the + * function caller gets the descriptor fields for processing. check the parameters to understand the * fields returned.` * @param[in] pointer to synopGMACdevice. * @param[out] pointer to hold the status of DMA. @@ -2219,53 +2219,53 @@ s32 synopGMAC_set_rx_qptr_init(synopGMACdevice * gmacdev, u32 Buffer1, u32 Lengt s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2, u32 * Ext_Status, u32 * Time_Stamp_High, u32 * Time_Stamp_Low) { - u32 rxnext = gmacdev->RxBusy; // index of descriptor the DMA just completed. May be useful when data - //is spread over multiple buffers/descriptors - DmaDesc * rxdesc = gmacdev->RxBusyDesc; - if(synopGMAC_is_desc_owned_by_dma(rxdesc)) - return -1; - if(synopGMAC_is_desc_empty(rxdesc)) - return -1; - + u32 rxnext = gmacdev->RxBusy; // index of descriptor the DMA just completed. May be useful when data + //is spread over multiple buffers/descriptors + DmaDesc * rxdesc = gmacdev->RxBusyDesc; + if(synopGMAC_is_desc_owned_by_dma(rxdesc)) + return -1; + if(synopGMAC_is_desc_empty(rxdesc)) + return -1; + - if(Status != 0) - *Status = rxdesc->status;// send the status of this descriptor + if(Status != 0) + *Status = rxdesc->status;// send the status of this descriptor - if(Ext_Status != 0) - *Ext_Status = rxdesc->extstatus; + if(Ext_Status != 0) + *Ext_Status = rxdesc->extstatus; if(Time_Stamp_High != 0) - *Time_Stamp_High = rxdesc->timestamphigh; + *Time_Stamp_High = rxdesc->timestamphigh; if(Time_Stamp_Low != 0) - *Time_Stamp_Low = rxdesc->timestamplow; - - if(Length1 != 0) - *Length1 = (rxdesc->length & DescSize1Mask) >> DescSize1Shift; - if(Buffer1 != 0) - *Buffer1 = rxdesc->buffer1; - if(Data1 != 0) - *Data1 = rxdesc->data1; - - if(Length2 != 0) - *Length2 = (rxdesc->length & DescSize2Mask) >> DescSize2Shift; - if(Buffer2 != 0) - *Buffer2 = rxdesc->buffer2; - if(Data1 != 0) - *Data2 = rxdesc->data2; - - gmacdev->RxBusy = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; - - if(synopGMAC_is_rx_desc_chained(rxdesc)){ - gmacdev->RxBusyDesc = (DmaDesc *)rxdesc->data2; - synopGMAC_rx_desc_init_chain(rxdesc); - //synopGMAC_desc_init_chain(rxdesc, synopGMAC_is_last_rx_desc(gmacdev,rxdesc),0,0); - } - else{ - gmacdev->RxBusyDesc = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? gmacdev->RxDesc : (rxdesc + 1); - synopGMAC_rx_desc_init_ring(rxdesc, synopGMAC_is_last_rx_desc(gmacdev,rxdesc)); - } - TR("%02d %08x %08x %08x %08x %08x %08x %08x\n",rxnext,(u32)rxdesc,rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2); - (gmacdev->BusyRxDesc)--; //busy tx descriptor is reduced by one as it will be handed over to Processor now - return(rxnext); + *Time_Stamp_Low = rxdesc->timestamplow; + + if(Length1 != 0) + *Length1 = (rxdesc->length & DescSize1Mask) >> DescSize1Shift; + if(Buffer1 != 0) + *Buffer1 = rxdesc->buffer1; + if(Data1 != 0) + *Data1 = rxdesc->data1; + + if(Length2 != 0) + *Length2 = (rxdesc->length & DescSize2Mask) >> DescSize2Shift; + if(Buffer2 != 0) + *Buffer2 = rxdesc->buffer2; + if(Data1 != 0) + *Data2 = rxdesc->data2; + + gmacdev->RxBusy = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; + + if(synopGMAC_is_rx_desc_chained(rxdesc)){ + gmacdev->RxBusyDesc = (DmaDesc *)rxdesc->data2; + synopGMAC_rx_desc_init_chain(rxdesc); + //synopGMAC_desc_init_chain(rxdesc, synopGMAC_is_last_rx_desc(gmacdev,rxdesc),0,0); + } + else{ + gmacdev->RxBusyDesc = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? gmacdev->RxDesc : (rxdesc + 1); + synopGMAC_rx_desc_init_ring(rxdesc, synopGMAC_is_last_rx_desc(gmacdev,rxdesc)); + } + TR("%02d %08x %08x %08x %08x %08x %08x %08x\n",rxnext,(u32)rxdesc,rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2); + (gmacdev->BusyRxDesc)--; //busy tx descriptor is reduced by one as it will be handed over to Processor now + return(rxnext); } #else @@ -2274,7 +2274,7 @@ s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1 * Get back the descriptor from DMA after data has been received. * When the DMA indicates that the data is received (interrupt is generated), this function should be * called to get the descriptor and hence the data buffers received. With successful return from this - * function caller gets the descriptor fields for processing. check the parameters to understand the + * function caller gets the descriptor fields for processing. check the parameters to understand the * fields returned.` * @param[in] pointer to synopGMACdevice. * @param[out] pointer to hold the status of DMA. @@ -2288,60 +2288,60 @@ s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1 */ s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2) { - u32 rxnext = gmacdev->RxBusy; // index of descriptor the DMA just completed. May be useful when data - //is spread over multiple buffers/descriptors - DmaDesc * rxdesc = gmacdev->RxBusyDesc; - - u32 len; - if(synopGMAC_is_desc_owned_by_dma(rxdesc)) - { - DEBUG_MES("synopGMAC_get_rx_qptr:DMA descriptor is owned by GMAC!\n"); - return -1; - } - - if(synopGMAC_is_desc_empty(rxdesc)) - { - DEBUG_MES("synopGMAC_get_rx_qptr:rx desc is empty!\n"); - return -1; - } - - if(Status != 0) - *Status = rxdesc->status;// send the status of this descriptor - - if(Length1 != 0) - *Length1 = (rxdesc->length & DescSize1Mask) >> DescSize1Shift; - if(Buffer1 != 0) - *Buffer1 = rxdesc->buffer1; - if(Data1 != 0) - *Data1 = rxdesc->data1; - if(Length2 != 0) - *Length2 = (rxdesc->length & DescSize2Mask) >> DescSize2Shift; - if(Buffer2 != 0) - *Buffer2 = rxdesc->buffer2; - if(Data1 != 0) - *Data2 = rxdesc->data2; - - len = synopGMAC_get_rx_desc_frame_length(*Status); - DEBUG_MES("Cache sync for data buffer in rx dma desc: length = 0x%x\n",len); - gmacdev->RxBusy = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; - if(synopGMAC_is_rx_desc_chained(rxdesc)){ - gmacdev->RxBusyDesc = (DmaDesc *)rxdesc->data2; - synopGMAC_rx_desc_init_chain(rxdesc); - } - else{ - gmacdev->RxBusyDesc = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? gmacdev->RxDesc : (rxdesc + 1); -//sw: raw data + u32 rxnext = gmacdev->RxBusy; // index of descriptor the DMA just completed. May be useful when data + //is spread over multiple buffers/descriptors + DmaDesc * rxdesc = gmacdev->RxBusyDesc; + + u32 len; + if(synopGMAC_is_desc_owned_by_dma(rxdesc)) + { + DEBUG_MES("synopGMAC_get_rx_qptr:DMA descriptor is owned by GMAC!\n"); + return -1; + } + + if(synopGMAC_is_desc_empty(rxdesc)) + { + DEBUG_MES("synopGMAC_get_rx_qptr:rx desc is empty!\n"); + return -1; + } + + if(Status != 0) + *Status = rxdesc->status;// send the status of this descriptor + + if(Length1 != 0) + *Length1 = (rxdesc->length & DescSize1Mask) >> DescSize1Shift; + if(Buffer1 != 0) + *Buffer1 = rxdesc->buffer1; + if(Data1 != 0) + *Data1 = rxdesc->data1; + if(Length2 != 0) + *Length2 = (rxdesc->length & DescSize2Mask) >> DescSize2Shift; + if(Buffer2 != 0) + *Buffer2 = rxdesc->buffer2; + if(Data1 != 0) + *Data2 = rxdesc->data2; + + len = synopGMAC_get_rx_desc_frame_length(*Status); + DEBUG_MES("Cache sync for data buffer in rx dma desc: length = 0x%x\n",len); + gmacdev->RxBusy = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; + if(synopGMAC_is_rx_desc_chained(rxdesc)){ + gmacdev->RxBusyDesc = (DmaDesc *)rxdesc->data2; + synopGMAC_rx_desc_init_chain(rxdesc); + } + else{ + gmacdev->RxBusyDesc = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? gmacdev->RxDesc : (rxdesc + 1); +//sw: raw data #if SYNOP_RX_DEBUG - DEBUG_MES("%02d %08x %08x %08x %08x %08x %08x %08x\n",rxnext,(u32)rxdesc,rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2); + DEBUG_MES("%02d %08x %08x %08x %08x %08x %08x %08x\n",rxnext,(u32)rxdesc,rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2); #endif - synopGMAC_rx_desc_init_ring(rxdesc, synopGMAC_is_last_rx_desc(gmacdev,rxdesc)); - } + synopGMAC_rx_desc_init_ring(rxdesc, synopGMAC_is_last_rx_desc(gmacdev,rxdesc)); + } #if SYNOP_RX_DEBUG - DEBUG_MES("%02d %08x %08x %08x %08x %08x %08x %08x\n",rxnext,(u32)rxdesc,rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2); + DEBUG_MES("%02d %08x %08x %08x %08x %08x %08x %08x\n",rxnext,(u32)rxdesc,rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2); #endif - (gmacdev->BusyRxDesc)--; //This returns one descriptor to processor. So busy count will be decremented by one - return(rxnext); + (gmacdev->BusyRxDesc)--; //This returns one descriptor to processor. So busy count will be decremented by one + return(rxnext); } @@ -2355,13 +2355,13 @@ s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1 */ void synopGMAC_clear_interrupt(synopGMACdevice *gmacdev) { - u32 data; - data = synopGMACReadReg(gmacdev->DmaBase, DmaStatus); - TR("DMA status reg = 0x%x before cleared!\n",data); - synopGMACWriteReg(gmacdev->DmaBase, DmaStatus ,data); + u32 data; + data = synopGMACReadReg(gmacdev->DmaBase, DmaStatus); + TR("DMA status reg = 0x%x before cleared!\n",data); + synopGMACWriteReg(gmacdev->DmaBase, DmaStatus ,data); // plat_delay(DEFAULT_LOOP_VARIABLE); -// data = synopGMACReadReg(gmacdev->DmaBase, DmaStatus); - TR("DMA status reg = 0x%x after cleared!\n",data); +// data = synopGMACReadReg(gmacdev->DmaBase, DmaStatus); + TR("DMA status reg = 0x%x after cleared!\n",data); } /** @@ -2371,22 +2371,22 @@ void synopGMAC_clear_interrupt(synopGMACdevice *gmacdev) */ u32 synopGMAC_get_interrupt_type(synopGMACdevice *gmacdev) { - u32 data; - u32 interrupts = 0; - data = synopGMACReadReg(gmacdev->DmaBase, DmaStatus); - - //data = data & ~0x84; //sw: some bits shoud not be cleaned - synopGMACWriteReg(gmacdev->DmaBase, DmaStatus ,data); //manju: I think this is the appropriate location to clear the interrupts + u32 data; + u32 interrupts = 0; + data = synopGMACReadReg(gmacdev->DmaBase, DmaStatus); + + //data = data & ~0x84; //sw: some bits shoud not be cleaned + synopGMACWriteReg(gmacdev->DmaBase, DmaStatus ,data); //manju: I think this is the appropriate location to clear the interrupts plat_delay(DEFAULT_LOOP_VARIABLE); - if(data & DmaIntErrorMask) interrupts |= synopGMACDmaError; - if(data & DmaIntRxNormMask) interrupts |= synopGMACDmaRxNormal; - if(data & DmaIntRxAbnMask) interrupts |= synopGMACDmaRxAbnormal; - if(data & DmaIntRxStoppedMask) interrupts |= synopGMACDmaRxStopped; - if(data & DmaIntTxNormMask) interrupts |= synopGMACDmaTxNormal; - if(data & DmaIntTxAbnMask) interrupts |= synopGMACDmaTxAbnormal; - if(data & DmaIntTxStoppedMask) interrupts |= synopGMACDmaTxStopped; + if(data & DmaIntErrorMask) interrupts |= synopGMACDmaError; + if(data & DmaIntRxNormMask) interrupts |= synopGMACDmaRxNormal; + if(data & DmaIntRxAbnMask) interrupts |= synopGMACDmaRxAbnormal; + if(data & DmaIntRxStoppedMask) interrupts |= synopGMACDmaRxStopped; + if(data & DmaIntTxNormMask) interrupts |= synopGMACDmaTxNormal; + if(data & DmaIntTxAbnMask) interrupts |= synopGMACDmaTxAbnormal; + if(data & DmaIntTxStoppedMask) interrupts |= synopGMACDmaTxStopped; - return interrupts; + return interrupts; } /** @@ -2397,7 +2397,7 @@ u32 synopGMAC_get_interrupt_type(synopGMACdevice *gmacdev) #if UNUSED u32 synopGMAC_get_interrupt_mask(synopGMACdevice *gmacdev) { - return(synopGMACReadReg(gmacdev->DmaBase, DmaInterrupt)); + return(synopGMACReadReg(gmacdev->DmaBase, DmaInterrupt)); } #endif @@ -2411,8 +2411,8 @@ u32 synopGMAC_get_interrupt_mask(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_enable_interrupt(synopGMACdevice *gmacdev, u32 interrupts) { - synopGMACWriteReg(gmacdev->DmaBase, DmaInterrupt, interrupts); - return; + synopGMACWriteReg(gmacdev->DmaBase, DmaInterrupt, interrupts); + return; } #endif @@ -2427,10 +2427,10 @@ void synopGMAC_enable_interrupt(synopGMACdevice *gmacdev, u32 interrupts) */ void synopGMAC_disable_interrupt_all(synopGMACdevice *gmacdev) { -// rt_kprintf("dmabase = 0x%x\n",gmacdev->DmaBase); - synopGMACWriteReg(gmacdev->DmaBase, DmaInterrupt, DmaIntDisable); -// synopGMACReadReg(gmacdev->DmaBase, DmaInterrupt); - return; +// rt_kprintf("dmabase = 0x%x\n",gmacdev->DmaBase); + synopGMACWriteReg(gmacdev->DmaBase, DmaInterrupt, DmaIntDisable); +// synopGMACReadReg(gmacdev->DmaBase, DmaInterrupt); + return; } /** @@ -2443,8 +2443,8 @@ void synopGMAC_disable_interrupt_all(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_disable_interrupt(synopGMACdevice *gmacdev, u32 interrupts) { - synopGMACClearBits(gmacdev->DmaBase, DmaInterrupt, interrupts); - return; + synopGMACClearBits(gmacdev->DmaBase, DmaInterrupt, interrupts); + return; } #endif /** @@ -2454,13 +2454,13 @@ void synopGMAC_disable_interrupt(synopGMACdevice *gmacdev, u32 interrupts) */ void synopGMAC_enable_dma_rx(synopGMACdevice * gmacdev) { -// synopGMACSetBits(gmacdev->DmaBase, DmaControl, DmaRxStart); - u32 data; - data = synopGMACReadReg(gmacdev->DmaBase, DmaControl); - data |= DmaRxStart; - TR0(" ===33334\n"); - synopGMACWriteReg(gmacdev->DmaBase, DmaControl ,data); - TR0(" ===33344\n"); +// synopGMACSetBits(gmacdev->DmaBase, DmaControl, DmaRxStart); + u32 data; + data = synopGMACReadReg(gmacdev->DmaBase, DmaControl); + data |= DmaRxStart; + TR0(" ===33334\n"); + synopGMACWriteReg(gmacdev->DmaBase, DmaControl ,data); + TR0(" ===33344\n"); } /** @@ -2470,11 +2470,11 @@ void synopGMAC_enable_dma_rx(synopGMACdevice * gmacdev) */ void synopGMAC_enable_dma_tx(synopGMACdevice * gmacdev) { -// synopGMACSetBits(gmacdev->DmaBase, DmaControl, DmaTxStart); - u32 data; - data = synopGMACReadReg(gmacdev->DmaBase, DmaControl); - data |= DmaTxStart; - synopGMACWriteReg(gmacdev->DmaBase, DmaControl ,data); +// synopGMACSetBits(gmacdev->DmaBase, DmaControl, DmaTxStart); + u32 data; + data = synopGMACReadReg(gmacdev->DmaBase, DmaControl); + data |= DmaTxStart; + synopGMACWriteReg(gmacdev->DmaBase, DmaControl ,data); } @@ -2487,7 +2487,7 @@ void synopGMAC_enable_dma_tx(synopGMACdevice * gmacdev) */ void synopGMAC_resume_dma_tx(synopGMACdevice * gmacdev) { - synopGMACWriteReg(gmacdev->DmaBase, DmaTxPollDemand, 1); + synopGMACWriteReg(gmacdev->DmaBase, DmaTxPollDemand, 1); } /** @@ -2499,7 +2499,7 @@ void synopGMAC_resume_dma_tx(synopGMACdevice * gmacdev) */ void synopGMAC_resume_dma_rx(synopGMACdevice * gmacdev) { - synopGMACWriteReg(gmacdev->DmaBase, DmaRxPollDemand, 0); + synopGMACWriteReg(gmacdev->DmaBase, DmaRxPollDemand, 0); } /** @@ -2510,10 +2510,10 @@ void synopGMAC_resume_dma_rx(synopGMACdevice * gmacdev) */ void synopGMAC_take_desc_ownership(DmaDesc * desc) { - if(desc){ - desc->status &= ~DescOwnByDma; //Clear the DMA own bit -// desc->status |= DescError; // Set the error to indicate this descriptor is bad - } + if(desc){ + desc->status &= ~DescOwnByDma; //Clear the DMA own bit +// desc->status |= DescError; // Set the error to indicate this descriptor is bad + } } /** @@ -2527,19 +2527,19 @@ void synopGMAC_take_desc_ownership(DmaDesc * desc) */ void synopGMAC_take_desc_ownership_rx(synopGMACdevice * gmacdev) { - s32 i; - DmaDesc *desc; - desc = gmacdev->RxDesc; - for(i = 0; i < gmacdev->RxDescCount; i++){ - if(synopGMAC_is_rx_desc_chained(desc)){ //This descriptor is in chain mode - - synopGMAC_take_desc_ownership(desc); - desc = (DmaDesc *)desc->data2; - } - else{ - synopGMAC_take_desc_ownership(desc + i); - } - } + s32 i; + DmaDesc *desc; + desc = gmacdev->RxDesc; + for(i = 0; i < gmacdev->RxDescCount; i++){ + if(synopGMAC_is_rx_desc_chained(desc)){ //This descriptor is in chain mode + + synopGMAC_take_desc_ownership(desc); + desc = (DmaDesc *)desc->data2; + } + else{ + synopGMAC_take_desc_ownership(desc + i); + } + } } /** @@ -2553,19 +2553,19 @@ void synopGMAC_take_desc_ownership_rx(synopGMACdevice * gmacdev) */ void synopGMAC_take_desc_ownership_tx(synopGMACdevice * gmacdev) { - s32 i; - DmaDesc *desc; - desc = gmacdev->TxDesc; - for(i = 0; i < gmacdev->TxDescCount; i++){ - if(synopGMAC_is_tx_desc_chained(desc)){ //This descriptor is in chain mode - synopGMAC_take_desc_ownership(desc); - desc = (DmaDesc *)desc->data2; - } - else{ - synopGMAC_take_desc_ownership(desc + i); - } - } - + s32 i; + DmaDesc *desc; + desc = gmacdev->TxDesc; + for(i = 0; i < gmacdev->TxDescCount; i++){ + if(synopGMAC_is_tx_desc_chained(desc)){ //This descriptor is in chain mode + synopGMAC_take_desc_ownership(desc); + desc = (DmaDesc *)desc->data2; + } + else{ + synopGMAC_take_desc_ownership(desc + i); + } + } + } /** @@ -2575,12 +2575,12 @@ void synopGMAC_take_desc_ownership_tx(synopGMACdevice * gmacdev) */ void synopGMAC_disable_dma_tx(synopGMACdevice * gmacdev) -{ -// synopGMACClearBits(gmacdev->DmaBase, DmaControl, DmaTxStart); - u32 data; - data = synopGMACReadReg(gmacdev->DmaBase, DmaControl); - data &= (~DmaTxStart); - synopGMACWriteReg(gmacdev->DmaBase, DmaControl ,data); +{ +// synopGMACClearBits(gmacdev->DmaBase, DmaControl, DmaTxStart); + u32 data; + data = synopGMACReadReg(gmacdev->DmaBase, DmaControl); + data &= (~DmaTxStart); + synopGMACWriteReg(gmacdev->DmaBase, DmaControl ,data); } /** * Disable the DMA for Reception. @@ -2588,16 +2588,16 @@ void synopGMAC_disable_dma_tx(synopGMACdevice * gmacdev) * \return returns void. */ void synopGMAC_disable_dma_rx(synopGMACdevice * gmacdev) -{ -// synopGMACClearBits(gmacdev->DmaBase, DmaControl, DmaRxStart); - u32 data; - data = synopGMACReadReg(gmacdev->DmaBase, DmaControl); - data &= (~DmaRxStart); - synopGMACWriteReg(gmacdev->DmaBase, DmaControl ,data); +{ +// synopGMACClearBits(gmacdev->DmaBase, DmaControl, DmaRxStart); + u32 data; + data = synopGMACReadReg(gmacdev->DmaBase, DmaControl); + data &= (~DmaRxStart); + synopGMACWriteReg(gmacdev->DmaBase, DmaControl ,data); } - + /*******************PMT APIs***************************************/ @@ -2613,7 +2613,7 @@ void synopGMAC_disable_dma_rx(synopGMACdevice * gmacdev) #if UNUSED void synopGMAC_pmt_int_enable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask); + synopGMACClearBits(gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask); return; } #endif @@ -2626,7 +2626,7 @@ void synopGMAC_pmt_int_enable(synopGMACdevice *gmacdev) */ void synopGMAC_pmt_int_disable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask); + synopGMACSetBits(gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask); return; } /** @@ -2638,8 +2638,8 @@ void synopGMAC_pmt_int_disable(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_power_down_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtPowerDown); - return; + synopGMACSetBits(gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtPowerDown); + return; } #endif /** @@ -2652,8 +2652,8 @@ void synopGMAC_power_down_enable(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_power_down_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtPowerDown); - return; + synopGMACClearBits(gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtPowerDown); + return; } #endif /** @@ -2664,7 +2664,7 @@ void synopGMAC_power_down_disable(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_enable_pmt_interrupt(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask); + synopGMACClearBits(gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask); } #endif /** @@ -2675,7 +2675,7 @@ void synopGMAC_enable_pmt_interrupt(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_disable_pmt_interrupt(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask); + synopGMACSetBits(gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask); } #endif /** @@ -2686,13 +2686,13 @@ void synopGMAC_disable_pmt_interrupt(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_magic_packet_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtMagicPktEnable); - return; + synopGMACSetBits(gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtMagicPktEnable); + return; } #endif /** - * Enables GMAC to look for wake up frame. + * Enables GMAC to look for wake up frame. * Wake up frame is defined by the user. * @param[in] pointer to synopGMACdevice. * \return returns void. @@ -2700,8 +2700,8 @@ void synopGMAC_magic_packet_enable(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_wakeup_frame_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtWakeupFrameEnable); - return; + synopGMACSetBits(gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtWakeupFrameEnable); + return; } #endif @@ -2713,8 +2713,8 @@ void synopGMAC_wakeup_frame_enable(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_pmt_unicast_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtGlobalUnicast); - return; + synopGMACSetBits(gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtGlobalUnicast); + return; } #endif /** @@ -2724,9 +2724,9 @@ void synopGMAC_pmt_unicast_enable(synopGMACdevice *gmacdev) */ bool synopGMAC_is_magic_packet_received(synopGMACdevice *gmacdev) { - u32 data; - data = synopGMACReadReg(gmacdev->MacBase,GmacPmtCtrlStatus); - return((data & GmacPmtMagicPktReceived) == GmacPmtMagicPktReceived); + u32 data; + data = synopGMACReadReg(gmacdev->MacBase,GmacPmtCtrlStatus); + return((data & GmacPmtMagicPktReceived) == GmacPmtMagicPktReceived); } /** * Checks whether the packet received is a wakeup frame?. @@ -2735,9 +2735,9 @@ bool synopGMAC_is_magic_packet_received(synopGMACdevice *gmacdev) */ bool synopGMAC_is_wakeup_frame_received(synopGMACdevice *gmacdev) { - u32 data; - data = synopGMACReadReg(gmacdev->MacBase,GmacPmtCtrlStatus); - return((data & GmacPmtWakeupFrameReceived) == GmacPmtWakeupFrameReceived); + u32 data; + data = synopGMACReadReg(gmacdev->MacBase,GmacPmtCtrlStatus); + return((data & GmacPmtWakeupFrameReceived) == GmacPmtWakeupFrameReceived); } /** @@ -2752,12 +2752,12 @@ bool synopGMAC_is_wakeup_frame_received(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_write_wakeup_frame_register(synopGMACdevice *gmacdev, u32 * filter_contents) { - s32 i; - synopGMACSetBits(gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtFrmFilterPtrReset); - plat_delay(10); - for(i =0; iMacBase, GmacWakeupAddr, *(filter_contents + i)); - return; + s32 i; + synopGMACSetBits(gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtFrmFilterPtrReset); + plat_delay(10); + for(i =0; iMacBase, GmacWakeupAddr, *(filter_contents + i)); + return; } #endif @@ -2774,8 +2774,8 @@ void synopGMAC_write_wakeup_frame_register(synopGMACdevice *gmacdev, u32 * filte #if UNUSED void synopGMAC_mmc_counters_stop(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterFreeze); - return; + synopGMACSetBits(gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterFreeze); + return; } #endif /** @@ -2786,8 +2786,8 @@ void synopGMAC_mmc_counters_stop(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_mmc_counters_resume(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterFreeze); - return; + synopGMACClearBits(gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterFreeze); + return; } #endif /** @@ -2799,8 +2799,8 @@ void synopGMAC_mmc_counters_resume(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_mmc_counters_set_selfclear(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterResetOnRead); - return; + synopGMACSetBits(gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterResetOnRead); + return; } #endif /** @@ -2812,8 +2812,8 @@ void synopGMAC_mmc_counters_set_selfclear(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_mmc_counters_reset_selfclear(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterResetOnRead); - return; + synopGMACClearBits(gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterResetOnRead); + return; } #endif /** @@ -2825,8 +2825,8 @@ void synopGMAC_mmc_counters_reset_selfclear(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_mmc_counters_disable_rollover(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterStopRollover); - return; + synopGMACSetBits(gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterStopRollover); + return; } /** * Configures the MMC to rollover. @@ -2836,8 +2836,8 @@ void synopGMAC_mmc_counters_disable_rollover(synopGMACdevice *gmacdev) */ void synopGMAC_mmc_counters_enable_rollover(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterStopRollover); - return; + synopGMACClearBits(gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterStopRollover); + return; } /** @@ -2848,7 +2848,7 @@ void synopGMAC_mmc_counters_enable_rollover(synopGMACdevice *gmacdev) */ u32 synopGMAC_read_mmc_counter(synopGMACdevice *gmacdev, u32 counter) { - return( synopGMACReadReg(gmacdev->MacBase,counter)); + return( synopGMACReadReg(gmacdev->MacBase,counter)); } #endif /** @@ -2858,7 +2858,7 @@ u32 synopGMAC_read_mmc_counter(synopGMACdevice *gmacdev, u32 counter) */ u32 synopGMAC_read_mmc_rx_int_status(synopGMACdevice *gmacdev) { - return( synopGMACReadReg(gmacdev->MacBase,GmacMmcIntrRx)); + return( synopGMACReadReg(gmacdev->MacBase,GmacMmcIntrRx)); } /** * Read the MMC Tx interrupt status. @@ -2867,7 +2867,7 @@ u32 synopGMAC_read_mmc_rx_int_status(synopGMACdevice *gmacdev) */ u32 synopGMAC_read_mmc_tx_int_status(synopGMACdevice *gmacdev) { - return( synopGMACReadReg(gmacdev->MacBase,GmacMmcIntrTx)); + return( synopGMACReadReg(gmacdev->MacBase,GmacMmcIntrTx)); } /** * Disable the MMC Tx interrupt. @@ -2878,8 +2878,8 @@ u32 synopGMAC_read_mmc_tx_int_status(synopGMACdevice *gmacdev) */ void synopGMAC_disable_mmc_tx_interrupt(synopGMACdevice *gmacdev, u32 mask) { - synopGMACSetBits(gmacdev->MacBase,GmacMmcIntrMaskTx,mask); - return; + synopGMACSetBits(gmacdev->MacBase,GmacMmcIntrMaskTx,mask); + return; } /** * Enable the MMC Tx interrupt. @@ -2891,7 +2891,7 @@ void synopGMAC_disable_mmc_tx_interrupt(synopGMACdevice *gmacdev, u32 mask) #if UNUSED void synopGMAC_enable_mmc_tx_interrupt(synopGMACdevice *gmacdev, u32 mask) { - synopGMACClearBits(gmacdev->MacBase,GmacMmcIntrMaskTx,mask); + synopGMACClearBits(gmacdev->MacBase,GmacMmcIntrMaskTx,mask); } #endif /** @@ -2903,8 +2903,8 @@ void synopGMAC_enable_mmc_tx_interrupt(synopGMACdevice *gmacdev, u32 mask) */ void synopGMAC_disable_mmc_rx_interrupt(synopGMACdevice *gmacdev, u32 mask) { - synopGMACSetBits(gmacdev->MacBase,GmacMmcIntrMaskRx,mask); - return; + synopGMACSetBits(gmacdev->MacBase,GmacMmcIntrMaskRx,mask); + return; } /** * Enable the MMC Rx interrupt. @@ -2916,8 +2916,8 @@ void synopGMAC_disable_mmc_rx_interrupt(synopGMACdevice *gmacdev, u32 mask) #if UNUSED void synopGMAC_enable_mmc_rx_interrupt(synopGMACdevice *gmacdev, u32 mask) { - synopGMACClearBits(gmacdev->MacBase,GmacMmcIntrMaskRx,mask); - return; + synopGMACClearBits(gmacdev->MacBase,GmacMmcIntrMaskRx,mask); + return; } #endif /** @@ -2929,8 +2929,8 @@ void synopGMAC_enable_mmc_rx_interrupt(synopGMACdevice *gmacdev, u32 mask) */ void synopGMAC_disable_mmc_ipc_rx_interrupt(synopGMACdevice *gmacdev, u32 mask) { - synopGMACSetBits(gmacdev->MacBase,GmacMmcRxIpcIntrMask,mask); - return; + synopGMACSetBits(gmacdev->MacBase,GmacMmcRxIpcIntrMask,mask); + return; } /** * Enable the MMC ipc rx checksum offload interrupt. @@ -2942,8 +2942,8 @@ void synopGMAC_disable_mmc_ipc_rx_interrupt(synopGMACdevice *gmacdev, u32 mask) #if UNUSED void synopGMAC_enable_mmc_ipc_rx_interrupt(synopGMACdevice *gmacdev, u32 mask) { - synopGMACClearBits(gmacdev->MacBase,GmacMmcRxIpcIntrMask,mask); - return; + synopGMACClearBits(gmacdev->MacBase,GmacMmcRxIpcIntrMask,mask); + return; } #endif /*******************MMC APIs***************************************/ @@ -2960,8 +2960,8 @@ void synopGMAC_enable_mmc_ipc_rx_interrupt(synopGMACdevice *gmacdev, u32 mask) #if UNUSED void synopGMAC_enable_rx_chksum_offload(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacConfig,GmacRxIpcOffload); - return; + synopGMACSetBits(gmacdev->MacBase,GmacConfig,GmacRxIpcOffload); + return; } /** * Disable the ip checksum offloading in receive path. @@ -2971,19 +2971,19 @@ void synopGMAC_enable_rx_chksum_offload(synopGMACdevice *gmacdev) */ void synopGMAC_disable_rx_Ipchecksum_offload(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacConfig,GmacRxIpcOffload); + synopGMACClearBits(gmacdev->MacBase,GmacConfig,GmacRxIpcOffload); } /** * Instruct the DMA to drop the packets fails tcp ip checksum. - * This is to instruct the receive DMA engine to drop the recevied packet if they + * This is to instruct the receive DMA engine to drop the recevied packet if they * fails the tcp/ip checksum in hardware. Valid only when full checksum offloading is enabled(type-2). * @param[in] pointer to synopGMACdevice. * \return returns void. */ void synopGMAC_rx_tcpip_chksum_drop_enable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->DmaBase,DmaControl,DmaDisableDropTcpCs); - return; + synopGMACClearBits(gmacdev->DmaBase,DmaControl,DmaDisableDropTcpCs); + return; } /** * Instruct the DMA not to drop the packets even if it fails tcp ip checksum. @@ -2994,12 +2994,12 @@ void synopGMAC_rx_tcpip_chksum_drop_enable(synopGMACdevice *gmacdev) */ void synopGMAC_rx_tcpip_chksum_drop_disable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->DmaBase,DmaControl,DmaDisableDropTcpCs); - return; + synopGMACSetBits(gmacdev->DmaBase,DmaControl,DmaDisableDropTcpCs); + return; } #endif -/** +/** * When the Enhanced Descriptor is enabled then the bit 0 of RDES0 indicates whether the * Extended Status is available (RDES4). Time Stamp feature and the Checksum Offload Engine2 * makes use of this extended status to provide the status of the received packet. @@ -3016,9 +3016,9 @@ void synopGMAC_rx_tcpip_chksum_drop_disable(synopGMACdevice *gmacdev) * @param[in] u32 status field of the corresponding descriptor. * \return returns TRUE or FALSE. */ -bool synopGMAC_is_ext_status(synopGMACdevice *gmacdev,u32 status) // extended status present indicates that the RDES4 need to be probed +bool synopGMAC_is_ext_status(synopGMACdevice *gmacdev,u32 status) // extended status present indicates that the RDES4 need to be probed { - return((status & DescRxEXTsts ) != 0 ); // if extstatus set then it returns 1 + return((status & DescRxEXTsts ) != 0 ); // if extstatus set then it returns 1 } /** * This function returns true if the IP header checksum bit is set in the extended status. @@ -3030,7 +3030,7 @@ bool synopGMAC_is_ext_status(synopGMACdevice *gmacdev,u32 status) // ext */ bool synopGMAC_ES_is_IP_header_error(synopGMACdevice *gmacdev,u32 ext_status) // IP header (IPV4) checksum error { - return((ext_status & DescRxIpHeaderError) != 0 ); // if IPV4 header error return 1 + return((ext_status & DescRxIpHeaderError) != 0 ); // if IPV4 header error return 1 } /** * This function returns true if the Checksum is bypassed in the hardware. @@ -3042,7 +3042,7 @@ bool synopGMAC_ES_is_IP_header_error(synopGMACdevice *gmacdev,u32 ext_status) */ bool synopGMAC_ES_is_rx_checksum_bypassed(synopGMACdevice *gmacdev,u32 ext_status) // Hardware engine bypassed the checksum computation/checking { - return((ext_status & DescRxChkSumBypass ) != 0 ); // if checksum offloading bypassed return 1 + return((ext_status & DescRxChkSumBypass ) != 0 ); // if checksum offloading bypassed return 1 } /** * This function returns true if payload checksum error is set in the extended status. @@ -3054,7 +3054,7 @@ bool synopGMAC_ES_is_rx_checksum_bypassed(synopGMACdevice *gmacdev,u32 ext_statu */ bool synopGMAC_ES_is_IP_payload_error(synopGMACdevice *gmacdev,u32 ext_status) // IP payload checksum is in error (UDP/TCP/ICMP checksum error) { - return((ext_status & DescRxIpPayloadError) != 0 ); // if IP payload error return 1 + return((ext_status & DescRxIpPayloadError) != 0 ); // if IP payload error return 1 } #endif @@ -3068,22 +3068,22 @@ bool synopGMAC_ES_is_IP_payload_error(synopGMACdevice *gmacdev,u32 ext_status) */ u32 synopGMAC_is_rx_checksum_error(synopGMACdevice *gmacdev, u32 status) { - if (((status & DescRxChkBit5) == 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) == 0)) - return RxLenLT600; - else if(((status & DescRxChkBit5) == 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) != 0)) - return RxIpHdrPayLoadChkBypass; - else if(((status & DescRxChkBit5) == 0) && ((status & DescRxChkBit7) != 0) && ((status & DescRxChkBit0) != 0)) - return RxChkBypass; - else if(((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) == 0)) - return RxNoChkError; - else if(((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) != 0)) - return RxPayLoadChkError; - else if(((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) != 0) && ((status & DescRxChkBit0) == 0)) - return RxIpHdrChkError; - else if(((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) != 0) && ((status & DescRxChkBit0) != 0)) - return RxIpHdrPayLoadChkError; - else - return RxIpHdrPayLoadRes; + if (((status & DescRxChkBit5) == 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) == 0)) + return RxLenLT600; + else if(((status & DescRxChkBit5) == 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) != 0)) + return RxIpHdrPayLoadChkBypass; + else if(((status & DescRxChkBit5) == 0) && ((status & DescRxChkBit7) != 0) && ((status & DescRxChkBit0) != 0)) + return RxChkBypass; + else if(((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) == 0)) + return RxNoChkError; + else if(((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) != 0)) + return RxPayLoadChkError; + else if(((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) != 0) && ((status & DescRxChkBit0) == 0)) + return RxIpHdrChkError; + else if(((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) != 0) && ((status & DescRxChkBit0) != 0)) + return RxIpHdrPayLoadChkError; + else + return RxIpHdrPayLoadRes; } /** * Checks if any Ipv4 header checksum error in the frame just transmitted. @@ -3095,7 +3095,7 @@ u32 synopGMAC_is_rx_checksum_error(synopGMACdevice *gmacdev, u32 status) */ bool synopGMAC_is_tx_ipv4header_checksum_error(synopGMACdevice *gmacdev, u32 status) { - return((status & DescTxIpv4ChkError) == DescTxIpv4ChkError); + return((status & DescTxIpv4ChkError) == DescTxIpv4ChkError); } @@ -3109,7 +3109,7 @@ bool synopGMAC_is_tx_ipv4header_checksum_error(synopGMACdevice *gmacdev, u32 sta */ bool synopGMAC_is_tx_payload_checksum_error(synopGMACdevice *gmacdev, u32 status) { - return((status & DescTxPayChkError) == DescTxPayChkError); + return((status & DescTxPayChkError) == DescTxPayChkError); } /** * The check summ offload engine is bypassed in the tx path. @@ -3120,11 +3120,11 @@ bool synopGMAC_is_tx_payload_checksum_error(synopGMACdevice *gmacdev, u32 status */ void synopGMAC_tx_checksum_offload_bypass(synopGMACdevice *gmacdev, DmaDesc *desc) { - #ifdef ENH_DESC - desc->status = (desc->length & (~DescTxCisMask));//ENH_DESC - #else - desc->length = (desc->length & (~DescTxCisMask)); - #endif + #ifdef ENH_DESC + desc->status = (desc->length & (~DescTxCisMask));//ENH_DESC + #else + desc->length = (desc->length & (~DescTxCisMask)); + #endif } /** @@ -3136,11 +3136,11 @@ void synopGMAC_tx_checksum_offload_bypass(synopGMACdevice *gmacdev, DmaDesc *des */ void synopGMAC_tx_checksum_offload_ipv4hdr(synopGMACdevice *gmacdev, DmaDesc *desc) { - #ifdef ENH_DESC - desc->status = ((desc->status & (~DescTxCisMask)) | DescTxCisIpv4HdrCs);//ENH_DESC - #else - desc->length = ((desc->length & (~DescTxCisMask)) | DescTxCisIpv4HdrCs); - #endif + #ifdef ENH_DESC + desc->status = ((desc->status & (~DescTxCisMask)) | DescTxCisIpv4HdrCs);//ENH_DESC + #else + desc->length = ((desc->length & (~DescTxCisMask)) | DescTxCisIpv4HdrCs); + #endif } @@ -3154,11 +3154,11 @@ void synopGMAC_tx_checksum_offload_ipv4hdr(synopGMACdevice *gmacdev, DmaDesc *de */ void synopGMAC_tx_checksum_offload_tcponly(synopGMACdevice *gmacdev, DmaDesc *desc) { - #ifdef ENH_DESC - desc->status = ((desc->status & (~DescTxCisMask)) | DescTxCisTcpOnlyCs);//ENH_DESC - #else - desc->length = ((desc->length & (~DescTxCisMask)) | DescTxCisTcpOnlyCs); - #endif + #ifdef ENH_DESC + desc->status = ((desc->status & (~DescTxCisMask)) | DescTxCisTcpOnlyCs);//ENH_DESC + #else + desc->length = ((desc->length & (~DescTxCisMask)) | DescTxCisTcpOnlyCs); + #endif } /** @@ -3172,11 +3172,11 @@ void synopGMAC_tx_checksum_offload_tcponly(synopGMACdevice *gmacdev, DmaDesc *de */ void synopGMAC_tx_checksum_offload_tcp_pseudo(synopGMACdevice *gmacdev, DmaDesc *desc) { - #ifdef ENH_DESC - desc->status = ((desc->length & (~DescTxCisMask)) | DescTxCisTcpPseudoCs); - #else - desc->length = ((desc->length & (~DescTxCisMask)) | DescTxCisTcpPseudoCs); - #endif + #ifdef ENH_DESC + desc->status = ((desc->length & (~DescTxCisMask)) | DescTxCisTcpPseudoCs); + #else + desc->length = ((desc->length & (~DescTxCisMask)) | DescTxCisTcpPseudoCs); + #endif } /*******************Ip checksum offloading APIs***************************************/ @@ -3192,7 +3192,7 @@ void synopGMAC_tx_checksum_offload_tcp_pseudo(synopGMACdevice *gmacdev, DmaDesc * At this time the driver supports the IEEE time stamping feature when the Enhanced Descriptors are enabled. * For normal descriptor and the IEEE time stamp (version 1), driver support is not proviced * Please make sure you have enabled the Advanced timestamp feature in the hardware and the driver should - * be compiled with the ADV_TME_STAMP feature. + * be compiled with the ADV_TME_STAMP feature. * Some of the APIs provided here may not be valid for all configurations. Please make sure you call the * API with due care. */ @@ -3206,48 +3206,48 @@ void synopGMAC_tx_checksum_offload_tcp_pseudo(synopGMACdevice *gmacdev, DmaDesc #if UNUSED void synopGMAC_TS_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSENA); - return; + synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSENA); + return; } /** - * This function disables the timestamping. + * This function disables the timestamping. * When disabled timestamp is not added to tx and receive frames and timestamp generator is suspended. * @param[in] pointer to synopGMACdevice * \return returns void */ void synopGMAC_TS_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacInterruptMask, GmacTSIntMask); - return; + synopGMACClearBits(gmacdev->MacBase,GmacInterruptMask, GmacTSIntMask); + return; } /** - * Enable the interrupt to get timestamping interrupt. - * This enables the host to get the interrupt when (1) system time is greater or equal to the + * Enable the interrupt to get timestamping interrupt. + * This enables the host to get the interrupt when (1) system time is greater or equal to the * target time high and low register or (2) there is a overflow in th esecond register. * @param[in] pointer to synopGMACdevice * \return returns void */ void synopGMAC_TS_int_enable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask); + synopGMACClearBits(gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask); return; } /** - * Disable the interrupt to get timestamping interrupt. + * Disable the interrupt to get timestamping interrupt. * @param[in] pointer to synopGMACdevice * \return returns void */ void synopGMAC_TS_int_disable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask); + synopGMACSetBits(gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask); return; } /** - * Enable MAC address for PTP frame filtering. + * Enable MAC address for PTP frame filtering. * When enabled, uses MAC address (apart from MAC address 0) to filter the PTP frames when * PTP is sent directly over Ethernet. * @param[in] pointer to synopGMACdevice @@ -3255,46 +3255,46 @@ void synopGMAC_TS_int_disable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_mac_addr_filt_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSENMACADDR); - return; + synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSENMACADDR); + return; } /** - * Disables MAC address for PTP frame filtering. + * Disables MAC address for PTP frame filtering. * @param[in] pointer to synopGMACdevice * \return returns void */ void synopGMAC_TS_mac_addr_filt_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSENMACADDR); - return; + synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSENMACADDR); + return; } /** - * Selet the type of clock mode for PTP. + * Selet the type of clock mode for PTP. * Please note to use one of the follwoing as the clk_type argument. - * GmacTSOrdClk = 0x00000000, 00=> Ordinary clock - * GmacTSBouClk = 0x00010000, 01=> Boundary clock - * GmacTSEtoEClk = 0x00020000, 10=> End-to-End transparent clock - * GmacTSPtoPClk = 0x00030000, 11=> P-to-P transparent clock + * GmacTSOrdClk = 0x00000000, 00=> Ordinary clock + * GmacTSBouClk = 0x00010000, 01=> Boundary clock + * GmacTSEtoEClk = 0x00020000, 10=> End-to-End transparent clock + * GmacTSPtoPClk = 0x00030000, 11=> P-to-P transparent clock * @param[in] pointer to synopGMACdevice * @param[in] u32 value representing one of the above clk value * \return returns void */ void synopGMAC_TS_set_clk_type(synopGMACdevice *gmacdev, u32 clk_type) { - u32 clkval; - clkval = synopGMACReadReg(gmacdev->MacBase,GmacTSControl); //set the mdc clock to the user defined value - clkval = clkval | clk_type; - synopGMACWriteReg(gmacdev->MacBase,GmacTSControl,clkval); - return; + u32 clkval; + clkval = synopGMACReadReg(gmacdev->MacBase,GmacTSControl); //set the mdc clock to the user defined value + clkval = clkval | clk_type; + synopGMACWriteReg(gmacdev->MacBase,GmacTSControl,clkval); + return; } /** - * Enable Snapshot for messages relevant to Master. - * When enabled, snapshot is taken for messages relevant to master mode only, else snapshot is taken for messages relevant - * to slave node. + * Enable Snapshot for messages relevant to Master. + * When enabled, snapshot is taken for messages relevant to master mode only, else snapshot is taken for messages relevant + * to slave node. * Valid only for Ordinary clock and Boundary clock * Reserved when "Advanced Time Stamp" is not selected * @param[in] pointer to synopGMACdevice @@ -3302,13 +3302,13 @@ void synopGMAC_TS_set_clk_type(synopGMACdevice *gmacdev, u32 clk_type) */ void synopGMAC_TS_master_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSMSTRENA); - return; + synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSMSTRENA); + return; } /** - * Disable Snapshot for messages relevant to Master. - * When disabled, snapshot is taken for messages relevant - * to slave node. + * Disable Snapshot for messages relevant to Master. + * When disabled, snapshot is taken for messages relevant + * to slave node. * Valid only for Ordinary clock and Boundary clock * Reserved when "Advanced Time Stamp" is not selected * @param[in] pointer to synopGMACdevice @@ -3316,11 +3316,11 @@ void synopGMAC_TS_master_enable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_master_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSMSTRENA); - return; + synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSMSTRENA); + return; } /** - * Enable Snapshot for Event messages. + * Enable Snapshot for Event messages. * When enabled, snapshot is taken for event messages only (SYNC, Delay_Req, Pdelay_Req or Pdelay_Resp) * When disabled, snapshot is taken for all messages except Announce, Management and Signaling. * Reserved when "Advanced Time Stamp" is not selected @@ -3329,11 +3329,11 @@ void synopGMAC_TS_master_disable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_event_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSEVNTENA); - return; + synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSEVNTENA); + return; } /** - * Disable Snapshot for Event messages. + * Disable Snapshot for Event messages. * When disabled, snapshot is taken for all messages except Announce, Management and Signaling. * Reserved when "Advanced Time Stamp" is not selected * @param[in] pointer to synopGMACdevice @@ -3341,12 +3341,12 @@ void synopGMAC_TS_event_enable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_event_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSEVNTENA); - return; + synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSEVNTENA); + return; } /** - * Enable time stamp snapshot for IPV4 frames. + * Enable time stamp snapshot for IPV4 frames. * When enabled, time stamp snapshot is taken for IPV4 frames * Reserved when "Advanced Time Stamp" is not selected * @param[in] pointer to synopGMACdevice @@ -3354,11 +3354,11 @@ void synopGMAC_TS_event_disable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_IPV4_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSIPV4ENA); - return; + synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSIPV4ENA); + return; } /** - * Disable time stamp snapshot for IPV4 frames. + * Disable time stamp snapshot for IPV4 frames. * When disabled, time stamp snapshot is not taken for IPV4 frames * Reserved when "Advanced Time Stamp" is not selected * @param[in] pointer to synopGMACdevice @@ -3366,11 +3366,11 @@ void synopGMAC_TS_IPV4_enable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_IPV4_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSIPV4ENA); - return; + synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSIPV4ENA); + return; } // Only for "Advanced Time Stamp" /** - * Enable time stamp snapshot for IPV6 frames. + * Enable time stamp snapshot for IPV6 frames. * When enabled, time stamp snapshot is taken for IPV6 frames * Reserved when "Advanced Time Stamp" is not selected * @param[in] pointer to synopGMACdevice @@ -3378,11 +3378,11 @@ void synopGMAC_TS_IPV4_disable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_IPV6_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSIPV6ENA); - return; + synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSIPV6ENA); + return; } /** - * Disable time stamp snapshot for IPV6 frames. + * Disable time stamp snapshot for IPV6 frames. * When disabled, time stamp snapshot is not taken for IPV6 frames * Reserved when "Advanced Time Stamp" is not selected * @param[in] pointer to synopGMACdevice @@ -3390,12 +3390,12 @@ void synopGMAC_TS_IPV6_enable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_IPV6_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSIPV6ENA); - return; + synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSIPV6ENA); + return; } /** - * Enable time stamp snapshot for PTP over Ethernet frames. + * Enable time stamp snapshot for PTP over Ethernet frames. * When enabled, time stamp snapshot is taken for PTP over Ethernet frames * Reserved when "Advanced Time Stamp" is not selected * @param[in] pointer to synopGMACdevice @@ -3403,11 +3403,11 @@ void synopGMAC_TS_IPV6_disable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_ptp_over_ethernet_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSIPENA); - return; + synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSIPENA); + return; } /** - * Disable time stamp snapshot for PTP over Ethernet frames. + * Disable time stamp snapshot for PTP over Ethernet frames. * When disabled, time stamp snapshot is not taken for PTP over Ethernet frames * Reserved when "Advanced Time Stamp" is not selected * @param[in] pointer to synopGMACdevice @@ -3415,58 +3415,58 @@ void synopGMAC_TS_ptp_over_ethernet_enable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_ptp_over_ethernet_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSIPENA); - return; + synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSIPENA); + return; } /** - * Snoop PTP packet for version 2 format + * Snoop PTP packet for version 2 format * When set the PTP packets are snooped using the version 2 format. * @param[in] pointer to synopGMACdevice * \return returns void */ void synopGMAC_TS_pkt_snoop_ver2(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSVER2ENA); - return; + synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSVER2ENA); + return; } /** - * Snoop PTP packet for version 2 format + * Snoop PTP packet for version 2 format * When set the PTP packets are snooped using the version 2 format. * @param[in] pointer to synopGMACdevice * \return returns void */ void synopGMAC_TS_pkt_snoop_ver1(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSVER2ENA); - return; + synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSVER2ENA); + return; } /** - * Timestamp digital rollover + * Timestamp digital rollover * When set the timestamp low register rolls over after 0x3B9A_C9FF value. * @param[in] pointer to synopGMACdevice * \return returns void */ void synopGMAC_TS_digital_rollover_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSCTRLSSR); - return; -} + synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSCTRLSSR); + return; +} /** - * Timestamp binary rollover + * Timestamp binary rollover * When set the timestamp low register rolls over after 0x7FFF_FFFF value. * @param[in] pointer to synopGMACdevice * \return returns void */ void synopGMAC_TS_binary_rollover_enable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSCTRLSSR); - return; + synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSCTRLSSR); + return; } /** - * Enable Time Stamp for All frames + * Enable Time Stamp for All frames * When set the timestamp snap shot is enabled for all frames received by the core. * Reserved when "Advanced Time Stamp" is not selected * @param[in] pointer to synopGMACdevice @@ -3474,11 +3474,11 @@ void synopGMAC_TS_binary_rollover_enable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_all_frames_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSENALL); - return; + synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSENALL); + return; } /** - * Disable Time Stamp for All frames + * Disable Time Stamp for All frames * When reset the timestamp snap shot is not enabled for all frames received by the core. * Reserved when "Advanced Time Stamp" is not selected * @param[in] pointer to synopGMACdevice @@ -3486,11 +3486,11 @@ void synopGMAC_TS_all_frames_enable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_all_frames_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSENALL); - return; + synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSENALL); + return; } /** - * Addend Register Update + * Addend Register Update * This function loads the contents of Time stamp addend register with the supplied 32 value. * This is reserved function when only coarse correction option is selected * @param[in] pointer to synopGMACdevice @@ -3499,25 +3499,25 @@ void synopGMAC_TS_all_frames_disable(synopGMACdevice *gmacdev) */ s32 synopGMAC_TS_addend_update(synopGMACdevice *gmacdev, u32 addend_value) { - u32 loop_variable; + u32 loop_variable; synopGMACWriteReg(gmacdev->MacBase,GmacTSAddend,addend_value);// Load the addend_value in to Addend register for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ //Wait till the busy bit gets cleared with in a certain amount of time - if(!((synopGMACReadReg(gmacdev->MacBase,GmacTSControl)) & GmacTSADDREG)){ // if it is cleared then break - break; - } + if(!((synopGMACReadReg(gmacdev->MacBase,GmacTSControl)) & GmacTSADDREG)){ // if it is cleared then break + break; + } plat_delay(DEFAULT_DELAY_VARIABLE); } if(loop_variable < DEFAULT_LOOP_VARIABLE) synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSADDREG); else{ TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n"); - return -ESYNOPGMACPHYERR; + return -ESYNOPGMACPHYERR; } return -ESYNOPGMACNOERR; } /** - * time stamp Update + * time stamp Update * This function updates (adds/subtracts) with the value specified in the Timestamp High Update and * Timestamp Low Update register. * @param[in] pointer to synopGMACdevice @@ -3527,26 +3527,26 @@ return -ESYNOPGMACNOERR; */ s32 synopGMAC_TS_timestamp_update(synopGMACdevice *gmacdev, u32 high_value, u32 low_value) { - u32 loop_variable; + u32 loop_variable; synopGMACWriteReg(gmacdev->MacBase,GmacTSHighUpdate,high_value);// Load the high value to Timestamp High register synopGMACWriteReg(gmacdev->MacBase,GmacTSLowUpdate,low_value);// Load the high value to Timestamp High register for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ //Wait till the busy bit gets cleared with in a certain amount of time - if(!((synopGMACReadReg(gmacdev->MacBase,GmacTSControl)) & GmacTSUPDT)){ // if it is cleared then break - break; - } + if(!((synopGMACReadReg(gmacdev->MacBase,GmacTSControl)) & GmacTSUPDT)){ // if it is cleared then break + break; + } plat_delay(DEFAULT_DELAY_VARIABLE); } if(loop_variable < DEFAULT_LOOP_VARIABLE) synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSUPDT); else{ TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n"); - return -ESYNOPGMACPHYERR; + return -ESYNOPGMACPHYERR; } return -ESYNOPGMACNOERR; } /** - * time stamp Initialize + * time stamp Initialize * This function Loads/Initializes h the value specified in the Timestamp High Update and * Timestamp Low Update register. * @param[in] pointer to synopGMACdevice @@ -3556,59 +3556,59 @@ return -ESYNOPGMACNOERR; */ s32 synopGMAC_TS_timestamp_init(synopGMACdevice *gmacdev, u32 high_value, u32 low_value) { - u32 loop_variable; + u32 loop_variable; synopGMACWriteReg(gmacdev->MacBase,GmacTSHighUpdate,high_value);// Load the high value to Timestamp High register synopGMACWriteReg(gmacdev->MacBase,GmacTSLowUpdate,low_value);// Load the high value to Timestamp High register for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ //Wait till the busy bit gets cleared with in a certain amount of time - if(!((synopGMACReadReg(gmacdev->MacBase,GmacTSControl)) & GmacTSINT)){ // if it is cleared then break - break; - } + if(!((synopGMACReadReg(gmacdev->MacBase,GmacTSControl)) & GmacTSINT)){ // if it is cleared then break + break; + } plat_delay(DEFAULT_DELAY_VARIABLE); } if(loop_variable < DEFAULT_LOOP_VARIABLE) synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSINT); else{ TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n"); - return -ESYNOPGMACPHYERR; + return -ESYNOPGMACPHYERR; } return -ESYNOPGMACNOERR; } /** - * Time Stamp Update Coarse + * Time Stamp Update Coarse * When reset the timestamp update is done using coarse method. * @param[in] pointer to synopGMACdevice * \return returns void */ void synopGMAC_TS_coarse_update(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSCFUPDT); - return; + synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSCFUPDT); + return; } /** - * Time Stamp Update Fine + * Time Stamp Update Fine * When reset the timestamp update is done using Fine method. * @param[in] pointer to synopGMACdevice * \return returns void */ void synopGMAC_TS_fine_update(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSCFUPDT); - return; + synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSCFUPDT); + return; } /** - * Load the Sub Second Increment value in to Sub Second increment register + * Load the Sub Second Increment value in to Sub Second increment register * @param[in] pointer to synopGMACdevice * \return returns void */ void synopGMAC_TS_subsecond_init(synopGMACdevice *gmacdev, u32 sub_sec_inc_value) { - synopGMACWriteReg(gmacdev->MacBase,GmacTSSubSecIncr,(sub_sec_inc_value & GmacSSINCMsk)); - return; + synopGMACWriteReg(gmacdev->MacBase,GmacTSSubSecIncr,(sub_sec_inc_value & GmacSSINCMsk)); + return; } /** - * Reads the time stamp contents in to the respective pointers + * Reads the time stamp contents in to the respective pointers * These registers are readonly. * This function returns the 48 bit time stamp assuming Version 2 timestamp with higher word is selected. * @param[in] pointer to synopGMACdevice @@ -3616,40 +3616,40 @@ void synopGMAC_TS_subsecond_init(synopGMACdevice *gmacdev, u32 sub_sec_inc_value * @param[in] pointer to hold 32 bit second register contents * @param[in] pointer to hold 32 bit subnanosecond register contents * \return returns void - * \note Please note that since the atomic access to the timestamp registers is not possible, - * the contents read may be different from the actual time stamp. + * \note Please note that since the atomic access to the timestamp registers is not possible, + * the contents read may be different from the actual time stamp. */ void synopGMAC_TS_read_timestamp(synopGMACdevice *gmacdev, u16 * higher_sec_val, u32 * sec_val, u32 * sub_sec_val) { - * higher_sec_val = (u16)(synopGMACReadReg(gmacdev->MacBase,GmacTSHighWord) & GmacTSHighWordMask); + * higher_sec_val = (u16)(synopGMACReadReg(gmacdev->MacBase,GmacTSHighWord) & GmacTSHighWordMask); * sec_val = synopGMACReadReg(gmacdev->MacBase,GmacTSHigh); * sub_sec_val = synopGMACReadReg(gmacdev->MacBase,GmacTSLow); - return; + return; } /** - * Loads the time stamp higher sec value from the value supplied + * Loads the time stamp higher sec value from the value supplied * @param[in] pointer to synopGMACdevice * @param[in] 16 higher bit second register contents passed as 32 bit value * \return returns void */ void synopGMAC_TS_load_timestamp_higher_val(synopGMACdevice *gmacdev, u32 higher_sec_val) { - synopGMACWriteReg(gmacdev->MacBase,GmacTSHighWord, (higher_sec_val & GmacTSHighWordMask)); - return; + synopGMACWriteReg(gmacdev->MacBase,GmacTSHighWord, (higher_sec_val & GmacTSHighWordMask)); + return; } /** - * Reads the time stamp higher sec value to respective pointers + * Reads the time stamp higher sec value to respective pointers * @param[in] pointer to synopGMACdevice * @param[in] pointer to hold 16 higher bit second register contents * \return returns void */ void synopGMAC_TS_read_timestamp_higher_val(synopGMACdevice *gmacdev, u16 * higher_sec_val) { - * higher_sec_val = (u16)(synopGMACReadReg(gmacdev->MacBase,GmacTSHighWord) & GmacTSHighWordMask); - return; + * higher_sec_val = (u16)(synopGMACReadReg(gmacdev->MacBase,GmacTSHighWord) & GmacTSHighWordMask); + return; } /** - * Load the Target time stamp registers + * Load the Target time stamp registers * This function Loads the target time stamp registers with the values proviced * @param[in] pointer to synopGMACdevice * @param[in] target Timestamp High value @@ -3658,12 +3658,12 @@ void synopGMAC_TS_read_timestamp_higher_val(synopGMACdevice *gmacdev, u16 * high */ void synopGMAC_TS_load_target_timestamp(synopGMACdevice *gmacdev, u32 sec_val, u32 sub_sec_val) { - synopGMACWriteReg(gmacdev->MacBase,GmacTSTargetTimeHigh,sec_val); - synopGMACWriteReg(gmacdev->MacBase,GmacTSTargetTimeLow,sub_sec_val); - return; + synopGMACWriteReg(gmacdev->MacBase,GmacTSTargetTimeHigh,sec_val); + synopGMACWriteReg(gmacdev->MacBase,GmacTSTargetTimeLow,sub_sec_val); + return; } /** - * Reads the Target time stamp registers + * Reads the Target time stamp registers * This function Loads the target time stamp registers with the values proviced * @param[in] pointer to synopGMACdevice * @param[in] pointer to hold target Timestamp High value @@ -3672,8 +3672,8 @@ void synopGMAC_TS_load_target_timestamp(synopGMACdevice *gmacdev, u32 sec_val, u */ void synopGMAC_TS_read_target_timestamp(synopGMACdevice *gmacdev, u32 * sec_val, u32 * sub_sec_val) { - * sec_val = synopGMACReadReg(gmacdev->MacBase,GmacTSTargetTimeHigh); - * sub_sec_val = synopGMACReadReg(gmacdev->MacBase,GmacTSTargetTimeLow); - return; + * sec_val = synopGMACReadReg(gmacdev->MacBase,GmacTSTargetTimeHigh); + * sub_sec_val = synopGMACReadReg(gmacdev->MacBase,GmacTSTargetTimeLow); + return; } #endif diff --git a/bsp/ls1cdev/drivers/net/synopGMAC_Dev.h b/bsp/ls1cdev/drivers/net/synopGMAC_Dev.h index 74bc850d86..9c1d9869e4 100644 --- a/bsp/ls1cdev/drivers/net/synopGMAC_Dev.h +++ b/bsp/ls1cdev/drivers/net/synopGMAC_Dev.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -8,9 +8,9 @@ * 2017-08-24 chinesebear first version */ - -#define UNUSED 1 - + +#define UNUSED 1 + #ifndef SYNOP_GMAC_DEV_H #define SYNOP_GMAC_DEV_H 1 @@ -31,41 +31,41 @@ #include "synopGMAC_plat.h" #include "synopGMAC_types.h" -//sw: typedef are included in synopGMAC_plat.h -// it is strange that we should add it here again!! +//sw: typedef are included in synopGMAC_plat.h +// it is strange that we should add it here again!! /*SynopGMAC can support up to 32 phys*/ #define GMAC_PHY_BASE 1 #ifdef GMAC_PHY_BASE #define DEFAULT_PHY_BASE GMAC_PHY_BASE #else -#define DEFAULT_PHY_BASE PHY16 //We use First Phy +#define DEFAULT_PHY_BASE PHY16 //We use First Phy #endif -#define MACBASE 0x0000 // The Mac Base address offset is 0x0000 -#define DMABASE 0x1000 // Dma base address starts with an offset 0x1000 +#define MACBASE 0x0000 // The Mac Base address offset is 0x0000 +#define DMABASE 0x1000 // Dma base address starts with an offset 0x1000 enum GMACPhyBase { - PHY0 = 0, //The device can support 32 phys, but we use first phy only - PHY1 = 1, - PHY16 = 16, - PHY31 = 31, + PHY0 = 0, //The device can support 32 phys, but we use first phy only + PHY1 = 1, + PHY16 = 16, + PHY31 = 31, }; -//#define TRANSMIT_DESC_SIZE 256 //Tx Descriptors needed in the Descriptor pool/queue -//#define RECEIVE_DESC_SIZE 256 //Rx Descriptors needed in the Descriptor pool/queue -//#define TRANSMIT_DESC_SIZE 13//256 //Tx Descriptors needed in the Descriptor pool/queue -#define TRANSMIT_DESC_SIZE 36 //48 //Tx Descriptors needed in the Descriptor pool/queue -#define RECEIVE_DESC_SIZE 72 //96 //Rx Descriptors needed in the Descriptor pool/queue +//#define TRANSMIT_DESC_SIZE 256 //Tx Descriptors needed in the Descriptor pool/queue +//#define RECEIVE_DESC_SIZE 256 //Rx Descriptors needed in the Descriptor pool/queue +//#define TRANSMIT_DESC_SIZE 13//256 //Tx Descriptors needed in the Descriptor pool/queue +#define TRANSMIT_DESC_SIZE 36 //48 //Tx Descriptors needed in the Descriptor pool/queue +#define RECEIVE_DESC_SIZE 72 //96 //Rx Descriptors needed in the Descriptor pool/queue -#define ETHERNET_HEADER 14 //6 byte Dest addr, 6 byte Src addr, 2 byte length/type -#define ETHERNET_CRC 4 //Ethernet CRC -#define ETHERNET_EXTRA 2 //Only God knows about this????? -#define ETHERNET_PACKET_COPY 250 // Maximum length when received data is copied on to a new skb -#define ETHERNET_PACKET_EXTRA 18 // Preallocated length for the rx packets is MTU + ETHERNET_PACKET_EXTRA -#define VLAN_TAG 4 //optional 802.1q VLAN Tag +#define ETHERNET_HEADER 14 //6 byte Dest addr, 6 byte Src addr, 2 byte length/type +#define ETHERNET_CRC 4 //Ethernet CRC +#define ETHERNET_EXTRA 2 //Only God knows about this????? +#define ETHERNET_PACKET_COPY 250 // Maximum length when received data is copied on to a new skb +#define ETHERNET_PACKET_EXTRA 18 // Preallocated length for the rx packets is MTU + ETHERNET_PACKET_EXTRA +#define VLAN_TAG 4 //optional 802.1q VLAN Tag #define MIN_ETHERNET_PAYLOAD 46 //Minimum Ethernet payload size #define MAX_ETHERNET_PAYLOAD 1500 //Maximum Ethernet payload size #define JUMBO_FRAME_PAYLOAD 9000 //Jumbo frame payload size @@ -84,80 +84,80 @@ The descriptor is of 4 words, but our structrue contains 6 words where last two words are to hold the virtual address of the network buffer pointers for driver's use From the GMAC core release 3.50a onwards, the Enhanced Descriptor structure got changed. -The descriptor (both transmit and receive) are of 8 words each rather the 4 words of normal +The descriptor (both transmit and receive) are of 8 words each rather the 4 words of normal descriptor structure. Whenever IEEE 1588 Timestamping is enabled TX/RX DESC6 provides the lower 32 bits of Timestamp value and TX/RX DESC7 provides the upper 32 bits of Timestamp value In addition to this whenever extended status bit is set (RX DESC0 bit 0), RX DESC4 contains the extended status information */ -#define MODULO_INTERRUPT 1 // if it is set to 1, interrupt is available for all the descriptors or else interrupt is available only for - // descriptor whose index%MODULO_INTERRUPT is zero +#define MODULO_INTERRUPT 1 // if it is set to 1, interrupt is available for all the descriptors or else interrupt is available only for + // descriptor whose index%MODULO_INTERRUPT is zero #ifdef ENH_DESC_8W -typedef struct DmaDescStruct -{ - u32 status; /* Status */ - u32 length; /* Buffer 1 and Buffer 2 length */ - u32 buffer1; /* Network Buffer 1 pointer (Dma-able) */ - u32 buffer2; /* Network Buffer 2 pointer or next descriptor pointer (Dma-able)in chain structure */ - /* This data below is used only by driver */ +typedef struct DmaDescStruct +{ + u32 status; /* Status */ + u32 length; /* Buffer 1 and Buffer 2 length */ + u32 buffer1; /* Network Buffer 1 pointer (Dma-able) */ + u32 buffer2; /* Network Buffer 2 pointer or next descriptor pointer (Dma-able)in chain structure */ + /* This data below is used only by driver */ u32 extstatus; /* Extended status of a Rx Descriptor */ u32 reserved1; /* Reserved word */ u32 timestamplow; /* Lower 32 bits of the 64 bit timestamp value */ u32 timestamphigh; /* Higher 32 bits of the 64 bit timestamp value */ - u32 data1; /* This holds virtual address of buffer1, not used by DMA */ - u32 data2; /* This holds virtual address of buffer2, not used by DMA */ + u32 data1; /* This holds virtual address of buffer1, not used by DMA */ + u32 data2; /* This holds virtual address of buffer2, not used by DMA */ } DmaDesc; #else -typedef struct DmaDescStruct -{ - u32 status; /* Status */ - u32 length; /* Buffer 1 and Buffer 2 length */ - u32 buffer1; /* Network Buffer 1 pointer (Dma-able) */ - u32 buffer2; /* Network Buffer 2 pointer or next descriptor pointer (Dma-able)in chain structure */ - /* This data below is used only by driver */ - u32 data1; /* This holds virtual address of buffer1, not used by DMA */ - u32 data2; /* This holds virtual address of buffer2, not used by DMA */ - - u32 dummy1; //sw: for addr align - u32 dummy2; // +typedef struct DmaDescStruct +{ + u32 status; /* Status */ + u32 length; /* Buffer 1 and Buffer 2 length */ + u32 buffer1; /* Network Buffer 1 pointer (Dma-able) */ + u32 buffer2; /* Network Buffer 2 pointer or next descriptor pointer (Dma-able)in chain structure */ + /* This data below is used only by driver */ + u32 data1; /* This holds virtual address of buffer1, not used by DMA */ + u32 data2; /* This holds virtual address of buffer2, not used by DMA */ + + u32 dummy1; //sw: for addr align + u32 dummy2; // } DmaDesc; #endif enum DescMode { - RINGMODE = 0x00000001, - CHAINMODE = 0x00000002, + RINGMODE = 0x00000001, + CHAINMODE = 0x00000002, }; enum BufferMode { - SINGLEBUF = 0x00000001, - DUALBUF = 0x00000002, + SINGLEBUF = 0x00000001, + DUALBUF = 0x00000002, }; /* synopGMAC device data */ -typedef struct synopGMACDeviceStruct +typedef struct synopGMACDeviceStruct { - u32 MacBase; /* base address of MAC registers */ - u32 DmaBase; /* base address of DMA registers */ - u32 PhyBase; /* PHY device address on MII interface */ - u32 Version; /* Gmac Revision version */ - - - dma_addr_t TxDescDma; /* Dma-able address of first tx descriptor either in ring or chain mode, this is used by the GMAC device*/ - dma_addr_t RxDescDma; /* Dma-albe address of first rx descriptor either in ring or chain mode, this is used by the GMAC device*/ + u32 MacBase; /* base address of MAC registers */ + u32 DmaBase; /* base address of DMA registers */ + u32 PhyBase; /* PHY device address on MII interface */ + u32 Version; /* Gmac Revision version */ + + + dma_addr_t TxDescDma; /* Dma-able address of first tx descriptor either in ring or chain mode, this is used by the GMAC device*/ + dma_addr_t RxDescDma; /* Dma-albe address of first rx descriptor either in ring or chain mode, this is used by the GMAC device*/ DmaDesc *TxDesc; /* start address of TX descriptors ring or chain, this is used by the driver */ DmaDesc *RxDesc; /* start address of RX descriptors ring or chain, this is used by the driver */ - u32 BusyTxDesc; /* Number of Tx Descriptors owned by DMA at any given time*/ - u32 BusyRxDesc; /* Number of Rx Descriptors owned by DMA at any given time*/ - + u32 BusyTxDesc; /* Number of Tx Descriptors owned by DMA at any given time*/ + u32 BusyRxDesc; /* Number of Rx Descriptors owned by DMA at any given time*/ + u32 RxDescCount; /* number of rx descriptors in the tx descriptor queue/pool */ u32 TxDescCount; /* number of tx descriptors in the rx descriptor queue/pool */ - + u32 TxBusy; /* index of the tx descriptor owned by DMA, is obtained by synopGMAC_get_tx_qptr() */ u32 TxNext; /* index of the tx descriptor next available with driver, given to DMA by synopGMAC_set_tx_qptr() */ u32 RxBusy; /* index of the rx descriptor owned by DMA, obtained by synopGMAC_get_rx_qptr() */ @@ -169,14 +169,14 @@ typedef struct synopGMACDeviceStruct DmaDesc * RxNextDesc; /* Rx Descriptor address corresponding to the index RxNext */ /*Phy related stuff*/ - u32 ClockDivMdc; /* Clock divider value programmed in the hardware */ + u32 ClockDivMdc; /* Clock divider value programmed in the hardware */ /* The status of the link */ - u32 LinkState0; /* Link status as reported by the Marvel Phy */ - u32 LinkState; /* Link status as reported by the Marvel Phy */ - u32 DuplexMode; /* Duplex mode of the Phy */ - u32 Speed; /* Speed of the Phy */ - u32 LoopBackMode; /* Loopback status of the Phy */ - + u32 LinkState0; /* Link status as reported by the Marvel Phy */ + u32 LinkState; /* Link status as reported by the Marvel Phy */ + u32 DuplexMode; /* Duplex mode of the Phy */ + u32 Speed; /* Speed of the Phy */ + u32 LoopBackMode; /* Loopback status of the Phy */ + // void * FirstTxDesc; // void * FirstRxDesc; // u32 skb_array[RECEIVE_DESC_SIZE]; @@ -184,36 +184,36 @@ typedef struct synopGMACDeviceStruct -/* Below is "88E1011/88E1011S Integrated 10/100/1000 Gigabit Ethernet Transceiver" +/* Below is "88E1011/88E1011S Integrated 10/100/1000 Gigabit Ethernet Transceiver" * Register and their layouts. This Phy has been used in the Dot Aster GMAC Phy daughter. * Since the Phy register map is standard, this map hardly changes to a different Ppy */ enum MiiRegisters { - PHY_CONTROL_REG = 0x0000, /*Control Register*/ - PHY_STATUS_REG = 0x0001, /*Status Register */ - PHY_ID_HI_REG = 0x0002, /*PHY Identifier High Register*/ - PHY_ID_LOW_REG = 0x0003, /*PHY Identifier High Register*/ - PHY_AN_ADV_REG = 0x0004, /*Auto-Negotiation Advertisement Register*/ - PHY_LNK_PART_ABl_REG = 0x0005, /*Link Partner Ability Register (Base Page)*/ - PHY_AN_EXP_REG = 0x0006, /*Auto-Negotiation Expansion Register*/ - PHY_AN_NXT_PAGE_TX_REG = 0x0007, /*Next Page Transmit Register*/ - PHY_LNK_PART_NXT_PAGE_REG = 0x0008, /*Link Partner Next Page Register*/ - PHY_1000BT_CTRL_REG = 0x0009, /*1000BASE-T Control Register*/ - PHY_1000BT_STATUS_REG = 0x000a, /*1000BASE-T Status Register*/ - PHY_SPECIFIC_CTRL_REG = 0x0010, /*Phy specific control register*/ - PHY_SPECIFIC_STATUS_REG = 0x0011, /*Phy specific status register*/ - PHY_INTERRUPT_ENABLE_REG = 0x0012, /*Phy interrupt enable register*/ - PHY_INTERRUPT_STATUS_REG = 0x0013, /*Phy interrupt status register*/ - PHY_EXT_PHY_SPC_CTRL = 0x0014, /*Extended Phy specific control*/ - PHY_RX_ERR_COUNTER = 0x0015, /*Receive Error Counter*/ - PHY_EXT_ADDR_CBL_DIAG = 0x0016, /*Extended address for cable diagnostic register*/ - PHY_LED_CONTROL = 0x0018, /*LED Control*/ - PHY_MAN_LED_OVERIDE = 0x0019, /*Manual LED override register*/ - PHY_EXT_PHY_SPC_CTRL2 = 0x001a, /*Extended Phy specific control 2*/ - PHY_EXT_PHY_SPC_STATUS = 0x001b, /*Extended Phy specific status*/ - PHY_CBL_DIAG_REG = 0x001c, /*Cable diagnostic registers*/ + PHY_CONTROL_REG = 0x0000, /*Control Register*/ + PHY_STATUS_REG = 0x0001, /*Status Register */ + PHY_ID_HI_REG = 0x0002, /*PHY Identifier High Register*/ + PHY_ID_LOW_REG = 0x0003, /*PHY Identifier High Register*/ + PHY_AN_ADV_REG = 0x0004, /*Auto-Negotiation Advertisement Register*/ + PHY_LNK_PART_ABl_REG = 0x0005, /*Link Partner Ability Register (Base Page)*/ + PHY_AN_EXP_REG = 0x0006, /*Auto-Negotiation Expansion Register*/ + PHY_AN_NXT_PAGE_TX_REG = 0x0007, /*Next Page Transmit Register*/ + PHY_LNK_PART_NXT_PAGE_REG = 0x0008, /*Link Partner Next Page Register*/ + PHY_1000BT_CTRL_REG = 0x0009, /*1000BASE-T Control Register*/ + PHY_1000BT_STATUS_REG = 0x000a, /*1000BASE-T Status Register*/ + PHY_SPECIFIC_CTRL_REG = 0x0010, /*Phy specific control register*/ + PHY_SPECIFIC_STATUS_REG = 0x0011, /*Phy specific status register*/ + PHY_INTERRUPT_ENABLE_REG = 0x0012, /*Phy interrupt enable register*/ + PHY_INTERRUPT_STATUS_REG = 0x0013, /*Phy interrupt status register*/ + PHY_EXT_PHY_SPC_CTRL = 0x0014, /*Extended Phy specific control*/ + PHY_RX_ERR_COUNTER = 0x0015, /*Receive Error Counter*/ + PHY_EXT_ADDR_CBL_DIAG = 0x0016, /*Extended address for cable diagnostic register*/ + PHY_LED_CONTROL = 0x0018, /*LED Control*/ + PHY_MAN_LED_OVERIDE = 0x0019, /*Manual LED override register*/ + PHY_EXT_PHY_SPC_CTRL2 = 0x001a, /*Extended Phy specific control 2*/ + PHY_EXT_PHY_SPC_STATUS = 0x001b, /*Extended Phy specific status*/ + PHY_CBL_DIAG_REG = 0x001c, /*Cable diagnostic registers*/ }; @@ -221,62 +221,62 @@ enum MiiRegisters */ enum Mii_GEN_CTRL -{ /* Description bits R/W default value */ - Mii_reset = 0x8000, - Mii_Speed_10 = 0x0000, /* 10 Mbps 6:13 RW */ - Mii_Speed_100 = 0x2000, /* 100 Mbps 6:13 RW */ - Mii_Speed_1000 = 0x0040, /* 1000 Mbit/s 6:13 RW */ - - Mii_Duplex = 0x0100, /* Full Duplex mode 8 RW */ - - Mii_Manual_Master_Config = 0x0800, /* Manual Master Config 11 RW */ - - Mii_Loopback = 0x4000, /* Enable Loop back 14 RW */ - Mii_NoLoopback = 0x0000, /* Enable Loop back 14 RW */ +{ /* Description bits R/W default value */ + Mii_reset = 0x8000, + Mii_Speed_10 = 0x0000, /* 10 Mbps 6:13 RW */ + Mii_Speed_100 = 0x2000, /* 100 Mbps 6:13 RW */ + Mii_Speed_1000 = 0x0040, /* 1000 Mbit/s 6:13 RW */ + + Mii_Duplex = 0x0100, /* Full Duplex mode 8 RW */ + + Mii_Manual_Master_Config = 0x0800, /* Manual Master Config 11 RW */ + + Mii_Loopback = 0x4000, /* Enable Loop back 14 RW */ + Mii_NoLoopback = 0x0000, /* Enable Loop back 14 RW */ }; enum Mii_Phy_Status { - Mii_phy_status_speed_10 = 0x0000, - Mii_phy_status_speed_100 = 0x4000, - Mii_phy_status_speed_1000 = 0x8000, - - Mii_phy_status_full_duplex = 0x2000, - Mii_phy_status_half_duplex = 0x0000, - - Mii_phy_status_link_up = 0x0400, //lyf:rtl 8211 phy -// Mii_phy_status_link_up = 0x0100, //sw: broadcom BCM5461 PHY + Mii_phy_status_speed_10 = 0x0000, + Mii_phy_status_speed_100 = 0x4000, + Mii_phy_status_speed_1000 = 0x8000, + + Mii_phy_status_full_duplex = 0x2000, + Mii_phy_status_half_duplex = 0x0000, + + Mii_phy_status_link_up = 0x0400, //lyf:rtl 8211 phy +// Mii_phy_status_link_up = 0x0100, //sw: broadcom BCM5461 PHY }; /* This is Status register layout. Status register is of 16 bit wide. */ enum Mii_GEN_STATUS { - Mii_AutoNegCmplt = 0x0020, /* Autonegotiation completed 5 RW */ - Mii_Link = 0x0004, /* Link status 2 RW */ + Mii_AutoNegCmplt = 0x0020, /* Autonegotiation completed 5 RW */ + Mii_Link = 0x0004, /* Link status 2 RW */ }; enum Mii_Link_Status { - LINKDOWN = 0, - LINKUP = 1, + LINKDOWN = 0, + LINKUP = 1, }; enum Mii_Duplex_Mode { - HALFDUPLEX = 1, - FULLDUPLEX = 2, + HALFDUPLEX = 1, + FULLDUPLEX = 2, }; enum Mii_Link_Speed { - SPEED10 = 1, - SPEED100 = 2, - SPEED1000 = 3, + SPEED10 = 1, + SPEED100 = 2, + SPEED1000 = 3, }; enum Mii_Loop_Back { - NOLOOPBACK = 0, - LOOPBACK = 1, + NOLOOPBACK = 0, + LOOPBACK = 1, }; @@ -286,107 +286,107 @@ enum Mii_Loop_Back * For Pci based system address is BARx + GmacRegisterBase * For any other system translation is done accordingly **********************************************************/ -enum GmacRegisters +enum GmacRegisters { - GmacConfig = 0x0000, /* Mac config Register */ - GmacFrameFilter = 0x0004, /* Mac frame filtering controls */ - GmacHashHigh = 0x0008, /* Multi-cast hash table high */ - GmacHashLow = 0x000C, /* Multi-cast hash table low */ - GmacGmiiAddr = 0x0010, /* GMII address Register(ext. Phy) */ - GmacGmiiData = 0x0014, /* GMII data Register(ext. Phy) */ - GmacFlowControl = 0x0018, /* Flow control Register */ - GmacVlan = 0x001C, /* VLAN tag Register (IEEE 802.1Q) */ - - GmacVersion = 0x0020, /* GMAC Core Version Register */ - GmacWakeupAddr = 0x0028, /* GMAC wake-up frame filter adrress reg */ - GmacPmtCtrlStatus = 0x002C, /* PMT control and status register */ - - GmacInterruptStatus = 0x0038, /* Mac Interrupt ststus register */ - GmacInterruptMask = 0x003C, /* Mac Interrupt Mask register */ - - GmacAddr0High = 0x0040, /* Mac address0 high Register */ - GmacAddr0Low = 0x0044, /* Mac address0 low Register */ - GmacAddr1High = 0x0048, /* Mac address1 high Register */ - GmacAddr1Low = 0x004C, /* Mac address1 low Register */ - GmacAddr2High = 0x0050, /* Mac address2 high Register */ - GmacAddr2Low = 0x0054, /* Mac address2 low Register */ - GmacAddr3High = 0x0058, /* Mac address3 high Register */ - GmacAddr3Low = 0x005C, /* Mac address3 low Register */ - GmacAddr4High = 0x0060, /* Mac address4 high Register */ - GmacAddr4Low = 0x0064, /* Mac address4 low Register */ - GmacAddr5High = 0x0068, /* Mac address5 high Register */ - GmacAddr5Low = 0x006C, /* Mac address5 low Register */ - GmacAddr6High = 0x0070, /* Mac address6 high Register */ - GmacAddr6Low = 0x0074, /* Mac address6 low Register */ - GmacAddr7High = 0x0078, /* Mac address7 high Register */ - GmacAddr7Low = 0x007C, /* Mac address7 low Register */ - GmacAddr8High = 0x0080, /* Mac address8 high Register */ - GmacAddr8Low = 0x0084, /* Mac address8 low Register */ - GmacAddr9High = 0x0088, /* Mac address9 high Register */ - GmacAddr9Low = 0x008C, /* Mac address9 low Register */ + GmacConfig = 0x0000, /* Mac config Register */ + GmacFrameFilter = 0x0004, /* Mac frame filtering controls */ + GmacHashHigh = 0x0008, /* Multi-cast hash table high */ + GmacHashLow = 0x000C, /* Multi-cast hash table low */ + GmacGmiiAddr = 0x0010, /* GMII address Register(ext. Phy) */ + GmacGmiiData = 0x0014, /* GMII data Register(ext. Phy) */ + GmacFlowControl = 0x0018, /* Flow control Register */ + GmacVlan = 0x001C, /* VLAN tag Register (IEEE 802.1Q) */ + + GmacVersion = 0x0020, /* GMAC Core Version Register */ + GmacWakeupAddr = 0x0028, /* GMAC wake-up frame filter adrress reg */ + GmacPmtCtrlStatus = 0x002C, /* PMT control and status register */ + + GmacInterruptStatus = 0x0038, /* Mac Interrupt ststus register */ + GmacInterruptMask = 0x003C, /* Mac Interrupt Mask register */ + + GmacAddr0High = 0x0040, /* Mac address0 high Register */ + GmacAddr0Low = 0x0044, /* Mac address0 low Register */ + GmacAddr1High = 0x0048, /* Mac address1 high Register */ + GmacAddr1Low = 0x004C, /* Mac address1 low Register */ + GmacAddr2High = 0x0050, /* Mac address2 high Register */ + GmacAddr2Low = 0x0054, /* Mac address2 low Register */ + GmacAddr3High = 0x0058, /* Mac address3 high Register */ + GmacAddr3Low = 0x005C, /* Mac address3 low Register */ + GmacAddr4High = 0x0060, /* Mac address4 high Register */ + GmacAddr4Low = 0x0064, /* Mac address4 low Register */ + GmacAddr5High = 0x0068, /* Mac address5 high Register */ + GmacAddr5Low = 0x006C, /* Mac address5 low Register */ + GmacAddr6High = 0x0070, /* Mac address6 high Register */ + GmacAddr6Low = 0x0074, /* Mac address6 low Register */ + GmacAddr7High = 0x0078, /* Mac address7 high Register */ + GmacAddr7Low = 0x007C, /* Mac address7 low Register */ + GmacAddr8High = 0x0080, /* Mac address8 high Register */ + GmacAddr8Low = 0x0084, /* Mac address8 low Register */ + GmacAddr9High = 0x0088, /* Mac address9 high Register */ + GmacAddr9Low = 0x008C, /* Mac address9 low Register */ GmacAddr10High = 0x0090, /* Mac address10 high Register */ - GmacAddr10Low = 0x0094, /* Mac address10 low Register */ - GmacAddr11High = 0x0098, /* Mac address11 high Register */ - GmacAddr11Low = 0x009C, /* Mac address11 low Register */ - GmacAddr12High = 0x00A0, /* Mac address12 high Register */ - GmacAddr12Low = 0x00A4, /* Mac address12 low Register */ - GmacAddr13High = 0x00A8, /* Mac address13 high Register */ - GmacAddr13Low = 0x00AC, /* Mac address13 low Register */ - GmacAddr14High = 0x00B0, /* Mac address14 high Register */ - GmacAddr14Low = 0x00B4, /* Mac address14 low Register */ - GmacAddr15High = 0x00B8, /* Mac address15 high Register */ - GmacAddr15Low = 0x00BC, /* Mac address15 low Register */ + GmacAddr10Low = 0x0094, /* Mac address10 low Register */ + GmacAddr11High = 0x0098, /* Mac address11 high Register */ + GmacAddr11Low = 0x009C, /* Mac address11 low Register */ + GmacAddr12High = 0x00A0, /* Mac address12 high Register */ + GmacAddr12Low = 0x00A4, /* Mac address12 low Register */ + GmacAddr13High = 0x00A8, /* Mac address13 high Register */ + GmacAddr13Low = 0x00AC, /* Mac address13 low Register */ + GmacAddr14High = 0x00B0, /* Mac address14 high Register */ + GmacAddr14Low = 0x00B4, /* Mac address14 low Register */ + GmacAddr15High = 0x00B8, /* Mac address15 high Register */ + GmacAddr15Low = 0x00BC, /* Mac address15 low Register */ GmacStatus = 0x00d8, /*MAC status*/ /*Time Stamp Register Map*/ - GmacTSControl = 0x0700, /* Controls the Timestamp update logic : only when IEEE 1588 time stamping is enabled in corekit */ + GmacTSControl = 0x0700, /* Controls the Timestamp update logic : only when IEEE 1588 time stamping is enabled in corekit */ + + GmacTSSubSecIncr = 0x0704, /* 8 bit value by which sub second register is incremented : only when IEEE 1588 time stamping without external timestamp input */ - GmacTSSubSecIncr = 0x0704, /* 8 bit value by which sub second register is incremented : only when IEEE 1588 time stamping without external timestamp input */ + GmacTSHigh = 0x0708, /* 32 bit seconds(MS) : only when IEEE 1588 time stamping without external timestamp input */ + GmacTSLow = 0x070C, /* 32 bit nano seconds(MS) : only when IEEE 1588 time stamping without external timestamp input */ - GmacTSHigh = 0x0708, /* 32 bit seconds(MS) : only when IEEE 1588 time stamping without external timestamp input */ - GmacTSLow = 0x070C, /* 32 bit nano seconds(MS) : only when IEEE 1588 time stamping without external timestamp input */ - GmacTSHighUpdate = 0x0710, /* 32 bit seconds(MS) to be written/added/subtracted : only when IEEE 1588 time stamping without external timestamp input */ GmacTSLowUpdate = 0x0714, /* 32 bit nano seconds(MS) to be writeen/added/subtracted : only when IEEE 1588 time stamping without external timestamp input */ - + GmacTSAddend = 0x0718, /* Used by Software to readjust the clock frequency linearly : only when IEEE 1588 time stamping without external timestamp input */ - - GmacTSTargetTimeHigh = 0x071C, /* 32 bit seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */ + + GmacTSTargetTimeHigh = 0x071C, /* 32 bit seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */ GmacTSTargetTimeLow = 0x0720, /* 32 bit nano seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */ GmacTSHighWord = 0x0724, /* Time Stamp Higher Word Register (Version 2 only); only lower 16 bits are valid */ //GmacTSHighWordUpdate = 0x072C, /* Time Stamp Higher Word Update Register (Version 2 only); only lower 16 bits are valid */ - + GmacTSStatus = 0x0728, /* Time Stamp Status Register */ }; /********************************************************** * GMAC Network interface registers * This explains the Register's Layout - - * FES is Read only by default and is enabled only when Tx + + * FES is Read only by default and is enabled only when Tx * Config Parameter is enabled for RGMII/SGMII interface * during CoreKit Config. - + * DM is Read only with value 1'b1 in Full duplex only Config **********************************************************/ /* GmacConfig = 0x0000, Mac config Register Layout */ -enum GmacConfigReg -{ +enum GmacConfigReg +{ /* Bit description Bits R/W Reset value */ - GmacWatchdog = 0x00800000, + GmacWatchdog = 0x00800000, GmacWatchdogDisable = 0x00800000, /* (WD)Disable watchdog timer on Rx 23 RW */ GmacWatchdogEnable = 0x00000000, /* Enable watchdog timer 0 */ - GmacJabber = 0x00400000, + GmacJabber = 0x00400000, GmacJabberDisable = 0x00400000, /* (JD)Disable jabber timer on Tx 22 RW */ GmacJabberEnable = 0x00000000, /* Enable jabber timer 0 */ GmacFrameBurst = 0x00200000, GmacFrameBurstEnable = 0x00200000, /* (BE)Enable frame bursting during Tx 21 RW */ GmacFrameBurstDisable = 0x00000000, /* Disable frame bursting 0 */ - + GmacJumboFrame = 0x00100000, GmacJumboFrameEnable = 0x00100000, /* (JE)Enable jumbo frame for Tx 20 RW */ GmacJumboFrameDisable = 0x00000000, /* Disable jumbo frame 0 */ @@ -399,69 +399,69 @@ enum GmacConfigReg GmacInterFrameGap2 = 0x00020000, /* (IFG) Config2 - 80 bit times */ GmacInterFrameGap1 = 0x00010000, /* (IFG) Config1 - 88 bit times */ GmacInterFrameGap0 = 0x00000000, /* (IFG) Config0 - 96 bit times 000 */ - - GmacDisableCrs = 0x00010000, - GmacMiiGmii = 0x00008000, + + GmacDisableCrs = 0x00010000, + GmacMiiGmii = 0x00008000, GmacSelectMii = 0x00008000, /* (PS)Port Select-MII mode 15 RW */ GmacSelectGmii = 0x00000000, /* GMII mode 0 */ - GmacFESpeed100 = 0x00004000, /*(FES)Fast Ethernet speed 100Mbps 14 RW */ - GmacFESpeed10 = 0x00000000, /* 10Mbps 0 */ + GmacFESpeed100 = 0x00004000, /*(FES)Fast Ethernet speed 100Mbps 14 RW */ + GmacFESpeed10 = 0x00000000, /* 10Mbps 0 */ - GmacRxOwn = 0x00002000, + GmacRxOwn = 0x00002000, GmacDisableRxOwn = 0x00002000, /* (DO)Disable receive own packets 13 RW */ GmacEnableRxOwn = 0x00000000, /* Enable receive own packets 0 */ - - GmacLoopback = 0x00001000, + + GmacLoopback = 0x00001000, GmacLoopbackOn = 0x00001000, /* (LM)Loopback mode for GMII/MII 12 RW */ GmacLoopbackOff = 0x00000000, /* Normal mode 0 */ - GmacDuplex = 0x00000800, + GmacDuplex = 0x00000800, GmacFullDuplex = 0x00000800, /* (DM)Full duplex mode 11 RW */ GmacHalfDuplex = 0x00000000, /* Half duplex mode 0 */ - GmacRxIpcOffload = 0x00000400, /*IPC checksum offload 10 RW 0 */ + GmacRxIpcOffload = 0x00000400, /*IPC checksum offload 10 RW 0 */ - GmacRetry = 0x00000200, + GmacRetry = 0x00000200, GmacRetryDisable = 0x00000200, /* (DR)Disable Retry 9 RW */ GmacRetryEnable = 0x00000000, /* Enable retransmission as per BL 0 */ - GmacLinkUp = 0x00000100, /* (LUD)Link UP 8 RW */ - GmacLinkDown = 0x00000100, /* Link Down 0 */ - - GmacPadCrcStrip = 0x00000080, + GmacLinkUp = 0x00000100, /* (LUD)Link UP 8 RW */ + GmacLinkDown = 0x00000100, /* Link Down 0 */ + + GmacPadCrcStrip = 0x00000080, GmacPadCrcStripEnable = 0x00000080, /* (ACS) Automatic Pad/Crc strip enable 7 RW */ GmacPadCrcStripDisable = 0x00000000, /* Automatic Pad/Crc stripping disable 0 */ - - GmacBackoffLimit = 0x00000060, + + GmacBackoffLimit = 0x00000060, GmacBackoffLimit3 = 0x00000060, /* (BL)Back-off limit in HD mode 6:5 RW */ GmacBackoffLimit2 = 0x00000040, /* */ GmacBackoffLimit1 = 0x00000020, /* */ GmacBackoffLimit0 = 0x00000000, /* 00 */ - GmacDeferralCheck = 0x00000010, + GmacDeferralCheck = 0x00000010, GmacDeferralCheckEnable = 0x00000010, /* (DC)Deferral check enable in HD mode 4 RW */ GmacDeferralCheckDisable = 0x00000000, /* Deferral check disable 0 */ - - GmacTx = 0x00000008, + + GmacTx = 0x00000008, GmacTxEnable = 0x00000008, /* (TE)Transmitter enable 3 RW */ GmacTxDisable = 0x00000000, /* Transmitter disable 0 */ - GmacRx = 0x00000004, + GmacRx = 0x00000004, GmacRxEnable = 0x00000004, /* (RE)Receiver enable 2 RW */ GmacRxDisable = 0x00000000, /* Receiver disable 0 */ }; /* GmacFrameFilter = 0x0004, Mac frame filtering controls Register Layout*/ -enum GmacFrameFilterReg +enum GmacFrameFilterReg { - GmacFilter = 0x80000000, + GmacFilter = 0x80000000, GmacFilterOff = 0x80000000, /* (RA)Receive all incoming packets 31 RW */ GmacFilterOn = 0x00000000, /* Receive filtered packets only 0 */ - GmacHashPerfectFilter = 0x00000400, /*Hash or Perfect Filter enable 10 RW 0 */ + GmacHashPerfectFilter = 0x00000400, /*Hash or Perfect Filter enable 10 RW 0 */ - GmacSrcAddrFilter = 0x00000200, + GmacSrcAddrFilter = 0x00000200, GmacSrcAddrFilterEnable = 0x00000200, /* (SAF)Source Address Filter enable 9 RW */ GmacSrcAddrFilterDisable = 0x00000000, /* 0 */ @@ -469,13 +469,13 @@ enum GmacFrameFilterReg GmacSrcInvAddrFilterEn = 0x00000100, /* (SAIF)Inv Src Addr Filter enable 8 RW */ GmacSrcInvAddrFilterDis = 0x00000000, /* 0 */ - GmacPassControl = 0x000000C0, + GmacPassControl = 0x000000C0, GmacPassControl3 = 0x000000C0, /* (PCS)Forwards ctrl frms that pass AF 7:6 RW */ GmacPassControl2 = 0x00000080, /* Forwards all control frames */ GmacPassControl1 = 0x00000040, /* Does not pass control frames */ GmacPassControl0 = 0x00000000, /* Does not pass control frames 00 */ - GmacBroadcast = 0x00000020, + GmacBroadcast = 0x00000020, GmacBroadcastDisable = 0x00000020, /* (DBF)Disable Rx of broadcast frames 5 RW */ GmacBroadcastEnable = 0x00000000, /* Enable broadcast frames 0 */ @@ -500,17 +500,17 @@ enum GmacFrameFilterReg GmacPromiscuousModeOff = 0x00000000, /* Receive filtered packets only 0 */ }; - + /*GmacGmiiAddr = 0x0010, GMII address Register(ext. Phy) Layout */ -enum GmacGmiiAddrReg +enum GmacGmiiAddrReg { GmiiDevMask = 0x0000F800, /* (PA)GMII device address 15:11 RW 0x00 */ GmiiDevShift = 11, GmiiRegMask = 0x000007C0, /* (GR)GMII register in selected Phy 10:6 RW 0x00 */ GmiiRegShift = 6, - - GmiiCsrClkMask = 0x0000001C, /*CSR Clock bit Mask 4:2 */ + + GmiiCsrClkMask = 0x0000001C, /*CSR Clock bit Mask 4:2 */ GmiiCsrClk5 = 0x00000014, /* (CR)CSR Clock Range 250-300 MHz 4:2 RW 000 */ GmiiCsrClk4 = 0x00000010, /* 150-250 MHz */ GmiiCsrClk3 = 0x0000000C, /* 35-60 MHz */ @@ -525,19 +525,19 @@ enum GmacGmiiAddrReg }; /* GmacGmiiData = 0x0014, GMII data Register(ext. Phy) Layout */ -enum GmacGmiiDataReg +enum GmacGmiiDataReg { GmiiDataMask = 0x0000FFFF, /* (GD)GMII Data 15:0 RW 0x0000 */ }; /*GmacFlowControl = 0x0018, Flow control Register Layout */ -enum GmacFlowControlReg -{ +enum GmacFlowControlReg +{ GmacPauseTimeMask = 0xFFFF0000, /* (PT) PAUSE TIME field in the control frame 31:16 RW 0x0000 */ GmacPauseTimeShift = 16, - - GmacPauseLowThresh = 0x00000030, + + GmacPauseLowThresh = 0x00000030, GmacPauseLowThresh3 = 0x00000030, /* (PLT)thresh for pause tmr 256 slot time 5:4 RW */ GmacPauseLowThresh2 = 0x00000020, /* 144 slot time */ GmacPauseLowThresh1 = 0x00000010, /* 28 slot time */ @@ -547,11 +547,11 @@ enum GmacFlowControlReg GmacUnicastPauseFrameOn = 0x00000008, /* (UP)Detect pause frame with unicast addr. 3 RW */ GmacUnicastPauseFrameOff = 0x00000000, /* Detect only pause frame with multicast addr. 0 */ - GmacRxFlowControl = 0x00000004, + GmacRxFlowControl = 0x00000004, GmacRxFlowControlEnable = 0x00000004, /* (RFE)Enable Rx flow control 2 RW */ GmacRxFlowControlDisable = 0x00000000, /* Disable Rx flow control 0 */ - GmacTxFlowControl = 0x00000002, + GmacTxFlowControl = 0x00000002, GmacTxFlowControlEnable = 0x00000002, /* (TFE)Enable Tx flow control 1 RW */ GmacTxFlowControlDisable = 0x00000000, /* Disable flow control 0 */ @@ -559,29 +559,29 @@ enum GmacFlowControlReg GmacSendPauseFrame = 0x00000001, /* (FCB/PBA)send pause frm/Apply back pressure 0 RW 0 */ }; -/* GmacInterruptStatus = 0x0038, Mac Interrupt ststus register */ +/* GmacInterruptStatus = 0x0038, Mac Interrupt ststus register */ enum GmacInterruptStatusBitDefinition { - GmacTSIntSts = 0x00000200, /* set if int generated due to TS (Read Time Stamp Status Register to know details)*/ - GmacMmcRxChksumOffload = 0x00000080, /* set if int generated in MMC RX CHECKSUM OFFLOAD int register */ - GmacMmcTxIntSts = 0x00000040, /* set if int generated in MMC TX Int register */ - GmacMmcRxIntSts = 0x00000020, /* set if int generated in MMC RX Int register */ - GmacMmcIntSts = 0x00000010, /* set if any of the above bit [7:5] is set */ - GmacPmtIntSts = 0x00000008, /* set whenver magic pkt/wake-on-lan frame is received */ - GmacPcsAnComplete = 0x00000004, /* set when AN is complete in TBI/RTBI/SGMIII phy interface */ - GmacPcsLnkStsChange = 0x00000002, /* set if any lnk status change in TBI/RTBI/SGMII interface */ - GmacRgmiiIntSts = 0x00000001, /* set if any change in lnk status of RGMII interface */ + GmacTSIntSts = 0x00000200, /* set if int generated due to TS (Read Time Stamp Status Register to know details)*/ + GmacMmcRxChksumOffload = 0x00000080, /* set if int generated in MMC RX CHECKSUM OFFLOAD int register */ + GmacMmcTxIntSts = 0x00000040, /* set if int generated in MMC TX Int register */ + GmacMmcRxIntSts = 0x00000020, /* set if int generated in MMC RX Int register */ + GmacMmcIntSts = 0x00000010, /* set if any of the above bit [7:5] is set */ + GmacPmtIntSts = 0x00000008, /* set whenver magic pkt/wake-on-lan frame is received */ + GmacPcsAnComplete = 0x00000004, /* set when AN is complete in TBI/RTBI/SGMIII phy interface */ + GmacPcsLnkStsChange = 0x00000002, /* set if any lnk status change in TBI/RTBI/SGMII interface */ + GmacRgmiiIntSts = 0x00000001, /* set if any change in lnk status of RGMII interface */ }; -/* GmacInterruptMask = 0x003C, Mac Interrupt Mask register */ +/* GmacInterruptMask = 0x003C, Mac Interrupt Mask register */ enum GmacInterruptMaskBitDefinition { - GmacTSIntMask = 0x00000200, /* when set disables the time stamp interrupt generation */ - GmacPmtIntMask = 0x00000008, /* when set Disables the assertion of PMT interrupt */ - GmacPcsAnIntMask = 0x00000004, /* When set disables the assertion of PCS AN complete interrupt */ - GmacPcsLnkStsIntMask = 0x00000002, /* when set disables the assertion of PCS lnk status change interrupt */ - GmacRgmiiIntMask = 0x00000001, /* when set disables the assertion of RGMII int */ + GmacTSIntMask = 0x00000200, /* when set disables the time stamp interrupt generation */ + GmacPmtIntMask = 0x00000008, /* when set Disables the assertion of PMT interrupt */ + GmacPcsAnIntMask = 0x00000004, /* When set disables the assertion of PCS AN complete interrupt */ + GmacPcsLnkStsIntMask = 0x00000002, /* when set disables the assertion of PCS lnk status change interrupt */ + GmacRgmiiIntMask = 0x00000001, /* when set disables the assertion of RGMII int */ }; /********************************************************** @@ -590,7 +590,7 @@ enum GmacInterruptMaskBitDefinition * For any other system translation is done accordingly **********************************************************/ -enum DmaRegisters +enum DmaRegisters { DmaBusMode = 0x0000, /* CSR0 - Bus Mode Register */ DmaTxPollDemand = 0x0004, /* CSR1 - Transmit Poll Demand Register */ @@ -601,8 +601,8 @@ enum DmaRegisters DmaControl = 0x0018, /* CSR6 - Dma Operation Mode Register */ DmaInterrupt = 0x001C, /* CSR7 - Interrupt enable */ DmaMissedFr = 0x0020, /* CSR8 - Missed Frame & Buffer overflow Counter */ - DmaTxCurrDesc = 0x0048, /* - Current host Tx Desc Register */ - DmaRxCurrDesc = 0x004C, /* - Current host Rx Desc Register */ + DmaTxCurrDesc = 0x0048, /* - Current host Tx Desc Register */ + DmaRxCurrDesc = 0x004C, /* - Current host Rx Desc Register */ DmaTxCurrAddr = 0x0050, /* CSR20 - Current host transmit buffer address */ DmaRxCurrAddr = 0x0054, /* CSR21 - Current host receive buffer address */ }; @@ -612,19 +612,19 @@ enum DmaRegisters **********************************************************/ /*DmaBusMode = 0x0000, CSR0 - Bus Mode */ -enum DmaBusModeReg +enum DmaBusModeReg { /* Bit description Bits R/W Reset value */ DmaFixedBurstEnable = 0x00010000, /* (FB)Fixed Burst SINGLE, INCR4, INCR8 or INCR16 16 RW */ DmaFixedBurstDisable = 0x00000000, /* SINGLE, INCR 0 */ - DmaTxPriorityRatio11 = 0x00000000, /* (PR)TX:RX DMA priority ratio 1:1 15:14 RW 00 */ - DmaTxPriorityRatio21 = 0x00004000, /* (PR)TX:RX DMA priority ratio 2:1 */ - DmaTxPriorityRatio31 = 0x00008000, /* (PR)TX:RX DMA priority ratio 3:1 */ - DmaTxPriorityRatio41 = 0x0000C000, /* (PR)TX:RX DMA priority ratio 4:1 */ - - DmaBurstLengthx8 = 0x01000000, /* When set mutiplies the PBL by 8 24 RW 0 */ - - DmaBurstLength256 = 0x01002000, /*(DmaBurstLengthx8 | DmaBurstLength32) = 256 [24]:13:8 */ + DmaTxPriorityRatio11 = 0x00000000, /* (PR)TX:RX DMA priority ratio 1:1 15:14 RW 00 */ + DmaTxPriorityRatio21 = 0x00004000, /* (PR)TX:RX DMA priority ratio 2:1 */ + DmaTxPriorityRatio31 = 0x00008000, /* (PR)TX:RX DMA priority ratio 3:1 */ + DmaTxPriorityRatio41 = 0x0000C000, /* (PR)TX:RX DMA priority ratio 4:1 */ + + DmaBurstLengthx8 = 0x01000000, /* When set mutiplies the PBL by 8 24 RW 0 */ + + DmaBurstLength256 = 0x01002000, /*(DmaBurstLengthx8 | DmaBurstLength32) = 256 [24]:13:8 */ DmaBurstLength128 = 0x01001000, /*(DmaBurstLengthx8 | DmaBurstLength16) = 128 [24]:13:8 */ DmaBurstLength64 = 0x01000800, /*(DmaBurstLengthx8 | DmaBurstLength8) = 64 [24]:13:8 */ DmaBurstLength32 = 0x00002000, /* (PBL) programmable Dma burst length = 32 13:8 RW */ @@ -645,20 +645,20 @@ enum DmaBusModeReg DmaDescriptorSkip1 = 0x00000004, /* */ DmaDescriptorSkip0 = 0x00000000, /* 0x00 */ - DmaArbitRr = 0x00000000, /* (DA) DMA RR arbitration 1 RW 0 */ - DmaArbitPr = 0x00000002, /* Rx has priority over Tx */ - + DmaArbitRr = 0x00000000, /* (DA) DMA RR arbitration 1 RW 0 */ + DmaArbitPr = 0x00000002, /* Rx has priority over Tx */ + DmaResetOn = 0x00000001, /* (SWR)Software Reset DMA engine 0 RW */ DmaResetOff = 0x00000000, /* 0 */ }; /*DmaStatus = 0x0014, CSR5 - Dma status Register */ -enum DmaStatusReg -{ - /*Bit 28 27 and 26 indicate whether the interrupt due to PMT GMACMMC or GMAC LINE Remaining bits are DMA interrupts*/ - GmacPmtIntr = 0x10000000, /* (GPI)Gmac subsystem interrupt 28 RO 0 */ - GmacMmcIntr = 0x08000000, /* (GMI)Gmac MMC subsystem interrupt 27 RO 0 */ +enum DmaStatusReg +{ + /*Bit 28 27 and 26 indicate whether the interrupt due to PMT GMACMMC or GMAC LINE Remaining bits are DMA interrupts*/ + GmacPmtIntr = 0x10000000, /* (GPI)Gmac subsystem interrupt 28 RO 0 */ + GmacMmcIntr = 0x08000000, /* (GMI)Gmac MMC subsystem interrupt 27 RO 0 */ GmacLineIntfIntr = 0x04000000, /* Line interface interrupt 26 RO 0 */ DmaErrorBit2 = 0x02000000, /* (EB)Error bits 0-data buffer, 1-desc. access 25 RO 0 */ @@ -700,52 +700,52 @@ enum DmaStatusReg }; /*DmaControl = 0x0018, CSR6 - Dma Operation Mode Register */ -enum DmaControlReg -{ - DmaDisableDropTcpCs = 0x04000000, /* (DT) Dis. drop. of tcp/ip CS error frames 26 RW 0 */ - +enum DmaControlReg +{ + DmaDisableDropTcpCs = 0x04000000, /* (DT) Dis. drop. of tcp/ip CS error frames 26 RW 0 */ + DmaStoreAndForward = 0x02200000, /* (SF)Store and forward 21 RW 0 */ - DmaFlushTxFifo = 0x00100000, /* (FTF)Tx FIFO controller is reset to default 20 RW 0 */ - - DmaTxThreshCtrl = 0x0001C000, /* (TTC)Controls thre Threh of MTL tx Fifo 16:14 RW */ - DmaTxThreshCtrl16 = 0x0001C000, /* (TTC)Controls thre Threh of MTL tx Fifo 16 16:14 RW */ - DmaTxThreshCtrl24 = 0x00018000, /* (TTC)Controls thre Threh of MTL tx Fifo 24 16:14 RW */ - DmaTxThreshCtrl32 = 0x00014000, /* (TTC)Controls thre Threh of MTL tx Fifo 32 16:14 RW */ - DmaTxThreshCtrl40 = 0x00010000, /* (TTC)Controls thre Threh of MTL tx Fifo 40 16:14 RW */ - DmaTxThreshCtrl256 = 0x0000c000, /* (TTC)Controls thre Threh of MTL tx Fifo 256 16:14 RW */ - DmaTxThreshCtrl192 = 0x00008000, /* (TTC)Controls thre Threh of MTL tx Fifo 192 16:14 RW */ - DmaTxThreshCtrl128 = 0x00004000, /* (TTC)Controls thre Threh of MTL tx Fifo 128 16:14 RW */ - DmaTxThreshCtrl64 = 0x00000000, /* (TTC)Controls thre Threh of MTL tx Fifo 64 16:14 RW 000 */ - + DmaFlushTxFifo = 0x00100000, /* (FTF)Tx FIFO controller is reset to default 20 RW 0 */ + + DmaTxThreshCtrl = 0x0001C000, /* (TTC)Controls thre Threh of MTL tx Fifo 16:14 RW */ + DmaTxThreshCtrl16 = 0x0001C000, /* (TTC)Controls thre Threh of MTL tx Fifo 16 16:14 RW */ + DmaTxThreshCtrl24 = 0x00018000, /* (TTC)Controls thre Threh of MTL tx Fifo 24 16:14 RW */ + DmaTxThreshCtrl32 = 0x00014000, /* (TTC)Controls thre Threh of MTL tx Fifo 32 16:14 RW */ + DmaTxThreshCtrl40 = 0x00010000, /* (TTC)Controls thre Threh of MTL tx Fifo 40 16:14 RW */ + DmaTxThreshCtrl256 = 0x0000c000, /* (TTC)Controls thre Threh of MTL tx Fifo 256 16:14 RW */ + DmaTxThreshCtrl192 = 0x00008000, /* (TTC)Controls thre Threh of MTL tx Fifo 192 16:14 RW */ + DmaTxThreshCtrl128 = 0x00004000, /* (TTC)Controls thre Threh of MTL tx Fifo 128 16:14 RW */ + DmaTxThreshCtrl64 = 0x00000000, /* (TTC)Controls thre Threh of MTL tx Fifo 64 16:14 RW 000 */ + DmaTxStart = 0x00002000, /* (ST)Start/Stop transmission 13 RW 0 */ - DmaRxFlowCtrlDeact = 0x00401800, /* (RFD)Rx flow control deact. threhold [22]:12:11 RW */ - DmaRxFlowCtrlDeact1K = 0x00000000, /* (RFD)Rx flow control deact. threhold (1kbytes) [22]:12:11 RW 00 */ - DmaRxFlowCtrlDeact2K = 0x00000800, /* (RFD)Rx flow control deact. threhold (2kbytes) [22]:12:11 RW */ - DmaRxFlowCtrlDeact3K = 0x00001000, /* (RFD)Rx flow control deact. threhold (3kbytes) [22]:12:11 RW */ - DmaRxFlowCtrlDeact4K = 0x00001800, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ - DmaRxFlowCtrlDeact5K = 0x00400000, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ - DmaRxFlowCtrlDeact6K = 0x00400800, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ - DmaRxFlowCtrlDeact7K = 0x00401000, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ - - DmaRxFlowCtrlAct = 0x00800600, /* (RFA)Rx flow control Act. threhold [23]:10:09 RW */ - DmaRxFlowCtrlAct1K = 0x00000000, /* (RFA)Rx flow control Act. threhold (1kbytes) [23]:10:09 RW 00 */ - DmaRxFlowCtrlAct2K = 0x00000200, /* (RFA)Rx flow control Act. threhold (2kbytes) [23]:10:09 RW */ - DmaRxFlowCtrlAct3K = 0x00000400, /* (RFA)Rx flow control Act. threhold (3kbytes) [23]:10:09 RW */ - DmaRxFlowCtrlAct4K = 0x00000300, /* (RFA)Rx flow control Act. threhold (4kbytes) [23]:10:09 RW */ - DmaRxFlowCtrlAct5K = 0x00800000, /* (RFA)Rx flow control Act. threhold (5kbytes) [23]:10:09 RW */ - DmaRxFlowCtrlAct6K = 0x00800200, /* (RFA)Rx flow control Act. threhold (6kbytes) [23]:10:09 RW */ - DmaRxFlowCtrlAct7K = 0x00800400, /* (RFA)Rx flow control Act. threhold (7kbytes) [23]:10:09 RW */ - - DmaRxThreshCtrl = 0x00000018, /* (RTC)Controls thre Threh of MTL rx Fifo 4:3 RW */ - DmaRxThreshCtrl64 = 0x00000000, /* (RTC)Controls thre Threh of MTL tx Fifo 64 4:3 RW */ - DmaRxThreshCtrl32 = 0x00000008, /* (RTC)Controls thre Threh of MTL tx Fifo 32 4:3 RW */ - DmaRxThreshCtrl96 = 0x00000010, /* (RTC)Controls thre Threh of MTL tx Fifo 96 4:3 RW */ - DmaRxThreshCtrl128 = 0x00000018, /* (RTC)Controls thre Threh of MTL tx Fifo 128 4:3 RW */ - - DmaEnHwFlowCtrl = 0x00000100, /* (EFC)Enable HW flow control 8 RW */ - DmaDisHwFlowCtrl = 0x00000000, /* Disable HW flow control 0 */ - + DmaRxFlowCtrlDeact = 0x00401800, /* (RFD)Rx flow control deact. threhold [22]:12:11 RW */ + DmaRxFlowCtrlDeact1K = 0x00000000, /* (RFD)Rx flow control deact. threhold (1kbytes) [22]:12:11 RW 00 */ + DmaRxFlowCtrlDeact2K = 0x00000800, /* (RFD)Rx flow control deact. threhold (2kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact3K = 0x00001000, /* (RFD)Rx flow control deact. threhold (3kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact4K = 0x00001800, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact5K = 0x00400000, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact6K = 0x00400800, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact7K = 0x00401000, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ + + DmaRxFlowCtrlAct = 0x00800600, /* (RFA)Rx flow control Act. threhold [23]:10:09 RW */ + DmaRxFlowCtrlAct1K = 0x00000000, /* (RFA)Rx flow control Act. threhold (1kbytes) [23]:10:09 RW 00 */ + DmaRxFlowCtrlAct2K = 0x00000200, /* (RFA)Rx flow control Act. threhold (2kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct3K = 0x00000400, /* (RFA)Rx flow control Act. threhold (3kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct4K = 0x00000300, /* (RFA)Rx flow control Act. threhold (4kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct5K = 0x00800000, /* (RFA)Rx flow control Act. threhold (5kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct6K = 0x00800200, /* (RFA)Rx flow control Act. threhold (6kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct7K = 0x00800400, /* (RFA)Rx flow control Act. threhold (7kbytes) [23]:10:09 RW */ + + DmaRxThreshCtrl = 0x00000018, /* (RTC)Controls thre Threh of MTL rx Fifo 4:3 RW */ + DmaRxThreshCtrl64 = 0x00000000, /* (RTC)Controls thre Threh of MTL tx Fifo 64 4:3 RW */ + DmaRxThreshCtrl32 = 0x00000008, /* (RTC)Controls thre Threh of MTL tx Fifo 32 4:3 RW */ + DmaRxThreshCtrl96 = 0x00000010, /* (RTC)Controls thre Threh of MTL tx Fifo 96 4:3 RW */ + DmaRxThreshCtrl128 = 0x00000018, /* (RTC)Controls thre Threh of MTL tx Fifo 128 4:3 RW */ + + DmaEnHwFlowCtrl = 0x00000100, /* (EFC)Enable HW flow control 8 RW */ + DmaDisHwFlowCtrl = 0x00000000, /* Disable HW flow control 0 */ + DmaFwdErrorFrames = 0x00000080, /* (FEF)Forward error frames 7 RW 0 */ DmaFwdUnderSzFrames = 0x00000040, /* (FUF)Forward undersize frames 6 RW 0 */ DmaTxSecondFrame = 0x00000004, /* (OSF)Operate on second frame 4 RW 0 */ @@ -755,7 +755,7 @@ enum DmaControlReg /*DmaInterrupt = 0x001C, CSR7 - Interrupt enable Register Layout */ enum DmaInterruptReg -{ +{ DmaIeNormal = DmaIntNormal , /* Normal interrupt enable RW 0 */ DmaIeAbnormal = DmaIntAbnormal , /* Abnormal interrupt enable RW 0 */ @@ -783,34 +783,34 @@ enum DmaInterruptReg #ifdef ENH_DESC /* **********Enhanced Descritpor structure to support 8K buffer per buffer **************************** - -DmaRxBaseAddr = 0x000C, CSR3 - Receive Descriptor list base address + +DmaRxBaseAddr = 0x000C, CSR3 - Receive Descriptor list base address DmaRxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format in Little endian with a -32 bit Data bus is as shown below +32 bit Data bus is as shown below -Similarly +Similarly DmaTxBaseAddr = 0x0010, CSR4 - Transmit Descriptor list base address DmaTxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format in Little endian with a 32 bit Data bus is as shown below -------------------------------------------------------------------------- - RDES0 |OWN (31)| Status | - -------------------------------------------------------------------------- - RDES1 | Ctrl | Res | Byte Count Buffer 2 | Ctrl | Res | Byte Count Buffer 1 | - -------------------------------------------------------------------------- - RDES2 | Buffer 1 Address | - -------------------------------------------------------------------------- - RDES3 | Buffer 2 Address / Next Descriptor Address | - -------------------------------------------------------------------------- + RDES0 |OWN (31)| Status | + -------------------------------------------------------------------------- + RDES1 | Ctrl | Res | Byte Count Buffer 2 | Ctrl | Res | Byte Count Buffer 1 | + -------------------------------------------------------------------------- + RDES2 | Buffer 1 Address | + -------------------------------------------------------------------------- + RDES3 | Buffer 2 Address / Next Descriptor Address | + -------------------------------------------------------------------------- -------------------------------------------------------------------------- - TDES0 |OWN (31)| Ctrl | Res | Ctrl | Res | Status | - -------------------------------------------------------------------------- - TDES1 | Res | Byte Count Buffer 2 | Res | Byte Count Buffer 1 | - -------------------------------------------------------------------------- - TDES2 | Buffer 1 Address | - -------------------------------------------------------------------------- + TDES0 |OWN (31)| Ctrl | Res | Ctrl | Res | Status | + -------------------------------------------------------------------------- + TDES1 | Res | Byte Count Buffer 2 | Res | Byte Count Buffer 1 | + -------------------------------------------------------------------------- + TDES2 | Buffer 1 Address | + -------------------------------------------------------------------------- TDES3 | Buffer 2 Address / Next Descriptor Address | - -------------------------------------------------------------------------- + -------------------------------------------------------------------------- */ @@ -819,15 +819,15 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ DescOwnByDma = 0x80000000, /* (OWN)Descriptor is owned by DMA engine 31 RW */ DescDAFilterFail = 0x40000000, /* (AFM)Rx - DA Filter Fail for the rx frame 30 */ - + DescFrameLengthMask = 0x3FFF0000, /* (FL)Receive descriptor frame length 29:16 */ DescFrameLengthShift = 16, DescError = 0x00008000, /* (ES)Error summary bit - OR of the follo. bits: 15 */ - /* DE || OE || IPC || LC || RWT || RE || CE */ + /* DE || OE || IPC || LC || RWT || RE || CE */ DescRxTruncated = 0x00004000, /* (DE)Rx - no more descriptors for receive frame 14 */ DescSAFilterFail = 0x00002000, /* (SAF)Rx - SA Filter Fail for the received frame 13 */ - DescRxLengthError = 0x00001000, /* (LE)Rx - frm size not matching with len field 12 */ + DescRxLengthError = 0x00001000, /* (LE)Rx - frm size not matching with len field 12 */ DescRxDamaged = 0x00000800, /* (OE)Rx - frm was damaged due to buffer overflow 11 */ DescRxVLANTag = 0x00000400, /* (VLAN)Rx - received frame is a VLAN frame 10 */ DescRxFirst = 0x00000200, /* (FS)Rx - first descriptor of the frame 9 */ @@ -839,31 +839,31 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ DescRxMiiError = 0x00000008, /* (RE)Rx - error reported by MII interface 3 */ DescRxDribbling = 0x00000004, /* (DE)Rx - frame contains non int multiple of 8 bits 2 */ DescRxCrc = 0x00000002, /* (CE)Rx - CRC error 1 */ -// DescRxMacMatch = 0x00000001, /* (RX MAC Address) Rx mac address reg(1 to 15)match 0 */ +// DescRxMacMatch = 0x00000001, /* (RX MAC Address) Rx mac address reg(1 to 15)match 0 */ + + DescRxEXTsts = 0x00000001, /* Extended Status Available (RDES4) 0 */ - DescRxEXTsts = 0x00000001, /* Extended Status Available (RDES4) 0 */ - DescTxIntEnable = 0x40000000, /* (IC)Tx - interrupt on completion 30 */ DescTxLast = 0x20000000, /* (LS)Tx - Last segment of the frame 29 */ DescTxFirst = 0x10000000, /* (FS)Tx - First segment of the frame 28 */ DescTxDisableCrc = 0x08000000, /* (DC)Tx - Add CRC disabled (first segment only) 27 */ - DescTxDisablePadd = 0x04000000, /* (DP)disable padding, added by - reyaz 26 */ + DescTxDisablePadd = 0x04000000, /* (DP)disable padding, added by - reyaz 26 */ - DescTxCisMask = 0x00c00000, /* Tx checksum offloading control mask 23:22 */ - DescTxCisBypass = 0x00000000, /* Checksum bypass */ - DescTxCisIpv4HdrCs = 0x00400000, /* IPv4 header checksum */ - DescTxCisTcpOnlyCs = 0x00800000, /* TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present */ - DescTxCisTcpPseudoCs = 0x00c00000, /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */ + DescTxCisMask = 0x00c00000, /* Tx checksum offloading control mask 23:22 */ + DescTxCisBypass = 0x00000000, /* Checksum bypass */ + DescTxCisIpv4HdrCs = 0x00400000, /* IPv4 header checksum */ + DescTxCisTcpOnlyCs = 0x00800000, /* TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present */ + DescTxCisTcpPseudoCs = 0x00c00000, /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */ TxDescEndOfRing = 0x00200000, /* (TER)End of descriptors ring 21 */ TxDescChain = 0x00100000, /* (TCH)Second buffer address is chain address 20 */ - - DescRxChkBit0 = 0x00000001, /*() Rx - Rx Payload Checksum Error 0 */ - DescRxChkBit7 = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */ - DescRxChkBit5 = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ - - DescRxTSavail = 0x00000080, /* Time stamp available 7 */ - DescRxFrameType = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ + + DescRxChkBit0 = 0x00000001, /*() Rx - Rx Payload Checksum Error 0 */ + DescRxChkBit7 = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */ + DescRxChkBit5 = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ + + DescRxTSavail = 0x00000080, /* Time stamp available 7 */ + DescRxFrameType = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ DescTxIpv4ChkError = 0x00010000, /* (IHE) Tx Ip header error 16 */ DescTxTimeout = 0x00004000, /* (JT)Tx - Transmit jabber timeout 14 */ @@ -874,25 +874,25 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ DescTxLateCollision = 0x00000200, /* (LC)Tx - transmission aborted due to collision 9 */ DescTxExcCollisions = 0x00000100, /* (EC)Tx - transmission aborted after 16 collisions 8 */ DescTxVLANFrame = 0x00000080, /* (VF)Tx - VLAN-type frame 7 */ - + DescTxCollMask = 0x00000078, /* (CC)Tx - Collision count 6:3 */ DescTxCollShift = 3, - + DescTxExcDeferral = 0x00000004, /* (ED)Tx - excessive deferral 2 */ DescTxUnderflow = 0x00000002, /* (UF)Tx - late data arrival from the memory 1 */ DescTxDeferred = 0x00000001, /* (DB)Tx - frame transmision deferred 0 */ - /* - This explains the RDES1/TDES1 bits layout - -------------------------------------------------------------------- - RDES1/TDES1 | Control Bits | Byte Count Buffer 2 | Byte Count Buffer 1 | - -------------------------------------------------------------------- + /* + This explains the RDES1/TDES1 bits layout + -------------------------------------------------------------------- + RDES1/TDES1 | Control Bits | Byte Count Buffer 2 | Byte Count Buffer 1 | + -------------------------------------------------------------------- - */ -// DmaDescriptorLength length word of DMA descriptor + */ +// DmaDescriptorLength length word of DMA descriptor - RxDisIntCompl = 0x80000000, /* (Disable Rx int on completion) 31 */ + RxDisIntCompl = 0x80000000, /* (Disable Rx int on completion) 31 */ RxDescEndOfRing = 0x00008000, /* (TER)End of descriptors ring 15 */ RxDescChain = 0x00004000, /* (TCH)Second buffer address is chain address 14 */ @@ -903,12 +903,12 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ DescSize1Shift = 0, - /* - This explains the RDES4 Extended Status bits layout - -------------------------------------------------------------------- - RDES4 | Extended Status | - -------------------------------------------------------------------- - */ + /* + This explains the RDES4 Extended Status bits layout + -------------------------------------------------------------------- + RDES4 | Extended Status | + -------------------------------------------------------------------- + */ DescRxPtpAvail = 0x00004000, /* PTP snapshot available 14 */ DescRxPtpVer = 0x00002000, /* When set indicates IEEE1584 Version 2 (else Ver1) 13 */ DescRxPtpFrameType = 0x00001000, /* PTP frame type Indicates PTP sent over ethernet 12 */ @@ -923,12 +923,12 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ DescRxPtpPdelayRespFP = 0x00000700, /* 0111 => Pdealy_Resp_Follow_Up (in P to P trans clk) or Signaling in Ord and Bound clk */ DescRxPtpIPV6 = 0x00000080, /* Received Packet is in IPV6 Packet 7 */ DescRxPtpIPV4 = 0x00000040, /* Received Packet is in IPV4 Packet 6 */ - + DescRxChkSumBypass = 0x00000020, /* When set indicates checksum offload engine 5 is bypassed */ DescRxIpPayloadError = 0x00000010, /* When set indicates 16bit IP payload CS is in error 4 */ DescRxIpHeaderError = 0x00000008, /* When set indicates 16bit IPV4 header CS is in 3 - error or IP datagram version is not consistent + error or IP datagram version is not consistent with Ethernet type value */ DescRxIpPayloadType = 0x00000007, /* Indicate the type of payload encapsulated 2:0 in IPdatagram processed by COE (Rx) */ @@ -943,38 +943,38 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ /* ********** Default Descritpor structure **************************** -DmaRxBaseAddr = 0x000C, CSR3 - Receive Descriptor list base address +DmaRxBaseAddr = 0x000C, CSR3 - Receive Descriptor list base address DmaRxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format in Little endian with a -32 bit Data bus is as shown below +32 bit Data bus is as shown below -Similarly +Similarly DmaTxBaseAddr = 0x0010, CSR4 - Transmit Descriptor list base address DmaTxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format in Little endian with a 32 bit Data bus is as shown below -------------------------------------------------------------------- RDES0/TDES0 |OWN (31)| Status | - -------------------------------------------------------------------- + -------------------------------------------------------------------- RDES1/TDES1 | Control Bits | Byte Count Buffer 2 | Byte Count Buffer 1 | - -------------------------------------------------------------------- + -------------------------------------------------------------------- RDES2/TDES2 | Buffer 1 Address | - -------------------------------------------------------------------- + -------------------------------------------------------------------- RDES3/TDES3 | Buffer 2 Address / Next Descriptor Address | - -------------------------------------------------------------------- + -------------------------------------------------------------------- */ enum DmaDescriptorStatus /* status word of DMA descriptor */ { DescOwnByDma = 0x80000000, /* (OWN)Descriptor is owned by DMA engine 31 RW */ DescDAFilterFail = 0x40000000, /* (AFM)Rx - DA Filter Fail for the rx frame 30 */ - + DescFrameLengthMask = 0x3FFF0000, /* (FL)Receive descriptor frame length 29:16 */ DescFrameLengthShift = 16, DescError = 0x00008000, /* (ES)Error summary bit - OR of the follo. bits: 15 */ - /* DE || OE || IPC || LC || RWT || RE || CE */ + /* DE || OE || IPC || LC || RWT || RE || CE */ DescRxTruncated = 0x00004000, /* (DE)Rx - no more descriptors for receive frame 14 */ DescSAFilterFail = 0x00002000, /* (SAF)Rx - SA Filter Fail for the received frame 13 */ - DescRxLengthError = 0x00001000, /* (LE)Rx - frm size not matching with len field 12 */ + DescRxLengthError = 0x00001000, /* (LE)Rx - frm size not matching with len field 12 */ DescRxDamaged = 0x00000800, /* (OE)Rx - frm was damaged due to buffer overflow 11 */ DescRxVLANTag = 0x00000400, /* (VLAN)Rx - received frame is a VLAN frame 10 */ DescRxFirst = 0x00000200, /* (FS)Rx - first descriptor of the frame 9 */ @@ -986,16 +986,16 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ DescRxMiiError = 0x00000008, /* (RE)Rx - error reported by MII interface 3 */ DescRxDribbling = 0x00000004, /* (DE)Rx - frame contains non int multiple of 8 bits 2 */ DescRxCrc = 0x00000002, /* (CE)Rx - CRC error 1 */ - DescRxMacMatch = 0x00000001, /* (RX MAC Address) Rx mac address reg(1 to 15)match 0 */ + DescRxMacMatch = 0x00000001, /* (RX MAC Address) Rx mac address reg(1 to 15)match 0 */ //Rx Descriptor Checksum Offload engine (type 2) encoding - //DescRxPayChkError = 0x00000001, /* () Rx - Rx Payload Checksum Error 0 */ + //DescRxPayChkError = 0x00000001, /* () Rx - Rx Payload Checksum Error 0 */ //DescRxIpv4ChkError = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */ - - DescRxChkBit0 = 0x00000001, /*() Rx - Rx Payload Checksum Error 0 */ - DescRxChkBit7 = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */ - DescRxChkBit5 = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ - + + DescRxChkBit0 = 0x00000001, /*() Rx - Rx Payload Checksum Error 0 */ + DescRxChkBit7 = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */ + DescRxChkBit5 = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ + DescTxIpv4ChkError = 0x00010000, /* (IHE) Tx Ip header error 16 */ DescTxTimeout = 0x00004000, /* (JT)Tx - Transmit jabber timeout 14 */ DescTxFrameFlushed = 0x00002000, /* (FF)Tx - DMA/MTL flushed the frame due to SW flush 13 */ @@ -1005,21 +1005,21 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ DescTxLateCollision = 0x00000200, /* (LC)Tx - transmission aborted due to collision 9 */ DescTxExcCollisions = 0x00000100, /* (EC)Tx - transmission aborted after 16 collisions 8 */ DescTxVLANFrame = 0x00000080, /* (VF)Tx - VLAN-type frame 7 */ - + DescTxCollMask = 0x00000078, /* (CC)Tx - Collision count 6:3 */ DescTxCollShift = 3, - + DescTxExcDeferral = 0x00000004, /* (ED)Tx - excessive deferral 2 */ DescTxUnderflow = 0x00000002, /* (UF)Tx - late data arrival from the memory 1 */ DescTxDeferred = 0x00000001, /* (DB)Tx - frame transmision deferred 0 */ - - /* - This explains the RDES1/TDES1 bits layout - -------------------------------------------------------------------- - RDES1/TDES1 | Control Bits | Byte Count Buffer 2 | Byte Count Buffer 1 | - -------------------------------------------------------------------- - - */ + + /* + This explains the RDES1/TDES1 bits layout + -------------------------------------------------------------------- + RDES1/TDES1 | Control Bits | Byte Count Buffer 2 | Byte Count Buffer 1 | + -------------------------------------------------------------------- + + */ //DmaDescriptorLength length word of DMA descriptor DescTxIntEnable = 0x80000000, /* (IC)Tx - interrupt on completion 31 */ @@ -1027,46 +1027,46 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ DescTxFirst = 0x20000000, /* (FS)Tx - First segment of the frame 29 */ DescTxDisableCrc = 0x04000000, /* (DC)Tx - Add CRC disabled (first segment only) 26 */ - RxDisIntCompl = 0x80000000, /* (Disable Rx int on completion) 31 */ + RxDisIntCompl = 0x80000000, /* (Disable Rx int on completion) 31 */ RxDescEndOfRing = 0x02000000, /* (TER)End of descriptors ring */ RxDescChain = 0x01000000, /* (TCH)Second buffer address is chain address 24 */ - - DescTxDisablePadd = 0x00800000, /* (DP)disable padding, added by - reyaz 23 */ + + DescTxDisablePadd = 0x00800000, /* (DP)disable padding, added by - reyaz 23 */ TxDescEndOfRing = 0x02000000, /* (TER)End of descriptors ring */ TxDescChain = 0x01000000, /* (TCH)Second buffer address is chain address 24 */ - + DescSize2Mask = 0x003FF800, /* (TBS2) Buffer 2 size 21:11 */ DescSize2Shift = 11, DescSize1Mask = 0x000007FF, /* (TBS1) Buffer 1 size 10:0 */ DescSize1Shift = 0, - DescTxCisMask = 0x18000000, /* Tx checksum offloading control mask 28:27 */ - DescTxCisBypass = 0x00000000, /* Checksum bypass */ - DescTxCisIpv4HdrCs = 0x08000000, /* IPv4 header checksum */ - DescTxCisTcpOnlyCs = 0x10000000, /* TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present */ - DescTxCisTcpPseudoCs = 0x18000000, /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */ + DescTxCisMask = 0x18000000, /* Tx checksum offloading control mask 28:27 */ + DescTxCisBypass = 0x00000000, /* Checksum bypass */ + DescTxCisIpv4HdrCs = 0x08000000, /* IPv4 header checksum */ + DescTxCisTcpOnlyCs = 0x10000000, /* TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present */ + DescTxCisTcpPseudoCs = 0x18000000, /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */ }; #endif // Rx Descriptor COE type2 encoding enum RxDescCOEEncode { - RxLenLT600 = 0, /* Bit(5:7:0)=>0 IEEE 802.3 type frame Length field is Lessthan 0x0600 */ - RxIpHdrPayLoadChkBypass = 1, /* Bit(5:7:0)=>1 Payload & Ip header checksum bypassed (unsuppported payload) */ - RxIpHdrPayLoadRes = 2, /* Bit(5:7:0)=>2 Reserved */ - RxChkBypass = 3, /* Bit(5:7:0)=>3 Neither IPv4 nor IPV6. So checksum bypassed */ - RxNoChkError = 4, /* Bit(5:7:0)=>4 No IPv4/IPv6 Checksum error detected */ - RxPayLoadChkError = 5, /* Bit(5:7:0)=>5 Payload checksum error detected for Ipv4/Ipv6 frames */ - RxIpHdrChkError = 6, /* Bit(5:7:0)=>6 Ip header checksum error detected for Ipv4 frames */ - RxIpHdrPayLoadChkError = 7, /* Bit(5:7:0)=>7 Payload & Ip header checksum error detected for Ipv4/Ipv6 frames */ + RxLenLT600 = 0, /* Bit(5:7:0)=>0 IEEE 802.3 type frame Length field is Lessthan 0x0600 */ + RxIpHdrPayLoadChkBypass = 1, /* Bit(5:7:0)=>1 Payload & Ip header checksum bypassed (unsuppported payload) */ + RxIpHdrPayLoadRes = 2, /* Bit(5:7:0)=>2 Reserved */ + RxChkBypass = 3, /* Bit(5:7:0)=>3 Neither IPv4 nor IPV6. So checksum bypassed */ + RxNoChkError = 4, /* Bit(5:7:0)=>4 No IPv4/IPv6 Checksum error detected */ + RxPayLoadChkError = 5, /* Bit(5:7:0)=>5 Payload checksum error detected for Ipv4/Ipv6 frames */ + RxIpHdrChkError = 6, /* Bit(5:7:0)=>6 Ip header checksum error detected for Ipv4 frames */ + RxIpHdrPayLoadChkError = 7, /* Bit(5:7:0)=>7 Payload & Ip header checksum error detected for Ipv4/Ipv6 frames */ }; /********************************************************** * DMA engine interrupt handling functions **********************************************************/ - + enum synopGMACDmaIntEnum /* Intrerrupt types */ { synopGMACDmaRxNormal = 0x01, /* normal receiver interrupt */ @@ -1089,7 +1089,7 @@ enum InitialRegisters | GmacSelectGmii | GmacEnableRxOwn | GmacLoopbackOff | GmacFullDuplex | GmacRetryEnable | GmacPadCrcStripDisable | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, - + /* Full-duplex mode with perfect filter on */ GmacConfigInitFdx110 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable | GmacSelectMii | GmacEnableRxOwn | GmacLoopbackOff @@ -1097,13 +1097,13 @@ enum InitialRegisters | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, /* Full-duplex mode */ - // CHANGED: Pass control config, dest addr filter normal, added source address filter, multicast & unicast - // Hash filter. + // CHANGED: Pass control config, dest addr filter normal, added source address filter, multicast & unicast + // Hash filter. /* = GmacFilterOff | GmacPassControlOff | GmacBroadcastEnable */ GmacFrameFilterInitFdx = GmacFilterOn | GmacPassControl0 | GmacBroadcastEnable | GmacSrcAddrFilterDisable | GmacMulticastFilterOn | GmacDestAddrFilterNor | GmacMcastHashFilterOff | GmacPromiscuousModeOff | GmacUcastHashFilterOff, - + /* Full-duplex mode */ GmacFlowControlInitFdx = GmacUnicastPauseFrameOff | GmacRxFlowControlEnable | GmacTxFlowControlEnable, @@ -1112,17 +1112,17 @@ enum InitialRegisters /* Half-duplex mode with perfect filter on */ - // CHANGED: Removed Endian configuration, added single bit config for PAD/CRC strip, + // CHANGED: Removed Endian configuration, added single bit config for PAD/CRC strip, /*| GmacSelectMii | GmacLittleEndian | GmacDisableRxOwn | GmacLoopbackOff*/ GmacConfigInitHdx1000 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable | GmacSelectGmii | GmacDisableRxOwn | GmacLoopbackOff - | GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable + | GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, /* Half-duplex mode with perfect filter on */ GmacConfigInitHdx110 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable | GmacSelectMii | GmacDisableRxOwn | GmacLoopbackOff - | GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable + | GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, /* Half-duplex mode */ @@ -1144,13 +1144,13 @@ enum InitialRegisters DmaBusModeInit = DmaFixedBurstEnable | DmaBurstLength8 | DmaDescriptorSkip2 | DmaResetOff, // DmaBusModeInit = DmaFixedBurstEnable | DmaBurstLength8 | DmaDescriptorSkip4 | DmaResetOff, - + /* 1000 Mb/s mode */ DmaControlInit1000 = DmaStoreAndForward,// | DmaTxSecondFrame , /* 100 Mb/s mode */ DmaControlInit100 = DmaStoreAndForward, - + /* 10 Mb/s mode */ DmaControlInit10 = DmaStoreAndForward, @@ -1178,191 +1178,191 @@ enum InitialRegisters enum MMC_ENABLE { - GmacMmcCntrl = 0x0100, /* mmc control for operating mode of MMC */ - GmacMmcIntrRx = 0x0104, /* maintains interrupts generated by rx counters */ - GmacMmcIntrTx = 0x0108, /* maintains interrupts generated by tx counters */ - GmacMmcIntrMaskRx = 0x010C, /* mask for interrupts generated from rx counters */ - GmacMmcIntrMaskTx = 0x0110, /* mask for interrupts generated from tx counters */ + GmacMmcCntrl = 0x0100, /* mmc control for operating mode of MMC */ + GmacMmcIntrRx = 0x0104, /* maintains interrupts generated by rx counters */ + GmacMmcIntrTx = 0x0108, /* maintains interrupts generated by tx counters */ + GmacMmcIntrMaskRx = 0x010C, /* mask for interrupts generated from rx counters */ + GmacMmcIntrMaskTx = 0x0110, /* mask for interrupts generated from tx counters */ }; enum MMC_TX { - GmacMmcTxOctetCountGb = 0x0114, /*Bytes Tx excl. of preamble and retried bytes (Good or Bad) */ - GmacMmcTxFrameCountGb = 0x0118, /*Frames Tx excl. of retried frames (Good or Bad) */ - GmacMmcTxBcFramesG = 0x011C, /*Broadcast Frames Tx (Good) */ - GmacMmcTxMcFramesG = 0x0120, /*Multicast Frames Tx (Good) */ - - GmacMmcTx64OctetsGb = 0x0124, /*Tx with len 64 bytes excl. of pre and retried (Good or Bad) */ - GmacMmcTx65To127OctetsGb = 0x0128, /*Tx with len >64 bytes <=127 excl. of pre and retried (Good or Bad) */ - GmacMmcTx128To255OctetsGb = 0x012C, /*Tx with len >128 bytes <=255 excl. of pre and retried (Good or Bad) */ - GmacMmcTx256To511OctetsGb = 0x0130, /*Tx with len >256 bytes <=511 excl. of pre and retried (Good or Bad) */ - GmacMmcTx512To1023OctetsGb = 0x0134, /*Tx with len >512 bytes <=1023 excl. of pre and retried (Good or Bad) */ - GmacMmcTx1024ToMaxOctetsGb = 0x0138, /*Tx with len >1024 bytes <=MaxSize excl. of pre and retried (Good or Bad) */ - - GmacMmcTxUcFramesGb = 0x013C, /*Unicast Frames Tx (Good or Bad) */ - GmacMmcTxMcFramesGb = 0x0140, /*Multicast Frames Tx (Good and Bad) */ - GmacMmcTxBcFramesGb = 0x0144, /*Broadcast Frames Tx (Good and Bad) */ - GmacMmcTxUnderFlowError = 0x0148, /*Frames aborted due to Underflow error */ - GmacMmcTxSingleColG = 0x014C, /*Successfully Tx Frames after singel collision in Half duplex mode */ - GmacMmcTxMultiColG = 0x0150, /*Successfully Tx Frames after more than singel collision in Half duplex mode */ - GmacMmcTxDeferred = 0x0154, /*Successfully Tx Frames after a deferral in Half duplex mode */ - GmacMmcTxLateCol = 0x0158, /*Frames aborted due to late collision error */ - GmacMmcTxExessCol = 0x015C, /*Frames aborted due to excessive (16) collision errors */ - GmacMmcTxCarrierError = 0x0160, /*Frames aborted due to carrier sense error (No carrier or Loss of carrier) */ - GmacMmcTxOctetCountG = 0x0164, /*Bytes Tx excl. of preamble and retried bytes (Good) */ - GmacMmcTxFrameCountG = 0x0168, /*Frames Tx (Good) */ - GmacMmcTxExessDef = 0x016C, /*Frames aborted due to excessive deferral errors (deferred for more than 2 max-sized frame times)*/ - - GmacMmcTxPauseFrames = 0x0170, /*Number of good pause frames Tx. */ - GmacMmcTxVlanFramesG = 0x0174, /*Number of good Vlan frames Tx excl. retried frames */ + GmacMmcTxOctetCountGb = 0x0114, /*Bytes Tx excl. of preamble and retried bytes (Good or Bad) */ + GmacMmcTxFrameCountGb = 0x0118, /*Frames Tx excl. of retried frames (Good or Bad) */ + GmacMmcTxBcFramesG = 0x011C, /*Broadcast Frames Tx (Good) */ + GmacMmcTxMcFramesG = 0x0120, /*Multicast Frames Tx (Good) */ + + GmacMmcTx64OctetsGb = 0x0124, /*Tx with len 64 bytes excl. of pre and retried (Good or Bad) */ + GmacMmcTx65To127OctetsGb = 0x0128, /*Tx with len >64 bytes <=127 excl. of pre and retried (Good or Bad) */ + GmacMmcTx128To255OctetsGb = 0x012C, /*Tx with len >128 bytes <=255 excl. of pre and retried (Good or Bad) */ + GmacMmcTx256To511OctetsGb = 0x0130, /*Tx with len >256 bytes <=511 excl. of pre and retried (Good or Bad) */ + GmacMmcTx512To1023OctetsGb = 0x0134, /*Tx with len >512 bytes <=1023 excl. of pre and retried (Good or Bad) */ + GmacMmcTx1024ToMaxOctetsGb = 0x0138, /*Tx with len >1024 bytes <=MaxSize excl. of pre and retried (Good or Bad) */ + + GmacMmcTxUcFramesGb = 0x013C, /*Unicast Frames Tx (Good or Bad) */ + GmacMmcTxMcFramesGb = 0x0140, /*Multicast Frames Tx (Good and Bad) */ + GmacMmcTxBcFramesGb = 0x0144, /*Broadcast Frames Tx (Good and Bad) */ + GmacMmcTxUnderFlowError = 0x0148, /*Frames aborted due to Underflow error */ + GmacMmcTxSingleColG = 0x014C, /*Successfully Tx Frames after singel collision in Half duplex mode */ + GmacMmcTxMultiColG = 0x0150, /*Successfully Tx Frames after more than singel collision in Half duplex mode */ + GmacMmcTxDeferred = 0x0154, /*Successfully Tx Frames after a deferral in Half duplex mode */ + GmacMmcTxLateCol = 0x0158, /*Frames aborted due to late collision error */ + GmacMmcTxExessCol = 0x015C, /*Frames aborted due to excessive (16) collision errors */ + GmacMmcTxCarrierError = 0x0160, /*Frames aborted due to carrier sense error (No carrier or Loss of carrier) */ + GmacMmcTxOctetCountG = 0x0164, /*Bytes Tx excl. of preamble and retried bytes (Good) */ + GmacMmcTxFrameCountG = 0x0168, /*Frames Tx (Good) */ + GmacMmcTxExessDef = 0x016C, /*Frames aborted due to excessive deferral errors (deferred for more than 2 max-sized frame times)*/ + + GmacMmcTxPauseFrames = 0x0170, /*Number of good pause frames Tx. */ + GmacMmcTxVlanFramesG = 0x0174, /*Number of good Vlan frames Tx excl. retried frames */ }; enum MMC_RX { - GmacMmcRxFrameCountGb = 0x0180, /*Frames Rx (Good or Bad) */ - GmacMmcRxOctetCountGb = 0x0184, /*Bytes Rx excl. of preamble and retried bytes (Good or Bad) */ - GmacMmcRxOctetCountG = 0x0188, /*Bytes Rx excl. of preamble and retried bytes (Good) */ - GmacMmcRxBcFramesG = 0x018C, /*Broadcast Frames Rx (Good) */ - GmacMmcRxMcFramesG = 0x0190, /*Multicast Frames Rx (Good) */ - - GmacMmcRxCrcError = 0x0194, /*Number of frames received with CRC error */ - GmacMmcRxAlignError = 0x0198, /*Number of frames received with alignment (dribble) error. Only in 10/100mode */ - GmacMmcRxRuntError = 0x019C, /*Number of frames received with runt (<64 bytes and CRC error) error */ - GmacMmcRxJabberError = 0x01A0, /*Number of frames rx with jabber (>1518/1522 or >9018/9022 and CRC) */ - GmacMmcRxUnderSizeG = 0x01A4, /*Number of frames received with <64 bytes without any error */ - GmacMmcRxOverSizeG = 0x01A8, /*Number of frames received with >1518/1522 bytes without any error */ - - GmacMmcRx64OctetsGb = 0x01AC, /*Rx with len 64 bytes excl. of pre and retried (Good or Bad) */ - GmacMmcRx65To127OctetsGb = 0x01B0, /*Rx with len >64 bytes <=127 excl. of pre and retried (Good or Bad) */ - GmacMmcRx128To255OctetsGb = 0x01B4, /*Rx with len >128 bytes <=255 excl. of pre and retried (Good or Bad) */ - GmacMmcRx256To511OctetsGb = 0x01B8, /*Rx with len >256 bytes <=511 excl. of pre and retried (Good or Bad) */ - GmacMmcRx512To1023OctetsGb = 0x01BC, /*Rx with len >512 bytes <=1023 excl. of pre and retried (Good or Bad) */ - GmacMmcRx1024ToMaxOctetsGb = 0x01C0, /*Rx with len >1024 bytes <=MaxSize excl. of pre and retried (Good or Bad) */ - - GmacMmcRxUcFramesG = 0x01C4, /*Unicast Frames Rx (Good) */ - GmacMmcRxLengthError = 0x01C8, /*Number of frames received with Length type field != frame size */ - GmacMmcRxOutOfRangeType = 0x01CC, /*Number of frames received with length field != valid frame size */ - - GmacMmcRxPauseFrames = 0x01D0, /*Number of good pause frames Rx. */ - GmacMmcRxFifoOverFlow = 0x01D4, /*Number of missed rx frames due to FIFO overflow */ - GmacMmcRxVlanFramesGb = 0x01D8, /*Number of good Vlan frames Rx */ - - GmacMmcRxWatchdobError = 0x01DC, /*Number of frames rx with error due to watchdog timeout error */ + GmacMmcRxFrameCountGb = 0x0180, /*Frames Rx (Good or Bad) */ + GmacMmcRxOctetCountGb = 0x0184, /*Bytes Rx excl. of preamble and retried bytes (Good or Bad) */ + GmacMmcRxOctetCountG = 0x0188, /*Bytes Rx excl. of preamble and retried bytes (Good) */ + GmacMmcRxBcFramesG = 0x018C, /*Broadcast Frames Rx (Good) */ + GmacMmcRxMcFramesG = 0x0190, /*Multicast Frames Rx (Good) */ + + GmacMmcRxCrcError = 0x0194, /*Number of frames received with CRC error */ + GmacMmcRxAlignError = 0x0198, /*Number of frames received with alignment (dribble) error. Only in 10/100mode */ + GmacMmcRxRuntError = 0x019C, /*Number of frames received with runt (<64 bytes and CRC error) error */ + GmacMmcRxJabberError = 0x01A0, /*Number of frames rx with jabber (>1518/1522 or >9018/9022 and CRC) */ + GmacMmcRxUnderSizeG = 0x01A4, /*Number of frames received with <64 bytes without any error */ + GmacMmcRxOverSizeG = 0x01A8, /*Number of frames received with >1518/1522 bytes without any error */ + + GmacMmcRx64OctetsGb = 0x01AC, /*Rx with len 64 bytes excl. of pre and retried (Good or Bad) */ + GmacMmcRx65To127OctetsGb = 0x01B0, /*Rx with len >64 bytes <=127 excl. of pre and retried (Good or Bad) */ + GmacMmcRx128To255OctetsGb = 0x01B4, /*Rx with len >128 bytes <=255 excl. of pre and retried (Good or Bad) */ + GmacMmcRx256To511OctetsGb = 0x01B8, /*Rx with len >256 bytes <=511 excl. of pre and retried (Good or Bad) */ + GmacMmcRx512To1023OctetsGb = 0x01BC, /*Rx with len >512 bytes <=1023 excl. of pre and retried (Good or Bad) */ + GmacMmcRx1024ToMaxOctetsGb = 0x01C0, /*Rx with len >1024 bytes <=MaxSize excl. of pre and retried (Good or Bad) */ + + GmacMmcRxUcFramesG = 0x01C4, /*Unicast Frames Rx (Good) */ + GmacMmcRxLengthError = 0x01C8, /*Number of frames received with Length type field != frame size */ + GmacMmcRxOutOfRangeType = 0x01CC, /*Number of frames received with length field != valid frame size */ + + GmacMmcRxPauseFrames = 0x01D0, /*Number of good pause frames Rx. */ + GmacMmcRxFifoOverFlow = 0x01D4, /*Number of missed rx frames due to FIFO overflow */ + GmacMmcRxVlanFramesGb = 0x01D8, /*Number of good Vlan frames Rx */ + + GmacMmcRxWatchdobError = 0x01DC, /*Number of frames rx with error due to watchdog timeout error */ }; enum MMC_IP_RELATED { - GmacMmcRxIpcIntrMask = 0x0200, /*Maintains the mask for interrupt generated from rx IPC statistic counters */ - GmacMmcRxIpcIntr = 0x0208, /*Maintains the interrupt that rx IPC statistic counters generate */ - - GmacMmcRxIpV4FramesG = 0x0210, /*Good IPV4 datagrams received */ - GmacMmcRxIpV4HdrErrFrames = 0x0214, /*Number of IPV4 datagrams received with header errors */ - GmacMmcRxIpV4NoPayFrames = 0x0218, /*Number of IPV4 datagrams received which didnot have TCP/UDP/ICMP payload */ - GmacMmcRxIpV4FragFrames = 0x021C, /*Number of IPV4 datagrams received with fragmentation */ - GmacMmcRxIpV4UdpChkDsblFrames = 0x0220, /*Number of IPV4 datagrams received that had a UDP payload checksum disabled */ - - GmacMmcRxIpV6FramesG = 0x0224, /*Good IPV6 datagrams received */ - GmacMmcRxIpV6HdrErrFrames = 0x0228, /*Number of IPV6 datagrams received with header errors */ - GmacMmcRxIpV6NoPayFrames = 0x022C, /*Number of IPV6 datagrams received which didnot have TCP/UDP/ICMP payload */ - - GmacMmcRxUdpFramesG = 0x0230, /*Number of good IP datagrams with good UDP payload */ - GmacMmcRxUdpErrorFrames = 0x0234, /*Number of good IP datagrams with UDP payload having checksum error */ - - GmacMmcRxTcpFramesG = 0x0238, /*Number of good IP datagrams with good TDP payload */ - GmacMmcRxTcpErrorFrames = 0x023C, /*Number of good IP datagrams with TCP payload having checksum error */ - - GmacMmcRxIcmpFramesG = 0x0240, /*Number of good IP datagrams with good Icmp payload */ - GmacMmcRxIcmpErrorFrames = 0x0244, /*Number of good IP datagrams with Icmp payload having checksum error */ - - GmacMmcRxIpV4OctetsG = 0x0250, /*Good IPV4 datagrams received excl. Ethernet hdr,FCS,Pad,Ip Pad bytes */ - GmacMmcRxIpV4HdrErrorOctets = 0x0254, /*Number of bytes in IPV4 datagram with header errors */ - GmacMmcRxIpV4NoPayOctets = 0x0258, /*Number of bytes in IPV4 datagram with no TCP/UDP/ICMP payload */ - GmacMmcRxIpV4FragOctets = 0x025C, /*Number of bytes received in fragmented IPV4 datagrams */ - GmacMmcRxIpV4UdpChkDsblOctets = 0x0260, /*Number of bytes received in UDP segment that had UDP checksum disabled */ - - GmacMmcRxIpV6OctetsG = 0x0264, /*Good IPV6 datagrams received excl. Ethernet hdr,FCS,Pad,Ip Pad bytes */ - GmacMmcRxIpV6HdrErrorOctets = 0x0268, /*Number of bytes in IPV6 datagram with header errors */ - GmacMmcRxIpV6NoPayOctets = 0x026C, /*Number of bytes in IPV6 datagram with no TCP/UDP/ICMP payload */ - - GmacMmcRxUdpOctetsG = 0x0270, /*Number of bytes in IP datagrams with good UDP payload */ - GmacMmcRxUdpErrorOctets = 0x0274, /*Number of bytes in IP datagrams with UDP payload having checksum error */ - - GmacMmcRxTcpOctetsG = 0x0278, /*Number of bytes in IP datagrams with good TDP payload */ - GmacMmcRxTcpErrorOctets = 0x027C, /*Number of bytes in IP datagrams with TCP payload having checksum error */ - - GmacMmcRxIcmpOctetsG = 0x0280, /*Number of bytes in IP datagrams with good Icmp payload */ - GmacMmcRxIcmpErrorOctets = 0x0284, /*Number of bytes in IP datagrams with Icmp payload having checksum error */ + GmacMmcRxIpcIntrMask = 0x0200, /*Maintains the mask for interrupt generated from rx IPC statistic counters */ + GmacMmcRxIpcIntr = 0x0208, /*Maintains the interrupt that rx IPC statistic counters generate */ + + GmacMmcRxIpV4FramesG = 0x0210, /*Good IPV4 datagrams received */ + GmacMmcRxIpV4HdrErrFrames = 0x0214, /*Number of IPV4 datagrams received with header errors */ + GmacMmcRxIpV4NoPayFrames = 0x0218, /*Number of IPV4 datagrams received which didnot have TCP/UDP/ICMP payload */ + GmacMmcRxIpV4FragFrames = 0x021C, /*Number of IPV4 datagrams received with fragmentation */ + GmacMmcRxIpV4UdpChkDsblFrames = 0x0220, /*Number of IPV4 datagrams received that had a UDP payload checksum disabled */ + + GmacMmcRxIpV6FramesG = 0x0224, /*Good IPV6 datagrams received */ + GmacMmcRxIpV6HdrErrFrames = 0x0228, /*Number of IPV6 datagrams received with header errors */ + GmacMmcRxIpV6NoPayFrames = 0x022C, /*Number of IPV6 datagrams received which didnot have TCP/UDP/ICMP payload */ + + GmacMmcRxUdpFramesG = 0x0230, /*Number of good IP datagrams with good UDP payload */ + GmacMmcRxUdpErrorFrames = 0x0234, /*Number of good IP datagrams with UDP payload having checksum error */ + + GmacMmcRxTcpFramesG = 0x0238, /*Number of good IP datagrams with good TDP payload */ + GmacMmcRxTcpErrorFrames = 0x023C, /*Number of good IP datagrams with TCP payload having checksum error */ + + GmacMmcRxIcmpFramesG = 0x0240, /*Number of good IP datagrams with good Icmp payload */ + GmacMmcRxIcmpErrorFrames = 0x0244, /*Number of good IP datagrams with Icmp payload having checksum error */ + + GmacMmcRxIpV4OctetsG = 0x0250, /*Good IPV4 datagrams received excl. Ethernet hdr,FCS,Pad,Ip Pad bytes */ + GmacMmcRxIpV4HdrErrorOctets = 0x0254, /*Number of bytes in IPV4 datagram with header errors */ + GmacMmcRxIpV4NoPayOctets = 0x0258, /*Number of bytes in IPV4 datagram with no TCP/UDP/ICMP payload */ + GmacMmcRxIpV4FragOctets = 0x025C, /*Number of bytes received in fragmented IPV4 datagrams */ + GmacMmcRxIpV4UdpChkDsblOctets = 0x0260, /*Number of bytes received in UDP segment that had UDP checksum disabled */ + + GmacMmcRxIpV6OctetsG = 0x0264, /*Good IPV6 datagrams received excl. Ethernet hdr,FCS,Pad,Ip Pad bytes */ + GmacMmcRxIpV6HdrErrorOctets = 0x0268, /*Number of bytes in IPV6 datagram with header errors */ + GmacMmcRxIpV6NoPayOctets = 0x026C, /*Number of bytes in IPV6 datagram with no TCP/UDP/ICMP payload */ + + GmacMmcRxUdpOctetsG = 0x0270, /*Number of bytes in IP datagrams with good UDP payload */ + GmacMmcRxUdpErrorOctets = 0x0274, /*Number of bytes in IP datagrams with UDP payload having checksum error */ + + GmacMmcRxTcpOctetsG = 0x0278, /*Number of bytes in IP datagrams with good TDP payload */ + GmacMmcRxTcpErrorOctets = 0x027C, /*Number of bytes in IP datagrams with TCP payload having checksum error */ + + GmacMmcRxIcmpOctetsG = 0x0280, /*Number of bytes in IP datagrams with good Icmp payload */ + GmacMmcRxIcmpErrorOctets = 0x0284, /*Number of bytes in IP datagrams with Icmp payload having checksum error */ }; enum MMC_CNTRL_REG_BIT_DESCRIPTIONS { - GmacMmcCounterFreeze = 0x00000008, /* when set MMC counters freeze to current value */ - GmacMmcCounterResetOnRead = 0x00000004, /* when set MMC counters will be reset to 0 after read */ - GmacMmcCounterStopRollover = 0x00000002, /* when set counters will not rollover after max value */ - GmacMmcCounterReset = 0x00000001, /* when set all counters wil be reset (automatically cleared after 1 clk) */ - + GmacMmcCounterFreeze = 0x00000008, /* when set MMC counters freeze to current value */ + GmacMmcCounterResetOnRead = 0x00000004, /* when set MMC counters will be reset to 0 after read */ + GmacMmcCounterStopRollover = 0x00000002, /* when set counters will not rollover after max value */ + GmacMmcCounterReset = 0x00000001, /* when set all counters wil be reset (automatically cleared after 1 clk) */ + }; enum MMC_RX_INTR_MASK_AND_STATUS_BIT_DESCRIPTIONS { - GmacMmcRxWDInt = 0x00800000, /* set when rxwatchdog error reaches half of max value */ - GmacMmcRxVlanInt = 0x00400000, /* set when GmacMmcRxVlanFramesGb counter reaches half of max value */ - GmacMmcRxFifoOverFlowInt = 0x00200000, /* set when GmacMmcRxFifoOverFlow counter reaches half of max value */ - GmacMmcRxPauseFrameInt = 0x00100000, /* set when GmacMmcRxPauseFrames counter reaches half of max value */ - GmacMmcRxOutOfRangeInt = 0x00080000, /* set when GmacMmcRxOutOfRangeType counter reaches half of max value */ - GmacMmcRxLengthErrorInt = 0x00040000, /* set when GmacMmcRxLengthError counter reaches half of max value */ - GmacMmcRxUcFramesInt = 0x00020000, /* set when GmacMmcRxUcFramesG counter reaches half of max value */ - GmacMmcRx1024OctInt = 0x00010000, /* set when GmacMmcRx1024ToMaxOctetsGb counter reaches half of max value */ - GmacMmcRx512OctInt = 0x00008000, /* set when GmacMmcRx512To1023OctetsGb counter reaches half of max value */ - GmacMmcRx256OctInt = 0x00004000, /* set when GmacMmcRx256To511OctetsGb counter reaches half of max value */ - GmacMmcRx128OctInt = 0x00002000, /* set when GmacMmcRx128To255OctetsGb counter reaches half of max value */ - GmacMmcRx65OctInt = 0x00001000, /* set when GmacMmcRx65To127OctetsG counter reaches half of max value */ - GmacMmcRx64OctInt = 0x00000800, /* set when GmacMmcRx64OctetsGb counter reaches half of max value */ - GmacMmcRxOverSizeInt = 0x00000400, /* set when GmacMmcRxOverSizeG counter reaches half of max value */ - GmacMmcRxUnderSizeInt = 0x00000200, /* set when GmacMmcRxUnderSizeG counter reaches half of max value */ - GmacMmcRxJabberErrorInt = 0x00000100, /* set when GmacMmcRxJabberError counter reaches half of max value */ - GmacMmcRxRuntErrorInt = 0x00000080, /* set when GmacMmcRxRuntError counter reaches half of max value */ - GmacMmcRxAlignErrorInt = 0x00000040, /* set when GmacMmcRxAlignError counter reaches half of max value */ - GmacMmcRxCrcErrorInt = 0x00000020, /* set when GmacMmcRxCrcError counter reaches half of max value */ - GmacMmcRxMcFramesInt = 0x00000010, /* set when GmacMmcRxMcFramesG counter reaches half of max value */ - GmacMmcRxBcFramesInt = 0x00000008, /* set when GmacMmcRxBcFramesG counter reaches half of max value */ - GmacMmcRxOctetGInt = 0x00000004, /* set when GmacMmcRxOctetCountG counter reaches half of max value */ - GmacMmcRxOctetGbInt = 0x00000002, /* set when GmacMmcRxOctetCountGb counter reaches half of max value */ - GmacMmcRxFrameInt = 0x00000001, /* set when GmacMmcRxFrameCountGb counter reaches half of max value */ + GmacMmcRxWDInt = 0x00800000, /* set when rxwatchdog error reaches half of max value */ + GmacMmcRxVlanInt = 0x00400000, /* set when GmacMmcRxVlanFramesGb counter reaches half of max value */ + GmacMmcRxFifoOverFlowInt = 0x00200000, /* set when GmacMmcRxFifoOverFlow counter reaches half of max value */ + GmacMmcRxPauseFrameInt = 0x00100000, /* set when GmacMmcRxPauseFrames counter reaches half of max value */ + GmacMmcRxOutOfRangeInt = 0x00080000, /* set when GmacMmcRxOutOfRangeType counter reaches half of max value */ + GmacMmcRxLengthErrorInt = 0x00040000, /* set when GmacMmcRxLengthError counter reaches half of max value */ + GmacMmcRxUcFramesInt = 0x00020000, /* set when GmacMmcRxUcFramesG counter reaches half of max value */ + GmacMmcRx1024OctInt = 0x00010000, /* set when GmacMmcRx1024ToMaxOctetsGb counter reaches half of max value */ + GmacMmcRx512OctInt = 0x00008000, /* set when GmacMmcRx512To1023OctetsGb counter reaches half of max value */ + GmacMmcRx256OctInt = 0x00004000, /* set when GmacMmcRx256To511OctetsGb counter reaches half of max value */ + GmacMmcRx128OctInt = 0x00002000, /* set when GmacMmcRx128To255OctetsGb counter reaches half of max value */ + GmacMmcRx65OctInt = 0x00001000, /* set when GmacMmcRx65To127OctetsG counter reaches half of max value */ + GmacMmcRx64OctInt = 0x00000800, /* set when GmacMmcRx64OctetsGb counter reaches half of max value */ + GmacMmcRxOverSizeInt = 0x00000400, /* set when GmacMmcRxOverSizeG counter reaches half of max value */ + GmacMmcRxUnderSizeInt = 0x00000200, /* set when GmacMmcRxUnderSizeG counter reaches half of max value */ + GmacMmcRxJabberErrorInt = 0x00000100, /* set when GmacMmcRxJabberError counter reaches half of max value */ + GmacMmcRxRuntErrorInt = 0x00000080, /* set when GmacMmcRxRuntError counter reaches half of max value */ + GmacMmcRxAlignErrorInt = 0x00000040, /* set when GmacMmcRxAlignError counter reaches half of max value */ + GmacMmcRxCrcErrorInt = 0x00000020, /* set when GmacMmcRxCrcError counter reaches half of max value */ + GmacMmcRxMcFramesInt = 0x00000010, /* set when GmacMmcRxMcFramesG counter reaches half of max value */ + GmacMmcRxBcFramesInt = 0x00000008, /* set when GmacMmcRxBcFramesG counter reaches half of max value */ + GmacMmcRxOctetGInt = 0x00000004, /* set when GmacMmcRxOctetCountG counter reaches half of max value */ + GmacMmcRxOctetGbInt = 0x00000002, /* set when GmacMmcRxOctetCountGb counter reaches half of max value */ + GmacMmcRxFrameInt = 0x00000001, /* set when GmacMmcRxFrameCountGb counter reaches half of max value */ }; enum MMC_TX_INTR_MASK_AND_STATUS_BIT_DESCRIPTIONS { - GmacMmcTxVlanInt = 0x01000000, /* set when GmacMmcTxVlanFramesG counter reaches half of max value */ - GmacMmcTxPauseFrameInt = 0x00800000, /* set when GmacMmcTxPauseFrames counter reaches half of max value */ - GmacMmcTxExessDefInt = 0x00400000, /* set when GmacMmcTxExessDef counter reaches half of max value */ - GmacMmcTxFrameInt = 0x00200000, /* set when GmacMmcTxFrameCount counter reaches half of max value */ - GmacMmcTxOctetInt = 0x00100000, /* set when GmacMmcTxOctetCountG counter reaches half of max value */ - GmacMmcTxCarrierErrorInt = 0x00080000, /* set when GmacMmcTxCarrierError counter reaches half of max value */ - GmacMmcTxExessColInt = 0x00040000, /* set when GmacMmcTxExessCol counter reaches half of max value */ - GmacMmcTxLateColInt = 0x00020000, /* set when GmacMmcTxLateCol counter reaches half of max value */ - GmacMmcTxDeferredInt = 0x00010000, /* set when GmacMmcTxDeferred counter reaches half of max value */ - GmacMmcTxMultiColInt = 0x00008000, /* set when GmacMmcTxMultiColG counter reaches half of max value */ - GmacMmcTxSingleCol = 0x00004000, /* set when GmacMmcTxSingleColG counter reaches half of max value */ - GmacMmcTxUnderFlowErrorInt = 0x00002000, /* set when GmacMmcTxUnderFlowError counter reaches half of max value */ - GmacMmcTxBcFramesGbInt = 0x00001000, /* set when GmacMmcTxBcFramesGb counter reaches half of max value */ - GmacMmcTxMcFramesGbInt = 0x00000800, /* set when GmacMmcTxMcFramesGb counter reaches half of max value */ - GmacMmcTxUcFramesInt = 0x00000400, /* set when GmacMmcTxUcFramesGb counter reaches half of max value */ - GmacMmcTx1024OctInt = 0x00000200, /* set when GmacMmcTx1024ToMaxOctetsGb counter reaches half of max value */ - GmacMmcTx512OctInt = 0x00000100, /* set when GmacMmcTx512To1023OctetsGb counter reaches half of max value */ - GmacMmcTx256OctInt = 0x00000080, /* set when GmacMmcTx256To511OctetsGb counter reaches half of max value */ - GmacMmcTx128OctInt = 0x00000040, /* set when GmacMmcTx128To255OctetsGb counter reaches half of max value */ - GmacMmcTx65OctInt = 0x00000020, /* set when GmacMmcTx65To127OctetsGb counter reaches half of max value */ - GmacMmcTx64OctInt = 0x00000010, /* set when GmacMmcTx64OctetsGb counter reaches half of max value */ - GmacMmcTxMcFramesInt = 0x00000008, /* set when GmacMmcTxMcFramesG counter reaches half of max value */ - GmacMmcTxBcFramesInt = 0x00000004, /* set when GmacMmcTxBcFramesG counter reaches half of max value */ - GmacMmcTxFrameGbInt = 0x00000002, /* set when GmacMmcTxFrameCountGb counter reaches half of max value */ - GmacMmcTxOctetGbInt = 0x00000001, /* set when GmacMmcTxOctetCountGb counter reaches half of max value */ - + GmacMmcTxVlanInt = 0x01000000, /* set when GmacMmcTxVlanFramesG counter reaches half of max value */ + GmacMmcTxPauseFrameInt = 0x00800000, /* set when GmacMmcTxPauseFrames counter reaches half of max value */ + GmacMmcTxExessDefInt = 0x00400000, /* set when GmacMmcTxExessDef counter reaches half of max value */ + GmacMmcTxFrameInt = 0x00200000, /* set when GmacMmcTxFrameCount counter reaches half of max value */ + GmacMmcTxOctetInt = 0x00100000, /* set when GmacMmcTxOctetCountG counter reaches half of max value */ + GmacMmcTxCarrierErrorInt = 0x00080000, /* set when GmacMmcTxCarrierError counter reaches half of max value */ + GmacMmcTxExessColInt = 0x00040000, /* set when GmacMmcTxExessCol counter reaches half of max value */ + GmacMmcTxLateColInt = 0x00020000, /* set when GmacMmcTxLateCol counter reaches half of max value */ + GmacMmcTxDeferredInt = 0x00010000, /* set when GmacMmcTxDeferred counter reaches half of max value */ + GmacMmcTxMultiColInt = 0x00008000, /* set when GmacMmcTxMultiColG counter reaches half of max value */ + GmacMmcTxSingleCol = 0x00004000, /* set when GmacMmcTxSingleColG counter reaches half of max value */ + GmacMmcTxUnderFlowErrorInt = 0x00002000, /* set when GmacMmcTxUnderFlowError counter reaches half of max value */ + GmacMmcTxBcFramesGbInt = 0x00001000, /* set when GmacMmcTxBcFramesGb counter reaches half of max value */ + GmacMmcTxMcFramesGbInt = 0x00000800, /* set when GmacMmcTxMcFramesGb counter reaches half of max value */ + GmacMmcTxUcFramesInt = 0x00000400, /* set when GmacMmcTxUcFramesGb counter reaches half of max value */ + GmacMmcTx1024OctInt = 0x00000200, /* set when GmacMmcTx1024ToMaxOctetsGb counter reaches half of max value */ + GmacMmcTx512OctInt = 0x00000100, /* set when GmacMmcTx512To1023OctetsGb counter reaches half of max value */ + GmacMmcTx256OctInt = 0x00000080, /* set when GmacMmcTx256To511OctetsGb counter reaches half of max value */ + GmacMmcTx128OctInt = 0x00000040, /* set when GmacMmcTx128To255OctetsGb counter reaches half of max value */ + GmacMmcTx65OctInt = 0x00000020, /* set when GmacMmcTx65To127OctetsGb counter reaches half of max value */ + GmacMmcTx64OctInt = 0x00000010, /* set when GmacMmcTx64OctetsGb counter reaches half of max value */ + GmacMmcTxMcFramesInt = 0x00000008, /* set when GmacMmcTxMcFramesG counter reaches half of max value */ + GmacMmcTxBcFramesInt = 0x00000004, /* set when GmacMmcTxBcFramesG counter reaches half of max value */ + GmacMmcTxFrameGbInt = 0x00000002, /* set when GmacMmcTxFrameCountGb counter reaches half of max value */ + GmacMmcTxOctetGbInt = 0x00000001, /* set when GmacMmcTxOctetCountGb counter reaches half of max value */ + }; /********************************************************** - * Power Management (PMT) Block + * Power Management (PMT) Block **********************************************************/ /** @@ -1372,36 +1372,36 @@ enum MMC_TX_INTR_MASK_AND_STATUS_BIT_DESCRIPTIONS * These enable are in PMT control and Status register and are programmed by apllication. * * When power down mode is enabled in PMT, all rx frames are dropped by the core. Core comes - * out of power down mode only when either Magic packe tor a Remote wake-up frame is received + * out of power down mode only when either Magic packe tor a Remote wake-up frame is received * and the corresponding detection is enabled. * - * Driver need not be modified to support this feature. Only Api to put the device in to power + * Driver need not be modified to support this feature. Only Api to put the device in to power * down mode is sufficient */ -#define WAKEUP_REG_LENGTH 8 /*This is the reg length for wake up register configuration*/ +#define WAKEUP_REG_LENGTH 8 /*This is the reg length for wake up register configuration*/ enum GmacPmtCtrlStatusBitDefinition { - GmacPmtFrmFilterPtrReset = 0x80000000, /* when set remote wake-up frame filter register pointer to 3'b000 */ - GmacPmtGlobalUnicast = 0x00000200, /* When set enables any unicast packet to be a wake-up frame */ - GmacPmtWakeupFrameReceived = 0x00000040, /* Wake up frame received */ - GmacPmtMagicPktReceived = 0x00000020, /* Magic Packet received */ - GmacPmtWakeupFrameEnable = 0x00000004, /* Wake-up frame enable */ - GmacPmtMagicPktEnable = 0x00000002, /* Magic packet enable */ - GmacPmtPowerDown = 0x00000001, /* Power Down */ + GmacPmtFrmFilterPtrReset = 0x80000000, /* when set remote wake-up frame filter register pointer to 3'b000 */ + GmacPmtGlobalUnicast = 0x00000200, /* When set enables any unicast packet to be a wake-up frame */ + GmacPmtWakeupFrameReceived = 0x00000040, /* Wake up frame received */ + GmacPmtMagicPktReceived = 0x00000020, /* Magic Packet received */ + GmacPmtWakeupFrameEnable = 0x00000004, /* Wake-up frame enable */ + GmacPmtMagicPktEnable = 0x00000002, /* Magic packet enable */ + GmacPmtPowerDown = 0x00000001, /* Power Down */ }; /********************************************************** - * IEEE 1588-2008 Precision Time Protocol (PTP) Support + * IEEE 1588-2008 Precision Time Protocol (PTP) Support **********************************************************/ enum PTPMessageType { - SYNC = 0x0, - Delay_Req = 0x1, + SYNC = 0x0, + Delay_Req = 0x1, Pdelay_Req = 0x2, Pdelay_Resp = 0x3, Follow_up = 0x8, @@ -1414,14 +1414,14 @@ enum PTPMessageType -typedef struct TimeStampStruct -{ +typedef struct TimeStampStruct +{ u32 TSversion; /* PTP Version 1 or PTP version2 */ - u32 TSmessagetype; /* Message type associated with this time stamp */ + u32 TSmessagetype; /* Message type associated with this time stamp */ - u16 TShighest16; /* Highest 16 bit time stamp value, Valid onley when ADV_TIME_HIGH_WORD configured in corekit */ - u32 TSupper32; /* Most significant 32 bit time stamp value */ - u32 TSlower32; /* Least Significat 32 bit time stamp value */ + u16 TShighest16; /* Highest 16 bit time stamp value, Valid onley when ADV_TIME_HIGH_WORD configured in corekit */ + u32 TSupper32; /* Most significant 32 bit time stamp value */ + u32 TSlower32; /* Least Significat 32 bit time stamp value */ } TimeStamp; @@ -1439,9 +1439,9 @@ typedef struct TimeStampStruct /* GmacTSControl = 0x0700, Controls the Timestamp update logic : only when IEEE 1588 time stamping is enabled in corekit */ enum GmacTSControlReg { - GmacTSENMACADDR = 0x00040000, /* Enable Mac Addr for PTP filtering 18 RW 0 */ - - GmacTSCLKTYPE = 0x00030000, /* Select the type of clock node 17:16 RW 00 */ + GmacTSENMACADDR = 0x00040000, /* Enable Mac Addr for PTP filtering 18 RW 0 */ + + GmacTSCLKTYPE = 0x00030000, /* Select the type of clock node 17:16 RW 00 */ /* TSCLKTYPE TSMSTRENA TSEVNTENA Messages for wihich TS snapshot is taken 00/01 X 0 SYNC, FOLLOW_UP, DELAY_REQ, DELAY_RESP @@ -1450,45 +1450,45 @@ enum GmacTSControlReg 10 NA 0 SYNC, FOLLOW_UP, DELAY_REQ, DELAY_RESP 10 NA 1 SYNC, FOLLOW_UP 11 NA 0 SYNC, FOLLOW_UP, DELAY_REQ, DELAY_RESP, PDELAY_REQ, PDELAY_RESP - 11 NA 1 SYNC, PDELAY_REQ, PDELAY_RESP + 11 NA 1 SYNC, PDELAY_REQ, PDELAY_RESP */ - GmacTSOrdClk = 0x00000000, /* 00=> Ordinary clock*/ - GmacTSBouClk = 0x00010000, /* 01=> Boundary clock*/ - GmacTSEtoEClk = 0x00020000, /* 10=> End-to-End transparent clock*/ - GmacTSPtoPClk = 0x00030000, /* 11=> P-to-P transparent clock*/ - - GmacTSMSTRENA = 0x00008000, /* Ena TS Snapshot for Master Messages 15 RW 0 */ - GmacTSEVNTENA = 0x00004000, /* Ena TS Snapshot for Event Messages 14 RW 0 */ - GmacTSIPV4ENA = 0x00002000, /* Ena TS snapshot for IPv4 13 RW 1 */ - GmacTSIPV6ENA = 0x00001000, /* Ena TS snapshot for IPv6 12 RW 0 */ - GmacTSIPENA = 0x00000800, /* Ena TS snapshot for PTP over E'net 11 RW 0 */ - GmacTSVER2ENA = 0x00000400, /* Ena PTP snooping for version 2 10 RW 0 */ + GmacTSOrdClk = 0x00000000, /* 00=> Ordinary clock*/ + GmacTSBouClk = 0x00010000, /* 01=> Boundary clock*/ + GmacTSEtoEClk = 0x00020000, /* 10=> End-to-End transparent clock*/ + GmacTSPtoPClk = 0x00030000, /* 11=> P-to-P transparent clock*/ + + GmacTSMSTRENA = 0x00008000, /* Ena TS Snapshot for Master Messages 15 RW 0 */ + GmacTSEVNTENA = 0x00004000, /* Ena TS Snapshot for Event Messages 14 RW 0 */ + GmacTSIPV4ENA = 0x00002000, /* Ena TS snapshot for IPv4 13 RW 1 */ + GmacTSIPV6ENA = 0x00001000, /* Ena TS snapshot for IPv6 12 RW 0 */ + GmacTSIPENA = 0x00000800, /* Ena TS snapshot for PTP over E'net 11 RW 0 */ + GmacTSVER2ENA = 0x00000400, /* Ena PTP snooping for version 2 10 RW 0 */ GmacTSCTRLSSR = 0x00000200, /* Digital or Binary Rollover 9 RW 0 */ GmacTSENALL = 0x00000100, /* Enable TS fro all frames (Ver2 only) 8 RW 0 */ - GmacTSADDREG = 0x00000020, /* Addend Register Update 5 RW_SC 0 */ - GmacTSUPDT = 0x00000008, /* Time Stamp Update 3 RW_SC 0 */ - GmacTSINT = 0x00000004, /* Time Atamp Initialize 2 RW_SC 0 */ - - GmacTSTRIG = 0x00000010, /* Time stamp interrupt Trigger Enable 4 RW_SC 0 */ + GmacTSADDREG = 0x00000020, /* Addend Register Update 5 RW_SC 0 */ + GmacTSUPDT = 0x00000008, /* Time Stamp Update 3 RW_SC 0 */ + GmacTSINT = 0x00000004, /* Time Atamp Initialize 2 RW_SC 0 */ - GmacTSCFUPDT = 0x00000002, /* Time Stamp Fine/Coarse 1 RW 0 */ - GmacTSCUPDTCoarse = 0x00000000, /* 0=> Time Stamp update method is coarse */ - GmacTSCUPDTFine = 0x00000002, /* 1=> Time Stamp update method is fine */ + GmacTSTRIG = 0x00000010, /* Time stamp interrupt Trigger Enable 4 RW_SC 0 */ - GmacTSENA = 0x00000001, /* Time Stamp Enable 0 RW 0 */ + GmacTSCFUPDT = 0x00000002, /* Time Stamp Fine/Coarse 1 RW 0 */ + GmacTSCUPDTCoarse = 0x00000000, /* 0=> Time Stamp update method is coarse */ + GmacTSCUPDTFine = 0x00000002, /* 1=> Time Stamp update method is fine */ + + GmacTSENA = 0x00000001, /* Time Stamp Enable 0 RW 0 */ }; -/* GmacTSSubSecIncr = 0x0704, 8 bit value by which sub second register is incremented : only when IEEE 1588 time stamping without external timestamp input */ +/* GmacTSSubSecIncr = 0x0704, 8 bit value by which sub second register is incremented : only when IEEE 1588 time stamping without external timestamp input */ enum GmacTSSubSecIncrReg { GmacSSINCMsk = 0x000000FF, /* Only Lower 8 bits are valid bits 7:0 RW 00 */ }; -/* GmacTSLow = 0x070C, Indicates whether the timestamp low count is positive or negative; for Adv timestamp it is always zero */ +/* GmacTSLow = 0x070C, Indicates whether the timestamp low count is positive or negative; for Adv timestamp it is always zero */ enum GmacTSSign { GmacTSSign = 0x80000000, /* PSNT 31 RW 0 */ @@ -1496,23 +1496,23 @@ enum GmacTSSign GmacTSNegative = 0x80000000, }; -/*GmacTargetTimeLow = 0x0718, 32 bit nano seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */ +/*GmacTargetTimeLow = 0x0718, 32 bit nano seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */ enum GmacTSLowReg { GmacTSDecThr = 0x3B9AC9FF, /*when TSCTRLSSR is set the max value for GmacTargetTimeLowReg and GmacTimeStampLow register is 0x3B9AC9FF at 1ns precision */ }; /* GmacTSHighWord = 0x0724, Time Stamp Higher Word Register (Version 2 only); only lower 16 bits are valid */ -enum GmacTSHighWordReg +enum GmacTSHighWordReg { - GmacTSHighWordMask = 0x0000FFFF, /* Time Stamp Higher work register has only lower 16 bits valid */ + GmacTSHighWordMask = 0x0000FFFF, /* Time Stamp Higher work register has only lower 16 bits valid */ }; /*GmacTSStatus = 0x0728, Time Stamp Status Register */ enum GmacTSStatusReg { GmacTSTargTimeReached = 0x00000002, /* Time Stamp Target Time Reached 1 RO 0 */ GmacTSSecondsOverflow = 0x00000001, /* Time Stamp Seconds Overflow 0 RO 0 */ -}; +}; /********************************************************** @@ -1527,9 +1527,9 @@ void synopGMAC_TS_int_disable(synopGMACdevice *gmacdev); void synopGMAC_TS_mac_addr_filt_enable(synopGMACdevice *gmacdev); void synopGMAC_TS_mac_addr_filt_disable(synopGMACdevice *gmacdev); void synopGMAC_TS_set_clk_type(synopGMACdevice *gmacdev, u32 clk_type); -void synopGMAC_TS_master_enable(synopGMACdevice *gmacdev); // Only for Ordinary clock and Boundary clock and "Advanced Time Stamp" -void synopGMAC_TS_master_disable(synopGMACdevice *gmacdev); // Only for Ordinary clock and Boundary clock and "Advanced Time Stamp" -void synopGMAC_TS_event_enable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" +void synopGMAC_TS_master_enable(synopGMACdevice *gmacdev); // Only for Ordinary clock and Boundary clock and "Advanced Time Stamp" +void synopGMAC_TS_master_disable(synopGMACdevice *gmacdev); // Only for Ordinary clock and Boundary clock and "Advanced Time Stamp" +void synopGMAC_TS_event_enable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" void synopGMAC_TS_event_disable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" void synopGMAC_TS_IPV4_enable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" void synopGMAC_TS_IPV4_disable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" @@ -1540,7 +1540,7 @@ void synopGMAC_TS_ptp_over_ethernet_disable(synopGMACdevice *gmacdev); // void synopGMAC_TS_pkt_snoop_ver2(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" void synopGMAC_TS_pkt_snoop_ver1(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" -void synopGMAC_TS_digital_rollover_enable(synopGMACdevice *gmacdev); +void synopGMAC_TS_digital_rollover_enable(synopGMACdevice *gmacdev); void synopGMAC_TS_binary_rollover_enable(synopGMACdevice *gmacdev); void synopGMAC_TS_all_frames_enable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" void synopGMAC_TS_all_frames_disable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" @@ -1549,11 +1549,11 @@ s32 synopGMAC_TS_addend_update(synopGMACdevice *gmacdev, u32 addend_value); s32 synopGMAC_TS_timestamp_update(synopGMACdevice *gmacdev, u32 high_value, u32 low_value); s32 synopGMAC_TS_timestamp_init(synopGMACdevice *gmacdev, u32 high_value, u32 low_value); -void synopGMAC_TS_coarse_update(synopGMACdevice *gmacdev); // Only if "fine correction" enabled -void synopGMAC_TS_fine_update(synopGMACdevice *gmacdev); // Only if "fine correction" enabled +void synopGMAC_TS_coarse_update(synopGMACdevice *gmacdev); // Only if "fine correction" enabled +void synopGMAC_TS_fine_update(synopGMACdevice *gmacdev); // Only if "fine correction" enabled void synopGMAC_TS_subsecond_init(synopGMACdevice *gmacdev, u32 sub_sec_inc_val); // Update should happen making use of subsecond mask -void synopGMAC_TS_read_timestamp(synopGMACdevice *gmacdev, u16 * higher_sec_val, +void synopGMAC_TS_read_timestamp(synopGMACdevice *gmacdev, u16 * higher_sec_val, u32 * sec_val, u32 * sub_sec_val); // Reads the timestamp low,high and higher(Ver2) registers in the the struct pointer; readonly contents void synopGMAC_TS_load_target_timestamp(synopGMACdevice *gmacdev, u32 sec_val, u32 sub_sec_val); //Loads the timestamp target register with the values provided @@ -1571,7 +1571,7 @@ s32 synopGMAC_read_phy_reg(u32 RegBase,u32 PhyBase, u32 RegOffset, u16 * data); s32 synopGMAC_write_phy_reg(u32 RegBase, u32 PhyBase, u32 RegOffset, u16 data); s32 synopGMAC_phy_loopback(synopGMACdevice *gmacdev, bool loopback); s32 synopGMAC_read_version (synopGMACdevice * gmacdev) ; -s32 synopGMAC_reset (synopGMACdevice * gmacdev ); +s32 synopGMAC_reset (synopGMACdevice * gmacdev ); s32 synopGMAC_dma_bus_mode_init(synopGMACdevice * gmacdev, u32 init_value ); s32 synopGMAC_dma_control_init(synopGMACdevice * gmacdev, u32 init_value ); void synopGMAC_wd_enable(synopGMACdevice * gmacdev); @@ -1669,15 +1669,15 @@ bool synopGMAC_is_rx_desc_chained(DmaDesc * desc); bool synopGMAC_is_tx_desc_chained(DmaDesc * desc); void synopGMAC_get_desc_data(DmaDesc * desc, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2); #ifdef ENH_DESC_8W -s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2, - u32 * Ext_Status, u32 * Time_Stamp_High, u32 * Time_Stamp_low); +s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2, + u32 * Ext_Status, u32 * Time_Stamp_High, u32 * Time_Stamp_low); #else s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2 ); #endif s32 synopGMAC_set_tx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u32 Data1, u32 Buffer2, u32 Length2, u32 Data2,u32 offload_needed,u32 * index,DmaDesc *Dpr); s32 synopGMAC_set_rx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u32 Data1, u32 Buffer2, u32 Length2, u32 Data2); #ifdef ENH_DESC_8W -s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2, +s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2, u32 * Ext_Status, u32 * Time_Stamp_High, u32 * Time_Stamp_low); #else s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2); @@ -1698,8 +1698,8 @@ void synopGMAC_take_desc_ownership_tx(synopGMACdevice * gmacdev); void synopGMAC_disable_dma_tx(synopGMACdevice * gmacdev); void synopGMAC_disable_dma_rx(synopGMACdevice * gmacdev); /******Following APIs are valid only for Enhanced Descriptor from 3.50a release onwards*******/ -bool synopGMAC_is_ext_status(synopGMACdevice *gmacdev,u32 status); -bool synopGMAC_ES_is_IP_header_error(synopGMACdevice *gmacdev,u32 ext_status); +bool synopGMAC_is_ext_status(synopGMACdevice *gmacdev,u32 status); +bool synopGMAC_ES_is_IP_header_error(synopGMACdevice *gmacdev,u32 ext_status); bool synopGMAC_ES_is_rx_checksum_bypassed(synopGMACdevice *gmacdev,u32 ext_status); bool synopGMAC_ES_is_IP_payload_error(synopGMACdevice *gmacdev,u32 ext_status); /*******************PMT APIs***************************************/ diff --git a/bsp/ls1cdev/drivers/net/synopGMAC_Host.h b/bsp/ls1cdev/drivers/net/synopGMAC_Host.h index e6d31d551d..d9cada37da 100644 --- a/bsp/ls1cdev/drivers/net/synopGMAC_Host.h +++ b/bsp/ls1cdev/drivers/net/synopGMAC_Host.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -21,35 +21,35 @@ struct net_device_stats { - unsigned long rx_packets; /* total packets received */ - unsigned long tx_packets; /* total packets transmitted */ - unsigned long rx_bytes; /* total bytes received */ - unsigned long tx_bytes; /* total bytes transmitted */ - unsigned long rx_errors; /* bad packets received */ - unsigned long tx_errors; /* packet transmit problems */ - unsigned long rx_dropped; /* no space in linux buffers */ - unsigned long tx_dropped; /* no space available in linux */ - unsigned long multicast; /* multicast packets received */ - unsigned long collisions; - - /* detailed rx_errors: */ - unsigned long rx_length_errors; - unsigned long rx_over_errors; /* receiver ring buff overflow */ - unsigned long rx_crc_errors; /* recved pkt with crc error */ - unsigned long rx_frame_errors; /* recv'd frame alignment error */ - unsigned long rx_fifo_errors; /* recv'r fifo overrun */ - unsigned long rx_missed_errors; /* receiver missed packet */ - - /* detailed tx_errors */ - unsigned long tx_aborted_errors; - unsigned long tx_carrier_errors; - unsigned long tx_fifo_errors; - unsigned long tx_heartbeat_errors; - unsigned long tx_window_errors; - - /* for cslip etc */ - unsigned long rx_compressed; - unsigned long tx_compressed; + unsigned long rx_packets; /* total packets received */ + unsigned long tx_packets; /* total packets transmitted */ + unsigned long rx_bytes; /* total bytes received */ + unsigned long tx_bytes; /* total bytes transmitted */ + unsigned long rx_errors; /* bad packets received */ + unsigned long tx_errors; /* packet transmit problems */ + unsigned long rx_dropped; /* no space in linux buffers */ + unsigned long tx_dropped; /* no space available in linux */ + unsigned long multicast; /* multicast packets received */ + unsigned long collisions; + + /* detailed rx_errors: */ + unsigned long rx_length_errors; + unsigned long rx_over_errors; /* receiver ring buff overflow */ + unsigned long rx_crc_errors; /* recved pkt with crc error */ + unsigned long rx_frame_errors; /* recv'd frame alignment error */ + unsigned long rx_fifo_errors; /* recv'r fifo overrun */ + unsigned long rx_missed_errors; /* receiver missed packet */ + + /* detailed tx_errors */ + unsigned long tx_aborted_errors; + unsigned long tx_carrier_errors; + unsigned long tx_fifo_errors; + unsigned long tx_heartbeat_errors; + unsigned long tx_window_errors; + + /* for cslip etc */ + unsigned long rx_compressed; + unsigned long tx_compressed; }; diff --git a/bsp/ls1cdev/drivers/net/synopGMAC_debug.h b/bsp/ls1cdev/drivers/net/synopGMAC_debug.h index 9766587e1a..bf2775bfc5 100644 --- a/bsp/ls1cdev/drivers/net/synopGMAC_debug.h +++ b/bsp/ls1cdev/drivers/net/synopGMAC_debug.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,8 +14,8 @@ //#define GMAC_DEBUG #include -#ifdef GMAC_DEBUG -#define DEBUG_MES rt_kprintf +#ifdef GMAC_DEBUG +#define DEBUG_MES rt_kprintf #else #define DEBUG_MES(...) #endif diff --git a/bsp/ls1cdev/drivers/net/synopGMAC_network_interface.h b/bsp/ls1cdev/drivers/net/synopGMAC_network_interface.h index 8ded91d359..578f4f59e2 100644 --- a/bsp/ls1cdev/drivers/net/synopGMAC_network_interface.h +++ b/bsp/ls1cdev/drivers/net/synopGMAC_network_interface.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -8,7 +8,7 @@ * 2017-08-24 chinesebear first version */ - + #ifndef SYNOP_GMAC_NETWORK_INTERFACE_H #define SYNOP_GMAC_NETWORK_INTERFACE_H 1 diff --git a/bsp/ls1cdev/drivers/net/synopGMAC_plat.c b/bsp/ls1cdev/drivers/net/synopGMAC_plat.c index 3dfbe077d7..95a8b13862 100644 --- a/bsp/ls1cdev/drivers/net/synopGMAC_plat.c +++ b/bsp/ls1cdev/drivers/net/synopGMAC_plat.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -8,7 +8,7 @@ * 2017-08-24 chinesebear first version */ - + #include "synopGMAC_plat.h" #include "synopGMAC_Dev.h" #include @@ -16,58 +16,58 @@ extern void flush_cache(unsigned long start_addr, unsigned long size); dma_addr_t __attribute__((weak)) gmac_dmamap(unsigned long va,u32 size) { - return VA_TO_PA (va); - //return UNCACHED_TO_PHYS(va); + return VA_TO_PA (va); + //return UNCACHED_TO_PHYS(va); } /** - * This is a wrapper function for Memory allocation routine. In linux Kernel + * This is a wrapper function for Memory allocation routine. In linux Kernel * it it kmalloc function * @param[in] bytes in bytes to allocate */ -void *plat_alloc_memory(u32 bytes) +void *plat_alloc_memory(u32 bytes) { //return (void*)malloc((size_t)bytes, M_DEVBUF, M_DONTWAIT); - void *buf = (void*)rt_malloc((u32)bytes); + void *buf = (void*)rt_malloc((u32)bytes); - flush_cache((unsigned long)buf, bytes); - return buf; + flush_cache((unsigned long)buf, bytes); + return buf; } /** - * This is a wrapper function for consistent dma-able Memory allocation routine. + * This is a wrapper function for consistent dma-able Memory allocation routine. * In linux Kernel, it depends on pci dev structure * @param[in] bytes in bytes to allocate */ -//void *plat_alloc_consistent_dmaable_memory(struct synopGMACdevice *dev, u32 size, u32 *addr) -void *plat_alloc_consistent_dmaable_memory(synopGMACdevice *pcidev, u32 size, u32 *addr) +//void *plat_alloc_consistent_dmaable_memory(struct synopGMACdevice *dev, u32 size, u32 *addr) +void *plat_alloc_consistent_dmaable_memory(synopGMACdevice *pcidev, u32 size, u32 *addr) { - void *buf; - buf = (void*)rt_malloc((u32)(size+16)); - //CPU_IOFlushDCache( buf,size, SYNC_W); - unsigned long i = (unsigned long)buf; -// rt_kprintf("size = %d\n", size); -// rt_kprintf("bufaddr = %p\n", buf); -// rt_kprintf("i%%16 == %d\n", i%16); - if(i%16 == 8){ - i += 8; - } - else if(i%16 == 4){ - i += 12; - } - else if(i%16 == 12){ - i += 4; - } - - flush_cache(i, size); - *addr =gmac_dmamap(i, size); - buf = (unsigned char *)CACHED_TO_UNCACHED(i); -// rt_kprintf("bufaddr = %p\n", buf); - return buf; + void *buf; + buf = (void*)rt_malloc((u32)(size+16)); + //CPU_IOFlushDCache( buf,size, SYNC_W); + unsigned long i = (unsigned long)buf; +// rt_kprintf("size = %d\n", size); +// rt_kprintf("bufaddr = %p\n", buf); +// rt_kprintf("i%%16 == %d\n", i%16); + if(i%16 == 8){ + i += 8; + } + else if(i%16 == 4){ + i += 12; + } + else if(i%16 == 12){ + i += 4; + } + + flush_cache(i, size); + *addr =gmac_dmamap(i, size); + buf = (unsigned char *)CACHED_TO_UNCACHED(i); +// rt_kprintf("bufaddr = %p\n", buf); + return buf; } @@ -78,46 +78,46 @@ void *plat_alloc_consistent_dmaable_memory(synopGMACdevice *pcidev, u32 size, u3 */ -//void plat_free_consistent_dmaable_memory(void * addr) -void plat_free_consistent_dmaable_memory(synopGMACdevice *pcidev, u32 size, void * addr,u32 dma_addr) +//void plat_free_consistent_dmaable_memory(void * addr) +void plat_free_consistent_dmaable_memory(synopGMACdevice *pcidev, u32 size, void * addr,u32 dma_addr) { - rt_free((void*)PHYS_TO_CACHED(UNCACHED_TO_PHYS(addr))); + rt_free((void*)PHYS_TO_CACHED(UNCACHED_TO_PHYS(addr))); return; } /** - * This is a wrapper function for Memory free routine. In linux Kernel + * This is a wrapper function for Memory free routine. In linux Kernel * it it kfree function * @param[in] buffer pointer to be freed */ -void plat_free_memory(void *buffer) +void plat_free_memory(void *buffer) { - rt_free(buffer); - return ; + rt_free(buffer); + return ; } dma_addr_t plat_dma_map_single(void *hwdev, void *ptr, - u32 size) + u32 size) { - unsigned long addr = (unsigned long) ptr; + unsigned long addr = (unsigned long) ptr; //CPU_IOFlushDCache(addr,size, direction); - flush_cache(addr, size); + flush_cache(addr, size); return gmac_dmamap(addr, size); } /** - * This is a wrapper function for platform dependent delay - * Take care while passing the argument to this function + * This is a wrapper function for platform dependent delay + * Take care while passing the argument to this function * @param[in] buffer pointer to be freed */ void plat_delay(u32 delay) { - while (delay--); - return; + while (delay--); + return; } diff --git a/bsp/ls1cdev/drivers/net/synopGMAC_plat.h b/bsp/ls1cdev/drivers/net/synopGMAC_plat.h index cec6473746..da15536012 100644 --- a/bsp/ls1cdev/drivers/net/synopGMAC_plat.h +++ b/bsp/ls1cdev/drivers/net/synopGMAC_plat.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -8,12 +8,12 @@ * 2017-08-24 chinesebear first version */ - - + + #ifndef SYNOP_GMAC_PLAT_H #define SYNOP_GMAC_PLAT_H 1 -/* sw +/* sw #include #include #include @@ -26,7 +26,7 @@ //#include "GMAC_Pmon.h" //#include "synopGMAC_Host.h" #include -//sw: copy the type define into here +//sw: copy the type define into here #define IOCTL_READ_REGISTER SIOCDEVPRIVATE+1 #define IOCTL_WRITE_REGISTER SIOCDEVPRIVATE+2 #define IOCTL_READ_IPSTRUCT SIOCDEVPRIVATE+3 @@ -66,18 +66,18 @@ typedef int bool; #define VA_TO_PA(x) UNCACHED_TO_PHYS(x) -/* sw -#define TR0(fmt, args...) printk(KERN_CRIT "SynopGMAC: " fmt, ##args) +/* sw +#define TR0(fmt, args...) printk(KERN_CRIT "SynopGMAC: " fmt, ##args) #ifdef DEBUG #undef TR # define TR(fmt, args...) printk(KERN_CRIT "SynopGMAC: " fmt, ##args) #else -# define TR(fmt, args...) // not debugging: nothing +# define TR(fmt, args...) // not debugging: nothing #endif */ /* -#define TR0(fmt, args...) printf("SynopGMAC: " fmt, ##args) +#define TR0(fmt, args...) printf("SynopGMAC: " fmt, ##args) */ /* @@ -85,21 +85,21 @@ typedef int bool; #undef TR # define TR(fmt, args...) printf("SynopGMAC: " fmt, ##args) #else -//# define TR(fmt, args...) // not debugging: nothing -#define TR(fmt, args...) printf("SynopGMAC: " fmt, ##args) +//# define TR(fmt, args...) // not debugging: nothing +#define TR(fmt, args...) printf("SynopGMAC: " fmt, ##args) #endif */ //sw: nothing to display -#define TR0(fmt, args...) //rt_kprintf(fmt, ##args) -#define TR(fmt, args...) //rt_kprintf(fmt, ##args) +#define TR0(fmt, args...) //rt_kprintf(fmt, ##args) +#define TR(fmt, args...) //rt_kprintf(fmt, ##args) //#define TR rt_kprintf //typedef int bool; enum synopGMAC_boolean - { + { false = 0, - true = 1 + true = 1 }; @@ -110,9 +110,9 @@ enum synopGMAC_boolean * */ -#define LE32_TO_CPU __le32_to_cpu -#define BE32_TO_CPU __be32_to_cpu -#define CPU_TO_LE32 __cpu_to_le32 +#define LE32_TO_CPU __le32_to_cpu +#define BE32_TO_CPU __be32_to_cpu +#define CPU_TO_LE32 __cpu_to_le32 /* Error Codes */ #define ESYNOPGMACNOERR 0 @@ -122,15 +122,15 @@ enum synopGMAC_boolean struct Network_interface_data { - u32 unit; - u32 addr; - u32 data; + u32 unit; + u32 addr; + u32 data; }; /** * These are the wrapper function prototypes for OS/platform related routines - */ + */ void * plat_alloc_memory(u32 ); void plat_free_memory(void *); @@ -143,10 +143,10 @@ void plat_delay(u32); /** * The Low level function to read register contents from Hardware. - * - * @param[in] pointer to the base of register map + * + * @param[in] pointer to the base of register map * @param[in] Offset from the base - * \return Returns the register contents + * \return Returns the register contents */ static u32 synopGMACReadReg(u32 RegBase, u32 RegOffset) { @@ -166,43 +166,43 @@ static u32 synopGMACReadReg(u32 RegBase, u32 RegOffset) /** * The Low level function to write to a register in Hardware. - * - * @param[in] pointer to the base of register map + * + * @param[in] pointer to the base of register map * @param[in] Offset from the base - * @param[in] Data to be written - * \return void + * @param[in] Data to be written + * \return void */ static void synopGMACWriteReg(u32 RegBase, u32 RegOffset, u32 RegData ) { u32 addr; - addr = RegBase + (u32)RegOffset; + addr = RegBase + (u32)RegOffset; // rt_kprintf("%s RegBase = 0x%08x RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__,(u32) RegBase, RegOffset, RegData ); #if SYNOP_REG_DEBUG TR("%s RegBase = 0x%08x RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__,(u32) RegBase, RegOffset, RegData ); #endif - *(volatile u32 *)addr = RegData; + *(volatile u32 *)addr = RegData; - if(addr == 0xbfe1100c) - DEBUG_MES("regdata = %08x\n", RegData); + if(addr == 0xbfe1100c) + DEBUG_MES("regdata = %08x\n", RegData); return; } /** * The Low level function to set bits of a register in Hardware. - * - * @param[in] pointer to the base of register map + * + * @param[in] pointer to the base of register map * @param[in] Offset from the base - * @param[in] Bit mask to set bits to logical 1 - * \return void + * @param[in] Bit mask to set bits to logical 1 + * \return void */ static void synopGMACSetBits(u32 RegBase, u32 RegOffset, u32 BitPos) { //u64 addr = (u64)RegBase + (u64)RegOffset; u32 data; data = synopGMACReadReg(RegBase, RegOffset); - data |= BitPos; + data |= BitPos; synopGMACWriteReg(RegBase, RegOffset, data); // writel(data,(void *)addr); #if SYNOP_REG_DEBUG @@ -214,17 +214,17 @@ static void synopGMACSetBits(u32 RegBase, u32 RegOffset, u32 BitPos) /** * The Low level function to clear bits of a register in Hardware. - * - * @param[in] pointer to the base of register map + * + * @param[in] pointer to the base of register map * @param[in] Offset from the base - * @param[in] Bit mask to clear bits to logical 0 - * \return void + * @param[in] Bit mask to clear bits to logical 0 + * \return void */ static void synopGMACClearBits(u32 RegBase, u32 RegOffset, u32 BitPos) { u32 data; data = synopGMACReadReg(RegBase, RegOffset); - data &= (~BitPos); + data &= (~BitPos); synopGMACWriteReg(RegBase, RegOffset, data); #if SYNOP_REG_DEBUG TR("%s !!!!!!!!!!!!! RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, RegOffset, data ); @@ -234,21 +234,21 @@ static void synopGMACClearBits(u32 RegBase, u32 RegOffset, u32 BitPos) /** * The Low level function to Check the setting of the bits. - * - * @param[in] pointer to the base of register map + * + * @param[in] pointer to the base of register map * @param[in] Offset from the base - * @param[in] Bit mask to set bits to logical 1 + * @param[in] Bit mask to set bits to logical 1 * \return returns TRUE if set to '1' returns FALSE if set to '0'. Result undefined there are no bit set in the BitPos argument. - * + * */ static bool synopGMACCheckBits(u32 RegBase, u32 RegOffset, u32 BitPos) { u32 data; data = synopGMACReadReg(RegBase, RegOffset); - data &= BitPos; + data &= BitPos; if(data) return true; - else return false; + else return false; } diff --git a/bsp/ls1cdev/drivers/net/synopGMAC_types.h b/bsp/ls1cdev/drivers/net/synopGMAC_types.h index 88504eebf7..d8cf93a24a 100644 --- a/bsp/ls1cdev/drivers/net/synopGMAC_types.h +++ b/bsp/ls1cdev/drivers/net/synopGMAC_types.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,4 +22,4 @@ typedef signed int s32; typedef u32 dma_addr_t; -#endif /*__TYPES__H*/ +#endif /*__TYPES__H*/ diff --git a/bsp/ls1cdev/drivers/touch.c b/bsp/ls1cdev/drivers/touch.c index 37a4b19213..1535faf444 100644 --- a/bsp/ls1cdev/drivers/touch.c +++ b/bsp/ls1cdev/drivers/touch.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,13 +7,13 @@ * Date Author Notes * 2017-12-30 Sundm75 first version */ - + #include #include #include #include #include "ls1c.h" -#include "ls1c_gpio.h" +#include "ls1c_gpio.h" #include "ls1c_spi.h" #include "drv_spi.h" #include "touch.h" @@ -44,7 +44,7 @@ TOUCH INT: 84 */ #define IS_TOUCH_UP() gpio_get(TOUCH_INT_PIN) -#define led_gpio 52 // led1指示 +#define led_gpio 52 // led1指示 #define DUMMY 0x00 @@ -88,12 +88,12 @@ s A2-A0 MODE SER/DFR PD1-PD0 #if defined(_ILI_HORIZONTAL_DIRECTION_) #define MIN_X_DEFAULT 2047 #define MAX_X_DEFAULT 47 -#define MIN_Y_DEFAULT 102 -#define MAX_Y_DEFAULT 1939 +#define MIN_Y_DEFAULT 102 +#define MAX_Y_DEFAULT 1939 #else #define MIN_X_DEFAULT 47 #define MAX_X_DEFAULT 2047 -#define MIN_Y_DEFAULT 1939 +#define MIN_Y_DEFAULT 1939 #define MAX_Y_DEFAULT 102 #endif @@ -105,29 +105,29 @@ s A2-A0 MODE SER/DFR PD1-PD0 /*宏定义 */ -#define TOUCH_SPI_X SPI1 -#define TOUCH_INT_PIN 84 -#define TOUCH_CS_PIN 49 +#define TOUCH_SPI_X SPI1 +#define TOUCH_INT_PIN 84 +#define TOUCH_CS_PIN 49 #define TOUCH_SCK_PIN 46 #define TOUCH_MISO_PIN 47 -#define TOUCH_MOSI_PIN 48 +#define TOUCH_MOSI_PIN 48 /*创建结构体将需要用到的东西进行打包*/ -struct rtgui_touch_device +struct rtgui_touch_device { struct rt_device parent; /* 用于注册设备*/ - rt_uint16_t x, y; /* 记录读取到的位置值 */ + rt_uint16_t x, y; /* 记录读取到的位置值 */ - rt_bool_t calibrating; /* 触摸校准标志 */ - rt_touch_calibration_func_t calibration_func;/* 触摸函数 函数指针 */ + rt_bool_t calibrating; /* 触摸校准标志 */ + rt_touch_calibration_func_t calibration_func;/* 触摸函数 函数指针 */ - rt_uint16_t min_x, max_x; /* 校准后 X 方向最小 最大值 */ + rt_uint16_t min_x, max_x; /* 校准后 X 方向最小 最大值 */ rt_uint16_t min_y, max_y; /* 校准后 Y 方向最小 最大值 */ - struct rt_spi_device * spi_device; /* SPI 设备 用于通信 */ - struct rt_event event; /* 事件同步，用于“笔中断” */ + struct rt_spi_device * spi_device; /* SPI 设备 用于通信 */ + struct rt_event event; /* 事件同步，用于“笔中断” */ }; static struct rtgui_touch_device *touch = RT_NULL; @@ -255,14 +255,14 @@ static void rtgui_touch_calculate(void) rt_uint32_t total_x = 0; rt_uint32_t total_y = 0; for(k=0; k<2; k++) - { + { // sorting the ADC value for(i=0; i tmpxy[k][j]) + if (tmpxy[k][min] > tmpxy[k][j]) min=j; } temp = tmpxy[k][i]; @@ -329,11 +329,11 @@ void ls1c_touch_irqhandler(void) /* TouchScreen */ { if(gpio_get(TOUCH_INT_PIN)==0) { - /* 触摸屏按下后操作 */ + /* 触摸屏按下后操作 */ if (gpio_level_low == gpio_get(led_gpio)) - gpio_set(led_gpio, gpio_level_high); + gpio_set(led_gpio, gpio_level_high); else - gpio_set(led_gpio, gpio_level_low); + gpio_set(led_gpio, gpio_level_low); touch_int_cmd(RT_FALSE); rt_event_send(&touch->event, 1); } @@ -341,19 +341,19 @@ void ls1c_touch_irqhandler(void) /* TouchScreen */ /*管脚初始化，配置中断打开SPI1 CS0 设备*/ rt_inline void touch_init(void) -{ +{ unsigned int touch_int_gpio = TOUCH_INT_PIN; // 触摸屏中断 - int touch_irq = LS1C_GPIO_TO_IRQ(touch_int_gpio); - - // 初始化按键中断 - gpio_set_irq_type(touch_int_gpio, IRQ_TYPE_EDGE_FALLING); - rt_hw_interrupt_install(touch_irq, ls1c_touch_irqhandler, RT_NULL, "touch"); - rt_hw_interrupt_umask(touch_irq); - gpio_init(touch_int_gpio, gpio_mode_input); - - // 初始化led - gpio_init(led_gpio, gpio_mode_output); - gpio_set(led_gpio, gpio_level_high); + int touch_irq = LS1C_GPIO_TO_IRQ(touch_int_gpio); + + // 初始化按键中断 + gpio_set_irq_type(touch_int_gpio, IRQ_TYPE_EDGE_FALLING); + rt_hw_interrupt_install(touch_irq, ls1c_touch_irqhandler, RT_NULL, "touch"); + rt_hw_interrupt_umask(touch_irq); + gpio_init(touch_int_gpio, gpio_mode_input); + + // 初始化led + gpio_init(led_gpio, gpio_mode_output); + gpio_set(led_gpio, gpio_level_high); } @@ -363,7 +363,7 @@ static rt_err_t rtgui_touch_init (rt_device_t dev) rt_uint8_t send; rt_uint8_t recv_buffer[2]; struct rtgui_touch_device * touch_device = (struct rtgui_touch_device *)dev; - + touch_init(); rt_kprintf("touch_init ...\n"); send = START | DIFFERENTIAL | POWER_MODE0; @@ -440,18 +440,18 @@ static void touch_thread_entry(void *parameter) emouse.x = touch->x; emouse.y = touch->y; - if(touch_down != RT_TRUE) - { + if(touch_down != RT_TRUE) + { touch_int_cmd(RT_TRUE); break; - } + } if ((touch->calibrating == RT_TRUE) && (touch->calibration_func != RT_NULL)) { /* 触摸校准处理 */ /* callback function */ touch->calibration_func(emouse.x, emouse.y); - + } else { @@ -482,7 +482,7 @@ static void touch_thread_entry(void *parameter) /* calculation */ rtgui_touch_calculate(); - + /* send mouse event */ emouse.parent.type = RTGUI_EVENT_MOUSE_BUTTON; emouse.parent.sender = RT_NULL; @@ -532,7 +532,7 @@ static void touch_thread_entry(void *parameter) rt_err_t rtgui_touch_hw_init(const char * spi_device_name) { - rt_uint32_t arg[2]; + rt_uint32_t arg[2]; struct rt_device * spi_device; struct rt_thread * touch_thread; rt_err_t err; @@ -550,12 +550,12 @@ rt_err_t rtgui_touch_hw_init(const char * spi_device_name) rt_kprintf("Open spi1 failed %08X, exit thread....\n", err); return; } - + /* config spi */ { struct rt_spi_configuration cfg; cfg.data_width = 8; - cfg.mode = RT_SPI_MODE_0; + cfg.mode = RT_SPI_MODE_0; cfg.max_hz = 200 * 1000; /* 200K */ rt_spi_configure((struct rt_spi_device *)spi_device, &cfg); } @@ -573,7 +573,7 @@ rt_err_t rtgui_touch_hw_init(const char * spi_device_name) touch->min_x = MIN_X_DEFAULT; touch->max_x = MAX_X_DEFAULT; - touch->min_y = MIN_Y_DEFAULT; + touch->min_y = MIN_Y_DEFAULT; touch->max_y = MAX_Y_DEFAULT; /* init device structure */ @@ -584,7 +584,7 @@ rt_err_t rtgui_touch_hw_init(const char * spi_device_name) /* register touch device to RT-Thread */ rt_device_register(&(touch->parent), "touch", RT_DEVICE_FLAG_RDWR); - + touch_thread = rt_thread_create("touch_thread", touch_thread_entry, RT_NULL, diff --git a/bsp/ls1cdev/drivers/touch.h b/bsp/ls1cdev/drivers/touch.h index 5dac833510..93422e9c05 100644 --- a/bsp/ls1cdev/drivers/touch.h +++ b/bsp/ls1cdev/drivers/touch.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -10,20 +10,20 @@ #ifndef __TOUCH_H__ #define __TOUCH_H__ -#define RT_TOUCH_NORMAL 0 -#define RT_TOUCH_CALIBRATION_DATA 1 -#define RT_TOUCH_CALIBRATION 2 +#define RT_TOUCH_NORMAL 0 +#define RT_TOUCH_CALIBRATION_DATA 1 +#define RT_TOUCH_CALIBRATION 2 //#define SAVE_CALIBRATION - + rt_uint16_t touch_read_x(void); rt_uint16_t touch_read_y(void); void touch_config(void); - + rt_err_t rtgui_touch_hw_init(const char * spi_device_name); - + #endif diff --git a/bsp/ls1cdev/libraries/ls1c_can.c b/bsp/ls1cdev/libraries/ls1c_can.c index 437ef3ba84..4d45994e49 100644 --- a/bsp/ls1cdev/libraries/ls1c_can.c +++ b/bsp/ls1cdev/libraries/ls1c_can.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -23,15 +23,15 @@ unsigned char set_reset_mode(CAN_TypeDef* CANx) /* 关闭中断 */ CANx->IER = 0x00; - + for (i = 0; i < 100; i++) { if((status & CAN_Mode_RM) == CAN_Mode_RM) return 1; - + /* 设置复位*/ CANx->MOD |= ((unsigned char)CAN_Mode_RM); - + /*延时*/ delay_us(10); @@ -39,7 +39,7 @@ unsigned char set_reset_mode(CAN_TypeDef* CANx) status = CANx->MOD; } printf("\r\nSetting SJA1000 into reset mode failed!\r\n"); - return 0; + return 0; } static unsigned char set_normal_mode(CAN_TypeDef* CANx) @@ -49,20 +49,20 @@ static unsigned char set_normal_mode(CAN_TypeDef* CANx) /*检查复位标志*/ status = CANx->MOD; - + for (i = 0; i < 100; i++) { if((status & CAN_Mode_RM) != CAN_Mode_RM) { /*开所有中断 （总线错误中断不开）*/ - CANx->IER |= (~(unsigned char)CAN_IR_BEI); + CANx->IER |= (~(unsigned char)CAN_IR_BEI); return 1; } /* 设置正常工作模式*/ - CANx->MOD &= (~(unsigned char) CAN_Mode_RM); + CANx->MOD &= (~(unsigned char) CAN_Mode_RM); /*延时*/ - delay_us(10); - status = CANx->MOD; + delay_us(10); + status = CANx->MOD; } printf("\r\nSetting SJA1000 into normal mode failed!\r\n"); return 0; @@ -75,9 +75,9 @@ unsigned char set_start(CAN_TypeDef* CANx) /*复位RX错误计数器*/ CANx->RXERR = 0; /*时钟分频寄存器: PeliCAN模式; CBP=1,中止输入比较器, RX0激活*/ - CANx->CDR = 0xC0; - - return set_normal_mode(CANx); + CANx->CDR = 0xC0; + + return set_normal_mode(CANx); } unsigned char CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) @@ -89,64 +89,64 @@ unsigned char CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) status = CANx->MOD; if( status == 0xFF) { - printf("\n Probe can0 failed \r\n"); + printf("\n Probe can0 failed \r\n"); return CAN_InitStatus_Failed; } /* 进入复位模式 */ InitStatus = set_reset_mode(CANx); - - if((CAN_InitStruct->CAN_Mode & CAN_Mode_SM) == CAN_Mode_SM) + + if((CAN_InitStruct->CAN_Mode & CAN_Mode_SM) == CAN_Mode_SM) { /* 睡眠模式 1: 睡眠 0: 唤醒*/ - CANx->MOD|= (unsigned char)CAN_Mode_SM; + CANx->MOD|= (unsigned char)CAN_Mode_SM; } else { - CANx->MOD&=~ (unsigned char)CAN_Mode_SM; + CANx->MOD&=~ (unsigned char)CAN_Mode_SM; } - if((CAN_InitStruct->CAN_Mode & CAN_Mode_LOM) == CAN_Mode_LOM) + if((CAN_InitStruct->CAN_Mode & CAN_Mode_LOM) == CAN_Mode_LOM) { /*只听模式 1:只听 0:正常 */ - CANx->MOD|= (unsigned char)CAN_Mode_LOM; + CANx->MOD|= (unsigned char)CAN_Mode_LOM; } else { - CANx->MOD&=~ (unsigned char)CAN_Mode_LOM; + CANx->MOD&=~ (unsigned char)CAN_Mode_LOM; } - if((CAN_InitStruct->CAN_Mode & CAN_Mode_AFM) == CAN_Mode_AFM) + if((CAN_InitStruct->CAN_Mode & CAN_Mode_AFM) == CAN_Mode_AFM) { /*单滤波模式 1:单 0: 双*/ - CANx->MOD |= (unsigned char)CAN_Mode_AFM; + CANx->MOD |= (unsigned char)CAN_Mode_AFM; } else { - CANx->MOD&=~ (unsigned char)CAN_Mode_AFM; + CANx->MOD&=~ (unsigned char)CAN_Mode_AFM; } - if((CAN_InitStruct->CAN_Mode & CAN_Mode_STM) == CAN_Mode_STM) + if((CAN_InitStruct->CAN_Mode & CAN_Mode_STM) == CAN_Mode_STM) { /*自检测模式 1:自检测 0:正常 */ - CANx->MOD |= (unsigned char)CAN_Mode_STM; + CANx->MOD |= (unsigned char)CAN_Mode_STM; } else { CANx->MOD&=~ (unsigned char)CAN_Mode_STM; } - + /* 配置时钟频率 */ CANx->BTR0 = (( unsigned char )( unsigned char )CAN_InitStruct->CAN_Prescaler -1) | \ (unsigned char)CAN_InitStruct->CAN_SJW << 6; - + CANx->BTR1 = ((unsigned char)CAN_InitStruct->CAN_BS1) | \ ((unsigned char)CAN_InitStruct->CAN_BS2 << 4) | \ ((unsigned char)CAN_InitStruct->CAN_SJW<<7); /* 进入工作模式 */ - set_start(CANx); - + set_start(CANx); + /* 返回初始化结果 */ return InitStatus; } @@ -169,11 +169,11 @@ void CAN_FilterInit(CAN_TypeDef* CANx, CAN_FilterInitTypeDef * CAN_FilterInit thismask1 = (CAN_FilterInitStruct->IDMASK & 0xFFFF0000 )>>16; thisid2 = (CAN_FilterInitStruct->ID & 0x0000FFFF ); thismask2 = ( CAN_FilterInitStruct->IDMASK& 0x0000FFFF ); - rtr = CAN_FilterInitStruct->RTR; + rtr = CAN_FilterInitStruct->RTR; ide = CAN_FilterInitStruct->IDE; firstdata = CAN_FilterInitStruct->First_Data; datamask = CAN_FilterInitStruct->Data_Mask; - fcase = CAN_FilterInitStruct->MODE; + fcase = CAN_FilterInitStruct->MODE; if(ide == 0)//标准帧 { @@ -230,7 +230,7 @@ void CAN_FilterInit(CAN_TypeDef* CANx, CAN_FilterInitTypeDef * CAN_FilterInit /* 进入复位模式 */ set_reset_mode(CANx); - + if(fcase == 1)// 1-单滤波器模式 { /*单滤波模式 */ @@ -257,62 +257,62 @@ void CAN_FilterInit(CAN_TypeDef* CANx, CAN_FilterInitTypeDef * CAN_FilterInit unsigned char CAN_SetBps(CAN_TypeDef* CANx, Ls1c_CanBPS_t Bps) { unsigned char InitStatus = CAN_InitStatus_Failed; - unsigned char CAN_Prescaler, CAN_BS1, CAN_BS2, CAN_SJW; + unsigned char CAN_Prescaler, CAN_BS1, CAN_BS2, CAN_SJW; CAN_SJW = CAN_SJW_1tq; /* 进入复位模式 */ InitStatus = set_reset_mode(CANx); if( InitStatus == CAN_InitStatus_Failed) - return CAN_InitStatus_Failed; + return CAN_InitStatus_Failed; /* BaudRate= f(APB)/((1+BS1+BS2)(SJW*2*Prescaler))=126000000/[(1+7+2)*1*2*63]=100000=100K*/ /* BPS PRE BS1 BS2 最低40K - 1M 9 4 2 - 800K 8 7 2 - 500K 9 11 2 - 250K 36 4 2 - 125K 36 11 2 - 100K 63 7 2 - 50K 63 16 3` - 40K 63 16 8 + 1M 9 4 2 + 800K 8 7 2 + 500K 9 11 2 + 250K 36 4 2 + 125K 36 11 2 + 100K 63 7 2 + 50K 63 16 3` + 40K 63 16 8 */ switch (Bps) { - case LS1C_CAN1MBaud: + case LS1C_CAN1MBaud: CAN_Prescaler = 9; CAN_BS1 = CAN_BS1_4tq; CAN_BS2 = CAN_BS2_2tq; break; - case LS1C_CAN800kBaud: + case LS1C_CAN800kBaud: CAN_Prescaler = 8; CAN_BS1 = CAN_BS1_7tq; CAN_BS2 = CAN_BS2_2tq; break; - case LS1C_CAN500kBaud: + case LS1C_CAN500kBaud: CAN_Prescaler = 9; CAN_BS1 = CAN_BS1_11tq; CAN_BS2 = CAN_BS2_2tq; break; - case LS1C_CAN250kBaud: + case LS1C_CAN250kBaud: CAN_Prescaler = 36; CAN_BS1 = CAN_BS1_4tq; CAN_BS2 = CAN_BS2_2tq; break; - case LS1C_CAN125kBaud: + case LS1C_CAN125kBaud: CAN_Prescaler = 36; CAN_BS1 = CAN_BS1_11tq; CAN_BS2 = CAN_BS2_2tq; break; - case LS1C_CAN100kBaud: + case LS1C_CAN100kBaud: CAN_Prescaler = 63; CAN_BS1 = CAN_BS1_7tq; CAN_BS2 = CAN_BS2_2tq; break; - case LS1C_CAN50kBaud: + case LS1C_CAN50kBaud: CAN_Prescaler = 63; CAN_BS1 = CAN_BS1_16tq; CAN_BS2 = CAN_BS2_3tq; break; - case LS1C_CAN40kBaud: + case LS1C_CAN40kBaud: CAN_Prescaler = 63; CAN_BS1 = CAN_BS1_16tq; CAN_BS2 = CAN_BS2_8tq; @@ -326,13 +326,13 @@ unsigned char CAN_SetBps(CAN_TypeDef* CANx, Ls1c_CanBPS_t Bps) /* 配置时钟频率 */ CANx->BTR0 = (( unsigned char )CAN_Prescaler -1) | \ (unsigned char)CAN_SJW << 6; - + CANx->BTR1 = ((unsigned char)CAN_BS1) | \ ((unsigned char)CAN_BS2 << 4) | \ ((unsigned char)CAN_SJW<<7); /* 进入工作模式 */ - set_start(CANx); + set_start(CANx); /* 返回初始化结果 */ return CAN_InitStatus_Failed; } @@ -347,30 +347,30 @@ unsigned char CAN_SetMode(CAN_TypeDef* CANx, unsigned char mode) /* 进入复位模式 */ InitStatus = set_reset_mode(CANx); if( InitStatus == CAN_InitStatus_Failed) - return CAN_InitStatus_Failed; + return CAN_InitStatus_Failed; switch( mode ) { case 0://正常 - CANx->MOD &= ~(unsigned char)CAN_Mode_STM; - CANx->MOD &= ~(unsigned char)CAN_Mode_LOM; + CANx->MOD &= ~(unsigned char)CAN_Mode_STM; + CANx->MOD &= ~(unsigned char)CAN_Mode_LOM; break; case 1://只听 - CANx->MOD &= ~(unsigned char)CAN_Mode_STM; - CANx->MOD |= (unsigned char)CAN_Mode_LOM; + CANx->MOD &= ~(unsigned char)CAN_Mode_STM; + CANx->MOD |= (unsigned char)CAN_Mode_LOM; break; case 2://回环 - CANx->MOD |= (unsigned char)CAN_Mode_STM; - CANx->MOD &= ~(unsigned char)CAN_Mode_LOM; + CANx->MOD |= (unsigned char)CAN_Mode_STM; + CANx->MOD &= ~(unsigned char)CAN_Mode_LOM; break; case 3://只听回环 - CANx->MOD |= (unsigned char)CAN_Mode_STM; - CANx->MOD |= (unsigned char)CAN_Mode_LOM; + CANx->MOD |= (unsigned char)CAN_Mode_STM; + CANx->MOD |= (unsigned char)CAN_Mode_LOM; break; } /* 进入工作模式 */ - set_start(CANx); - + set_start(CANx); + /* 返回初始化结果 */ return CAN_InitStatus_Failed; } @@ -442,6 +442,6 @@ void CAN_Receive(CAN_TypeDef* CANx, CanRxMsg* RxMessage) RxMessage->Data[5] = (unsigned char)CANx->BUF[5]; RxMessage->Data[6] = (unsigned char)CANx->BUF[6]; RxMessage->Data[7] = (unsigned char)CANx->BUF[7]; - } + } } diff --git a/bsp/ls1cdev/libraries/ls1c_can.h b/bsp/ls1cdev/libraries/ls1c_can.h index b2b0f8efa8..4f06579249 100644 --- a/bsp/ls1cdev/libraries/ls1c_can.h +++ b/bsp/ls1cdev/libraries/ls1c_can.h @@ -1,9 +1,9 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * - * Change Logs: (Pelican Mode) + * Change Logs: (Pelican Mode) * Date Author Notes * 2018-01-06 sundm75 first version */ @@ -84,7 +84,7 @@ #define CAN_SR_TS ((unsigned char)0x20) /*!< 发送状态1: 发送 0: 空闲*/ #define CAN_SR_ES ((unsigned char)0x40) /*!< 出错状态1:出错 0: 正常 */ #define CAN_SR_BS ((unsigned char)0x80) /*!< 总线状态1: 关闭 0: 开启 */ - + /************************** CAN_IR 中断寄存器位定义****************************/ #define CAN_IR_RI ((unsigned char)0x01) /*!< 接收中断 */ #define CAN_IR_TI ((unsigned char)0x02) /*!< 发送中断 */ @@ -94,7 +94,7 @@ #define CAN_IR_EPI ((unsigned char)0x20) /*!< 错误消极中断 */ #define CAN_IR_ALI ((unsigned char)0x40) /*!< 仲裁丢失中断 */ #define CAN_IR_BEI ((unsigned char)0x80) /*!< 总线错误中断 */ - + /************************* CAN_IER 中断使能寄存器位定义************************/ #define CAN_IER_RIE ((unsigned char)0x01) /*!< 接收中断使能 */ #define CAN_IER_TIE ((unsigned char)0x02) /*!< 发送中断使能 */ @@ -104,17 +104,17 @@ #define CAN_IER_EPIE ((unsigned char)0x20) /*!< 错误消极中断使能 */ #define CAN_IER_ALIE ((unsigned char)0x40) /*!< 仲裁丢失中断使能 */ #define CAN_IER_BEIE ((unsigned char)0x80) /*!< 总线错误中断使能 */ - -typedef enum + +typedef enum { - LS1C_CAN1MBaud=0, // 1 MBit/sec - LS1C_CAN800kBaud, // 800 kBit/sec - LS1C_CAN500kBaud, // 500 kBit/sec - LS1C_CAN250kBaud, // 250 kBit/sec - LS1C_CAN125kBaud, // 125 kBit/sec - LS1C_CAN100kBaud, // 100 kBit/sec - LS1C_CAN50kBaud, // 50 kBit/sec - LS1C_CAN40kBaud, // 40 kBit/sec + LS1C_CAN1MBaud=0, // 1 MBit/sec + LS1C_CAN800kBaud, // 800 kBit/sec + LS1C_CAN500kBaud, // 500 kBit/sec + LS1C_CAN250kBaud, // 250 kBit/sec + LS1C_CAN125kBaud, // 125 kBit/sec + LS1C_CAN100kBaud, // 100 kBit/sec + LS1C_CAN50kBaud, // 50 kBit/sec + LS1C_CAN40kBaud, // 40 kBit/sec }Ls1c_CanBPS_t; typedef struct @@ -143,12 +143,12 @@ typedef struct typedef struct { - unsigned char CAN_Prescaler; /* 波特率分频系数1 to 31. */ + unsigned char CAN_Prescaler; /* 波特率分频系数1 to 31. */ unsigned char CAN_Mode; /*0x10:睡眠0x08:单,双滤波 0x40:正常工作0x20:只听 0x01:复位*/ unsigned char CAN_SJW; /*同步跳转宽度 */ unsigned char CAN_BS1; /*时间段1计数值*/ - unsigned char CAN_BS2; /*时间段2计数值*/ - + unsigned char CAN_BS2; /*时间段2计数值*/ + } CAN_InitTypeDef; typedef struct diff --git a/bsp/ls1cdev/libraries/ls1c_clock.c b/bsp/ls1cdev/libraries/ls1c_clock.c index 1ae621cbbb..7e3398746f 100644 --- a/bsp/ls1cdev/libraries/ls1c_clock.c +++ b/bsp/ls1cdev/libraries/ls1c_clock.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -56,7 +56,7 @@ unsigned long clk_get_pll_rate(void) ctrl = reg_read_32((volatile unsigned int *)LS1C_START_FREQ); pll_rate = (((ctrl & M_PLL) >> M_PLL_SHIFT) + ((ctrl & FRAC_N) >> FRAC_N_SHIFT)) * APB_CLK / 4; - + return pll_rate; } diff --git a/bsp/ls1cdev/libraries/ls1c_gpio.c b/bsp/ls1cdev/libraries/ls1c_gpio.c index 4bf6b7a20b..bbaf446285 100644 --- a/bsp/ls1cdev/libraries/ls1c_gpio.c +++ b/bsp/ls1cdev/libraries/ls1c_gpio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -61,7 +61,7 @@ volatile unsigned int *gpio_get_en_reg(unsigned int gpio) { volatile unsigned int *gpio_enx = NULL; // GPIO_ENx寄存器 unsigned int port = GPIO_GET_PORT(gpio); - + switch (port) { case 0: @@ -274,4 +274,4 @@ void gpio_set_irq_type(unsigned int gpio, gpio_irq_type_t type) } - + diff --git a/bsp/ls1cdev/libraries/ls1c_pin.c b/bsp/ls1cdev/libraries/ls1c_pin.c index 0a817abe07..43783521a6 100644 --- a/bsp/ls1cdev/libraries/ls1c_pin.c +++ b/bsp/ls1cdev/libraries/ls1c_pin.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/ls1cdev/libraries/ls1c_public.h b/bsp/ls1cdev/libraries/ls1c_public.h index 5d2390acec..249a767f58 100644 --- a/bsp/ls1cdev/libraries/ls1c_public.h +++ b/bsp/ls1cdev/libraries/ls1c_public.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -19,17 +19,17 @@ // pmon提供的打印函数，见main()函数 struct callvectors { - int (*open) (char *, int, int); - int (*close) (int); - int (*read) (int, void *, int); - int (*write) (int, void *, int); - long long (*lseek) (int, long long, int); - int (*printf) (const char *, ...); - void (*cacheflush) (void); - char *(*gets) (char *); + int (*open) (char *, int, int); + int (*close) (int); + int (*read) (int, void *, int); + int (*write) (int, void *, int); + long long (*lseek) (int, long long, int); + int (*printf) (const char *, ...); + void (*cacheflush) (void); + char *(*gets) (char *); }; -#define myprintf (*callvec->printf) -#define mygets (*callvec->gets) +#define myprintf (*callvec->printf) +#define mygets (*callvec->gets) extern struct callvectors *callvec; @@ -40,7 +40,7 @@ extern struct callvectors *callvec; typedef enum { - FALSE=0, + FALSE=0, TRUE=1 }BOOL; diff --git a/bsp/ls1cdev/libraries/ls1c_regs.h b/bsp/ls1cdev/libraries/ls1c_regs.h index 7947c2bfe0..91d9d32ab0 100644 --- a/bsp/ls1cdev/libraries/ls1c_regs.h +++ b/bsp/ls1cdev/libraries/ls1c_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -83,8 +83,8 @@ #define LS1C_REG_BASE_PWM3 (0xbfe5c030) //CAN基地址 -#define LS1C_REG_BASE_CAN0 (0xbfe50000) -#define LS1C_REG_BASE_CAN1 (0xbfe54000) +#define LS1C_REG_BASE_CAN0 (0xbfe50000) +#define LS1C_REG_BASE_CAN1 (0xbfe54000) // 中断配置寄存器 #define LS1C_INT0_SR (0xbfd01040) diff --git a/bsp/ls1cdev/libraries/ls1c_rtc.c b/bsp/ls1cdev/libraries/ls1c_rtc.c index 838f6a85c1..3ec20daaad 100644 --- a/bsp/ls1cdev/libraries/ls1c_rtc.c +++ b/bsp/ls1cdev/libraries/ls1c_rtc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -11,66 +11,66 @@ #include "ls1c_public.h" #include "ls1c_rtc.h" -#define LS1C_SEC_OFFSET (4) -#define LS1C_MIN_OFFSET (10) -#define LS1C_HOUR_OFFSET (16) -#define LS1C_DAY_OFFSET (21) -#define LS1C_MONTH_OFFSET (26) +#define LS1C_SEC_OFFSET (4) +#define LS1C_MIN_OFFSET (10) +#define LS1C_HOUR_OFFSET (16) +#define LS1C_DAY_OFFSET (21) +#define LS1C_MONTH_OFFSET (26) -#define LS1C_SEC_MASK (0x3f) -#define LS1C_MIN_MASK (0x3f) -#define LS1C_HOUR_MASK (0x1f) -#define LS1C_DAY_MASK (0x1f) -#define LS1C_MONTH_MASK (0x3f) -#define LS1C_YEAR_MASK (0xff) +#define LS1C_SEC_MASK (0x3f) +#define LS1C_MIN_MASK (0x3f) +#define LS1C_HOUR_MASK (0x1f) +#define LS1C_DAY_MASK (0x1f) +#define LS1C_MONTH_MASK (0x3f) +#define LS1C_YEAR_MASK (0xff) -#define ls1c_get_sec(t) (((t) >> LS1C_SEC_OFFSET) & LS1C_SEC_MASK) -#define ls1c_get_min(t) (((t) >> LS1C_MIN_OFFSET) & LS1C_MIN_MASK) -#define ls1c_get_hour(t) (((t) >> LS1C_HOUR_OFFSET) & LS1C_HOUR_MASK) -#define ls1c_get_day(t) (((t) >> LS1C_DAY_OFFSET) & LS1C_DAY_MASK) -#define ls1c_get_month(t) (((t) >> LS1C_MONTH_OFFSET) & LS1C_MONTH_MASK) +#define ls1c_get_sec(t) (((t) >> LS1C_SEC_OFFSET) & LS1C_SEC_MASK) +#define ls1c_get_min(t) (((t) >> LS1C_MIN_OFFSET) & LS1C_MIN_MASK) +#define ls1c_get_hour(t) (((t) >> LS1C_HOUR_OFFSET) & LS1C_HOUR_MASK) +#define ls1c_get_day(t) (((t) >> LS1C_DAY_OFFSET) & LS1C_DAY_MASK) +#define ls1c_get_month(t) (((t) >> LS1C_MONTH_OFFSET) & LS1C_MONTH_MASK) int RTC_SetTime(RTC_TypeDef *hrtc, RTC_TimeTypeDef *sTime) { - hrtc->SYS_TOYWRITE0 - = (sTime->Month << LS1C_MONTH_OFFSET) - | (sTime->Date << LS1C_DAY_OFFSET) - | (sTime->Hours << LS1C_HOUR_OFFSET) - | (sTime->Minutes << LS1C_MIN_OFFSET) - | (sTime->Seconds << LS1C_SEC_OFFSET); - hrtc->SYS_TOYWRITE1 = sTime->Year % 100; - printf("\r\ntoy_read0 = 0x%x, toy_read1 = 0x%x.\r\n", hrtc->SYS_TOYREAD0, hrtc->SYS_TOYREAD1); + hrtc->SYS_TOYWRITE0 + = (sTime->Month << LS1C_MONTH_OFFSET) + | (sTime->Date << LS1C_DAY_OFFSET) + | (sTime->Hours << LS1C_HOUR_OFFSET) + | (sTime->Minutes << LS1C_MIN_OFFSET) + | (sTime->Seconds << LS1C_SEC_OFFSET); + hrtc->SYS_TOYWRITE1 = sTime->Year % 100; + printf("\r\ntoy_read0 = 0x%x, toy_read1 = 0x%x.\r\n", hrtc->SYS_TOYREAD0, hrtc->SYS_TOYREAD1); return 0; } int RTC_GetTime(RTC_TypeDef *hrtc, RTC_TimeTypeDef *sTime) { - unsigned long toy_read0, toy_read1; + unsigned long toy_read0, toy_read1; toy_read0 = hrtc->SYS_TOYREAD0; - toy_read1 = hrtc->SYS_TOYREAD1; + toy_read1 = hrtc->SYS_TOYREAD1; sTime->Seconds = ls1c_get_sec(toy_read0); sTime->Minutes = ls1c_get_min(toy_read0); sTime->Hours = ls1c_get_hour(toy_read0); sTime->Date = ls1c_get_day(toy_read0); sTime->Month = ls1c_get_month(toy_read0); - sTime->Year = toy_read1 & LS1C_YEAR_MASK; + sTime->Year = toy_read1 & LS1C_YEAR_MASK; return 0 ; } unsigned char RTC_IsLeapYear(unsigned int nYear) { - if((nYear % 4U) != 0U) + if((nYear % 4U) != 0U) { return 0U; } - - if((nYear % 100U) != 0U) + + if((nYear % 100U) != 0U) { return 1U; } - + if((nYear % 400U) == 0U) { return 1U; @@ -86,7 +86,7 @@ unsigned char RTC_WeekDayNum(unsigned long nYear, unsigned char nMonth, unsigned unsigned long year = 0U, weekday = 0U; year = 2000U + nYear; - + if(nMonth < 3U) { /*D = { [(23 x month)/9] + day + 4 + year + [(year-1)/4] - [(year-1)/100] + [(year-1)/400] } mod 7*/ @@ -95,7 +95,7 @@ unsigned char RTC_WeekDayNum(unsigned long nYear, unsigned char nMonth, unsigned else { /*D = { [(23 x month)/9] + day + 4 + year + [year/4] - [year/100] + [year/400] - 2 } mod 7*/ - weekday = (((23U * nMonth)/9U) + nDay + 4U + year + (year/4U) - (year/100U) + (year/400U) - 2U ) % 7U; + weekday = (((23U * nMonth)/9U) + nDay + 4U + year + (year/4U) - (year/100U) + (year/400U) - 2U ) % 7U; } return (unsigned char)weekday; diff --git a/bsp/ls1cdev/libraries/ls1c_rtc.h b/bsp/ls1cdev/libraries/ls1c_rtc.h index dee8000d6b..e7589da078 100644 --- a/bsp/ls1cdev/libraries/ls1c_rtc.h +++ b/bsp/ls1cdev/libraries/ls1c_rtc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,7 +22,7 @@ typedef struct unsigned char Hours; /*0 ~ 23 */ unsigned char Minutes; /*0 ~ 59 */ unsigned char Seconds; /*0 ~ 59 */ -}RTC_TimeTypeDef; +}RTC_TimeTypeDef; typedef struct { diff --git a/bsp/ls1cdev/libraries/ls1c_spi.c b/bsp/ls1cdev/libraries/ls1c_spi.c index 6ad39d964c..13cd8dc620 100644 --- a/bsp/ls1cdev/libraries/ls1c_spi.c +++ b/bsp/ls1cdev/libraries/ls1c_spi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -53,7 +53,7 @@ void *ls1c_spi_get_base(unsigned char SPIx) void ls1c_spi_print_all_regs_info(void *spi_base) { printf("[%s] SPCR=0x%x, SPSR=0x%x, SPER=0x%x, SFC_PARAM=0x%x, SFC_SOFTCS=0x%x, SFC_TIMING=0x%x\r\n", - __FUNCTION__, + __FUNCTION__, reg_read_8(spi_base + LS1C_SPI_SPCR_OFFSET), reg_read_8(spi_base + LS1C_SPI_SPSR_OFFSET), reg_read_8(spi_base + LS1C_SPI_SPER_OFFSET), @@ -121,8 +121,8 @@ unsigned int ls1c_spi_get_div(unsigned int max_speed_hz) } break; } -/* - printf("[%s] clk=%ld, max_speed_hz=%d, div_tmp=%d, bit=%d\r\n", +/* + printf("[%s] clk=%ld, max_speed_hz=%d, div_tmp=%d, bit=%d\r\n", __FUNCTION__, clk, max_speed_hz, div_tmp, bit); */ return div_tmp; @@ -169,15 +169,15 @@ void ls1c_spi_set_mode(void *spi_base, unsigned char cpol, unsigned char cpha) unsigned char val = 0; val = reg_read_8(spi_base + LS1C_SPI_SPCR_OFFSET); - + // 设置时钟极性--cpol val &= (~LS1C_SPI_SPCR_CPOL_MASK); // cpol清0 val |= (cpol << LS1C_SPI_SPCR_CPOL_BIT); // 写入新的cpol - + // 设置时钟相位--cpha val &= (~LS1C_SPI_SPCR_CPHA_MASK); // cpha清0 val |= (cpha << LS1C_SPI_SPCR_CPHA_BIT); // 写入新的cpha - + reg_write_8(val, spi_base + LS1C_SPI_SPCR_OFFSET); return ; @@ -195,7 +195,7 @@ void ls1c_spi_set_cs(void *spi_base, unsigned char cs, int new_status) unsigned char val = 0; val = reg_read_8(spi_base + LS1C_SPI_SFC_SOFTCS_OFFSET); - val |= 0x01 << cs ; //对应的csen=1 + val |= 0x01 << cs ; //对应的csen=1 if (new_status) // cs = 1 { val |= (0x10 << cs); // 指定csn=1 @@ -223,7 +223,7 @@ void ls1c_spi_wait_txrx_done(void *spi_base) if (LS1C_SPI_SPSR_SPIF_MASK & reg_read_8(spi_base + LS1C_SPI_SPSR_OFFSET)) break; } - + return ; } diff --git a/bsp/ls1cdev/libraries/ls1c_spi.h b/bsp/ls1cdev/libraries/ls1c_spi.h index bd02dd8d17..3abcfa63cc 100644 --- a/bsp/ls1cdev/libraries/ls1c_spi.h +++ b/bsp/ls1cdev/libraries/ls1c_spi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/ls1cdev/libraries/ls1c_uart.c b/bsp/ls1cdev/libraries/ls1c_uart.c index fac2010964..5aefaf994e 100644 --- a/bsp/ls1cdev/libraries/ls1c_uart.c +++ b/bsp/ls1cdev/libraries/ls1c_uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -53,7 +53,7 @@ void *uart_get_base(ls1c_uart_t UARTx) case LS1C_UART1: base = (void *)LS1C_UART1_BASE; break; - + case LS1C_UART2: base = (void *)LS1C_UART2_BASE; break; @@ -61,7 +61,7 @@ void *uart_get_base(ls1c_uart_t UARTx) case LS1C_UART3: base = (void *)LS1C_UART3_BASE; break; - + case LS1C_UART4: base = (void *)LS1C_UART4_BASE; break; @@ -113,10 +113,10 @@ void uart_init(ls1c_uart_info_t *uart_info_p) // 禁止所有中断 reg_write_8(0, uart_base + LS1C_UART_IER_OFFSET); - + // 接收FIFO的中断申请Trigger为14字节，清空发送和接收FIFO，并复位 reg_write_8(0xc3, uart_base + LS1C_UART_FCR_OFFSET); - + // 设置波特率 reg_write_8(0x80, uart_base + LS1C_UART_LCR_OFFSET); baudrate_div = clk_get_cpu_rate() / 16 / uart_info_p->baudrate / 2; @@ -165,7 +165,7 @@ BOOL uart_is_transmit_empty(ls1c_uart_t uartx) void uart_putc(ls1c_uart_t uartx, unsigned char ch) { void *uart_base = uart_get_base(uartx); - + // 等待 while (FALSE == uart_is_transmit_empty(uartx)) ; @@ -205,7 +205,7 @@ void uart2_init(void) // 设置复用 pin_set_remap(tx_gpio, PIN_REMAP_SECOND); pin_set_remap(rx_gpio, PIN_REMAP_SECOND); - + // 初始化相关寄存器 debug_uart_info.UARTx = LS1C_UART2; debug_uart_info.baudrate = 115200; @@ -257,7 +257,7 @@ void uart_debug_putc(unsigned char ch) ls1c_uart_t uart_irqn_to_uartx(int IRQn) { ls1c_uart_t uartx = LS1C_UART2; - + switch (IRQn) { /* 串口UART00和UART01的中断号还待确定 @@ -273,47 +273,47 @@ ls1c_uart_t uart_irqn_to_uartx(int IRQn) case LS1C_UART1_IRQ: uartx = LS1C_UART1; break; - + case LS1C_UART2_IRQ: uartx = LS1C_UART2; break; - + case LS1C_UART3_IRQ: uartx = LS1C_UART3; break; - + case LS1C_UART4_IRQ: uartx = LS1C_UART4; break; - + case LS1C_UART5_IRQ: uartx = LS1C_UART5; break; - + case LS1C_UART6_IRQ: uartx = LS1C_UART6; break; - + case LS1C_UART7_IRQ: uartx = LS1C_UART7; break; - + case LS1C_UART8_IRQ: uartx = LS1C_UART8; break; - + case LS1C_UART9_IRQ: uartx = LS1C_UART9; break; - + case LS1C_UART10_IRQ: uartx = LS1C_UART10; break; - + case LS1C_UART11_IRQ: uartx = LS1C_UART11; break; - + default: uartx = LS1C_UART2; break; diff --git a/bsp/ls1cdev/libraries/ls1c_uart.h b/bsp/ls1cdev/libraries/ls1c_uart.h index 8d017dd767..0a95da236b 100644 --- a/bsp/ls1cdev/libraries/ls1c_uart.h +++ b/bsp/ls1cdev/libraries/ls1c_uart.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -31,63 +31,63 @@ #define LS1C_UART_MSB_OFFSET (1) // 分频锁存器2 /* interrupt enable register */ -#define IER_IRxE 0x1 /* 接收有效数据中断使能 */ -#define IER_ITxE 0x2 /* 传输保存寄存器为空中断使能 */ -#define IER_ILE 0x4 /* 接收器线路状态中断使能 */ -#define IER_IME 0x8 /* Modem状态中断使能 */ +#define IER_IRxE 0x1 /* 接收有效数据中断使能 */ +#define IER_ITxE 0x2 /* 传输保存寄存器为空中断使能 */ +#define IER_ILE 0x4 /* 接收器线路状态中断使能 */ +#define IER_IME 0x8 /* Modem状态中断使能 */ /* interrupt identification register */ -#define IIR_IMASK 0xf /* mask */ -#define IIR_RXTOUT 0xc /* receive timeout */ -#define IIR_RLS 0x6 /* receive line status */ -#define IIR_RXRDY 0x4 /* receive ready */ -#define IIR_TXRDY 0x2 /* transmit ready */ -#define IIR_NOPEND 0x1 /* nothing */ -#define IIR_MLSC 0x0 /* modem status */ -#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ +#define IIR_IMASK 0xf /* mask */ +#define IIR_RXTOUT 0xc /* receive timeout */ +#define IIR_RLS 0x6 /* receive line status */ +#define IIR_RXRDY 0x4 /* receive ready */ +#define IIR_TXRDY 0x2 /* transmit ready */ +#define IIR_NOPEND 0x1 /* nothing */ +#define IIR_MLSC 0x0 /* modem status */ +#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ /* fifo control register */ -#define FIFO_ENABLE 0x01 /* enable fifo */ -#define FIFO_RCV_RST 0x02 /* reset receive fifo */ -#define FIFO_XMT_RST 0x04 /* reset transmit fifo */ -#define FIFO_DMA_MODE 0x08 /* enable dma mode */ -#define FIFO_TRIGGER_1 0x00 /* trigger at 1 char */ -#define FIFO_TRIGGER_4 0x40 /* trigger at 4 chars */ -#define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */ -#define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */ +#define FIFO_ENABLE 0x01 /* enable fifo */ +#define FIFO_RCV_RST 0x02 /* reset receive fifo */ +#define FIFO_XMT_RST 0x04 /* reset transmit fifo */ +#define FIFO_DMA_MODE 0x08 /* enable dma mode */ +#define FIFO_TRIGGER_1 0x00 /* trigger at 1 char */ +#define FIFO_TRIGGER_4 0x40 /* trigger at 4 chars */ +#define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */ +#define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */ // 线路控制寄存器 /* character format control register */ -#define CFCR_DLAB 0x80 /* divisor latch */ -#define CFCR_SBREAK 0x40 /* send break */ -#define CFCR_PZERO 0x30 /* zero parity */ -#define CFCR_PONE 0x20 /* one parity */ -#define CFCR_PEVEN 0x10 /* even parity */ -#define CFCR_PODD 0x00 /* odd parity */ -#define CFCR_PENAB 0x08 /* parity enable */ -#define CFCR_STOPB 0x04 /* 2 stop bits */ -#define CFCR_8BITS 0x03 /* 8 data bits */ -#define CFCR_7BITS 0x02 /* 7 data bits */ -#define CFCR_6BITS 0x01 /* 6 data bits */ -#define CFCR_5BITS 0x00 /* 5 data bits */ +#define CFCR_DLAB 0x80 /* divisor latch */ +#define CFCR_SBREAK 0x40 /* send break */ +#define CFCR_PZERO 0x30 /* zero parity */ +#define CFCR_PONE 0x20 /* one parity */ +#define CFCR_PEVEN 0x10 /* even parity */ +#define CFCR_PODD 0x00 /* odd parity */ +#define CFCR_PENAB 0x08 /* parity enable */ +#define CFCR_STOPB 0x04 /* 2 stop bits */ +#define CFCR_8BITS 0x03 /* 8 data bits */ +#define CFCR_7BITS 0x02 /* 7 data bits */ +#define CFCR_6BITS 0x01 /* 6 data bits */ +#define CFCR_5BITS 0x00 /* 5 data bits */ /* modem control register */ -#define MCR_LOOPBACK 0x10 /* loopback */ -#define MCR_IENABLE 0x08 /* output 2 = int enable */ -#define MCR_DRS 0x04 /* output 1 = xxx */ -#define MCR_RTS 0x02 /* enable RTS */ -#define MCR_DTR 0x01 /* enable DTR */ +#define MCR_LOOPBACK 0x10 /* loopback */ +#define MCR_IENABLE 0x08 /* output 2 = int enable */ +#define MCR_DRS 0x04 /* output 1 = xxx */ +#define MCR_RTS 0x02 /* enable RTS */ +#define MCR_DTR 0x01 /* enable DTR */ /* line status register */ -#define LSR_RCV_FIFO 0x80 /* error in receive fifo */ -#define LSR_TSRE 0x40 /* transmitter empty */ -#define LSR_TXRDY 0x20 /* transmitter ready */ -#define LSR_BI 0x10 /* break detected */ -#define LSR_FE 0x08 /* framing error */ -#define LSR_PE 0x04 /* parity error */ -#define LSR_OE 0x02 /* overrun error */ -#define LSR_RXRDY 0x01 /* receiver ready */ -#define LSR_RCV_MASK 0x1f +#define LSR_RCV_FIFO 0x80 /* error in receive fifo */ +#define LSR_TSRE 0x40 /* transmitter empty */ +#define LSR_TXRDY 0x20 /* transmitter ready */ +#define LSR_BI 0x10 /* break detected */ +#define LSR_FE 0x08 /* framing error */ +#define LSR_PE 0x04 /* parity error */ +#define LSR_OE 0x02 /* overrun error */ +#define LSR_RXRDY 0x01 /* receiver ready */ +#define LSR_RCV_MASK 0x1f // 串口模块编号 diff --git a/bsp/ls1cdev/libraries/ls1c_wdog.c b/bsp/ls1cdev/libraries/ls1c_wdog.c index 4034281d10..774fa013b2 100644 --- a/bsp/ls1cdev/libraries/ls1c_wdog.c +++ b/bsp/ls1cdev/libraries/ls1c_wdog.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,13 +22,13 @@ static unsigned int WDT_timer = 0; /* 暂时为空 */ -unsigned int Wdog_Init(void) +unsigned int Wdog_Init(void) { return 0; } /* 配置看门狗使能寄存器(WDT_EN) */ -unsigned int Wdog_Enable(void) +unsigned int Wdog_Enable(void) { unsigned int ctrl; ctrl = (WDT_EN); @@ -39,7 +39,7 @@ unsigned int Wdog_Enable(void) } /* 配置看门狗失能寄存器(WDT_EN) */ -unsigned int Wdog_Disable(void) +unsigned int Wdog_Disable(void) { unsigned int ctrl; ctrl = (WDT_EN); @@ -49,7 +49,7 @@ unsigned int Wdog_Disable(void) } /* 配置看门狗设置寄存器 (WDT_SET) */ -unsigned int Wdog_Set(void) +unsigned int Wdog_Set(void) { unsigned int ctrl; ctrl = (WDT_SET); @@ -59,7 +59,7 @@ unsigned int Wdog_Set(void) } /* 配置看门狗设置寄存器 (WDT_SET) */ -unsigned int Wdog_Reset(void) +unsigned int Wdog_Reset(void) { unsigned int ctrl; ctrl = (WDT_SET); @@ -69,7 +69,7 @@ unsigned int Wdog_Reset(void) } /* 获得看门狗计数器(WDT_timer) 的值*/ -unsigned int Wdog_GetValue(void) +unsigned int Wdog_GetValue(void) { unsigned int cnt; cnt = (WDT_TIMER); @@ -77,7 +77,7 @@ unsigned int Wdog_GetValue(void) } /* 配置看门狗计数器(WDT_timer)的值*/ -unsigned int Wdog_LoadValue(unsigned int cnt) +unsigned int Wdog_LoadValue(unsigned int cnt) { WDT_TIMER = cnt; WDT_timer = cnt; @@ -85,7 +85,7 @@ unsigned int Wdog_LoadValue(unsigned int cnt) } /* 获得看门狗计数器设定值 */ -unsigned int Wdog_GetPreValue(void) +unsigned int Wdog_GetPreValue(void) { return WDT_timer; } diff --git a/bsp/ls1cdev/libraries/ls1c_wdog.h b/bsp/ls1cdev/libraries/ls1c_wdog.h index a4717eedbf..eeeb8ac475 100644 --- a/bsp/ls1cdev/libraries/ls1c_wdog.h +++ b/bsp/ls1cdev/libraries/ls1c_wdog.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/m16c62p/applications/application.c b/bsp/m16c62p/applications/application.c index 7693ef8862..35eb423193 100644 --- a/bsp/m16c62p/applications/application.c +++ b/bsp/m16c62p/applications/application.c @@ -44,7 +44,7 @@ int rt_application_init(void) sizeof(led_stack), RT_THREAD_PRIORITY_MAX / 2, 32); - + if (result == RT_EOK) rt_thread_startup(&led); diff --git a/bsp/m16c62p/applications/startup.c b/bsp/m16c62p/applications/startup.c index 322476b60d..a3c9448201 100644 --- a/bsp/m16c62p/applications/startup.c +++ b/bsp/m16c62p/applications/startup.c @@ -36,67 +36,67 @@ extern unsigned char user_ram_end; */ void rtthread_startup(void) { - /* init hardware interrupt */ - rt_hw_interrupt_init(); - - /* init board */ - rt_hw_board_init(); - - /* show version */ - rt_show_version(); - - /* init tick */ - rt_system_tick_init(); - - /* init kernel object */ - rt_system_object_init(); - - /* init timer system */ - rt_system_timer_init(); - + /* init hardware interrupt */ + rt_hw_interrupt_init(); + + /* init board */ + rt_hw_board_init(); + + /* show version */ + rt_show_version(); + + /* init tick */ + rt_system_tick_init(); + + /* init kernel object */ + rt_system_object_init(); + + /* init timer system */ + rt_system_timer_init(); + #ifdef RT_USING_HEAP #ifdef __ICCM16C__ - rt_system_heap_init(__segment_begin("DATA16_HEAP"), __segment_end("DATA16_HEAP")); + rt_system_heap_init(__segment_begin("DATA16_HEAP"), __segment_end("DATA16_HEAP")); #elif (defined (__GNUC__)) - rt_system_heap_init((void*)&user_ram_end, (void*)M16C62P_SRAM_END); + rt_system_heap_init((void*)&user_ram_end, (void*)M16C62P_SRAM_END); #endif #endif - /* init scheduler system */ - rt_system_scheduler_init(); + /* init scheduler system */ + rt_system_scheduler_init(); - /* init application */ - rt_application_init(); + /* init application */ + rt_application_init(); #ifdef RT_USING_FINSH - /* init finsh */ - finsh_system_init(); - finsh_set_device("uart0"); + /* init finsh */ + finsh_system_init(); + finsh_set_device("uart0"); #endif - /* init timer thread */ - rt_system_timer_thread_init(); - - /* init idle thread */ - rt_thread_idle_init(); - - /* start scheduler */ - rt_system_scheduler_start(); - - /* never reach here */ - return ; + /* init timer thread */ + rt_system_timer_thread_init(); + + /* init idle thread */ + rt_thread_idle_init(); + + /* start scheduler */ + rt_system_scheduler_start(); + + /* never reach here */ + return ; } int main(void) { - /* disable interrupt first */ - rt_hw_interrupt_disable(); + /* disable interrupt first */ + rt_hw_interrupt_disable(); + + /* init system setting */ + system_init(); - /* init system setting */ - system_init(); - - /* startup RT-Thread RTOS */ - rtthread_startup(); + /* startup RT-Thread RTOS */ + rtthread_startup(); - return 0; + return 0; } diff --git a/bsp/m16c62p/drivers/board.c b/bsp/m16c62p/drivers/board.c index bf37fae8cb..9771e97fed 100644 --- a/bsp/m16c62p/drivers/board.c +++ b/bsp/m16c62p/drivers/board.c @@ -23,8 +23,8 @@ void rt_hw_board_init(void) { #ifdef RT_USING_UART0 - rt_hw_uart_init(); - rt_console_set_device("uart0"); + rt_hw_uart_init(); + rt_console_set_device("uart0"); #endif rt_kprintf("\r\n\r\nSystemInit......\r\n"); diff --git a/bsp/m16c62p/drivers/bsp.c b/bsp/m16c62p/drivers/bsp.c index df80d0936b..29732cb636 100644 --- a/bsp/m16c62p/drivers/bsp.c +++ b/bsp/m16c62p/drivers/bsp.c @@ -35,31 +35,31 @@ void led_off(void) static void mcu_init(void) { - volatile rt_uint32_t count; - /* Configure clock for divide by 1 mode */ - PRCR.BYTE |= 0x01; /* Enable access to clock registers PRCR.PRC0 = 1 */ - CM1.BYTE = 0x20; /* Set CM16, CM17 divide ratio to 1: */ - /* ... main clock on in high drive no PLL */ - CM0.BYTE &= ~0x40; /* Set divide ratio to 1 CM0.CM06 = 0 */ + volatile rt_uint32_t count; + /* Configure clock for divide by 1 mode */ + PRCR.BYTE |= 0x01; /* Enable access to clock registers PRCR.PRC0 = 1 */ + CM1.BYTE = 0x20; /* Set CM16, CM17 divide ratio to 1: */ + /* ... main clock on in high drive no PLL */ + CM0.BYTE &= ~0x40; /* Set divide ratio to 1 CM0.CM06 = 0 */ /* Configure main PLL */ - PRCR.BYTE |= 0x02; /* Allow writing to processor mode register PRCR.PRC0 = 1 */ - PM2.BYTE |= 0x01; /* Set SFR access to 2 wait, which is required for */ - /* ... operation greater than 16 MHz PM2.PM20 = 1 */ - PRCR.BYTE &= ~0x02; /* Protect processor mode register PRCR.PRC0 = 0 */ - PLC0.BYTE = 0x91; /* Enable and turn on PLL */ + PRCR.BYTE |= 0x02; /* Allow writing to processor mode register PRCR.PRC0 = 1 */ + PM2.BYTE |= 0x01; /* Set SFR access to 2 wait, which is required for */ + /* ... operation greater than 16 MHz PM2.PM20 = 1 */ + PRCR.BYTE &= ~0x02; /* Protect processor mode register PRCR.PRC0 = 0 */ + PLC0.BYTE = 0x91; /* Enable and turn on PLL */ count = 20000; /* Delay while PLL stabilizes */ - while (count > 0) { + while (count > 0) { count--; } CM1.BYTE |= 0x02; /* Switch to PLL CM1.CM11 = 1 */ PRCR.BYTE &= ~0x01; /* Protect clock control register PRCR.PRC0 = 0 */ - - PRCR.BYTE |= 0x02; /* Allow writing to processor mode register PRCR.PRC0 = 1 */ - PM1.BYTE |= 0x01; /* Enable data flash area PM1.PM10 = 1 */ - PRCR.BYTE &= ~0x02; /* Protect processor mode register PRCR.PRC0 = 0 */ + + PRCR.BYTE |= 0x02; /* Allow writing to processor mode register PRCR.PRC0 = 1 */ + PM1.BYTE |= 0x01; /* Enable data flash area PM1.PM10 = 1 */ + PRCR.BYTE &= ~0x02; /* Protect processor mode register PRCR.PRC0 = 0 */ } /* @@ -85,15 +85,15 @@ static void mcu_init(void) static void timer_tick_init(void) { - /* Set timer to timer mode */ + /* Set timer to timer mode */ /* Set count source as PLL clock / 8 (f8) */ - TB0MR.BYTE = 0x40; + TB0MR.BYTE = 0x40; /* Assign timer value and reload value */ - TB0 = (CPU_CLK_FREQ / 8) / RT_TICK_PER_SECOND; - /* Set timer B channel 0 interrupt level = 7 */ - /* Clear interrupt request */ + TB0 = (CPU_CLK_FREQ / 8) / RT_TICK_PER_SECOND; + /* Set timer B channel 0 interrupt level = 7 */ + /* Clear interrupt request */ TB0IC.BYTE = 0x07; - TABSR.BYTE |= 0x20; /* Start timer */ + TABSR.BYTE |= 0x20; /* Start timer */ } void system_init(void) diff --git a/bsp/m16c62p/drivers/uart.c b/bsp/m16c62p/drivers/uart.c index 62e2a6b885..67f56b98a3 100644 --- a/bsp/m16c62p/drivers/uart.c +++ b/bsp/m16c62p/drivers/uart.c @@ -19,44 +19,44 @@ struct rt_uart_m16c { - struct rt_device parent; + struct rt_device parent; - /* buffer for reception */ - rt_uint8_t read_index, save_index; - rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; + /* buffer for reception */ + rt_uint8_t read_index, save_index; + rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; }uart_device; void u0rec_handler(void) { - rt_ubase_t level; - rt_uint8_t c; + rt_ubase_t level; + rt_uint8_t c; - struct rt_uart_m16c *uart = &uart_device; + struct rt_uart_m16c *uart = &uart_device; - while (U0C1.BIT.RI == 0) - ; - c = U0RB.BYTE.U0RBL; + while (U0C1.BIT.RI == 0) + ; + c = U0RB.BYTE.U0RBL; - /* Receive Data Available */ + /* Receive Data Available */ uart->rx_buffer[uart->save_index] = c; level = rt_hw_interrupt_disable(); - uart->save_index ++; + uart->save_index ++; if (uart->save_index >= RT_UART_RX_BUFFER_SIZE) uart->save_index = 0; rt_hw_interrupt_enable(level); - /* invoke callback */ - if (uart->parent.rx_indicate != RT_NULL) - { - rt_size_t length; - if (uart->read_index > uart->save_index) + /* invoke callback */ + if (uart->parent.rx_indicate != RT_NULL) + { + rt_size_t length; + if (uart->read_index > uart->save_index) length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index; else length = uart->save_index - uart->read_index; uart->parent.rx_indicate(&uart->parent, length); - } + } } static rt_err_t rt_uart_init (rt_device_t dev) @@ -65,7 +65,7 @@ static rt_err_t rt_uart_init (rt_device_t dev) /* set UART0 bit rate generator bit rate can be calculated by: bit rate = ((BRG count source / 16)/baud rate) - 1 Baud rate is based on main crystal or PLL not CPU core clock */ - //pclk1 = 1; /// seleck F1SIO + //pclk1 = 1; /// seleck F1SIO U0BRG = (unsigned char)(((CPU_CLK_FREQ/16)/BAUD_RATE)-1); //(N+1) /* UART Transmit/Receive Control Register 2 */ @@ -139,144 +139,144 @@ static rt_err_t rt_uart_init (rt_device_t dev) b6 UOLCH Data logic select bit b7 UOERE Error signal output enable bit */ - return RT_EOK; + return RT_EOK; } static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag) { - RT_ASSERT(dev != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* Enable the UART Interrupt */ - } + RT_ASSERT(dev != RT_NULL); + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* Enable the UART Interrupt */ + } - return RT_EOK; + return RT_EOK; } static rt_err_t rt_uart_close(rt_device_t dev) { - RT_ASSERT(dev != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* Disable the UART Interrupt */ - } + RT_ASSERT(dev != RT_NULL); + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* Disable the UART Interrupt */ + } - return RT_EOK; + return RT_EOK; } static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t *ptr; - struct rt_uart_m16c *uart = (struct rt_uart_m16c *)dev; - RT_ASSERT(uart != RT_NULL); - - /* point to buffer */ - ptr = (rt_uint8_t *)buffer; - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - while (size) - { - /* interrupt receive */ - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - if (uart->read_index != uart->save_index) - { - *ptr = uart->rx_buffer[uart->read_index]; - - uart->read_index ++; - if (uart->read_index >= RT_UART_RX_BUFFER_SIZE) - uart->read_index = 0; - } - else - { - /* no data in rx buffer */ - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - break; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - - ptr ++; - size --; - } - - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; - } - - return 0; + rt_uint8_t *ptr; + struct rt_uart_m16c *uart = (struct rt_uart_m16c *)dev; + RT_ASSERT(uart != RT_NULL); + + /* point to buffer */ + ptr = (rt_uint8_t *)buffer; + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + while (size) + { + /* interrupt receive */ + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + if (uart->read_index != uart->save_index) + { + *ptr = uart->rx_buffer[uart->read_index]; + + uart->read_index ++; + if (uart->read_index >= RT_UART_RX_BUFFER_SIZE) + uart->read_index = 0; + } + else + { + /* no data in rx buffer */ + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + ptr ++; + size --; + } + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + } + + return 0; } static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) { - char *ptr; - ptr = (char *)buffer; - - if (dev->flag & RT_DEVICE_FLAG_STREAM) - { - /* stream mode */ - while (size) - { - if (*ptr == '\n') - { - while (U0C1.BIT.TI == 0) - ; - U0TB.BYTE.U0TBL = '\r'; - } - - /* THRE status, contain valid data */ - while (U0C1.BIT.TI == 0) - ; - U0TB.BYTE.U0TBL = *ptr; - - ptr ++; - size --; - } - } - else - { - while (size != 0) - { - /* THRE status, contain valid data */ - while (U0C1.BIT.TI == 0) - ; - U0TB.BYTE.U0TBL = *ptr; - - ptr ++; - size --; - } - } - - return (rt_size_t)ptr - (rt_size_t)buffer; + char *ptr; + ptr = (char *)buffer; + + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* stream mode */ + while (size) + { + if (*ptr == '\n') + { + while (U0C1.BIT.TI == 0) + ; + U0TB.BYTE.U0TBL = '\r'; + } + + /* THRE status, contain valid data */ + while (U0C1.BIT.TI == 0) + ; + U0TB.BYTE.U0TBL = *ptr; + + ptr ++; + size --; + } + } + else + { + while (size != 0) + { + /* THRE status, contain valid data */ + while (U0C1.BIT.TI == 0) + ; + U0TB.BYTE.U0TBL = *ptr; + + ptr ++; + size --; + } + } + + return (rt_size_t)ptr - (rt_size_t)buffer; } void rt_hw_uart_init(void) { - struct rt_uart_m16c *uart; - - /* get uart device */ - uart = &uart_device; - - /* device initialization */ - uart->parent.type = RT_Device_Class_Char; - rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer)); - uart->read_index = uart->save_index = 0; - - /* device interface */ - uart->parent.init = rt_uart_init; - uart->parent.open = rt_uart_open; - uart->parent.close = rt_uart_close; - uart->parent.read = rt_uart_read; - uart->parent.write = rt_uart_write; - uart->parent.control = RT_NULL; - uart->parent.user_data = RT_NULL; - - rt_device_register(&uart->parent, - "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX); + struct rt_uart_m16c *uart; + + /* get uart device */ + uart = &uart_device; + + /* device initialization */ + uart->parent.type = RT_Device_Class_Char; + rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer)); + uart->read_index = uart->save_index = 0; + + /* device interface */ + uart->parent.init = rt_uart_init; + uart->parent.open = rt_uart_open; + uart->parent.close = rt_uart_close; + uart->parent.read = rt_uart_read; + uart->parent.write = rt_uart_write; + uart->parent.control = RT_NULL; + uart->parent.user_data = RT_NULL; + + rt_device_register(&uart->parent, + "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX); } #endif /* end of UART */ diff --git a/bsp/m16c62p/rtconfig.h b/bsp/m16c62p/rtconfig.h index adcf67e748..1b3d1cda12 100644 --- a/bsp/m16c62p/rtconfig.h +++ b/bsp/m16c62p/rtconfig.h @@ -3,16 +3,16 @@ #define __RTTHREAD_CFG_H__ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 32 +#define RT_THREAD_PRIORITY_MAX 32 /* Tick per Second */ -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 /* SECTION: RT_DEBUG */ /* Thread Debug */ @@ -27,9 +27,9 @@ /* Using Software Timer */ /* #define RT_USING_TIMER_SOFT */ -#define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 512 -#define RT_TIMER_TICK_PER_SECOND 10 +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_TICK_PER_SECOND 10 /* SECTION: IPC */ /* Using Semaphore */ @@ -62,12 +62,12 @@ #define RT_USING_DEVICE /* RT_USING_UART */ #define RT_USING_UART0 -#define RT_UART_RX_BUFFER_SIZE 64 +#define RT_UART_RX_BUFFER_SIZE 64 /* SECTION: Console options */ #define RT_USING_CONSOLE /* the buffer size of console */ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 /* SECTION: finsh, a C-Express shell */ /* Using FinSH as Shell*/ diff --git a/bsp/mb9bf500r/adc.c b/bsp/mb9bf500r/adc.c index 03017a1030..afb1f47210 100644 --- a/bsp/mb9bf500r/adc.c +++ b/bsp/mb9bf500r/adc.c @@ -7,7 +7,7 @@ * Date Author Notes * 2011-03-03 lgnq */ - + #include #include #include "mb9bf506r.h" @@ -29,45 +29,45 @@ static rt_err_t rt_adc_init(rt_device_t dev) if(!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) { - /* I/O setting AN08 - P18 */ + /* I/O setting AN08 - P18 */ FM3_GPIO->ADE |= 0x100; - FM3_GPIO->PFR1 = 0x100; - - /* A/DC setting */ - FM3_ADC0->SCIS1 = 0x01; - FM3_ADC0->ADSS1 = 0x00; /* sampling timming ADST0 */ - FM3_ADC0->ADST1 = 0x43; - FM3_ADC0->ADCT = 0x02; - FM3_ADC0->SCCR = 0x10; /* FIFO clear,single mode */ - FM3_ADC0->CMPCR = 0x00; /* disable comparator */ - - /* starting A/DC */ - FM3_ADC0->SCCR |= 0x01; /* A/DC start */ - + FM3_GPIO->PFR1 = 0x100; + + /* A/DC setting */ + FM3_ADC0->SCIS1 = 0x01; + FM3_ADC0->ADSS1 = 0x00; /* sampling timming ADST0 */ + FM3_ADC0->ADST1 = 0x43; + FM3_ADC0->ADCT = 0x02; + FM3_ADC0->SCCR = 0x10; /* FIFO clear,single mode */ + FM3_ADC0->CMPCR = 0x00; /* disable comparator */ + + /* starting A/DC */ + FM3_ADC0->SCCR |= 0x01; /* A/DC start */ + dev->flag |= RT_DEVICE_FLAG_ACTIVATED; - } - return RT_EOK; + } + return RT_EOK; } static rt_err_t rt_adc_control(rt_device_t dev, int cmd, void *args) { - RT_ASSERT(dev != RT_NULL); + RT_ASSERT(dev != RT_NULL); - switch (cmd) - { - case RT_DEVICE_CTRL_ADC_START: + switch (cmd) + { + case RT_DEVICE_CTRL_ADC_START: FM3_ADC0->SCCR |= 0x1; - break; - - case RT_DEVICE_CTRL_ADC_RESULT: + break; + + case RT_DEVICE_CTRL_ADC_RESULT: while(FM3_ADC0->ADSR & 0x1) ; *((rt_uint16_t*)args) = FM3_ADC0->SCFD; *((rt_uint16_t*)args) = *((rt_uint16_t*)args) >> 6; *((rt_uint16_t*)args) = (*((rt_uint16_t*)args)*3300)/1024; - break; - } - return RT_EOK; + break; + } + return RT_EOK; } extern struct rt_messagequeue mq; @@ -76,29 +76,29 @@ rt_uint16_t adc_value; static void adc_thread_entry(void *parameter) { rt_device_t device; - + #ifdef RT_USING_RTGUI struct rtgui_event_command ecmd; - + RTGUI_EVENT_COMMAND_INIT(&ecmd); ecmd.type = RTGUI_CMD_USER_INT; ecmd.command_id = ADC_UPDATE; #else struct lcd_msg msg; -#endif +#endif device = rt_device_find("adc"); while(1) { - rt_device_control(device, RT_DEVICE_CTRL_ADC_START, RT_NULL); + rt_device_control(device, RT_DEVICE_CTRL_ADC_START, RT_NULL); rt_device_control(device, RT_DEVICE_CTRL_ADC_RESULT, &adc_value); pwm_update(adc_value/3); #ifdef RT_USING_RTGUI rtgui_thread_send(info_tid, &ecmd.parent, sizeof(ecmd)); #else msg.type = ADC_MSG; - msg.adc_value = adc_value; + msg.adc_value = adc_value; rt_mq_send(&mq, &msg, sizeof(msg)); #endif rt_thread_delay(20); @@ -108,22 +108,22 @@ static void adc_thread_entry(void *parameter) static rt_thread_t adc_thread; void rt_hw_adc_init(void) { - adc.type = RT_Device_Class_Char; - adc.rx_indicate = RT_NULL; - adc.tx_complete = RT_NULL; - adc.init = rt_adc_init; - adc.open = RT_NULL; - adc.close = RT_NULL; - adc.read = RT_NULL; - adc.write = RT_NULL; - adc.control = rt_adc_control; - adc.user_data = RT_NULL; + adc.type = RT_Device_Class_Char; + adc.rx_indicate = RT_NULL; + adc.tx_complete = RT_NULL; + adc.init = rt_adc_init; + adc.open = RT_NULL; + adc.close = RT_NULL; + adc.read = RT_NULL; + adc.write = RT_NULL; + adc.control = rt_adc_control; + adc.user_data = RT_NULL; adc_thread = rt_thread_create("adc", adc_thread_entry, RT_NULL, 384, 26, 5); - if(adc_thread != RT_NULL) + if(adc_thread != RT_NULL) rt_thread_startup(adc_thread); - - /* register a character device */ - rt_device_register(&adc, "adc", RT_DEVICE_FLAG_RDWR); + + /* register a character device */ + rt_device_register(&adc, "adc", RT_DEVICE_FLAG_RDWR); } diff --git a/bsp/mb9bf500r/adc.h b/bsp/mb9bf500r/adc.h index f8bc628b76..c8846b0beb 100644 --- a/bsp/mb9bf500r/adc.h +++ b/bsp/mb9bf500r/adc.h @@ -7,18 +7,18 @@ * Date Author Notes * 2011-03-03 lgnq */ - + #ifndef __ADC_H__ #define __ADC_H__ /* Exported constants ---------------------------------------------------------*/ /* Exported macro -------------------------------------------------------------*/ -#define ADC_MODE_SINGLE 0x00UL -#define ADC_MODE_SCAN 0x01UL -#define ADC_MODE_TAILGATE 0x02UL +#define ADC_MODE_SINGLE 0x00UL +#define ADC_MODE_SCAN 0x01UL +#define ADC_MODE_TAILGATE 0x02UL #define RT_DEVICE_CTRL_ADC_START 0xF1 /* start ADC conversion */ -#define RT_DEVICE_CTRL_ADC_RESULT 0xF2 /* get ADC result */ +#define RT_DEVICE_CTRL_ADC_RESULT 0xF2 /* get ADC result */ #define ADC_UPDATE 0 diff --git a/bsp/mb9bf500r/application.c b/bsp/mb9bf500r/application.c index d738d91b5a..1cbd0c2d83 100644 --- a/bsp/mb9bf500r/application.c +++ b/bsp/mb9bf500r/application.c @@ -11,7 +11,7 @@ /** * @addtogroup FM3 */ - + /*@{*/ #include @@ -33,96 +33,96 @@ static char msg_pool[2048]; void rt_init_thread_entry(void *parameter) { - rt_device_t lcd; - + rt_device_t lcd; + rt_hw_led_init(); - rt_hw_key_init(); - rt_hw_adc_init(); - rt_hw_lcd_init(); - rt_hw_cpu_init(); + rt_hw_key_init(); + rt_hw_adc_init(); + rt_hw_lcd_init(); + rt_hw_cpu_init(); #ifdef RT_USING_RTGUI - extern void rtgui_system_server_init(void); - - /* find lcd device */ - lcd = rt_device_find("lcd"); - - /* set lcd device as rtgui graphic driver */ - rtgui_graphic_set_device(lcd); - - /* init rtgui system server */ - rtgui_system_server_init(); - - /* startup rtgui */ - rtgui_startup(); + extern void rtgui_system_server_init(void); + + /* find lcd device */ + lcd = rt_device_find("lcd"); + + /* set lcd device as rtgui graphic driver */ + rtgui_graphic_set_device(lcd); + + /* init rtgui system server */ + rtgui_system_server_init(); + + /* startup rtgui */ + rtgui_startup(); #else - { - char buf[20] = {'\0'}; + { + char buf[20] = {'\0'}; struct lcd_msg msg; - rt_device_t device; + rt_device_t device; device = rt_device_find("lcd"); - rt_device_control(device, RT_DEVICE_CTRL_LCD_CLEAR_SCR, RT_NULL); - x = 1; - y = 1; - rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, "ADC"); - x = 1; - y = 20; - rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, "CPU"); - x = 1; - y = 40; - rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, "KEY"); - + rt_device_control(device, RT_DEVICE_CTRL_LCD_CLEAR_SCR, RT_NULL); + x = 1; + y = 1; + rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, "ADC"); + x = 1; + y = 20; + rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, "CPU"); + x = 1; + y = 40; + rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, "KEY"); + while(1) { if (rt_mq_recv(&mq, &msg, sizeof(msg), RT_WAITING_FOREVER) == RT_EOK) { - switch(msg.type) - { - case ADC_MSG: - x = 40; - y = 1; - rt_memset(buf, 0, sizeof(buf)); - rt_sprintf(buf, "%04d", msg.adc_value); - rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, buf); - break; - case CPU_MSG: - x = 40; - y = 20; - rt_memset(buf, 0, sizeof(buf)); - rt_sprintf(buf, "%03d %03d", msg.major, msg.minor); - rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, buf); - break; - case KEY_MSG: - x = 40; - y = 40; - rt_memset(buf, 0, sizeof(buf)); + switch(msg.type) + { + case ADC_MSG: + x = 40; + y = 1; + rt_memset(buf, 0, sizeof(buf)); + rt_sprintf(buf, "%04d", msg.adc_value); + rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, buf); + break; + case CPU_MSG: + x = 40; + y = 20; + rt_memset(buf, 0, sizeof(buf)); + rt_sprintf(buf, "%03d %03d", msg.major, msg.minor); + rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, buf); + break; + case KEY_MSG: + x = 40; + y = 40; + rt_memset(buf, 0, sizeof(buf)); switch(msg.key) - { - case KEY_DOWN: - rt_sprintf(buf, "DOWN KEY "); - break; - case KEY_UP: - rt_sprintf(buf, "UP KEY "); - break; - case KEY_RIGHT: - rt_sprintf(buf, "RIGHT KEY"); - break; - case KEY_LEFT: - rt_sprintf(buf, "LEFT KEY "); - break; - case KEY_ENTER: - rt_sprintf(buf, "ENTER KEY"); - break; - default: - rt_sprintf(buf, "NO KEY "); - break; - } - rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, buf); - break; - } + { + case KEY_DOWN: + rt_sprintf(buf, "DOWN KEY "); + break; + case KEY_UP: + rt_sprintf(buf, "UP KEY "); + break; + case KEY_RIGHT: + rt_sprintf(buf, "RIGHT KEY"); + break; + case KEY_LEFT: + rt_sprintf(buf, "LEFT KEY "); + break; + case KEY_ENTER: + rt_sprintf(buf, "ENTER KEY"); + break; + default: + rt_sprintf(buf, "NO KEY "); + break; + } + rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, buf); + break; + } } } - } + } #endif } @@ -130,12 +130,12 @@ int rt_application_init(void) { rt_thread_t init_thread; - rt_mq_init(&mq, "mqt", &msg_pool[0], 128 - sizeof(void*), sizeof(msg_pool), RT_IPC_FLAG_FIFO); - + rt_mq_init(&mq, "mqt", &msg_pool[0], 128 - sizeof(void*), sizeof(msg_pool), RT_IPC_FLAG_FIFO); + init_thread = rt_thread_create("init", rt_init_thread_entry, RT_NULL, 1024, 21, 20); if(init_thread != RT_NULL) rt_thread_startup(init_thread); - + return 0; } diff --git a/bsp/mb9bf500r/board.c b/bsp/mb9bf500r/board.c index 9bfba04f05..f52a5fa3a8 100644 --- a/bsp/mb9bf500r/board.c +++ b/bsp/mb9bf500r/board.c @@ -29,13 +29,13 @@ extern const uint32_t SystemFrequency; */ void SysTick_Handler(void) { - /* enter interrupt */ - rt_interrupt_enter(); + /* enter interrupt */ + rt_interrupt_enter(); - rt_tick_increase(); + rt_tick_increase(); - /* leave interrupt */ - rt_interrupt_leave(); + /* leave interrupt */ + rt_interrupt_leave(); } /** diff --git a/bsp/mb9bf500r/cpuusage.h b/bsp/mb9bf500r/cpuusage.h index 16c7b171a5..6a53481f3f 100644 --- a/bsp/mb9bf500r/cpuusage.h +++ b/bsp/mb9bf500r/cpuusage.h @@ -7,7 +7,7 @@ * Date Author Notes * 2011-03-03 lgnq */ - + #ifndef __CPUUSAGE_H__ #define __CPUUSAGE_H__ diff --git a/bsp/mb9bf500r/key.c b/bsp/mb9bf500r/key.c index 2fc3274317..1886e72974 100644 --- a/bsp/mb9bf500r/key.c +++ b/bsp/mb9bf500r/key.c @@ -5,7 +5,7 @@ * * Change Logs: * Date Author Notes - * 2011-03-03 lgnq + * 2011-03-03 lgnq */ #include @@ -21,7 +21,7 @@ static void key_io_init(void) { /*Select CPIO function*/ KEY_PFR &= ~KEY_MASK; - /*Set CPIO Pull-Up function*/ + /*Set CPIO Pull-Up function*/ KEY_PCR |= KEY_MASK; /*Make button pins inputs*/ KEY_DDR &= ~KEY_MASK; @@ -34,7 +34,7 @@ static void key_thread_entry(void *parameter) rt_uint8_t i; struct rtgui_event_kbd kbd_event; - + key_io_init(); /* init keyboard event */ @@ -105,49 +105,49 @@ static void key_thread_entry(void *parameter) rt_thread_delay(next_delay); } #else - extern struct rt_messagequeue mq; - rt_time_t next_delay; - struct lcd_msg msg; - msg.type = KEY_MSG; - - key_io_init(); - - while (1) - { - msg.key = NO_KEY; - - next_delay = RT_TICK_PER_SECOND/10; - - if (KEY_ENTER_GETVALUE() == 0 ) - { - msg.key = KEY_ENTER; - } - - if (KEY_DOWN_GETVALUE() == 0) - { - msg.key = KEY_DOWN; - } - - if (KEY_UP_GETVALUE() == 0) - { - msg.key = KEY_UP; - } - - if (KEY_RIGHT_GETVALUE() == 0) - { - msg.key = KEY_RIGHT; - } - - if (KEY_LEFT_GETVALUE() == 0) - { - msg.key = KEY_LEFT; - } - - rt_mq_send(&mq, &msg, sizeof(msg)); - - /* wait next key press */ - rt_thread_delay(next_delay); - } + extern struct rt_messagequeue mq; + rt_time_t next_delay; + struct lcd_msg msg; + msg.type = KEY_MSG; + + key_io_init(); + + while (1) + { + msg.key = NO_KEY; + + next_delay = RT_TICK_PER_SECOND/10; + + if (KEY_ENTER_GETVALUE() == 0 ) + { + msg.key = KEY_ENTER; + } + + if (KEY_DOWN_GETVALUE() == 0) + { + msg.key = KEY_DOWN; + } + + if (KEY_UP_GETVALUE() == 0) + { + msg.key = KEY_UP; + } + + if (KEY_RIGHT_GETVALUE() == 0) + { + msg.key = KEY_RIGHT; + } + + if (KEY_LEFT_GETVALUE() == 0) + { + msg.key = KEY_LEFT; + } + + rt_mq_send(&mq, &msg, sizeof(msg)); + + /* wait next key press */ + rt_thread_delay(next_delay); + } #endif } @@ -155,6 +155,6 @@ static rt_thread_t key_thread; void rt_hw_key_init(void) { key_thread = rt_thread_create("key", key_thread_entry, RT_NULL, 384, 28, 5); - if (key_thread != RT_NULL) + if (key_thread != RT_NULL) rt_thread_startup(key_thread); } diff --git a/bsp/mb9bf500r/lcd.c b/bsp/mb9bf500r/lcd.c index 5aabb5f0e9..8b61abf2e0 100644 --- a/bsp/mb9bf500r/lcd.c +++ b/bsp/mb9bf500r/lcd.c @@ -55,7 +55,7 @@ void lcd_write_cmd(unsigned char command) LCD_DATA_HIGH(); else LCD_DATA_LOW(); - + LCD_CLK_LOW(); delay(); LCD_CLK_HIGH(); @@ -77,7 +77,7 @@ void lcd_write_data(unsigned char data) LCD_DATA_HIGH(); else LCD_DATA_LOW(); - + LCD_CLK_LOW(); delay(); LCD_CLK_HIGH(); @@ -93,12 +93,12 @@ void lcd_write_data(unsigned char data) static void rt_hw_lcd_update(struct rt_device_rect_info *rect_info) { rt_uint8_t i,j = GUI_LCM_XMAX; - rt_uint8_t* p = (rt_uint8_t*)gui_disp_buf; - + rt_uint8_t* p = (rt_uint8_t*)gui_disp_buf; + for (i=0; i> 4; - - lcd_write_cmd(SET_PAGE_ADDR_0 | page); // page no. - lcd_write_cmd(SET_COLH_ADDR_0 | colh); // fixed col first addr + + lcd_write_cmd(SET_PAGE_ADDR_0 | page); // page no. + lcd_write_cmd(SET_COLH_ADDR_0 | colh); // fixed col first addr lcd_write_cmd(SET_COLL_ADDR_0 | coll); lcd_write_data(gui_disp_buf[page][x]); } /**************************************************************************** * Function Name : LCD_PutChar -* Description : output a char to screen +* Description : output a char to screen (the char only can be ' ','0'~'9','A'~'Z','a'~'z') * Input : x X-coordinate y Y-coordinate @@ -359,13 +359,13 @@ void LCD_UpdatePoint(unsigned int x, unsigned int y) 0 Fail ****************************************************************************/ unsigned char LCD_PutChar(unsigned long x, unsigned long y, unsigned char ch) -{ +{ unsigned char data; unsigned char i, j; if( x >=(GUI_LCM_XMAX-8) ) return(0); if( y >=(GUI_LCM_YMAX-8) ) return(0); - + if(ch == 0x20) ch -= 0x20; else if((ch >= 0x30)&&(ch <= 0x39)) @@ -376,30 +376,30 @@ unsigned char LCD_PutChar(unsigned long x, unsigned long y, unsigned char ch) ch -= 0x3C; else return(0); - + for(i = 0; i < 8; i++) - { + { data = FONTTYPE8_8[ch][i]; - + for(j = 0; j < 8; j++) - { + { if( (data&BIT_MASK[j]) == 0) gui_disp_buf[y / 8][x] &= (~(0x01 << ( y % 8))); - else + else gui_disp_buf[y / 8][x] |= (0x01 <<( y % 8)); LCD_UpdatePoint(x, y); x ++; } - x -= 8; - y++; + x -= 8; + y++; } - + return(1); } /**************************************************************************** * Function Name : LCD_PutString -* Description : output string to screen +* Description : output string to screen * Input : x X-coordinate y Y-coordinate str pointer to string @@ -407,32 +407,32 @@ unsigned char LCD_PutChar(unsigned long x, unsigned long y, unsigned char ch) * Return : None ****************************************************************************/ void LCD_PutString(unsigned long x, unsigned long y, char *str) -{ +{ while(1) - { + { if( (*str)=='\0' ) break; if( LCD_PutChar(x, y, *str++) == 0 ) break; - x += 6; + x += 6; } } static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args) { - switch (cmd) - { -#ifdef RT_USING_RTGUI - case RTGRAPHIC_CTRL_RECT_UPDATE: - rt_hw_lcd_update(args); - break; - case RTGRAPHIC_CTRL_POWERON: - break; - case RTGRAPHIC_CTRL_POWEROFF: - break; - case RTGRAPHIC_CTRL_GET_INFO: - rt_memcpy(args, &_lcd_info, sizeof(_lcd_info)); - break; - case RTGRAPHIC_CTRL_SET_MODE: - break; + switch (cmd) + { +#ifdef RT_USING_RTGUI + case RTGRAPHIC_CTRL_RECT_UPDATE: + rt_hw_lcd_update(args); + break; + case RTGRAPHIC_CTRL_POWERON: + break; + case RTGRAPHIC_CTRL_POWEROFF: + break; + case RTGRAPHIC_CTRL_GET_INFO: + rt_memcpy(args, &_lcd_info, sizeof(_lcd_info)); + break; + case RTGRAPHIC_CTRL_SET_MODE: + break; #else case RT_DEVICE_CTRL_LCD_DISPLAY_ON: lcd_write_cmd(DISPLAY_ON); @@ -446,32 +446,32 @@ static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args) case RT_DEVICE_CTRL_LCD_CLEAR_SCR: LCD_ClearSCR(); break; -#endif - } +#endif + } - return RT_EOK; + return RT_EOK; } void rt_hw_lcd_init(void) { - rt_device_t lcd = rt_malloc(sizeof(struct rt_device)); - if (lcd == RT_NULL) return; /* no memory yet */ - - _lcd_info.bits_per_pixel = 16; - _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565; - _lcd_info.framebuffer = RT_NULL; - _lcd_info.width = LCD_WIDTH; - _lcd_info.height = LCD_HEIGHT; - - /* init device structure */ - lcd->type = RT_Device_Class_Unknown; - lcd->init = rt_lcd_init; - lcd->open = RT_NULL; - lcd->close = RT_NULL; - lcd->control = rt_lcd_control; + rt_device_t lcd = rt_malloc(sizeof(struct rt_device)); + if (lcd == RT_NULL) return; /* no memory yet */ + + _lcd_info.bits_per_pixel = 16; + _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565; + _lcd_info.framebuffer = RT_NULL; + _lcd_info.width = LCD_WIDTH; + _lcd_info.height = LCD_HEIGHT; + + /* init device structure */ + lcd->type = RT_Device_Class_Unknown; + lcd->init = rt_lcd_init; + lcd->open = RT_NULL; + lcd->close = RT_NULL; + lcd->control = rt_lcd_control; #ifdef RT_USING_RTGUI - lcd->user_data = (void*)&_lcd_ops; -#endif - /* register lcd device to RT-Thread */ - rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR); + lcd->user_data = (void*)&_lcd_ops; +#endif + /* register lcd device to RT-Thread */ + rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR); } diff --git a/bsp/mb9bf500r/lcd.h b/bsp/mb9bf500r/lcd.h index bb500f341f..e0fa9efdc3 100644 --- a/bsp/mb9bf500r/lcd.h +++ b/bsp/mb9bf500r/lcd.h @@ -15,166 +15,166 @@ #include "mb9bf506r.h" /********* LCD Hardward Interface ************* -LCD_CS PORT1.7 -LCD_CD PORT1.6 -LCD_WR PORT1.5 -LCD_RD PORT1.4 -LCD_SCK PORT1.3 -LCD_MOSI PORT1.2 -LCD_C86 PORT1.1 -LCD_PS PORT1.0 -LCD_DATA[0..7] PORT5.[0..7] +LCD_CS PORT1.7 +LCD_CD PORT1.6 +LCD_WR PORT1.5 +LCD_RD PORT1.4 +LCD_SCK PORT1.3 +LCD_MOSI PORT1.2 +LCD_C86 PORT1.1 +LCD_PS PORT1.0 +LCD_DATA[0..7] PORT5.[0..7] ***********************************************/ -#define LCD_CS (1UL << 7) -#define LCD_CS_DDR (FM3_GPIO->DDR1) -#define LCD_CS_PFR (FM3_GPIO->PFR1) -#define LCD_CS_PDOR (FM3_GPIO->PDOR1) - -#define LCD_CD (1UL << 6) -#define LCD_CD_DDR (FM3_GPIO->DDR1) -#define LCD_CD_PFR (FM3_GPIO->PFR1) -#define LCD_CD_PDOR (FM3_GPIO->PDOR1) - -#define LCD_PS (1UL << 0) -#define LCD_PS_DDR (FM3_GPIO->DDR1) -#define LCD_PS_PFR (FM3_GPIO->PFR1) -#define LCD_PS_PDOR (FM3_GPIO->PDOR1) - -#define LCD_CLK (1UL << 6) -#define LCD_CLK_DDR (FM3_GPIO->DDR5) -#define LCD_CLK_PFR (FM3_GPIO->PFR5) -#define LCD_CLK_PDOR (FM3_GPIO->PDOR5) - -#define LCD_DATA (1UL << 7) -#define LCD_DATA_DDR (FM3_GPIO->DDR5) -#define LCD_DATA_PFR (FM3_GPIO->PFR5) -#define LCD_DATA_PDOR (FM3_GPIO->PDOR5) +#define LCD_CS (1UL << 7) +#define LCD_CS_DDR (FM3_GPIO->DDR1) +#define LCD_CS_PFR (FM3_GPIO->PFR1) +#define LCD_CS_PDOR (FM3_GPIO->PDOR1) + +#define LCD_CD (1UL << 6) +#define LCD_CD_DDR (FM3_GPIO->DDR1) +#define LCD_CD_PFR (FM3_GPIO->PFR1) +#define LCD_CD_PDOR (FM3_GPIO->PDOR1) + +#define LCD_PS (1UL << 0) +#define LCD_PS_DDR (FM3_GPIO->DDR1) +#define LCD_PS_PFR (FM3_GPIO->PFR1) +#define LCD_PS_PDOR (FM3_GPIO->PDOR1) + +#define LCD_CLK (1UL << 6) +#define LCD_CLK_DDR (FM3_GPIO->DDR5) +#define LCD_CLK_PFR (FM3_GPIO->PFR5) +#define LCD_CLK_PDOR (FM3_GPIO->PDOR5) + +#define LCD_DATA (1UL << 7) +#define LCD_DATA_DDR (FM3_GPIO->DDR5) +#define LCD_DATA_PFR (FM3_GPIO->PFR5) +#define LCD_DATA_PDOR (FM3_GPIO->PDOR5) /* LCD driver for ZYMG12864C3 */ -#define LCD_WIDTH 128 -#define LCD_HEIGHT 64 +#define LCD_WIDTH 128 +#define LCD_HEIGHT 64 // Driver the LCD with Parallel or serial interface and the command/data control pin is gpio -#define LCD_CS_HIGH() LCD_CS_PDOR |= LCD_CS -#define LCD_CS_LOW() LCD_CS_PDOR &= ~LCD_CS +#define LCD_CS_HIGH() LCD_CS_PDOR |= LCD_CS +#define LCD_CS_LOW() LCD_CS_PDOR &= ~LCD_CS -#define LCD_CD_HIGH() LCD_CD_PDOR |= LCD_CD -#define LCD_CD_LOW() LCD_CD_PDOR &= ~LCD_CD +#define LCD_CD_HIGH() LCD_CD_PDOR |= LCD_CD +#define LCD_CD_LOW() LCD_CD_PDOR &= ~LCD_CD -#define LCD_PS_HIGH() LCD_PS_PDOR |= LCD_PS -#define LCD_PS_LOW() LCD_PS_PDOR &= ~LCD_PS +#define LCD_PS_HIGH() LCD_PS_PDOR |= LCD_PS +#define LCD_PS_LOW() LCD_PS_PDOR &= ~LCD_PS -#define LCD_CLK_HIGH() LCD_CLK_PDOR |= LCD_CLK -#define LCD_CLK_LOW() LCD_CLK_PDOR &= ~LCD_CLK +#define LCD_CLK_HIGH() LCD_CLK_PDOR |= LCD_CLK +#define LCD_CLK_LOW() LCD_CLK_PDOR &= ~LCD_CLK -#define LCD_DATA_HIGH() LCD_DATA_PDOR |= LCD_DATA -#define LCD_DATA_LOW() LCD_DATA_PDOR &= ~LCD_DATA +#define LCD_DATA_HIGH() LCD_DATA_PDOR |= LCD_DATA +#define LCD_DATA_LOW() LCD_DATA_PDOR &= ~LCD_DATA // define the arrtibute of ZYMG12864(LCM) -#define GUI_LCM_XMAX 128 // defined the lcd's line-number is 128 -#define GUI_LCM_YMAX 64 // defined the lcd's column-number is 64 -#define GUI_LCM_PAGE 8 // defined the lcd's page-number is 8(GUI_LCM_YMAX/8) +#define GUI_LCM_XMAX 128 // defined the lcd's line-number is 128 +#define GUI_LCM_YMAX 64 // defined the lcd's column-number is 64 +#define GUI_LCM_PAGE 8 // defined the lcd's page-number is 8(GUI_LCM_YMAX/8) /* set LCD command */ -#define DISPLAY_ON 0xAF // A0,RD,WR:010 -#define DISPLAY_OFF 0xAE // A0,RD,WR:010 - -#define SET_START_LINE_0 0x40 // A0,RD,WR:010; line0~line63 -#define SET_PAGE_ADDR_0 0xB0 // A0,RD,WR:010; addr0~addr8 -#define SET_COLH_ADDR_0 0x10 // A0,RD,WR:010; -#define SET_COLL_ADDR_0 0x00 // A0,RD,WR:010; addr0~addr131 - -#define READ_STATUS 0x-0 // A0,RD,WR:001; BUSY | ADC | ON/OFF | RESET | 0 0 0 0 -#define STATUS_BUSY 0x80 -#define STATUS_ADC_REVERSE 0x40 // column address 131-n : SEG n, else column address n : SEG n -#define STATUS_DISPLAY_OFF 0x20 -#define STATUS_RESET 0x80 - -#define WRITE_DATA 0x-- // A0,RD,WR:110 -#define READ_DATE 0x-- // A0,RD,WR:101; spi mode is unavailable - -#define SET_ADC_NORMAL 0xA0 // A0,RD,WR:010 -#define SET_ADC_REVERSE 0xA1 // A0,RD,WR:010 -#define DISPLAY_NORMAL 0xA6 // A0,RD,WR:010 -#define DISPLAY_REVERSE 0xA7 // A0,RD,WR:010; reverse color -#define DISPLAY_ALL_ON 0xA5 // A0,RD,WR:010 -#define DISPLAY_ALL_NORMAL 0xA4 // A0,RD,WR:010 +#define DISPLAY_ON 0xAF // A0,RD,WR:010 +#define DISPLAY_OFF 0xAE // A0,RD,WR:010 + +#define SET_START_LINE_0 0x40 // A0,RD,WR:010; line0~line63 +#define SET_PAGE_ADDR_0 0xB0 // A0,RD,WR:010; addr0~addr8 +#define SET_COLH_ADDR_0 0x10 // A0,RD,WR:010; +#define SET_COLL_ADDR_0 0x00 // A0,RD,WR:010; addr0~addr131 + +#define READ_STATUS 0x-0 // A0,RD,WR:001; BUSY | ADC | ON/OFF | RESET | 0 0 0 0 +#define STATUS_BUSY 0x80 +#define STATUS_ADC_REVERSE 0x40 // column address 131-n : SEG n, else column address n : SEG n +#define STATUS_DISPLAY_OFF 0x20 +#define STATUS_RESET 0x80 + +#define WRITE_DATA 0x-- // A0,RD,WR:110 +#define READ_DATE 0x-- // A0,RD,WR:101; spi mode is unavailable + +#define SET_ADC_NORMAL 0xA0 // A0,RD,WR:010 +#define SET_ADC_REVERSE 0xA1 // A0,RD,WR:010 +#define DISPLAY_NORMAL 0xA6 // A0,RD,WR:010 +#define DISPLAY_REVERSE 0xA7 // A0,RD,WR:010; reverse color +#define DISPLAY_ALL_ON 0xA5 // A0,RD,WR:010 +#define DISPLAY_ALL_NORMAL 0xA4 // A0,RD,WR:010 /************************************************************* -* bias: 1/65duty | 1/49duty | 1/33duty | 1/55duty | 1/53duty * -* ---------------|----------|----------|----------|--------- * -* A2: 1/9 bias | 1/8 bias | 1/6 bias | 1/8 bias | 1/8 bias * -* A3: 1/7 bias | 1/6 bias | 1/5 bias | 1/6 bias | 1/6 bias * +* bias: 1/65duty | 1/49duty | 1/33duty | 1/55duty | 1/53duty * +* ---------------|----------|----------|----------|--------- * +* A2: 1/9 bias | 1/8 bias | 1/6 bias | 1/8 bias | 1/8 bias * +* A3: 1/7 bias | 1/6 bias | 1/5 bias | 1/6 bias | 1/6 bias * **************************************************************/ -#define SET_LCD_BIAS_7 0xA3 // A0,RD,WR:010 -#define SET_LCD_BIAS_9 0xA2 // A0,RD,WR:010 +#define SET_LCD_BIAS_7 0xA3 // A0,RD,WR:010 +#define SET_LCD_BIAS_9 0xA2 // A0,RD,WR:010 -#define RMW_MODE_ENABLE 0xE0 // A0,RD,WR:010; the column address locked when read command operating -#define RMW_MODE_END 0xEE // A0,RD,WR:010; returns to the column address when RMW was entered. -#define RESET_LCD 0xE2 // A0,RD,WR:010 +#define RMW_MODE_ENABLE 0xE0 // A0,RD,WR:010; the column address locked when read command operating +#define RMW_MODE_END 0xEE // A0,RD,WR:010; returns to the column address when RMW was entered. +#define RESET_LCD 0xE2 // A0,RD,WR:010 /************************************************************************************** -* Com Scan Dir: | 1/65duty | 1/49duty | 1/33duty | 1/55duty | 1/53duty * -* --------------|-------------|-------------|-------------|------------------------ * -* C0: Normal | COM0:COM63 | COM0:COM47 | COM0:COM31 | COM0:COM53 | COM0:COM51 * -* C8: Reverse | COM63:COM0 | COM47:COM0 | COM31:COM0 | COM53:COM0 | COM51:COM0 * +* Com Scan Dir: | 1/65duty | 1/49duty | 1/33duty | 1/55duty | 1/53duty * +* --------------|-------------|-------------|-------------|------------------------ * +* C0: Normal | COM0:COM63 | COM0:COM47 | COM0:COM31 | COM0:COM53 | COM0:COM51 * +* C8: Reverse | COM63:COM0 | COM47:COM0 | COM31:COM0 | COM53:COM0 | COM51:COM0 * ***************************************************************************************/ -#define COM_SCAN_DIR_NORMAL 0xC0 // A0,RD,WR:010 -#define COM_SCAN_DIR_REVERSE 0xC8 // A0,RD,WR:010 +#define COM_SCAN_DIR_NORMAL 0xC0 // A0,RD,WR:010 +#define COM_SCAN_DIR_REVERSE 0xC8 // A0,RD,WR:010 // 0 0 1 0 1 | Booster On | Regulator On | Follower On -#define POWER_BOOSTER_ON 0x2C // A0,RD,WR:010 -#define POWER_REGULATOR_ON 0x2E // A0,RD,WR:010 -#define POWER_FOLLOWER_ON 0x2F // A0,RD,WR:010 - -#define SET_RESISTOR_RATIO 0x20 // A0,RD,WR:010; 20~27:small~large - -#define SET_ELECVOL_MODE 0x81 // A0,RD,WR:010; double byte command -#define SET_ELECVOL_REG 0x20 // A0,RD,WR:010; the electronic volume(64 voltage levels:00~3F) function is not used. - -#define SLEEP_MODE_ENABLE 0xAC // A0,RD,WR:010; double byte command, preceding command -#define SLEEP_MODE_DISABLE 0xAD // A0,RD,WR:010; preceding command -#define SLEEP_MODE_DELIVER 0x00 // A0,RD,WR:010; following command - -#define BOOST_RATIO_SET 0xF8 // A0,RD,WR:010; double byte command, preceding command -#define BOOST_RATIO_234 0x00 // A0,RD,WR:010; following command -#define BOOST_RATIO_5 0x01 // A0,RD,WR:010; following command -#define BOOST_RATIO_6 0x03 // A0,RD,WR:010; following command - -#define COMMAND_NOP 0xE3 // A0,RD,WR:010 -#define COMMAND_IC_TEST 0xFC // A0,RD,WR:010; don't use - -#define RT_DEVICE_CTRL_LCD_GET_WIDTH 0 -#define RT_DEVICE_CTRL_LCD_GET_HEIGHT 1 -#define RT_DEVICE_CTRL_LCD_GET_BPP 2 -#define RT_DEVICE_CTRL_LCD_GET_FRAMEBUFFER 3 -#define RT_DEVICE_CTRL_LCD_POWER_ON 4 -#define RT_DEVICE_CTRL_LCD_POWER_OFF 5 -#define RT_DEVICE_CTRL_LCD_CLEAR_SCR 6 -#define RT_DEVICE_CTRL_LCD_FILL_ALL 7 -#define RT_DEVICE_CTRL_LCD_UPDATE_POINT 8 -#define RT_DEVICE_CTRL_LCD_DISPLAY_ON 9 -#define RT_DEVICE_CTRL_LCD_DISPLAY_OFF 10 -#define RT_DEVICE_CTRL_LCD_PUT_STRING 11 - -enum +#define POWER_BOOSTER_ON 0x2C // A0,RD,WR:010 +#define POWER_REGULATOR_ON 0x2E // A0,RD,WR:010 +#define POWER_FOLLOWER_ON 0x2F // A0,RD,WR:010 + +#define SET_RESISTOR_RATIO 0x20 // A0,RD,WR:010; 20~27:small~large + +#define SET_ELECVOL_MODE 0x81 // A0,RD,WR:010; double byte command +#define SET_ELECVOL_REG 0x20 // A0,RD,WR:010; the electronic volume(64 voltage levels:00~3F) function is not used. + +#define SLEEP_MODE_ENABLE 0xAC // A0,RD,WR:010; double byte command, preceding command +#define SLEEP_MODE_DISABLE 0xAD // A0,RD,WR:010; preceding command +#define SLEEP_MODE_DELIVER 0x00 // A0,RD,WR:010; following command + +#define BOOST_RATIO_SET 0xF8 // A0,RD,WR:010; double byte command, preceding command +#define BOOST_RATIO_234 0x00 // A0,RD,WR:010; following command +#define BOOST_RATIO_5 0x01 // A0,RD,WR:010; following command +#define BOOST_RATIO_6 0x03 // A0,RD,WR:010; following command + +#define COMMAND_NOP 0xE3 // A0,RD,WR:010 +#define COMMAND_IC_TEST 0xFC // A0,RD,WR:010; don't use + +#define RT_DEVICE_CTRL_LCD_GET_WIDTH 0 +#define RT_DEVICE_CTRL_LCD_GET_HEIGHT 1 +#define RT_DEVICE_CTRL_LCD_GET_BPP 2 +#define RT_DEVICE_CTRL_LCD_GET_FRAMEBUFFER 3 +#define RT_DEVICE_CTRL_LCD_POWER_ON 4 +#define RT_DEVICE_CTRL_LCD_POWER_OFF 5 +#define RT_DEVICE_CTRL_LCD_CLEAR_SCR 6 +#define RT_DEVICE_CTRL_LCD_FILL_ALL 7 +#define RT_DEVICE_CTRL_LCD_UPDATE_POINT 8 +#define RT_DEVICE_CTRL_LCD_DISPLAY_ON 9 +#define RT_DEVICE_CTRL_LCD_DISPLAY_OFF 10 +#define RT_DEVICE_CTRL_LCD_PUT_STRING 11 + +enum { - ADC_MSG, - KEY_MSG, - CPU_MSG, - MAX_MSG, + ADC_MSG, + KEY_MSG, + CPU_MSG, + MAX_MSG, }; struct lcd_msg { - rt_uint8_t type; - rt_uint16_t adc_value; - rt_uint8_t key; - rt_uint16_t major; - rt_uint16_t minor; + rt_uint8_t type; + rt_uint16_t adc_value; + rt_uint8_t key; + rt_uint16_t major; + rt_uint16_t minor; }; extern rt_uint32_t x; diff --git a/bsp/mb9bf500r/led.c b/bsp/mb9bf500r/led.c index e546a6eadc..ee28af7035 100644 --- a/bsp/mb9bf500r/led.c +++ b/bsp/mb9bf500r/led.c @@ -7,7 +7,7 @@ * Date Author Notes * 2011-03-03 lgnq */ - + #include #include @@ -16,8 +16,8 @@ void rt_hw_led_on(rt_uint8_t num) { - RT_ASSERT(num < LEDS_MAX_NUMBER); - + RT_ASSERT(num < LEDS_MAX_NUMBER); + switch (num) { case 1: @@ -27,16 +27,16 @@ void rt_hw_led_on(rt_uint8_t num) LED_PDOR &= ~LED2; break; case 3: - LED_PDOR &= ~LED3; + LED_PDOR &= ~LED3; break; default: break; - } + } } void rt_hw_led_off(rt_uint8_t num) { - RT_ASSERT(num < LEDS_MAX_NUMBER); + RT_ASSERT(num < LEDS_MAX_NUMBER); switch (num) { @@ -47,17 +47,17 @@ void rt_hw_led_off(rt_uint8_t num) LED_PDOR |= LED2; break; case 3: - LED_PDOR |= LED3; + LED_PDOR |= LED3; break; default: break; - } + } } void rt_hw_led_toggle(rt_uint8_t num) { - RT_ASSERT(num < LEDS_MAX_NUMBER); - + RT_ASSERT(num < LEDS_MAX_NUMBER); + switch (num) { case 1: @@ -76,11 +76,11 @@ void rt_hw_led_toggle(rt_uint8_t num) if (LED_PDOR&LED3) LED_PDOR &= ~LED3; else - LED_PDOR |= LED3; + LED_PDOR |= LED3; break; default: break; - } + } } static rt_err_t led_io_init(void) @@ -91,23 +91,23 @@ static rt_err_t led_io_init(void) LED_PDOR |= LED_MASK; /*Make led pins outputs*/ LED_DDR |= LED_MASK; - + //LED3 is controled by PWM FM3_GPIO->PFR3 = 0x1000; FM3_GPIO->EPFR04 = 0x00080000; FM3_BT2_PWM->TMCR = 0x0018; - FM3_BT2_PWM->TMCR2 = 0x01; /* cks=0b1000 count clk 1/512 */ + FM3_BT2_PWM->TMCR2 = 0x01; /* cks=0b1000 count clk 1/512 */ FM3_BT2_PWM->STC = 0x00; - FM3_BT2_PWM->PCSR = 0x61A; /* Down count = 1562 */ - FM3_BT2_PWM->PDUT = 0x0; /* Duty count = 16/1562=10% */ - - FM3_BT2_PWM->TMCR |= 0x03; /* start base timer(softwere TRG) */ + FM3_BT2_PWM->PCSR = 0x61A; /* Down count = 1562 */ + FM3_BT2_PWM->PDUT = 0x0; /* Duty count = 16/1562=10% */ + + FM3_BT2_PWM->TMCR |= 0x03; /* start base timer(softwere TRG) */ return RT_EOK; } void pwm_update(rt_uint16_t value) { - FM3_BT2_PWM->PDUT = value; + FM3_BT2_PWM->PDUT = value; } static void led1_thread_entry(void *parameter) @@ -135,11 +135,11 @@ void rt_hw_led_init(void) led_io_init(); led1_thread = rt_thread_create("led1", led1_thread_entry, RT_NULL, 384, 29, 5); - if (led1_thread != RT_NULL) + if (led1_thread != RT_NULL) rt_thread_startup(led1_thread); - + led2_thread = rt_thread_create("led2", led2_thread_entry, RT_NULL, 384, 30, 5); - if (led2_thread != RT_NULL) + if (led2_thread != RT_NULL) rt_thread_startup(led2_thread); } diff --git a/bsp/mb9bf500r/led.h b/bsp/mb9bf500r/led.h index 1c7c2064e9..c4a433cb81 100644 --- a/bsp/mb9bf500r/led.h +++ b/bsp/mb9bf500r/led.h @@ -7,13 +7,13 @@ * Date Author Notes * 2011-03-03 lgnq */ - + #ifndef __LED_H__ #define __LED_H__ #include "mb9bf506r.h" -#define LEDS_MAX_NUMBER 4 +#define LEDS_MAX_NUMBER 4 /*LEDs*/ #define LED1 (1UL<<10) @@ -25,9 +25,9 @@ #define LED_DDR (FM3_GPIO->DDR3) #define LED_PDOR (FM3_GPIO->PDOR3) -#define RT_DEVICE_CTRL_LED_ON 0 -#define RT_DEVICE_CTRL_LED_OFF 1 -#define RT_DEVICE_CTRL_LED_TOGGLE 2 +#define RT_DEVICE_CTRL_LED_ON 0 +#define RT_DEVICE_CTRL_LED_OFF 1 +#define RT_DEVICE_CTRL_LED_TOGGLE 2 void rt_hw_led_init(void); void rt_hw_led_on(rt_uint8_t num); diff --git a/bsp/mb9bf500r/rtconfig.h b/bsp/mb9bf500r/rtconfig.h index cb2c62fccd..ac37ecb464 100644 --- a/bsp/mb9bf500r/rtconfig.h +++ b/bsp/mb9bf500r/rtconfig.h @@ -3,16 +3,16 @@ #define __RTTHREAD_CFG_H__ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 32 +#define RT_THREAD_PRIORITY_MAX 32 /* Tick per Second */ -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 /* SECTION: RT_DEBUG */ /* Thread Debug */ @@ -53,20 +53,20 @@ #define RT_USING_DEVICE /* RT_USING_UART */ #define RT_USING_UART0 -#define RT_UART_RX_BUFFER_SIZE 64 +#define RT_UART_RX_BUFFER_SIZE 64 /* SECTION: Console options */ #define RT_TINY_SIZE #define RT_USING_CONSOLE /* the buffer size of console */ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 /* SECTION: RTGUI support */ /* using RTGUI support */ /* #define RT_USING_RTGUI */ /* name length of RTGUI object */ -#define RTGUI_NAME_MAX 16 +#define RTGUI_NAME_MAX 16 /* support 16 weight font */ //#define RTGUI_USING_FONT16 /* support 12 weight font */ diff --git a/bsp/mb9bf500r/startup.c b/bsp/mb9bf500r/startup.c index 9fddacbee3..463bb21408 100644 --- a/bsp/mb9bf500r/startup.c +++ b/bsp/mb9bf500r/startup.c @@ -34,68 +34,68 @@ extern int __bss_end; */ void rtthread_startup(void) { - /* init board */ - rt_hw_board_init(); + /* init board */ + rt_hw_board_init(); - /* show version */ - rt_show_version(); + /* show version */ + rt_show_version(); - /* init tick */ - rt_system_tick_init(); + /* init tick */ + rt_system_tick_init(); - /* init kernel object */ - rt_system_object_init(); + /* init kernel object */ + rt_system_object_init(); - /* init timer system */ - rt_system_timer_init(); + /* init timer system */ + rt_system_timer_init(); #ifdef RT_USING_HEAP - #ifdef __CC_ARM - rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)FM3_SRAM_END); - #elif __ICCARM__ - rt_system_heap_init(__segment_end("HEAP"), (void*)FM3_SRAM_END); - #else - /* init memory system */ - rt_system_heap_init((void*)&__bss_end, (void*)FM3_SRAM_END); - #endif + #ifdef __CC_ARM + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)FM3_SRAM_END); + #elif __ICCARM__ + rt_system_heap_init(__segment_end("HEAP"), (void*)FM3_SRAM_END); + #else + /* init memory system */ + rt_system_heap_init((void*)&__bss_end, (void*)FM3_SRAM_END); + #endif #endif - /* init scheduler system */ - rt_system_scheduler_init(); + /* init scheduler system */ + rt_system_scheduler_init(); #ifdef RT_USING_DEVICE - /* init all device */ - rt_device_init_all(); + /* init all device */ + rt_device_init_all(); #endif - /* init application */ - rt_application_init(); + /* init application */ + rt_application_init(); /* init timer thread */ rt_system_timer_thread_init(); - /* init idle thread */ - rt_thread_idle_init(); + /* init idle thread */ + rt_thread_idle_init(); - /* start scheduler */ - rt_system_scheduler_start(); + /* start scheduler */ + rt_system_scheduler_start(); - /* never reach here */ - return ; + /* never reach here */ + return ; } int main(void) { - /* disable interrupt first */ - rt_hw_interrupt_disable(); + /* disable interrupt first */ + rt_hw_interrupt_disable(); - /* init system setting */ - SystemInit(); - - /* startup RT-Thread RTOS */ - rtthread_startup(); + /* init system setting */ + SystemInit(); - return 0; + /* startup RT-Thread RTOS */ + rtthread_startup(); + + return 0; } /*@}*/ diff --git a/bsp/mb9bf506r/applications/application.c b/bsp/mb9bf506r/applications/application.c index dec091a849..fdc42a9100 100644 --- a/bsp/mb9bf506r/applications/application.c +++ b/bsp/mb9bf506r/applications/application.c @@ -29,35 +29,35 @@ void rt_init_thread_entry(void *parameter) { - /* LED Initialization */ - rt_hw_led_init(); + /* LED Initialization */ + rt_hw_led_init(); #ifdef RT_USING_COMPONENTS_INIT - /* initialization RT-Thread Components */ - rt_components_init(); + /* initialization RT-Thread Components */ + rt_components_init(); #endif - /* Filesystem Initialization */ + /* Filesystem Initialization */ #ifdef RT_USING_DFS - /* mount nand fat partition 1 as root directory */ - if (dfs_mount("nand", "/", "elm", 0, 0) == 0) - rt_kprintf("File System initialized!\n"); - else - rt_kprintf("File System init failed!\n"); + /* mount nand fat partition 1 as root directory */ + if (dfs_mount("nand", "/", "elm", 0, 0) == 0) + rt_kprintf("File System initialized!\n"); + else + rt_kprintf("File System init failed!\n"); #endif } int rt_application_init(void) { - rt_thread_t tid; + rt_thread_t tid; - tid = rt_thread_create("init", - rt_init_thread_entry, RT_NULL, - 2048, RT_THREAD_PRIORITY_MAX/3, 20); - if (tid != RT_NULL) - rt_thread_startup(tid); + tid = rt_thread_create("init", + rt_init_thread_entry, RT_NULL, + 2048, RT_THREAD_PRIORITY_MAX/3, 20); + if (tid != RT_NULL) + rt_thread_startup(tid); - return 0; + return 0; } /*@}*/ diff --git a/bsp/mb9bf506r/applications/startup.c b/bsp/mb9bf506r/applications/startup.c index 087837cf08..ccb31d40b4 100644 --- a/bsp/mb9bf506r/applications/startup.c +++ b/bsp/mb9bf506r/applications/startup.c @@ -34,60 +34,60 @@ extern int __bss_end; */ void rtthread_startup(void) { - /* initialize board */ - rt_hw_board_init(); + /* initialize board */ + rt_hw_board_init(); - /* show version */ - rt_show_version(); + /* show version */ + rt_show_version(); #ifdef RT_USING_HEAP - #ifdef __CC_ARM - rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)FM3_SRAM_END); - #elif __ICCARM__ - rt_system_heap_init(__segment_end("HEAP"), (void*)FM3_SRAM_END); - #else - /* init memory system */ - rt_system_heap_init((void*)&__bss_end, (void*)FM3_SRAM_END); - #endif + #ifdef __CC_ARM + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)FM3_SRAM_END); + #elif __ICCARM__ + rt_system_heap_init(__segment_end("HEAP"), (void*)FM3_SRAM_END); + #else + /* init memory system */ + rt_system_heap_init((void*)&__bss_end, (void*)FM3_SRAM_END); + #endif #endif - /* init scheduler system */ - rt_system_scheduler_init(); + /* init scheduler system */ + rt_system_scheduler_init(); #ifdef RT_USING_DEVICE #if defined(RT_USING_DFS) && defined(RT_USING_DFS_UFFS) - rt_hw_nand_init(); + rt_hw_nand_init(); #endif #endif - /* initialize application */ - rt_application_init(); + /* initialize application */ + rt_application_init(); /* initialize timer */ rt_system_timer_init(); - /* initialize timer thread */ - rt_system_timer_thread_init(); + /* initialize timer thread */ + rt_system_timer_thread_init(); - /* initialize idle thread */ - rt_thread_idle_init(); + /* initialize idle thread */ + rt_thread_idle_init(); - /* start scheduler */ - rt_system_scheduler_start(); + /* start scheduler */ + rt_system_scheduler_start(); - /* never reach here */ - return ; + /* never reach here */ + return ; } int main(void) { - /* disable interrupt first */ - rt_hw_interrupt_disable(); + /* disable interrupt first */ + rt_hw_interrupt_disable(); - /* startup RT-Thread RTOS */ - rtthread_startup(); + /* startup RT-Thread RTOS */ + rtthread_startup(); - return 0; + return 0; } /*@}*/ diff --git a/bsp/mb9bf506r/drivers/board.c b/bsp/mb9bf506r/drivers/board.c index 4bfaebc1d8..d687bea929 100644 --- a/bsp/mb9bf506r/drivers/board.c +++ b/bsp/mb9bf506r/drivers/board.c @@ -28,13 +28,13 @@ */ void SysTick_Handler(void) { - /* enter interrupt */ - rt_interrupt_enter(); + /* enter interrupt */ + rt_interrupt_enter(); - rt_tick_increase(); + rt_tick_increase(); - /* leave interrupt */ - rt_interrupt_leave(); + /* leave interrupt */ + rt_interrupt_leave(); } /** @@ -42,16 +42,16 @@ void SysTick_Handler(void) */ void rt_hw_board_init(void) { - /* init systick */ - SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); - - /* initialize UART device */ - rt_hw_serial_init(); - /* set console as UART device */ - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); - - /* initialize nand flash device */ - rt_hw_nand_init(); + /* init systick */ + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + + /* initialize UART device */ + rt_hw_serial_init(); + /* set console as UART device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + + /* initialize nand flash device */ + rt_hw_nand_init(); } /*@}*/ diff --git a/bsp/mb9bf506r/drivers/fm3_uart.c b/bsp/mb9bf506r/drivers/fm3_uart.c index ca20047f52..ece042cca4 100644 --- a/bsp/mb9bf506r/drivers/fm3_uart.c +++ b/bsp/mb9bf506r/drivers/fm3_uart.c @@ -17,19 +17,19 @@ /* UART0 device driver structure */ struct uart03_device uart0 = { - FM3_MFS0_UART, - MFS0RX_IRQn, - MFS0TX_IRQn, + FM3_MFS0_UART, + MFS0RX_IRQn, + MFS0TX_IRQn, }; struct rt_serial_device serial0; void MFS0RX_IRQHandler(void) { - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND); - /* leave interrupt */ - rt_interrupt_leave(); + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND); + /* leave interrupt */ + rt_interrupt_leave(); } #endif @@ -37,19 +37,19 @@ void MFS0RX_IRQHandler(void) /* UART1 device driver structure */ struct uart03_device uart1 = { - FM3_MFS1_UART, - MFS1RX_IRQn, - MFS1TX_IRQn, + FM3_MFS1_UART, + MFS1RX_IRQn, + MFS1TX_IRQn, }; struct rt_serial_device serial1; void MFS1RX_IRQHandler(void) { - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND); - /* leave interrupt */ - rt_interrupt_leave(); + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND); + /* leave interrupt */ + rt_interrupt_leave(); } #endif @@ -57,19 +57,19 @@ void MFS1RX_IRQHandler(void) /* UART2 device driver structure */ struct uart03_device uart2 = { - FM3_MFS2_UART, - MFS2RX_IRQn, - MFS2TX_IRQn, + FM3_MFS2_UART, + MFS2RX_IRQn, + MFS2TX_IRQn, }; struct rt_serial_device serial2; void MFS2RX_IRQHandler(void) { - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND); - /* leave interrupt */ - rt_interrupt_leave(); + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND); + /* leave interrupt */ + rt_interrupt_leave(); } #endif @@ -77,19 +77,19 @@ void MFS2RX_IRQHandler(void) /* UART3 device driver structure */ struct uart03_device uart3 = { - FM3_MFS3_UART, - MFS3RX_IRQn, - MFS3TX_IRQn, + FM3_MFS3_UART, + MFS3RX_IRQn, + MFS3TX_IRQn, }; struct rt_serial_device serial3; void MFS3RX_IRQHandler(void) { - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&serial3, RT_SERIAL_EVENT_RX_IND); - /* leave interrupt */ - rt_interrupt_leave(); + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&serial3, RT_SERIAL_EVENT_RX_IND); + /* leave interrupt */ + rt_interrupt_leave(); } #endif @@ -97,20 +97,20 @@ void MFS3RX_IRQHandler(void) /* UART4 device driver structure */ struct uart47_device uart4 = { - FM3_MFS4_UART, - MFS4RX_IRQn, - MFS4TX_IRQn, - FIFO_SIZE, + FM3_MFS4_UART, + MFS4RX_IRQn, + MFS4TX_IRQn, + FIFO_SIZE, }; struct rt_serial_device serial4; void MFS4RX_IRQHandler(void) { - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&serial4, RT_SERIAL_EVENT_RX_IND); - /* leave interrupt */ - rt_interrupt_leave(); + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&serial4, RT_SERIAL_EVENT_RX_IND); + /* leave interrupt */ + rt_interrupt_leave(); } #endif @@ -118,20 +118,20 @@ void MFS4RX_IRQHandler(void) /* UART5 device driver structure */ struct uart47_device uart5 = { - FM3_MFS5_UART, - MFS5RX_IRQn, - MFS5TX_IRQn, - FIFO_SIZE, + FM3_MFS5_UART, + MFS5RX_IRQn, + MFS5TX_IRQn, + FIFO_SIZE, }; struct rt_serial_device serial5; void MFS5RX_IRQHandler(void) { - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&serial5, RT_SERIAL_EVENT_RX_IND); - /* leave interrupt */ - rt_interrupt_leave(); + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&serial5, RT_SERIAL_EVENT_RX_IND); + /* leave interrupt */ + rt_interrupt_leave(); } #endif @@ -139,20 +139,20 @@ void MFS5RX_IRQHandler(void) /* UART6 device driver structure */ struct uart47_device uart6 = { - FM3_MFS6_UART, - MFS6RX_IRQn, - MFS6TX_IRQn, - FIFO_SIZE, + FM3_MFS6_UART, + MFS6RX_IRQn, + MFS6TX_IRQn, + FIFO_SIZE, }; struct rt_serial_device serial6; void MFS6RX_IRQHandler(void) { - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&serial6, RT_SERIAL_EVENT_RX_IND); - /* leave interrupt */ - rt_interrupt_leave(); + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&serial6, RT_SERIAL_EVENT_RX_IND); + /* leave interrupt */ + rt_interrupt_leave(); } #endif @@ -160,20 +160,20 @@ void MFS6RX_IRQHandler(void) /* UART7 device driver structure */ struct uart47_device uart7 = { - FM3_MFS7_UART, - MFS7RX_IRQn, - MFS7TX_IRQn, - FIFO_SIZE, + FM3_MFS7_UART, + MFS7RX_IRQn, + MFS7TX_IRQn, + FIFO_SIZE, }; struct rt_serial_device serial7; void MFS7RX_IRQHandler(void) { - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&serial7, RT_SERIAL_EVENT_RX_IND); - /* leave interrupt */ - rt_interrupt_leave(); + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&serial7, RT_SERIAL_EVENT_RX_IND); + /* leave interrupt */ + rt_interrupt_leave(); } #endif @@ -181,749 +181,749 @@ void MFS7RX_IRQHandler(void) void uart_pin_setup(void) { #if defined(RT_USING_UART0_0) - /* Set UART Ch0 Port, SIN0_0(P21), SOT0_0(P22) */ - FM3_GPIO->PFR2_f.P1 = 1; - FM3_GPIO->PFR2_f.P2 = 1; - FM3_GPIO->EPFR07_f.SIN0S0 = 1; - FM3_GPIO->EPFR07_f.SIN0S1 = 0; - FM3_GPIO->EPFR07_f.SOT0B0 = 1; - FM3_GPIO->EPFR07_f.SOT0B1 = 0; + /* Set UART Ch0 Port, SIN0_0(P21), SOT0_0(P22) */ + FM3_GPIO->PFR2_f.P1 = 1; + FM3_GPIO->PFR2_f.P2 = 1; + FM3_GPIO->EPFR07_f.SIN0S0 = 1; + FM3_GPIO->EPFR07_f.SIN0S1 = 0; + FM3_GPIO->EPFR07_f.SOT0B0 = 1; + FM3_GPIO->EPFR07_f.SOT0B1 = 0; #elif defined(RT_USING_UART0_1) - /* Set UART Ch0 Port, SIN0_1(P14), SOT0_1(P15) */ - FM3_GPIO->PFR1_f.P4 = 1; - FM3_GPIO->PFR1_f.P5 = 1; - FM3_GPIO->EPFR07_f.SIN0S0 = 0; - FM3_GPIO->EPFR07_f.SIN0S1 = 1; - FM3_GPIO->EPFR07_f.SOT0B0 = 0; - FM3_GPIO->EPFR07_f.SOT0B1 = 1; + /* Set UART Ch0 Port, SIN0_1(P14), SOT0_1(P15) */ + FM3_GPIO->PFR1_f.P4 = 1; + FM3_GPIO->PFR1_f.P5 = 1; + FM3_GPIO->EPFR07_f.SIN0S0 = 0; + FM3_GPIO->EPFR07_f.SIN0S1 = 1; + FM3_GPIO->EPFR07_f.SOT0B0 = 0; + FM3_GPIO->EPFR07_f.SOT0B1 = 1; #endif #if defined(RT_USING_UART1_0) - /* Set UART Ch1 Port, SIN1_0(P56), SOT1_0(P57) */ - FM3_GPIO->PFR5_f.P6 = 1; - FM3_GPIO->PFR5_f.P7 = 1; - FM3_GPIO->EPFR07_f.SIN1S0 = 1; - FM3_GPIO->EPFR07_f.SIN1S1 = 0; - FM3_GPIO->EPFR07_f.SOT1B0 = 1; - FM3_GPIO->EPFR07_f.SOT1B1 = 0; + /* Set UART Ch1 Port, SIN1_0(P56), SOT1_0(P57) */ + FM3_GPIO->PFR5_f.P6 = 1; + FM3_GPIO->PFR5_f.P7 = 1; + FM3_GPIO->EPFR07_f.SIN1S0 = 1; + FM3_GPIO->EPFR07_f.SIN1S1 = 0; + FM3_GPIO->EPFR07_f.SOT1B0 = 1; + FM3_GPIO->EPFR07_f.SOT1B1 = 0; #elif defined(RT_USING_UART1_1) - /* Set UART Ch1 Port, SIN1_1(P11), SOT1_1(P12) */ - FM3_GPIO->PFR1_f.P1 = 1; - FM3_GPIO->PFR1_f.P2 = 1; - FM3_GPIO->EPFR07_f.SIN1S0 = 0; - FM3_GPIO->EPFR07_f.SIN1S1 = 1; - FM3_GPIO->EPFR07_f.SOT1B0 = 0; - FM3_GPIO->EPFR07_f.SOT1B1 = 1; + /* Set UART Ch1 Port, SIN1_1(P11), SOT1_1(P12) */ + FM3_GPIO->PFR1_f.P1 = 1; + FM3_GPIO->PFR1_f.P2 = 1; + FM3_GPIO->EPFR07_f.SIN1S0 = 0; + FM3_GPIO->EPFR07_f.SIN1S1 = 1; + FM3_GPIO->EPFR07_f.SOT1B0 = 0; + FM3_GPIO->EPFR07_f.SOT1B1 = 1; #endif #if defined(RT_USING_UART2_0) - /* Set UART Ch2 Port, SIN2_0(P72), SOT2_0(P73) */ - FM3_GPIO->PFR7_f.P2 = 1; - FM3_GPIO->PFR7_f.P3 = 1; - FM3_GPIO->EPFR07_f.SIN2S0 = 1; - FM3_GPIO->EPFR07_f.SIN2S1 = 0; - FM3_GPIO->EPFR07_f.SOT2B0 = 1; - FM3_GPIO->EPFR07_f.SOT2B1 = 0; + /* Set UART Ch2 Port, SIN2_0(P72), SOT2_0(P73) */ + FM3_GPIO->PFR7_f.P2 = 1; + FM3_GPIO->PFR7_f.P3 = 1; + FM3_GPIO->EPFR07_f.SIN2S0 = 1; + FM3_GPIO->EPFR07_f.SIN2S1 = 0; + FM3_GPIO->EPFR07_f.SOT2B0 = 1; + FM3_GPIO->EPFR07_f.SOT2B1 = 0; #elif defined(RT_USING_UART2_1) - /* Set UART Ch2 Port, SIN2_1(P24), SOT2_1(P25) */ - FM3_GPIO->PFR2_f.P4 = 1; - FM3_GPIO->PFR2_f.P5 = 1; - FM3_GPIO->EPFR07_f.SIN2S0 = 0; - FM3_GPIO->EPFR07_f.SIN2S1 = 1; - FM3_GPIO->EPFR07_f.SOT2B0 = 0; - FM3_GPIO->EPFR07_f.SOT2B1 = 1; + /* Set UART Ch2 Port, SIN2_1(P24), SOT2_1(P25) */ + FM3_GPIO->PFR2_f.P4 = 1; + FM3_GPIO->PFR2_f.P5 = 1; + FM3_GPIO->EPFR07_f.SIN2S0 = 0; + FM3_GPIO->EPFR07_f.SIN2S1 = 1; + FM3_GPIO->EPFR07_f.SOT2B0 = 0; + FM3_GPIO->EPFR07_f.SOT2B1 = 1; #elif defined(RT_USING_UART2_2) - /* Set UART Ch2 Port, SIN2_2(P17), SOT2_2(P18) */ - FM3_GPIO->PFR1_f.P7 = 1; - FM3_GPIO->PFR1_f.P8 = 1; - FM3_GPIO->EPFR07_f.SIN2S0 = 1; - FM3_GPIO->EPFR07_f.SIN2S1 = 1; - FM3_GPIO->EPFR07_f.SOT2B0 = 1; - FM3_GPIO->EPFR07_f.SOT2B1 = 1; + /* Set UART Ch2 Port, SIN2_2(P17), SOT2_2(P18) */ + FM3_GPIO->PFR1_f.P7 = 1; + FM3_GPIO->PFR1_f.P8 = 1; + FM3_GPIO->EPFR07_f.SIN2S0 = 1; + FM3_GPIO->EPFR07_f.SIN2S1 = 1; + FM3_GPIO->EPFR07_f.SOT2B0 = 1; + FM3_GPIO->EPFR07_f.SOT2B1 = 1; #endif #if defined(RT_USING_UART3_0) - /* Set UART Ch3 Port, SIN3_0(P66), SOT3_0(P67) */ - FM3_GPIO->PFR6_f.P6 = 1; - FM3_GPIO->PFR6_f.P7 = 1; - FM3_GPIO->EPFR07_f.SIN3S0 = 1; - FM3_GPIO->EPFR07_f.SIN3S1 = 0; - FM3_GPIO->EPFR07_f.SOT3B0 = 1; - FM3_GPIO->EPFR07_f.SOT3B1 = 0; + /* Set UART Ch3 Port, SIN3_0(P66), SOT3_0(P67) */ + FM3_GPIO->PFR6_f.P6 = 1; + FM3_GPIO->PFR6_f.P7 = 1; + FM3_GPIO->EPFR07_f.SIN3S0 = 1; + FM3_GPIO->EPFR07_f.SIN3S1 = 0; + FM3_GPIO->EPFR07_f.SOT3B0 = 1; + FM3_GPIO->EPFR07_f.SOT3B1 = 0; #elif defined(RT_USING_UART3_1) - /* Set UART Ch3 Port, SIN3_1(P50), SOT3_1(P51) */ - FM3_GPIO->PFR5_f.P0 = 1; - FM3_GPIO->PFR5_f.P1 = 1; - FM3_GPIO->EPFR07_f.SIN3S0 = 0; - FM3_GPIO->EPFR07_f.SIN3S1 = 1; - FM3_GPIO->EPFR07_f.SOT3B0 = 0; - FM3_GPIO->EPFR07_f.SOT3B1 = 1; + /* Set UART Ch3 Port, SIN3_1(P50), SOT3_1(P51) */ + FM3_GPIO->PFR5_f.P0 = 1; + FM3_GPIO->PFR5_f.P1 = 1; + FM3_GPIO->EPFR07_f.SIN3S0 = 0; + FM3_GPIO->EPFR07_f.SIN3S1 = 1; + FM3_GPIO->EPFR07_f.SOT3B0 = 0; + FM3_GPIO->EPFR07_f.SOT3B1 = 1; #elif defined(RT_USING_UART3_2) - /* Set UART Ch3 Port, SIN3_2(P48), SOT3_2(P49) */ - FM3_GPIO->PFR4_f.P8 = 1; - FM3_GPIO->PFR4_f.P9 = 1; - FM3_GPIO->EPFR07_f.SIN3S0 = 1; - FM3_GPIO->EPFR07_f.SIN3S1 = 1; - FM3_GPIO->EPFR07_f.SOT3B0 = 1; - FM3_GPIO->EPFR07_f.SOT3B1 = 1; + /* Set UART Ch3 Port, SIN3_2(P48), SOT3_2(P49) */ + FM3_GPIO->PFR4_f.P8 = 1; + FM3_GPIO->PFR4_f.P9 = 1; + FM3_GPIO->EPFR07_f.SIN3S0 = 1; + FM3_GPIO->EPFR07_f.SIN3S1 = 1; + FM3_GPIO->EPFR07_f.SOT3B0 = 1; + FM3_GPIO->EPFR07_f.SOT3B1 = 1; #endif #if defined(RT_USING_UART4_0) - /* Set UART Ch4 Port, SIN4_0(P0A), SOT4_0(P0B), CTS4_0(P0E), RTS4_0(P0D) */ - FM3_GPIO->PFR0_f.PA = 1; - FM3_GPIO->PFR0_f.PB = 1; - FM3_GPIO->PFR0_f.PD = 1; - FM3_GPIO->PFR0_f.PE = 1; - FM3_GPIO->EPFR08_f.SIN4S0 = 1; - FM3_GPIO->EPFR08_f.SIN4S1 = 0; - FM3_GPIO->EPFR08_f.SOT4B0 = 1; - FM3_GPIO->EPFR08_f.SOT4B1 = 0; - FM3_GPIO->EPFR08_f.CTS4S0 = 1; - FM3_GPIO->EPFR08_f.CTS4S1 = 0; - FM3_GPIO->EPFR08_f.RTS4E0 = 1; - FM3_GPIO->EPFR08_f.RTS4E1 = 0; + /* Set UART Ch4 Port, SIN4_0(P0A), SOT4_0(P0B), CTS4_0(P0E), RTS4_0(P0D) */ + FM3_GPIO->PFR0_f.PA = 1; + FM3_GPIO->PFR0_f.PB = 1; + FM3_GPIO->PFR0_f.PD = 1; + FM3_GPIO->PFR0_f.PE = 1; + FM3_GPIO->EPFR08_f.SIN4S0 = 1; + FM3_GPIO->EPFR08_f.SIN4S1 = 0; + FM3_GPIO->EPFR08_f.SOT4B0 = 1; + FM3_GPIO->EPFR08_f.SOT4B1 = 0; + FM3_GPIO->EPFR08_f.CTS4S0 = 1; + FM3_GPIO->EPFR08_f.CTS4S1 = 0; + FM3_GPIO->EPFR08_f.RTS4E0 = 1; + FM3_GPIO->EPFR08_f.RTS4E1 = 0; #elif defined(RT_USING_UART4_1) - /* Set UART Ch4 Port, SIN4_1(P1A), SOT4_1(P1B), CTS4_1(P1D), RTS4_1(P1E) */ - FM3_GPIO->PFR1_f.PA = 1; - FM3_GPIO->PFR1_f.PB = 1; - FM3_GPIO->PFR1_f.PD = 1; - FM3_GPIO->PFR1_f.PE = 1; - FM3_GPIO->EPFR08_f.SIN4S0 = 0; - FM3_GPIO->EPFR08_f.SIN4S1 = 1; - FM3_GPIO->EPFR08_f.SOT4B0 = 0; - FM3_GPIO->EPFR08_f.SOT4B1 = 1; - FM3_GPIO->EPFR08_f.CTS4S0 = 0; - FM3_GPIO->EPFR08_f.CTS4S1 = 1; - FM3_GPIO->EPFR08_f.RTS4E0 = 0; - FM3_GPIO->EPFR08_f.RTS4E1 = 1; + /* Set UART Ch4 Port, SIN4_1(P1A), SOT4_1(P1B), CTS4_1(P1D), RTS4_1(P1E) */ + FM3_GPIO->PFR1_f.PA = 1; + FM3_GPIO->PFR1_f.PB = 1; + FM3_GPIO->PFR1_f.PD = 1; + FM3_GPIO->PFR1_f.PE = 1; + FM3_GPIO->EPFR08_f.SIN4S0 = 0; + FM3_GPIO->EPFR08_f.SIN4S1 = 1; + FM3_GPIO->EPFR08_f.SOT4B0 = 0; + FM3_GPIO->EPFR08_f.SOT4B1 = 1; + FM3_GPIO->EPFR08_f.CTS4S0 = 0; + FM3_GPIO->EPFR08_f.CTS4S1 = 1; + FM3_GPIO->EPFR08_f.RTS4E0 = 0; + FM3_GPIO->EPFR08_f.RTS4E1 = 1; #elif defined(RT_USING_UART4_2) - /* Set UART Ch4 Port, SIN4_2(P05), SOT4_2(P06), CTS4_2(P08), RTS4_2(P09)*/ - FM3_GPIO->PFR0_f.P5 = 1; - FM3_GPIO->PFR0_f.P6 = 1; - FM3_GPIO->PFR0_f.P8 = 1; - FM3_GPIO->PFR0_f.P9 = 1; - FM3_GPIO->EPFR08_f.SIN4S0 = 1; - FM3_GPIO->EPFR08_f.SIN4S1 = 1; - FM3_GPIO->EPFR08_f.SOT4B0 = 1; - FM3_GPIO->EPFR08_f.SOT4B1 = 1; - FM3_GPIO->EPFR08_f.CTS4S0 = 1; - FM3_GPIO->EPFR08_f.CTS4S1 = 1; - FM3_GPIO->EPFR08_f.RTS4E0 = 1; - FM3_GPIO->EPFR08_f.RTS4E1 = 1; + /* Set UART Ch4 Port, SIN4_2(P05), SOT4_2(P06), CTS4_2(P08), RTS4_2(P09)*/ + FM3_GPIO->PFR0_f.P5 = 1; + FM3_GPIO->PFR0_f.P6 = 1; + FM3_GPIO->PFR0_f.P8 = 1; + FM3_GPIO->PFR0_f.P9 = 1; + FM3_GPIO->EPFR08_f.SIN4S0 = 1; + FM3_GPIO->EPFR08_f.SIN4S1 = 1; + FM3_GPIO->EPFR08_f.SOT4B0 = 1; + FM3_GPIO->EPFR08_f.SOT4B1 = 1; + FM3_GPIO->EPFR08_f.CTS4S0 = 1; + FM3_GPIO->EPFR08_f.CTS4S1 = 1; + FM3_GPIO->EPFR08_f.RTS4E0 = 1; + FM3_GPIO->EPFR08_f.RTS4E1 = 1; #endif #if defined(RT_USING_UART5_0) - /* Set UART Ch5 Port, SIN5_0(P60), SOT5_0(P61) */ - FM3_GPIO->PFR6_f.P0 = 1; - FM3_GPIO->PFR6_f.P1 = 1; - FM3_GPIO->EPFR08_f.SIN5S0 = 1; - FM3_GPIO->EPFR08_f.SIN5S1 = 0; - FM3_GPIO->EPFR08_f.SOT5B0 = 1; - FM3_GPIO->EPFR08_f.SOT5B1 = 0; + /* Set UART Ch5 Port, SIN5_0(P60), SOT5_0(P61) */ + FM3_GPIO->PFR6_f.P0 = 1; + FM3_GPIO->PFR6_f.P1 = 1; + FM3_GPIO->EPFR08_f.SIN5S0 = 1; + FM3_GPIO->EPFR08_f.SIN5S1 = 0; + FM3_GPIO->EPFR08_f.SOT5B0 = 1; + FM3_GPIO->EPFR08_f.SOT5B1 = 0; #elif defined(RT_USING_UART5_1) - /* Set UART Ch5 Port, SIN5_1(P63), SOT5_1(P64) */ - FM3_GPIO->PFR6_f.P3 = 1; - FM3_GPIO->PFR6_f.P4 = 1; - FM3_GPIO->EPFR08_f.SIN5S0 = 0; - FM3_GPIO->EPFR08_f.SIN5S1 = 1; - FM3_GPIO->EPFR08_f.SOT5B0 = 0; - FM3_GPIO->EPFR08_f.SOT5B1 = 1; + /* Set UART Ch5 Port, SIN5_1(P63), SOT5_1(P64) */ + FM3_GPIO->PFR6_f.P3 = 1; + FM3_GPIO->PFR6_f.P4 = 1; + FM3_GPIO->EPFR08_f.SIN5S0 = 0; + FM3_GPIO->EPFR08_f.SIN5S1 = 1; + FM3_GPIO->EPFR08_f.SOT5B0 = 0; + FM3_GPIO->EPFR08_f.SOT5B1 = 1; #elif defined(RT_USING_UART5_2) - /* Set UART Ch5 Port, SIN5_2(P36), SOT5_2(P37) */ - FM3_GPIO->PFR3_f.P6 = 1; - FM3_GPIO->PFR3_f.P7 = 1; - FM3_GPIO->EPFR08_f.SIN5S0 = 1; - FM3_GPIO->EPFR08_f.SIN5S1 = 1; - FM3_GPIO->EPFR08_f.SOT5B0 = 1; - FM3_GPIO->EPFR08_f.SOT5B1 = 1; + /* Set UART Ch5 Port, SIN5_2(P36), SOT5_2(P37) */ + FM3_GPIO->PFR3_f.P6 = 1; + FM3_GPIO->PFR3_f.P7 = 1; + FM3_GPIO->EPFR08_f.SIN5S0 = 1; + FM3_GPIO->EPFR08_f.SIN5S1 = 1; + FM3_GPIO->EPFR08_f.SOT5B0 = 1; + FM3_GPIO->EPFR08_f.SOT5B1 = 1; #endif #if defined(RT_USING_UART6_0) - /* Set UART Ch6 Port, SIN6_0(P53), SOT6_0(P54) */ - FM3_GPIO->PFR5_f.P3 = 1; - FM3_GPIO->PFR5_f.P4 = 1; - FM3_GPIO->EPFR08_f.SIN6S0 = 1; - FM3_GPIO->EPFR08_f.SIN6S1 = 0; - FM3_GPIO->EPFR08_f.SOT6B0 = 1; - FM3_GPIO->EPFR08_f.SOT6B1 = 0; + /* Set UART Ch6 Port, SIN6_0(P53), SOT6_0(P54) */ + FM3_GPIO->PFR5_f.P3 = 1; + FM3_GPIO->PFR5_f.P4 = 1; + FM3_GPIO->EPFR08_f.SIN6S0 = 1; + FM3_GPIO->EPFR08_f.SIN6S1 = 0; + FM3_GPIO->EPFR08_f.SOT6B0 = 1; + FM3_GPIO->EPFR08_f.SOT6B1 = 0; #elif defined(RT_USING_UART6_1) - /* Set UART Ch6 Port, SIN6_1(P33), SOT6_1(P32) */ - FM3_GPIO->PFR3_f.P2 = 1; - FM3_GPIO->PFR3_f.P3 = 1; - FM3_GPIO->EPFR08_f.SIN6S0 = 0; - FM3_GPIO->EPFR08_f.SIN6S1 = 1; - FM3_GPIO->EPFR08_f.SOT6B0 = 0; - FM3_GPIO->EPFR08_f.SOT6B1 = 1; + /* Set UART Ch6 Port, SIN6_1(P33), SOT6_1(P32) */ + FM3_GPIO->PFR3_f.P2 = 1; + FM3_GPIO->PFR3_f.P3 = 1; + FM3_GPIO->EPFR08_f.SIN6S0 = 0; + FM3_GPIO->EPFR08_f.SIN6S1 = 1; + FM3_GPIO->EPFR08_f.SOT6B0 = 0; + FM3_GPIO->EPFR08_f.SOT6B1 = 1; #endif #if defined(RT_USING_UART7_0) - /* Set UART Ch7 Port, SIN7_0(P59), SOT7_0(P5A) */ - FM3_GPIO->PFR5_f.P9 = 1; - FM3_GPIO->PFR5_f.PA = 1; - FM3_GPIO->EPFR08_f.SIN7S0 = 1; - FM3_GPIO->EPFR08_f.SIN7S1 = 0; - FM3_GPIO->EPFR08_f.SOT7B0 = 1; - FM3_GPIO->EPFR08_f.SOT7B1 = 0; + /* Set UART Ch7 Port, SIN7_0(P59), SOT7_0(P5A) */ + FM3_GPIO->PFR5_f.P9 = 1; + FM3_GPIO->PFR5_f.PA = 1; + FM3_GPIO->EPFR08_f.SIN7S0 = 1; + FM3_GPIO->EPFR08_f.SIN7S1 = 0; + FM3_GPIO->EPFR08_f.SOT7B0 = 1; + FM3_GPIO->EPFR08_f.SOT7B1 = 0; #elif defined(RT_USING_UART7_1) - /* Set UART Ch7 Port, SIN7_1(P4E), SOT7_1(P4D) */ - FM3_GPIO->PFR4_f.PD = 1; - FM3_GPIO->PFR4_f.PE = 1; - FM3_GPIO->EPFR08_f.SIN7S0 = 0; - FM3_GPIO->EPFR08_f.SIN7S1 = 1; - FM3_GPIO->EPFR08_f.SOT7B0 = 0; - FM3_GPIO->EPFR08_f.SOT7B1 = 1; + /* Set UART Ch7 Port, SIN7_1(P4E), SOT7_1(P4D) */ + FM3_GPIO->PFR4_f.PD = 1; + FM3_GPIO->PFR4_f.PE = 1; + FM3_GPIO->EPFR08_f.SIN7S0 = 0; + FM3_GPIO->EPFR08_f.SIN7S1 = 1; + FM3_GPIO->EPFR08_f.SOT7B0 = 0; + FM3_GPIO->EPFR08_f.SOT7B1 = 1; #endif } static rt_err_t uart03_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { - struct uart03_device *uart; - - RT_ASSERT(serial != RT_NULL); - - uart = (struct uart03_device *)serial->parent.user_data; - - uart->uart_regs->SMR = SMR_MD_UART | SMR_SOE; - - /* set baudreate */ - uart->uart_regs->BGR = (40000000UL + (cfg->baud_rate/2))/cfg->baud_rate - 1; - - /* set stop bits */ - switch (cfg->stop_bits) - { - case STOP_BITS_1: - uart->uart_regs->SMR_f.SBL = 0; - uart->uart_regs->ESCR_f.ESBL = 0; - break; - case STOP_BITS_2: - uart->uart_regs->SMR_f.SBL = 1; - uart->uart_regs->ESCR_f.ESBL = 0; - break; - case STOP_BITS_3: - uart->uart_regs->SMR_f.SBL = 0; - uart->uart_regs->ESCR_f.ESBL = 1; - break; - case STOP_BITS_4: - uart->uart_regs->SMR_f.SBL = 1; - uart->uart_regs->ESCR_f.ESBL = 1; - break; - default: - return RT_ERROR; - } - - /* set data bits */ - switch (cfg->data_bits) - { - case DATA_BITS_5: - uart->uart_regs->ESCR_f.L0 = 1; - uart->uart_regs->ESCR_f.L1 = 0; - uart->uart_regs->ESCR_f.L2 = 0; - break; - case DATA_BITS_6: - uart->uart_regs->ESCR_f.L0 = 0; - uart->uart_regs->ESCR_f.L1 = 1; - uart->uart_regs->ESCR_f.L2 = 0; - break; - case DATA_BITS_7: - uart->uart_regs->ESCR_f.L0 = 1; - uart->uart_regs->ESCR_f.L1 = 1; - uart->uart_regs->ESCR_f.L2 = 0; - break; - case DATA_BITS_8: - uart->uart_regs->ESCR_f.L0 = 0; - uart->uart_regs->ESCR_f.L1 = 0; - uart->uart_regs->ESCR_f.L2 = 0; - break; - case DATA_BITS_9: - uart->uart_regs->ESCR_f.L0 = 0; - uart->uart_regs->ESCR_f.L1 = 0; - uart->uart_regs->ESCR_f.L2 = 1; - break; - default: - return RT_ERROR; - } - - /* set parity */ - switch (cfg->parity) - { - case PARITY_NONE: - uart->uart_regs->ESCR_f.PEN = 0; - break; - case PARITY_EVEN: - uart->uart_regs->ESCR_f.PEN = 1; - uart->uart_regs->ESCR_f.P = 0; - break; - case PARITY_ODD: - uart->uart_regs->ESCR_f.PEN = 1; - uart->uart_regs->ESCR_f.P = 1; - break; - default: - return RT_ERROR; - } - - /* set bit order */ - switch (cfg->bit_order) - { - case BIT_ORDER_LSB: - uart->uart_regs->SMR_f.BDS = 0; - break; - case BIT_ORDER_MSB: - uart->uart_regs->SMR_f.BDS = 1; - break; - default: - return RT_ERROR; - } - - /* set NRZ mode */ - switch (cfg->invert) - { - case NRZ_NORMAL: - uart->uart_regs->ESCR_f.INV = 0; - break; - case NRZ_INVERTED: - uart->uart_regs->ESCR_f.INV = 1; - break; - default: - return RT_ERROR; - } - - uart->uart_regs->SCR = SCR_RXE | SCR_TXE | SCR_RIE; - - return RT_EOK; + struct uart03_device *uart; + + RT_ASSERT(serial != RT_NULL); + + uart = (struct uart03_device *)serial->parent.user_data; + + uart->uart_regs->SMR = SMR_MD_UART | SMR_SOE; + + /* set baudreate */ + uart->uart_regs->BGR = (40000000UL + (cfg->baud_rate/2))/cfg->baud_rate - 1; + + /* set stop bits */ + switch (cfg->stop_bits) + { + case STOP_BITS_1: + uart->uart_regs->SMR_f.SBL = 0; + uart->uart_regs->ESCR_f.ESBL = 0; + break; + case STOP_BITS_2: + uart->uart_regs->SMR_f.SBL = 1; + uart->uart_regs->ESCR_f.ESBL = 0; + break; + case STOP_BITS_3: + uart->uart_regs->SMR_f.SBL = 0; + uart->uart_regs->ESCR_f.ESBL = 1; + break; + case STOP_BITS_4: + uart->uart_regs->SMR_f.SBL = 1; + uart->uart_regs->ESCR_f.ESBL = 1; + break; + default: + return RT_ERROR; + } + + /* set data bits */ + switch (cfg->data_bits) + { + case DATA_BITS_5: + uart->uart_regs->ESCR_f.L0 = 1; + uart->uart_regs->ESCR_f.L1 = 0; + uart->uart_regs->ESCR_f.L2 = 0; + break; + case DATA_BITS_6: + uart->uart_regs->ESCR_f.L0 = 0; + uart->uart_regs->ESCR_f.L1 = 1; + uart->uart_regs->ESCR_f.L2 = 0; + break; + case DATA_BITS_7: + uart->uart_regs->ESCR_f.L0 = 1; + uart->uart_regs->ESCR_f.L1 = 1; + uart->uart_regs->ESCR_f.L2 = 0; + break; + case DATA_BITS_8: + uart->uart_regs->ESCR_f.L0 = 0; + uart->uart_regs->ESCR_f.L1 = 0; + uart->uart_regs->ESCR_f.L2 = 0; + break; + case DATA_BITS_9: + uart->uart_regs->ESCR_f.L0 = 0; + uart->uart_regs->ESCR_f.L1 = 0; + uart->uart_regs->ESCR_f.L2 = 1; + break; + default: + return RT_ERROR; + } + + /* set parity */ + switch (cfg->parity) + { + case PARITY_NONE: + uart->uart_regs->ESCR_f.PEN = 0; + break; + case PARITY_EVEN: + uart->uart_regs->ESCR_f.PEN = 1; + uart->uart_regs->ESCR_f.P = 0; + break; + case PARITY_ODD: + uart->uart_regs->ESCR_f.PEN = 1; + uart->uart_regs->ESCR_f.P = 1; + break; + default: + return RT_ERROR; + } + + /* set bit order */ + switch (cfg->bit_order) + { + case BIT_ORDER_LSB: + uart->uart_regs->SMR_f.BDS = 0; + break; + case BIT_ORDER_MSB: + uart->uart_regs->SMR_f.BDS = 1; + break; + default: + return RT_ERROR; + } + + /* set NRZ mode */ + switch (cfg->invert) + { + case NRZ_NORMAL: + uart->uart_regs->ESCR_f.INV = 0; + break; + case NRZ_INVERTED: + uart->uart_regs->ESCR_f.INV = 1; + break; + default: + return RT_ERROR; + } + + uart->uart_regs->SCR = SCR_RXE | SCR_TXE | SCR_RIE; + + return RT_EOK; } - + static rt_err_t uart03_control(struct rt_serial_device *serial, int cmd, void *arg) { - struct uart03_device *uart; - - RT_ASSERT(serial != RT_NULL); - uart = (struct uart03_device *)serial->parent.user_data; - - switch (cmd) - { - case RT_DEVICE_CTRL_CLR_INT: - /* disable rx irq */ - UART_DISABLE_IRQ(uart->rx_irq); - break; - case RT_DEVICE_CTRL_SET_INT: - /* enable rx irq */ - UART_ENABLE_IRQ(uart->rx_irq); - break; - } - - return (RT_EOK); + struct uart03_device *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct uart03_device *)serial->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + UART_DISABLE_IRQ(uart->rx_irq); + break; + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + UART_ENABLE_IRQ(uart->rx_irq); + break; + } + + return (RT_EOK); } - + static int uart03_putc(struct rt_serial_device *serial, char c) { - struct uart03_device *uart; + struct uart03_device *uart; + + RT_ASSERT(serial != RT_NULL); - RT_ASSERT(serial != RT_NULL); - - uart = (struct uart03_device *)serial->parent.user_data; - /* while send buffer is empty */ - while (!(uart->uart_regs->SSR & SSR_TDRE)); - /* write to send buffer */ - uart->uart_regs->TDR = c; + uart = (struct uart03_device *)serial->parent.user_data; + /* while send buffer is empty */ + while (!(uart->uart_regs->SSR & SSR_TDRE)); + /* write to send buffer */ + uart->uart_regs->TDR = c; - return (1); + return (1); } static int uart03_getc(struct rt_serial_device *serial) -{ - struct uart03_device *uart; - int ch; - - RT_ASSERT(serial != RT_NULL); - - uart = (struct uart03_device *)serial->parent.user_data; - /* receive buffer is full */ - if (uart->uart_regs->SSR & SSR_RDRF) - { - ch = uart->uart_regs->RDR & 0xff; - return (ch); - } - else - return (-1); +{ + struct uart03_device *uart; + int ch; + + RT_ASSERT(serial != RT_NULL); + + uart = (struct uart03_device *)serial->parent.user_data; + /* receive buffer is full */ + if (uart->uart_regs->SSR & SSR_RDRF) + { + ch = uart->uart_regs->RDR & 0xff; + return (ch); + } + else + return (-1); } static struct rt_uart_ops uart03_ops = { - uart03_configure, - uart03_control, - uart03_putc, - uart03_getc, + uart03_configure, + uart03_control, + uart03_putc, + uart03_getc, }; static rt_err_t uart47_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { - struct uart47_device *uart; - - RT_ASSERT(serial != RT_NULL); - - uart = (struct uart47_device *)serial->parent.user_data; - - uart->uart_regs->SMR = SMR_MD_UART | SMR_SOE; - - /* set baudreate */ - uart->uart_regs->BGR = (40000000UL + (cfg->baud_rate/2))/cfg->baud_rate - 1; - - /* set stop bits */ - switch (cfg->stop_bits) - { - case STOP_BITS_1: - uart->uart_regs->SMR_f.SBL = 0; - uart->uart_regs->ESCR_f.ESBL = 0; - break; - case STOP_BITS_2: - uart->uart_regs->SMR_f.SBL = 1; - uart->uart_regs->ESCR_f.ESBL = 0; - break; - case STOP_BITS_3: - uart->uart_regs->SMR_f.SBL = 0; - uart->uart_regs->ESCR_f.ESBL = 1; - break; - case STOP_BITS_4: - uart->uart_regs->SMR_f.SBL = 1; - uart->uart_regs->ESCR_f.ESBL = 1; - break; - default: - return RT_ERROR; - } - - /* set data bits */ - switch (cfg->data_bits) - { - case DATA_BITS_5: - uart->uart_regs->ESCR_f.L0 = 1; - uart->uart_regs->ESCR_f.L1 = 0; - uart->uart_regs->ESCR_f.L2 = 0; - break; - case DATA_BITS_6: - uart->uart_regs->ESCR_f.L0 = 0; - uart->uart_regs->ESCR_f.L1 = 1; - uart->uart_regs->ESCR_f.L2 = 0; - break; - case DATA_BITS_7: - uart->uart_regs->ESCR_f.L0 = 1; - uart->uart_regs->ESCR_f.L1 = 1; - uart->uart_regs->ESCR_f.L2 = 0; - break; - case DATA_BITS_8: - uart->uart_regs->ESCR_f.L0 = 0; - uart->uart_regs->ESCR_f.L1 = 0; - uart->uart_regs->ESCR_f.L2 = 0; - break; - case DATA_BITS_9: - uart->uart_regs->ESCR_f.L0 = 0; - uart->uart_regs->ESCR_f.L1 = 0; - uart->uart_regs->ESCR_f.L2 = 1; - break; - default: - return RT_ERROR; - } - - /* set parity */ - switch (cfg->parity) - { - case PARITY_NONE: - uart->uart_regs->ESCR_f.PEN = 0; - break; - case PARITY_EVEN: - uart->uart_regs->ESCR_f.PEN = 1; - uart->uart_regs->ESCR_f.P = 0; - break; - case PARITY_ODD: - uart->uart_regs->ESCR_f.PEN = 1; - uart->uart_regs->ESCR_f.P = 1; - break; - default: - return RT_ERROR; - } - - /* set bit order */ - switch (cfg->bit_order) - { - case BIT_ORDER_LSB: - uart->uart_regs->SMR_f.BDS = 0; - break; - case BIT_ORDER_MSB: - uart->uart_regs->SMR_f.BDS = 1; - break; - default: - return RT_ERROR; - } - - /* set NRZ mode */ - switch (cfg->invert) - { - case NRZ_NORMAL: - uart->uart_regs->ESCR_f.INV = 0; - break; - case NRZ_INVERTED: - uart->uart_regs->ESCR_f.INV = 1; - break; - default: - return RT_ERROR; - } - - /* configure fifo */ - /* Disable the Data Lost detection */ - uart->uart_regs->FCR1_f.FLSTE = 0; - /* Enable the received FIFO idle detection */ - uart->uart_regs->FCR1_f.FRIE = 1; - /* Requests for the transmit FIFO data */ - uart->uart_regs->FCR1_f.FDRQ = 1; - /* Disable the transmit FIFO interrupt */ - uart->uart_regs->FCR1_f.FTIE = 0; - /* Transmit FIFO:FIFO1; Received FIFO:FIFO2 */ - uart->uart_regs->FCR1_f.FSEL = 0; - - /* Transfer data count */ - uart->uart_regs->FBYTE1 = 0; - /* Set the data count to generate a received interrupt */ - uart->uart_regs->FBYTE2 = uart->fifo_size; - - /* FIFO pointer Not reloaded */ - uart->uart_regs->FCR0_f.FLD = 0; - /* FIFO pointer Not saved */ - uart->uart_regs->FCR0_f.FSET = 0; - /* FIFO2 is reset */ - uart->uart_regs->FCR0_f.FCL2 = 1; - /* FIFO1 is reset */ - uart->uart_regs->FCR0_f.FCL1 = 1; - /* Enables the FIFO2 operation */ - uart->uart_regs->FCR0_f.FE2 = 1; - /* Enables the FIFO1 operation */ - uart->uart_regs->FCR0_f.FE1 = 1; - - /* enable receive and send */ - uart->uart_regs->SCR = SCR_RXE | SCR_TXE | SCR_RIE; - - return RT_EOK; + struct uart47_device *uart; + + RT_ASSERT(serial != RT_NULL); + + uart = (struct uart47_device *)serial->parent.user_data; + + uart->uart_regs->SMR = SMR_MD_UART | SMR_SOE; + + /* set baudreate */ + uart->uart_regs->BGR = (40000000UL + (cfg->baud_rate/2))/cfg->baud_rate - 1; + + /* set stop bits */ + switch (cfg->stop_bits) + { + case STOP_BITS_1: + uart->uart_regs->SMR_f.SBL = 0; + uart->uart_regs->ESCR_f.ESBL = 0; + break; + case STOP_BITS_2: + uart->uart_regs->SMR_f.SBL = 1; + uart->uart_regs->ESCR_f.ESBL = 0; + break; + case STOP_BITS_3: + uart->uart_regs->SMR_f.SBL = 0; + uart->uart_regs->ESCR_f.ESBL = 1; + break; + case STOP_BITS_4: + uart->uart_regs->SMR_f.SBL = 1; + uart->uart_regs->ESCR_f.ESBL = 1; + break; + default: + return RT_ERROR; + } + + /* set data bits */ + switch (cfg->data_bits) + { + case DATA_BITS_5: + uart->uart_regs->ESCR_f.L0 = 1; + uart->uart_regs->ESCR_f.L1 = 0; + uart->uart_regs->ESCR_f.L2 = 0; + break; + case DATA_BITS_6: + uart->uart_regs->ESCR_f.L0 = 0; + uart->uart_regs->ESCR_f.L1 = 1; + uart->uart_regs->ESCR_f.L2 = 0; + break; + case DATA_BITS_7: + uart->uart_regs->ESCR_f.L0 = 1; + uart->uart_regs->ESCR_f.L1 = 1; + uart->uart_regs->ESCR_f.L2 = 0; + break; + case DATA_BITS_8: + uart->uart_regs->ESCR_f.L0 = 0; + uart->uart_regs->ESCR_f.L1 = 0; + uart->uart_regs->ESCR_f.L2 = 0; + break; + case DATA_BITS_9: + uart->uart_regs->ESCR_f.L0 = 0; + uart->uart_regs->ESCR_f.L1 = 0; + uart->uart_regs->ESCR_f.L2 = 1; + break; + default: + return RT_ERROR; + } + + /* set parity */ + switch (cfg->parity) + { + case PARITY_NONE: + uart->uart_regs->ESCR_f.PEN = 0; + break; + case PARITY_EVEN: + uart->uart_regs->ESCR_f.PEN = 1; + uart->uart_regs->ESCR_f.P = 0; + break; + case PARITY_ODD: + uart->uart_regs->ESCR_f.PEN = 1; + uart->uart_regs->ESCR_f.P = 1; + break; + default: + return RT_ERROR; + } + + /* set bit order */ + switch (cfg->bit_order) + { + case BIT_ORDER_LSB: + uart->uart_regs->SMR_f.BDS = 0; + break; + case BIT_ORDER_MSB: + uart->uart_regs->SMR_f.BDS = 1; + break; + default: + return RT_ERROR; + } + + /* set NRZ mode */ + switch (cfg->invert) + { + case NRZ_NORMAL: + uart->uart_regs->ESCR_f.INV = 0; + break; + case NRZ_INVERTED: + uart->uart_regs->ESCR_f.INV = 1; + break; + default: + return RT_ERROR; + } + + /* configure fifo */ + /* Disable the Data Lost detection */ + uart->uart_regs->FCR1_f.FLSTE = 0; + /* Enable the received FIFO idle detection */ + uart->uart_regs->FCR1_f.FRIE = 1; + /* Requests for the transmit FIFO data */ + uart->uart_regs->FCR1_f.FDRQ = 1; + /* Disable the transmit FIFO interrupt */ + uart->uart_regs->FCR1_f.FTIE = 0; + /* Transmit FIFO:FIFO1; Received FIFO:FIFO2 */ + uart->uart_regs->FCR1_f.FSEL = 0; + + /* Transfer data count */ + uart->uart_regs->FBYTE1 = 0; + /* Set the data count to generate a received interrupt */ + uart->uart_regs->FBYTE2 = uart->fifo_size; + + /* FIFO pointer Not reloaded */ + uart->uart_regs->FCR0_f.FLD = 0; + /* FIFO pointer Not saved */ + uart->uart_regs->FCR0_f.FSET = 0; + /* FIFO2 is reset */ + uart->uart_regs->FCR0_f.FCL2 = 1; + /* FIFO1 is reset */ + uart->uart_regs->FCR0_f.FCL1 = 1; + /* Enables the FIFO2 operation */ + uart->uart_regs->FCR0_f.FE2 = 1; + /* Enables the FIFO1 operation */ + uart->uart_regs->FCR0_f.FE1 = 1; + + /* enable receive and send */ + uart->uart_regs->SCR = SCR_RXE | SCR_TXE | SCR_RIE; + + return RT_EOK; } static rt_err_t uart47_control(struct rt_serial_device *serial, int cmd, void *arg) { - struct uart47_device *uart; - - RT_ASSERT(serial != RT_NULL); - uart = (struct uart47_device *)serial->parent.user_data; - - switch (cmd) - { - case RT_DEVICE_CTRL_CLR_INT: - /* disable rx irq */ - UART_DISABLE_IRQ(uart->rx_irq); - break; - case RT_DEVICE_CTRL_SET_INT: - /* enable rx irq */ - UART_ENABLE_IRQ(uart->rx_irq); - break; - } - - return (RT_EOK); + struct uart47_device *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct uart47_device *)serial->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + UART_DISABLE_IRQ(uart->rx_irq); + break; + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + UART_ENABLE_IRQ(uart->rx_irq); + break; + } + + return (RT_EOK); } static int uart47_putc(struct rt_serial_device *serial, char c) { - struct uart47_device *uart; + struct uart47_device *uart; + + RT_ASSERT(serial != RT_NULL); - RT_ASSERT(serial != RT_NULL); - - uart = (struct uart47_device *)serial->parent.user_data; + uart = (struct uart47_device *)serial->parent.user_data; - /* while send fifo is empty */ - while (!(uart->uart_regs->SSR & SSR_TDRE)); - /* write to fifo */ - uart->uart_regs->TDR = c; + /* while send fifo is empty */ + while (!(uart->uart_regs->SSR & SSR_TDRE)); + /* write to fifo */ + uart->uart_regs->TDR = c; - return (1); + return (1); } static int uart47_getc(struct rt_serial_device *serial) -{ - int ch; - struct uart47_device *uart; - - RT_ASSERT(serial != RT_NULL); - - uart = (struct uart47_device *)serial->parent.user_data; - - /* receive is disabled */ - if (!(uart->uart_regs->SCR & SCR_RXE)) - return (-1); +{ + int ch; + struct uart47_device *uart; + + RT_ASSERT(serial != RT_NULL); + + uart = (struct uart47_device *)serial->parent.user_data; + + /* receive is disabled */ + if (!(uart->uart_regs->SCR & SCR_RXE)) + return (-1); /* receive fifo is not full */ - if ((uart->uart_regs->SSR & SSR_RDRF) == 0) - return (-1); - /* read char */ - ch = uart->uart_regs->RDR & 0xff; - - return (ch); + if ((uart->uart_regs->SSR & SSR_RDRF) == 0) + return (-1); + /* read char */ + ch = uart->uart_regs->RDR & 0xff; + + return (ch); } static struct rt_uart_ops uart47_ops = { - uart47_configure, - uart47_control, - uart47_putc, - uart47_getc, + uart47_configure, + uart47_control, + uart47_putc, + uart47_getc, }; void rt_hw_serial_init(void) { - struct serial_configure config; + struct serial_configure config; - uart_pin_setup(); + uart_pin_setup(); #if (defined(RT_USING_UART0_0) || defined(RT_USING_UART0_1)) - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; - - serial0.ops = &uart03_ops; - serial0.config = config; - - /* register UART0 device */ - rt_hw_serial_register(&serial0, "uart0", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart0); + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; + + serial0.ops = &uart03_ops; + serial0.config = config; + + /* register UART0 device */ + rt_hw_serial_register(&serial0, "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart0); #endif #if (defined(RT_USING_UART1_0) || defined(RT_USING_UART1_1)) - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; - - serial1.ops = &uart03_ops; - serial1.config = config; - - /* register UART1 device */ - rt_hw_serial_register(&serial1, - "uart1", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart1); + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; + + serial1.ops = &uart03_ops; + serial1.config = config; + + /* register UART1 device */ + rt_hw_serial_register(&serial1, + "uart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart1); #endif #if (defined(RT_USING_UART2_0) || defined(RT_USING_UART2_1) || defined(RT_USING_UART2_2)) - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; - - serial2.ops = &uart03_ops; - serial2.config = config; - - /* register UART2 device */ - rt_hw_serial_register(&serial2, - "uart2", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart2); + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; + + serial2.ops = &uart03_ops; + serial2.config = config; + + /* register UART2 device */ + rt_hw_serial_register(&serial2, + "uart2", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart2); #endif #if (defined(RT_USING_UART3_0) || defined(RT_USING_UART3_1) || defined(RT_USING_UART3_2)) - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; - - serial3.ops = &uart03_ops; - serial3.config = config; - - /* register UART3 device */ - rt_hw_serial_register(&serial3, - "uart3", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart3); + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; + + serial3.ops = &uart03_ops; + serial3.config = config; + + /* register UART3 device */ + rt_hw_serial_register(&serial3, + "uart3", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart3); #endif #if (defined(RT_USING_UART4_0) || defined(RT_USING_UART4_1) || defined(RT_USING_UART4_2)) - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; - - serial4.ops = &uart47_ops; - serial4.config = config; - - /* register UART4 device */ - rt_hw_serial_register(&serial4, - "uart4", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart4); + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; + + serial4.ops = &uart47_ops; + serial4.config = config; + + /* register UART4 device */ + rt_hw_serial_register(&serial4, + "uart4", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart4); #endif #if (defined(RT_USING_UART5_0) || defined(RT_USING_UART5_1) || defined(RT_USING_UART5_2)) - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; - - serial5.ops = &uart47_ops; - serial5.config = config; - - /* register UART5 device */ - rt_hw_serial_register(&serial5, - "uart5", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart5); + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; + + serial5.ops = &uart47_ops; + serial5.config = config; + + /* register UART5 device */ + rt_hw_serial_register(&serial5, + "uart5", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart5); #endif #if (defined(RT_USING_UART6_0) || defined(RT_USING_UART6_1)) - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; - - serial6.ops = &uart47_ops; - serial6.config = config; - - /* register UART6 device */ - rt_hw_serial_register(&serial6, - "uart6", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart6); + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; + + serial6.ops = &uart47_ops; + serial6.config = config; + + /* register UART6 device */ + rt_hw_serial_register(&serial6, + "uart6", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart6); #endif #if (defined(RT_USING_UART7_0) || defined(RT_USING_UART7_1)) - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; - - serial7.ops = &uart47_ops; - serial7.config = config; - - /* register UART7 device */ - rt_hw_serial_register(&serial7, - "uart7", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart7); + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; + + serial7.ops = &uart47_ops; + serial7.config = config; + + /* register UART7 device */ + rt_hw_serial_register(&serial7, + "uart7", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart7); #endif } diff --git a/bsp/mb9bf506r/drivers/fm3_uart.h b/bsp/mb9bf506r/drivers/fm3_uart.h index 6cafb7b051..824592c850 100644 --- a/bsp/mb9bf506r/drivers/fm3_uart.h +++ b/bsp/mb9bf506r/drivers/fm3_uart.h @@ -51,7 +51,7 @@ #define ESCR_DATABITS_7 0x03U #define ESCR_DATABITS_9 0x04U -#define FIFO_SIZE 16 +#define FIFO_SIZE 16 /* * Enable/DISABLE Interrupt Controller @@ -62,19 +62,19 @@ struct uart03_device { - FM3_MFS03_UART_TypeDef *uart_regs; - /* irq number */ - IRQn_Type rx_irq; - IRQn_Type tx_irq; + FM3_MFS03_UART_TypeDef *uart_regs; + /* irq number */ + IRQn_Type rx_irq; + IRQn_Type tx_irq; }; struct uart47_device { - FM3_MFS47_UART_TypeDef *uart_regs; - /* irq number */ - IRQn_Type rx_irq; - IRQn_Type tx_irq; - rt_uint8_t fifo_size; + FM3_MFS47_UART_TypeDef *uart_regs; + /* irq number */ + IRQn_Type rx_irq; + IRQn_Type tx_irq; + rt_uint8_t fifo_size; }; void rt_hw_serial_init(void); diff --git a/bsp/mb9bf506r/drivers/led.c b/bsp/mb9bf506r/drivers/led.c index 25f04e3f93..3f6a11fcfe 100644 --- a/bsp/mb9bf506r/drivers/led.c +++ b/bsp/mb9bf506r/drivers/led.c @@ -7,7 +7,7 @@ * Date Author Notes * 2011-03-03 lgnq */ - + #include #include @@ -16,8 +16,8 @@ void rt_hw_led_on(rt_uint8_t num) { - RT_ASSERT(num < LEDS_MAX_NUMBER); - + RT_ASSERT(num < LEDS_MAX_NUMBER); + switch (num) { case 1: @@ -27,16 +27,16 @@ void rt_hw_led_on(rt_uint8_t num) USER_LED_PDOR &= ~USER_LED2; break; case 3: - USER_LED_PDOR &= ~USER_LED3; + USER_LED_PDOR &= ~USER_LED3; break; default: break; - } + } } void rt_hw_led_off(rt_uint8_t num) { - RT_ASSERT(num < LEDS_MAX_NUMBER); + RT_ASSERT(num < LEDS_MAX_NUMBER); switch (num) { @@ -47,17 +47,17 @@ void rt_hw_led_off(rt_uint8_t num) USER_LED_PDOR |= USER_LED2; break; case 3: - USER_LED_PDOR |= USER_LED3; + USER_LED_PDOR |= USER_LED3; break; default: break; - } + } } void rt_hw_led_toggle(rt_uint8_t num) { - RT_ASSERT(num < LEDS_MAX_NUMBER); - + RT_ASSERT(num < LEDS_MAX_NUMBER); + switch (num) { case 1: @@ -76,11 +76,11 @@ void rt_hw_led_toggle(rt_uint8_t num) if (USER_LED_PDOR&USER_LED3) USER_LED_PDOR &= ~USER_LED3; else - USER_LED_PDOR |= USER_LED3; + USER_LED_PDOR |= USER_LED3; break; default: break; - } + } } void led_init(void) @@ -98,7 +98,7 @@ void led_init(void) void pwm_update(rt_uint16_t value) { - FM3_BT2_PWM->PDUT = value; + FM3_BT2_PWM->PDUT = value; } static void led1_thread_entry(void *parameter) @@ -126,11 +126,11 @@ void rt_hw_led_init(void) led_init(); led1_thread = rt_thread_create("led1", led1_thread_entry, RT_NULL, 384, 29, 5); - if (led1_thread != RT_NULL) + if (led1_thread != RT_NULL) rt_thread_startup(led1_thread); - + led2_thread = rt_thread_create("led2", led2_thread_entry, RT_NULL, 384, 30, 5); - if (led2_thread != RT_NULL) + if (led2_thread != RT_NULL) rt_thread_startup(led2_thread); } diff --git a/bsp/mb9bf506r/drivers/led.h b/bsp/mb9bf506r/drivers/led.h index c7a07a553f..bcbfaf9b62 100644 --- a/bsp/mb9bf506r/drivers/led.h +++ b/bsp/mb9bf506r/drivers/led.h @@ -7,28 +7,28 @@ * Date Author Notes * 2011-03-03 lgnq */ - + #ifndef __LED_H__ #define __LED_H__ #include "mb9bf506r.h" -#define LEDS_MAX_NUMBER 4 +#define LEDS_MAX_NUMBER 4 /* LED */ #define USER_LED1 (1UL<<0x9) #define USER_LED2 (1UL<<0xa) #define USER_LED3 (1UL<<0xb) -#define USER_LED_MASK (USER_LED1 | USER_LED2 | USER_LED3) -#define USER_LED_PFR FM3_GPIO->PFR1 -#define USER_LED_PCR FM3_GPIO->PCR1 -#define USER_LED_PDOR FM3_GPIO->PDOR1 -#define USER_LED_DDR FM3_GPIO->DDR1 +#define USER_LED_MASK (USER_LED1 | USER_LED2 | USER_LED3) +#define USER_LED_PFR FM3_GPIO->PFR1 +#define USER_LED_PCR FM3_GPIO->PCR1 +#define USER_LED_PDOR FM3_GPIO->PDOR1 +#define USER_LED_DDR FM3_GPIO->DDR1 -#define RT_DEVICE_CTRL_LED_ON 0 -#define RT_DEVICE_CTRL_LED_OFF 1 -#define RT_DEVICE_CTRL_LED_TOGGLE 2 +#define RT_DEVICE_CTRL_LED_ON 0 +#define RT_DEVICE_CTRL_LED_OFF 1 +#define RT_DEVICE_CTRL_LED_TOGGLE 2 void rt_hw_led_init(void); void rt_hw_led_on(rt_uint8_t num); diff --git a/bsp/mb9bf506r/drivers/nand.c b/bsp/mb9bf506r/drivers/nand.c index e0cfc17995..fcd8cf42d4 100644 --- a/bsp/mb9bf506r/drivers/nand.c +++ b/bsp/mb9bf506r/drivers/nand.c @@ -12,17 +12,17 @@ #include "mb9bf506r.h" /* - * NandFlash driver for SamSung K9F5608 + * NandFlash driver for SamSung K9F5608 * 32M x 8bit */ -#define PAGE_SIZE 512 -#define PAGE_PER_BLOCK 32 -#define BLOCK_NUM 2048 +#define PAGE_SIZE 512 +#define PAGE_PER_BLOCK 32 +#define BLOCK_NUM 2048 /* device driver debug trace */ /* #define NAND_DEBUG */ #ifdef NAND_DEBUG -#define trace_log rt_kprintf +#define trace_log rt_kprintf #else #define trace_log(...) #endif @@ -34,14 +34,14 @@ */ struct rt_device_nand { - struct rt_device parent; /* which is inherited from rt_device */ + struct rt_device parent; /* which is inherited from rt_device */ - rt_uint16_t block_num; /* total block number in device */ - rt_uint16_t page_per_block; /* pages in one block */ - rt_uint16_t page_size; /* page size */ + rt_uint16_t block_num; /* total block number in device */ + rt_uint16_t page_per_block; /* pages in one block */ + rt_uint16_t page_size; /* page size */ - /* this buffer which used as to save data before erase block */ - rt_uint8_t block_buffer[PAGE_SIZE * PAGE_PER_BLOCK]; + /* this buffer which used as to save data before erase block */ + rt_uint8_t block_buffer[PAGE_SIZE * PAGE_PER_BLOCK]; }; static struct rt_device_nand _nand; @@ -56,8 +56,8 @@ static struct rt_device_nand _nand; #define NF_OE_H() {IO_NF_PDOR |= NF_EN;} #define NF_OE_L() {IO_NF_PDOR &= ~NF_EN;} -#define NF_DATA_OUT() {IO_NF_PDOR &= ~NF_DATA_DIR;} -#define NF_DATA_IN() {IO_NF_PDOR |= NF_DATA_DIR;} +#define NF_DATA_OUT() {IO_NF_PDOR &= ~NF_DATA_DIR;} +#define NF_DATA_IN() {IO_NF_PDOR |= NF_DATA_DIR;} static unsigned char NF_ReadStatus(void); static void Wait(unsigned int cnt); @@ -103,11 +103,11 @@ static unsigned char NF_ReadStatus(void) */ static void NF_Init(void) { - FM3_GPIO->PFR5 |= (0x7ff); /* D0-D5, CS7, ALE, CLE, WEX, REX */ - FM3_GPIO->PFR3 |= (0x3); /* D6-D7 */ - FM3_GPIO->EPFR10 |= (1<<13 /* CS enable */ - |1<<6 /* ALE, CLE, WEX, REX enable */ - |1<<0); /* D0-D7 enable */ + FM3_GPIO->PFR5 |= (0x7ff); /* D0-D5, CS7, ALE, CLE, WEX, REX */ + FM3_GPIO->PFR3 |= (0x3); /* D6-D7 */ + FM3_GPIO->EPFR10 |= (1<<13 /* CS enable */ + |1<<6 /* ALE, CLE, WEX, REX enable */ + |1<<0); /* D0-D7 enable */ FM3_EXBUS->AREA7 = 0x001f00e0; /* Select CS7 area, 32Mbyte size */ FM3_EXBUS->MODE7 |= (1<<4); /* Nand Flash mode turn on, set 8 bit width */ @@ -121,9 +121,9 @@ static void NF_Init(void) static void NF_UnInit(void) { - FM3_GPIO->PFR5 &= ~(0x7ff); /* disable D0-D5, CS7, ALE, CLE, WEX, REX */ - FM3_GPIO->PFR3 &= ~(0x3); /* disable D6-D7 */ - FM3_GPIO->EPFR10 &= ~(1<<13 /* disable CS enable */ + FM3_GPIO->PFR5 &= ~(0x7ff); /* disable D0-D5, CS7, ALE, CLE, WEX, REX */ + FM3_GPIO->PFR3 &= ~(0x3); /* disable D6-D7 */ + FM3_GPIO->EPFR10 &= ~(1<<13 /* disable CS enable */ |1<<6 /* disable ALE, CLE, WEX, REX enable */ |1<<0); /* disable D0-D7 enable */ FM3_EXBUS->MODE7 &= ~(1<<4); @@ -140,52 +140,52 @@ static void NF_UnInit(void) * Return: 0: Flash Operation OK * 1: Flash Operation NG */ -int NF_ReadPage(unsigned int block, unsigned int page, unsigned char *buffer, +int NF_ReadPage(unsigned int block, unsigned int page, unsigned char *buffer, unsigned char *oob) { unsigned int blockPage,i; NF_Init(); - blockPage=(block<<5)+page; /* 1 block=32 page */ + blockPage=(block<<5)+page; /* 1 block=32 page */ NF_OE_L(); NF_DATA_OUT(); - if (buffer != RT_NULL) - { - volatile unsigned char ch; - - NF_CMD(NAND_CMD_READ0); /* send read data */ - - NF_ADDR(0); - NF_ADDR(blockPage & 0xff); - NF_ADDR((blockPage>>8) & 0xff); /* send 3 byte address */ - NF_CLR_ALE(); - NF_DATA_IN(); - - Wait(500); - - for(i=0;i<512;i++) /* read 512 bytes data */ - buffer[i] = NF_RDDATA(); - for(i=0;i<16;i++) /* read 16 bytes oob */ - if (oob != RT_NULL) - oob[i] = NF_RDDATA(); - else - ch = NF_RDDATA(); - } - else - { - NF_CMD(NAND_CMD_READOOB); /* send read data */ - - NF_ADDR(0); - NF_ADDR(blockPage & 0xff); - NF_ADDR((blockPage>>8) & 0xff); /* send 3 byte address */ - NF_CLR_ALE(); - NF_DATA_IN(); - - Wait(500); - - for (i=0; i<16; i++) /* read 16 bytes oob */ - oob[i] = NF_RDDATA(); - } + if (buffer != RT_NULL) + { + volatile unsigned char ch; + + NF_CMD(NAND_CMD_READ0); /* send read data */ + + NF_ADDR(0); + NF_ADDR(blockPage & 0xff); + NF_ADDR((blockPage>>8) & 0xff); /* send 3 byte address */ + NF_CLR_ALE(); + NF_DATA_IN(); + + Wait(500); + + for(i=0;i<512;i++) /* read 512 bytes data */ + buffer[i] = NF_RDDATA(); + for(i=0;i<16;i++) /* read 16 bytes oob */ + if (oob != RT_NULL) + oob[i] = NF_RDDATA(); + else + ch = NF_RDDATA(); + } + else + { + NF_CMD(NAND_CMD_READOOB); /* send read data */ + + NF_ADDR(0); + NF_ADDR(blockPage & 0xff); + NF_ADDR((blockPage>>8) & 0xff); /* send 3 byte address */ + NF_CLR_ALE(); + NF_DATA_IN(); + + Wait(500); + + for (i=0; i<16; i++) /* read 16 bytes oob */ + oob[i] = NF_RDDATA(); + } NF_OE_H(); NF_UnInit(); @@ -202,7 +202,7 @@ int NF_EraseBlock(unsigned int block) { rt_uint32_t blockPage; - trace_log("Erase block %d: ", block); + trace_log("Erase block %d: ", block); NF_Init(); blockPage = (block << 5); @@ -215,19 +215,19 @@ int NF_EraseBlock(unsigned int block) if(NF_ReadStatus()) { - NF_Reset(); - NF_OE_H(); - NF_UnInit(); - trace_log("Failed\n"); - rt_kprintf("erase block failed\n"); + NF_Reset(); + NF_OE_H(); + NF_UnInit(); + trace_log("Failed\n"); + rt_kprintf("erase block failed\n"); - return FLASH_NG; + return FLASH_NG; } NF_OE_H(); NF_UnInit(); - trace_log("OK\n"); + trace_log("OK\n"); return FLASH_OK; } @@ -257,24 +257,24 @@ int NF_WritePage(unsigned block, unsigned page, const rt_uint8_t *buffer) NF_ADDR((blockPage>>8) & 0xff); NF_CLR_ALE(); - for(i=0;i<512;i++) NF_WRDATA(buffer[i]); /* write data */ - for(i=0;i<16;i++) NF_WRDATA(se[i]); /* dummy write */ + for(i=0;i<512;i++) NF_WRDATA(buffer[i]); /* write data */ + for(i=0;i<16;i++) NF_WRDATA(se[i]); /* dummy write */ - NF_CMD(NAND_CMD_PAGEPROG); /* start programming */ + NF_CMD(NAND_CMD_PAGEPROG); /* start programming */ if(NF_ReadStatus()) { - NF_Reset(); - NF_OE_H(); - NF_UnInit(); - - trace_log("write failed\n"); - return FLASH_NG; + NF_Reset(); + NF_OE_H(); + NF_UnInit(); + + trace_log("write failed\n"); + return FLASH_NG; } /* verify the write data */ NF_DATA_OUT(); - NF_CMD(NAND_CMD_READ0); /* send read command */ + NF_CMD(NAND_CMD_READ0); /* send read command */ NF_ADDR(0); NF_ADDR(blockPage & 0xff); NF_ADDR((blockPage>>8) & 0xff); @@ -284,11 +284,11 @@ int NF_WritePage(unsigned block, unsigned page, const rt_uint8_t *buffer) Wait(500); for(i=0; i<512; i++) { - data=NF_RDDATA(); /* verify 1-512 byte */ + data=NF_RDDATA(); /* verify 1-512 byte */ if(data != buffer[i]) { - trace_log("block %d, page %d\n", block , page); - trace_log("write data failed[%d]: %02x %02x\n", i, data, buffer[i]); + trace_log("block %d, page %d\n", block , page); + trace_log("write data failed[%d]: %02x %02x\n", i, data, buffer[i]); NF_Reset(); NF_OE_H(); @@ -299,11 +299,11 @@ int NF_WritePage(unsigned block, unsigned page, const rt_uint8_t *buffer) for(i=0; i<16; i++) { - data=NF_RDDATA(); /* verify 16 byte dummy data */ + data=NF_RDDATA(); /* verify 16 byte dummy data */ if(data != se[i]) { - trace_log("block %d, page %d\n", block , page); - trace_log("write oob failed[%d]: %02x %02x\n", i, data, se[i]); + trace_log("block %d, page %d\n", block , page); + trace_log("write oob failed[%d]: %02x %02x\n", i, data, se[i]); NF_Reset(); NF_OE_H(); NF_UnInit(); @@ -323,7 +323,7 @@ int NF_WritePage(unsigned block, unsigned page, const rt_uint8_t *buffer) */ void NF_ReadID(unsigned char *id) { - unsigned char maker_code; + unsigned char maker_code; NF_Init(); NF_OE_L(); NF_DATA_OUT(); @@ -333,7 +333,7 @@ void NF_ReadID(unsigned char *id) Wait(10); NF_DATA_IN(); maker_code = NF_RDDATA(); - maker_code = maker_code; + maker_code = maker_code; *id = NF_RDDATA(); NF_OE_H(); NF_UnInit(); @@ -341,58 +341,58 @@ void NF_ReadID(unsigned char *id) static rt_err_t rt_nand_init (rt_device_t dev) { - /* empty implementation */ - return RT_EOK; + /* empty implementation */ + return RT_EOK; } static rt_err_t rt_nand_open(rt_device_t dev, rt_uint16_t oflag) { - /* empty implementation */ - return RT_EOK; + /* empty implementation */ + return RT_EOK; } static rt_err_t rt_nand_close(rt_device_t dev) { - /* empty implementation */ - return RT_EOK; + /* empty implementation */ + return RT_EOK; } /* nand device read */ -static rt_size_t rt_nand_read (rt_device_t dev, rt_off_t pos, void* buffer, +static rt_size_t rt_nand_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_ubase_t block; /* block of position */ - rt_ubase_t page, index; /* page in block of position */ - rt_uint8_t *page_ptr, oob[16]; - struct rt_device_nand *nand; - - /* get nand device */ - nand = (struct rt_device_nand*) dev; - RT_ASSERT(nand != RT_NULL); - - /* get block and page */ - block = pos / nand->page_per_block; - page = pos % nand->page_per_block; - - trace_log("nand read: position %d, block %d, page %d, size %d\n", - pos, block, page, size); - - /* set page buffer pointer */ - page_ptr = (rt_uint8_t*) buffer; - for (index = 0; index < size; index ++) - { - NF_ReadPage(block, page + index, page_ptr, oob); - page_ptr += nand->page_size; - - if (page + index > nand->page_per_block) - { - block += 1; - page = 0; - } - } - - /* return read size (count of block) */ - return size; + rt_ubase_t block; /* block of position */ + rt_ubase_t page, index; /* page in block of position */ + rt_uint8_t *page_ptr, oob[16]; + struct rt_device_nand *nand; + + /* get nand device */ + nand = (struct rt_device_nand*) dev; + RT_ASSERT(nand != RT_NULL); + + /* get block and page */ + block = pos / nand->page_per_block; + page = pos % nand->page_per_block; + + trace_log("nand read: position %d, block %d, page %d, size %d\n", + pos, block, page, size); + + /* set page buffer pointer */ + page_ptr = (rt_uint8_t*) buffer; + for (index = 0; index < size; index ++) + { + NF_ReadPage(block, page + index, page_ptr, oob); + page_ptr += nand->page_size; + + if (page + index > nand->page_per_block) + { + block += 1; + page = 0; + } + } + + /* return read size (count of block) */ + return size; } /* @@ -403,190 +403,190 @@ static rt_size_t rt_nand_read (rt_device_t dev, rt_off_t pos, void* buffer, * @param buffer the data buffer to be written * @param pages the number of pages to be written */ -static int rt_nand_eraseblock_writepage(struct rt_device_nand* nand, - rt_ubase_t block, rt_ubase_t page, - const rt_uint8_t *buffer, rt_ubase_t pages) +static int rt_nand_eraseblock_writepage(struct rt_device_nand* nand, + rt_ubase_t block, rt_ubase_t page, + const rt_uint8_t *buffer, rt_ubase_t pages) { - rt_ubase_t index; - rt_uint32_t page_status; - rt_uint8_t *page_ptr, oob[16]; - - /* set page status */ - page_status = 0; - - /* read each page in block */ - page_ptr = nand->block_buffer; - for (index = 0; index < nand->page_per_block; index ++) - { - NF_ReadPage(block, index, page_ptr, oob); - if (!oob[0]) - page_status |= (1 << index); - page_ptr += nand->page_size; - } - - /* erase block */ - NF_EraseBlock(block); - - page_ptr = &(nand->block_buffer[page * nand->page_size]); - /* merge buffer to page buffer */ - for (index = 0; index < pages; index ++) - { - rt_memcpy(page_ptr, buffer, nand->page_size); - - /* set page status */ - page_status |= (1 << (page + index)); - - /* move to next page */ - page_ptr += nand->page_size; - buffer += nand->page_size; - } - - /* write to flash */ - page_ptr = nand->block_buffer; - for (index = 0; index < nand->page_per_block; index ++) - { - if (page_status & (1 << index)) - NF_WritePage(block, index, page_ptr); - - /* move to next page */ - page_ptr += nand->page_size; - } - - return 0; + rt_ubase_t index; + rt_uint32_t page_status; + rt_uint8_t *page_ptr, oob[16]; + + /* set page status */ + page_status = 0; + + /* read each page in block */ + page_ptr = nand->block_buffer; + for (index = 0; index < nand->page_per_block; index ++) + { + NF_ReadPage(block, index, page_ptr, oob); + if (!oob[0]) + page_status |= (1 << index); + page_ptr += nand->page_size; + } + + /* erase block */ + NF_EraseBlock(block); + + page_ptr = &(nand->block_buffer[page * nand->page_size]); + /* merge buffer to page buffer */ + for (index = 0; index < pages; index ++) + { + rt_memcpy(page_ptr, buffer, nand->page_size); + + /* set page status */ + page_status |= (1 << (page + index)); + + /* move to next page */ + page_ptr += nand->page_size; + buffer += nand->page_size; + } + + /* write to flash */ + page_ptr = nand->block_buffer; + for (index = 0; index < nand->page_per_block; index ++) + { + if (page_status & (1 << index)) + NF_WritePage(block, index, page_ptr); + + /* move to next page */ + page_ptr += nand->page_size; + } + + return 0; } /* nand device write */ -static rt_size_t rt_nand_write (rt_device_t dev, rt_off_t pos, +static rt_size_t rt_nand_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_ubase_t block, page; - rt_uint8_t oob[16]; - struct rt_device_nand *nand; - - nand = (struct rt_device_nand*) dev; - RT_ASSERT(nand != RT_NULL); - - /* get block and page */ - block = pos / nand->page_per_block; - page = pos % nand->page_per_block; - - trace_log("nand write: position %d, block %d, page %d, size %d\n", - pos, block, page, size); - - if (size == 1) - { - /* write one page */ - - /* read oob to get page status */ - NF_ReadPage(block, page, RT_NULL, oob); - if (oob[0]) - NF_WritePage(block, page, buffer); - else - /* erase block and then write page */ - rt_nand_eraseblock_writepage(nand, block, page, buffer, 1); - } - else if (size > 1) - { - rt_ubase_t index; - rt_ubase_t need_erase_block; - const rt_uint8_t *page_ptr; - rt_ubase_t chunk_pages, pages; - - pages = size; - page_ptr = (const rt_uint8_t*) buffer; - do - { - need_erase_block = 0; - /* calculate pages in current chunk */ - if (pages > nand->page_per_block - page) - chunk_pages = nand->page_per_block - page; - else - chunk_pages = pages; - - /* get page status in current block */ - for (index = page; index < page + chunk_pages; index ++) - { - NF_ReadPage(block, index, RT_NULL, oob); - if (!oob[0]) - { - /* this page has data, need erase this block firstly */ - need_erase_block = 1; - break; - } - } - - if (need_erase_block) - { - /* erase block and then write it */ - rt_nand_eraseblock_writepage(nand, block, page, page_ptr, chunk_pages); - page_ptr += chunk_pages * nand->page_size; - } - else - { - /* write pages directly */ - for (index = page; index < page + chunk_pages; index ++) - { - NF_WritePage(block, index, page_ptr); - page_ptr += nand->page_size; - } - } - - pages -= chunk_pages; - page = 0; block ++; /* move to next block */ - } - while (pages); - } - - return size; + rt_ubase_t block, page; + rt_uint8_t oob[16]; + struct rt_device_nand *nand; + + nand = (struct rt_device_nand*) dev; + RT_ASSERT(nand != RT_NULL); + + /* get block and page */ + block = pos / nand->page_per_block; + page = pos % nand->page_per_block; + + trace_log("nand write: position %d, block %d, page %d, size %d\n", + pos, block, page, size); + + if (size == 1) + { + /* write one page */ + + /* read oob to get page status */ + NF_ReadPage(block, page, RT_NULL, oob); + if (oob[0]) + NF_WritePage(block, page, buffer); + else + /* erase block and then write page */ + rt_nand_eraseblock_writepage(nand, block, page, buffer, 1); + } + else if (size > 1) + { + rt_ubase_t index; + rt_ubase_t need_erase_block; + const rt_uint8_t *page_ptr; + rt_ubase_t chunk_pages, pages; + + pages = size; + page_ptr = (const rt_uint8_t*) buffer; + do + { + need_erase_block = 0; + /* calculate pages in current chunk */ + if (pages > nand->page_per_block - page) + chunk_pages = nand->page_per_block - page; + else + chunk_pages = pages; + + /* get page status in current block */ + for (index = page; index < page + chunk_pages; index ++) + { + NF_ReadPage(block, index, RT_NULL, oob); + if (!oob[0]) + { + /* this page has data, need erase this block firstly */ + need_erase_block = 1; + break; + } + } + + if (need_erase_block) + { + /* erase block and then write it */ + rt_nand_eraseblock_writepage(nand, block, page, page_ptr, chunk_pages); + page_ptr += chunk_pages * nand->page_size; + } + else + { + /* write pages directly */ + for (index = page; index < page + chunk_pages; index ++) + { + NF_WritePage(block, index, page_ptr); + page_ptr += nand->page_size; + } + } + + pages -= chunk_pages; + page = 0; block ++; /* move to next block */ + } + while (pages); + } + + return size; } static rt_err_t rt_nand_control (rt_device_t dev, int cmd, void *args) { - struct rt_device_nand *nand; + struct rt_device_nand *nand; - nand = (struct rt_device_nand*) dev; + nand = (struct rt_device_nand*) dev; RT_ASSERT(dev != RT_NULL); switch (cmd) - { - case RT_DEVICE_CTRL_BLK_GETGEOME: - { - struct rt_device_blk_geometry *geometry; - - geometry = (struct rt_device_blk_geometry *)args; - if (geometry == RT_NULL) return -RT_ERROR; - - geometry->bytes_per_sector = nand->page_size; - geometry->block_size = nand->page_size * nand->page_per_block; - geometry->sector_count = nand->block_num * nand->page_per_block; - } - break; - } - - return RT_EOK; + { + case RT_DEVICE_CTRL_BLK_GETGEOME: + { + struct rt_device_blk_geometry *geometry; + + geometry = (struct rt_device_blk_geometry *)args; + if (geometry == RT_NULL) return -RT_ERROR; + + geometry->bytes_per_sector = nand->page_size; + geometry->block_size = nand->page_size * nand->page_per_block; + geometry->sector_count = nand->block_num * nand->page_per_block; + } + break; + } + + return RT_EOK; } void rt_hw_nand_init(void) { - /* initialize nand flash structure */ - _nand.block_num = BLOCK_NUM; - _nand.page_per_block = PAGE_PER_BLOCK; - _nand.page_size = PAGE_SIZE; - - rt_memset(_nand.block_buffer, 0, sizeof(_nand.block_buffer)); - - _nand.parent.type = RT_Device_Class_MTD; - _nand.parent.rx_indicate = RT_NULL; - _nand.parent.tx_complete = RT_NULL; - _nand.parent.init = rt_nand_init; - _nand.parent.open = rt_nand_open; - _nand.parent.close = rt_nand_close; - _nand.parent.read = rt_nand_read; - _nand.parent.write = rt_nand_write; - _nand.parent.control = rt_nand_control; - - /* register a MTD device */ - rt_device_register(&(_nand.parent), "nand", RT_DEVICE_FLAG_RDWR); + /* initialize nand flash structure */ + _nand.block_num = BLOCK_NUM; + _nand.page_per_block = PAGE_PER_BLOCK; + _nand.page_size = PAGE_SIZE; + + rt_memset(_nand.block_buffer, 0, sizeof(_nand.block_buffer)); + + _nand.parent.type = RT_Device_Class_MTD; + _nand.parent.rx_indicate = RT_NULL; + _nand.parent.tx_complete = RT_NULL; + _nand.parent.init = rt_nand_init; + _nand.parent.open = rt_nand_open; + _nand.parent.close = rt_nand_close; + _nand.parent.read = rt_nand_read; + _nand.parent.write = rt_nand_write; + _nand.parent.control = rt_nand_control; + + /* register a MTD device */ + rt_device_register(&(_nand.parent), "nand", RT_DEVICE_FLAG_RDWR); } #ifdef NAND_DEBUG @@ -596,68 +596,68 @@ unsigned char nand_oob[16]; void dump_mem(unsigned char* buffer, int length) { - int i; - - if (length > 64) length = 64; - for (i = 0; i < length; i ++) - { - rt_kprintf("%02x ", *buffer++); - if (((i+1) % 16) == 0) - rt_kprintf("\n"); - } - rt_kprintf("\n"); + int i; + + if (length > 64) length = 64; + for (i = 0; i < length; i ++) + { + rt_kprintf("%02x ", *buffer++); + if (((i+1) % 16) == 0) + rt_kprintf("\n"); + } + rt_kprintf("\n"); } void nand_read(int block, int page) { - rt_kprintf("read block %d, page %d\n", block, page); + rt_kprintf("read block %d, page %d\n", block, page); - NF_ReadPage(block, page, nand_buffer, nand_oob); - rt_kprintf("page data:\n"); - dump_mem(nand_buffer, 512); - rt_kprintf("oob data:\n"); - dump_mem(nand_oob, 16); + NF_ReadPage(block, page, nand_buffer, nand_oob); + rt_kprintf("page data:\n"); + dump_mem(nand_buffer, 512); + rt_kprintf("oob data:\n"); + dump_mem(nand_oob, 16); } FINSH_FUNCTION_EXPORT_ALIAS(nand_read, read_page, read page[block/page]); void nand_write(int block, int page) { - int i; - for (i = 0; i < 512; i ++) - nand_buffer[i] = i; + int i; + for (i = 0; i < 512; i ++) + nand_buffer[i] = i; - NF_WritePage(block, page, nand_buffer); + NF_WritePage(block, page, nand_buffer); } FINSH_FUNCTION_EXPORT_ALIAS(nand_write, write_page, write page[block/page]); void nand_erase(int block) { - NF_EraseBlock(block); + NF_EraseBlock(block); } FINSH_FUNCTION_EXPORT_ALIAS(nand_erase, erase_block, erase block[block]); void nand_readoob(int block, int page) { - rt_kprintf("read oob on block %d, page %d\n", block, page); + rt_kprintf("read oob on block %d, page %d\n", block, page); - NF_ReadPage(block, page, RT_NULL, (unsigned char*)nand_oob); - rt_kprintf("oob data:\n"); - dump_mem(nand_oob, 16); + NF_ReadPage(block, page, RT_NULL, (unsigned char*)nand_oob); + rt_kprintf("oob data:\n"); + dump_mem(nand_oob, 16); } FINSH_FUNCTION_EXPORT_ALIAS(nand_readoob, readoob, read oob[block/page]); void nand_erase_chip() { - int i; - unsigned char id; - - NF_ReadID(&id); - rt_kprintf("id: %02x\n", id); - - for (i = 0; i < 2048; i ++) - { - NF_EraseBlock(i); - } + int i; + unsigned char id; + + NF_ReadID(&id); + rt_kprintf("id: %02x\n", id); + + for (i = 0; i < 2048; i ++) + { + NF_EraseBlock(i); + } } FINSH_FUNCTION_EXPORT_ALIAS(nand_erase_chip, erase_chip, erase whole chip); #endif diff --git a/bsp/mb9bf506r/drivers/nand.h b/bsp/mb9bf506r/drivers/nand.h index 8a5ab79a0d..d00909ddce 100644 --- a/bsp/mb9bf506r/drivers/nand.h +++ b/bsp/mb9bf506r/drivers/nand.h @@ -29,7 +29,7 @@ #define NF_ALE_OFFSET 0x00003000 #define NF_ADDR_OFFSET 0x00002000 #define NF_CMD_OFFSET 0x00001000 -#define NF_DATA_OFFSET 0x00000000 +#define NF_DATA_OFFSET 0x00000000 /* NAND command */ #define NAND_CMD_READ0 0x00 @@ -43,7 +43,7 @@ #define NAND_CMD_READID1 0x91 #define NAND_CMD_ERASE2 0xd0 #define NAND_CMD_RESET 0xff - + #define FLASH_OK 0 #define FLASH_NG 1 diff --git a/bsp/mb9bf506r/rtconfig.h b/bsp/mb9bf506r/rtconfig.h index b7b675ab20..3109845755 100644 --- a/bsp/mb9bf506r/rtconfig.h +++ b/bsp/mb9bf506r/rtconfig.h @@ -5,17 +5,17 @@ // // -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 // -#define RT_ALIGN_SIZE 8 +#define RT_ALIGN_SIZE 8 // // 8 // 32 // 256 // -#define RT_THREAD_PRIORITY_MAX 32 +#define RT_THREAD_PRIORITY_MAX 32 // -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 //
// #define RT_DEBUG // @@ -29,11 +29,11 @@ //
// #define RT_USING_TIMER_SOFT // -#define RT_TIMER_THREAD_PRIO 8 +#define RT_TIMER_THREAD_PRIO 8 // -#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_THREAD_STACK_SIZE 512 // -#define RT_TIMER_TICK_PER_SECOND 10 +#define RT_TIMER_TICK_PER_SECOND 10 //
//
@@ -110,15 +110,15 @@ // // #define RT_USING_UART7_1 // -#define RT_UART_RX_BUFFER_SIZE 64 +#define RT_UART_RX_BUFFER_SIZE 64 //
//
#define RT_USING_CONSOLE // -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 // -#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_CONSOLE_DEVICE_NAME "uart0" //
// @@ -130,7 +130,7 @@ // #define FINSH_USING_DESCRIPTION // -#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_THREAD_STACK_SIZE 4096 //
//
@@ -145,18 +145,18 @@ // // #define DFS_USING_WORKDIR // -#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEMS_MAX 2 // -#define DFS_FD_MAX 4 +#define DFS_FD_MAX 4 // #define RT_USING_DFS_ELMFAT // // 1 // 2 // -#define RT_DFS_ELM_USE_LFN 1 +#define RT_DFS_ELM_USE_LFN 1 // -#define RT_DFS_ELM_MAX_LFN 64 +#define RT_DFS_ELM_MAX_LFN 64 // // #define RT_USING_DFS_YAFFS2 // @@ -166,7 +166,7 @@ // // #define RT_USING_DFS_NFS // -#define RT_NFS_HOST_EXPORT "192.168.1.5:/" +#define RT_NFS_HOST_EXPORT "192.168.1.5:/" //
// diff --git a/bsp/mb9bf568r/applications/application.c b/bsp/mb9bf568r/applications/application.c index 64fb44f10b..17a6707814 100644 --- a/bsp/mb9bf568r/applications/application.c +++ b/bsp/mb9bf568r/applications/application.c @@ -24,7 +24,7 @@ void rt_init_thread_entry(void *parameter) #endif - //finsh_system_init(); + //finsh_system_init(); finsh_set_device(RT_CONSOLE_DEVICE_NAME); @@ -33,7 +33,7 @@ void rt_init_thread_entry(void *parameter) extern void rt_led_hw_init(void); rt_led_hw_init(); } - { + { extern int demo_init(void); demo_init(); } diff --git a/bsp/mb9bf568r/applications/startup.c b/bsp/mb9bf568r/applications/startup.c index 41055cf8a1..263bd20a28 100644 --- a/bsp/mb9bf568r/applications/startup.c +++ b/bsp/mb9bf568r/applications/startup.c @@ -39,7 +39,7 @@ void rtthread_startup(void) /* show version */ rt_show_version(); - + /* init timer system */ rt_system_timer_init(); diff --git a/bsp/mb9bf568r/drivers/board.c b/bsp/mb9bf568r/drivers/board.c index 1b2cf35e62..bd44ad80b1 100644 --- a/bsp/mb9bf568r/drivers/board.c +++ b/bsp/mb9bf568r/drivers/board.c @@ -60,7 +60,7 @@ rt_uint32_t rt_hw_tick_get_microsecond(void) rt_tick_t tick; rt_uint32_t value; -#define TICK_US (1000000/RT_TICK_PER_SECOND) +#define TICK_US (1000000/RT_TICK_PER_SECOND) tick = rt_tick_get(); value = tick * TICK_US + (SysTick->LOAD - SysTick->VAL) * TICK_US / SysTick->LOAD; diff --git a/bsp/mb9bf568r/drivers/serial.c b/bsp/mb9bf568r/drivers/serial.c index 5e12b3c22f..6c3a132216 100644 --- a/bsp/mb9bf568r/drivers/serial.c +++ b/bsp/mb9bf568r/drivers/serial.c @@ -254,16 +254,16 @@ rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, { RT_ASSERT(device != RT_NULL); - device->type = RT_Device_Class_Char; + device->type = RT_Device_Class_Char; device->rx_indicate = RT_NULL; device->tx_complete = RT_NULL; - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; - device->user_data = serial; + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; + device->user_data = serial; /* register a character device */ return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); @@ -299,7 +299,7 @@ void rt_hw_serial_isr(rt_device_t device) #ifdef RT_USING_UART0 /* UART0 device driver structure */ -#define UART0 FM4_MFS0 +#define UART0 FM4_MFS0 struct serial_int_rx uart0_int_rx; struct serial_device uart0 = { @@ -312,8 +312,8 @@ struct serial_device uart0 = struct rt_device uart0_device; void MFS0_RX_IRQHandler(void) -{ - /* enter interrupt */ +{ + /* enter interrupt */ rt_interrupt_enter(); rt_hw_serial_isr(&uart0_device); /* leave interrupt */ @@ -326,28 +326,28 @@ void MFS0_RX_IRQHandler(void) void rt_hw_serial_init(void) { - uint32_t APB2_clock = (SystemCoreClock >> (APBC2_PSR_Val & 0x03)); - + uint32_t APB2_clock = (SystemCoreClock >> (APBC2_PSR_Val & 0x03)); + #ifdef RT_USING_UART0 // Initialize ports for MFS0 - FM4_GPIO->PFR2 = 0x06u; // P21>SIN0_0, P22>SOT0_0 - FM4_GPIO->EPFR07 &= 0xFFFFFF0Ful; - FM4_GPIO->EPFR07 |= 0x00000040ul; - - // Initialize MFS to UART asynchronous mode - - uart0.uart_device->SMR = SMR_MD_UART | SMR_SOE;; + FM4_GPIO->PFR2 = 0x06u; // P21>SIN0_0, P22>SOT0_0 + FM4_GPIO->EPFR07 &= 0xFFFFFF0Ful; + FM4_GPIO->EPFR07 |= 0x00000040ul; + + // Initialize MFS to UART asynchronous mode + + uart0.uart_device->SMR = SMR_MD_UART | SMR_SOE;; uart0.uart_device->BGR = (APB2_clock + (BPS/2))/BPS - 1; /* round */ uart0.uart_device->ESCR = ESCR_DATABITS_8; uart0.uart_device->SCR = SCR_RXE | SCR_TXE | SCR_RIE; - + /* register UART0 device */ rt_hw_serial_register(&uart0_device, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, &uart0); - - + + #endif /**< #ifdef RT_USING_UART0 */ } diff --git a/bsp/mb9bf568r/drivers/serial.h b/bsp/mb9bf568r/drivers/serial.h index 832a0ee5c5..776b2a3877 100644 --- a/bsp/mb9bf568r/drivers/serial.h +++ b/bsp/mb9bf568r/drivers/serial.h @@ -6,7 +6,7 @@ * Change Logs: * Date Author Notes * 2006-03-13 Bernard first version - * 2011-05-15 lgnq modified according bernard's implementaion. + * 2011-05-15 lgnq modified according bernard's implementaion. */ #ifndef __RT_HW_SERIAL_H__ @@ -53,21 +53,21 @@ #define ESCR_DATABITS_7 0x03U #define ESCR_DATABITS_9 0x04U -#define BPS 115200 /* serial baudrate */ +#define BPS 115200 /* serial baudrate */ -#define UART_RX_BUFFER_SIZE 128 -#define UART_TX_BUFFER_SIZE 128 +#define UART_RX_BUFFER_SIZE 128 +#define UART_TX_BUFFER_SIZE 128 struct serial_int_rx { - rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; - rt_uint32_t read_index, save_index; + rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; + rt_uint32_t read_index, save_index; }; struct serial_int_tx { - rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; - rt_uint32_t write_index, save_index; + rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; + rt_uint32_t write_index, save_index; }; /* @@ -79,15 +79,15 @@ struct serial_int_tx struct serial_device { - FM4_MFS_TypeDef* uart_device; - /* irq number */ - IRQn_Type rx_irq; - IRQn_Type tx_irq; - - /* rx structure */ - struct serial_int_rx* int_rx; - /* tx structure */ - struct serial_int_tx* int_tx; + FM4_MFS_TypeDef* uart_device; + /* irq number */ + IRQn_Type rx_irq; + IRQn_Type tx_irq; + + /* rx structure */ + struct serial_int_rx* int_rx; + /* tx structure */ + struct serial_int_tx* int_tx; }; void rt_hw_serial_isr(rt_device_t device); diff --git a/bsp/mb9bf568r/rtconfig.h b/bsp/mb9bf568r/rtconfig.h index 1982028ce7..8191fc8e65 100644 --- a/bsp/mb9bf568r/rtconfig.h +++ b/bsp/mb9bf568r/rtconfig.h @@ -3,16 +3,16 @@ #define __RTTHREAD_CFG_H__ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 64 +#define RT_THREAD_PRIORITY_MAX 64 /* Tick per Second */ -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 /* SECTION: RT_DEBUG */ /* Thread Debug */ @@ -60,9 +60,9 @@ /* #define RT_TINY_SIZE */ #define RT_USING_CONSOLE /* the buffer size of console */ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 // -#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_CONSOLE_DEVICE_NAME "uart0" /* SECTION: finsh, a C-Express shell */ /* Using FinSH as Shell*/ diff --git a/bsp/mb9bf618s/applications/startup.c b/bsp/mb9bf618s/applications/startup.c index 5ea4f5f6c4..22d38bcf95 100644 --- a/bsp/mb9bf618s/applications/startup.c +++ b/bsp/mb9bf618s/applications/startup.c @@ -39,7 +39,7 @@ void rtthread_startup(void) /* show version */ rt_show_version(); - + /* init timer system */ rt_system_timer_init(); diff --git a/bsp/mb9bf618s/drivers/board.c b/bsp/mb9bf618s/drivers/board.c index 946c17349c..8490e7a060 100644 --- a/bsp/mb9bf618s/drivers/board.c +++ b/bsp/mb9bf618s/drivers/board.c @@ -60,7 +60,7 @@ rt_uint32_t rt_hw_tick_get_microsecond(void) rt_tick_t tick; rt_uint32_t value; -#define TICK_US (1000000/RT_TICK_PER_SECOND) +#define TICK_US (1000000/RT_TICK_PER_SECOND) tick = rt_tick_get(); value = tick * TICK_US + (SysTick->LOAD - SysTick->VAL) * TICK_US / SysTick->LOAD; diff --git a/bsp/mb9bf618s/drivers/serial.c b/bsp/mb9bf618s/drivers/serial.c index 43a1cb45bd..79279e79e5 100644 --- a/bsp/mb9bf618s/drivers/serial.c +++ b/bsp/mb9bf618s/drivers/serial.c @@ -254,16 +254,16 @@ rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, { RT_ASSERT(device != RT_NULL); - device->type = RT_Device_Class_Char; + device->type = RT_Device_Class_Char; device->rx_indicate = RT_NULL; device->tx_complete = RT_NULL; - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; - device->user_data = serial; + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; + device->user_data = serial; /* register a character device */ return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); @@ -299,7 +299,7 @@ void rt_hw_serial_isr(rt_device_t device) #ifdef RT_USING_UART0 /* UART0 device driver structure */ -#define UART0 FM3_MFS0_UART +#define UART0 FM3_MFS0_UART struct serial_int_rx uart0_int_rx; struct serial_device uart0 = { @@ -323,7 +323,7 @@ void MFS0RX_IRQHandler(void) #ifdef RT_USING_UART2 /* UART2 device driver structure */ -#define UART2 FM3_MFS2_UART +#define UART2 FM3_MFS2_UART struct serial_int_rx uart2_int_rx; struct serial_device uart2 = { @@ -347,7 +347,7 @@ void MFS2RX_IRQHandler(void) #ifdef RT_USING_UART4 /* UART4 device driver structure */ -#define UART4 FM3_MFS4_UART +#define UART4 FM3_MFS4_UART struct serial_int_rx uart4_int_rx; struct serial_device uart4 = { diff --git a/bsp/mb9bf618s/drivers/serial.h b/bsp/mb9bf618s/drivers/serial.h index f26a161489..388f9eef86 100644 --- a/bsp/mb9bf618s/drivers/serial.h +++ b/bsp/mb9bf618s/drivers/serial.h @@ -6,7 +6,7 @@ * Change Logs: * Date Author Notes * 2006-03-13 Bernard first version - * 2011-05-15 lgnq modified according bernard's implementaion. + * 2011-05-15 lgnq modified according bernard's implementaion. */ #ifndef __RT_HW_SERIAL_H__ @@ -53,21 +53,21 @@ #define ESCR_DATABITS_7 0x03U #define ESCR_DATABITS_9 0x04U -#define BPS 115200 /* serial baudrate */ +#define BPS 115200 /* serial baudrate */ -#define UART_RX_BUFFER_SIZE 64 -#define UART_TX_BUFFER_SIZE 64 +#define UART_RX_BUFFER_SIZE 64 +#define UART_TX_BUFFER_SIZE 64 struct serial_int_rx { - rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; - rt_uint32_t read_index, save_index; + rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; + rt_uint32_t read_index, save_index; }; struct serial_int_tx { - rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; - rt_uint32_t write_index, save_index; + rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; + rt_uint32_t write_index, save_index; }; /* @@ -79,14 +79,14 @@ struct serial_int_tx struct serial_device { - FM3_MFS03_UART_TypeDef* uart_device; - /* irq number */ - IRQn_Type rx_irq, tx_irq; - - /* rx structure */ - struct serial_int_rx* int_rx; - /* tx structure */ - struct serial_int_tx* int_tx; + FM3_MFS03_UART_TypeDef* uart_device; + /* irq number */ + IRQn_Type rx_irq, tx_irq; + + /* rx structure */ + struct serial_int_rx* int_rx; + /* tx structure */ + struct serial_int_tx* int_tx; }; void rt_hw_serial_isr(rt_device_t device); diff --git a/bsp/mb9bf618s/rtconfig.h b/bsp/mb9bf618s/rtconfig.h index 1b647a7a30..d887692233 100644 --- a/bsp/mb9bf618s/rtconfig.h +++ b/bsp/mb9bf618s/rtconfig.h @@ -3,16 +3,16 @@ #define __RTTHREAD_CFG_H__ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 32 +#define RT_THREAD_PRIORITY_MAX 32 /* Tick per Second */ -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 /* SECTION: RT_DEBUG */ /* Thread Debug */ @@ -60,9 +60,9 @@ /* #define RT_TINY_SIZE */ #define RT_USING_CONSOLE /* the buffer size of console */ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 // -#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_CONSOLE_DEVICE_NAME "uart0" /* SECTION: finsh, a C-Express shell */ /* Using FinSH as Shell*/ diff --git a/bsp/microblaze/application.c b/bsp/microblaze/application.c index a889b2605e..d2ec464861 100755 --- a/bsp/microblaze/application.c +++ b/bsp/microblaze/application.c @@ -16,7 +16,7 @@ int rt_application_init() { - return 0; + return 0; } /*@}*/ diff --git a/bsp/microblaze/board.c b/bsp/microblaze/board.c index 1de9171151..817666999c 100755 --- a/bsp/microblaze/board.c +++ b/bsp/microblaze/board.c @@ -33,83 +33,83 @@ #include "serial.h" #endif -#define TIMER_CNTR_0 0 -#define PIV (XPAR_PROC_BUS_0_FREQ_HZ / RT_TICK_PER_SECOND) -#define LEDS_DEVICE_ID XPAR_LEDS_4BITS_DEVICE_ID -#define RS232_DEVICE_ID XPAR_USB_UART_DEVICE_ID +#define TIMER_CNTR_0 0 +#define PIV (XPAR_PROC_BUS_0_FREQ_HZ / RT_TICK_PER_SECOND) +#define LEDS_DEVICE_ID XPAR_LEDS_4BITS_DEVICE_ID +#define RS232_DEVICE_ID XPAR_USB_UART_DEVICE_ID #ifdef RT_USING_UART1 -#define USB_UART_BASE ((struct uartport *)XPAR_USB_UART_BASEADDR) +#define USB_UART_BASE ((struct uartport *)XPAR_USB_UART_BASEADDR) #endif /* Global Variables: */ -XTmrCtr timer; /* The instance of the timer */ -XGpio gpio_output; /* The driver instance for GPIO Device configured as O/P */ -XUartLite uart_lite; /* Instance of the UartLite device */ -XIntc int_ctl; /* The instance of the Interrupt Controller */ -static rt_uint32_t led_data; +XTmrCtr timer; /* The instance of the timer */ +XGpio gpio_output; /* The driver instance for GPIO Device configured as O/P */ +XUartLite uart_lite; /* Instance of the UartLite device */ +XIntc int_ctl; /* The instance of the Interrupt Controller */ +static rt_uint32_t led_data; static int cnt; static void rt_hw_board_led_init(void); -/** +/** * This function will init led on the board */ static void rt_hw_board_led_init() { - rt_uint32_t status; - led_data = 0; - cnt = 0; - status = XGpio_Initialize(&gpio_output, LEDS_DEVICE_ID); - if (status != XST_SUCCESS) - { - return; - } - - /* - * Set the direction for all signals to be outputs - */ - XGpio_SetDataDirection(&gpio_output, 1, 0x0); - /* - * Set the GPIO outputs to high - */ - XGpio_DiscreteWrite(&gpio_output, 1, 3); + rt_uint32_t status; + led_data = 0; + cnt = 0; + status = XGpio_Initialize(&gpio_output, LEDS_DEVICE_ID); + if (status != XST_SUCCESS) + { + return; + } + + /* + * Set the direction for all signals to be outputs + */ + XGpio_SetDataDirection(&gpio_output, 1, 0x0); + /* + * Set the GPIO outputs to high + */ + XGpio_DiscreteWrite(&gpio_output, 1, 3); } -/** +/** * This function will take the led on board on. * * @param n the number nth led */ void rt_hw_board_led_on(rt_uint32_t led) { - led_data |= led; - XGpio_DiscreteWrite(&gpio_output, 1, led_data); + led_data |= led; + XGpio_DiscreteWrite(&gpio_output, 1, led_data); } -/** +/** * This function will take the led on board off. * * @param n the number nth led */ void rt_hw_board_led_off(rt_uint32_t led) { - led_data &= ~led; - XGpio_DiscreteWrite(&gpio_output, 1, led_data); + led_data &= ~led; + XGpio_DiscreteWrite(&gpio_output, 1, led_data); } void rt_hw_led_flash(void) { - volatile rt_uint32_t i; + volatile rt_uint32_t i; - rt_hw_board_led_off(1); - for (i = 0; i < 20000; i ++); + rt_hw_board_led_off(1); + for (i = 0; i < 20000; i ++); - rt_hw_board_led_on(1); - for (i = 0; i < 20000; i ++); + rt_hw_board_led_on(1); + for (i = 0; i < 20000; i ++); } @@ -126,30 +126,30 @@ void rt_hw_led_flash(void) */ void rt_hw_console_output(const char* str) { - while (*str) - { + while (*str) + { - /* Transmit Character */ + /* Transmit Character */ - XUartLite_SendByte(STDOUT_BASEADDRESS, *str); - if (*str == '\n') - XUartLite_SendByte(STDOUT_BASEADDRESS, '\r'); - str++; - } + XUartLite_SendByte(STDOUT_BASEADDRESS, *str); + if (*str == '\n') + XUartLite_SendByte(STDOUT_BASEADDRESS, '\r'); + str++; + } } static void rt_hw_console_init() { - rt_uint32_t status; + rt_uint32_t status; - /* - * Initialize the UartLite driver so that it is ready to use. - */ - status = XUartLite_Initialize(&uart_lite, RS232_DEVICE_ID); - if (status != XST_SUCCESS) - { - return; - } + /* + * Initialize the UartLite driver so that it is ready to use. + */ + status = XUartLite_Initialize(&uart_lite, RS232_DEVICE_ID); + if (status != XST_SUCCESS) + { + return; + } } #endif @@ -157,16 +157,16 @@ static void rt_hw_console_init() void rt_hw_timer_handler(void) { - rt_uint32_t csr; - csr = XTmrCtr_ReadReg(timer.BaseAddress, TIMER_CNTR_0, XTC_TCSR_OFFSET); - /* - * Check if timer expired and interrupt occured - */ - if (csr & XTC_CSR_INT_OCCURED_MASK) - { - rt_tick_increase(); - XTmrCtr_WriteReg(timer.BaseAddress, TIMER_CNTR_0, XTC_TCSR_OFFSET, csr | XTC_CSR_INT_OCCURED_MASK); - } + rt_uint32_t csr; + csr = XTmrCtr_ReadReg(timer.BaseAddress, TIMER_CNTR_0, XTC_TCSR_OFFSET); + /* + * Check if timer expired and interrupt occured + */ + if (csr & XTC_CSR_INT_OCCURED_MASK) + { + rt_tick_increase(); + XTmrCtr_WriteReg(timer.BaseAddress, TIMER_CNTR_0, XTC_TCSR_OFFSET, csr | XTC_CSR_INT_OCCURED_MASK); + } } @@ -192,24 +192,24 @@ void rt_intc_init (void) status = XIntc_Initialize(&int_ctl, XPAR_INTC_0_DEVICE_ID); - /* install interrupt handler */ + /* install interrupt handler */ rt_hw_interrupt_install(XPAR_INTC_0_TMRCTR_0_VEC_ID, (rt_isr_handler_t)rt_hw_timer_handler, RT_NULL); - rt_hw_interrupt_umask(XPAR_INTC_0_TMRCTR_0_VEC_ID); + rt_hw_interrupt_umask(XPAR_INTC_0_TMRCTR_0_VEC_ID); - XIntc_Start(&int_ctl, XIN_REAL_MODE); + XIntc_Start(&int_ctl, XIN_REAL_MODE); } void rt_tmr_init (void) { - rt_uint32_t ctl; - XStatus status; + rt_uint32_t ctl; + XStatus status; status = XTmrCtr_Initialize(&timer,XPAR_AXI_TIMER_0_DEVICE_ID); - XTmrCtr_WriteReg(timer.BaseAddress, TIMER_CNTR_0, XTC_TLR_OFFSET, PIV); + XTmrCtr_WriteReg(timer.BaseAddress, TIMER_CNTR_0, XTC_TLR_OFFSET, PIV); ctl = XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK; - XTmrCtr_WriteReg(timer.BaseAddress, TIMER_CNTR_0, XTC_TCSR_OFFSET, ctl); + XTmrCtr_WriteReg(timer.BaseAddress, TIMER_CNTR_0, XTC_TCSR_OFFSET, ctl); } @@ -219,15 +219,15 @@ void rt_tmr_init (void) */ void rt_hw_board_init() { - microblaze_disable_icache(); - microblaze_disable_dcache(); - /* init hardware console */ - rt_hw_console_init(); + microblaze_disable_icache(); + microblaze_disable_dcache(); + /* init hardware console */ + rt_hw_console_init(); - /* init led */ - rt_hw_board_led_init(); + /* init led */ + rt_hw_board_led_init(); - /* init intc */ + /* init intc */ rt_intc_init(); /* timer init */ diff --git a/bsp/microblaze/board.h b/bsp/microblaze/board.h index 9e542c17c5..0047bfebed 100755 --- a/bsp/microblaze/board.h +++ b/bsp/microblaze/board.h @@ -13,7 +13,7 @@ #define __BOARD_H__ -#define MCK 50000000 +#define MCK 50000000 void rt_hw_board_led_on(rt_uint32_t); void rt_hw_board_led_off(rt_uint32_t); diff --git a/bsp/microblaze/rtconfig.h b/bsp/microblaze/rtconfig.h index d054c175b9..feedfdd09b 100755 --- a/bsp/microblaze/rtconfig.h +++ b/bsp/microblaze/rtconfig.h @@ -2,19 +2,19 @@ #ifndef __RTTHREAD_CFG_H__ #define __RTTHREAD_CFG_H__ -#define IDLE_THREAD_STACK_SIZE 2048 +#define IDLE_THREAD_STACK_SIZE 2048 /* RT_NAME_MAX*/ -#define RT_NAME_MAX 32 +#define RT_NAME_MAX 32 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX*/ -#define RT_THREAD_PRIORITY_MAX 32 +#define RT_THREAD_PRIORITY_MAX 32 /* Tick per Second*/ -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 /* SECTION: RT_DEBUG */ @@ -61,10 +61,10 @@ #define RT_USING_DEVICE /* buffer size for UART reception*/ -#define RT_UART_RX_BUFFER_SIZE 64 +#define RT_UART_RX_BUFFER_SIZE 64 /* buffer size for UART transmission*/ -#define RT_UART_TX_BUFFER_SIZE 64 +#define RT_UART_TX_BUFFER_SIZE 64 /* Using UART1*/ #define RT_USING_UART1 @@ -78,7 +78,7 @@ /* SECTION: Console options */ #define RT_USING_CONSOLE /* the buffer size of console*/ -#define RT_CONSOLEBUF_SIZE 256 +#define RT_CONSOLEBUF_SIZE 256 /* SECTION: FinSH shell options */ /* Using FinSH as Shell*/ @@ -137,10 +137,10 @@ #define RT_LWIP_TCP /* the number of simulatenously active TCP connections*/ -#define RT_LWIP_TCP_PCB_NUM 5 +#define RT_LWIP_TCP_PCB_NUM 5 /* TCP sender buffer space*/ -#define RT_LWIP_TCP_SND_BUF 10240 +#define RT_LWIP_TCP_SND_BUF 10240 /* Enable SNMP protocol*/ /* #define RT_LWIP_SNMP */ @@ -149,42 +149,42 @@ /* #define RT_LWIP_DHCP */ /* ip address of target*/ -#define RT_LWIP_IPADDR0 192 -#define RT_LWIP_IPADDR1 168 -#define RT_LWIP_IPADDR2 0 -#define RT_LWIP_IPADDR3 30 +#define RT_LWIP_IPADDR0 192 +#define RT_LWIP_IPADDR1 168 +#define RT_LWIP_IPADDR2 0 +#define RT_LWIP_IPADDR3 30 /* gateway address of target*/ -#define RT_LWIP_GWADDR0 192 -#define RT_LWIP_GWADDR1 168 -#define RT_LWIP_GWADDR2 0 -#define RT_LWIP_GWADDR3 1 +#define RT_LWIP_GWADDR0 192 +#define RT_LWIP_GWADDR1 168 +#define RT_LWIP_GWADDR2 0 +#define RT_LWIP_GWADDR3 1 /* mask address of target*/ -#define RT_LWIP_MSKADDR0 255 -#define RT_LWIP_MSKADDR1 255 -#define RT_LWIP_MSKADDR2 255 -#define RT_LWIP_MSKADDR3 0 +#define RT_LWIP_MSKADDR0 255 +#define RT_LWIP_MSKADDR1 255 +#define RT_LWIP_MSKADDR2 255 +#define RT_LWIP_MSKADDR3 0 /* the number of blocks for pbuf*/ -#define RT_LWIP_PBUF_NUM 16 +#define RT_LWIP_PBUF_NUM 16 /* thread priority of tcpip thread*/ -#define RT_LWIP_TCPTHREAD_PRIORITY 128 +#define RT_LWIP_TCPTHREAD_PRIORITY 128 /* mail box size of tcpip thread to wait for*/ -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 /* thread stack size of tcpip thread*/ -#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 +#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 /* thread priority of ethnetif thread*/ -#define RT_LWIP_ETHTHREAD_PRIORITY 144 +#define RT_LWIP_ETHTHREAD_PRIORITY 144 /* mail box size of ethnetif thread to wait for*/ -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 32 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 32 /* thread stack size of ethnetif thread*/ -#define RT_LWIP_ETHTHREAD_STACKSIZE 1024 +#define RT_LWIP_ETHTHREAD_STACKSIZE 1024 #endif diff --git a/bsp/microblaze/startup.c b/bsp/microblaze/startup.c index 941a908f8f..eb32b0ad8f 100755 --- a/bsp/microblaze/startup.c +++ b/bsp/microblaze/startup.c @@ -6,7 +6,7 @@ * Change Logs: * Date Author Notes * 2006-08-31 Bernard first implementation - * 2011-12-17 nl1031 for MicroBlaze + * 2011-12-17 nl1031 for MicroBlaze */ #include @@ -43,72 +43,72 @@ extern rt_err_t rt_hw_serial_init(void); */ void rtthread_startup(void) { - /* init hardware interrupt */ - rt_hw_interrupt_init(); + /* init hardware interrupt */ + rt_hw_interrupt_init(); - /* init board */ - rt_hw_board_init(); - - rt_show_version(); + /* init board */ + rt_hw_board_init(); - /* init tick */ - rt_system_tick_init(); + rt_show_version(); - /* init kernel object */ - rt_system_object_init(); + /* init tick */ + rt_system_tick_init(); - /* init timer system */ - rt_system_timer_init(); + /* init kernel object */ + rt_system_object_init(); + + /* init timer system */ + rt_system_timer_init(); #ifdef RT_USING_HEAP #ifdef __CC_ARM - rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x204000); + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x204000); #elif __ICCARM__ rt_system_heap_init(__segment_end("HEAP"), (void*)0x204000); #else - rt_system_heap_init((void*)&__bss_end, (void*)(&__bss_end+0x4000)); + rt_system_heap_init((void*)&__bss_end, (void*)(&__bss_end+0x4000)); #endif #endif - /* init scheduler system */ - rt_system_scheduler_init(); + /* init scheduler system */ + rt_system_scheduler_init(); #ifdef RT_USING_HOOK /* if the hook is used */ - /* set idle thread hook */ - rt_thread_idle_sethook(rt_hw_led_flash); + /* set idle thread hook */ + rt_thread_idle_sethook(rt_hw_led_flash); #endif #ifdef RT_USING_DEVICE - /* init hardware serial device */ - rt_hw_serial_init(); + /* init hardware serial device */ + rt_hw_serial_init(); #endif - /* init application */ - rt_application_init(); + /* init application */ + rt_application_init(); #ifdef RT_USING_FINSH - /* init finsh */ - finsh_system_init(); - finsh_set_device("uart1"); + /* init finsh */ + finsh_system_init(); + finsh_set_device("uart1"); #endif - /* init idle thread */ - rt_thread_idle_init(); + /* init idle thread */ + rt_thread_idle_init(); - /* start scheduler */ - rt_system_scheduler_start(); + /* start scheduler */ + rt_system_scheduler_start(); - /* never reach here */ - return ; + /* never reach here */ + return ; } int main (void) { - /* invoke rtthread_startup */ - rtthread_startup(); - - return 0; + /* invoke rtthread_startup */ + rtthread_startup(); + + return 0; } /*@}*/ diff --git a/bsp/mini2440/applications/application.c b/bsp/mini2440/applications/application.c index 194618a925..4412847170 100644 --- a/bsp/mini2440/applications/application.c +++ b/bsp/mini2440/applications/application.c @@ -4,15 +4,15 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2007-11-20 Yi.Qiu add rtgui application - * 2008-6-28 Bernard no rtgui init + * Date Author Notes + * 2007-11-20 Yi.Qiu add rtgui application + * 2008-6-28 Bernard no rtgui init */ /** * @addtogroup mini2440 */ - + /*@{*/ #include @@ -56,11 +56,11 @@ static char* argv[] = {"ftk", NULL}; void rt_ftk_thread_entry(void *parameter) { - int FTK_MAIN(int argc, char *argv[]); + int FTK_MAIN(int argc, char *argv[]); - FTK_MAIN(argc, argv); + FTK_MAIN(argc, argv); - return; + return; } #endif @@ -69,180 +69,180 @@ void rt_init_thread_entry(void *parameter) { /* Filesystem Initialization */ #ifdef RT_USING_DFS - { - /* init the device filesystem */ - dfs_init(); + { + /* init the device filesystem */ + dfs_init(); #if defined(RT_USING_DFS_ELMFAT) - /* init the elm chan FatFs filesystam*/ - elm_init(); - /* mount sd card fat partition 1 as root directory */ - if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) - { - rt_kprintf("File System initialized!\n"); - } - else - rt_kprintf("File System initialzation failed!\n"); + /* init the elm chan FatFs filesystam*/ + elm_init(); + /* mount sd card fat partition 1 as root directory */ + if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) + { + rt_kprintf("File System initialized!\n"); + } + else + rt_kprintf("File System initialzation failed!\n"); #endif #if defined(RT_USING_DFS_ROMFS) - dfs_romfs_init(); - if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0) - { - rt_kprintf("ROM File System initialized!\n"); - } - else - rt_kprintf("ROM File System initialzation failed!\n"); + dfs_romfs_init(); + if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0) + { + rt_kprintf("ROM File System initialized!\n"); + } + else + rt_kprintf("ROM File System initialzation failed!\n"); #endif #if defined(RT_USING_DFS_DEVFS) - devfs_init(); - if (dfs_mount(RT_NULL, "/dev", "devfs", 0, 0) == 0) - rt_kprintf("Device File System initialized!\n"); - else - rt_kprintf("Device File System initialzation failed!\n"); + devfs_init(); + if (dfs_mount(RT_NULL, "/dev", "devfs", 0, 0) == 0) + rt_kprintf("Device File System initialized!\n"); + else + rt_kprintf("Device File System initialzation failed!\n"); - #ifdef RT_USING_NEWLIB - /* init libc */ - libc_system_init("uart0"); - #endif + #ifdef RT_USING_NEWLIB + /* init libc */ + libc_system_init("uart0"); + #endif #endif #if defined(RT_USING_DFS) && defined(RT_USING_LWIP) && defined(RT_USING_DFS_NFS) - /* NFSv3 Initialization */ - nfs_init(); + /* NFSv3 Initialization */ + nfs_init(); - if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0) - rt_kprintf("NFSv3 File System initialized!\n"); - else - rt_kprintf("NFSv3 File System initialzation failed!\n"); + if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0) + rt_kprintf("NFSv3 File System initialized!\n"); + else + rt_kprintf("NFSv3 File System initialzation failed!\n"); #endif #if defined(RT_USING_DFS_UFFS) - /* init the uffs filesystem */ - dfs_uffs_init(); + /* init the uffs filesystem */ + dfs_uffs_init(); - /* mount flash device as flash directory */ - if (dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0) - rt_kprintf("UFFS File System initialized!\n"); - else - rt_kprintf("UFFS File System initialzation failed!\n"); + /* mount flash device as flash directory */ + if (dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0) + rt_kprintf("UFFS File System initialized!\n"); + else + rt_kprintf("UFFS File System initialzation failed!\n"); #endif - } + } #endif #ifdef RT_USING_RTGUI - { - extern void rtgui_system_server_init(void); + { + extern void rtgui_system_server_init(void); + + rt_device_t lcd; + + /* init lcd */ + rt_hw_lcd_init(); - rt_device_t lcd; - - /* init lcd */ - rt_hw_lcd_init(); - - /* init touch panel */ - rtgui_touch_hw_init(); + /* init touch panel */ + rtgui_touch_hw_init(); - /* init keypad */ - rt_hw_key_init(); + /* init keypad */ + rt_hw_key_init(); - /* find lcd device */ - lcd = rt_device_find("lcd"); + /* find lcd device */ + lcd = rt_device_find("lcd"); - /* set lcd device as rtgui graphic driver */ - rtgui_graphic_set_device(lcd); + /* set lcd device as rtgui graphic driver */ + rtgui_graphic_set_device(lcd); - /* initalize rtgui system server */ - rtgui_system_server_init(); - } + /* initalize rtgui system server */ + rtgui_system_server_init(); + } #endif /* LwIP Initialization */ #ifdef RT_USING_LWIP - { - extern void lwip_sys_init(void); - eth_system_device_init(); + { + extern void lwip_sys_init(void); + eth_system_device_init(); - /* register ethernetif device */ - rt_hw_dm9000_init(); + /* register ethernetif device */ + rt_hw_dm9000_init(); - /* init lwip system */ - lwip_sys_init(); - rt_kprintf("TCP/IP initialized!\n"); - } + /* init lwip system */ + lwip_sys_init(); + rt_kprintf("TCP/IP initialized!\n"); + } #endif #ifdef RT_USING_FTK - { - rt_thread_t ftk_thread; + { + rt_thread_t ftk_thread; - /* init lcd */ - rt_hw_lcd_init(); + /* init lcd */ + rt_hw_lcd_init(); - /* init touch panel */ - rtgui_touch_hw_init(); + /* init touch panel */ + rtgui_touch_hw_init(); - /* init keypad */ - rt_hw_key_init(); + /* init keypad */ + rt_hw_key_init(); - /* create ftk thread */ - ftk_thread = rt_thread_create("ftk", - rt_ftk_thread_entry, RT_NULL, - 10 * 1024, 8, 20); + /* create ftk thread */ + ftk_thread = rt_thread_create("ftk", + rt_ftk_thread_entry, RT_NULL, + 10 * 1024, 8, 20); - /* startup ftk thread */ - if (ftk_thread != RT_NULL) - rt_thread_startup(ftk_thread); - } + /* startup ftk thread */ + if (ftk_thread != RT_NULL) + rt_thread_startup(ftk_thread); + } #endif } void rt_led_thread_entry(void *parameter) { - while (1) - { - /* light on leds for one second */ - rt_hw_led_on(LED2|LED3); - rt_hw_led_off(LED1|LED4); - rt_thread_delay(100); - - /* light off leds for one second */ - rt_hw_led_off(LED2|LED3); - rt_hw_led_on(LED1|LED4); - rt_thread_delay(100); - } + while (1) + { + /* light on leds for one second */ + rt_hw_led_on(LED2|LED3); + rt_hw_led_off(LED1|LED4); + rt_thread_delay(100); + + /* light off leds for one second */ + rt_hw_led_off(LED2|LED3); + rt_hw_led_on(LED1|LED4); + rt_thread_delay(100); + } } int rt_application_init(void) { - rt_thread_t init_thread; - rt_thread_t led_thread; + rt_thread_t init_thread; + rt_thread_t led_thread; #if (RT_THREAD_PRIORITY_MAX == 32) - init_thread = rt_thread_create("init", - rt_init_thread_entry, RT_NULL, - RT_INIT_THREAD_STACK_SIZE, 8, 20); + init_thread = rt_thread_create("init", + rt_init_thread_entry, RT_NULL, + RT_INIT_THREAD_STACK_SIZE, 8, 20); - led_thread = rt_thread_create("led", - rt_led_thread_entry, RT_NULL, - 512, 20, 20); + led_thread = rt_thread_create("led", + rt_led_thread_entry, RT_NULL, + 512, 20, 20); #else - init_thread = rt_thread_create("init", - rt_init_thread_entry, RT_NULL, - RT_INIT_THREAD_STACK_SIZE, 80, 20); + init_thread = rt_thread_create("init", + rt_init_thread_entry, RT_NULL, + RT_INIT_THREAD_STACK_SIZE, 80, 20); - led_thread = rt_thread_create("led", - rt_led_thread_entry, RT_NULL, - 512, 200, 20); + led_thread = rt_thread_create("led", + rt_led_thread_entry, RT_NULL, + 512, 200, 20); #endif - if (init_thread != RT_NULL) - rt_thread_startup(init_thread); + if (init_thread != RT_NULL) + rt_thread_startup(init_thread); - if (led_thread != RT_NULL) - rt_thread_startup(led_thread); + if (led_thread != RT_NULL) + rt_thread_startup(led_thread); - return 0; + return 0; } /*@}*/ diff --git a/bsp/mini2440/applications/startup.c b/bsp/mini2440/applications/startup.c index 162cc8a7b4..3d21949b6c 100644 --- a/bsp/mini2440/applications/startup.c +++ b/bsp/mini2440/applications/startup.c @@ -43,17 +43,17 @@ extern struct rt_device uart2_device; /*@{*/ #if defined(__CC_ARM) - extern int Image$$ER_ZI$$ZI$$Base; - extern int Image$$ER_ZI$$ZI$$Length; - extern int Image$$ER_ZI$$ZI$$Limit; + extern int Image$$ER_ZI$$ZI$$Base; + extern int Image$$ER_ZI$$ZI$$Length; + extern int Image$$ER_ZI$$ZI$$Limit; #elif (defined (__GNUC__)) - rt_uint8_t _irq_stack_start[1024]; - rt_uint8_t _fiq_stack_start[1024]; - rt_uint8_t _undefined_stack_start[512]; - rt_uint8_t _abort_stack_start[512]; - rt_uint8_t _svc_stack_start[4096] SECTION(".nobss"); - extern unsigned char __bss_start; - extern unsigned char __bss_end; + rt_uint8_t _irq_stack_start[1024]; + rt_uint8_t _fiq_stack_start[1024]; + rt_uint8_t _undefined_stack_start[512]; + rt_uint8_t _abort_stack_start[512]; + rt_uint8_t _svc_stack_start[4096] SECTION(".nobss"); + extern unsigned char __bss_start; + extern unsigned char __bss_end; #endif #ifdef RT_USING_FINSH @@ -65,97 +65,97 @@ extern int finsh_system_init(void); */ void rtthread_startup(void) { - /* enable cpu cache */ - rt_hw_cpu_icache_enable(); - rt_hw_cpu_dcache_enable(); + /* enable cpu cache */ + rt_hw_cpu_icache_enable(); + rt_hw_cpu_dcache_enable(); - /* init hardware interrupt */ - rt_hw_interrupt_init(); + /* init hardware interrupt */ + rt_hw_interrupt_init(); - /* init board */ - rt_hw_board_init(); + /* init board */ + rt_hw_board_init(); - /* show version */ - rt_show_version(); + /* show version */ + rt_show_version(); - /* init tick */ - rt_system_tick_init(); + /* init tick */ + rt_system_tick_init(); - /* init kernel object */ - rt_system_object_init(); + /* init kernel object */ + rt_system_object_init(); - /* init timer system */ - rt_system_timer_init(); + /* init timer system */ + rt_system_timer_init(); - /* init heap memory system */ + /* init heap memory system */ #ifdef __CC_ARM - rt_system_heap_init((void*)&Image$$ER_ZI$$ZI$$Limit, (void*)0x33F00000); + rt_system_heap_init((void*)&Image$$ER_ZI$$ZI$$Limit, (void*)0x33F00000); #else - rt_system_heap_init((void*)&__bss_end, (void*)0x33F00000); + rt_system_heap_init((void*)&__bss_end, (void*)0x33F00000); #endif #ifdef RT_USING_MODULE - /* init module system*/ - rt_system_module_init(); + /* init module system*/ + rt_system_module_init(); #endif - /* init scheduler system */ - rt_system_scheduler_init(); + /* init scheduler system */ + rt_system_scheduler_init(); #ifdef RT_USING_DEVICE - /* register uart0 */ - rt_hw_serial_register(&uart0_device, "uart0", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart0); + /* register uart0 */ + rt_hw_serial_register(&uart0_device, "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart0); - /* register uart2, used for RTI debug */ - rt_hw_serial_register(&uart2_device, "uart2", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart2); + /* register uart2, used for RTI debug */ + rt_hw_serial_register(&uart2_device, "uart2", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart2); #ifdef RT_USING_DFS - rt_hw_sdcard_init(); + rt_hw_sdcard_init(); #ifdef RT_USING_DFS_UFFS - rt_hw_nand_init(); + rt_hw_nand_init(); #endif #endif - /* rtc init */ - rt_hw_rtc_init(); + /* rtc init */ + rt_hw_rtc_init(); #endif - /* init application */ - rt_application_init(); + /* init application */ + rt_application_init(); #ifdef RT_USING_FINSH - /* init finsh */ - finsh_system_init(); + /* init finsh */ + finsh_system_init(); #ifdef RT_USING_DEVICE - finsh_set_device("uart0"); + finsh_set_device("uart0"); #endif #endif - rt_system_timer_thread_init(); + rt_system_timer_thread_init(); - /* init idle thread */ - rt_thread_idle_init(); + /* init idle thread */ + rt_thread_idle_init(); - /* start scheduler */ - rt_system_scheduler_start(); + /* start scheduler */ + rt_system_scheduler_start(); - /* never reach here */ - return ; + /* never reach here */ + return ; } int main(void) { - /* disable interrupt first */ - rt_hw_interrupt_disable(); + /* disable interrupt first */ + rt_hw_interrupt_disable(); - /* startup RT-Thread RTOS */ - rtthread_startup(); + /* startup RT-Thread RTOS */ + rtthread_startup(); - return 0; + return 0; } /*@}*/ diff --git a/bsp/mini2440/drivers/board.c b/bsp/mini2440/drivers/board.c index a8592610aa..8029a7c507 100644 --- a/bsp/mini2440/drivers/board.c +++ b/bsp/mini2440/drivers/board.c @@ -8,7 +8,7 @@ * 2006-03-24 Bernard first implementation * 2006-05-05 Bernard add DATA_COUNT definition * 2006-10-05 Alsor.Z for s3c2410x porting - * 2007-11-20 Yi.Qiu add lcd,touch,console + * 2007-11-20 Yi.Qiu add lcd,touch,console */ #include @@ -31,23 +31,23 @@ extern void rt_hw_get_clock(void); extern void rt_hw_set_dividor(rt_uint8_t hdivn, rt_uint8_t pdivn); extern void rt_hw_set_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv); -#define UART0 ((struct uartport *)&U0BASE) +#define UART0 ((struct uartport *)&U0BASE) struct serial_int_rx uart0_int_rx; struct serial_device uart0 = { - UART0, - &uart0_int_rx, - RT_NULL + UART0, + &uart0_int_rx, + RT_NULL }; struct rt_device uart0_device; -#define UART2 ((struct uartport *)&U2BASE) +#define UART2 ((struct uartport *)&U2BASE) struct serial_int_rx uart2_int_rx; struct serial_device uart2 = { - UART2, - &uart2_int_rx, - RT_NULL + UART2, + &uart2_int_rx, + RT_NULL }; struct rt_device uart2_device; @@ -56,7 +56,7 @@ struct rt_device uart2_device; */ static void rt_timer_handler(int vector, void *param) { - rt_tick_increase(); + rt_tick_increase(); } /** @@ -64,14 +64,14 @@ static void rt_timer_handler(int vector, void *param) */ static void rt_serial0_handler(int vector, void *param) { - INTSUBMSK |= (BIT_SUB_RXD0); + INTSUBMSK |= (BIT_SUB_RXD0); - rt_hw_serial_isr(&uart0_device); + rt_hw_serial_isr(&uart0_device); - SUBSRCPND |= BIT_SUB_RXD0; + SUBSRCPND |= BIT_SUB_RXD0; - /* Unmask sub interrupt (RXD0) */ - INTSUBMSK &=~(BIT_SUB_RXD0); + /* Unmask sub interrupt (RXD0) */ + INTSUBMSK &=~(BIT_SUB_RXD0); } /** @@ -79,14 +79,14 @@ static void rt_serial0_handler(int vector, void *param) */ static void rt_serial2_handler(int vector, void *param) { - INTSUBMSK |= (BIT_SUB_RXD2); + INTSUBMSK |= (BIT_SUB_RXD2); - rt_hw_serial_isr(&uart2_device); + rt_hw_serial_isr(&uart2_device); - SUBSRCPND |= BIT_SUB_RXD2; + SUBSRCPND |= BIT_SUB_RXD2; - /* Unmask sub interrupt (RXD0) */ - INTSUBMSK &=~(BIT_SUB_RXD2); + /* Unmask sub interrupt (RXD0) */ + INTSUBMSK &=~(BIT_SUB_RXD2); } /** @@ -94,55 +94,55 @@ static void rt_serial2_handler(int vector, void *param) */ static void rt_hw_uart_init(void) { - int i; - /* UART0 port configure */ - GPHCON |= 0xAA; - /* PULLUP is disable */ - GPHUP |= 0xF; - - /* FIFO enable, Tx/Rx FIFO clear */ - uart0.uart_device->ufcon = 0x0; - /* disable the flow control */ - uart0.uart_device->umcon = 0x0; - /* Normal,No parity,1 stop,8 bit */ - uart0.uart_device->ulcon = 0x3; - /* - * tx=level,rx=edge,disable timeout int.,enable rx error int., - * normal,interrupt or polling - */ - uart0.uart_device->ucon = 0x245; - /* Set uart0 bps */ - uart0.uart_device->ubrd = (rt_int32_t)(PCLK / (BPS * 16)) - 1; - /* output PCLK to UART0/1, PWMTIMER */ - CLKCON |= 0x0D00; - - /* FIFO enable, Tx/Rx FIFO clear */ - uart2.uart_device->ufcon = 0x0; - /* disable the flow control */ - uart2.uart_device->umcon = 0x0; - /* Normal,No parity,1 stop,8 bit */ - uart2.uart_device->ulcon = 0x3; - /* - * tx=level,rx=edge,disable timeout int.,enable rx error int., - * normal,interrupt or polling - */ - uart2.uart_device->ucon = 0x245; - /* Set uart0 bps */ - uart2.uart_device->ubrd = (rt_int32_t)(PCLK / (BPS * 16)) - 1; - - for (i = 0; i < 100; i++); - - /* install uart0 isr */ - INTSUBMSK &= ~(BIT_SUB_RXD0); - - /* install uart2 isr */ - INTSUBMSK &= ~(BIT_SUB_RXD2); - - rt_hw_interrupt_install(INTUART0, rt_serial0_handler, RT_NULL, "UART0"); - rt_hw_interrupt_umask(INTUART0); - - rt_hw_interrupt_install(INTUART2, rt_serial2_handler, RT_NULL, "UART2"); - rt_hw_interrupt_umask(INTUART2); + int i; + /* UART0 port configure */ + GPHCON |= 0xAA; + /* PULLUP is disable */ + GPHUP |= 0xF; + + /* FIFO enable, Tx/Rx FIFO clear */ + uart0.uart_device->ufcon = 0x0; + /* disable the flow control */ + uart0.uart_device->umcon = 0x0; + /* Normal,No parity,1 stop,8 bit */ + uart0.uart_device->ulcon = 0x3; + /* + * tx=level,rx=edge,disable timeout int.,enable rx error int., + * normal,interrupt or polling + */ + uart0.uart_device->ucon = 0x245; + /* Set uart0 bps */ + uart0.uart_device->ubrd = (rt_int32_t)(PCLK / (BPS * 16)) - 1; + /* output PCLK to UART0/1, PWMTIMER */ + CLKCON |= 0x0D00; + + /* FIFO enable, Tx/Rx FIFO clear */ + uart2.uart_device->ufcon = 0x0; + /* disable the flow control */ + uart2.uart_device->umcon = 0x0; + /* Normal,No parity,1 stop,8 bit */ + uart2.uart_device->ulcon = 0x3; + /* + * tx=level,rx=edge,disable timeout int.,enable rx error int., + * normal,interrupt or polling + */ + uart2.uart_device->ucon = 0x245; + /* Set uart0 bps */ + uart2.uart_device->ubrd = (rt_int32_t)(PCLK / (BPS * 16)) - 1; + + for (i = 0; i < 100; i++); + + /* install uart0 isr */ + INTSUBMSK &= ~(BIT_SUB_RXD0); + + /* install uart2 isr */ + INTSUBMSK &= ~(BIT_SUB_RXD2); + + rt_hw_interrupt_install(INTUART0, rt_serial0_handler, RT_NULL, "UART0"); + rt_hw_interrupt_umask(INTUART0); + + rt_hw_interrupt_install(INTUART2, rt_serial2_handler, RT_NULL, "UART2"); + rt_hw_interrupt_umask(INTUART2); } /** @@ -150,22 +150,22 @@ static void rt_hw_uart_init(void) */ static void rt_hw_timer_init(void) { - /* timer4, pre = 15+1 */ - TCFG0 &= 0xffff00ff; - TCFG0 |= 15 << 8; - /* all are interrupt mode,set Timer 4 MUX 1/4 */ - TCFG1 &= 0xfff0ffff; - TCFG1 |= 0x00010000; - - TCNTB4 = (rt_int32_t)(PCLK / (4 *16* RT_TICK_PER_SECOND)) - 1; - /* manual update */ - TCON = TCON & (~(0x0f<<20)) | (0x02<<20); - /* install interrupt handler */ - rt_hw_interrupt_install(INTTIMER4, rt_timer_handler, RT_NULL, "tick"); - rt_hw_interrupt_umask(INTTIMER4); + /* timer4, pre = 15+1 */ + TCFG0 &= 0xffff00ff; + TCFG0 |= 15 << 8; + /* all are interrupt mode,set Timer 4 MUX 1/4 */ + TCFG1 &= 0xfff0ffff; + TCFG1 |= 0x00010000; + + TCNTB4 = (rt_int32_t)(PCLK / (4 *16* RT_TICK_PER_SECOND)) - 1; + /* manual update */ + TCON = TCON & (~(0x0f<<20)) | (0x02<<20); + /* install interrupt handler */ + rt_hw_interrupt_install(INTTIMER4, rt_timer_handler, RT_NULL, "tick"); + rt_hw_interrupt_umask(INTTIMER4); /* start timer4, reload */ - TCON = TCON & (~(0x0f<<20)) | (0x05<<20); + TCON = TCON & (~(0x0f<<20)) | (0x05<<20); } /** @@ -173,23 +173,23 @@ static void rt_hw_timer_init(void) */ void rt_hw_board_init(void) { - /* initialize the system clock */ - rt_hw_clock_init(); + /* initialize the system clock */ + rt_hw_clock_init(); - /* Get the clock */ - rt_hw_get_clock(); + /* Get the clock */ + rt_hw_get_clock(); - /* initialize led port */ - rt_hw_led_init(); + /* initialize led port */ + rt_hw_led_init(); - /* initialize uart */ - rt_hw_uart_init(); + /* initialize uart */ + rt_hw_uart_init(); - /* initialize mmu */ - rt_hw_mmu_init(); + /* initialize mmu */ + rt_hw_mmu_init(); - /* initialize timer4 */ - rt_hw_timer_init(); + /* initialize timer4 */ + rt_hw_timer_init(); } /*@}*/ diff --git a/bsp/mini2440/drivers/key.c b/bsp/mini2440/drivers/key.c index 8c59b0fbdf..c33285c290 100644 --- a/bsp/mini2440/drivers/key.c +++ b/bsp/mini2440/drivers/key.c @@ -8,68 +8,68 @@ * 2010-10-01 Yi.Qiu first version */ - /* - * Warning, this keypad driver can only work on QEMU emulator + /* + * Warning, this keypad driver can only work on QEMU emulator */ - + #include #include #include -#define KEY_RX_BUFFER_SIZE 32 +#define KEY_RX_BUFFER_SIZE 32 struct rt_key_device { - struct rt_device parent; + struct rt_device parent; - rt_uint32_t rx_buffer[KEY_RX_BUFFER_SIZE]; - rt_uint32_t read_index, save_index; -}; + rt_uint32_t rx_buffer[KEY_RX_BUFFER_SIZE]; + rt_uint32_t read_index, save_index; +}; static struct rt_key_device *key_device = RT_NULL; /* save a char to serial buffer */ static void rt_key_savechar(char ch) { - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - key_device->rx_buffer[key_device->save_index] = ch; - key_device->save_index ++; - if (key_device->save_index >= KEY_RX_BUFFER_SIZE) - key_device->save_index = 0; - - /* if the next position is read index, discard this 'read char' */ - if (key_device->save_index == key_device->read_index) - { - key_device->read_index ++; - if (key_device->read_index >= KEY_RX_BUFFER_SIZE) - key_device->read_index = 0; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + key_device->rx_buffer[key_device->save_index] = ch; + key_device->save_index ++; + if (key_device->save_index >= KEY_RX_BUFFER_SIZE) + key_device->save_index = 0; + + /* if the next position is read index, discard this 'read char' */ + if (key_device->save_index == key_device->read_index) + { + key_device->read_index ++; + if (key_device->read_index >= KEY_RX_BUFFER_SIZE) + key_device->read_index = 0; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); } /* ISR for serial interrupt */ static void rt_hw_key_isr(void) { - /* save on rx buffer */ - rt_key_savechar(URXH1 & 0xff); - - /* invoke callback */ - if (key_device->parent.rx_indicate != RT_NULL) - { - rt_size_t rx_length; - - /* get rx length */ - rx_length = key_device->read_index > key_device->save_index ? - KEY_RX_BUFFER_SIZE - key_device->read_index + key_device->save_index : - key_device->save_index - key_device->read_index; - - key_device->parent.rx_indicate(&key_device->parent, rx_length); - } + /* save on rx buffer */ + rt_key_savechar(URXH1 & 0xff); + + /* invoke callback */ + if (key_device->parent.rx_indicate != RT_NULL) + { + rt_size_t rx_length; + + /* get rx length */ + rx_length = key_device->read_index > key_device->save_index ? + KEY_RX_BUFFER_SIZE - key_device->read_index + key_device->save_index : + key_device->save_index - key_device->read_index; + + key_device->parent.rx_indicate(&key_device->parent, rx_length); + } } /** @@ -77,14 +77,14 @@ static void rt_hw_key_isr(void) */ static void rt_key_handler(int vector) { - INTSUBMSK |= (BIT_SUB_RXD1); - - rt_hw_key_isr(); - - SUBSRCPND |= BIT_SUB_RXD1; - - /*Unmask sub interrupt (RXD0)*/ - INTSUBMSK &=~(BIT_SUB_RXD1); + INTSUBMSK |= (BIT_SUB_RXD1); + + rt_hw_key_isr(); + + SUBSRCPND |= BIT_SUB_RXD1; + + /*Unmask sub interrupt (RXD0)*/ + INTSUBMSK &=~(BIT_SUB_RXD1); } /** @@ -92,114 +92,114 @@ static void rt_key_handler(int vector) */ static void key_init(void) { - int i = 0; - - GPHCON |= 0xa0; - /*PULLUP is enable */ - GPHUP |= 0x0c; - - /* FIFO enable, Tx/Rx FIFO clear */ - UFCON1 = 0x0; - /* disable the flow control */ - UMCON1= 0x0; - /* Normal,No parity,1 stop,8 bit */ - ULCON1 = 0x3; - /* - * tx=level,rx=edge,disable timeout int.,enable rx error int., - * normal,interrupt or polling - */ - UCON1 = 0x245; - - //UBRD0 = div; - // UBRD0 = 0x500; /* baudrate = 19200bps */ - UBRD1 = 0x1a; - - UTXH1 = 0x2; - URXH1 = 0x1; - - /* output PCLK to UART0/1, PWMTIMER */ - CLKCON |= 0x0D00; - - for (i = 0; i < 100; i++); - - /* install key isr */ - INTSUBMSK &= ~(BIT_SUB_RXD1); - - rt_hw_interrupt_install(INTUART1, rt_key_handler, RT_NULL , "INTUART1"); - rt_hw_interrupt_umask(INTUART1); + int i = 0; + + GPHCON |= 0xa0; + /*PULLUP is enable */ + GPHUP |= 0x0c; + + /* FIFO enable, Tx/Rx FIFO clear */ + UFCON1 = 0x0; + /* disable the flow control */ + UMCON1= 0x0; + /* Normal,No parity,1 stop,8 bit */ + ULCON1 = 0x3; + /* + * tx=level,rx=edge,disable timeout int.,enable rx error int., + * normal,interrupt or polling + */ + UCON1 = 0x245; + + //UBRD0 = div; + // UBRD0 = 0x500; /* baudrate = 19200bps */ + UBRD1 = 0x1a; + + UTXH1 = 0x2; + URXH1 = 0x1; + + /* output PCLK to UART0/1, PWMTIMER */ + CLKCON |= 0x0D00; + + for (i = 0; i < 100; i++); + + /* install key isr */ + INTSUBMSK &= ~(BIT_SUB_RXD1); + + rt_hw_interrupt_install(INTUART1, rt_key_handler, RT_NULL , "INTUART1"); + rt_hw_interrupt_umask(INTUART1); } static rt_err_t rt_key_init(rt_device_t dev) -{ - if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) - { +{ + if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) + { - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_memset(key_device->rx_buffer, 0, - sizeof(key_device->rx_buffer)); - key_device->read_index = key_device->save_index = 0; - } + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_memset(key_device->rx_buffer, 0, + sizeof(key_device->rx_buffer)); + key_device->read_index = key_device->save_index = 0; + } - dev->flag |= RT_DEVICE_FLAG_ACTIVATED; - } + dev->flag |= RT_DEVICE_FLAG_ACTIVATED; + } - return RT_EOK; + return RT_EOK; } static rt_err_t rt_key_open(rt_device_t dev, rt_uint16_t oflag) -{ - return RT_EOK; +{ + return RT_EOK; } static rt_err_t rt_key_close(rt_device_t dev) -{ - return RT_EOK; +{ + return RT_EOK; } static rt_size_t rt_key_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - rt_err_t err_code; - rt_base_t level; - - ptr = buffer; - err_code = RT_EOK; - - /* interrupt mode Rx */ - while (size) - { - if (key_device->read_index != key_device->save_index) - { - *ptr++ = key_device->rx_buffer[key_device->read_index]; - size --; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - key_device->read_index ++; - if (key_device->read_index >= KEY_RX_BUFFER_SIZE) - key_device->read_index = 0; - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } - else - { - /* set error code */ - err_code = -RT_EEMPTY; - break; - } - } - - /* set error code */ - rt_set_errno(err_code); - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + rt_uint8_t* ptr; + rt_err_t err_code; + rt_base_t level; + + ptr = buffer; + err_code = RT_EOK; + + /* interrupt mode Rx */ + while (size) + { + if (key_device->read_index != key_device->save_index) + { + *ptr++ = key_device->rx_buffer[key_device->read_index]; + size --; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + key_device->read_index ++; + if (key_device->read_index >= KEY_RX_BUFFER_SIZE) + key_device->read_index = 0; + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + else + { + /* set error code */ + err_code = -RT_EEMPTY; + break; + } + } + + /* set error code */ + rt_set_errno(err_code); + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; } static rt_err_t rt_key_control(rt_device_t dev, int cmd, void *args) { - return RT_EOK; + return RT_EOK; } #ifdef RT_USING_RTGUI @@ -211,96 +211,96 @@ static int s_key_map[0xff] = {0}; static void rt_keymap_init(void) { - s_key_map[0x1] = RTGUIK_ESCAPE; - s_key_map[0xc] = RTGUIK_MINUS; - s_key_map[0x39] = RTGUIK_SPACE; - s_key_map[0xd] = RTGUIK_KP_EQUALS; - s_key_map[0xe] = RTGUIK_BACKSPACE; - s_key_map[0xf] = RTGUIK_TAB; - s_key_map[0x1c] = RTGUIK_KP_ENTER; - s_key_map[0xb] = RTGUIK_0; - s_key_map[0x2] = RTGUIK_1; - s_key_map[0x3] = RTGUIK_2; - s_key_map[0x4] = RTGUIK_3; - s_key_map[0x5] = RTGUIK_4; - s_key_map[0x6] = RTGUIK_5; - s_key_map[0x7] = RTGUIK_6; - s_key_map[0x8] = RTGUIK_7; - s_key_map[0x9] = RTGUIK_8; - s_key_map[0xa] = RTGUIK_9; - s_key_map[0x3b] = RTGUIK_F1; - s_key_map[0x3c] = RTGUIK_F2; - s_key_map[0x3d] = RTGUIK_F3; - s_key_map[0x3e] = RTGUIK_F4; - s_key_map[0xef] = RTGUIK_F5; - s_key_map[0x40] = RTGUIK_F6; - s_key_map[0x41] = RTGUIK_F7; - s_key_map[0x42] = RTGUIK_F8; - s_key_map[0x43] = RTGUIK_F9; - s_key_map[0x1e] = RTGUIK_a; - s_key_map[0x30] = RTGUIK_b; - s_key_map[0x2c] = RTGUIK_c; - s_key_map[0x20] = RTGUIK_d; - s_key_map[0x12] = RTGUIK_e; - s_key_map[0x21] = RTGUIK_f; - s_key_map[0x22] = RTGUIK_g; - s_key_map[0x23] = RTGUIK_h; - s_key_map[0x17] = RTGUIK_i; - s_key_map[0x24] = RTGUIK_j; - s_key_map[0x25] = RTGUIK_k; - s_key_map[0x26] = RTGUIK_l; - s_key_map[0x32] = RTGUIK_m; - s_key_map[0x31] = RTGUIK_n; - s_key_map[0x18] = RTGUIK_o; - s_key_map[0x19] = RTGUIK_p; - s_key_map[0x10] = RTGUIK_q; - s_key_map[0x13] = RTGUIK_r; - s_key_map[0x1f] = RTGUIK_s; - s_key_map[0x14] = RTGUIK_t; - s_key_map[0x16] = RTGUIK_u; - s_key_map[0x2f] = RTGUIK_v; - s_key_map[0x11] = RTGUIK_w; - s_key_map[0x2d] = RTGUIK_x; - s_key_map[0x15] = RTGUIK_y; - s_key_map[0x2c] = RTGUIK_z; - s_key_map[0x4b] = RTGUIK_LEFT; - s_key_map[0x4d] = RTGUIK_RIGHT; - s_key_map[0x50] = RTGUIK_DOWN; - s_key_map[0x2e] = RTGUIK_DELETE; - s_key_map[0x48] = RTGUIK_UP; -} + s_key_map[0x1] = RTGUIK_ESCAPE; + s_key_map[0xc] = RTGUIK_MINUS; + s_key_map[0x39] = RTGUIK_SPACE; + s_key_map[0xd] = RTGUIK_KP_EQUALS; + s_key_map[0xe] = RTGUIK_BACKSPACE; + s_key_map[0xf] = RTGUIK_TAB; + s_key_map[0x1c] = RTGUIK_KP_ENTER; + s_key_map[0xb] = RTGUIK_0; + s_key_map[0x2] = RTGUIK_1; + s_key_map[0x3] = RTGUIK_2; + s_key_map[0x4] = RTGUIK_3; + s_key_map[0x5] = RTGUIK_4; + s_key_map[0x6] = RTGUIK_5; + s_key_map[0x7] = RTGUIK_6; + s_key_map[0x8] = RTGUIK_7; + s_key_map[0x9] = RTGUIK_8; + s_key_map[0xa] = RTGUIK_9; + s_key_map[0x3b] = RTGUIK_F1; + s_key_map[0x3c] = RTGUIK_F2; + s_key_map[0x3d] = RTGUIK_F3; + s_key_map[0x3e] = RTGUIK_F4; + s_key_map[0xef] = RTGUIK_F5; + s_key_map[0x40] = RTGUIK_F6; + s_key_map[0x41] = RTGUIK_F7; + s_key_map[0x42] = RTGUIK_F8; + s_key_map[0x43] = RTGUIK_F9; + s_key_map[0x1e] = RTGUIK_a; + s_key_map[0x30] = RTGUIK_b; + s_key_map[0x2c] = RTGUIK_c; + s_key_map[0x20] = RTGUIK_d; + s_key_map[0x12] = RTGUIK_e; + s_key_map[0x21] = RTGUIK_f; + s_key_map[0x22] = RTGUIK_g; + s_key_map[0x23] = RTGUIK_h; + s_key_map[0x17] = RTGUIK_i; + s_key_map[0x24] = RTGUIK_j; + s_key_map[0x25] = RTGUIK_k; + s_key_map[0x26] = RTGUIK_l; + s_key_map[0x32] = RTGUIK_m; + s_key_map[0x31] = RTGUIK_n; + s_key_map[0x18] = RTGUIK_o; + s_key_map[0x19] = RTGUIK_p; + s_key_map[0x10] = RTGUIK_q; + s_key_map[0x13] = RTGUIK_r; + s_key_map[0x1f] = RTGUIK_s; + s_key_map[0x14] = RTGUIK_t; + s_key_map[0x16] = RTGUIK_u; + s_key_map[0x2f] = RTGUIK_v; + s_key_map[0x11] = RTGUIK_w; + s_key_map[0x2d] = RTGUIK_x; + s_key_map[0x15] = RTGUIK_y; + s_key_map[0x2c] = RTGUIK_z; + s_key_map[0x4b] = RTGUIK_LEFT; + s_key_map[0x4d] = RTGUIK_RIGHT; + s_key_map[0x50] = RTGUIK_DOWN; + s_key_map[0x2e] = RTGUIK_DELETE; + s_key_map[0x48] = RTGUIK_UP; +} static rt_err_t rtgui_key_rx(rt_device_t dev, rt_size_t size) { - struct rtgui_event_kbd kbd_event; - char key_value; - - while(rt_device_read(dev, 0, &key_value, 1) == 1) - { - /* init keyboard event */ - RTGUI_EVENT_KBD_INIT(&kbd_event); - kbd_event.mod = RTGUI_KMOD_NONE; - kbd_event.unicode = 0; - kbd_event.key = RTGUIK_UNKNOWN; - - if(key_value & 0x80) - { - kbd_event.type = RTGUI_KEYUP; - } - else - { - kbd_event.type = RTGUI_KEYDOWN; - } - - kbd_event.key = s_key_map[key_value & 0x7F]; - } - if (kbd_event.key != RTGUIK_UNKNOWN) - { - /* post down event */ - rtgui_server_post_event(&(kbd_event.parent), sizeof(kbd_event)); - } - - return RT_EOK; + struct rtgui_event_kbd kbd_event; + char key_value; + + while(rt_device_read(dev, 0, &key_value, 1) == 1) + { + /* init keyboard event */ + RTGUI_EVENT_KBD_INIT(&kbd_event); + kbd_event.mod = RTGUI_KMOD_NONE; + kbd_event.unicode = 0; + kbd_event.key = RTGUIK_UNKNOWN; + + if(key_value & 0x80) + { + kbd_event.type = RTGUI_KEYUP; + } + else + { + kbd_event.type = RTGUI_KEYDOWN; + } + + kbd_event.key = s_key_map[key_value & 0x7F]; + } + if (kbd_event.key != RTGUIK_UNKNOWN) + { + /* post down event */ + rtgui_server_post_event(&(kbd_event.parent), sizeof(kbd_event)); + } + + return RT_EOK; } #endif @@ -310,33 +310,33 @@ static rt_err_t rtgui_key_rx(rt_device_t dev, rt_size_t size) */ void rt_hw_key_init(void) { - /* hardware init */ - key_init(); - - key_device = (struct rt_key_device*)rt_malloc (sizeof(struct rt_key_device)); - if (key_device == RT_NULL) return; /* no memory yet */ - - /* clear device structure */ - rt_memset(&(key_device->parent), 0, sizeof(struct rt_device)); - - key_device->parent.type = RT_Device_Class_Char; - key_device->parent.tx_complete = RT_NULL; - key_device->parent.init = rt_key_init; - key_device->parent.open = rt_key_open; - key_device->parent.close = rt_key_close; - key_device->parent.read = rt_key_read; - key_device->parent.write = RT_NULL; - key_device->parent.control = rt_key_control; - key_device->parent.user_data = RT_NULL; + /* hardware init */ + key_init(); + + key_device = (struct rt_key_device*)rt_malloc (sizeof(struct rt_key_device)); + if (key_device == RT_NULL) return; /* no memory yet */ + + /* clear device structure */ + rt_memset(&(key_device->parent), 0, sizeof(struct rt_device)); + + key_device->parent.type = RT_Device_Class_Char; + key_device->parent.tx_complete = RT_NULL; + key_device->parent.init = rt_key_init; + key_device->parent.open = rt_key_open; + key_device->parent.close = rt_key_close; + key_device->parent.read = rt_key_read; + key_device->parent.write = RT_NULL; + key_device->parent.control = rt_key_control; + key_device->parent.user_data = RT_NULL; #ifdef RT_USING_RTGUI - key_device->parent.rx_indicate = rtgui_key_rx; + key_device->parent.rx_indicate = rtgui_key_rx; - /* init keymap */ - rt_keymap_init(); + /* init keymap */ + rt_keymap_init(); #endif - /* register key device to RT-Thread */ - rt_device_register(&(key_device->parent), "key", RT_DEVICE_FLAG_RDONLY | RT_DEVICE_FLAG_INT_RX); + /* register key device to RT-Thread */ + rt_device_register(&(key_device->parent), "key", RT_DEVICE_FLAG_RDONLY | RT_DEVICE_FLAG_INT_RX); } diff --git a/bsp/mini2440/drivers/lcd_a70.c b/bsp/mini2440/drivers/lcd_a70.c index 4ce787cbcc..a6b92f69e5 100644 --- a/bsp/mini2440/drivers/lcd_a70.c +++ b/bsp/mini2440/drivers/lcd_a70.c @@ -31,81 +31,81 @@ #define SCR_XSIZE LCD_WIDTH #define SCR_YSIZE LCD_HEIGHT -#define RT_HW_LCD_WIDTH LCD_WIDTH -#define RT_HW_LCD_HEIGHT LCD_HEIGHT +#define RT_HW_LCD_WIDTH LCD_WIDTH +#define RT_HW_LCD_HEIGHT LCD_HEIGHT -#define MVAL (13) -#define MVAL_USED (0) //0=each frame 1=rate by MVAL -#define INVVDEN (1) //0=normal 1=inverted -#define BSWP (0) //Byte swap control -#define HWSWP (1) //Half word swap control +#define MVAL (13) +#define MVAL_USED (0) //0=each frame 1=rate by MVAL +#define INVVDEN (1) //0=normal 1=inverted +#define BSWP (0) //Byte swap control +#define HWSWP (1) //Half word swap control -#define GPB1_TO_OUT() (GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004) -#define GPB1_TO_1() (GPBDAT |= 0x0002) -#define GPB1_TO_0() (GPBDAT &= 0xfffd) +#define GPB1_TO_OUT() (GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004) +#define GPB1_TO_1() (GPBDAT |= 0x0002) +#define GPB1_TO_0() (GPBDAT &= 0xfffd) #define S3C2410_LCDCON1_CLKVAL(x) ((x) << 8) -#define S3C2410_LCDCON1_MMODE (1<<7) -#define S3C2410_LCDCON1_DSCAN4 (0<<5) -#define S3C2410_LCDCON1_STN4 (1<<5) -#define S3C2410_LCDCON1_STN8 (2<<5) -#define S3C2410_LCDCON1_TFT (3<<5) +#define S3C2410_LCDCON1_MMODE (1<<7) +#define S3C2410_LCDCON1_DSCAN4 (0<<5) +#define S3C2410_LCDCON1_STN4 (1<<5) +#define S3C2410_LCDCON1_STN8 (2<<5) +#define S3C2410_LCDCON1_TFT (3<<5) -#define S3C2410_LCDCON1_STN1BPP (0<<1) +#define S3C2410_LCDCON1_STN1BPP (0<<1) #define S3C2410_LCDCON1_STN2GREY (1<<1) #define S3C2410_LCDCON1_STN4GREY (2<<1) -#define S3C2410_LCDCON1_STN8BPP (3<<1) +#define S3C2410_LCDCON1_STN8BPP (3<<1) #define S3C2410_LCDCON1_STN12BPP (4<<1) -#define S3C2410_LCDCON1_TFT1BPP (8<<1) -#define S3C2410_LCDCON1_TFT2BPP (9<<1) -#define S3C2410_LCDCON1_TFT4BPP (10<<1) -#define S3C2410_LCDCON1_TFT8BPP (11<<1) +#define S3C2410_LCDCON1_TFT1BPP (8<<1) +#define S3C2410_LCDCON1_TFT2BPP (9<<1) +#define S3C2410_LCDCON1_TFT4BPP (10<<1) +#define S3C2410_LCDCON1_TFT8BPP (11<<1) #define S3C2410_LCDCON1_TFT16BPP (12<<1) #define S3C2410_LCDCON1_TFT24BPP (13<<1) -#define S3C2410_LCDCON1_ENVID (1) +#define S3C2410_LCDCON1_ENVID (1) #define S3C2410_LCDCON1_MODEMASK 0x1E -#define S3C2410_LCDCON2_VBPD(x) ((x) << 24) +#define S3C2410_LCDCON2_VBPD(x) ((x) << 24) #define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14) -#define S3C2410_LCDCON2_VFPD(x) ((x) << 6) -#define S3C2410_LCDCON2_VSPW(x) ((x) << 0) +#define S3C2410_LCDCON2_VFPD(x) ((x) << 6) +#define S3C2410_LCDCON2_VSPW(x) ((x) << 0) #define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF) #define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >> 6) & 0xFF) #define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >> 0) & 0x3F) -#define S3C2410_LCDCON3_HBPD(x) ((x) << 19) -#define S3C2410_LCDCON3_WDLY(x) ((x) << 19) +#define S3C2410_LCDCON3_HBPD(x) ((x) << 19) +#define S3C2410_LCDCON3_WDLY(x) ((x) << 19) #define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8) -#define S3C2410_LCDCON3_HFPD(x) ((x) << 0) +#define S3C2410_LCDCON3_HFPD(x) ((x) << 0) #define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0) #define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F) #define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF) -#define S3C2410_LCDCON4_MVAL(x) ((x) << 8) -#define S3C2410_LCDCON4_HSPW(x) ((x) << 0) -#define S3C2410_LCDCON4_WLH(x) ((x) << 0) +#define S3C2410_LCDCON4_MVAL(x) ((x) << 8) +#define S3C2410_LCDCON4_HSPW(x) ((x) << 0) +#define S3C2410_LCDCON4_WLH(x) ((x) << 0) #define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >> 0) & 0xFF) -#define S3C2410_LCDCON5_BPP24BL (1<<12) -#define S3C2410_LCDCON5_FRM565 (1<<11) -#define S3C2410_LCDCON5_INVVCLK (1<<10) +#define S3C2410_LCDCON5_BPP24BL (1<<12) +#define S3C2410_LCDCON5_FRM565 (1<<11) +#define S3C2410_LCDCON5_INVVCLK (1<<10) #define S3C2410_LCDCON5_INVVLINE (1<<9) #define S3C2410_LCDCON5_INVVFRAME (1<<8) -#define S3C2410_LCDCON5_INVVD (1<<7) -#define S3C2410_LCDCON5_INVVDEN (1<<6) +#define S3C2410_LCDCON5_INVVD (1<<7) +#define S3C2410_LCDCON5_INVVDEN (1<<6) #define S3C2410_LCDCON5_INVPWREN (1<<5) -#define S3C2410_LCDCON5_INVLEND (1<<4) -#define S3C2410_LCDCON5_PWREN (1<<3) -#define S3C2410_LCDCON5_ENLEND (1<<2) -#define S3C2410_LCDCON5_BSWP (1<<1) -#define S3C2410_LCDCON5_HWSWP (1<<0) -#define S3C2410_LCDINT_FRSYNC (1<<1) +#define S3C2410_LCDCON5_INVLEND (1<<4) +#define S3C2410_LCDCON5_PWREN (1<<3) +#define S3C2410_LCDCON5_ENLEND (1<<2) +#define S3C2410_LCDCON5_BSWP (1<<1) +#define S3C2410_LCDCON5_HWSWP (1<<0) +#define S3C2410_LCDINT_FRSYNC (1<<1) static volatile rt_uint16_t _rt_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH]; //static volatile rt_uint16_t _rt_hw_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH]; @@ -124,121 +124,121 @@ static void lcd_power_enable(int invpwren, int pwren) static void lcd_envid_on_off(int onoff) { - if(onoff==1) - /*ENVID=ON*/ - LCDCON1|=1; - else - /*ENVID Off*/ - LCDCON1 =LCDCON1 & 0x3fffe; + if(onoff==1) + /*ENVID=ON*/ + LCDCON1|=1; + else + /*ENVID Off*/ + LCDCON1 =LCDCON1 & 0x3fffe; } //********************** BOARD LCD backlight **************************** static void LcdBkLtSet(rt_uint32_t HiRatio) { -#define FREQ_PWM1 1000 - if(!HiRatio) - { - GPBCON = GPBCON & (~(3<<2)) | (1<<2) ; //GPB1设置为output - GPBDAT &= ~(1<<1); - return; - } - GPBCON = GPBCON & (~(3<<2)) | (2<<2) ; +#define FREQ_PWM1 1000 + if(!HiRatio) + { + GPBCON = GPBCON & (~(3<<2)) | (1<<2) ; //GPB1设置为output + GPBDAT &= ~(1<<1); + return; + } + GPBCON = GPBCON & (~(3<<2)) | (2<<2) ; - if( HiRatio > 100 ) HiRatio = 100 ; + if( HiRatio > 100 ) HiRatio = 100 ; - TCON = TCON & (~(0xf<<8)) ; // clear manual update bit, stop Timer1 + TCON = TCON & (~(0xf<<8)) ; // clear manual update bit, stop Timer1 - TCFG0 &= 0xffffff00; // set Timer 0&1 prescaler 0 - TCFG0 |= 15; //prescaler = 15+1 + TCFG0 &= 0xffffff00; // set Timer 0&1 prescaler 0 + TCFG0 |= 15; //prescaler = 15+1 - TCFG1 &= 0xffffff0f; // set Timer 1 MUX 1/16 - TCFG1 |= 0x00000030; // set Timer 1 MUX 1/16 + TCFG1 &= 0xffffff0f; // set Timer 1 MUX 1/16 + TCFG1 |= 0x00000030; // set Timer 1 MUX 1/16 - TCNTB1 = ( 100000000>>8 )/FREQ_PWM1; //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low - TCMPB1 = ( TCNTB1*(100-HiRatio))/100 ; //if set inverter on, when TCNT2<=TCMP2, TOUT is low, TCNT2>TCMP2, TOUT is high + TCNTB1 = ( 100000000>>8 )/FREQ_PWM1; //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low + TCMPB1 = ( TCNTB1*(100-HiRatio))/100 ; //if set inverter on, when TCNT2<=TCMP2, TOUT is low, TCNT2>TCMP2, TOUT is high - TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ; - TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ; + TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ; + TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ; } /* RT-Thread Device Interface */ static rt_err_t rt_lcd_init (rt_device_t dev) -{ - GPB1_TO_OUT(); - GPB1_TO_1(); +{ + GPB1_TO_OUT(); + GPB1_TO_1(); - GPCUP = 0x00000000; - GPCCON = 0xaaaa02a9; + GPCUP = 0x00000000; + GPCCON = 0xaaaa02a9; - GPDUP = 0x00000000; - GPDCON = 0xaaaaaaaa; + GPDUP = 0x00000000; + GPDCON = 0xaaaaaaaa; -#define M5D(n) ((n)&0x1fffff) +#define M5D(n) ((n)&0x1fffff) #define LCD_ADDR ((rt_uint32_t)_rt_framebuffer) - LCDCON1 = (LCD_PIXCLOCK << 8) | (3 << 5) | (12 << 1); - LCDCON2 = (LCD_UPPER_MARGIN << 24) | ((LCD_HEIGHT - 1) << 14) | (LCD_LOWER_MARGIN << 6) | (LCD_VSYNC_LEN << 0); - LCDCON3 = (LCD_RIGHT_MARGIN << 19) | ((LCD_WIDTH - 1) << 8) | (LCD_LEFT_MARGIN << 0); - LCDCON4 = (13 << 8) | (LCD_HSYNC_LEN << 0); + LCDCON1 = (LCD_PIXCLOCK << 8) | (3 << 5) | (12 << 1); + LCDCON2 = (LCD_UPPER_MARGIN << 24) | ((LCD_HEIGHT - 1) << 14) | (LCD_LOWER_MARGIN << 6) | (LCD_VSYNC_LEN << 0); + LCDCON3 = (LCD_RIGHT_MARGIN << 19) | ((LCD_WIDTH - 1) << 8) | (LCD_LEFT_MARGIN << 0); + LCDCON4 = (13 << 8) | (LCD_HSYNC_LEN << 0); #if !defined(LCD_CON5) #define LCD_CON5 ((1<<11) | (1 << 9) | (1 << 8) | (1 << 3) | (1 << 0)) #endif - LCDCON5 = LCD_CON5; + LCDCON5 = LCD_CON5; - LCDSADDR1 = ((LCD_ADDR >> 22) << 21) | ((M5D(LCD_ADDR >> 1)) << 0); - LCDSADDR2 = M5D((LCD_ADDR + LCD_WIDTH * LCD_HEIGHT * 2) >> 1); - LCDSADDR3 = LCD_WIDTH; + LCDSADDR1 = ((LCD_ADDR >> 22) << 21) | ((M5D(LCD_ADDR >> 1)) << 0); + LCDSADDR2 = M5D((LCD_ADDR + LCD_WIDTH * LCD_HEIGHT * 2) >> 1); + LCDSADDR3 = LCD_WIDTH; - LCDINTMSK |= (3); - LPCSEL &= (~7) ; - TPAL=0; + LCDINTMSK |= (3); + LPCSEL &= (~7) ; + TPAL=0; - LcdBkLtSet(70) ; - lcd_power_enable(0, 1); - lcd_envid_on_off(1); + LcdBkLtSet(70) ; + lcd_power_enable(0, 1); + lcd_envid_on_off(1); - return RT_EOK; + return RT_EOK; } static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args) { - switch (cmd) - { - case RTGRAPHIC_CTRL_RECT_UPDATE: - break; - case RTGRAPHIC_CTRL_POWERON: - break; - case RTGRAPHIC_CTRL_POWEROFF: - break; - case RTGRAPHIC_CTRL_GET_INFO: - rt_memcpy(args, &_lcd_info, sizeof(_lcd_info)); - break; - case RTGRAPHIC_CTRL_SET_MODE: - break; - } - - return RT_EOK; + switch (cmd) + { + case RTGRAPHIC_CTRL_RECT_UPDATE: + break; + case RTGRAPHIC_CTRL_POWERON: + break; + case RTGRAPHIC_CTRL_POWEROFF: + break; + case RTGRAPHIC_CTRL_GET_INFO: + rt_memcpy(args, &_lcd_info, sizeof(_lcd_info)); + break; + case RTGRAPHIC_CTRL_SET_MODE: + break; + } + + return RT_EOK; } void rt_hw_lcd_init(void) { - rt_device_t lcd = rt_malloc(sizeof(struct rt_device)); - if (lcd == RT_NULL) return; /* no memory yet */ - - _lcd_info.bits_per_pixel = 16; - _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P; - _lcd_info.framebuffer = (void*)_rt_framebuffer; - _lcd_info.width = LCD_WIDTH; - _lcd_info.height = LCD_HEIGHT; - - /* init device structure */ - lcd->type = RT_Device_Class_Unknown; - lcd->init = rt_lcd_init; - lcd->open = RT_NULL; - lcd->close = RT_NULL; - lcd->control = rt_lcd_control; - lcd->user_data = (void*)&_lcd_info; - - /* register lcd device to RT-Thread */ - rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR); + rt_device_t lcd = rt_malloc(sizeof(struct rt_device)); + if (lcd == RT_NULL) return; /* no memory yet */ + + _lcd_info.bits_per_pixel = 16; + _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P; + _lcd_info.framebuffer = (void*)_rt_framebuffer; + _lcd_info.width = LCD_WIDTH; + _lcd_info.height = LCD_HEIGHT; + + /* init device structure */ + lcd->type = RT_Device_Class_Unknown; + lcd->init = rt_lcd_init; + lcd->open = RT_NULL; + lcd->close = RT_NULL; + lcd->control = rt_lcd_control; + lcd->user_data = (void*)&_lcd_info; + + /* register lcd device to RT-Thread */ + rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR); } diff --git a/bsp/mini2440/drivers/lcd_n35.c b/bsp/mini2440/drivers/lcd_n35.c index 25881b0f14..5abf5f4f21 100644 --- a/bsp/mini2440/drivers/lcd_n35.c +++ b/bsp/mini2440/drivers/lcd_n35.c @@ -31,82 +31,82 @@ #define SCR_XSIZE LCD_WIDTH #define SCR_YSIZE LCD_HEIGHT -#define RT_HW_LCD_WIDTH LCD_WIDTH -#define RT_HW_LCD_HEIGHT LCD_HEIGHT +#define RT_HW_LCD_WIDTH LCD_WIDTH +#define RT_HW_LCD_HEIGHT LCD_HEIGHT -#define MVAL (13) -#define MVAL_USED (0) //0=each frame 1=rate by MVAL -#define INVVDEN (1) //0=normal 1=inverted -#define BSWP (0) //Byte swap control -#define HWSWP (1) //Half word swap control +#define MVAL (13) +#define MVAL_USED (0) //0=each frame 1=rate by MVAL +#define INVVDEN (1) //0=normal 1=inverted +#define BSWP (0) //Byte swap control +#define HWSWP (1) //Half word swap control -#define GPB1_TO_OUT() (GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004) -#define GPB1_TO_1() (GPBDAT |= 0x0002) -#define GPB1_TO_0() (GPBDAT &= 0xfffd) +#define GPB1_TO_OUT() (GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004) +#define GPB1_TO_1() (GPBDAT |= 0x0002) +#define GPB1_TO_0() (GPBDAT &= 0xfffd) #define S3C2410_LCDCON1_CLKVAL(x) ((x) << 8) -#define S3C2410_LCDCON1_MMODE (1<<7) -#define S3C2410_LCDCON1_DSCAN4 (0<<5) -#define S3C2410_LCDCON1_STN4 (1<<5) -#define S3C2410_LCDCON1_STN8 (2<<5) -#define S3C2410_LCDCON1_TFT (3<<5) +#define S3C2410_LCDCON1_MMODE (1<<7) +#define S3C2410_LCDCON1_DSCAN4 (0<<5) +#define S3C2410_LCDCON1_STN4 (1<<5) +#define S3C2410_LCDCON1_STN8 (2<<5) +#define S3C2410_LCDCON1_TFT (3<<5) -#define S3C2410_LCDCON1_STN1BPP (0<<1) +#define S3C2410_LCDCON1_STN1BPP (0<<1) #define S3C2410_LCDCON1_STN2GREY (1<<1) #define S3C2410_LCDCON1_STN4GREY (2<<1) -#define S3C2410_LCDCON1_STN8BPP (3<<1) +#define S3C2410_LCDCON1_STN8BPP (3<<1) #define S3C2410_LCDCON1_STN12BPP (4<<1) -#define S3C2410_LCDCON1_TFT1BPP (8<<1) -#define S3C2410_LCDCON1_TFT2BPP (9<<1) -#define S3C2410_LCDCON1_TFT4BPP (10<<1) -#define S3C2410_LCDCON1_TFT8BPP (11<<1) +#define S3C2410_LCDCON1_TFT1BPP (8<<1) +#define S3C2410_LCDCON1_TFT2BPP (9<<1) +#define S3C2410_LCDCON1_TFT4BPP (10<<1) +#define S3C2410_LCDCON1_TFT8BPP (11<<1) #define S3C2410_LCDCON1_TFT16BPP (12<<1) #define S3C2410_LCDCON1_TFT24BPP (13<<1) -#define S3C2410_LCDCON1_ENVID (1) +#define S3C2410_LCDCON1_ENVID (1) #define S3C2410_LCDCON1_MODEMASK 0x1E -#define S3C2410_LCDCON2_VBPD(x) ((x) << 24) +#define S3C2410_LCDCON2_VBPD(x) ((x) << 24) #define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14) -#define S3C2410_LCDCON2_VFPD(x) ((x) << 6) -#define S3C2410_LCDCON2_VSPW(x) ((x) << 0) +#define S3C2410_LCDCON2_VFPD(x) ((x) << 6) +#define S3C2410_LCDCON2_VSPW(x) ((x) << 0) #define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF) #define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >> 6) & 0xFF) #define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >> 0) & 0x3F) -#define S3C2410_LCDCON3_HBPD(x) ((x) << 19) -#define S3C2410_LCDCON3_WDLY(x) ((x) << 19) +#define S3C2410_LCDCON3_HBPD(x) ((x) << 19) +#define S3C2410_LCDCON3_WDLY(x) ((x) << 19) #define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8) -#define S3C2410_LCDCON3_HFPD(x) ((x) << 0) +#define S3C2410_LCDCON3_HFPD(x) ((x) << 0) #define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0) #define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F) #define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF) -#define S3C2410_LCDCON4_MVAL(x) ((x) << 8) -#define S3C2410_LCDCON4_HSPW(x) ((x) << 0) -#define S3C2410_LCDCON4_WLH(x) ((x) << 0) +#define S3C2410_LCDCON4_MVAL(x) ((x) << 8) +#define S3C2410_LCDCON4_HSPW(x) ((x) << 0) +#define S3C2410_LCDCON4_WLH(x) ((x) << 0) #define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >> 0) & 0xFF) -#define S3C2410_LCDCON5_BPP24BL (1<<12) -#define S3C2410_LCDCON5_FRM565 (1<<11) -#define S3C2410_LCDCON5_INVVCLK (1<<10) +#define S3C2410_LCDCON5_BPP24BL (1<<12) +#define S3C2410_LCDCON5_FRM565 (1<<11) +#define S3C2410_LCDCON5_INVVCLK (1<<10) #define S3C2410_LCDCON5_INVVLINE (1<<9) #define S3C2410_LCDCON5_INVVFRAME (1<<8) -#define S3C2410_LCDCON5_INVVD (1<<7) -#define S3C2410_LCDCON5_INVVDEN (1<<6) +#define S3C2410_LCDCON5_INVVD (1<<7) +#define S3C2410_LCDCON5_INVVDEN (1<<6) #define S3C2410_LCDCON5_INVPWREN (1<<5) -#define S3C2410_LCDCON5_INVLEND (1<<4) -#define S3C2410_LCDCON5_PWREN (1<<3) -#define S3C2410_LCDCON5_ENLEND (1<<2) -#define S3C2410_LCDCON5_BSWP (1<<1) -#define S3C2410_LCDCON5_HWSWP (1<<0) +#define S3C2410_LCDCON5_INVLEND (1<<4) +#define S3C2410_LCDCON5_PWREN (1<<3) +#define S3C2410_LCDCON5_ENLEND (1<<2) +#define S3C2410_LCDCON5_BSWP (1<<1) +#define S3C2410_LCDCON5_HWSWP (1<<0) -#define S3C2410_LCDINT_FRSYNC (1<<1) +#define S3C2410_LCDINT_FRSYNC (1<<1) static volatile rt_uint16_t _rt_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH]; //static volatile rt_uint16_t _rt_hw_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH]; @@ -125,61 +125,61 @@ static void lcd_power_enable(int invpwren, int pwren) static void lcd_envid_on_off(int onoff) { - if(onoff==1) - /*ENVID=ON*/ - LCDCON1|=1; - else - /*ENVID Off*/ - LCDCON1 =LCDCON1 & 0x3fffe; + if(onoff==1) + /*ENVID=ON*/ + LCDCON1|=1; + else + /*ENVID Off*/ + LCDCON1 =LCDCON1 & 0x3fffe; } //********************** BOARD LCD backlight **************************** static void LcdBkLtSet(rt_uint32_t HiRatio) { -#define FREQ_PWM1 1000 - if(!HiRatio) - { - GPBCON = GPBCON & (~(3<<2)) | (1<<2) ; //GPB1设置为output - GPBDAT &= ~(1<<1); - return; - } - GPBCON = GPBCON & (~(3<<2)) | (2<<2) ; +#define FREQ_PWM1 1000 + if(!HiRatio) + { + GPBCON = GPBCON & (~(3<<2)) | (1<<2) ; //GPB1设置为output + GPBDAT &= ~(1<<1); + return; + } + GPBCON = GPBCON & (~(3<<2)) | (2<<2) ; - if( HiRatio > 100 ) HiRatio = 100 ; + if( HiRatio > 100 ) HiRatio = 100 ; - TCON = TCON & (~(0xf<<8)) ; // clear manual update bit, stop Timer1 + TCON = TCON & (~(0xf<<8)) ; // clear manual update bit, stop Timer1 - TCFG0 &= 0xffffff00; // set Timer 0&1 prescaler 0 - TCFG0 |= 15; //prescaler = 15+1 + TCFG0 &= 0xffffff00; // set Timer 0&1 prescaler 0 + TCFG0 |= 15; //prescaler = 15+1 - TCFG1 &= 0xffffff0f; // set Timer 1 MUX 1/16 - TCFG1 |= 0x00000030; // set Timer 1 MUX 1/16 + TCFG1 &= 0xffffff0f; // set Timer 1 MUX 1/16 + TCFG1 |= 0x00000030; // set Timer 1 MUX 1/16 - TCNTB1 = ( 100000000>>8 )/FREQ_PWM1; //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low - TCMPB1 = ( TCNTB1*(100-HiRatio))/100 ; //if set inverter on, when TCNT2<=TCMP2, TOUT is low, TCNT2>TCMP2, TOUT is high + TCNTB1 = ( 100000000>>8 )/FREQ_PWM1; //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low + TCMPB1 = ( TCNTB1*(100-HiRatio))/100 ; //if set inverter on, when TCNT2<=TCMP2, TOUT is low, TCNT2>TCMP2, TOUT is high - TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ; - TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ; + TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ; + TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ; } /* RT-Thread Device Interface */ static rt_err_t rt_lcd_init (rt_device_t dev) -{ - GPB1_TO_OUT(); - GPB1_TO_1(); +{ + GPB1_TO_OUT(); + GPB1_TO_1(); - GPCUP = 0x00000000; - GPCCON = 0xaaaa02a9; + GPCUP = 0x00000000; + GPCCON = 0xaaaa02a9; - GPDUP = 0x00000000; - GPDCON = 0xaaaaaaaa; + GPDUP = 0x00000000; + GPDCON = 0xaaaaaaaa; -#define M5D(n) ((n)&0x1fffff) +#define M5D(n) ((n)&0x1fffff) #define LCD_ADDR ((rt_uint32_t)_rt_framebuffer) - LCDCON1 = (LCD_PIXCLOCK << 8) | (3 << 5) | (12 << 1); - LCDCON2 = (LCD_UPPER_MARGIN << 24) | ((LCD_HEIGHT - 1) << 14) | (LCD_LOWER_MARGIN << 6) | (LCD_VSYNC_LEN << 0); - LCDCON3 = (LCD_RIGHT_MARGIN << 19) | ((LCD_WIDTH - 1) << 8) | (LCD_LEFT_MARGIN << 0); - LCDCON4 = (13 << 8) | (LCD_HSYNC_LEN << 0); + LCDCON1 = (LCD_PIXCLOCK << 8) | (3 << 5) | (12 << 1); + LCDCON2 = (LCD_UPPER_MARGIN << 24) | ((LCD_HEIGHT - 1) << 14) | (LCD_LOWER_MARGIN << 6) | (LCD_VSYNC_LEN << 0); + LCDCON3 = (LCD_RIGHT_MARGIN << 19) | ((LCD_WIDTH - 1) << 8) | (LCD_LEFT_MARGIN << 0); + LCDCON4 = (13 << 8) | (LCD_HSYNC_LEN << 0); #if !defined(LCD_CON5) #define LCD_CON5 ((1<<11) | (1 << 9) | (1 << 8) | (1 << 3) | (1 << 0)) #endif @@ -189,57 +189,57 @@ static rt_err_t rt_lcd_init (rt_device_t dev) LCDSADDR2 = M5D((LCD_ADDR + LCD_WIDTH * LCD_HEIGHT * 2) >> 1); LCDSADDR3 = LCD_WIDTH; - LCDINTMSK |= (3); - LPCSEL &= (~7) ; - TPAL=0; + LCDINTMSK |= (3); + LPCSEL &= (~7) ; + TPAL=0; - LcdBkLtSet(70) ; - lcd_power_enable(0, 1); - lcd_envid_on_off(1); + LcdBkLtSet(70) ; + lcd_power_enable(0, 1); + lcd_envid_on_off(1); - return RT_EOK; + return RT_EOK; } static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args) { - switch (cmd) - { - case RTGRAPHIC_CTRL_RECT_UPDATE: - break; - case RTGRAPHIC_CTRL_POWERON: - break; - case RTGRAPHIC_CTRL_POWEROFF: - break; - case RTGRAPHIC_CTRL_GET_INFO: - rt_memcpy(args, &_lcd_info, sizeof(_lcd_info)); - break; - case RTGRAPHIC_CTRL_SET_MODE: - break; - } - - return RT_EOK; + switch (cmd) + { + case RTGRAPHIC_CTRL_RECT_UPDATE: + break; + case RTGRAPHIC_CTRL_POWERON: + break; + case RTGRAPHIC_CTRL_POWEROFF: + break; + case RTGRAPHIC_CTRL_GET_INFO: + rt_memcpy(args, &_lcd_info, sizeof(_lcd_info)); + break; + case RTGRAPHIC_CTRL_SET_MODE: + break; + } + + return RT_EOK; } void rt_hw_lcd_init(void) { - rt_device_t lcd = rt_malloc(sizeof(struct rt_device)); - if (lcd == RT_NULL) return; /* no memory yet */ - - _lcd_info.bits_per_pixel = 16; - _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P; - _lcd_info.framebuffer = (void*)_rt_framebuffer; - _lcd_info.width = LCD_WIDTH; - _lcd_info.height = LCD_HEIGHT; - - /* init device structure */ - lcd->type = RT_Device_Class_Unknown; - lcd->init = rt_lcd_init; - lcd->open = RT_NULL; - lcd->close = RT_NULL; - lcd->control = rt_lcd_control; - lcd->user_data = (void*)&_lcd_info; - - /* register lcd device to RT-Thread */ - rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR); + rt_device_t lcd = rt_malloc(sizeof(struct rt_device)); + if (lcd == RT_NULL) return; /* no memory yet */ + + _lcd_info.bits_per_pixel = 16; + _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P; + _lcd_info.framebuffer = (void*)_rt_framebuffer; + _lcd_info.width = LCD_WIDTH; + _lcd_info.height = LCD_HEIGHT; + + /* init device structure */ + lcd->type = RT_Device_Class_Unknown; + lcd->init = rt_lcd_init; + lcd->open = RT_NULL; + lcd->close = RT_NULL; + lcd->control = rt_lcd_control; + lcd->user_data = (void*)&_lcd_info; + + /* register lcd device to RT-Thread */ + rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR); } diff --git a/bsp/mini2440/drivers/lcd_t35.c b/bsp/mini2440/drivers/lcd_t35.c index 51e038ec8b..5a19e3f68a 100644 --- a/bsp/mini2440/drivers/lcd_t35.c +++ b/bsp/mini2440/drivers/lcd_t35.c @@ -31,82 +31,82 @@ #define SCR_XSIZE LCD_WIDTH #define SCR_YSIZE LCD_HEIGHT -#define RT_HW_LCD_WIDTH LCD_WIDTH -#define RT_HW_LCD_HEIGHT LCD_HEIGHT +#define RT_HW_LCD_WIDTH LCD_WIDTH +#define RT_HW_LCD_HEIGHT LCD_HEIGHT -#define MVAL (13) -#define MVAL_USED (0) //0=each frame 1=rate by MVAL -#define INVVDEN (1) //0=normal 1=inverted -#define BSWP (0) //Byte swap control -#define HWSWP (1) //Half word swap control +#define MVAL (13) +#define MVAL_USED (0) //0=each frame 1=rate by MVAL +#define INVVDEN (1) //0=normal 1=inverted +#define BSWP (0) //Byte swap control +#define HWSWP (1) //Half word swap control -#define GPB1_TO_OUT() (GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004) -#define GPB1_TO_1() (GPBDAT |= 0x0002) -#define GPB1_TO_0() (GPBDAT &= 0xfffd) +#define GPB1_TO_OUT() (GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004) +#define GPB1_TO_1() (GPBDAT |= 0x0002) +#define GPB1_TO_0() (GPBDAT &= 0xfffd) #define S3C2410_LCDCON1_CLKVAL(x) ((x) << 8) -#define S3C2410_LCDCON1_MMODE (1<<7) -#define S3C2410_LCDCON1_DSCAN4 (0<<5) -#define S3C2410_LCDCON1_STN4 (1<<5) -#define S3C2410_LCDCON1_STN8 (2<<5) -#define S3C2410_LCDCON1_TFT (3<<5) +#define S3C2410_LCDCON1_MMODE (1<<7) +#define S3C2410_LCDCON1_DSCAN4 (0<<5) +#define S3C2410_LCDCON1_STN4 (1<<5) +#define S3C2410_LCDCON1_STN8 (2<<5) +#define S3C2410_LCDCON1_TFT (3<<5) -#define S3C2410_LCDCON1_STN1BPP (0<<1) +#define S3C2410_LCDCON1_STN1BPP (0<<1) #define S3C2410_LCDCON1_STN2GREY (1<<1) #define S3C2410_LCDCON1_STN4GREY (2<<1) -#define S3C2410_LCDCON1_STN8BPP (3<<1) +#define S3C2410_LCDCON1_STN8BPP (3<<1) #define S3C2410_LCDCON1_STN12BPP (4<<1) -#define S3C2410_LCDCON1_TFT1BPP (8<<1) -#define S3C2410_LCDCON1_TFT2BPP (9<<1) -#define S3C2410_LCDCON1_TFT4BPP (10<<1) -#define S3C2410_LCDCON1_TFT8BPP (11<<1) +#define S3C2410_LCDCON1_TFT1BPP (8<<1) +#define S3C2410_LCDCON1_TFT2BPP (9<<1) +#define S3C2410_LCDCON1_TFT4BPP (10<<1) +#define S3C2410_LCDCON1_TFT8BPP (11<<1) #define S3C2410_LCDCON1_TFT16BPP (12<<1) #define S3C2410_LCDCON1_TFT24BPP (13<<1) -#define S3C2410_LCDCON1_ENVID (1) +#define S3C2410_LCDCON1_ENVID (1) #define S3C2410_LCDCON1_MODEMASK 0x1E -#define S3C2410_LCDCON2_VBPD(x) ((x) << 24) +#define S3C2410_LCDCON2_VBPD(x) ((x) << 24) #define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14) -#define S3C2410_LCDCON2_VFPD(x) ((x) << 6) -#define S3C2410_LCDCON2_VSPW(x) ((x) << 0) +#define S3C2410_LCDCON2_VFPD(x) ((x) << 6) +#define S3C2410_LCDCON2_VSPW(x) ((x) << 0) #define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF) #define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >> 6) & 0xFF) #define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >> 0) & 0x3F) -#define S3C2410_LCDCON3_HBPD(x) ((x) << 19) -#define S3C2410_LCDCON3_WDLY(x) ((x) << 19) +#define S3C2410_LCDCON3_HBPD(x) ((x) << 19) +#define S3C2410_LCDCON3_WDLY(x) ((x) << 19) #define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8) -#define S3C2410_LCDCON3_HFPD(x) ((x) << 0) +#define S3C2410_LCDCON3_HFPD(x) ((x) << 0) #define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0) #define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F) #define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF) -#define S3C2410_LCDCON4_MVAL(x) ((x) << 8) -#define S3C2410_LCDCON4_HSPW(x) ((x) << 0) -#define S3C2410_LCDCON4_WLH(x) ((x) << 0) +#define S3C2410_LCDCON4_MVAL(x) ((x) << 8) +#define S3C2410_LCDCON4_HSPW(x) ((x) << 0) +#define S3C2410_LCDCON4_WLH(x) ((x) << 0) #define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >> 0) & 0xFF) -#define S3C2410_LCDCON5_BPP24BL (1<<12) -#define S3C2410_LCDCON5_FRM565 (1<<11) -#define S3C2410_LCDCON5_INVVCLK (1<<10) +#define S3C2410_LCDCON5_BPP24BL (1<<12) +#define S3C2410_LCDCON5_FRM565 (1<<11) +#define S3C2410_LCDCON5_INVVCLK (1<<10) #define S3C2410_LCDCON5_INVVLINE (1<<9) #define S3C2410_LCDCON5_INVVFRAME (1<<8) -#define S3C2410_LCDCON5_INVVD (1<<7) -#define S3C2410_LCDCON5_INVVDEN (1<<6) +#define S3C2410_LCDCON5_INVVD (1<<7) +#define S3C2410_LCDCON5_INVVDEN (1<<6) #define S3C2410_LCDCON5_INVPWREN (1<<5) -#define S3C2410_LCDCON5_INVLEND (1<<4) -#define S3C2410_LCDCON5_PWREN (1<<3) -#define S3C2410_LCDCON5_ENLEND (1<<2) -#define S3C2410_LCDCON5_BSWP (1<<1) -#define S3C2410_LCDCON5_HWSWP (1<<0) +#define S3C2410_LCDCON5_INVLEND (1<<4) +#define S3C2410_LCDCON5_PWREN (1<<3) +#define S3C2410_LCDCON5_ENLEND (1<<2) +#define S3C2410_LCDCON5_BSWP (1<<1) +#define S3C2410_LCDCON5_HWSWP (1<<0) -#define S3C2410_LCDINT_FRSYNC (1<<1) +#define S3C2410_LCDINT_FRSYNC (1<<1) volatile rt_uint16_t _rt_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH]; //volatile rt_uint16_t _rt_hw_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH]; @@ -125,122 +125,122 @@ static void lcd_power_enable(int invpwren, int pwren) static void lcd_envid_on_off(int onoff) { - if(onoff==1) - /*ENVID=ON*/ - LCDCON1|=1; - else - /*ENVID Off*/ - LCDCON1 =LCDCON1 & 0x3fffe; + if(onoff==1) + /*ENVID=ON*/ + LCDCON1|=1; + else + /*ENVID Off*/ + LCDCON1 =LCDCON1 & 0x3fffe; } //********************** BOARD LCD backlight **************************** static void LcdBkLtSet(rt_uint32_t HiRatio) { -#define FREQ_PWM1 1000 - if(!HiRatio) - { - GPBCON = GPBCON & (~(3<<2)) | (1<<2) ; //GPB1设置为output - GPBDAT &= ~(1<<1); - return; - } - GPBCON = GPBCON & (~(3<<2)) | (2<<2) ; +#define FREQ_PWM1 1000 + if(!HiRatio) + { + GPBCON = GPBCON & (~(3<<2)) | (1<<2) ; //GPB1设置为output + GPBDAT &= ~(1<<1); + return; + } + GPBCON = GPBCON & (~(3<<2)) | (2<<2) ; - if( HiRatio > 100 ) HiRatio = 100 ; + if( HiRatio > 100 ) HiRatio = 100 ; - TCON = TCON & (~(0xf<<8)) ; // clear manual update bit, stop Timer1 + TCON = TCON & (~(0xf<<8)) ; // clear manual update bit, stop Timer1 - TCFG0 &= 0xffffff00; // set Timer 0&1 prescaler 0 - TCFG0 |= 15; //prescaler = 15+1 + TCFG0 &= 0xffffff00; // set Timer 0&1 prescaler 0 + TCFG0 |= 15; //prescaler = 15+1 - TCFG1 &= 0xffffff0f; // set Timer 1 MUX 1/16 - TCFG1 |= 0x00000030; // set Timer 1 MUX 1/16 + TCFG1 &= 0xffffff0f; // set Timer 1 MUX 1/16 + TCFG1 |= 0x00000030; // set Timer 1 MUX 1/16 - TCNTB1 = ( 100000000>>8 )/FREQ_PWM1; //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low - TCMPB1 = ( TCNTB1*(100-HiRatio))/100 ; //if set inverter on, when TCNT2<=TCMP2, TOUT is low, TCNT2>TCMP2, TOUT is high + TCNTB1 = ( 100000000>>8 )/FREQ_PWM1; //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low + TCMPB1 = ( TCNTB1*(100-HiRatio))/100 ; //if set inverter on, when TCNT2<=TCMP2, TOUT is low, TCNT2>TCMP2, TOUT is high - TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ; - TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ; + TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ; + TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ; } /* RT-Thread Device Interface */ static rt_err_t rt_lcd_init (rt_device_t dev) -{ - GPB1_TO_OUT(); - GPB1_TO_1(); +{ + GPB1_TO_OUT(); + GPB1_TO_1(); - GPCUP = 0x00000000; - GPCCON = 0xaaaa02a9; + GPCUP = 0x00000000; + GPCCON = 0xaaaa02a9; - GPDUP = 0x00000000; - GPDCON = 0xaaaaaaaa; + GPDUP = 0x00000000; + GPDCON = 0xaaaaaaaa; -#define M5D(n) ((n)&0x1fffff) +#define M5D(n) ((n)&0x1fffff) #define LCD_ADDR ((rt_uint32_t)_rt_framebuffer) - LCDCON1 = (LCD_PIXCLOCK << 8) | (3 << 5) | (12 << 1); - LCDCON2 = (LCD_UPPER_MARGIN << 24) | ((LCD_HEIGHT - 1) << 14) | (LCD_LOWER_MARGIN << 6) | (LCD_VSYNC_LEN << 0); - LCDCON3 = (LCD_RIGHT_MARGIN << 19) | ((LCD_WIDTH - 1) << 8) | (LCD_LEFT_MARGIN << 0); - LCDCON4 = (13 << 8) | (LCD_HSYNC_LEN << 0); + LCDCON1 = (LCD_PIXCLOCK << 8) | (3 << 5) | (12 << 1); + LCDCON2 = (LCD_UPPER_MARGIN << 24) | ((LCD_HEIGHT - 1) << 14) | (LCD_LOWER_MARGIN << 6) | (LCD_VSYNC_LEN << 0); + LCDCON3 = (LCD_RIGHT_MARGIN << 19) | ((LCD_WIDTH - 1) << 8) | (LCD_LEFT_MARGIN << 0); + LCDCON4 = (13 << 8) | (LCD_HSYNC_LEN << 0); #if !defined(LCD_CON5) #define LCD_CON5 ((1<<11) | (1 << 9) | (1 << 8) | (1 << 3) | (1 << 0)) #endif - LCDCON5 = LCD_CON5; + LCDCON5 = LCD_CON5; - LCDSADDR1 = ((LCD_ADDR >> 22) << 21) | ((M5D(LCD_ADDR >> 1)) << 0); - LCDSADDR2 = M5D((LCD_ADDR + LCD_WIDTH * LCD_HEIGHT * 2) >> 1); - LCDSADDR3 = LCD_WIDTH; + LCDSADDR1 = ((LCD_ADDR >> 22) << 21) | ((M5D(LCD_ADDR >> 1)) << 0); + LCDSADDR2 = M5D((LCD_ADDR + LCD_WIDTH * LCD_HEIGHT * 2) >> 1); + LCDSADDR3 = LCD_WIDTH; - LCDINTMSK |= (3); - LPCSEL &= (~7) ; - TPAL=0; + LCDINTMSK |= (3); + LPCSEL &= (~7) ; + TPAL=0; - LcdBkLtSet(70) ; - lcd_power_enable(0, 1); - lcd_envid_on_off(1); + LcdBkLtSet(70) ; + lcd_power_enable(0, 1); + lcd_envid_on_off(1); - return RT_EOK; + return RT_EOK; } static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args) { - switch (cmd) - { - case RTGRAPHIC_CTRL_RECT_UPDATE: - break; - case RTGRAPHIC_CTRL_POWERON: - break; - case RTGRAPHIC_CTRL_POWEROFF: - break; - case RTGRAPHIC_CTRL_GET_INFO: - rt_memcpy(args, &_lcd_info, sizeof(_lcd_info)); - break; - case RTGRAPHIC_CTRL_SET_MODE: - break; - } - - return RT_EOK; + switch (cmd) + { + case RTGRAPHIC_CTRL_RECT_UPDATE: + break; + case RTGRAPHIC_CTRL_POWERON: + break; + case RTGRAPHIC_CTRL_POWEROFF: + break; + case RTGRAPHIC_CTRL_GET_INFO: + rt_memcpy(args, &_lcd_info, sizeof(_lcd_info)); + break; + case RTGRAPHIC_CTRL_SET_MODE: + break; + } + + return RT_EOK; } void rt_hw_lcd_init(void) { - rt_device_t lcd = rt_malloc(sizeof(struct rt_device)); - if (lcd == RT_NULL) return; /* no memory yet */ - - _lcd_info.bits_per_pixel = 16; - _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P; - _lcd_info.framebuffer = (void*)_rt_framebuffer; - _lcd_info.width = LCD_WIDTH; - _lcd_info.height = LCD_HEIGHT; - - /* init device structure */ - lcd->type = RT_Device_Class_Unknown; - lcd->init = rt_lcd_init; - lcd->open = RT_NULL; - lcd->close = RT_NULL; - lcd->control = rt_lcd_control; - lcd->user_data = (void*)&_lcd_info; - - /* register lcd device to RT-Thread */ - rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR); + rt_device_t lcd = rt_malloc(sizeof(struct rt_device)); + if (lcd == RT_NULL) return; /* no memory yet */ + + _lcd_info.bits_per_pixel = 16; + _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P; + _lcd_info.framebuffer = (void*)_rt_framebuffer; + _lcd_info.width = LCD_WIDTH; + _lcd_info.height = LCD_HEIGHT; + + /* init device structure */ + lcd->type = RT_Device_Class_Unknown; + lcd->init = rt_lcd_init; + lcd->open = RT_NULL; + lcd->close = RT_NULL; + lcd->control = rt_lcd_control; + lcd->user_data = (void*)&_lcd_info; + + /* register lcd device to RT-Thread */ + rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR); } diff --git a/bsp/mini2440/drivers/lcd_x35.c b/bsp/mini2440/drivers/lcd_x35.c index d3f547df1d..1bb6b9d907 100644 --- a/bsp/mini2440/drivers/lcd_x35.c +++ b/bsp/mini2440/drivers/lcd_x35.c @@ -6,7 +6,7 @@ * Change Logs: * Date Author Notes * 2010-01-01 bernard first version from QiuYi's driver - * 2011-07-13 Manoel Modifications on lcd_n35.c to support X35 LCD + * 2011-07-13 Manoel Modifications on lcd_n35.c to support X35 LCD * ACX502BMU - 7522J16D SONY */ @@ -25,7 +25,7 @@ #define LCD_HSYNC_LEN 5 // hsync #define LCD_UPPER_MARGIN 1 // margin_top -#define LCD_LOWER_MARGIN 3 // margin_botton +#define LCD_LOWER_MARGIN 3 // margin_botton #define LCD_VSYNC_LEN 9 // vsync #define LCD_XSIZE LCD_WIDTH @@ -33,82 +33,82 @@ #define SCR_XSIZE LCD_WIDTH #define SCR_YSIZE LCD_HEIGHT -#define RT_HW_LCD_WIDTH LCD_WIDTH -#define RT_HW_LCD_HEIGHT LCD_HEIGHT +#define RT_HW_LCD_WIDTH LCD_WIDTH +#define RT_HW_LCD_HEIGHT LCD_HEIGHT -#define MVAL (13) -#define MVAL_USED (0) //0=each frame 1=rate by MVAL -#define INVVDEN (1) //0=normal 1=inverted -#define BSWP (0) //Byte swap control -#define HWSWP (1) //Half word swap control +#define MVAL (13) +#define MVAL_USED (0) //0=each frame 1=rate by MVAL +#define INVVDEN (1) //0=normal 1=inverted +#define BSWP (0) //Byte swap control +#define HWSWP (1) //Half word swap control -#define GPB1_TO_OUT() (GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004) -#define GPB1_TO_1() (GPBDAT |= 0x0002) -#define GPB1_TO_0() (GPBDAT &= 0xfffd) +#define GPB1_TO_OUT() (GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004) +#define GPB1_TO_1() (GPBDAT |= 0x0002) +#define GPB1_TO_0() (GPBDAT &= 0xfffd) #define S3C2410_LCDCON1_CLKVAL(x) ((x) << 8) -#define S3C2410_LCDCON1_MMODE (1<<7) -#define S3C2410_LCDCON1_DSCAN4 (0<<5) -#define S3C2410_LCDCON1_STN4 (1<<5) -#define S3C2410_LCDCON1_STN8 (2<<5) -#define S3C2410_LCDCON1_TFT (3<<5) +#define S3C2410_LCDCON1_MMODE (1<<7) +#define S3C2410_LCDCON1_DSCAN4 (0<<5) +#define S3C2410_LCDCON1_STN4 (1<<5) +#define S3C2410_LCDCON1_STN8 (2<<5) +#define S3C2410_LCDCON1_TFT (3<<5) -#define S3C2410_LCDCON1_STN1BPP (0<<1) +#define S3C2410_LCDCON1_STN1BPP (0<<1) #define S3C2410_LCDCON1_STN2GREY (1<<1) #define S3C2410_LCDCON1_STN4GREY (2<<1) -#define S3C2410_LCDCON1_STN8BPP (3<<1) +#define S3C2410_LCDCON1_STN8BPP (3<<1) #define S3C2410_LCDCON1_STN12BPP (4<<1) -#define S3C2410_LCDCON1_TFT1BPP (8<<1) -#define S3C2410_LCDCON1_TFT2BPP (9<<1) -#define S3C2410_LCDCON1_TFT4BPP (10<<1) -#define S3C2410_LCDCON1_TFT8BPP (11<<1) +#define S3C2410_LCDCON1_TFT1BPP (8<<1) +#define S3C2410_LCDCON1_TFT2BPP (9<<1) +#define S3C2410_LCDCON1_TFT4BPP (10<<1) +#define S3C2410_LCDCON1_TFT8BPP (11<<1) #define S3C2410_LCDCON1_TFT16BPP (12<<1) #define S3C2410_LCDCON1_TFT24BPP (13<<1) -#define S3C2410_LCDCON1_ENVID (1) +#define S3C2410_LCDCON1_ENVID (1) #define S3C2410_LCDCON1_MODEMASK 0x1E -#define S3C2410_LCDCON2_VBPD(x) ((x) << 24) +#define S3C2410_LCDCON2_VBPD(x) ((x) << 24) #define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14) -#define S3C2410_LCDCON2_VFPD(x) ((x) << 6) -#define S3C2410_LCDCON2_VSPW(x) ((x) << 0) +#define S3C2410_LCDCON2_VFPD(x) ((x) << 6) +#define S3C2410_LCDCON2_VSPW(x) ((x) << 0) #define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF) #define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >> 6) & 0xFF) #define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >> 0) & 0x3F) -#define S3C2410_LCDCON3_HBPD(x) ((x) << 19) -#define S3C2410_LCDCON3_WDLY(x) ((x) << 19) +#define S3C2410_LCDCON3_HBPD(x) ((x) << 19) +#define S3C2410_LCDCON3_WDLY(x) ((x) << 19) #define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8) -#define S3C2410_LCDCON3_HFPD(x) ((x) << 0) +#define S3C2410_LCDCON3_HFPD(x) ((x) << 0) #define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0) #define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F) #define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF) -#define S3C2410_LCDCON4_MVAL(x) ((x) << 8) -#define S3C2410_LCDCON4_HSPW(x) ((x) << 0) -#define S3C2410_LCDCON4_WLH(x) ((x) << 0) +#define S3C2410_LCDCON4_MVAL(x) ((x) << 8) +#define S3C2410_LCDCON4_HSPW(x) ((x) << 0) +#define S3C2410_LCDCON4_WLH(x) ((x) << 0) #define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >> 0) & 0xFF) -#define S3C2410_LCDCON5_BPP24BL (1<<12) -#define S3C2410_LCDCON5_FRM565 (1<<11) -#define S3C2410_LCDCON5_INVVCLK (1<<10) +#define S3C2410_LCDCON5_BPP24BL (1<<12) +#define S3C2410_LCDCON5_FRM565 (1<<11) +#define S3C2410_LCDCON5_INVVCLK (1<<10) #define S3C2410_LCDCON5_INVVLINE (1<<9) #define S3C2410_LCDCON5_INVVFRAME (1<<8) -#define S3C2410_LCDCON5_INVVD (1<<7) -#define S3C2410_LCDCON5_INVVDEN (1<<6) +#define S3C2410_LCDCON5_INVVD (1<<7) +#define S3C2410_LCDCON5_INVVDEN (1<<6) #define S3C2410_LCDCON5_INVPWREN (1<<5) -#define S3C2410_LCDCON5_INVLEND (1<<4) -#define S3C2410_LCDCON5_PWREN (1<<3) -#define S3C2410_LCDCON5_ENLEND (1<<2) -#define S3C2410_LCDCON5_BSWP (1<<1) -#define S3C2410_LCDCON5_HWSWP (1<<0) +#define S3C2410_LCDCON5_INVLEND (1<<4) +#define S3C2410_LCDCON5_PWREN (1<<3) +#define S3C2410_LCDCON5_ENLEND (1<<2) +#define S3C2410_LCDCON5_BSWP (1<<1) +#define S3C2410_LCDCON5_HWSWP (1<<0) -#define S3C2410_LCDINT_FRSYNC (1<<1) +#define S3C2410_LCDINT_FRSYNC (1<<1) static volatile rt_uint16_t _rt_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH]; //static volatile rt_uint16_t _rt_hw_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH]; @@ -127,61 +127,61 @@ static void lcd_power_enable(int invpwren, int pwren) static void lcd_envid_on_off(int onoff) { - if(onoff==1) - /*ENVID=ON*/ - LCDCON1|=1; - else - /*ENVID Off*/ - LCDCON1 =LCDCON1 & 0x3fffe; + if(onoff==1) + /*ENVID=ON*/ + LCDCON1|=1; + else + /*ENVID Off*/ + LCDCON1 =LCDCON1 & 0x3fffe; } //********************** BOARD LCD backlight **************************** static void LcdBkLtSet(rt_uint32_t HiRatio) { -#define FREQ_PWM1 1000 - if(!HiRatio) - { - GPBCON = GPBCON & (~(3<<2)) | (1<<2) ; //GPB1设置为output - GPBDAT &= ~(1<<1); - return; - } - GPBCON = GPBCON & (~(3<<2)) | (2<<2) ; +#define FREQ_PWM1 1000 + if(!HiRatio) + { + GPBCON = GPBCON & (~(3<<2)) | (1<<2) ; //GPB1设置为output + GPBDAT &= ~(1<<1); + return; + } + GPBCON = GPBCON & (~(3<<2)) | (2<<2) ; - if( HiRatio > 100 ) HiRatio = 100 ; + if( HiRatio > 100 ) HiRatio = 100 ; - TCON = TCON & (~(0xf<<8)) ; // clear manual update bit, stop Timer1 + TCON = TCON & (~(0xf<<8)) ; // clear manual update bit, stop Timer1 - TCFG0 &= 0xffffff00; // set Timer 0&1 prescaler 0 - TCFG0 |= 15; //prescaler = 15+1 + TCFG0 &= 0xffffff00; // set Timer 0&1 prescaler 0 + TCFG0 |= 15; //prescaler = 15+1 - TCFG1 &= 0xffffff0f; // set Timer 1 MUX 1/16 - TCFG1 |= 0x00000030; // set Timer 1 MUX 1/16 + TCFG1 &= 0xffffff0f; // set Timer 1 MUX 1/16 + TCFG1 |= 0x00000030; // set Timer 1 MUX 1/16 - TCNTB1 = ( 100000000>>8 )/FREQ_PWM1; //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low - TCMPB1 = ( TCNTB1*(100-HiRatio))/100 ; //if set inverter on, when TCNT2<=TCMP2, TOUT is low, TCNT2>TCMP2, TOUT is high + TCNTB1 = ( 100000000>>8 )/FREQ_PWM1; //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low + TCMPB1 = ( TCNTB1*(100-HiRatio))/100 ; //if set inverter on, when TCNT2<=TCMP2, TOUT is low, TCNT2>TCMP2, TOUT is high - TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ; - TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ; + TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ; + TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ; } /* RT-Thread Device Interface */ static rt_err_t rt_lcd_init (rt_device_t dev) -{ - GPB1_TO_OUT(); - GPB1_TO_1(); +{ + GPB1_TO_OUT(); + GPB1_TO_1(); - GPCUP = 0x00000000; - GPCCON = 0xaaaa02a9; + GPCUP = 0x00000000; + GPCCON = 0xaaaa02a9; - GPDUP = 0x00000000; - GPDCON = 0xaaaaaaaa; + GPDUP = 0x00000000; + GPDCON = 0xaaaaaaaa; -#define M5D(n) ((n)&0x1fffff) +#define M5D(n) ((n)&0x1fffff) #define LCD_ADDR ((rt_uint32_t)_rt_framebuffer) - LCDCON1 = (LCD_PIXCLOCK << 8) | (3 << 5) | (12 << 1); - LCDCON2 = (LCD_UPPER_MARGIN << 24) | ((LCD_HEIGHT - 1) << 14) | (LCD_LOWER_MARGIN << 6) | (LCD_VSYNC_LEN << 0); - LCDCON3 = (LCD_RIGHT_MARGIN << 19) | ((LCD_WIDTH - 1) << 8) | (LCD_LEFT_MARGIN << 0); - LCDCON4 = (13 << 8) | (LCD_HSYNC_LEN << 0); + LCDCON1 = (LCD_PIXCLOCK << 8) | (3 << 5) | (12 << 1); + LCDCON2 = (LCD_UPPER_MARGIN << 24) | ((LCD_HEIGHT - 1) << 14) | (LCD_LOWER_MARGIN << 6) | (LCD_VSYNC_LEN << 0); + LCDCON3 = (LCD_RIGHT_MARGIN << 19) | ((LCD_WIDTH - 1) << 8) | (LCD_LEFT_MARGIN << 0); + LCDCON4 = (13 << 8) | (LCD_HSYNC_LEN << 0); #define LCD_CON5 (S3C2410_LCDCON5_FRM565 | S3C2410_LCDCON5_INVVDEN | S3C2410_LCDCON5_INVVFRAME | \ S3C2410_LCDCON5_INVVLINE | S3C2410_LCDCON5_INVVCLK | S3C2410_LCDCON5_PWREN| S3C2410_LCDCON5_HWSWP) @@ -195,57 +195,57 @@ S3C2410_LCDCON5_INVVLINE | S3C2410_LCDCON5_INVVCLK | S3C2410_LCDCON5_PWREN| S3C2 LCDSADDR2 = M5D((LCD_ADDR + LCD_WIDTH * LCD_HEIGHT * 2) >> 1); LCDSADDR3 = LCD_WIDTH; - LCDINTMSK |= (3); - LPCSEL &= (~7) ; - TPAL=0; + LCDINTMSK |= (3); + LPCSEL &= (~7) ; + TPAL=0; - LcdBkLtSet(70) ; - lcd_power_enable(0, 1); - lcd_envid_on_off(1); + LcdBkLtSet(70) ; + lcd_power_enable(0, 1); + lcd_envid_on_off(1); - return RT_EOK; + return RT_EOK; } static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args) { - switch (cmd) - { - case RTGRAPHIC_CTRL_RECT_UPDATE: - break; - case RTGRAPHIC_CTRL_POWERON: - break; - case RTGRAPHIC_CTRL_POWEROFF: - break; - case RTGRAPHIC_CTRL_GET_INFO: - rt_memcpy(args, &_lcd_info, sizeof(_lcd_info)); - break; - case RTGRAPHIC_CTRL_SET_MODE: - break; - } - - return RT_EOK; + switch (cmd) + { + case RTGRAPHIC_CTRL_RECT_UPDATE: + break; + case RTGRAPHIC_CTRL_POWERON: + break; + case RTGRAPHIC_CTRL_POWEROFF: + break; + case RTGRAPHIC_CTRL_GET_INFO: + rt_memcpy(args, &_lcd_info, sizeof(_lcd_info)); + break; + case RTGRAPHIC_CTRL_SET_MODE: + break; + } + + return RT_EOK; } void rt_hw_lcd_init(void) { - rt_device_t lcd = rt_malloc(sizeof(struct rt_device)); - if (lcd == RT_NULL) return; /* no memory yet */ - - _lcd_info.bits_per_pixel = 16; - _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P; - _lcd_info.framebuffer = (void*)_rt_framebuffer; - _lcd_info.width = LCD_WIDTH; - _lcd_info.height = LCD_HEIGHT; - - /* init device structure */ - lcd->type = RT_Device_Class_Unknown; - lcd->init = rt_lcd_init; - lcd->open = RT_NULL; - lcd->close = RT_NULL; - lcd->control = rt_lcd_control; - lcd->user_data = (void*)&_lcd_info; - - /* register lcd device to RT-Thread */ - rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR); + rt_device_t lcd = rt_malloc(sizeof(struct rt_device)); + if (lcd == RT_NULL) return; /* no memory yet */ + + _lcd_info.bits_per_pixel = 16; + _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P; + _lcd_info.framebuffer = (void*)_rt_framebuffer; + _lcd_info.width = LCD_WIDTH; + _lcd_info.height = LCD_HEIGHT; + + /* init device structure */ + lcd->type = RT_Device_Class_Unknown; + lcd->init = rt_lcd_init; + lcd->open = RT_NULL; + lcd->close = RT_NULL; + lcd->control = rt_lcd_control; + lcd->user_data = (void*)&_lcd_info; + + /* register lcd device to RT-Thread */ + rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR); } diff --git a/bsp/mini2440/drivers/led.c b/bsp/mini2440/drivers/led.c index 3cc830012e..88e83d33ef 100644 --- a/bsp/mini2440/drivers/led.c +++ b/bsp/mini2440/drivers/led.c @@ -18,19 +18,19 @@ void rt_hw_led_init(void) { - /* GPB5,GPB6,GPB7,GPB8 for LED */ - GPBCON = GPBCON & (~(0xff << 10)) | (0x55 << 10); - GPBUP |= (0x0f << 5); + /* GPB5,GPB6,GPB7,GPB8 for LED */ + GPBCON = GPBCON & (~(0xff << 10)) | (0x55 << 10); + GPBUP |= (0x0f << 5); } void rt_hw_led_on(unsigned char value) { - GPBDAT &= ~ ((value & 0x0f) << 5); + GPBDAT &= ~ ((value & 0x0f) << 5); } void rt_hw_led_off(unsigned char value) { - GPBDAT |= (value & 0x0f) << 5; + GPBDAT |= (value & 0x0f) << 5; } /*@}*/ diff --git a/bsp/mini2440/drivers/sdcard.c b/bsp/mini2440/drivers/sdcard.c index 87ab4a27e7..0f1555f4ce 100644 --- a/bsp/mini2440/drivers/sdcard.c +++ b/bsp/mini2440/drivers/sdcard.c @@ -286,15 +286,15 @@ static int sd_ocr(void) rt_err_t sd_cmd8(void) { - SDICARG = 0x000001AA; + SDICARG = 0x000001AA; SDICCON = (0x1<<9) | (0x1<<8) | 0x48; //sht_resp, wait_resp, start if (sd_cmd_end(8, 1) == RT_ERROR) return RT_ERROR; SDICSTA = 0xa00; - + if ((SDIRSP0&0x1aa) == 0x1aa) - return RT_EOK; - else + return RT_EOK; + else return RT_ERROR; } diff --git a/bsp/mini2440/drivers/touch.c b/bsp/mini2440/drivers/touch.c index 2c9f8ca52f..d2e20c9db4 100644 --- a/bsp/mini2440/drivers/touch.c +++ b/bsp/mini2440/drivers/touch.c @@ -7,7 +7,7 @@ * Date Author Notes * 2010-01-01 Yi.Qiu first version */ - + #include #include #include @@ -22,473 +22,473 @@ #include "touch.h" /* ADCCON Register Bits */ -#define S3C2410_ADCCON_ECFLG (1<<15) -#define S3C2410_ADCCON_PRSCEN (1<<14) -#define S3C2410_ADCCON_PRSCVL(x) (((x)&0xFF)<<6) -#define S3C2410_ADCCON_PRSCVLMASK (0xFF<<6) -#define S3C2410_ADCCON_SELMUX(x) (((x)&0x7)<<3) -#define S3C2410_ADCCON_MUXMASK (0x7<<3) -#define S3C2410_ADCCON_STDBM (1<<2) -#define S3C2410_ADCCON_READ_START (1<<1) -#define S3C2410_ADCCON_ENABLE_START (1<<0) -#define S3C2410_ADCCON_STARTMASK (0x3<<0) +#define S3C2410_ADCCON_ECFLG (1<<15) +#define S3C2410_ADCCON_PRSCEN (1<<14) +#define S3C2410_ADCCON_PRSCVL(x) (((x)&0xFF)<<6) +#define S3C2410_ADCCON_PRSCVLMASK (0xFF<<6) +#define S3C2410_ADCCON_SELMUX(x) (((x)&0x7)<<3) +#define S3C2410_ADCCON_MUXMASK (0x7<<3) +#define S3C2410_ADCCON_STDBM (1<<2) +#define S3C2410_ADCCON_READ_START (1<<1) +#define S3C2410_ADCCON_ENABLE_START (1<<0) +#define S3C2410_ADCCON_STARTMASK (0x3<<0) /* ADCTSC Register Bits */ -#define S3C2410_ADCTSC_UD_SEN (1<<8) /* ghcstop add for s3c2440a */ -#define S3C2410_ADCTSC_YM_SEN (1<<7) -#define S3C2410_ADCTSC_YP_SEN (1<<6) -#define S3C2410_ADCTSC_XM_SEN (1<<5) -#define S3C2410_ADCTSC_XP_SEN (1<<4) -#define S3C2410_ADCTSC_PULL_UP_DISABLE (1<<3) -#define S3C2410_ADCTSC_AUTO_PST (1<<2) -#define S3C2410_ADCTSC_XY_PST(x) (((x)&0x3)<<0) +#define S3C2410_ADCTSC_UD_SEN (1<<8) /* ghcstop add for s3c2440a */ +#define S3C2410_ADCTSC_YM_SEN (1<<7) +#define S3C2410_ADCTSC_YP_SEN (1<<6) +#define S3C2410_ADCTSC_XM_SEN (1<<5) +#define S3C2410_ADCTSC_XP_SEN (1<<4) +#define S3C2410_ADCTSC_PULL_UP_DISABLE (1<<3) +#define S3C2410_ADCTSC_AUTO_PST (1<<2) +#define S3C2410_ADCTSC_XY_PST(x) (((x)&0x3)<<0) /* ADCDAT0 Bits */ -#define S3C2410_ADCDAT0_UPDOWN (1<<15) -#define S3C2410_ADCDAT0_AUTO_PST (1<<14) -#define S3C2410_ADCDAT0_XY_PST (0x3<<12) -#define S3C2410_ADCDAT0_XPDATA_MASK (0x03FF) +#define S3C2410_ADCDAT0_UPDOWN (1<<15) +#define S3C2410_ADCDAT0_AUTO_PST (1<<14) +#define S3C2410_ADCDAT0_XY_PST (0x3<<12) +#define S3C2410_ADCDAT0_XPDATA_MASK (0x03FF) /* ADCDAT1 Bits */ -#define S3C2410_ADCDAT1_UPDOWN (1<<15) -#define S3C2410_ADCDAT1_AUTO_PST (1<<14) -#define S3C2410_ADCDAT1_XY_PST (0x3<<12) -#define S3C2410_ADCDAT1_YPDATA_MASK (0x03FF) +#define S3C2410_ADCDAT1_UPDOWN (1<<15) +#define S3C2410_ADCDAT1_AUTO_PST (1<<14) +#define S3C2410_ADCDAT1_XY_PST (0x3<<12) +#define S3C2410_ADCDAT1_YPDATA_MASK (0x03FF) #define WAIT4INT(x) (((x)<<8) | \ - S3C2410_ADCTSC_YM_SEN | S3C2410_ADCTSC_YP_SEN | S3C2410_ADCTSC_XP_SEN | \ - S3C2410_ADCTSC_XY_PST(3)) + S3C2410_ADCTSC_YM_SEN | S3C2410_ADCTSC_YP_SEN | S3C2410_ADCTSC_XP_SEN | \ + S3C2410_ADCTSC_XY_PST(3)) -#define AUTOPST (S3C2410_ADCTSC_YM_SEN | S3C2410_ADCTSC_YP_SEN | S3C2410_ADCTSC_XP_SEN | \ - S3C2410_ADCTSC_AUTO_PST | S3C2410_ADCTSC_XY_PST(0)) +#define AUTOPST (S3C2410_ADCTSC_YM_SEN | S3C2410_ADCTSC_YP_SEN | S3C2410_ADCTSC_XP_SEN | \ + S3C2410_ADCTSC_AUTO_PST | S3C2410_ADCTSC_XY_PST(0)) -#define X_MIN 74 -#define X_MAX 934 -#define Y_MIN 920 -#define Y_MAX 89 +#define X_MIN 74 +#define X_MAX 934 +#define Y_MIN 920 +#define Y_MAX 89 struct s3c2410ts { - long xp; - long yp; - int count; - int shift; + long xp; + long yp; + int count; + int shift; - int delay; - int presc; + int delay; + int presc; - char phys[32]; + char phys[32]; }; static struct s3c2410ts ts; struct rtgui_touch_device { - struct rt_device parent; + struct rt_device parent; + + rt_timer_t poll_timer; + rt_uint16_t x, y; - rt_timer_t poll_timer; - rt_uint16_t x, y; + rt_bool_t calibrating; + rt_touch_calibration_func_t calibration_func; - rt_bool_t calibrating; - rt_touch_calibration_func_t calibration_func; + rt_touch_eventpost_func_t eventpost_func; + void *eventpost_param; - rt_touch_eventpost_func_t eventpost_func; - void *eventpost_param; + rt_uint16_t min_x, max_x; + rt_uint16_t min_y, max_y; - rt_uint16_t min_x, max_x; - rt_uint16_t min_y, max_y; + rt_uint16_t width; + rt_uint16_t height; - rt_uint16_t width; - rt_uint16_t height; - - rt_bool_t first_down_report; + rt_bool_t first_down_report; }; static struct rtgui_touch_device *touch = RT_NULL; #ifdef RT_USING_RTGUI static void report_touch_input(int updown) { - struct rtgui_event_mouse emouse; - - RTGUI_EVENT_MOUSE_BUTTON_INIT(&emouse); - emouse.wid = RT_NULL; - - /* set emouse button */ - emouse.button = RTGUI_MOUSE_BUTTON_LEFT; - emouse.parent.sender = RT_NULL; - - if (updown) - { - ts.xp = ts.xp / ts.count; - ts.yp = ts.yp / ts.count;; - - if ((touch->calibrating == RT_TRUE) && (touch->calibration_func != RT_NULL)) - { - touch->x = ts.xp; - touch->y = ts.yp; - } - else - { - if (touch->max_x > touch->min_x) - { - touch->x = touch->width * (ts.xp-touch->min_x)/(touch->max_x-touch->min_x); - } - else - { - touch->x = touch->width * ( touch->min_x - ts.xp ) / (touch->min_x-touch->max_x); - } - - if (touch->max_y > touch->min_y) - { - touch->y = touch->height * ( ts.yp - touch->min_y ) / (touch->max_y-touch->min_y); - } - else - { - touch->y = touch->height * ( touch->min_y - ts.yp ) / (touch->min_y-touch->max_y); - } - } - - emouse.x = touch->x; - emouse.y = touch->y; - if (touch->first_down_report == RT_TRUE) - { - emouse.parent.type = RTGUI_EVENT_MOUSE_BUTTON; - emouse.button |= RTGUI_MOUSE_BUTTON_DOWN; - } - else - { - emouse.parent.type = RTGUI_EVENT_MOUSE_MOTION; - emouse.button = 0; - } - } - else - { - emouse.x = touch->x; - emouse.y = touch->y; - emouse.parent.type = RTGUI_EVENT_MOUSE_BUTTON; - emouse.button |= RTGUI_MOUSE_BUTTON_UP; - if ((touch->calibrating == RT_TRUE) && (touch->calibration_func != RT_NULL)) - { - /* callback function */ - touch->calibration_func(emouse.x, emouse.y); - } - } - - /* rt_kprintf("touch %s: ts.x: %d, ts.y: %d\n", updown? "down" : "up", - touch->x, touch->y); */ - - /* send event to server */ - if (touch->calibrating != RT_TRUE) - { - rtgui_server_post_event((&emouse.parent), sizeof(emouse)); - } + struct rtgui_event_mouse emouse; + + RTGUI_EVENT_MOUSE_BUTTON_INIT(&emouse); + emouse.wid = RT_NULL; + + /* set emouse button */ + emouse.button = RTGUI_MOUSE_BUTTON_LEFT; + emouse.parent.sender = RT_NULL; + + if (updown) + { + ts.xp = ts.xp / ts.count; + ts.yp = ts.yp / ts.count;; + + if ((touch->calibrating == RT_TRUE) && (touch->calibration_func != RT_NULL)) + { + touch->x = ts.xp; + touch->y = ts.yp; + } + else + { + if (touch->max_x > touch->min_x) + { + touch->x = touch->width * (ts.xp-touch->min_x)/(touch->max_x-touch->min_x); + } + else + { + touch->x = touch->width * ( touch->min_x - ts.xp ) / (touch->min_x-touch->max_x); + } + + if (touch->max_y > touch->min_y) + { + touch->y = touch->height * ( ts.yp - touch->min_y ) / (touch->max_y-touch->min_y); + } + else + { + touch->y = touch->height * ( touch->min_y - ts.yp ) / (touch->min_y-touch->max_y); + } + } + + emouse.x = touch->x; + emouse.y = touch->y; + if (touch->first_down_report == RT_TRUE) + { + emouse.parent.type = RTGUI_EVENT_MOUSE_BUTTON; + emouse.button |= RTGUI_MOUSE_BUTTON_DOWN; + } + else + { + emouse.parent.type = RTGUI_EVENT_MOUSE_MOTION; + emouse.button = 0; + } + } + else + { + emouse.x = touch->x; + emouse.y = touch->y; + emouse.parent.type = RTGUI_EVENT_MOUSE_BUTTON; + emouse.button |= RTGUI_MOUSE_BUTTON_UP; + if ((touch->calibrating == RT_TRUE) && (touch->calibration_func != RT_NULL)) + { + /* callback function */ + touch->calibration_func(emouse.x, emouse.y); + } + } + + /* rt_kprintf("touch %s: ts.x: %d, ts.y: %d\n", updown? "down" : "up", + touch->x, touch->y); */ + + /* send event to server */ + if (touch->calibrating != RT_TRUE) + { + rtgui_server_post_event((&emouse.parent), sizeof(emouse)); + } } #else static void report_touch_input(int updown) { - struct rt_touch_event touch_event; - - if (updown) - { - ts.xp = ts.xp / ts.count; - ts.yp = ts.yp / ts.count; - - if ((touch->calibrating == RT_TRUE) && (touch->calibration_func != RT_NULL)) - { - touch->x = ts.xp; - touch->y = ts.yp; - } - else - { - if (touch->max_x > touch->min_x) - { - touch->x = touch->width * ( ts.xp - touch->min_x ) / (touch->max_x-touch->min_x); - } - else - { - touch->x = touch->width * ( touch->min_x - ts.xp ) / (touch->min_x-touch->max_x); - } - - if (touch->max_y > touch->min_y) - { - touch->y = touch->height * ( ts.yp - touch->min_y ) / (touch->max_y-touch->min_y); - } - else - { - touch->y = touch->height * ( touch->min_y - ts.yp ) / (touch->min_y-touch->max_y); - } - } - - touch_event.x = touch->x; - touch_event.y = touch->y; - touch_event.pressed = 1; - - if (touch->first_down_report == RT_TRUE) - { - if (touch->calibrating != RT_TRUE && touch->eventpost_func) - { - touch->eventpost_func(touch->eventpost_param, &touch_event); - } - } - } - else - { - touch_event.x = touch->x; - touch_event.y = touch->y; - touch_event.pressed = 0; - - if ((touch->calibrating == RT_TRUE) && (touch->calibration_func != RT_NULL)) - { - /* callback function */ - touch->calibration_func(touch_event.x, touch_event.y); - } - - if (touch->calibrating != RT_TRUE && touch->eventpost_func) - { - touch->eventpost_func(touch->eventpost_param, &touch_event); - } - } + struct rt_touch_event touch_event; + + if (updown) + { + ts.xp = ts.xp / ts.count; + ts.yp = ts.yp / ts.count; + + if ((touch->calibrating == RT_TRUE) && (touch->calibration_func != RT_NULL)) + { + touch->x = ts.xp; + touch->y = ts.yp; + } + else + { + if (touch->max_x > touch->min_x) + { + touch->x = touch->width * ( ts.xp - touch->min_x ) / (touch->max_x-touch->min_x); + } + else + { + touch->x = touch->width * ( touch->min_x - ts.xp ) / (touch->min_x-touch->max_x); + } + + if (touch->max_y > touch->min_y) + { + touch->y = touch->height * ( ts.yp - touch->min_y ) / (touch->max_y-touch->min_y); + } + else + { + touch->y = touch->height * ( touch->min_y - ts.yp ) / (touch->min_y-touch->max_y); + } + } + + touch_event.x = touch->x; + touch_event.y = touch->y; + touch_event.pressed = 1; + + if (touch->first_down_report == RT_TRUE) + { + if (touch->calibrating != RT_TRUE && touch->eventpost_func) + { + touch->eventpost_func(touch->eventpost_param, &touch_event); + } + } + } + else + { + touch_event.x = touch->x; + touch_event.y = touch->y; + touch_event.pressed = 0; + + if ((touch->calibrating == RT_TRUE) && (touch->calibration_func != RT_NULL)) + { + /* callback function */ + touch->calibration_func(touch_event.x, touch_event.y); + } + + if (touch->calibrating != RT_TRUE && touch->eventpost_func) + { + touch->eventpost_func(touch->eventpost_param, &touch_event); + } + } } #endif static void touch_timer_fire(void *parameter) { - rt_uint32_t data0; - rt_uint32_t data1; - int updown; + rt_uint32_t data0; + rt_uint32_t data1; + int updown; - data0 = ADCDAT0; - data1 = ADCDAT1; + data0 = ADCDAT0; + data1 = ADCDAT1; - updown = (!(data0 & S3C2410_ADCDAT0_UPDOWN)) && (!(data1 & S3C2410_ADCDAT0_UPDOWN)); + updown = (!(data0 & S3C2410_ADCDAT0_UPDOWN)) && (!(data1 & S3C2410_ADCDAT0_UPDOWN)); - if (updown) - { - if (ts.count != 0) - { - report_touch_input(updown); - } + if (updown) + { + if (ts.count != 0) + { + report_touch_input(updown); + } - ts.xp = 0; - ts.yp = 0; - ts.count = 0; + ts.xp = 0; + ts.yp = 0; + ts.count = 0; - ADCTSC = S3C2410_ADCTSC_PULL_UP_DISABLE | AUTOPST; - ADCCON |= S3C2410_ADCCON_ENABLE_START; - } + ADCTSC = S3C2410_ADCTSC_PULL_UP_DISABLE | AUTOPST; + ADCCON |= S3C2410_ADCCON_ENABLE_START; + } } static void s3c2410_adc_stylus_action(void) { - rt_uint32_t data0; - rt_uint32_t data1; - - data0 = ADCDAT0; - data1 = ADCDAT1; - - ts.xp += data0 & S3C2410_ADCDAT0_XPDATA_MASK; - ts.yp += data1 & S3C2410_ADCDAT1_YPDATA_MASK; - ts.count ++; - - if (ts.count < (1<first_down_report) - { - report_touch_input(1); - ts.xp = 0; - ts.yp = 0; - ts.count = 0; - touch->first_down_report = 0; - } - /* start timer */ - rt_timer_start(touch->poll_timer); - ADCTSC = WAIT4INT(1); - } - - SUBSRCPND |= BIT_SUB_ADC; + rt_uint32_t data0; + rt_uint32_t data1; + + data0 = ADCDAT0; + data1 = ADCDAT1; + + ts.xp += data0 & S3C2410_ADCDAT0_XPDATA_MASK; + ts.yp += data1 & S3C2410_ADCDAT1_YPDATA_MASK; + ts.count ++; + + if (ts.count < (1<first_down_report) + { + report_touch_input(1); + ts.xp = 0; + ts.yp = 0; + ts.count = 0; + touch->first_down_report = 0; + } + /* start timer */ + rt_timer_start(touch->poll_timer); + ADCTSC = WAIT4INT(1); + } + + SUBSRCPND |= BIT_SUB_ADC; } static void s3c2410_intc_stylus_updown(void) { - rt_uint32_t data0; - rt_uint32_t data1; - int updown; - - data0 = ADCDAT0; - data1 = ADCDAT1; - - updown = (!(data0 & S3C2410_ADCDAT0_UPDOWN)) && (!(data1 & S3C2410_ADCDAT0_UPDOWN)); - - /* rt_kprintf("stylus: %s\n", updown? "down" : "up"); */ - - if (updown) - { - touch_timer_fire(0); - } - else - { - /* stop timer */ - rt_timer_stop(touch->poll_timer); - touch->first_down_report = RT_TRUE; - if (ts.xp >= 0 && ts.yp >= 0) - { - report_touch_input(updown); - } - ts.count = 0; - ADCTSC = WAIT4INT(0); - } - - SUBSRCPND |= BIT_SUB_TC; + rt_uint32_t data0; + rt_uint32_t data1; + int updown; + + data0 = ADCDAT0; + data1 = ADCDAT1; + + updown = (!(data0 & S3C2410_ADCDAT0_UPDOWN)) && (!(data1 & S3C2410_ADCDAT0_UPDOWN)); + + /* rt_kprintf("stylus: %s\n", updown? "down" : "up"); */ + + if (updown) + { + touch_timer_fire(0); + } + else + { + /* stop timer */ + rt_timer_stop(touch->poll_timer); + touch->first_down_report = RT_TRUE; + if (ts.xp >= 0 && ts.yp >= 0) + { + report_touch_input(updown); + } + ts.count = 0; + ADCTSC = WAIT4INT(0); + } + + SUBSRCPND |= BIT_SUB_TC; } static void rt_touch_handler(int irqno) { - if (SUBSRCPND & BIT_SUB_ADC) - { - /* INT_SUB_ADC */ - s3c2410_adc_stylus_action(); - } - - if (SUBSRCPND & BIT_SUB_TC) - { - /* INT_SUB_TC */ - s3c2410_intc_stylus_updown(); - } - - /* clear interrupt */ - INTPND |= (1ul << INTADC); + if (SUBSRCPND & BIT_SUB_ADC) + { + /* INT_SUB_ADC */ + s3c2410_adc_stylus_action(); + } + + if (SUBSRCPND & BIT_SUB_TC) + { + /* INT_SUB_TC */ + s3c2410_intc_stylus_updown(); + } + + /* clear interrupt */ + INTPND |= (1ul << INTADC); } /* RT-Thread Device Interface */ static rt_err_t rtgui_touch_init(rt_device_t dev) { - /* init touch screen structure */ - rt_memset(&ts, 0, sizeof(struct s3c2410ts)); + /* init touch screen structure */ + rt_memset(&ts, 0, sizeof(struct s3c2410ts)); - ts.delay = 50000; - ts.presc = 9; - ts.shift = 2; - ts.count = 0; - ts.xp = ts.yp = 0; + ts.delay = 50000; + ts.presc = 9; + ts.shift = 2; + ts.count = 0; + ts.xp = ts.yp = 0; - ADCCON = S3C2410_ADCCON_PRSCEN | S3C2410_ADCCON_PRSCVL(ts.presc); - ADCDLY = ts.delay; + ADCCON = S3C2410_ADCCON_PRSCEN | S3C2410_ADCCON_PRSCVL(ts.presc); + ADCDLY = ts.delay; - ADCTSC = WAIT4INT(0); + ADCTSC = WAIT4INT(0); - rt_hw_interrupt_install(INTADC, rt_touch_handler, RT_NULL , "INTADC"); - rt_hw_interrupt_umask(INTADC); + rt_hw_interrupt_install(INTADC, rt_touch_handler, RT_NULL , "INTADC"); + rt_hw_interrupt_umask(INTADC); - /* clear interrupt */ - INTPND |= (1ul << INTADC); + /* clear interrupt */ + INTPND |= (1ul << INTADC); - SUBSRCPND |= BIT_SUB_TC; - SUBSRCPND |= BIT_SUB_ADC; + SUBSRCPND |= BIT_SUB_TC; + SUBSRCPND |= BIT_SUB_ADC; - /* install interrupt handler */ - INTSUBMSK &= ~BIT_SUB_ADC; - INTSUBMSK &= ~BIT_SUB_TC; + /* install interrupt handler */ + INTSUBMSK &= ~BIT_SUB_ADC; + INTSUBMSK &= ~BIT_SUB_TC; - touch->first_down_report = RT_TRUE; + touch->first_down_report = RT_TRUE; - return RT_EOK; + return RT_EOK; } static rt_err_t rtgui_touch_control(rt_device_t dev, int cmd, void *args) { - switch (cmd) - { - case RT_TOUCH_CALIBRATION: - touch->calibrating = RT_TRUE; - touch->calibration_func = (rt_touch_calibration_func_t)args; - break; - - case RT_TOUCH_NORMAL: - touch->calibrating = RT_FALSE; - break; - - case RT_TOUCH_CALIBRATION_DATA: - { - struct calibration_data *data; - - data = (struct calibration_data *)args; - - /* update */ - touch->min_x = data->min_x; - touch->max_x = data->max_x; - touch->min_y = data->min_y; - touch->max_y = data->max_y; - - /* - rt_kprintf("min_x = %d, max_x = %d, min_y = %d, max_y = %d\n", - touch->min_x, touch->max_x, touch->min_y, touch->max_y); - */ - } - break; - - case RT_TOUCH_EVENTPOST: - touch->eventpost_func = (rt_touch_eventpost_func_t)args; - break; - - case RT_TOUCH_EVENTPOST_PARAM: - touch->eventpost_param = args; - break; - } - - return RT_EOK; + switch (cmd) + { + case RT_TOUCH_CALIBRATION: + touch->calibrating = RT_TRUE; + touch->calibration_func = (rt_touch_calibration_func_t)args; + break; + + case RT_TOUCH_NORMAL: + touch->calibrating = RT_FALSE; + break; + + case RT_TOUCH_CALIBRATION_DATA: + { + struct calibration_data *data; + + data = (struct calibration_data *)args; + + /* update */ + touch->min_x = data->min_x; + touch->max_x = data->max_x; + touch->min_y = data->min_y; + touch->max_y = data->max_y; + + /* + rt_kprintf("min_x = %d, max_x = %d, min_y = %d, max_y = %d\n", + touch->min_x, touch->max_x, touch->min_y, touch->max_y); + */ + } + break; + + case RT_TOUCH_EVENTPOST: + touch->eventpost_func = (rt_touch_eventpost_func_t)args; + break; + + case RT_TOUCH_EVENTPOST_PARAM: + touch->eventpost_param = args; + break; + } + + return RT_EOK; } void rtgui_touch_hw_init(void) { - rt_err_t result = RT_FALSE; - rt_device_t device = RT_NULL; - struct rt_device_graphic_info info; - - touch = (struct rtgui_touch_device *)rt_malloc(sizeof(struct rtgui_touch_device)); - if (touch == RT_NULL) - return; /* no memory yet */ - - /* clear device structure */ - rt_memset(&(touch->parent), 0, sizeof(struct rt_device)); - touch->calibrating = RT_FALSE; - touch->min_x = X_MIN; - touch->max_x = X_MAX; - touch->min_y = Y_MIN; - touch->max_y = Y_MAX; - touch->eventpost_func = RT_NULL; - touch->eventpost_param = RT_NULL; - - /* init device structure */ - touch->parent.type = RT_Device_Class_Unknown; - touch->parent.init = rtgui_touch_init; - touch->parent.control = rtgui_touch_control; - touch->parent.user_data = RT_NULL; - - device = rt_device_find("lcd"); - if (device == RT_NULL) - return; /* no this device */ - - /* get graphic device info */ - result = rt_device_control(device, RTGRAPHIC_CTRL_GET_INFO, &info); - if (result != RT_EOK) - { - - /* get device information failed */ - - return; - } - - touch->width = info.width; - touch->height = info.height; - - /* create 1/8 second timer */ - touch->poll_timer = rt_timer_create("touch", touch_timer_fire, RT_NULL, - RT_TICK_PER_SECOND/8, RT_TIMER_FLAG_PERIODIC); - - /* register touch device to RT-Thread */ - rt_device_register(&(touch->parent), "touch", RT_DEVICE_FLAG_RDWR); + rt_err_t result = RT_FALSE; + rt_device_t device = RT_NULL; + struct rt_device_graphic_info info; + + touch = (struct rtgui_touch_device *)rt_malloc(sizeof(struct rtgui_touch_device)); + if (touch == RT_NULL) + return; /* no memory yet */ + + /* clear device structure */ + rt_memset(&(touch->parent), 0, sizeof(struct rt_device)); + touch->calibrating = RT_FALSE; + touch->min_x = X_MIN; + touch->max_x = X_MAX; + touch->min_y = Y_MIN; + touch->max_y = Y_MAX; + touch->eventpost_func = RT_NULL; + touch->eventpost_param = RT_NULL; + + /* init device structure */ + touch->parent.type = RT_Device_Class_Unknown; + touch->parent.init = rtgui_touch_init; + touch->parent.control = rtgui_touch_control; + touch->parent.user_data = RT_NULL; + + device = rt_device_find("lcd"); + if (device == RT_NULL) + return; /* no this device */ + + /* get graphic device info */ + result = rt_device_control(device, RTGRAPHIC_CTRL_GET_INFO, &info); + if (result != RT_EOK) + { + + /* get device information failed */ + + return; + } + + touch->width = info.width; + touch->height = info.height; + + /* create 1/8 second timer */ + touch->poll_timer = rt_timer_create("touch", touch_timer_fire, RT_NULL, + RT_TICK_PER_SECOND/8, RT_TIMER_FLAG_PERIODIC); + + /* register touch device to RT-Thread */ + rt_device_register(&(touch->parent), "touch", RT_DEVICE_FLAG_RDWR); } diff --git a/bsp/mini2440/rtconfig.h b/bsp/mini2440/rtconfig.h index 8147715c8f..e35b367ba5 100644 --- a/bsp/mini2440/rtconfig.h +++ b/bsp/mini2440/rtconfig.h @@ -5,17 +5,17 @@ // // -#define RT_NAME_MAX 32 +#define RT_NAME_MAX 32 // -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 // // 8 // 32 // 256 // -#define RT_THREAD_PRIORITY_MAX 256 +#define RT_THREAD_PRIORITY_MAX 256 // -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 //
// #define RT_DEBUG // @@ -31,11 +31,11 @@ //
// #define RT_USING_TIMER_SOFT // -#define RT_TIMER_THREAD_PRIO 8 +#define RT_TIMER_THREAD_PRIO 8 // -#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_THREAD_STACK_SIZE 512 // -#define RT_TIMER_TICK_PER_SECOND 10 +#define RT_TIMER_TICK_PER_SECOND 10 //
//
@@ -68,13 +68,13 @@ // #define RT_USING_UART0 // -#define RT_UART_RX_BUFFER_SIZE 64 +#define RT_UART_RX_BUFFER_SIZE 64 //
//
#define RT_USING_CONSOLE // -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 //
//
@@ -84,7 +84,7 @@ // #define FINSH_USING_DESCRIPTION // -#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_THREAD_STACK_SIZE 4096 //
//
@@ -99,22 +99,22 @@ // #define DFS_USING_WORKDIR // -#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEMS_MAX 2 // -#define DFS_FD_MAX 4 +#define DFS_FD_MAX 4 // #define RT_USING_DFS_ELMFAT // // 1 // 2 // -#define RT_DFS_ELM_USE_LFN 1 +#define RT_DFS_ELM_USE_LFN 1 // -#define RT_DFS_ELM_CODE_PAGE 936 +#define RT_DFS_ELM_CODE_PAGE 936 // // #define RT_DFS_ELM_CODE_PAGE_FILE // -#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_MAX_LFN 255 // // #define RT_USING_DFS_YAFFS2 // @@ -124,7 +124,7 @@ // // #define RT_USING_DFS_NFS // -#define RT_NFS_HOST_EXPORT "192.168.1.5:/" +#define RT_NFS_HOST_EXPORT "192.168.1.5:/" //
//
@@ -140,29 +140,29 @@ // #define RT_LWIP_DNS // -#define RT_LWIP_TCP_PCB_NUM 5 +#define RT_LWIP_TCP_PCB_NUM 5 // -#define RT_LWIP_TCP_SND_BUF 8192 +#define RT_LWIP_TCP_SND_BUF 8192 // -#define RT_LWIP_TCP_WND 8192 +#define RT_LWIP_TCP_WND 8192 // // #define RT_LWIP_SNMP // // #define RT_LWIP_DHCP // -#define RT_LWIP_TCP_SEG_NUM 40 +#define RT_LWIP_TCP_SEG_NUM 40 // -#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 // -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 32 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 32 // -#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 +#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 // -#define RT_LWIP_ETHTHREAD_PRIORITY 144 +#define RT_LWIP_ETHTHREAD_PRIORITY 144 // -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 32 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 32 // -#define RT_LWIP_ETHTHREAD_STACKSIZE 512 +#define RT_LWIP_ETHTHREAD_STACKSIZE 512 // #define RT_LWIP_IPADDR "192.168.1.30" // diff --git a/bsp/mini4020/applications/application.c b/bsp/mini4020/applications/application.c index 688055933c..f5a77d8c60 100644 --- a/bsp/mini4020/applications/application.c +++ b/bsp/mini4020/applications/application.c @@ -4,15 +4,15 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2007-11-20 Yi.Qiu add rtgui application - * 2008-6-28 Bernard no rtgui init + * Date Author Notes + * 2007-11-20 Yi.Qiu add rtgui application + * 2008-6-28 Bernard no rtgui init */ /** * @addtogroup mini4020 */ - + /*@{*/ #include @@ -34,54 +34,54 @@ extern void radio_rtgui_init(void); void rt_init_thread_entry(void *parameter) { - int fd; - rt_uint32_t sz; - char buffer[20]; + int fd; + rt_uint32_t sz; + char buffer[20]; #ifdef RT_USING_DFS - dfs_init(); + dfs_init(); #ifdef RT_USING_DFS_ELMFAT - elm_init(); - /* mount sd card fat partition 1 as root directory */ - if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) - { - rt_kprintf("File System initialized!\n"); - - /*Open a file*/ - fd = open("/fattest.txt", O_RDWR|O_CREAT, 0); - if (fd < 0) - { - rt_kprintf("open file for write failed\n"); - return; - } - - sz = write(fd,"Hello RT-Thread!",sizeof("Hello RT-Thread!")); - - if (sz != 0) - { - rt_kprintf("written %d\n",sz); - } - else - rt_kprintf("haven't written\n"); - - lseek(fd, 0, SEEK_SET); - - sz = read(fd, buffer, sizeof(buffer)); - - if (sz != 0) - { - rt_kprintf("READ %d:",sz); - while (sz--) - rt_kprintf("%c",buffer[sz]);//opposite - rt_kprintf("\n"); - } - else - rt_kprintf("haven't read\n"); - - close(fd); - } - else - rt_kprintf("File System initialzation failed!\n"); -#endif + elm_init(); + /* mount sd card fat partition 1 as root directory */ + if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) + { + rt_kprintf("File System initialized!\n"); + + /*Open a file*/ + fd = open("/fattest.txt", O_RDWR|O_CREAT, 0); + if (fd < 0) + { + rt_kprintf("open file for write failed\n"); + return; + } + + sz = write(fd,"Hello RT-Thread!",sizeof("Hello RT-Thread!")); + + if (sz != 0) + { + rt_kprintf("written %d\n",sz); + } + else + rt_kprintf("haven't written\n"); + + lseek(fd, 0, SEEK_SET); + + sz = read(fd, buffer, sizeof(buffer)); + + if (sz != 0) + { + rt_kprintf("READ %d:",sz); + while (sz--) + rt_kprintf("%c",buffer[sz]);//opposite + rt_kprintf("\n"); + } + else + rt_kprintf("haven't read\n"); + + close(fd); + } + else + rt_kprintf("File System initialzation failed!\n"); +#endif #endif } @@ -104,23 +104,23 @@ void rt_led_thread_entry(void *parameter) int rt_application_init(void) { - rt_thread_t init_thread; - rt_thread_t led_thread; - - init_thread = rt_thread_create("init", - rt_init_thread_entry, RT_NULL, - RT_INIT_THREAD_STACK_SIZE, 8, 20); - led_thread = rt_thread_create("led", - rt_led_thread_entry, RT_NULL, - 512, 200, 20); - - if (init_thread != RT_NULL) - rt_thread_startup(init_thread); - - if (led_thread != RT_NULL) - rt_thread_startup(led_thread); - - return 0; + rt_thread_t init_thread; + rt_thread_t led_thread; + + init_thread = rt_thread_create("init", + rt_init_thread_entry, RT_NULL, + RT_INIT_THREAD_STACK_SIZE, 8, 20); + led_thread = rt_thread_create("led", + rt_led_thread_entry, RT_NULL, + 512, 200, 20); + + if (init_thread != RT_NULL) + rt_thread_startup(init_thread); + + if (led_thread != RT_NULL) + rt_thread_startup(led_thread); + + return 0; } /*@}*/ diff --git a/bsp/mini4020/applications/startup.c b/bsp/mini4020/applications/startup.c index 94c0c43a26..6a006dced0 100644 --- a/bsp/mini4020/applications/startup.c +++ b/bsp/mini4020/applications/startup.c @@ -22,12 +22,12 @@ #include #endif -#define SDRAM_BASE 0x30000000 +#define SDRAM_BASE 0x30000000 #ifdef __CC_ARM extern int Image$$RW_RAM1$$ZI$$Limit; #elif (defined (__GNUC__)) - extern unsigned char __bss_end; + extern unsigned char __bss_end; #endif extern void rt_application_init(void); @@ -36,78 +36,78 @@ extern void sd_init(void); void rtthread_startup() { - /* init hardware interrupt */ - rt_hw_interrupt_init(); + /* init hardware interrupt */ + rt_hw_interrupt_init(); - /* init board */ - rt_hw_board_init(); + /* init board */ + rt_hw_board_init(); - /* show version */ - rt_show_version(); - - /* init tick */ - rt_system_tick_init(); + /* show version */ + rt_show_version(); - /* init kernel object */ - rt_system_object_init(); + /* init tick */ + rt_system_tick_init(); - /* init timer system */ - rt_system_timer_init(); + /* init kernel object */ + rt_system_object_init(); - /* init heap memory system */ + /* init timer system */ + rt_system_timer_init(); + + /* init heap memory system */ #ifdef __CC_ARM - rt_system_heap_init((void*)&Image$$RW_RAM1$$ZI$$Limit, (void*)(SDRAM_BASE + 0x200000)); + rt_system_heap_init((void*)&Image$$RW_RAM1$$ZI$$Limit, (void*)(SDRAM_BASE + 0x200000)); #else - rt_system_heap_init(&__bss_end, (void*)0x34000000); + rt_system_heap_init(&__bss_end, (void*)0x34000000); #endif - /* init scheduler system */ - rt_system_scheduler_init(); + /* init scheduler system */ + rt_system_scheduler_init(); #ifdef RT_USING_DEVICE #ifdef RT_USING_DFS - rt_hw_sdcard_init(); + rt_hw_sdcard_init(); #endif #ifdef RT_USING_LWIP - eth_system_device_init(); - rt_hw_dm9161_init(); + eth_system_device_init(); + rt_hw_dm9161_init(); #endif #endif - /* init application */ - rt_application_init(); + /* init application */ + rt_application_init(); #ifdef RT_USING_FINSH - /* init finsh */ - finsh_system_init(); + /* init finsh */ + finsh_system_init(); #ifdef RT_USING_DEVICE - finsh_set_device("uart0"); + finsh_set_device("uart0"); #endif #endif - /* init idle thread */ - rt_thread_idle_init(); + /* init idle thread */ + rt_thread_idle_init(); + + /* start scheduler */ + rt_system_scheduler_start(); - /* start scheduler */ - rt_system_scheduler_start(); + /* never reach here */ + return ; - /* never reach here */ - return ; - } int main() { - /* disable interrupt first */ - rt_hw_interrupt_disable(); + /* disable interrupt first */ + rt_hw_interrupt_disable(); - /* startup RT-Thread RTOS */ - rtthread_startup(); + /* startup RT-Thread RTOS */ + rtthread_startup(); - return 0; + return 0; } diff --git a/bsp/mini4020/drivers/board.c b/bsp/mini4020/drivers/board.c index b77d8faf59..eddfc7d571 100644 --- a/bsp/mini4020/drivers/board.c +++ b/bsp/mini4020/drivers/board.c @@ -21,14 +21,14 @@ void rt_hw_serial_putc(const char c); -#define UART0 ((struct uartport *)UART0_BASE) +#define UART0 ((struct uartport *)UART0_BASE) struct rt_device uart0_device; struct serial_int_rx uart0_int_rx; struct serial_device uart0 = { - UART0, - &uart0_int_rx, - RT_NULL + UART0, + &uart0_int_rx, + RT_NULL }; /** @@ -36,12 +36,12 @@ struct serial_device uart0 = */ void rt_timer_handler(int vector, void *param) { - rt_uint32_t clear_int; - rt_tick_increase(); + rt_uint32_t clear_int; + rt_tick_increase(); - /*Clear timer interrupt*/ - clear_int = *(RP)TIMER_T1ISCR; - *(RP)TIMER_T1ISCR=clear_int; + /*Clear timer interrupt*/ + clear_int = *(RP)TIMER_T1ISCR; + *(RP)TIMER_T1ISCR=clear_int; } /** @@ -49,31 +49,31 @@ void rt_timer_handler(int vector, void *param) */ void rt_serial_handler(int vector, void *param) { - //rt_kprintf("in rt_serial_handler\n"); - rt_int32_t stat = *(RP)UART0_IIR ; - RT_UNUSED char c; - - /*Received data*/ - if (((stat & 0x0E) >> 1) == 0x02) - { - rt_hw_serial_isr(&uart0_device); - } - else - { - /*clear the timeout interrupt*/ - while (uart0.uart_device->lsr & USTAT_RCV_READY) - c = uart0.uart_device->dlbl_fifo.rxfifo; - } + //rt_kprintf("in rt_serial_handler\n"); + rt_int32_t stat = *(RP)UART0_IIR ; + RT_UNUSED char c; + + /*Received data*/ + if (((stat & 0x0E) >> 1) == 0x02) + { + rt_hw_serial_isr(&uart0_device); + } + else + { + /*clear the timeout interrupt*/ + while (uart0.uart_device->lsr & USTAT_RCV_READY) + c = uart0.uart_device->dlbl_fifo.rxfifo; + } } -/** +/** * This function will init led on the board */ static void rt_hw_board_led_init(void) { /* PE3 PE4 PE5 for led */ *(RP)GPIO_PORTE_SEL |=0x38; /* GPIO */ - + *(RP)GPIO_PORTE_DIR &= ~0x38; /* output*/ *(RP)GPIO_PORTE_DATA &= ~0x38; /* low */ @@ -84,15 +84,15 @@ static void rt_hw_board_led_init(void) */ void rt_hw_timer_init(void) { - /*Set timer1*/ - *(RP)TIMER_T1LCR = 880000; - *(RP)TIMER_T1CR = 0x06; + /*Set timer1*/ + *(RP)TIMER_T1LCR = 880000; + *(RP)TIMER_T1CR = 0x06; - rt_hw_interrupt_install(INTSRC_TIMER1, rt_timer_handler, RT_NULL, "tick"); - rt_hw_interrupt_umask(INTSRC_TIMER1); + rt_hw_interrupt_install(INTSRC_TIMER1, rt_timer_handler, RT_NULL, "tick"); + rt_hw_interrupt_umask(INTSRC_TIMER1); - /*Enable timer1*/ - *(RP)TIMER_T1CR |= 0x01; + /*Enable timer1*/ + *(RP)TIMER_T1CR |= 0x01; } /** @@ -100,55 +100,55 @@ void rt_hw_timer_init(void) */ void rt_hw_uart_init(void) { - const rt_int32_t sysclk = 72000000; - - /*Set data bit:8*/ - *(RP)(UART0_LCR) = 0x83; - /*Set baud rate high*/ - *(RP)(UART0_DLBH) = (sysclk/16/115200) >> 8; - /*Set baud rate low*/ - *(RP)(UART0_DLBL) = (sysclk/16/115200) & 0xff; - - *(RP)(UART0_LCR) = 0x83&(~(0x1 << 7)); - - /*Set trigger level*/ - *(RP)(UART0_FCR) = 0x0; - *(RP)(UART0_IER) = 0x0; - - /*Enable rx interrupt*/ - *(RP)(UART0_IER) |= 0x01; - /*Disable tx interrupt*/ - *(RP)(UART0_IER) &= ~(0x1<<1); - - rt_hw_interrupt_install(INTSRC_UART0, rt_serial_handler, RT_NULL, "UART0"); - rt_hw_interrupt_umask(INTSRC_UART0); - /* register uart0 */ - rt_hw_serial_register(&uart0_device, "uart0", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart0); + const rt_int32_t sysclk = 72000000; + + /*Set data bit:8*/ + *(RP)(UART0_LCR) = 0x83; + /*Set baud rate high*/ + *(RP)(UART0_DLBH) = (sysclk/16/115200) >> 8; + /*Set baud rate low*/ + *(RP)(UART0_DLBL) = (sysclk/16/115200) & 0xff; + + *(RP)(UART0_LCR) = 0x83&(~(0x1 << 7)); + + /*Set trigger level*/ + *(RP)(UART0_FCR) = 0x0; + *(RP)(UART0_IER) = 0x0; + + /*Enable rx interrupt*/ + *(RP)(UART0_IER) |= 0x01; + /*Disable tx interrupt*/ + *(RP)(UART0_IER) &= ~(0x1<<1); + + rt_hw_interrupt_install(INTSRC_UART0, rt_serial_handler, RT_NULL, "UART0"); + rt_hw_interrupt_umask(INTSRC_UART0); + /* register uart0 */ + rt_hw_serial_register(&uart0_device, "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart0); } void rt_hw_board_init(void) { - /* initialize uart */ - rt_hw_uart_init(); -// rt_hw_board_led_init(); - rt_hw_timer_init(); + /* initialize uart */ + rt_hw_uart_init(); +// rt_hw_board_led_init(); + rt_hw_timer_init(); } /* write one character to serial, must not trigger interrupt */ void rt_hw_serial_putc(const char c) { - /* - to be polite with serial console add a line feed - to the carriage return character - */ - if (c=='\n') - rt_hw_serial_putc('\r'); + /* + to be polite with serial console add a line feed + to the carriage return character + */ + if (c=='\n') + rt_hw_serial_putc('\r'); - while (!((*(RP)UART0_LSR) & 0x40)); + while (!((*(RP)UART0_LSR) & 0x40)); - *(RP)(UART0_BASE) = c; + *(RP)(UART0_BASE) = c; } /** @@ -158,8 +158,8 @@ void rt_hw_serial_putc(const char c) */ void rt_hw_console_output(const char *str) { - while (*str) - { - rt_hw_serial_putc(*str++); - } + while (*str) + { + rt_hw_serial_putc(*str++); + } } diff --git a/bsp/mini4020/drivers/dm9161.c b/bsp/mini4020/drivers/dm9161.c index 482cd9c268..013070c4e3 100644 --- a/bsp/mini4020/drivers/dm9161.c +++ b/bsp/mini4020/drivers/dm9161.c @@ -18,8 +18,8 @@ #define SPEED_100 100 #define SPEED_1000 1000 /* Duplex, half or full. */ -#define DUPLEX_HALF 0x00 -#define DUPLEX_FULL 0x01 +#define DUPLEX_HALF 0x00 +#define DUPLEX_FULL 0x01 /* * Davicom dm9161EP driver @@ -28,9 +28,9 @@ * nLAN_CS connects to nGCS4 */ -/* #define dm9161_DEBUG 1 */ +/* #define dm9161_DEBUG 1 */ #if DM9161_DEBUG -#define DM9161_TRACE rt_kprintf +#define DM9161_TRACE rt_kprintf #else #define DM9161_TRACE(...) #endif @@ -61,18 +61,18 @@ struct rt_dm9161_eth struct eth_device parent; enum DM9161_TYPE type; - enum DM9161_PHY_mode mode; + enum DM9161_PHY_mode mode; rt_uint8_t imr_all; - rt_uint8_t phy_addr; + rt_uint8_t phy_addr; - rt_uint32_t tx_index; + rt_uint32_t tx_index; rt_uint8_t packet_cnt; /* packet I or II */ rt_uint16_t queue_packet_len; /* queued packet (packet II) */ /* interface address info. */ - rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ }; static struct rt_dm9161_eth dm9161_device; static struct rt_semaphore sem_ack, sem_lock; @@ -81,33 +81,33 @@ void rt_dm9161_isr(int irqno, void *param); static void udelay(unsigned long ns) { - unsigned long i; + unsigned long i; - while (ns--) - { - i = 100; - while (i--); - } + while (ns--) + { + i = 100; + while (i--); + } } static __inline unsigned long sep_emac_read(unsigned int reg) { - void __iomem *emac_base = (void __iomem *)reg; + void __iomem *emac_base = (void __iomem *)reg; - return read_reg(emac_base); + return read_reg(emac_base); } - + /* * Write to a EMAC register. */ static __inline void sep_emac_write(unsigned int reg, unsigned long value) { - void __iomem *emac_base = (void __iomem *)reg; - - write_reg(emac_base,value); + void __iomem *emac_base = (void __iomem *)reg; + + write_reg(emac_base,value); } - + /* ........................... PHY INTERFACE ........................... */ /* CAN DO MAC CONFIGRATION * Enable the MDIO bit in MAC control register @@ -116,12 +116,12 @@ static __inline void sep_emac_write(unsigned int reg, unsigned long value) */ static void enable_mdi(void) //need think more { - unsigned long ctl; + unsigned long ctl; - ctl = sep_emac_read(MAC_CTRL); - sep_emac_write(MAC_CTRL, ctl&(~0x3)); /* enable management port */ + ctl = sep_emac_read(MAC_CTRL); + sep_emac_write(MAC_CTRL, ctl&(~0x3)); /* enable management port */ - return; + return; } /* CANNOT DO MAC CONFIGRATION @@ -129,216 +129,216 @@ static void enable_mdi(void) //need think more */ static void disable_mdi(void) { - unsigned long ctl; - - ctl = sep_emac_read(MAC_CTRL); - sep_emac_write(MAC_CTRL, ctl|(0x3)); /* disable management port */ + unsigned long ctl; - return; + ctl = sep_emac_read(MAC_CTRL); + sep_emac_write(MAC_CTRL, ctl|(0x3)); /* disable management port */ + + return; } /* * Wait until the PHY operation is complete. */ -static __inline void sep_phy_wait(void) +static __inline void sep_phy_wait(void) { - unsigned long timeout = 2; - - while ((sep_emac_read(MAC_MII_STATUS) & 0x2)) - { - timeout--; - if (!timeout) - { - EOUT("sep_ether: MDIO timeout\n"); - break; - } - } - - return; + unsigned long timeout = 2; + + while ((sep_emac_read(MAC_MII_STATUS) & 0x2)) + { + timeout--; + if (!timeout) + { + EOUT("sep_ether: MDIO timeout\n"); + break; + } + } + + return; } - + /* * Write value to the a PHY register * Note: MDI interface is assumed to already have been enabled. */ static void write_phy(unsigned char phy_addr, unsigned char address, unsigned int value) { - unsigned short mii_txdata; - - mii_txdata = value; - sep_emac_write(MAC_MII_ADDRESS,(unsigned long)(address<<8) | phy_addr); - sep_emac_write(MAC_MII_TXDATA ,mii_txdata); - sep_emac_write(MAC_MII_CMD ,0x4); - udelay(40); + unsigned short mii_txdata; - sep_phy_wait(); + mii_txdata = value; + sep_emac_write(MAC_MII_ADDRESS,(unsigned long)(address<<8) | phy_addr); + sep_emac_write(MAC_MII_TXDATA ,mii_txdata); + sep_emac_write(MAC_MII_CMD ,0x4); + udelay(40); - return; + sep_phy_wait(); + + return; } - + /* * Read value stored in a PHY register. * Note: MDI interface is assumed to already have been enabled. */ static void read_phy(unsigned char phy_addr, unsigned char address, unsigned int *value) { - unsigned short mii_rxdata; -// unsigned long mii_status; - - sep_emac_write(MAC_MII_ADDRESS,(unsigned long)(address<<8) | phy_addr); - sep_emac_write(MAC_MII_CMD ,0x2); - udelay(40); - sep_phy_wait(); - - mii_rxdata = sep_emac_read(MAC_MII_RXDATA); - *value = mii_rxdata; - - return; + unsigned short mii_rxdata; +// unsigned long mii_status; + + sep_emac_write(MAC_MII_ADDRESS,(unsigned long)(address<<8) | phy_addr); + sep_emac_write(MAC_MII_CMD ,0x2); + udelay(40); + sep_phy_wait(); + + mii_rxdata = sep_emac_read(MAC_MII_RXDATA); + *value = mii_rxdata; + + return; } /* interrupt service routine */ void rt_dm9161_isr(int irqno, void *param) { - unsigned long intstatus; - rt_uint32_t address; - - mask_irq(INTSRC_MAC); - intstatus = sep_emac_read(MAC_INTSRC); - - sep_emac_write(MAC_INTSRC,intstatus); - - /*Receive complete*/ - if(intstatus & 0x04) - { - eth_device_ready(&(dm9161_device.parent)); - } - /*Receive error*/ - else if(intstatus & 0x08) - { - rt_kprintf("Receive error\n"); - } - /*Transmit complete*/ - else if(intstatus & 0x03) - { - if(dm9161_device.tx_index == 0) - address = (MAC_TX_BD +(MAX_TX_DESCR-2)*8); - else if(dm9161_device.tx_index == 1) - address = (MAC_TX_BD +(MAX_TX_DESCR-1)*8); - else - address = (MAC_TX_BD + dm9161_device.tx_index*8-16); - //printk("free tx skb 0x%x in inter!!\n",lp->txBuffIndex); - sep_emac_write(address,0x0); - } - else if (intstatus & 0x10) - { - rt_kprintf("ROVER ERROR\n"); - } - - while(intstatus) - { - sep_emac_write(MAC_INTSRC,intstatus); - intstatus = sep_emac_read(MAC_INTSRC); - } - - unmask_irq(INTSRC_MAC); + unsigned long intstatus; + rt_uint32_t address; + + mask_irq(INTSRC_MAC); + intstatus = sep_emac_read(MAC_INTSRC); + + sep_emac_write(MAC_INTSRC,intstatus); + + /*Receive complete*/ + if(intstatus & 0x04) + { + eth_device_ready(&(dm9161_device.parent)); + } + /*Receive error*/ + else if(intstatus & 0x08) + { + rt_kprintf("Receive error\n"); + } + /*Transmit complete*/ + else if(intstatus & 0x03) + { + if(dm9161_device.tx_index == 0) + address = (MAC_TX_BD +(MAX_TX_DESCR-2)*8); + else if(dm9161_device.tx_index == 1) + address = (MAC_TX_BD +(MAX_TX_DESCR-1)*8); + else + address = (MAC_TX_BD + dm9161_device.tx_index*8-16); + //printk("free tx skb 0x%x in inter!!\n",lp->txBuffIndex); + sep_emac_write(address,0x0); + } + else if (intstatus & 0x10) + { + rt_kprintf("ROVER ERROR\n"); + } + + while(intstatus) + { + sep_emac_write(MAC_INTSRC,intstatus); + intstatus = sep_emac_read(MAC_INTSRC); + } + + unmask_irq(INTSRC_MAC); } static rt_err_t update_mac_address() { - rt_uint32_t lo,hi; - hi = sep_emac_read(MAC_ADDR1); - lo = sep_emac_read(MAC_ADDR0); - DBOUT("Before MAC: hi=%x lo=%x\n",hi,lo); + rt_uint32_t lo,hi; + hi = sep_emac_read(MAC_ADDR1); + lo = sep_emac_read(MAC_ADDR0); + DBOUT("Before MAC: hi=%x lo=%x\n",hi,lo); - sep_emac_write(MAC_ADDR0,(dm9161_device.dev_addr[2] << 24) | (dm9161_device.dev_addr[3] << 16) | (dm9161_device.dev_addr[4] << 8) | (dm9161_device.dev_addr[5])); - sep_emac_write(MAC_ADDR1,dm9161_device.dev_addr[1]|(dm9161_device.dev_addr[0]<<8)); + sep_emac_write(MAC_ADDR0,(dm9161_device.dev_addr[2] << 24) | (dm9161_device.dev_addr[3] << 16) | (dm9161_device.dev_addr[4] << 8) | (dm9161_device.dev_addr[5])); + sep_emac_write(MAC_ADDR1,dm9161_device.dev_addr[1]|(dm9161_device.dev_addr[0]<<8)); - hi = sep_emac_read(MAC_ADDR1); - lo = sep_emac_read(MAC_ADDR0); - DBOUT("After MAC: hi=%x lo=%x\n",hi,lo); + hi = sep_emac_read(MAC_ADDR1); + lo = sep_emac_read(MAC_ADDR0); + DBOUT("After MAC: hi=%x lo=%x\n",hi,lo); - return RT_EOK; + return RT_EOK; } static int mii_link_ok(unsigned long phy_id) { - /* first, a dummy read, needed to latch some MII phys */ - unsigned int value; + /* first, a dummy read, needed to latch some MII phys */ + unsigned int value; - read_phy(phy_id, MII_BMSR,&value); - if (value & BMSR_LSTATUS) - return 1; + read_phy(phy_id, MII_BMSR,&value); + if (value & BMSR_LSTATUS) + return 1; - return 0; + return 0; } static void update_link_speed(unsigned short phy_addr) { - unsigned int bmsr, bmcr, lpa, mac_cfg; - unsigned int speed, duplex; - - if (!mii_link_ok(phy_addr)) - { - EOUT("Link Down\n"); - //goto result; - } - - read_phy(phy_addr,MII_BMSR,&bmsr); - read_phy(phy_addr,MII_BMCR,&bmcr); - - if (bmcr & BMCR_ANENABLE) /* AutoNegotiation is enabled */ - { - if (!(bmsr & BMSR_ANEGCOMPLETE)) /* Do nothing - another interrupt generated when negotiation complete */ - goto result; - - read_phy(phy_addr, MII_LPA, &lpa); - - if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF)) - speed = SPEED_100; - else - speed = SPEED_10; - - if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL)) - duplex = DUPLEX_FULL; - else - duplex = DUPLEX_HALF; - } - else - { - speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10; - duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF; - } - - /* Update the MAC */ - mac_cfg = sep_emac_read(MAC_CTRL); - if (speed == SPEED_100) - { - mac_cfg |= 0x800; /* set speed 100 M */ - //bmcr &=(~0x2000); - //write_phy(lp->phy_address, MII_BMCR, bmcr); //将dm9161的速度设为10M - if (duplex == DUPLEX_FULL) /* 100 Full Duplex */ - mac_cfg |= 0x400; - else /* 100 Half Duplex */ - mac_cfg &= (~0x400); - } - else - { - mac_cfg &= (~0x800); /* set speed 10 M */ - - if (duplex == DUPLEX_FULL) /* 10 Full Duplex */ - mac_cfg |= 0x400; - else /* 10 Half Duplex */ - mac_cfg &= (~0x400); - } - - sep_emac_write(MAC_CTRL, mac_cfg); - rt_kprintf("Link now %i M-%s\n", speed, (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex"); - + unsigned int bmsr, bmcr, lpa, mac_cfg; + unsigned int speed, duplex; + + if (!mii_link_ok(phy_addr)) + { + EOUT("Link Down\n"); + //goto result; + } + + read_phy(phy_addr,MII_BMSR,&bmsr); + read_phy(phy_addr,MII_BMCR,&bmcr); + + if (bmcr & BMCR_ANENABLE) /* AutoNegotiation is enabled */ + { + if (!(bmsr & BMSR_ANEGCOMPLETE)) /* Do nothing - another interrupt generated when negotiation complete */ + goto result; + + read_phy(phy_addr, MII_LPA, &lpa); + + if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF)) + speed = SPEED_100; + else + speed = SPEED_10; + + if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL)) + duplex = DUPLEX_FULL; + else + duplex = DUPLEX_HALF; + } + else + { + speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10; + duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF; + } + + /* Update the MAC */ + mac_cfg = sep_emac_read(MAC_CTRL); + if (speed == SPEED_100) + { + mac_cfg |= 0x800; /* set speed 100 M */ + //bmcr &=(~0x2000); + //write_phy(lp->phy_address, MII_BMCR, bmcr); //将dm9161的速度设为10M + if (duplex == DUPLEX_FULL) /* 100 Full Duplex */ + mac_cfg |= 0x400; + else /* 100 Half Duplex */ + mac_cfg &= (~0x400); + } + else + { + mac_cfg &= (~0x800); /* set speed 10 M */ + + if (duplex == DUPLEX_FULL) /* 10 Full Duplex */ + mac_cfg |= 0x400; + else /* 10 Half Duplex */ + mac_cfg &= (~0x400); + } + + sep_emac_write(MAC_CTRL, mac_cfg); + rt_kprintf("Link now %i M-%s\n", speed, (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex"); + result: - mac_cfg = sep_emac_read(MAC_CTRL); - DBOUT("After mac_cfg=%d\n",mac_cfg); - - return; + mac_cfg = sep_emac_read(MAC_CTRL); + DBOUT("After mac_cfg=%d\n",mac_cfg); + + return; } static rt_err_t rt_dm9161_open(rt_device_t dev, rt_uint16_t oflag); @@ -346,53 +346,53 @@ static rt_err_t rt_dm9161_open(rt_device_t dev, rt_uint16_t oflag); /* initialize the interface */ static rt_err_t rt_dm9161_init(rt_device_t dev) { - unsigned int phyid1, phyid2; - int detected = -1; - unsigned long phy_id; - unsigned short phy_address = 0; - - while ((detected != 0) && (phy_address < 32)) - { - /* Read the PHY ID registers */ - enable_mdi(); - read_phy(phy_address, MII_PHYSID1, &phyid1); - read_phy(phy_address, MII_PHYSID2, &phyid2); - - disable_mdi(); - - phy_id = (phyid1 << 16) | (phyid2 & 0xfff0); - switch (phy_id) - { - case MII_DM9161_ID: /* Davicom 9161: PHY_ID1 = 0x181, PHY_ID2 = B881 */ - case MII_DM9161A_ID: /* Davicom 9161A: PHY_ID1 = 0x181, PHY_ID2 = B8A0 */ - case MII_RTL8201_ID: /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */ - case MII_BCM5221_ID: /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */ - case MII_DP83847_ID: /* National Semiconductor DP83847: */ - case MII_AC101L_ID: /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */ - case MII_KS8721_ID: /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */ - { - enable_mdi(); - #warning SHOULD SET MAC ADDR - //get_mac_address(dev); /* Get ethernet address and store it in dev->dev_addr */ - update_mac_address(); /* Program ethernet address into MAC */ - - //用哈希寄存器比较当前群播地址，全双工，添加CRC校验，短数据帧进行填充 - sep_emac_write(MAC_CTRL, 0xa413); - #warning SHOULD DETERMIN LINK SPEED - update_link_speed(phy_address); - dm9161_device.phy_addr = phy_address; - disable_mdi(); - break; - } - - } - - phy_address++; - } - - rt_dm9161_open(dev,0); - - return RT_EOK; + unsigned int phyid1, phyid2; + int detected = -1; + unsigned long phy_id; + unsigned short phy_address = 0; + + while ((detected != 0) && (phy_address < 32)) + { + /* Read the PHY ID registers */ + enable_mdi(); + read_phy(phy_address, MII_PHYSID1, &phyid1); + read_phy(phy_address, MII_PHYSID2, &phyid2); + + disable_mdi(); + + phy_id = (phyid1 << 16) | (phyid2 & 0xfff0); + switch (phy_id) + { + case MII_DM9161_ID: /* Davicom 9161: PHY_ID1 = 0x181, PHY_ID2 = B881 */ + case MII_DM9161A_ID: /* Davicom 9161A: PHY_ID1 = 0x181, PHY_ID2 = B8A0 */ + case MII_RTL8201_ID: /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */ + case MII_BCM5221_ID: /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */ + case MII_DP83847_ID: /* National Semiconductor DP83847: */ + case MII_AC101L_ID: /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */ + case MII_KS8721_ID: /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */ + { + enable_mdi(); + #warning SHOULD SET MAC ADDR + //get_mac_address(dev); /* Get ethernet address and store it in dev->dev_addr */ + update_mac_address(); /* Program ethernet address into MAC */ + + //用哈希寄存器比较当前群播地址，全双工，添加CRC校验，短数据帧进行填充 + sep_emac_write(MAC_CTRL, 0xa413); + #warning SHOULD DETERMIN LINK SPEED + update_link_speed(phy_address); + dm9161_device.phy_addr = phy_address; + disable_mdi(); + break; + } + + } + + phy_address++; + } + + rt_dm9161_open(dev,0); + + return RT_EOK; } /* ................................ MAC ................................ */ @@ -402,300 +402,300 @@ static rt_err_t rt_dm9161_init(rt_device_t dev) */ static void sepether_start(void) { - int i; - unsigned int tempaddr; - - sep_emac_write(MAC_TXBD_NUM,MAX_TX_DESCR); - - //初始化发送和接收描述符 - for (i = 0; i < MAX_TX_DESCR; i++) - { - tempaddr=(MAC_TX_BD+i*8); - sep_emac_write(tempaddr,0); - tempaddr=(MAC_TX_BD+i*8+4); - sep_emac_write(tempaddr,0); - } - for (i = 0; i < MAX_RX_DESCR; i++) - { - tempaddr=(MAC_TX_BD + MAX_TX_DESCR*8+i*8); - sep_emac_write(tempaddr,0); - tempaddr=(MAC_TX_BD + MAX_TX_DESCR*8+i*8+4); - sep_emac_write(tempaddr,0); - } - - for (i = 0; i < MAX_RX_DESCR; i++) - { - tempaddr=(MAC_TX_BD + MAX_TX_DESCR*8+i*8); - sep_emac_write(tempaddr,0xc000); - tempaddr=(MAC_TX_BD + MAX_TX_DESCR*8+i*8+4); - sep_emac_write(tempaddr,ESRAM_BASE+ MAX_TX_DESCR*0x600+i*0x600); - } - - /* Set the Wrap bit on the last descriptor */ - tempaddr=(MAC_TX_BD + MAX_TX_DESCR*8+i*8-8); - sep_emac_write(tempaddr,0xe000); - - for (i = 0; i < MAX_TX_DESCR; i++) - { - tempaddr=(MAC_TX_BD+i*8); - sep_emac_write(tempaddr,0x0); - tempaddr=(MAC_TX_BD+i*8+4); - sep_emac_write(tempaddr,ESRAM_BASE+i*0x600); - } - - return; + int i; + unsigned int tempaddr; + + sep_emac_write(MAC_TXBD_NUM,MAX_TX_DESCR); + + //初始化发送和接收描述符 + for (i = 0; i < MAX_TX_DESCR; i++) + { + tempaddr=(MAC_TX_BD+i*8); + sep_emac_write(tempaddr,0); + tempaddr=(MAC_TX_BD+i*8+4); + sep_emac_write(tempaddr,0); + } + for (i = 0; i < MAX_RX_DESCR; i++) + { + tempaddr=(MAC_TX_BD + MAX_TX_DESCR*8+i*8); + sep_emac_write(tempaddr,0); + tempaddr=(MAC_TX_BD + MAX_TX_DESCR*8+i*8+4); + sep_emac_write(tempaddr,0); + } + + for (i = 0; i < MAX_RX_DESCR; i++) + { + tempaddr=(MAC_TX_BD + MAX_TX_DESCR*8+i*8); + sep_emac_write(tempaddr,0xc000); + tempaddr=(MAC_TX_BD + MAX_TX_DESCR*8+i*8+4); + sep_emac_write(tempaddr,ESRAM_BASE+ MAX_TX_DESCR*0x600+i*0x600); + } + + /* Set the Wrap bit on the last descriptor */ + tempaddr=(MAC_TX_BD + MAX_TX_DESCR*8+i*8-8); + sep_emac_write(tempaddr,0xe000); + + for (i = 0; i < MAX_TX_DESCR; i++) + { + tempaddr=(MAC_TX_BD+i*8); + sep_emac_write(tempaddr,0x0); + tempaddr=(MAC_TX_BD+i*8+4); + sep_emac_write(tempaddr,ESRAM_BASE+i*0x600); + } + + return; } static rt_err_t rt_dm9161_open(rt_device_t dev, rt_uint16_t oflag) { - unsigned int dsintr; + unsigned int dsintr; + + enable_mdi(); + mask_irq(28); + + sep_emac_write(MAC_INTMASK,0x0); //首先屏蔽中断 + + sepether_start(); - enable_mdi(); - mask_irq(28); + /* Enable PHY interrupt */ + *(volatile unsigned long*)GPIO_PORTA_DIR |= 0x0080 ; //1 stands for in + *(volatile unsigned long*)GPIO_PORTA_SEL |= 0x0080 ; //for common use + *(volatile unsigned long*)GPIO_PORTA_INCTL |= 0x0080; //中断输入方式 + *(volatile unsigned long*)GPIO_PORTA_INTRCTL |= (0x3UL<<14); //中断类型为低电平解发 + *(volatile unsigned long*)GPIO_PORTA_INTRCLR |= 0x0080; //清除中断 + *(volatile unsigned long*)GPIO_PORTA_INTRCLR = 0x0000; //清除中断 - sep_emac_write(MAC_INTMASK,0x0); //首先屏蔽中断 + rt_hw_interrupt_install(INTSRC_MAC, rt_dm9161_isr, RT_NULL, "EMAC"); + enable_irq(INTSRC_EXINT7); - sepether_start(); - /* Enable PHY interrupt */ - *(volatile unsigned long*)GPIO_PORTA_DIR |= 0x0080 ; //1 stands for in - *(volatile unsigned long*)GPIO_PORTA_SEL |= 0x0080 ; //for common use - *(volatile unsigned long*)GPIO_PORTA_INCTL |= 0x0080; //中断输入方式 - *(volatile unsigned long*)GPIO_PORTA_INTRCTL |= (0x3UL<<14); //中断类型为低电平解发 - *(volatile unsigned long*)GPIO_PORTA_INTRCLR |= 0x0080; //清除中断 - *(volatile unsigned long*)GPIO_PORTA_INTRCLR = 0x0000; //清除中断 + read_phy(dm9161_device.phy_addr, MII_DSINTR_REG, &dsintr); + dsintr = dsintr & ~0xf00; /* clear bits 8..11 */ + write_phy(dm9161_device.phy_addr, MII_DSINTR_REG, dsintr); - rt_hw_interrupt_install(INTSRC_MAC, rt_dm9161_isr, RT_NULL, "EMAC"); - enable_irq(INTSRC_EXINT7); + update_link_speed(dm9161_device.phy_addr); - read_phy(dm9161_device.phy_addr, MII_DSINTR_REG, &dsintr); - dsintr = dsintr & ~0xf00; /* clear bits 8..11 */ - write_phy(dm9161_device.phy_addr, MII_DSINTR_REG, dsintr); + /************************************************************************************/ + /* Enable MAC interrupts */ + sep_emac_write(MAC_INTMASK,0xff); //open中断 + sep_emac_write(MAC_INTSRC,0xff); //clear all mac irq + unmask_irq(28); + disable_mdi(); - update_link_speed(dm9161_device.phy_addr); - - - /************************************************************************************/ - /* Enable MAC interrupts */ - sep_emac_write(MAC_INTMASK,0xff); //open中断 - sep_emac_write(MAC_INTSRC,0xff); //clear all mac irq - unmask_irq(28); - disable_mdi(); - - rt_kprintf("SEP4020 ethernet interface open!\n\r"); + rt_kprintf("SEP4020 ethernet interface open!\n\r"); - return RT_EOK; + return RT_EOK; } static rt_err_t rt_dm9161_close(rt_device_t dev) { - rt_kprintf("SEP4020 ethernet interface close!\n\r"); - - /* Disable Receiver and Transmitter */ - disable_mdi(); - #warning disable ether; - -// INT_ENABLE(28); - /* Disable PHY interrupt */ -// disable_phyirq(dev); - - /* Disable MAC interrupts */ - sep_emac_write(MAC_INTMASK,0); //屏蔽中断 - -// INT_DISABLE(28); - - return RT_EOK; + rt_kprintf("SEP4020 ethernet interface close!\n\r"); + + /* Disable Receiver and Transmitter */ + disable_mdi(); + #warning disable ether; + +// INT_ENABLE(28); + /* Disable PHY interrupt */ +// disable_phyirq(dev); + + /* Disable MAC interrupts */ + sep_emac_write(MAC_INTMASK,0); //屏蔽中断 + +// INT_DISABLE(28); + + return RT_EOK; } static rt_size_t rt_dm9161_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); + rt_set_errno(-RT_ENOSYS); - return 0; + return 0; } static rt_size_t rt_dm9161_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); + rt_set_errno(-RT_ENOSYS); - return 0; + return 0; } static rt_err_t rt_dm9161_control(rt_device_t dev, int cmd, void *args) { - return RT_EOK; + return RT_EOK; } /* ethernet device interface */ /* transmit packet. */ rt_err_t rt_dm9161_tx( rt_device_t dev, struct pbuf* p) { - rt_uint8_t i; - rt_uint32_t length = 0; - struct pbuf *q; - unsigned long address; - unsigned long tmp_tx_bd; - - /* lock DM9000 device */ -// rt_sem_take(&sem_lock, RT_WAITING_FOREVER); - - /* disable dm9000a interrupt */ - #warning SHOULD DISABLE INTEERUPT? - - /*Search for available BD*/ - for (i = 0;ipayload,q->len); - length += q->len; - q = q->next; - } - - #warning SHOULD NOTICE IT'S LENGTH - - length = length << 16; - - if (i == MAX_TX_DESCR - 1) - length |= 0xb800; - else - length |= 0x9800; - - address = (MAC_TX_BD + i*8); - dm9161_device.tx_index = i; - sep_emac_write(address,length); - - //wait for tranfer complete - while(!(sep_emac_read(address)&0x8000)); - - /* unlock DM9000 device */ + rt_uint8_t i; + rt_uint32_t length = 0; + struct pbuf *q; + unsigned long address; + unsigned long tmp_tx_bd; + + /* lock DM9000 device */ +// rt_sem_take(&sem_lock, RT_WAITING_FOREVER); + + /* disable dm9000a interrupt */ + #warning SHOULD DISABLE INTEERUPT? + + /*Search for available BD*/ + for (i = 0;ipayload,q->len); + length += q->len; + q = q->next; + } + + #warning SHOULD NOTICE IT'S LENGTH + + length = length << 16; + + if (i == MAX_TX_DESCR - 1) + length |= 0xb800; + else + length |= 0x9800; + + address = (MAC_TX_BD + i*8); + dm9161_device.tx_index = i; + sep_emac_write(address,length); + + //wait for tranfer complete + while(!(sep_emac_read(address)&0x8000)); + + /* unlock DM9000 device */ // rt_sem_release(&sem_lock); - /* wait ack */ + /* wait ack */ // rt_sem_take(&sem_ack, RT_WAITING_FOREVER); - return RT_EOK; + return RT_EOK; } /* reception packet. */ struct pbuf *rt_dm9161_rx(rt_device_t dev) { - unsigned int temp_rx_bd,address; - rt_uint32_t i = 0; - rt_uint32_t length; - unsigned char *p_recv; - struct pbuf* p = RT_NULL; - - /* lock DM9000 device */ - rt_sem_take(&sem_lock, RT_WAITING_FOREVER); - - while (1) - { - - address = MAC_TX_BD + (MAX_TX_DESCR + i) * 8; - temp_rx_bd = sep_emac_read(address); - - if (!(temp_rx_bd & 0x8000)) - { - length = temp_rx_bd; - length = length >> 16; - - p_recv = (unsigned char *)(ESRAM_BASE + (MAX_TX_DESCR + i) * 0x600); - p = pbuf_alloc(PBUF_LINK,length,PBUF_RAM); - if (p != RT_NULL) - { - struct pbuf *q; - rt_int32_t len; - - for (q = p; q != RT_NULL; q = q->next) - { - rt_memcpy((rt_uint8_t *)(q->payload),p_recv,q->len); - } - } - else - { - rt_kprintf("Droping %d packet \n",length); - } - - if(i == (MAX_RX_DESCR-1)) - { - sep_emac_write(address,0xe000); - i = 0; - } - else - { - sep_emac_write(address,0xc000); - i++; - } - } - else - break; - } - - rt_sem_release(&sem_lock); - - return p; + unsigned int temp_rx_bd,address; + rt_uint32_t i = 0; + rt_uint32_t length; + unsigned char *p_recv; + struct pbuf* p = RT_NULL; + + /* lock DM9000 device */ + rt_sem_take(&sem_lock, RT_WAITING_FOREVER); + + while (1) + { + + address = MAC_TX_BD + (MAX_TX_DESCR + i) * 8; + temp_rx_bd = sep_emac_read(address); + + if (!(temp_rx_bd & 0x8000)) + { + length = temp_rx_bd; + length = length >> 16; + + p_recv = (unsigned char *)(ESRAM_BASE + (MAX_TX_DESCR + i) * 0x600); + p = pbuf_alloc(PBUF_LINK,length,PBUF_RAM); + if (p != RT_NULL) + { + struct pbuf *q; + rt_int32_t len; + + for (q = p; q != RT_NULL; q = q->next) + { + rt_memcpy((rt_uint8_t *)(q->payload),p_recv,q->len); + } + } + else + { + rt_kprintf("Droping %d packet \n",length); + } + + if(i == (MAX_RX_DESCR-1)) + { + sep_emac_write(address,0xe000); + i = 0; + } + else + { + sep_emac_write(address,0xc000); + i++; + } + } + else + break; + } + + rt_sem_release(&sem_lock); + + return p; } void rt_hw_dm9161_init() { - rt_sem_init(&sem_ack, "tx_ack", 1, RT_IPC_FLAG_FIFO); - rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO); - - dm9161_device.type = TYPE_DM9161; - dm9161_device.mode = DM9161_AUTO; - dm9161_device.packet_cnt = 0; - dm9161_device.queue_packet_len = 0; - - /* - * SRAM Tx/Rx pointer automatically return to start address, - * Packet Transmitted, Packet Received - */ - #warning NOTICE: - //dm9161_device.imr_all = IMR_PAR | IMR_PTM | IMR_PRM; - - dm9161_device.dev_addr[0] = 0x01; - dm9161_device.dev_addr[1] = 0x60; - dm9161_device.dev_addr[2] = 0x6E; - dm9161_device.dev_addr[3] = 0x11; - dm9161_device.dev_addr[4] = 0x02; - dm9161_device.dev_addr[5] = 0x0F; - - dm9161_device.parent.parent.init = rt_dm9161_init; - dm9161_device.parent.parent.open = rt_dm9161_open; - dm9161_device.parent.parent.close = rt_dm9161_close; - dm9161_device.parent.parent.read = rt_dm9161_read; - dm9161_device.parent.parent.write = rt_dm9161_write; - dm9161_device.parent.parent.control = rt_dm9161_control; - dm9161_device.parent.parent.user_data = RT_NULL; - - dm9161_device.parent.eth_rx = rt_dm9161_rx; - dm9161_device.parent.eth_tx = rt_dm9161_tx; - - eth_device_init(&(dm9161_device.parent), "e0"); - - /* instal interrupt */ - #warning TODO - //rt_hw_interrupt_install(INTEINT4_7, rt_dm9161_isr, RT_NULL); - //rt_hw_interrupt_umask(INTEINT4_7); + rt_sem_init(&sem_ack, "tx_ack", 1, RT_IPC_FLAG_FIFO); + rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO); + + dm9161_device.type = TYPE_DM9161; + dm9161_device.mode = DM9161_AUTO; + dm9161_device.packet_cnt = 0; + dm9161_device.queue_packet_len = 0; + + /* + * SRAM Tx/Rx pointer automatically return to start address, + * Packet Transmitted, Packet Received + */ + #warning NOTICE: + //dm9161_device.imr_all = IMR_PAR | IMR_PTM | IMR_PRM; + + dm9161_device.dev_addr[0] = 0x01; + dm9161_device.dev_addr[1] = 0x60; + dm9161_device.dev_addr[2] = 0x6E; + dm9161_device.dev_addr[3] = 0x11; + dm9161_device.dev_addr[4] = 0x02; + dm9161_device.dev_addr[5] = 0x0F; + + dm9161_device.parent.parent.init = rt_dm9161_init; + dm9161_device.parent.parent.open = rt_dm9161_open; + dm9161_device.parent.parent.close = rt_dm9161_close; + dm9161_device.parent.parent.read = rt_dm9161_read; + dm9161_device.parent.parent.write = rt_dm9161_write; + dm9161_device.parent.parent.control = rt_dm9161_control; + dm9161_device.parent.parent.user_data = RT_NULL; + + dm9161_device.parent.eth_rx = rt_dm9161_rx; + dm9161_device.parent.eth_tx = rt_dm9161_tx; + + eth_device_init(&(dm9161_device.parent), "e0"); + + /* instal interrupt */ + #warning TODO + //rt_hw_interrupt_install(INTEINT4_7, rt_dm9161_isr, RT_NULL); + //rt_hw_interrupt_umask(INTEINT4_7); } void dm9161a(void) diff --git a/bsp/mini4020/drivers/dm9161.h b/bsp/mini4020/drivers/dm9161.h index babaf05614..5b63508aaa 100644 --- a/bsp/mini4020/drivers/dm9161.h +++ b/bsp/mini4020/drivers/dm9161.h @@ -17,15 +17,15 @@ /* Davicom 9161 PHY */ #define MII_DM9161_ID 0x0181b880 #define MII_DM9161A_ID 0x0181b8a0 - + /* Davicom specific registers */ #define MII_DSCR_REG 16 #define MII_DSCSR_REG 17 #define MII_DSINTR_REG 21 - + /* Intel LXT971A PHY */ #define MII_LXT971A_ID 0x001378E0 - + /* Intel specific registers */ #define MII_ISINTE_REG 18 #define MII_ISINTS_REG 19 @@ -33,41 +33,41 @@ /* Realtek RTL8201 PHY */ #define MII_RTL8201_ID 0x00008200 - + /* Broadcom BCM5221 PHY */ #define MII_BCM5221_ID 0x004061e0 - + /* Broadcom specific registers */ #define MII_BCMINTR_REG 26 - + /* National Semiconductor DP83847 */ #define MII_DP83847_ID 0x20005c30 - + /* Altima AC101L PHY */ #define MII_AC101L_ID 0x00225520 - + /* Micrel KS8721 PHY */ #define MII_KS8721_ID 0x00221610 - + /* ........................................................................ */ - + #define MAX_RBUFF_SZ 0x600 /* 1518 rounded up */ #define MAX_RX_DESCR 20 /* max number of receive buffers */ - + #define MAX_TBUFF_SZ 0x600 /* 1518 rounded up */ #define MAX_TX_DESCR 20 /* max number of receive buffers */ - + #define EMAC_DESC_DONE 0x00000001 /* bit for if DMA is done */ #define EMAC_DESC_WRAP 0x00000002 /* bit for wrap */ - + #define EMAC_BROADCAST 0x80000000 /* broadcast address */ #define EMAC_MULTICAST 0x40000000 /* multicast address */ #define EMAC_UNICAST 0x20000000 /* unicast address */ - -#define DM9161_inb(r) (*(volatile rt_uint8_t *)r) -#define DM9161_outb(r, d) (*(volatile rt_uint8_t *)r = d) -#define DM9161_inw(r) (*(volatile rt_uint16_t *)r) -#define DM9161_outw(r, d) (*(volatile rt_uint16_t *)r = d) + +#define DM9161_inb(r) (*(volatile rt_uint8_t *)r) +#define DM9161_outb(r, d) (*(volatile rt_uint8_t *)r = d) +#define DM9161_inw(r) (*(volatile rt_uint16_t *)r) +#define DM9161_outw(r, d) (*(volatile rt_uint16_t *)r = d) void rt_hw_dm9616_init(void); diff --git a/bsp/mini4020/drivers/lcd.c b/bsp/mini4020/drivers/lcd.c index ca3f30158f..c325764953 100644 --- a/bsp/mini4020/drivers/lcd.c +++ b/bsp/mini4020/drivers/lcd.c @@ -52,7 +52,7 @@ void radio_rtgui_init(void) _rtgui_lcd_driver.bits_per_pixel = 16; _rtgui_lcd_driver.width = 320; _rtgui_lcd_driver.height = 240; - + _rtgui_lcd_driver.ops = &_rtgui_graphic_driver_ops; //_rtgui_lcd_driver.screen_update = lcd_update; diff --git a/bsp/mini4020/drivers/lcdc.h b/bsp/mini4020/drivers/lcdc.h index f00a55ea99..39a88e82e0 100644 --- a/bsp/mini4020/drivers/lcdc.h +++ b/bsp/mini4020/drivers/lcdc.h @@ -28,7 +28,7 @@ #define COLOR (1 << 30) //1为色彩. #define PBSIZE (0 << 28) #define BPIX (4 << 25) //存储器中一个像素对应16bit -#define PIXPOL (0 << 24) //像素极性—设置像素的极性,高有效 //0<<24 +#define PIXPOL (0 << 24) //像素极性—设置像素的极性,高有效 //0<<24 #define FLMPOL (1 << 23) //首行标志极性—设置首行标志的极性,低有效. #define LPPOL (1 << 22) //行脉冲极性—设置行脉冲信号的极性,低有效. #define CLKPOL (0 << 21) //LCD 移位时钟极性—设置LCD 移位时钟的有效沿的极性,下降延有效. diff --git a/bsp/mini4020/drivers/mii.h b/bsp/mini4020/drivers/mii.h index b898b83b74..b58d8bf56f 100644 --- a/bsp/mini4020/drivers/mii.h +++ b/bsp/mini4020/drivers/mii.h @@ -21,7 +21,7 @@ #define MII_EXPANSION 0x06 /* Expansion register */ #define MII_CTRL1000 0x09 /* 1000BASE-T control */ #define MII_STAT1000 0x0a /* 1000BASE-T status */ -#define MII_ESTATUS 0x0f /* Extended Status */ +#define MII_ESTATUS 0x0f /* Extended Status */ #define MII_DCOUNTER 0x12 /* Disconnect counter */ #define MII_FCSCOUNTER 0x13 /* False carrier counter */ #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ @@ -36,7 +36,7 @@ /* Basic mode control register. */ #define BMCR_RESV 0x003f /* Unused... */ -#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ +#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ #define BMCR_CTST 0x0080 /* Collision test */ #define BMCR_FULLDPLX 0x0100 /* Full duplex */ #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ @@ -55,9 +55,9 @@ #define BMSR_RFAULT 0x0010 /* Remote fault detected */ #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ #define BMSR_RESV 0x00c0 /* Unused... */ -#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ -#define BMSR_100FULL2 0x0200 /* Can do 100BASE-T2 HDX */ -#define BMSR_100HALF2 0x0400 /* Can do 100BASE-T2 FDX */ +#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ +#define BMSR_100FULL2 0x0200 /* Can do 100BASE-T2 HDX */ +#define BMSR_100HALF2 0x0400 /* Can do 100BASE-T2 FDX */ #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ #define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ @@ -84,7 +84,7 @@ #define ADVERTISE_NPAGE 0x8000 /* Next page bit */ #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ - ADVERTISE_CSMA) + ADVERTISE_CSMA) #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ ADVERTISE_100HALF | ADVERTISE_100FULL) @@ -106,8 +106,8 @@ #define LPA_LPACK 0x4000 /* Link partner acked us */ #define LPA_NPAGE 0x8000 /* Next page bit */ -#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) -#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) +#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) +#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) /* Expansion register for auto-negotiation. */ #define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */ @@ -117,8 +117,8 @@ #define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ #define EXPANSION_RESV 0xffe0 /* Unused... */ -#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ -#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ +#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ +#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ /* N-way test register. */ #define NWAYTEST_RESV1 0x00ff /* Unused... */ diff --git a/bsp/mini4020/drivers/sdcard.c b/bsp/mini4020/drivers/sdcard.c index afa6dcecf1..52c3b5cd82 100644 --- a/bsp/mini4020/drivers/sdcard.c +++ b/bsp/mini4020/drivers/sdcard.c @@ -58,7 +58,7 @@ static void delay(U32 j) for (i = 0; i < j; i++) { - /* nothing */ + /* nothing */ } } diff --git a/bsp/mini4020/rtconfig.h b/bsp/mini4020/rtconfig.h index c35134731b..16e4a205e1 100644 --- a/bsp/mini4020/rtconfig.h +++ b/bsp/mini4020/rtconfig.h @@ -3,16 +3,16 @@ #define __RTTHREAD_CFG_H__ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 256 +#define RT_THREAD_PRIORITY_MAX 256 /* Tick per Second */ -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 /* SECTION: RT_DEBUG */ /* Thread Debug */ @@ -28,9 +28,9 @@ /* Using Software Timer */ #define RT_USING_TIMER_SOFT -#define RT_TIMER_THREAD_PRIO 8 -#define RT_TIMER_THREAD_STACK_SIZE 512 -#define RT_TIMER_TICK_PER_SECOND 10 +#define RT_TIMER_THREAD_PRIO 8 +#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_TICK_PER_SECOND 10 /* SECTION: IPC */ /* Using Semaphore */ @@ -68,7 +68,7 @@ /* SECTION: Console options */ /* the buffer size of console */ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 /* SECTION: finsh, a C-Express shell */ /* Using FinSH as Shell*/ @@ -95,11 +95,11 @@ /* #define DFS_USING_WORKDIR */ /* the max number of mounted filesystem */ -#define DFS_FILESYSTEMS_MAX 2 -/* the max number of opened files */ -#define DFS_FD_MAX 16 -/* the max number of cached sector */ -#define DFS_CACHE_MAX_NUM 4 +#define DFS_FILESYSTEMS_MAX 2 +/* the max number of opened files */ +#define DFS_FD_MAX 16 +/* the max number of cached sector */ +#define DFS_CACHE_MAX_NUM 4 /* SECTION: lwip, a lighwight TCP/IP protocol stack */ /* Using lighweight TCP/IP protocol stack */ @@ -122,13 +122,13 @@ #define RT_LWIP_TCP /* the number of simulatenously active TCP connections*/ -#define RT_LWIP_TCP_PCB_NUM 5 +#define RT_LWIP_TCP_PCB_NUM 5 /* TCP sender buffer space */ -#define RT_LWIP_TCP_SND_BUF 1024*10 +#define RT_LWIP_TCP_SND_BUF 1024*10 /* TCP receive window. */ -#define RT_LWIP_TCP_WND 1024 +#define RT_LWIP_TCP_WND 1024 /* Enable SNMP protocol */ /* #define RT_LWIP_SNMP */ @@ -137,50 +137,50 @@ /* #define RT_LWIP_DHCP */ /* ip address of target */ -#define RT_LWIP_IPADDR0 192 -#define RT_LWIP_IPADDR1 168 -#define RT_LWIP_IPADDR2 1 -#define RT_LWIP_IPADDR3 30 +#define RT_LWIP_IPADDR0 192 +#define RT_LWIP_IPADDR1 168 +#define RT_LWIP_IPADDR2 1 +#define RT_LWIP_IPADDR3 30 /* gateway address of target */ -#define RT_LWIP_GWADDR0 192 -#define RT_LWIP_GWADDR1 168 -#define RT_LWIP_GWADDR2 1 -#define RT_LWIP_GWADDR3 1 +#define RT_LWIP_GWADDR0 192 +#define RT_LWIP_GWADDR1 168 +#define RT_LWIP_GWADDR2 1 +#define RT_LWIP_GWADDR3 1 /* mask address of target */ -#define RT_LWIP_MSKADDR0 255 -#define RT_LWIP_MSKADDR1 255 -#define RT_LWIP_MSKADDR2 255 -#define RT_LWIP_MSKADDR3 0 +#define RT_LWIP_MSKADDR0 255 +#define RT_LWIP_MSKADDR1 255 +#define RT_LWIP_MSKADDR2 255 +#define RT_LWIP_MSKADDR3 0 /* the number of blocks for pbuf */ -#define RT_LWIP_PBUF_NUM 16 +#define RT_LWIP_PBUF_NUM 16 /* thread priority of tcpip thread */ -#define RT_LWIP_TCPTHREAD_PRIORITY 128 +#define RT_LWIP_TCPTHREAD_PRIORITY 128 /* mail box size of tcpip thread to wait for */ -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 /* thread stack size of tcpip thread */ -#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 +#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 /* thread priority of ethnetif thread */ -#define RT_LWIP_ETHTHREAD_PRIORITY 144 +#define RT_LWIP_ETHTHREAD_PRIORITY 144 /* mail box size of ethnetif thread to wait for */ -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 32 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 32 /* thread stack size of ethnetif thread */ -#define RT_LWIP_ETHTHREAD_STACKSIZE 1024 +#define RT_LWIP_ETHTHREAD_STACKSIZE 1024 /* SECTION: RTGUI support */ /* using RTGUI support */ /* #define RT_USING_RTGUI */ /* name length of RTGUI object */ -#define RTGUI_NAME_MAX 16 +#define RTGUI_NAME_MAX 16 /* support 16 weight font */ #define RTGUI_USING_FONT16 /* support 16 weight font */ diff --git a/bsp/nios_ii/rtconfig.h b/bsp/nios_ii/rtconfig.h index fcd3799846..6a7d9c7d33 100644 --- a/bsp/nios_ii/rtconfig.h +++ b/bsp/nios_ii/rtconfig.h @@ -6,17 +6,17 @@ #define __RTTHREAD_CFG_H__ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 32 +#define RT_THREAD_PRIORITY_MAX 32 /* Tick per Second */ /* TIMER_TICKS_PER_SEC define in system.h */ -#define RT_TICK_PER_SECOND TIMER_TICKS_PER_SEC +#define RT_TICK_PER_SECOND TIMER_TICKS_PER_SEC /* SECTION: RT_DEBUG */ /* Thread Debug */ @@ -35,9 +35,9 @@ /* Using Software Timer */ /* #define RT_USING_TIMER_SOFT */ -#define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 512 -#define RT_TIMER_TICK_PER_SECOND 10 +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_TICK_PER_SECOND 10 /* SECTION: IPC */ /* Using Semaphore*/ @@ -73,7 +73,7 @@ /* SECTION: Console options */ #define RT_USING_CONSOLE /* the buffer size of console*/ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 #define RT_USING_NEWLIB @@ -92,11 +92,11 @@ #define RT_USING_DFS_ELMFAT /* the max number of mounted filesystem */ -#define DFS_FILESYSTEMS_MAX 2 -/* the max number of opened files */ -#define DFS_FD_MAX 4 -/* the max number of cached sector */ -#define DFS_CACHE_MAX_NUM 4 +#define DFS_FILESYSTEMS_MAX 2 +/* the max number of opened files */ +#define DFS_FD_MAX 4 +/* the max number of cached sector */ +#define DFS_CACHE_MAX_NUM 4 /* SECTION: lwip, a lighwight TCP/IP protocol stack */ //#define RT_USING_LWIP @@ -110,37 +110,37 @@ #define RT_LWIP_DNS /* the number of simulatenously active TCP connections*/ -#define RT_LWIP_TCP_PCB_NUM 5 +#define RT_LWIP_TCP_PCB_NUM 5 /* Using DHCP */ //#define RT_LWIP_DHCP /* ip address of target*/ -#define RT_LWIP_IPADDR0 192 -#define RT_LWIP_IPADDR1 168 -#define RT_LWIP_IPADDR2 1 -#define RT_LWIP_IPADDR3 30 +#define RT_LWIP_IPADDR0 192 +#define RT_LWIP_IPADDR1 168 +#define RT_LWIP_IPADDR2 1 +#define RT_LWIP_IPADDR3 30 /* gateway address of target*/ -#define RT_LWIP_GWADDR0 192 -#define RT_LWIP_GWADDR1 168 -#define RT_LWIP_GWADDR2 1 -#define RT_LWIP_GWADDR3 1 +#define RT_LWIP_GWADDR0 192 +#define RT_LWIP_GWADDR1 168 +#define RT_LWIP_GWADDR2 1 +#define RT_LWIP_GWADDR3 1 /* mask address of target*/ -#define RT_LWIP_MSKADDR0 255 -#define RT_LWIP_MSKADDR1 255 -#define RT_LWIP_MSKADDR2 255 -#define RT_LWIP_MSKADDR3 0 +#define RT_LWIP_MSKADDR0 255 +#define RT_LWIP_MSKADDR1 255 +#define RT_LWIP_MSKADDR2 255 +#define RT_LWIP_MSKADDR3 0 /* tcp thread options */ -#define RT_LWIP_TCPTHREAD_PRIORITY 12 -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4 -#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4 +#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 /* ethernet if thread options */ -#define RT_LWIP_ETHTHREAD_PRIORITY 15 -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4 -#define RT_LWIP_ETHTHREAD_STACKSIZE 512 +#define RT_LWIP_ETHTHREAD_PRIORITY 15 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4 +#define RT_LWIP_ETHTHREAD_STACKSIZE 512 #endif diff --git a/bsp/nrf51822/drivers/board.h b/bsp/nrf51822/drivers/board.h index f5eaa11b63..59f0c03898 100644 --- a/bsp/nrf51822/drivers/board.h +++ b/bsp/nrf51822/drivers/board.h @@ -10,9 +10,9 @@ // Internal SRAM memory size[Kbytes] <16 or 32> // Default: 16 -#define NRF_SRAM_BEGIN (0x20000000) -#define NRF_SRAM_SIZE (16 * 1024) -#define NRF_SRAM_END (NRF_SRAM_BEGIN + NRF_SRAM_SIZE) +#define NRF_SRAM_BEGIN (0x20000000) +#define NRF_SRAM_SIZE (16 * 1024) +#define NRF_SRAM_END (NRF_SRAM_BEGIN + NRF_SRAM_SIZE) //#endif diff --git a/bsp/nrf51822/drivers/uart.c b/bsp/nrf51822/drivers/uart.c index 4c3bd8d6ba..b884be6ebe 100644 --- a/bsp/nrf51822/drivers/uart.c +++ b/bsp/nrf51822/drivers/uart.c @@ -185,10 +185,10 @@ void rt_hw_uart_init(void) rt_ringbuffer_init(&(uart->rx_rb), rx_buffer, sizeof(rx_buffer)); /* device interface */ - uart->parent.init = rt_uart_init; - uart->parent.open = rt_uart_open; + uart->parent.init = rt_uart_init; + uart->parent.open = rt_uart_open; uart->parent.close = rt_uart_close; - uart->parent.read = rt_uart_read; + uart->parent.read = rt_uart_read; uart->parent.write = rt_uart_write; uart->parent.control = RT_NULL; uart->parent.user_data = RT_NULL; diff --git a/bsp/nrf51822/rtconfig.h b/bsp/nrf51822/rtconfig.h index ee7cb6b2f4..66a727c898 100644 --- a/bsp/nrf51822/rtconfig.h +++ b/bsp/nrf51822/rtconfig.h @@ -3,16 +3,16 @@ #define __RTTHREAD_CFG_H__ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 6 +#define RT_NAME_MAX 6 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 8 +#define RT_THREAD_PRIORITY_MAX 8 /* Tick per Second */ -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 /* SECTION: RT_DEBUG */ /* Thread Debug */ @@ -24,13 +24,13 @@ /* Using Hook */ #define RT_USING_HOOK -#define IDLE_THREAD_STACK_SIZE 512 +#define IDLE_THREAD_STACK_SIZE 512 /* Using Software Timer */ /* #define RT_USING_TIMER_SOFT */ -#define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 512 -#define RT_TIMER_TICK_PER_SECOND 100 +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_TICK_PER_SECOND 100 /* SECTION: IPC */ /* Using Semaphore*/ @@ -74,9 +74,9 @@ /* SECTION: Console options */ #define RT_USING_CONSOLE /* the buffer size of console*/ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 // -#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_CONSOLE_DEVICE_NAME "uart0" @@ -84,8 +84,8 @@ #define RT_USING_FINSH /* configure finsh parameters */ #define FINSH_THREAD_PRIORITY 6 -#define FINSH_THREAD_STACK_SIZE 512 -#define FINSH_HISTORY_LINES 1 +#define FINSH_THREAD_STACK_SIZE 512 +#define FINSH_HISTORY_LINES 1 /* Using symbol table */ #define FINSH_USING_SYMTAB #define FINSH_USING_DESCRIPTION diff --git a/bsp/nuvoton_m05x/drivers/board.c b/bsp/nuvoton_m05x/drivers/board.c index bc8028a266..013cdb4719 100644 --- a/bsp/nuvoton_m05x/drivers/board.c +++ b/bsp/nuvoton_m05x/drivers/board.c @@ -38,11 +38,11 @@ void NVIC_Configuration(void) */ static void delay(__IO uint32_t nCount) { - /* Decrement nCount value */ - while (nCount != 0) - { - nCount--; - } + /* Decrement nCount value */ + while (nCount != 0) + { + nCount--; + } } static void rt_hw_system_init(void) @@ -65,7 +65,7 @@ static void rt_hw_system_init(void) /* Set SysTick clock source to HCLK source divide 2 */ CLK_SetSysTickClockSrc(CLK_CLKSEL0_STCLK_S_HCLK_DIV2); - + SYS_LockReg(); } @@ -75,29 +75,29 @@ static void rt_hw_system_init(void) */ void SysTick_Handler(void) { - /* enter interrupt */ - rt_interrupt_enter(); + /* enter interrupt */ + rt_interrupt_enter(); - rt_tick_increase(); + rt_tick_increase(); - /* leave interrupt */ - rt_interrupt_leave(); + /* leave interrupt */ + rt_interrupt_leave(); } /** * This function will initial Nuvoton board. */ void rt_hw_board_init() { - /* NVIC Configuration */ - NVIC_Configuration(); + /* NVIC Configuration */ + NVIC_Configuration(); /* Configure the system clock */ rt_hw_system_init(); - /* Configure the SysTick */ - SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + /* Configure the SysTick */ + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); - /* Initial usart deriver, and set console device */ - rt_hw_usart_init(); + /* Initial usart deriver, and set console device */ + rt_hw_usart_init(); #ifdef RT_USING_HEAP rt_system_heap_init((void *)M05X_SRAM_BEGIN, (void *)M05X_SRAM_END); #endif diff --git a/bsp/nuvoton_m05x/drivers/led.h b/bsp/nuvoton_m05x/drivers/led.h index c48b64c4f6..a98a32f6a3 100644 --- a/bsp/nuvoton_m05x/drivers/led.h +++ b/bsp/nuvoton_m05x/drivers/led.h @@ -15,7 +15,7 @@ #include #include "M051Series.h" -void rt_hw_led_on(void); +void rt_hw_led_on(void); void rt_hw_led_off(void); #endif diff --git a/bsp/nuvoton_m05x/drivers/usart.c b/bsp/nuvoton_m05x/drivers/usart.c index 60cb54e8a0..7f521735b6 100644 --- a/bsp/nuvoton_m05x/drivers/usart.c +++ b/bsp/nuvoton_m05x/drivers/usart.c @@ -28,12 +28,12 @@ static rt_err_t m05x_configure(struct rt_serial_device *serial, struct serial_co /* Set P3 multi-function pins for UART0 RXD and TXD */ SYS->P3_MFP &= ~(SYS_MFP_P30_Msk | SYS_MFP_P31_Msk); SYS->P3_MFP |= (SYS_MFP_P30_RXD0 | SYS_MFP_P31_TXD0); - + /* Reset IP */ SYS_ResetModule(UART0_RST); /* Configure UART0 and set UART0 Baudrate */ UART_Open(UART0, cfg->baud_rate); - + /* Enable Interrupt */ UART_EnableInt(UART0, UART_IER_RDA_IEN_Msk); } @@ -71,7 +71,7 @@ static int m05x_putc(struct rt_serial_device *serial, char c) uart = (UART_T *)serial->parent.user_data; if (UART_IS_TX_FULL(uart)) { UART_WAIT_TX_EMPTY(uart); - + } UART_WRITE(uart, c); return 1; diff --git a/bsp/nuvoton_m451/applications/application.c b/bsp/nuvoton_m451/applications/application.c index ba1d5748c3..9c1e57f36d 100644 --- a/bsp/nuvoton_m451/applications/application.c +++ b/bsp/nuvoton_m451/applications/application.c @@ -24,18 +24,18 @@ static void led_thread_entry(void* parameter) { rt_hw_led_init(); - while(1) - { + while(1) + { rt_hw_led_on(); rt_thread_delay(RT_TICK_PER_SECOND); rt_hw_led_off(); rt_thread_delay(RT_TICK_PER_SECOND); - } + } } static void rt_init_thread_entry(void* parameter) { - rt_thread_t led_thread; + rt_thread_t led_thread; /* Initialization RT-Thread Components */ #ifdef RT_USING_COMPONENTS_INIT @@ -44,15 +44,15 @@ static void rt_init_thread_entry(void* parameter) /* Create led thread */ led_thread = rt_thread_create("led", - led_thread_entry, RT_NULL, - 256, 20, 20); + led_thread_entry, RT_NULL, + 256, 20, 20); if(led_thread != RT_NULL) - rt_thread_startup(led_thread); + rt_thread_startup(led_thread); } int rt_application_init() { - rt_thread_t init_thread; + rt_thread_t init_thread; #if (RT_THREAD_PRIORITY_MAX == 32) init_thread = rt_thread_create("init", @@ -64,7 +64,7 @@ int rt_application_init() 512, 80, 20); #endif if(init_thread != RT_NULL) - rt_thread_startup(init_thread); + rt_thread_startup(init_thread); return 0; } diff --git a/bsp/nuvoton_m451/applications/startup.c b/bsp/nuvoton_m451/applications/startup.c index b1f57ceb90..8e8422915e 100644 --- a/bsp/nuvoton_m451/applications/startup.c +++ b/bsp/nuvoton_m451/applications/startup.c @@ -51,11 +51,11 @@ extern int __bss_end; *******************************************************************************/ void assert_failed(uint8_t* file, uint32_t line) { - rt_kprintf("\n\r Wrong parameter value detected on\r\n"); - rt_kprintf(" file %s\r\n", file); - rt_kprintf(" line %d\r\n", line); + rt_kprintf("\n\r Wrong parameter value detected on\r\n"); + rt_kprintf(" file %s\r\n", file); + rt_kprintf(" line %d\r\n", line); - while (1) ; + while (1) ; } /** @@ -63,31 +63,31 @@ void assert_failed(uint8_t* file, uint32_t line) */ void rtthread_startup(void) { - /* init board */ - rt_hw_board_init(); + /* init board */ + rt_hw_board_init(); - /* show version */ - rt_show_version(); + /* show version */ + rt_show_version(); - /* init tick */ - rt_system_tick_init(); + /* init tick */ + rt_system_tick_init(); - /* init kernel object */ - rt_system_object_init(); + /* init kernel object */ + rt_system_object_init(); - /* init timer system */ - rt_system_timer_init(); + /* init timer system */ + rt_system_timer_init(); #ifdef RT_USING_HEAP rt_system_heap_init((void*)M451_SRAM_BEGIN, (void*)M451_SRAM_END); #endif - /* init scheduler system */ - rt_system_scheduler_init(); + /* init scheduler system */ + rt_system_scheduler_init(); + + /* init application */ + rt_application_init(); - /* init application */ - rt_application_init(); - /* Set finsh device */ #ifdef RT_USING_FINSH finsh_system_init(); @@ -97,25 +97,25 @@ void rtthread_startup(void) /* init timer thread */ rt_system_timer_thread_init(); - /* init idle thread */ - rt_thread_idle_init(); + /* init idle thread */ + rt_thread_idle_init(); - /* start scheduler */ - rt_system_scheduler_start(); + /* start scheduler */ + rt_system_scheduler_start(); - /* never reach here */ - return ; + /* never reach here */ + return ; } int main(void) { - /* disable interrupt first */ - rt_hw_interrupt_disable(); + /* disable interrupt first */ + rt_hw_interrupt_disable(); - /* startup RT-Thread RTOS */ - rtthread_startup(); + /* startup RT-Thread RTOS */ + rtthread_startup(); - return 0; + return 0; } /*@}*/ diff --git a/bsp/nuvoton_m451/drivers/board.c b/bsp/nuvoton_m451/drivers/board.c index 39dbd04c62..9ab8d97b27 100644 --- a/bsp/nuvoton_m451/drivers/board.c +++ b/bsp/nuvoton_m451/drivers/board.c @@ -38,11 +38,11 @@ void NVIC_Configuration(void) */ static void delay(__IO uint32_t nCount) { - /* Decrement nCount value */ - while (nCount != 0) - { - nCount--; - } + /* Decrement nCount value */ + while (nCount != 0) + { + nCount--; + } } static void rt_hw_system_init(void) @@ -52,7 +52,7 @@ static void rt_hw_system_init(void) /*---------------------------------------------------------------------------------------------------------*/ /* Unlock protected registers */ SYS_UnlockReg(); - + /* Enable HIRC clock (Internal RC 22.1184MHz) */ CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk); @@ -73,7 +73,7 @@ static void rt_hw_system_init(void) /* Set SysTick clock source to HCLK source divide 2 */ CLK_SetSysTickClockSrc(CLK_CLKSEL0_STCLKSEL_HCLK_DIV2); - + /* Lock protected registers */ SYS_LockReg(); } @@ -84,34 +84,34 @@ static void rt_hw_system_init(void) */ void SysTick_Handler(void) { - /* enter interrupt */ - rt_interrupt_enter(); + /* enter interrupt */ + rt_interrupt_enter(); - rt_tick_increase(); + rt_tick_increase(); - /* leave interrupt */ - rt_interrupt_leave(); + /* leave interrupt */ + rt_interrupt_leave(); } /** * This function will initial Nuvoton board. */ void rt_hw_board_init() { - /* NVIC Configuration */ - NVIC_Configuration(); + /* NVIC Configuration */ + NVIC_Configuration(); /* Configure the system clock */ rt_hw_system_init(); - /* Configure the SysTick */ - SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + /* Configure the SysTick */ + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); - /* Initial usart deriver, and set console device */ - rt_hw_usart_init(); + /* Initial usart deriver, and set console device */ + rt_hw_usart_init(); #ifdef RT_USING_CONSOLE - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); #endif - /* Call components board initial (use INIT_BOARD_EXPORT()) */ + /* Call components board initial (use INIT_BOARD_EXPORT()) */ #ifdef RT_USING_COMPONENTS_INIT rt_components_board_init(); #endif diff --git a/bsp/nuvoton_m451/drivers/board.h b/bsp/nuvoton_m451/drivers/board.h index 3aba14d32e..93588253c0 100644 --- a/bsp/nuvoton_m451/drivers/board.h +++ b/bsp/nuvoton_m451/drivers/board.h @@ -18,7 +18,7 @@ /* board configuration */ // Internal SRAM memory size[Kbytes] -// Default: 64 +// Default: 64 #define M451_SRAM_SIZE 32 #define M451_SRAM_END (0x20000000 + M451_SRAM_SIZE * 1024) diff --git a/bsp/nuvoton_m451/drivers/led.h b/bsp/nuvoton_m451/drivers/led.h index e4c1eb7ce9..730e82c0c6 100644 --- a/bsp/nuvoton_m451/drivers/led.h +++ b/bsp/nuvoton_m451/drivers/led.h @@ -15,7 +15,7 @@ #include #include "M451Series.h" -void rt_hw_led_on(void); +void rt_hw_led_on(void); void rt_hw_led_off(void); int rt_hw_led_init(void); diff --git a/bsp/nuvoton_m451/drivers/usart.c b/bsp/nuvoton_m451/drivers/usart.c index 1ee0ded403..e0644a4828 100644 --- a/bsp/nuvoton_m451/drivers/usart.c +++ b/bsp/nuvoton_m451/drivers/usart.c @@ -20,20 +20,20 @@ static rt_err_t m451_configure(struct rt_serial_device *serial, struct serial_co if (uart == UART0) { /* Enable UART module clock */ CLK_EnableModuleClock(UART0_MODULE); - + /* Select UART module clock source as HXT and UART module clock divider as 1 */ CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1)); - + /* Set PD multi-function pins for UART0 RXD(PD.0) and TXD(PD.1) */ SYS->GPD_MFPL &= ~(SYS_GPD_MFPL_PD0MFP_Msk | SYS_GPD_MFPL_PD1MFP_Msk); SYS->GPD_MFPL |= (SYS_GPD_MFPL_PD0MFP_UART0_RXD | SYS_GPD_MFPL_PD1MFP_UART0_TXD); - + /* Reset UART module */ SYS_ResetModule(UART0_RST); - + /* Configure UART0 and set UART0 Baudrate */ UART_Open(UART0, cfg->baud_rate); - + /* Enable Interrupt */ UART_EnableInt(UART0, UART_INTEN_RDAIEN_Msk); } diff --git a/bsp/nuvoton_m451/rtconfig.h b/bsp/nuvoton_m451/rtconfig.h index b47eb84c59..61f0496a22 100644 --- a/bsp/nuvoton_m451/rtconfig.h +++ b/bsp/nuvoton_m451/rtconfig.h @@ -3,16 +3,16 @@ #define __RTTHREAD_CFG_H__ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 32 +#define RT_THREAD_PRIORITY_MAX 32 //#define IDLE_THREAD_STACK_SIZE 128 /* Tick per Second */ -#define RT_TICK_PER_SECOND 1000 +#define RT_TICK_PER_SECOND 1000 /* SECTION: RT_DEBUG */ /* Thread Debug */ @@ -26,9 +26,9 @@ /* Using Software Timer */ /* #define RT_USING_TIMER_SOFT */ -#define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 512 -#define RT_TIMER_TICK_PER_SECOND 10 +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_TICK_PER_SECOND 10 /* SECTION: IPC */ /* Using Semaphore*/ @@ -71,9 +71,9 @@ /* SECTION: Console options */ #define RT_USING_CONSOLE /* the buffer size of console*/ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 // -#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_CONSOLE_DEVICE_NAME "uart0" @@ -82,9 +82,9 @@ /* configure finsh parameters */ /* #define FINSH_THREAD_PRIORITY 25 -#define FINSH_THREAD_STACK_SIZE 1024 +#define FINSH_THREAD_STACK_SIZE 1024 #define FINSH_USING_HISTORY 0 -#define FINSH_HISTORY_LINES 1 +#define FINSH_HISTORY_LINES 1 */ /* Using symbol table */ #define FINSH_USING_SYMTAB @@ -100,17 +100,17 @@ /* Reentrancy (thread safe) of the FatFs module. */ #define RT_DFS_ELM_REENTRANT /* Number of volumes (logical drives) to be used. */ -#define RT_DFS_ELM_DRIVES 2 -/* #define RT_DFS_ELM_USE_LFN 1 */ -#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +/* #define RT_DFS_ELM_USE_LFN 1 */ +#define RT_DFS_ELM_MAX_LFN 255 /* Maximum sector size to be handled. */ #define RT_DFS_ELM_MAX_SECTOR_SIZE 512 #define RT_USING_DFS_ROMFS /* the max number of mounted filesystem */ -#define DFS_FILESYSTEMS_MAX 2 -/* the max number of opened files */ -#define DFS_FD_MAX 4 +#define DFS_FILESYSTEMS_MAX 2 +/* the max number of opened files */ +#define DFS_FD_MAX 4 #endif diff --git a/bsp/nuvoton_m487/applications/main.c b/bsp/nuvoton_m487/applications/main.c index 28f91dba97..30d4e53553 100644 --- a/bsp/nuvoton_m487/applications/main.c +++ b/bsp/nuvoton_m487/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/nuvoton_m487/applications/mnt.c b/bsp/nuvoton_m487/applications/mnt.c index d528a7424d..db45518cfb 100644 --- a/bsp/nuvoton_m487/applications/mnt.c +++ b/bsp/nuvoton_m487/applications/mnt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/nuvoton_m487/driver/board.c b/bsp/nuvoton_m487/driver/board.c index 3105de76c3..dead5015d4 100644 --- a/bsp/nuvoton_m487/driver/board.c +++ b/bsp/nuvoton_m487/driver/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -81,9 +81,9 @@ void rt_hw_board_init(void) #endif SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); - - NVIC_SetPriorityGrouping(7); - + + NVIC_SetPriorityGrouping(7); + #ifdef RT_USING_COMPONENTS_INIT rt_components_board_init(); #endif diff --git a/bsp/nuvoton_m487/driver/board.h b/bsp/nuvoton_m487/driver/board.h index 8db57161ad..db972776f0 100644 --- a/bsp/nuvoton_m487/driver/board.h +++ b/bsp/nuvoton_m487/driver/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/nuvoton_m487/driver/drv_emac.c b/bsp/nuvoton_m487/driver/drv_emac.c index a12ba9ba37..cdd229cf51 100644 --- a/bsp/nuvoton_m487/driver/drv_emac.c +++ b/bsp/nuvoton_m487/driver/drv_emac.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -101,7 +101,7 @@ static void init_tx_desc(void) cur_tx_desc_ptr = fin_tx_desc_ptr = &tx_desc[0]; - for(i = 0; i < TX_DESCRIPTOR_NUM; i++) + for(i = 0; i < TX_DESCRIPTOR_NUM; i++) { tx_desc[i].status1 = TXFD_PADEN | TXFD_CRCAPP | TXFD_INTEN; tx_desc[i].buf = (rt_uint8_t*)tx_buf[i]; @@ -248,7 +248,7 @@ __inline static rt_uint8_t *emac_get_tx_buf(void) __inline static void ETH_trigger_tx(rt_uint16_t length) { struct eth_descriptor volatile *desc; - + cur_tx_desc_ptr->status2 = (unsigned int)length; desc = cur_tx_desc_ptr->next; // in case TX is transmitting and overwrite next pointer before we can update cur_tx_desc_ptr cur_tx_desc_ptr->status1 |= OWNERSHIP_EMAC; @@ -290,7 +290,7 @@ void EMAC_RX_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - + unsigned int status = EMAC->INTSTS; if(status & EMAC_INTSTS_RDUIF_Msk) @@ -523,7 +523,7 @@ static rt_err_t rt_m480_emac_init(rt_device_t dev) #if LWIP_IPV4 && LWIP_IGMP netif_set_igmp_mac_filter(eth.netif, igmp_mac_filter); #endif /* LWIP_IPV4 && LWIP_IGMP */ - + return RT_EOK; } @@ -666,7 +666,7 @@ start: } return p; - + end: if(!(EMAC->INTEN & EMAC_INTEN_RDUIEN_Msk)) { @@ -680,7 +680,7 @@ end: EMAC->INTSTS = EMAC_INTSTS_RXGDIF_Msk; EMAC->INTEN |= EMAC_INTEN_RXGDIEN_Msk; } - + return RT_NULL; } diff --git a/bsp/nuvoton_m487/driver/drv_qspi.c b/bsp/nuvoton_m487/driver/drv_qspi.c index c4dd3cded5..64a7257c68 100644 --- a/bsp/nuvoton_m487/driver/drv_qspi.c +++ b/bsp/nuvoton_m487/driver/drv_qspi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -259,7 +259,7 @@ static int m487_qspi_register_bus(struct m487_qspi *spi_bus, const char *name) static int rt_hw_qspi_init(void) { #ifdef USEING_QSPI0 - m487_qspi_register_bus(&qspi0, "qspi0"); + m487_qspi_register_bus(&qspi0, "qspi0"); #endif return 0; diff --git a/bsp/nuvoton_m487/driver/drv_spiflash.c b/bsp/nuvoton_m487/driver/drv_spiflash.c index 488df7ba42..d1cf5bfc8e 100644 --- a/bsp/nuvoton_m487/driver/drv_spiflash.c +++ b/bsp/nuvoton_m487/driver/drv_spiflash.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/nuvoton_m487/driver/drv_uart.c b/bsp/nuvoton_m487/driver/drv_uart.c index af527abe53..d6ab246b0b 100644 --- a/bsp/nuvoton_m487/driver/drv_uart.c +++ b/bsp/nuvoton_m487/driver/drv_uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/nuvoton_m487/driver/drv_uart.h b/bsp/nuvoton_m487/driver/drv_uart.h index 9eb0077e2f..81ec7ff7c4 100644 --- a/bsp/nuvoton_m487/driver/drv_uart.h +++ b/bsp/nuvoton_m487/driver/drv_uart.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/nuvoton_nuc472/applications/application.c b/bsp/nuvoton_nuc472/applications/application.c index 8a5cb26fdf..688508b795 100644 --- a/bsp/nuvoton_nuc472/applications/application.c +++ b/bsp/nuvoton_nuc472/applications/application.c @@ -17,7 +17,7 @@ int main(void) extern void rt_hw_nuc472_emac_init(void); rt_hw_nuc472_emac_init(); #endif /* RT_USING_LWIP */ - + while(1) { rt_thread_delay(RT_TICK_PER_SECOND); diff --git a/bsp/nuvoton_nuc472/rtconfig.h b/bsp/nuvoton_nuc472/rtconfig.h index af9eacbef5..74ce409b76 100644 --- a/bsp/nuvoton_nuc472/rtconfig.h +++ b/bsp/nuvoton_nuc472/rtconfig.h @@ -3,16 +3,16 @@ #define __RTTHREAD_CFG_H__ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 32 +#define RT_THREAD_PRIORITY_MAX 32 /* Tick per Second */ -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 /* SECTION: RT_DEBUG */ /* Thread Debug */ @@ -27,9 +27,9 @@ /* Using Software Timer */ /* #define RT_USING_TIMER_SOFT */ -#define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 512 -#define RT_TIMER_TICK_PER_SECOND 10 +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_TICK_PER_SECOND 10 /* SECTION: IPC */ /* Using Semaphore*/ @@ -72,9 +72,9 @@ /* SECTION: Console options */ #define RT_USING_CONSOLE /* the buffer size of console*/ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 // -#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_CONSOLE_DEVICE_NAME "uart0" /* SECTION: finsh, a C-Express shell */ #define RT_USING_FINSH @@ -99,17 +99,17 @@ /* Reentrancy (thread safe) of the FatFs module. */ #define RT_DFS_ELM_REENTRANT /* Number of volumes (logical drives) to be used. */ -#define RT_DFS_ELM_DRIVES 2 -/* #define RT_DFS_ELM_USE_LFN 1 */ -/* #define RT_DFS_ELM_CODE_PAGE 936 */ -#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +/* #define RT_DFS_ELM_USE_LFN 1 */ +/* #define RT_DFS_ELM_CODE_PAGE 936 */ +#define RT_DFS_ELM_MAX_LFN 255 /* Maximum sector size to be handled. */ #define RT_DFS_ELM_MAX_SECTOR_SIZE 512 /* the max number of mounted filesystem */ -#define DFS_FILESYSTEMS_MAX 2 -/* the max number of opened files */ -#define DFS_FD_MAX 4 +#define DFS_FILESYSTEMS_MAX 2 +/* the max number of opened files */ +#define DFS_FD_MAX 4 /* SECTION: lwip, a lighwight TCP/IP protocol stack */ #define RT_USING_LWIP @@ -123,7 +123,7 @@ #define RT_LWIP_DNS /* the number of simulatenously active TCP connections*/ -#define RT_LWIP_TCP_PCB_NUM 5 +#define RT_LWIP_TCP_PCB_NUM 5 /* Using DHCP */ /* #define RT_LWIP_DHCP */ @@ -138,25 +138,25 @@ #define RT_LWIP_MSKADDR "255.255.255.0" /* tcp thread options */ -#define RT_LWIP_TCPTHREAD_PRIORITY 12 -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 10 -#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 10 +#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 /* ethernet if thread options */ -#define RT_LWIP_ETHTHREAD_PRIORITY 15 -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 10 -#define RT_LWIP_ETHTHREAD_STACKSIZE 512 +#define RT_LWIP_ETHTHREAD_PRIORITY 15 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 10 +#define RT_LWIP_ETHTHREAD_STACKSIZE 512 /* TCP sender buffer space */ -#define RT_LWIP_TCP_SND_BUF 8192 +#define RT_LWIP_TCP_SND_BUF 8192 /* TCP receive window. */ -#define RT_LWIP_TCP_WND 8192 +#define RT_LWIP_TCP_WND 8192 /* SECTION: RT-Thread/GUI */ /* #define RT_USING_RTGUI */ /* name length of RTGUI object */ -#define RTGUI_NAME_MAX 12 +#define RTGUI_NAME_MAX 12 /* support 16 weight font */ #define RTGUI_USING_FONT16 /* support Chinese font */ @@ -172,7 +172,7 @@ /* use mouse cursor */ /* #define RTGUI_USING_MOUSE_CURSOR */ /* default font size in RTGUI */ -#define RTGUI_DEFAULT_FONT_SIZE 16 +#define RTGUI_DEFAULT_FONT_SIZE 16 /* image support */ /* #define RTGUI_IMAGE_XPM */ diff --git a/bsp/nv32f100x/app/src/ledapp.c b/bsp/nv32f100x/app/src/ledapp.c index 71009b1af0..129b906a96 100644 --- a/bsp/nv32f100x/app/src/ledapp.c +++ b/bsp/nv32f100x/app/src/ledapp.c @@ -7,7 +7,7 @@ * Date Author Notes * 2017-09-19 Quintin.Z the first version */ - + #include #include #include @@ -21,11 +21,11 @@ void led_thread_entry(void* parameter) { GPIO_Init (GPIOA, GPIO_PTB5_MASK, GPIO_PinOutput); - - while(1) - { + + while(1) + { GPIO_Toggle (GPIOA, GPIO_PTB5_MASK); rt_thread_delay(RT_TICK_PER_SECOND / 10); - } + } } diff --git a/bsp/nv32f100x/board/src/board.c b/bsp/nv32f100x/board/src/board.c index 985c4d256e..372099a6ba 100644 --- a/bsp/nv32f100x/board/src/board.c +++ b/bsp/nv32f100x/board/src/board.c @@ -50,11 +50,11 @@ extern int __bss_end; *******************************************************************************/ void assert_failed(uint8_t* file, uint32_t line) { - rt_kprintf("\n\r Wrong parameter value detected on\r\n"); - rt_kprintf(" file %s\r\n", file); - rt_kprintf(" line %d\r\n", line); + rt_kprintf("\n\r Wrong parameter value detected on\r\n"); + rt_kprintf(" file %s\r\n", file); + rt_kprintf(" line %d\r\n", line); - while (1) ; + while (1) ; } /** @@ -94,7 +94,7 @@ void rt_hw_board_init() rt_console_set_device(RT_CONSOLE_DEVICE_NAME); #endif - + #ifdef RT_USING_HEAP rt_system_heap_init((void*)NV32_SRAM_BEGIN, (void*)NV32_SRAM_END); #endif diff --git a/bsp/nv32f100x/rtconfig.h b/bsp/nv32f100x/rtconfig.h index e5b146528e..24e10c892e 100644 --- a/bsp/nv32f100x/rtconfig.h +++ b/bsp/nv32f100x/rtconfig.h @@ -3,16 +3,16 @@ #define __RTTHREAD_CFG_H__ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 32 +#define RT_THREAD_PRIORITY_MAX 32 /* Tick per Second */ -#define RT_TICK_PER_SECOND 1000 +#define RT_TICK_PER_SECOND 1000 /* SECTION: RT_DEBUG */ /* Thread Debug */ @@ -25,9 +25,9 @@ /* Using Software Timer */ /* #define RT_USING_TIMER_SOFT */ -#define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 512 -#define RT_TIMER_TICK_PER_SECOND 10 +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_TICK_PER_SECOND 10 /* SECTION: IPC */ /* Using Semaphore*/ @@ -73,9 +73,9 @@ #define RT_USING_CONSOLE #define RT_USING_RTTTERMINAL /* the buffer size of console*/ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 // -#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_CONSOLE_DEVICE_NAME "uart0" /* SECTION: finsh, a C-Express shell */ @@ -83,8 +83,8 @@ #define RT_FINSHPROMRT_SIZE 16 /* configure finsh parameters */ #define FINSH_THREAD_PRIORITY 25 -#define FINSH_THREAD_STACK_SIZE 512 -#define FINSH_HISTORY_LINES 1 +#define FINSH_THREAD_STACK_SIZE 512 +#define FINSH_HISTORY_LINES 1 /* Using symbol table */ #define FINSH_USING_SYMTAB //#define FINSH_USING_DESCRIPTION diff --git a/bsp/pic32ethernet/application.c b/bsp/pic32ethernet/application.c index 2a14dd8f3f..ae2238f60b 100644 --- a/bsp/pic32ethernet/application.c +++ b/bsp/pic32ethernet/application.c @@ -29,7 +29,7 @@ void thread_led1_entry(void* parameter) static void thread_led2_entry(void* parameter) { - // configure PORTD.RD2 = output + // configure PORTD.RD2 = output mPORTDSetPinsDigitalOut(BIT_2); while (1) diff --git a/bsp/pic32ethernet/board.c b/bsp/pic32ethernet/board.c index d7d5167998..5a738af8b1 100644 --- a/bsp/pic32ethernet/board.c +++ b/bsp/pic32ethernet/board.c @@ -32,12 +32,12 @@ #pragma config DEBUG = OFF // Debugger Disabled for Starter Kit // The following is used by the main application -#define SYS_FREQ (80000000UL) +#define SYS_FREQ (80000000UL) -#define PB_DIV (1 << ((OSCCON&_OSCCON_PBDIV0_MASK)>>_OSCCON_PBDIV0_POSITION) ) -#define PRESCALE 256 -#define TOGGLES_PER_SEC RT_TICK_PER_SECOND -#define T1_TICK (SYS_FREQ/PB_DIV/PRESCALE/TOGGLES_PER_SEC) +#define PB_DIV (1 << ((OSCCON&_OSCCON_PBDIV0_MASK)>>_OSCCON_PBDIV0_POSITION) ) +#define PRESCALE 256 +#define TOGGLES_PER_SEC RT_TICK_PER_SECOND +#define T1_TICK (SYS_FREQ/PB_DIV/PRESCALE/TOGGLES_PER_SEC) static void rt_hw_show_info(void) { @@ -64,18 +64,18 @@ static void rt_hw_timer_handler(void) void rt_hw_board_init() { // Configure the device for maximum performance, but do not change the PBDIV clock divisor. - // Given the options, this function will change the program Flash wait states, - // RAM wait state and enable prefetch cache, but will not change the PBDIV. + // Given the options, this function will change the program Flash wait states, + // RAM wait state and enable prefetch cache, but will not change the PBDIV. // The PBDIV value is already set via the pragma FPBDIV option above. - SYSTEMConfig(SYS_FREQ, SYS_CFG_WAIT_STATES | SYS_CFG_PCACHE); + SYSTEMConfig(SYS_FREQ, SYS_CFG_WAIT_STATES | SYS_CFG_PCACHE); - /* use DBPRINTF */ - /* rt_hw_console_init(); */ + /* use DBPRINTF */ + /* rt_hw_console_init(); */ - rt_hw_usart_init(); - rt_console_set_device("uart1"); + rt_hw_usart_init(); + rt_console_set_device("uart1"); - rt_hw_show_info(); + rt_hw_show_info(); // enable multi-vector interrupts INTEnableSystemMultiVectoredInt(); @@ -93,7 +93,7 @@ void rt_hw_board_init() ConfigIntTimer1(T1_INT_ON | T1_INT_PRIOR_2); /* Setup the software interrupt. */ - mConfigIntCoreSW0( CSW_INT_ON | CSW_INT_PRIOR_1 | CSW_INT_SUB_PRIOR_0 ); + mConfigIntCoreSW0( CSW_INT_ON | CSW_INT_PRIOR_1 | CSW_INT_SUB_PRIOR_0 ); } void __ISR(_TIMER_1_VECTOR, ipl2) Timer1Handler(void) diff --git a/bsp/pic32ethernet/console.c b/bsp/pic32ethernet/console.c index 587b90ef32..35c6725cf2 100644 --- a/bsp/pic32ethernet/console.c +++ b/bsp/pic32ethernet/console.c @@ -19,8 +19,8 @@ void rt_hw_console_init(void) { - //Initialize the DB_UTILS IO channel -// DBINIT(); + //Initialize the DB_UTILS IO channel +// DBINIT(); } /** diff --git a/bsp/pic32ethernet/rtconfig.h b/bsp/pic32ethernet/rtconfig.h index 5d329788bc..9783379c99 100644 --- a/bsp/pic32ethernet/rtconfig.h +++ b/bsp/pic32ethernet/rtconfig.h @@ -3,16 +3,16 @@ #define __RTTHREAD_CFG_H__ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 32 +#define RT_THREAD_PRIORITY_MAX 32 /* Tick per Second */ -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 /* SECTION: RT_DEBUG */ /* Thread Debug */ @@ -31,9 +31,9 @@ /* Using Software Timer */ /* #define RT_USING_TIMER_SOFT */ -#define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 512 -#define RT_TIMER_TICK_PER_SECOND 10 +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_TICK_PER_SECOND 10 /* SECTION: IPC */ /* Using Semaphore*/ @@ -69,7 +69,7 @@ /* SECTION: Console options */ #define RT_USING_CONSOLE /* the buffer size of console*/ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 //#define RT_USING_NEWLIB @@ -84,11 +84,11 @@ #define RT_USING_DFS_ELMFAT /* the max number of mounted filesystem */ -#define DFS_FILESYSTEMS_MAX 2 -/* the max number of opened files */ -#define DFS_FD_MAX 4 -/* the max number of cached sector */ -#define DFS_CACHE_MAX_NUM 4 +#define DFS_FILESYSTEMS_MAX 2 +/* the max number of opened files */ +#define DFS_FD_MAX 4 +/* the max number of cached sector */ +#define DFS_CACHE_MAX_NUM 4 /* SECTION: lwip, a lighwight TCP/IP protocol stack */ //#define RT_USING_LWIP @@ -102,37 +102,37 @@ #define RT_LWIP_DNS /* the number of simulatenously active TCP connections*/ -#define RT_LWIP_TCP_PCB_NUM 5 +#define RT_LWIP_TCP_PCB_NUM 5 /* Using DHCP */ //#define RT_LWIP_DHCP /* ip address of target*/ -#define RT_LWIP_IPADDR0 192 -#define RT_LWIP_IPADDR1 168 -#define RT_LWIP_IPADDR2 1 -#define RT_LWIP_IPADDR3 30 +#define RT_LWIP_IPADDR0 192 +#define RT_LWIP_IPADDR1 168 +#define RT_LWIP_IPADDR2 1 +#define RT_LWIP_IPADDR3 30 /* gateway address of target*/ -#define RT_LWIP_GWADDR0 192 -#define RT_LWIP_GWADDR1 168 -#define RT_LWIP_GWADDR2 1 -#define RT_LWIP_GWADDR3 1 +#define RT_LWIP_GWADDR0 192 +#define RT_LWIP_GWADDR1 168 +#define RT_LWIP_GWADDR2 1 +#define RT_LWIP_GWADDR3 1 /* mask address of target*/ -#define RT_LWIP_MSKADDR0 255 -#define RT_LWIP_MSKADDR1 255 -#define RT_LWIP_MSKADDR2 255 -#define RT_LWIP_MSKADDR3 0 +#define RT_LWIP_MSKADDR0 255 +#define RT_LWIP_MSKADDR1 255 +#define RT_LWIP_MSKADDR2 255 +#define RT_LWIP_MSKADDR3 0 /* tcp thread options */ -#define RT_LWIP_TCPTHREAD_PRIORITY 12 -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4 -#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4 +#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 /* ethernet if thread options */ -#define RT_LWIP_ETHTHREAD_PRIORITY 15 -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4 -#define RT_LWIP_ETHTHREAD_STACKSIZE 512 +#define RT_LWIP_ETHTHREAD_PRIORITY 15 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4 +#define RT_LWIP_ETHTHREAD_STACKSIZE 512 #endif diff --git a/bsp/pic32ethernet/startup.c b/bsp/pic32ethernet/startup.c index 33ea631e77..16285d8c56 100644 --- a/bsp/pic32ethernet/startup.c +++ b/bsp/pic32ethernet/startup.c @@ -25,61 +25,61 @@ extern void finsh_set_device(const char* device); */ void rtthread_startup(void) { - /* init board */ - rt_hw_board_init(); + /* init board */ + rt_hw_board_init(); - /* show version */ - rt_show_version(); + /* show version */ + rt_show_version(); - /* init tick */ - rt_system_tick_init(); + /* init tick */ + rt_system_tick_init(); - /* init kernel object */ - rt_system_object_init(); + /* init kernel object */ + rt_system_object_init(); - /* init timer system */ - rt_system_timer_init(); + /* init timer system */ + rt_system_timer_init(); #ifdef RT_USING_HEAP /* init memory system */ rt_system_heap_init((void*)&_ramfunc_end, (void*)PIC32_SRAM_END); #endif - /* init scheduler system */ - rt_system_scheduler_init(); + /* init scheduler system */ + rt_system_scheduler_init(); - /* init application */ - rt_application_init(); + /* init application */ + rt_application_init(); #ifdef RT_USING_FINSH - /* init finsh */ - finsh_system_init(); + /* init finsh */ + finsh_system_init(); #ifdef RT_USING_DEVICE - finsh_set_device("uart1"); + finsh_set_device("uart1"); #endif #endif /* init timer thread */ rt_system_timer_thread_init(); - /* init idle thread */ - rt_thread_idle_init(); + /* init idle thread */ + rt_thread_idle_init(); - /* start scheduler */ - rt_system_scheduler_start(); + /* start scheduler */ + rt_system_scheduler_start(); - /* never reach here */ - return ; + /* never reach here */ + return ; } int main(void) { - /* disable interrupt first */ - rt_hw_interrupt_disable(); + /* disable interrupt first */ + rt_hw_interrupt_disable(); - /* startup RT-Thread RTOS */ - rtthread_startup(); + /* startup RT-Thread RTOS */ + rtthread_startup(); - return 0; + return 0; } diff --git a/bsp/qemu-vexpress-a9/applications/lcd_init.c b/bsp/qemu-vexpress-a9/applications/lcd_init.c index ad4ad9f8ef..7d2d74a08f 100644 --- a/bsp/qemu-vexpress-a9/applications/lcd_init.c +++ b/bsp/qemu-vexpress-a9/applications/lcd_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/qemu-vexpress-a9/applications/main.c b/bsp/qemu-vexpress-a9/applications/main.c index 276a5943d9..c0c1e34d98 100644 --- a/bsp/qemu-vexpress-a9/applications/main.c +++ b/bsp/qemu-vexpress-a9/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/qemu-vexpress-a9/applications/mnt.c b/bsp/qemu-vexpress-a9/applications/mnt.c index 8f5b1cec44..be3ee236f8 100644 --- a/bsp/qemu-vexpress-a9/applications/mnt.c +++ b/bsp/qemu-vexpress-a9/applications/mnt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/qemu-vexpress-a9/drivers/audio/drv_ac97.c b/bsp/qemu-vexpress-a9/drivers/audio/drv_ac97.c index cf88ebed5e..bf6c1604ba 100644 --- a/bsp/qemu-vexpress-a9/drivers/audio/drv_ac97.c +++ b/bsp/qemu-vexpress-a9/drivers/audio/drv_ac97.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/qemu-vexpress-a9/drivers/audio/drv_ac97.h b/bsp/qemu-vexpress-a9/drivers/audio/drv_ac97.h index 0d783adef2..8a63b92e4b 100644 --- a/bsp/qemu-vexpress-a9/drivers/audio/drv_ac97.h +++ b/bsp/qemu-vexpress-a9/drivers/audio/drv_ac97.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,33 +12,33 @@ #define __DRV_AC97_H__ /* Register offsets */ -#define AC97_RESET 0x00 -#define AC97_MASTER 0x02 -#define AC97_HEADPHONE 0x04 -#define AC97_MASTER_MONO 0x06 -#define AC97_MASTER_TONE 0x08 -#define AC97_PC_BEEP 0x0A //mixer volume -#define AC97_PHONE 0x0C -#define AC97_MIC 0x0E //qwert db -#define AC97_LINE 0x10 -#define AC97_CD 0x12 -#define AC97_VIDEO 0x14 -#define AC97_AUX 0x16 -#define AC97_PCM 0x18 -#define AC97_REC_SEL 0x1A //0 represent mic -#define AC97_REC_GAIN 0x1C -#define AC97_REC_GAIN_MIC 0x1E -#define AC97_GENERAL_PURPOSE 0x20 -#define AC97_3D_CONTROL 0x22 -#define AC97_INT_PAGING 0x24 //qwert -#define AC97_POWERDOWN 0x26 -#define AC97_PCM_FRONT_DAC_RATE 0x2c /* PCM Front DAC Rate */ -#define AC97_PCM_SURR_DAC_RATE 0x2e /* PCM Surround DAC Rate */ -#define AC97_PCM_LFE_DAC_RATE 0x30 /* PCM LFE DAC Rate */ -#define AC97_PCM_LR_ADC_RATE 0x32 /* PCM LR ADC Rate */ -#define AC97_PCM_MIC_ADC_RATE 0x34 /* PCM MIC ADC Rate */ -#define AC97_DAC_SLOT_MAP 0x6C -#define AC97_ADC_SLOT_MAP 0x6E +#define AC97_RESET 0x00 +#define AC97_MASTER 0x02 +#define AC97_HEADPHONE 0x04 +#define AC97_MASTER_MONO 0x06 +#define AC97_MASTER_TONE 0x08 +#define AC97_PC_BEEP 0x0A //mixer volume +#define AC97_PHONE 0x0C +#define AC97_MIC 0x0E //qwert db +#define AC97_LINE 0x10 +#define AC97_CD 0x12 +#define AC97_VIDEO 0x14 +#define AC97_AUX 0x16 +#define AC97_PCM 0x18 +#define AC97_REC_SEL 0x1A //0 represent mic +#define AC97_REC_GAIN 0x1C +#define AC97_REC_GAIN_MIC 0x1E +#define AC97_GENERAL_PURPOSE 0x20 +#define AC97_3D_CONTROL 0x22 +#define AC97_INT_PAGING 0x24 //qwert +#define AC97_POWERDOWN 0x26 +#define AC97_PCM_FRONT_DAC_RATE 0x2c /* PCM Front DAC Rate */ +#define AC97_PCM_SURR_DAC_RATE 0x2e /* PCM Surround DAC Rate */ +#define AC97_PCM_LFE_DAC_RATE 0x30 /* PCM LFE DAC Rate */ +#define AC97_PCM_LR_ADC_RATE 0x32 /* PCM LR ADC Rate */ +#define AC97_PCM_MIC_ADC_RATE 0x34 /* PCM MIC ADC Rate */ +#define AC97_DAC_SLOT_MAP 0x6C +#define AC97_ADC_SLOT_MAP 0x6E void ac97_reset(void); rt_err_t ac97_set_vol(int vol); diff --git a/bsp/qemu-vexpress-a9/drivers/audio/drv_pl041.c b/bsp/qemu-vexpress-a9/drivers/audio/drv_pl041.c index 3498031d7b..ad237bbf08 100644 --- a/bsp/qemu-vexpress-a9/drivers/audio/drv_pl041.c +++ b/bsp/qemu-vexpress-a9/drivers/audio/drv_pl041.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/qemu-vexpress-a9/drivers/audio/drv_pl041.h b/bsp/qemu-vexpress-a9/drivers/audio/drv_pl041.h index 0edda3d6ea..33b8ac8258 100644 --- a/bsp/qemu-vexpress-a9/drivers/audio/drv_pl041.h +++ b/bsp/qemu-vexpress-a9/drivers/audio/drv_pl041.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,11 +14,11 @@ #define PL041_BASE_ADDR (0x10004000) /* offsets in CTRL_CH */ -#define AACI_RXCR 0x00 /* 29 bits Control Rx FIFO */ -#define AACI_TXCR 0x04 /* 17 bits Control Tx FIFO */ -#define AACI_SR 0x08 /* 12 bits Status */ -#define AACI_ISR 0x0C /* 7 bits Int Status */ -#define AACI_IE 0x10 /* 7 bits Int Enable */ +#define AACI_RXCR 0x00 /* 29 bits Control Rx FIFO */ +#define AACI_TXCR 0x04 /* 17 bits Control Tx FIFO */ +#define AACI_SR 0x08 /* 12 bits Status */ +#define AACI_ISR 0x0C /* 7 bits Int Status */ +#define AACI_IE 0x10 /* 7 bits Int Enable */ /* both for AACI_RXCR and AACI_TXCR */ #define AACI_CR_FEN (1 << 16) /* fifo enable */ @@ -39,7 +39,7 @@ #define AACI_CR_SL3 (1 << 3) #define AACI_CR_SL2 (1 << 2) #define AACI_CR_SL1 (1 << 1) -#define AACI_CR_EN (1 << 0) /* receive enable */ +#define AACI_CR_EN (1 << 0) /* receive enable */ /* status register bits */ #define AACI_SR_RXTOFE (1 << 11) /* rx timeout fifo empty */ @@ -66,29 +66,29 @@ /* interrupt enable */ #define AACI_IE_RXTOIE (1 << 6) /*rx timeout interrupt enable*/ #define AACI_IE_URIE (1 << 5) /*Transmit underrun interrupt enable*/ -#define AACI_IE_ORIE (1 << 4) /*Overrun receive interrupt enable*/ +#define AACI_IE_ORIE (1 << 4) /*Overrun receive interrupt enable*/ #define AACI_IE_RXIE (1 << 3) /*Receive interrupt enable*/ #define AACI_IE_TXIE (1 << 2) /*Transmit interrupt enable*/ #define AACI_IE_RXTIE (1 << 1) /*Receive timeout interrupt enable*/ -#define AACI_IE_TXCIE (1 << 0) /*Transmit complete interrupt enable*/ +#define AACI_IE_TXCIE (1 << 0) /*Transmit complete interrupt enable*/ /* interrupt status */ -#define AACI_ISR_RXTOFE (1 << 6) /* rx timeout fifo empty */ -#define AACI_ISR_UR (1 << 5) /* tx fifo underrun */ -#define AACI_ISR_OR (1 << 4) /* rx fifo overrun */ -#define AACI_ISR_RX (1 << 3) /* rx interrupt status */ -#define AACI_ISR_TX (1 << 2) /* tx interrupt status */ -#define AACI_ISR_RXTO (1 << 1) /* rx timeout */ -#define AACI_ISR_TXC (1 << 0) /* tx complete */ +#define AACI_ISR_RXTOFE (1 << 6) /* rx timeout fifo empty */ +#define AACI_ISR_UR (1 << 5) /* tx fifo underrun */ +#define AACI_ISR_OR (1 << 4) /* rx fifo overrun */ +#define AACI_ISR_RX (1 << 3) /* rx interrupt status */ +#define AACI_ISR_TX (1 << 2) /* tx interrupt status */ +#define AACI_ISR_RXTO (1 << 1) /* rx timeout */ +#define AACI_ISR_TXC (1 << 0) /* tx complete */ /* interrupt enable */ -#define AACI_IE_RXTOFE (1 << 6) /* rx timeout fifo empty */ -#define AACI_IE_UR (1 << 5) /* tx fifo underrun */ -#define AACI_IE_OR (1 << 4) /* rx fifo overrun */ -#define AACI_IE_RX (1 << 3) /* rx interrupt status */ -#define AACI_IE_TX (1 << 2) /* tx interrupt status */ -#define AACI_IE_RXTO (1 << 1) /* rx timeout */ -#define AACI_IE_TXC (1 << 0) /* tx complete */ +#define AACI_IE_RXTOFE (1 << 6) /* rx timeout fifo empty */ +#define AACI_IE_UR (1 << 5) /* tx fifo underrun */ +#define AACI_IE_OR (1 << 4) /* rx fifo overrun */ +#define AACI_IE_RX (1 << 3) /* rx interrupt status */ +#define AACI_IE_TX (1 << 2) /* tx interrupt status */ +#define AACI_IE_RXTO (1 << 1) /* rx timeout */ +#define AACI_IE_TXC (1 << 0) /* tx complete */ /* slot flag register bits */ #define AACI_SLFR_RWIS (1 << 13) /* raw wake-up interrupt status */ @@ -120,7 +120,7 @@ #define AACI_ICLR_RXOEC2 (1 << 2) /* Receive overrun error clear */ #define AACI_ICLR_RXOEC1 (1 << 1) /* Receive overrun error clear */ #define AACI_ICLR_WISC (1 << 0) /* Wake-up interrupt status clear */ - + /* Main control register bits AACI_MAINCR */ #define AACI_MAINCR_SCRA(x) ((x) << 10) /* secondary codec reg access */ #define AACI_MAINCR_DMAEN (1 << 9) /* dma enable */ @@ -141,8 +141,8 @@ #define SYNC_FORCE (1 << 0) /* Main flag register bits. P66 */ -#define MAINFR_TXB (1 << 1) /* transmit busy */ -#define MAINFR_RXB (1 << 0) /* receive busy */ +#define MAINFR_TXB (1 << 1) /* transmit busy */ +#define MAINFR_RXB (1 << 0) /* receive busy */ #define PL041_CHANNEL_LEFT_DAC (0x1 << 3) #define PL041_CHANNEL_RIGHT_DAC (0x1 << 3) diff --git a/bsp/qemu-vexpress-a9/drivers/audio/drv_sound.c b/bsp/qemu-vexpress-a9/drivers/audio/drv_sound.c index a2b46831b8..226a2cdb51 100644 --- a/bsp/qemu-vexpress-a9/drivers/audio/drv_sound.c +++ b/bsp/qemu-vexpress-a9/drivers/audio/drv_sound.c @@ -1,6 +1,6 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team - * + * Copyright (c) 2006-2021, RT-Thread Development Team + * * SPDX-License-Identifier: Apache-2.0 * * Date Author Notes diff --git a/bsp/qemu-vexpress-a9/drivers/audio/drv_sound.h b/bsp/qemu-vexpress-a9/drivers/audio/drv_sound.h index 7cb47532be..0752418495 100644 --- a/bsp/qemu-vexpress-a9/drivers/audio/drv_sound.h +++ b/bsp/qemu-vexpress-a9/drivers/audio/drv_sound.h @@ -1,6 +1,6 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team - * + * Copyright (c) 2006-2021, RT-Thread Development Team + * * SPDX-License-Identifier: Apache-2.0 * * Date Author Notes diff --git a/bsp/qemu-vexpress-a9/drivers/board.c b/bsp/qemu-vexpress-a9/drivers/board.c index e236c68b80..8b26e68eab 100644 --- a/bsp/qemu-vexpress-a9/drivers/board.c +++ b/bsp/qemu-vexpress-a9/drivers/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/qemu-vexpress-a9/drivers/drv_timer.c b/bsp/qemu-vexpress-a9/drivers/drv_timer.c index 7abfea0fae..6d6001b565 100644 --- a/bsp/qemu-vexpress-a9/drivers/drv_timer.c +++ b/bsp/qemu-vexpress-a9/drivers/drv_timer.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -89,7 +89,7 @@ void timer_init(int timer, unsigned int preload) { uint32_t val; - if (timer == 0) + if (timer == 0) { /* Setup Timer0 for generating irq */ val = TIMER_CTRL(TIMER01_HW_BASE); @@ -101,8 +101,8 @@ void timer_init(int timer, unsigned int preload) /* enable timer */ TIMER_CTRL(TIMER01_HW_BASE) |= TIMER_CTRL_ENABLE; - } - else + } + else { /* Setup Timer1 for generating irq */ val = TIMER_CTRL(TIMER23_HW_BASE); @@ -122,7 +122,7 @@ void timer_clear_pending(int timer) if (timer == 0) { TIMER_INTCLR(TIMER01_HW_BASE) = 0x01; - } + } else { TIMER_INTCLR(TIMER23_HW_BASE) = 0x01; diff --git a/bsp/qemu-vexpress-a9/drivers/drv_timer.h b/bsp/qemu-vexpress-a9/drivers/drv_timer.h index 718f5d43cf..c50b073d36 100644 --- a/bsp/qemu-vexpress-a9/drivers/drv_timer.h +++ b/bsp/qemu-vexpress-a9/drivers/drv_timer.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/qemu-vexpress-a9/drivers/secondary_cpu.c b/bsp/qemu-vexpress-a9/drivers/secondary_cpu.c index 3b0428859f..cddba63aac 100644 --- a/bsp/qemu-vexpress-a9/drivers/secondary_cpu.c +++ b/bsp/qemu-vexpress-a9/drivers/secondary_cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/qemu-vexpress-a9/drivers/vexpress_a9.h b/bsp/qemu-vexpress-a9/drivers/vexpress_a9.h index a6467973c5..5ecb8ecf39 100644 --- a/bsp/qemu-vexpress-a9/drivers/vexpress_a9.h +++ b/bsp/qemu-vexpress-a9/drivers/vexpress_a9.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/qemu-vexpress-gemini/applications/application.c b/bsp/qemu-vexpress-gemini/applications/application.c index 535e63c8ea..b65c758208 100644 --- a/bsp/qemu-vexpress-gemini/applications/application.c +++ b/bsp/qemu-vexpress-gemini/applications/application.c @@ -19,7 +19,7 @@ int rt_application_init() { rt_thread_t tid; - tid = rt_thread_create("init", init_thread, RT_NULL, + tid = rt_thread_create("init", init_thread, RT_NULL, 1024, RT_THREAD_PRIORITY_MAX/3, 10); if (tid != RT_NULL) rt_thread_startup(tid); diff --git a/bsp/qemu-vexpress-gemini/cpu/cpu.c b/bsp/qemu-vexpress-gemini/cpu/cpu.c index 6f46584eec..5f82671c1b 100644 --- a/bsp/qemu-vexpress-gemini/cpu/cpu.c +++ b/bsp/qemu-vexpress-gemini/cpu/cpu.c @@ -20,14 +20,14 @@ /** shutdown CPU */ void rt_hw_cpu_shutdown() { - rt_uint32_t level; - rt_kprintf("shutdown...\n"); + rt_uint32_t level; + rt_kprintf("shutdown...\n"); - level = rt_hw_interrupt_disable(); - while (level) - { - RT_ASSERT(0); - } + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } } /*@}*/ diff --git a/bsp/qemu-vexpress-gemini/cpu/interrupt.h b/bsp/qemu-vexpress-gemini/cpu/interrupt.h index 9c2eaf4ae7..90f392f407 100644 --- a/bsp/qemu-vexpress-gemini/cpu/interrupt.h +++ b/bsp/qemu-vexpress-gemini/cpu/interrupt.h @@ -14,28 +14,28 @@ #define INT_IRQ 0x00 #define INT_FIQ 0x01 -#define INTC_REVISION(hw_base) REG32((hw_base) + 0x0) -#define INTC_SYSCONFIG(hw_base) REG32((hw_base) + 0x10) -#define INTC_SYSSTATUS(hw_base) REG32((hw_base) + 0x14) -#define INTC_SIR_IRQ(hw_base) REG32((hw_base) + 0x40) -#define INTC_SIR_FIQ(hw_base) REG32((hw_base) + 0x44) -#define INTC_CONTROL(hw_base) REG32((hw_base) + 0x48) -#define INTC_PROTECTION(hw_base) REG32((hw_base) + 0x4c) -#define INTC_IDLE(hw_base) REG32((hw_base) + 0x50) -#define INTC_IRQ_PRIORITY(hw_base) REG32((hw_base) + 0x60) -#define INTC_FIQ_PRIORITY(hw_base) REG32((hw_base) + 0x64) -#define INTC_THRESHOLD(hw_base) REG32((hw_base) + 0x68) -#define INTC_SICR(hw_base) REG32((hw_base) + 0x6c) -#define INTC_SCR(hw_base, n) REG32((hw_base) + 0x70 + ((n) * 0x04)) -#define INTC_ITR(hw_base, n) REG32((hw_base) + 0x80 + ((n) * 0x20)) -#define INTC_MIR(hw_base, n) REG32((hw_base) + 0x84 + ((n) * 0x20)) -#define INTC_MIR_CLEAR(hw_base, n) REG32((hw_base) + 0x88 + ((n) * 0x20)) -#define INTC_MIR_SET(hw_base, n) REG32((hw_base) + 0x8c + ((n) * 0x20)) -#define INTC_ISR_SET(hw_base, n) REG32((hw_base) + 0x90 + ((n) * 0x20)) -#define INTC_ISR_CLEAR(hw_base, n) REG32((hw_base) + 0x94 + ((n) * 0x20)) +#define INTC_REVISION(hw_base) REG32((hw_base) + 0x0) +#define INTC_SYSCONFIG(hw_base) REG32((hw_base) + 0x10) +#define INTC_SYSSTATUS(hw_base) REG32((hw_base) + 0x14) +#define INTC_SIR_IRQ(hw_base) REG32((hw_base) + 0x40) +#define INTC_SIR_FIQ(hw_base) REG32((hw_base) + 0x44) +#define INTC_CONTROL(hw_base) REG32((hw_base) + 0x48) +#define INTC_PROTECTION(hw_base) REG32((hw_base) + 0x4c) +#define INTC_IDLE(hw_base) REG32((hw_base) + 0x50) +#define INTC_IRQ_PRIORITY(hw_base) REG32((hw_base) + 0x60) +#define INTC_FIQ_PRIORITY(hw_base) REG32((hw_base) + 0x64) +#define INTC_THRESHOLD(hw_base) REG32((hw_base) + 0x68) +#define INTC_SICR(hw_base) REG32((hw_base) + 0x6c) +#define INTC_SCR(hw_base, n) REG32((hw_base) + 0x70 + ((n) * 0x04)) +#define INTC_ITR(hw_base, n) REG32((hw_base) + 0x80 + ((n) * 0x20)) +#define INTC_MIR(hw_base, n) REG32((hw_base) + 0x84 + ((n) * 0x20)) +#define INTC_MIR_CLEAR(hw_base, n) REG32((hw_base) + 0x88 + ((n) * 0x20)) +#define INTC_MIR_SET(hw_base, n) REG32((hw_base) + 0x8c + ((n) * 0x20)) +#define INTC_ISR_SET(hw_base, n) REG32((hw_base) + 0x90 + ((n) * 0x20)) +#define INTC_ISR_CLEAR(hw_base, n) REG32((hw_base) + 0x94 + ((n) * 0x20)) #define INTC_PENDING_IRQ(hw_base, n) REG32((hw_base) + 0x98 + ((n) * 0x20)) #define INTC_PENDING_FIQ(hw_base, n) REG32((hw_base) + 0x9c + ((n) * 0x20)) -#define INTC_ILR(hw_base, n) REG32((hw_base) + 0x100 + ((n) * 0x04)) +#define INTC_ILR(hw_base, n) REG32((hw_base) + 0x100 + ((n) * 0x04)) void rt_hw_interrupt_control(int vector, int priority, int route); int rt_hw_interrupt_get_active(int fiq_irq); diff --git a/bsp/qemu-vexpress-gemini/cpu/stack.c b/bsp/qemu-vexpress-gemini/cpu/stack.c index 786d936fca..c1d9262d4b 100644 --- a/bsp/qemu-vexpress-gemini/cpu/stack.c +++ b/bsp/qemu-vexpress-gemini/cpu/stack.c @@ -20,42 +20,42 @@ * This function will initialize thread stack * * @param tentry the entry of thread - * @param parameter the parameter of entry + * @param parameter the parameter of entry * @param stack_addr the beginning stack address * @param texit the function will be called when thread exit * * @return stack address */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) + rt_uint8_t *stack_addr, void *texit) { - rt_uint32_t *stk; + rt_uint32_t *stk; - stk = (rt_uint32_t*)stack_addr; - *(stk) = (rt_uint32_t)tentry; /* entry point */ - *(--stk) = (rt_uint32_t)texit; /* lr */ - *(--stk) = 0; /* r12 */ - *(--stk) = 0; /* r11 */ - *(--stk) = 0; /* r10 */ - *(--stk) = 0; /* r9 */ - *(--stk) = 0; /* r8 */ - *(--stk) = 0; /* r7 */ - *(--stk) = 0; /* r6 */ - *(--stk) = 0; /* r5 */ - *(--stk) = 0; /* r4 */ - *(--stk) = 0; /* r3 */ - *(--stk) = 0; /* r2 */ - *(--stk) = 0; /* r1 */ - *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ + stk = (rt_uint32_t*)stack_addr; + *(stk) = (rt_uint32_t)tentry; /* entry point */ + *(--stk) = (rt_uint32_t)texit; /* lr */ + *(--stk) = 0; /* r12 */ + *(--stk) = 0; /* r11 */ + *(--stk) = 0; /* r10 */ + *(--stk) = 0; /* r9 */ + *(--stk) = 0; /* r8 */ + *(--stk) = 0; /* r7 */ + *(--stk) = 0; /* r6 */ + *(--stk) = 0; /* r5 */ + *(--stk) = 0; /* r4 */ + *(--stk) = 0; /* r3 */ + *(--stk) = 0; /* r2 */ + *(--stk) = 0; /* r1 */ + *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ - /* cpsr */ - if ((rt_uint32_t)tentry & 0x01) - *(--stk) = SVCMODE | 0x20; /* thumb mode */ - else - *(--stk) = SVCMODE; /* arm mode */ + /* cpsr */ + if ((rt_uint32_t)tentry & 0x01) + *(--stk) = SVCMODE | 0x20; /* thumb mode */ + else + *(--stk) = SVCMODE; /* arm mode */ - /* return task's current stack address */ - return (rt_uint8_t *)stk; + /* return task's current stack address */ + return (rt_uint8_t *)stk; } /*@}*/ diff --git a/bsp/qemu-vexpress-gemini/cpu/trap.c b/bsp/qemu-vexpress-gemini/cpu/trap.c index fb03bc6fa6..c6ca45aee7 100644 --- a/bsp/qemu-vexpress-gemini/cpu/trap.c +++ b/bsp/qemu-vexpress-gemini/cpu/trap.c @@ -131,7 +131,7 @@ void rt_hw_trap_resv(struct rt_hw_exp_stack *regs) rt_hw_cpu_shutdown(); } -#define GIC_ACK_INTID_MASK 0x000003ff +#define GIC_ACK_INTID_MASK 0x000003ff void rt_hw_trap_irq(void) { diff --git a/bsp/rm48x50/application/startup.c b/bsp/rm48x50/application/startup.c index 2b6311bc42..44b081ad07 100644 --- a/bsp/rm48x50/application/startup.c +++ b/bsp/rm48x50/application/startup.c @@ -71,27 +71,27 @@ void rtthread_startup(void) *rt_hw_cpu_dcache_enable(); */ - /* init hardware interrupt */ - rt_hw_interrupt_init(); + /* init hardware interrupt */ + rt_hw_interrupt_init(); - /* init board */ - rt_hw_board_init(); + /* init board */ + rt_hw_board_init(); - /* init tick */ - rt_system_tick_init(); + /* init tick */ + rt_system_tick_init(); - /* init kernel object */ - rt_system_object_init(); + /* init kernel object */ + rt_system_object_init(); - rt_show_version(); + rt_show_version(); - /* init timer system */ - rt_system_timer_init(); + /* init timer system */ + rt_system_timer_init(); - /* init memory system */ + /* init memory system */ #ifdef RT_USING_HEAP #ifdef __CC_ARM - rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)MEMEND); + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)MEMEND); #elif defined(__GNUC__) rt_system_heap_init((void*)&__bss_end, (void*)MEMEND); #elif defined(__TI_COMPILER_VERSION__) @@ -101,40 +101,40 @@ void rtthread_startup(void) #endif #endif - /* init scheduler system */ - rt_system_scheduler_init(); + /* init scheduler system */ + rt_system_scheduler_init(); - /* init application */ - rt_application_init(); + /* init application */ + rt_application_init(); #ifdef RT_USING_FINSH - /* init finsh */ - finsh_system_init(); - finsh_set_device("sci2"); + /* init finsh */ + finsh_system_init(); + finsh_set_device("sci2"); #endif - /* init soft timer thread */ - rt_system_timer_thread_init(); + /* init soft timer thread */ + rt_system_timer_thread_init(); - /* init idle thread */ - rt_thread_idle_init(); + /* init idle thread */ + rt_thread_idle_init(); - /* start scheduler */ - rt_system_scheduler_start(); + /* start scheduler */ + rt_system_scheduler_start(); - /* never reach here */ - return ; + /* never reach here */ + return ; } int main(void) { - /* disable interrupt first */ - rt_hw_interrupt_disable(); + /* disable interrupt first */ + rt_hw_interrupt_disable(); - /* invoke rtthread_startup */ - rtthread_startup(); + /* invoke rtthread_startup */ + rtthread_startup(); - return 0; + return 0; } /*@}*/ diff --git a/bsp/rm48x50/drivers/board.c b/bsp/rm48x50/drivers/board.c index 2ff930ce11..27dc8abb00 100644 --- a/bsp/rm48x50/drivers/board.c +++ b/bsp/rm48x50/drivers/board.c @@ -28,14 +28,14 @@ void rt_timer_handler(int vector, void* param) { rtiREG1->INTFLAG = 8U; /* clear interrupt flag */ - rt_tick_increase(); + rt_tick_increase(); } void rt_hw_board_init(void) { rtiInit(); - rt_hw_interrupt_install(RTI_INT_VEC, rt_timer_handler, RT_NULL, "tick"); + rt_hw_interrupt_install(RTI_INT_VEC, rt_timer_handler, RT_NULL, "tick"); rt_hw_interrupt_umask(RTI_INT_VEC); rtiStartCounter(rtiCOUNTER_BLOCK1); diff --git a/bsp/rm48x50/drivers/board.h b/bsp/rm48x50/drivers/board.h index 8ac5b3f48c..62223efced 100644 --- a/bsp/rm48x50/drivers/board.h +++ b/bsp/rm48x50/drivers/board.h @@ -18,7 +18,7 @@ /* RT_USING_UART */ #define RT_USING_UART1 #define RT_USING_UART2 -#define RT_UART_RX_BUFFER_SIZE 64 +#define RT_UART_RX_BUFFER_SIZE 64 void rt_hw_board_init(void); void rt_hw_led_set(int led); void rt_hw_led_flash(void); @@ -27,93 +27,93 @@ void rt_hw_led_flash(void); void rt_hw_finsh_init(void); #endif -#define USE_USB 0 +#define USE_USB 0 -#if USE_USB /* 1 is USB, 0 is non-USB related */ -#define PLL_MValue 11 -#define PLL_NValue 0 -#define CCLKDivValue 4 -#define USBCLKDivValue 5 +#if USE_USB /* 1 is USB, 0 is non-USB related */ +#define PLL_MValue 11 +#define PLL_NValue 0 +#define CCLKDivValue 4 +#define USBCLKDivValue 5 -#define Fosc 12000000 -#define Fcclk 57600000 -#define Fcco 288000000 +#define Fosc 12000000 +#define Fcclk 57600000 +#define Fcco 288000000 #else -#define PLL_MValue 12 -#define PLL_NValue 1 -#define CCLKDivValue 5 +#define PLL_MValue 12 +#define PLL_NValue 1 +#define CCLKDivValue 5 -#define Fosc 12000000 -#define Fcclk 72000000 -#define Fcco 360000000 +#define Fosc 12000000 +#define Fcclk 72000000 +#define Fcco 360000000 #endif #if USE_USB -#define Fpclk (Fcclk / 2) +#define Fpclk (Fcclk / 2) #else -#define Fpclk (Fcclk / 4) +#define Fpclk (Fcclk / 4) #endif /* IRQ define */ -#define SYS32Mode 0x1F -#define IRQ32Mode 0x12 -#define FIQ32Mode 0x11 - -#define HIGHEST_PRIORITY 0x01 -#define LOWEST_PRIORITY 0x0F - -#define WDT_INT 0 -#define SWI_INT 1 -#define ARM_CORE0_INT 2 -#define ARM_CORE1_INT 3 -#define TIMER0_INT 4 -#define TIMER1_INT 5 -#define UART0_INT 6 -#define UART1_INT 7 -#define PWM0_1_INT 8 -#define I2C0_INT 9 -#define SPI0_INT 10 /* SPI and SSP0 share VIC slot */ -#define SSP0_INT 10 -#define SSP1_INT 11 -#define PLL_INT 12 -#define RTC_INT 13 -#define EINT0_INT 14 -#define EINT1_INT 15 -#define EINT2_INT 16 -#define EINT3_INT 17 -#define ADC0_INT 18 -#define I2C1_INT 19 -#define BOD_INT 20 -#define EMAC_INT 21 -#define USB_INT 22 -#define CAN_INT 23 -#define MCI_INT 24 -#define GPDMA_INT 25 -#define TIMER2_INT 26 -#define TIMER3_INT 27 -#define UART2_INT 28 -#define UART3_INT 29 -#define I2C2_INT 30 -#define I2S_INT 31 - -#define VIC_SIZE 32 - -#define VECT_ADDR_INDEX 0x100 +#define SYS32Mode 0x1F +#define IRQ32Mode 0x12 +#define FIQ32Mode 0x11 + +#define HIGHEST_PRIORITY 0x01 +#define LOWEST_PRIORITY 0x0F + +#define WDT_INT 0 +#define SWI_INT 1 +#define ARM_CORE0_INT 2 +#define ARM_CORE1_INT 3 +#define TIMER0_INT 4 +#define TIMER1_INT 5 +#define UART0_INT 6 +#define UART1_INT 7 +#define PWM0_1_INT 8 +#define I2C0_INT 9 +#define SPI0_INT 10 /* SPI and SSP0 share VIC slot */ +#define SSP0_INT 10 +#define SSP1_INT 11 +#define PLL_INT 12 +#define RTC_INT 13 +#define EINT0_INT 14 +#define EINT1_INT 15 +#define EINT2_INT 16 +#define EINT3_INT 17 +#define ADC0_INT 18 +#define I2C1_INT 19 +#define BOD_INT 20 +#define EMAC_INT 21 +#define USB_INT 22 +#define CAN_INT 23 +#define MCI_INT 24 +#define GPDMA_INT 25 +#define TIMER2_INT 26 +#define TIMER3_INT 27 +#define UART2_INT 28 +#define UART3_INT 29 +#define I2C2_INT 30 +#define I2S_INT 31 + +#define VIC_SIZE 32 + +#define VECT_ADDR_INDEX 0x100 #define VECT_CNTL_INDEX 0x200 -#define CCLK 60000000 /* Fosc = 12MHz, M = 5 */ -#define PCLK 15000000 /* CCLK/4, use default */ +#define CCLK 60000000 /* Fosc = 12MHz, M = 5 */ +#define PCLK 15000000 /* CCLK/4, use default */ /****************************************************************************** -** Function name: TargetInit +** Function name: TargetInit ** -** Descriptions: Initialize the target board; it is called in a -** necessary place, change it as needed +** Descriptions: Initialize the target board; it is called in a +** necessary place, change it as needed ** -** parameters: None -** Returned value: None +** parameters: None +** Returned value: None ** ******************************************************************************/ extern void TargetInit(void); diff --git a/bsp/rm48x50/drivers/drv_uart.c b/bsp/rm48x50/drivers/drv_uart.c index d42a52bc6b..2ebea5ad4f 100644 --- a/bsp/rm48x50/drivers/drv_uart.c +++ b/bsp/rm48x50/drivers/drv_uart.c @@ -194,7 +194,7 @@ void rt_hw_uart_init(void) config.parity = PARITY_NONE; config.stop_bits = STOP_BITS_1; config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; + config.bufsz = RT_SERIAL_RB_BUFSZ; _sci2_serial.ops = &_sci_ops; _sci2_serial.config = config; diff --git a/bsp/rm48x50/rtconfig.h b/bsp/rm48x50/rtconfig.h index f7d9235a5b..e7ae2ed7ae 100644 --- a/bsp/rm48x50/rtconfig.h +++ b/bsp/rm48x50/rtconfig.h @@ -5,19 +5,19 @@ // // -#define RT_NAME_MAX 6 +#define RT_NAME_MAX 6 // -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 // // 8 // 32 // 256 // -#define RT_THREAD_PRIORITY_MAX 32 +#define RT_THREAD_PRIORITY_MAX 32 // -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 // -#define IDLE_THREAD_STACK_SIZE 512 +#define IDLE_THREAD_STACK_SIZE 512 //
//#define RT_DEBUG // @@ -31,11 +31,11 @@ //
// #define RT_USING_TIMER_SOFT // -#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_PRIO 4 // -#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_THREAD_STACK_SIZE 512 // -#define RT_TIMER_TICK_PER_SECOND 10 +#define RT_TIMER_TICK_PER_SECOND 10 //
//
@@ -78,9 +78,9 @@ //
#define RT_USING_CONSOLE // -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 // -#define RT_CONSOLE_DEVICE_NAME "sci2" +#define RT_CONSOLE_DEVICE_NAME "sci2" //
// @@ -92,7 +92,7 @@ // #define FINSH_USING_DESCRIPTION // -#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_THREAD_STACK_SIZE 4096 //
//
@@ -107,18 +107,18 @@ // // #define DFS_USING_WORKDIR // -#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEMS_MAX 2 // -#define DFS_FD_MAX 4 +#define DFS_FD_MAX 4 // #define RT_USING_DFS_ELMFAT // // 1 // 2 // -#define RT_DFS_ELM_USE_LFN 1 +#define RT_DFS_ELM_USE_LFN 1 // -#define RT_DFS_ELM_MAX_LFN 64 +#define RT_DFS_ELM_MAX_LFN 64 // // #define RT_USING_DFS_YAFFS2 // @@ -128,7 +128,7 @@ // // #define RT_USING_DFS_NFS // -#define RT_NFS_HOST_EXPORT "192.168.1.5:/" +#define RT_NFS_HOST_EXPORT "192.168.1.5:/" //
//
@@ -146,31 +146,31 @@ // #define RT_LWIP_DNS // -#define RT_LWIP_PBUF_NUM 4 +#define RT_LWIP_PBUF_NUM 4 // -#define RT_LWIP_TCP_PCB_NUM 3 +#define RT_LWIP_TCP_PCB_NUM 3 // -#define RT_LWIP_TCP_SND_BUF 2048 +#define RT_LWIP_TCP_SND_BUF 2048 // -#define RT_LWIP_TCP_WND 2048 +#define RT_LWIP_TCP_WND 2048 // // #define RT_LWIP_SNMP // // #define RT_LWIP_DHCP // -#define RT_LWIP_TCP_SEG_NUM 4 +#define RT_LWIP_TCP_SEG_NUM 4 // -#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 // -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 // -#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 +#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 // -#define RT_LWIP_ETHTHREAD_PRIORITY 14 +#define RT_LWIP_ETHTHREAD_PRIORITY 14 // -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 // -#define RT_LWIP_ETHTHREAD_STACKSIZE 512 +#define RT_LWIP_ETHTHREAD_STACKSIZE 512 // #define RT_LWIP_IPADDR0 192 #define RT_LWIP_IPADDR1 168 @@ -191,7 +191,7 @@ //
// #define RT_USING_RTGUI // -#define RTGUI_NAME_MAX 12 +#define RTGUI_NAME_MAX 12 // #define RTGUI_USING_SMALL_SIZE // @@ -201,7 +201,7 @@ // #define RTGUI_USING_FONTHZ // -#define RTGUI_DEFAULT_FONT_SIZE 16 +#define RTGUI_DEFAULT_FONT_SIZE 16 // // #define RTGUI_USING_DFS_FILERW // diff --git a/bsp/rx/applications/application.c b/bsp/rx/applications/application.c index de27e10bba..6126d6a9a5 100644 --- a/bsp/rx/applications/application.c +++ b/bsp/rx/applications/application.c @@ -52,81 +52,81 @@ void cali_store(struct calibration_data *data) void rt_init_thread_entry(void* parameter) { - + #ifdef RT_USING_MODULE rt_system_module_init(); #endif #ifdef RT_USING_FINSH - /* initialize finsh */ - finsh_system_init(); - finsh_set_device(RT_CONSOLE_DEVICE_NAME); + /* initialize finsh */ + finsh_system_init(); + finsh_set_device(RT_CONSOLE_DEVICE_NAME); #endif #ifdef RT_USING_LWIP - /* initialize lwip stack */ - /* register ethernetif device */ - eth_system_device_init(); + /* initialize lwip stack */ + /* register ethernetif device */ + eth_system_device_init(); - /* initialize lwip system */ - lwip_system_init(); - rt_kprintf("TCP/IP initialized!\n"); + /* initialize lwip system */ + lwip_system_init(); + rt_kprintf("TCP/IP initialized!\n"); #endif #ifdef RT_USING_DFS - /* initialize the device file system */ - dfs_init(); + /* initialize the device file system */ + dfs_init(); #ifdef RT_USING_DFS_ELMFAT - /* initialize the elm chan FatFS file system*/ - elm_init(); + /* initialize the elm chan FatFS file system*/ + elm_init(); #endif #if defined(RT_USING_DFS_NFS) && defined(RT_USING_LWIP) - /* initialize NFSv3 client file system */ - nfs_init(); + /* initialize NFSv3 client file system */ + nfs_init(); #endif #ifdef RT_USING_DFS_YAFFS2 - dfs_yaffs2_init(); + dfs_yaffs2_init(); #endif #ifdef RT_USING_DFS_UFFS - dfs_uffs_init(); + dfs_uffs_init(); #endif #ifdef RT_USING_DFS_JFFS2 - dfs_jffs2_init(); + dfs_jffs2_init(); #endif #ifdef RT_USING_DFS_ROMFS - dfs_romfs_init(); + dfs_romfs_init(); #endif #ifdef RT_USING_DFS_RAMFS - dfs_ramfs_init(); + dfs_ramfs_init(); #endif #ifdef RT_USING_DFS_DEVFS - devfs_init(); + devfs_init(); #endif #endif /* end of RT_USING_DFS */ #ifdef RT_USING_NEWLIB - libc_system_init(RT_CONSOLE_DEVICE_NAME); + libc_system_init(RT_CONSOLE_DEVICE_NAME); #else - /* the pthread system initialization will be initiallized in libc */ -#ifdef RT_USING_PTHREADS - pthread_system_init(); + /* the pthread system initialization will be initiallized in libc */ +#ifdef RT_USING_PTHREADS + pthread_system_init(); #endif #endif #ifdef RT_USING_RTGUI - rtgui_system_server_init(); + rtgui_system_server_init(); #endif #ifdef RT_USING_USB_HOST - rt_usb_host_init(); + rt_usb_host_init(); #endif #ifdef RT_USING_FINSH diff --git a/bsp/rx/applications/startup.c b/bsp/rx/applications/startup.c index 4b195492f6..f266935731 100644 --- a/bsp/rx/applications/startup.c +++ b/bsp/rx/applications/startup.c @@ -90,7 +90,7 @@ int main(void) { rt_hw_system_freq_init(); - + __enable_interrupt(); /* disable interrupt first */ rt_hw_interrupt_disable(); diff --git a/bsp/rx/rtconfig.h b/bsp/rx/rtconfig.h index 6f055dce1a..57524271da 100644 --- a/bsp/rx/rtconfig.h +++ b/bsp/rx/rtconfig.h @@ -3,16 +3,16 @@ #define __RTTHREAD_CFG_H__ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 32 +#define RT_THREAD_PRIORITY_MAX 32 /* Tick per Second */ -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 /* SECTION: RT_DEBUG */ /* Thread Debug */ @@ -27,9 +27,9 @@ /* Using Software Timer */ /* #define RT_USING_TIMER_SOFT */ -#define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 512 -#define RT_TIMER_TICK_PER_SECOND 10 +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_TICK_PER_SECOND 10 /* SECTION: IPC */ /* Using Semaphore*/ @@ -72,9 +72,9 @@ /* SECTION: Console options */ #define RT_USING_CONSOLE /* the buffer size of console*/ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 // -#define RT_CONSOLE_DEVICE_NAME "uart2" +#define RT_CONSOLE_DEVICE_NAME "uart2" /* SECTION: finsh, a C-Express shell */ #define RT_USING_FINSH @@ -89,17 +89,17 @@ /* Reentrancy (thread safe) of the FatFs module. */ #define RT_DFS_ELM_REENTRANT /* Number of volumes (logical drives) to be used. */ -#define RT_DFS_ELM_DRIVES 2 -/* #define RT_DFS_ELM_USE_LFN 1 */ -/* #define RT_DFS_ELM_CODE_PAGE 936 */ -#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +/* #define RT_DFS_ELM_USE_LFN 1 */ +/* #define RT_DFS_ELM_CODE_PAGE 936 */ +#define RT_DFS_ELM_MAX_LFN 255 /* Maximum sector size to be handled. */ #define RT_DFS_ELM_MAX_SECTOR_SIZE 512 /* the max number of mounted filesystem */ -#define DFS_FILESYSTEMS_MAX 2 -/* the max number of opened files */ -#define DFS_FD_MAX 4 +#define DFS_FILESYSTEMS_MAX 2 +/* the max number of opened files */ +#define DFS_FD_MAX 4 /* SECTION: lwip, a lighwight TCP/IP protocol stack */ /* #define RT_USING_LWIP */ @@ -113,49 +113,49 @@ #define RT_LWIP_DNS /* the number of simulatenously active TCP connections*/ -#define RT_LWIP_TCP_PCB_NUM 5 +#define RT_LWIP_TCP_PCB_NUM 5 /* Using DHCP */ /* #define RT_LWIP_DHCP */ /* ip address of target*/ -#define RT_LWIP_IPADDR0 192 -#define RT_LWIP_IPADDR1 168 -#define RT_LWIP_IPADDR2 1 -#define RT_LWIP_IPADDR3 30 +#define RT_LWIP_IPADDR0 192 +#define RT_LWIP_IPADDR1 168 +#define RT_LWIP_IPADDR2 1 +#define RT_LWIP_IPADDR3 30 /* gateway address of target*/ -#define RT_LWIP_GWADDR0 192 -#define RT_LWIP_GWADDR1 168 -#define RT_LWIP_GWADDR2 1 -#define RT_LWIP_GWADDR3 1 +#define RT_LWIP_GWADDR0 192 +#define RT_LWIP_GWADDR1 168 +#define RT_LWIP_GWADDR2 1 +#define RT_LWIP_GWADDR3 1 /* mask address of target*/ -#define RT_LWIP_MSKADDR0 255 -#define RT_LWIP_MSKADDR1 255 -#define RT_LWIP_MSKADDR2 255 -#define RT_LWIP_MSKADDR3 0 +#define RT_LWIP_MSKADDR0 255 +#define RT_LWIP_MSKADDR1 255 +#define RT_LWIP_MSKADDR2 255 +#define RT_LWIP_MSKADDR3 0 /* tcp thread options */ -#define RT_LWIP_TCPTHREAD_PRIORITY 12 -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 10 -#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 10 +#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 /* ethernet if thread options */ -#define RT_LWIP_ETHTHREAD_PRIORITY 15 -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 10 -#define RT_LWIP_ETHTHREAD_STACKSIZE 512 +#define RT_LWIP_ETHTHREAD_PRIORITY 15 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 10 +#define RT_LWIP_ETHTHREAD_STACKSIZE 512 /* TCP sender buffer space */ -#define RT_LWIP_TCP_SND_BUF 8192 +#define RT_LWIP_TCP_SND_BUF 8192 /* TCP receive window. */ -#define RT_LWIP_TCP_WND 8192 +#define RT_LWIP_TCP_WND 8192 /* SECTION: RT-Thread/GUI */ /* #define RT_USING_RTGUI */ /* name length of RTGUI object */ -#define RTGUI_NAME_MAX 12 +#define RTGUI_NAME_MAX 12 /* support 16 weight font */ #define RTGUI_USING_FONT16 /* support Chinese font */ @@ -171,7 +171,7 @@ /* use mouse cursor */ /* #define RTGUI_USING_MOUSE_CURSOR */ /* default font size in RTGUI */ -#define RTGUI_DEFAULT_FONT_SIZE 16 +#define RTGUI_DEFAULT_FONT_SIZE 16 /* image support */ /* #define RTGUI_IMAGE_XPM */ diff --git a/bsp/sam7x/applications/application.c b/bsp/sam7x/applications/application.c index 403cbf3aed..6500ddfa10 100644 --- a/bsp/sam7x/applications/application.c +++ b/bsp/sam7x/applications/application.c @@ -40,49 +40,49 @@ void rt_init_thread_entry(void *parameter) { /* Filesystem Initialization */ #ifdef RT_USING_DFS - { - /* init the device filesystem */ - dfs_init(); - /* init the efsl filesystam*/ - efsl_init(); + { + /* init the device filesystem */ + dfs_init(); + /* init the efsl filesystam*/ + efsl_init(); - /* mount sd card fat partition 1 as root directory */ - if (dfs_mount("sd0", "/", "efs", 0, 0) == 0) - rt_kprintf("File System initialized!\n"); - else - rt_kprintf("File System init failed!\n"); - } + /* mount sd card fat partition 1 as root directory */ + if (dfs_mount("sd0", "/", "efs", 0, 0) == 0) + rt_kprintf("File System initialized!\n"); + else + rt_kprintf("File System init failed!\n"); + } #endif /* LwIP Initialization */ #ifdef RT_USING_LWIP - { - extern void lwip_sys_init(void); + { + extern void lwip_sys_init(void); - eth_system_device_init(); + eth_system_device_init(); - /* register AT91 EMAC device */ - sam7xether_register("E0"); + /* register AT91 EMAC device */ + sam7xether_register("E0"); - /* init lwip system */ - lwip_sys_init(); - rt_kprintf("TCP/IP initialized!\n"); - } + /* init lwip system */ + lwip_sys_init(); + rt_kprintf("TCP/IP initialized!\n"); + } #endif } int rt_application_init() { - rt_thread_t init_thread; + rt_thread_t init_thread; - init_thread = rt_thread_create("init", - rt_init_thread_entry, RT_NULL, - 1024, 8, 5); - rt_thread_startup(init_thread); + init_thread = rt_thread_create("init", + rt_init_thread_entry, RT_NULL, + 1024, 8, 5); + rt_thread_startup(init_thread); - rt_kprintf("enter list() to get function list!\n"); + rt_kprintf("enter list() to get function list!\n"); - return 0; + return 0; } /*@}*/ diff --git a/bsp/sam7x/applications/startup.c b/bsp/sam7x/applications/startup.c index 5e0462ede9..0bc5bec3a9 100644 --- a/bsp/sam7x/applications/startup.c +++ b/bsp/sam7x/applications/startup.c @@ -52,17 +52,17 @@ extern int finsh_system_init(void); void led_flash() { - int i; - static int j = 0; + int i; + static int j = 0; - rt_hw_board_led_off(j); - for (i = 0; i < 2000000; i ++); + rt_hw_board_led_off(j); + for (i = 0; i < 2000000; i ++); - j ++; - if (j >= 4) j = 0; + j ++; + if (j >= 4) j = 0; - rt_hw_board_led_on(j); - for (i = 0; i < 2000000; i ++); + rt_hw_board_led_on(j); + for (i = 0; i < 2000000; i ++); } /** @@ -70,76 +70,76 @@ void led_flash() */ void rtthread_startup(void) { - /* init hardware interrupt */ - rt_hw_interrupt_init(); + /* init hardware interrupt */ + rt_hw_interrupt_init(); - /* init board */ - rt_hw_board_init(); + /* init board */ + rt_hw_board_init(); - rt_show_version(); + rt_show_version(); - /* init tick */ - rt_system_tick_init(); + /* init tick */ + rt_system_tick_init(); - /* init kernel object */ - rt_system_object_init(); + /* init kernel object */ + rt_system_object_init(); - /* init timer system */ - rt_system_timer_init(); + /* init timer system */ + rt_system_timer_init(); #ifdef RT_USING_HEAP #ifdef __CC_ARM - rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x00210000); + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x00210000); #elif __ICCARM__ rt_system_heap_init(__segment_end("HEAP"), (void*)0x00210000); #else - rt_system_heap_init(&__bss_end, (void*)0x00210000); + rt_system_heap_init(&__bss_end, (void*)0x00210000); #endif #endif - /* init scheduler system */ - rt_system_scheduler_init(); + /* init scheduler system */ + rt_system_scheduler_init(); #ifdef RT_USING_HOOK /* if the hook is used */ - /* set idle thread hook */ - rt_thread_idle_sethook(led_flash); + /* set idle thread hook */ + rt_thread_idle_sethook(led_flash); #endif #ifdef RT_USING_DEVICE - /* init hardware serial device */ - rt_hw_serial_init(); + /* init hardware serial device */ + rt_hw_serial_init(); #ifdef RT_USING_DFS - rt_hw_sdcard_init(); + rt_hw_sdcard_init(); #endif #endif - /* init application */ - rt_application_init(); + /* init application */ + rt_application_init(); #ifdef RT_USING_FINSH - /* init finsh */ - finsh_system_init(); - finsh_set_device("uart1"); + /* init finsh */ + finsh_system_init(); + finsh_set_device("uart1"); #endif - /* init idle thread */ - rt_thread_idle_init(); + /* init idle thread */ + rt_thread_idle_init(); - /* start scheduler */ - rt_system_scheduler_start(); + /* start scheduler */ + rt_system_scheduler_start(); - /* never reach here */ - return ; + /* never reach here */ + return ; } #ifdef __CC_ARM int main (void) { - /* invoke rtthread_startup */ - rtthread_startup(); + /* invoke rtthread_startup */ + rtthread_startup(); - return 0; + return 0; } #endif diff --git a/bsp/sam7x/drivers/AT91SAM7X.h b/bsp/sam7x/drivers/AT91SAM7X.h index 96430b2a17..2ee0c4fedc 100644 --- a/bsp/sam7x/drivers/AT91SAM7X.h +++ b/bsp/sam7x/drivers/AT91SAM7X.h @@ -19,229 +19,229 @@ extern "C" { #endif -#define AT91_REG *(volatile unsigned int *) /* Hardware register definition */ +#define AT91_REG *(volatile unsigned int *) /* Hardware register definition */ /* ========== Register definition for TC0 peripheral ========== */ -#define AT91C_TC0_SR (AT91_REG(0xFFFA0020)) /* TC0 Status Register */ -#define AT91C_TC0_RC (AT91_REG(0xFFFA001C)) /* TC0 Register C */ -#define AT91C_TC0_RB (AT91_REG(0xFFFA0018)) /* TC0 Register B */ -#define AT91C_TC0_CCR (AT91_REG(0xFFFA0000)) /* TC0 Channel Control Register */ -#define AT91C_TC0_CMR (AT91_REG(0xFFFA0004)) /* TC0 Channel Mode Register (Capture Mode / Waveform Mode) */ -#define AT91C_TC0_IER (AT91_REG(0xFFFA0024)) /* TC0 Interrupt Enable Register */ -#define AT91C_TC0_RA (AT91_REG(0xFFFA0014)) /* TC0 Register A */ -#define AT91C_TC0_IDR (AT91_REG(0xFFFA0028)) /* TC0 Interrupt Disable Register */ -#define AT91C_TC0_CV (AT91_REG(0xFFFA0010)) /* TC0 Counter Value */ -#define AT91C_TC0_IMR (AT91_REG(0xFFFA002C)) /* TC0 Interrupt Mask Register */ +#define AT91C_TC0_SR (AT91_REG(0xFFFA0020)) /* TC0 Status Register */ +#define AT91C_TC0_RC (AT91_REG(0xFFFA001C)) /* TC0 Register C */ +#define AT91C_TC0_RB (AT91_REG(0xFFFA0018)) /* TC0 Register B */ +#define AT91C_TC0_CCR (AT91_REG(0xFFFA0000)) /* TC0 Channel Control Register */ +#define AT91C_TC0_CMR (AT91_REG(0xFFFA0004)) /* TC0 Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC0_IER (AT91_REG(0xFFFA0024)) /* TC0 Interrupt Enable Register */ +#define AT91C_TC0_RA (AT91_REG(0xFFFA0014)) /* TC0 Register A */ +#define AT91C_TC0_IDR (AT91_REG(0xFFFA0028)) /* TC0 Interrupt Disable Register */ +#define AT91C_TC0_CV (AT91_REG(0xFFFA0010)) /* TC0 Counter Value */ +#define AT91C_TC0_IMR (AT91_REG(0xFFFA002C)) /* TC0 Interrupt Mask Register */ /* ========== Register definition for TC1 peripheral ========== */ -#define AT91C_TC1_RB (AT91_REG(0xFFFA0058)) /* TC1 Register B */ -#define AT91C_TC1_CCR (AT91_REG(0xFFFA0040)) /* TC1 Channel Control Register */ -#define AT91C_TC1_IER (AT91_REG(0xFFFA0064)) /* TC1 Interrupt Enable Register */ -#define AT91C_TC1_IDR (AT91_REG(0xFFFA0068)) /* TC1 Interrupt Disable Register */ -#define AT91C_TC1_SR (AT91_REG(0xFFFA0060)) /* TC1 Status Register */ -#define AT91C_TC1_CMR (AT91_REG(0xFFFA0044)) /* TC1 Channel Mode Register (Capture Mode / Waveform Mode) */ -#define AT91C_TC1_RA (AT91_REG(0xFFFA0054)) /* TC1 Register A */ -#define AT91C_TC1_RC (AT91_REG(0xFFFA005C)) /* TC1 Register C */ -#define AT91C_TC1_IMR (AT91_REG(0xFFFA006C)) /* TC1 Interrupt Mask Register */ -#define AT91C_TC1_CV (AT91_REG(0xFFFA0050)) /* TC1 Counter Value */ +#define AT91C_TC1_RB (AT91_REG(0xFFFA0058)) /* TC1 Register B */ +#define AT91C_TC1_CCR (AT91_REG(0xFFFA0040)) /* TC1 Channel Control Register */ +#define AT91C_TC1_IER (AT91_REG(0xFFFA0064)) /* TC1 Interrupt Enable Register */ +#define AT91C_TC1_IDR (AT91_REG(0xFFFA0068)) /* TC1 Interrupt Disable Register */ +#define AT91C_TC1_SR (AT91_REG(0xFFFA0060)) /* TC1 Status Register */ +#define AT91C_TC1_CMR (AT91_REG(0xFFFA0044)) /* TC1 Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC1_RA (AT91_REG(0xFFFA0054)) /* TC1 Register A */ +#define AT91C_TC1_RC (AT91_REG(0xFFFA005C)) /* TC1 Register C */ +#define AT91C_TC1_IMR (AT91_REG(0xFFFA006C)) /* TC1 Interrupt Mask Register */ +#define AT91C_TC1_CV (AT91_REG(0xFFFA0050)) /* TC1 Counter Value */ /* ========== Register definition for TC2 peripheral ========== */ -#define AT91C_TC2_CMR (AT91_REG(0xFFFA0084)) /* TC2 Channel Mode Register (Capture Mode / Waveform Mode) */ -#define AT91C_TC2_CCR (AT91_REG(0xFFFA0080)) /* TC2 Channel Control Register */ -#define AT91C_TC2_CV (AT91_REG(0xFFFA0090)) /* TC2 Counter Value */ -#define AT91C_TC2_RA (AT91_REG(0xFFFA0094)) /* TC2 Register A */ -#define AT91C_TC2_RB (AT91_REG(0xFFFA0098)) /* TC2 Register B */ -#define AT91C_TC2_IDR (AT91_REG(0xFFFA00A8)) /* TC2 Interrupt Disable Register */ -#define AT91C_TC2_IMR (AT91_REG(0xFFFA00AC)) /* TC2 Interrupt Mask Register */ -#define AT91C_TC2_RC (AT91_REG(0xFFFA009C)) /* TC2 Register C */ -#define AT91C_TC2_IER (AT91_REG(0xFFFA00A4)) /* TC2 Interrupt Enable Register */ -#define AT91C_TC2_SR (AT91_REG(0xFFFA00A0)) /* TC2 Status Register */ +#define AT91C_TC2_CMR (AT91_REG(0xFFFA0084)) /* TC2 Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC2_CCR (AT91_REG(0xFFFA0080)) /* TC2 Channel Control Register */ +#define AT91C_TC2_CV (AT91_REG(0xFFFA0090)) /* TC2 Counter Value */ +#define AT91C_TC2_RA (AT91_REG(0xFFFA0094)) /* TC2 Register A */ +#define AT91C_TC2_RB (AT91_REG(0xFFFA0098)) /* TC2 Register B */ +#define AT91C_TC2_IDR (AT91_REG(0xFFFA00A8)) /* TC2 Interrupt Disable Register */ +#define AT91C_TC2_IMR (AT91_REG(0xFFFA00AC)) /* TC2 Interrupt Mask Register */ +#define AT91C_TC2_RC (AT91_REG(0xFFFA009C)) /* TC2 Register C */ +#define AT91C_TC2_IER (AT91_REG(0xFFFA00A4)) /* TC2 Interrupt Enable Register */ +#define AT91C_TC2_SR (AT91_REG(0xFFFA00A0)) /* TC2 Status Register */ /* ========== Register definition for PITC peripheral ========== */ -#define AT91C_PITC_PIVR (AT91_REG(0xFFFFFD38)) /* PITC Period Interval Value Register */ -#define AT91C_PITC_PISR (AT91_REG(0xFFFFFD34)) /* PITC Period Interval Status Register */ -#define AT91C_PITC_PIIR (AT91_REG(0xFFFFFD3C)) /* PITC Period Interval Image Register */ -#define AT91C_PITC_PIMR (AT91_REG(0xFFFFFD30)) /* PITC Period Interval Mode Register */ +#define AT91C_PITC_PIVR (AT91_REG(0xFFFFFD38)) /* PITC Period Interval Value Register */ +#define AT91C_PITC_PISR (AT91_REG(0xFFFFFD34)) /* PITC Period Interval Status Register */ +#define AT91C_PITC_PIIR (AT91_REG(0xFFFFFD3C)) /* PITC Period Interval Image Register */ +#define AT91C_PITC_PIMR (AT91_REG(0xFFFFFD30)) /* PITC Period Interval Mode Register */ /* ========== Register definition for UDP peripheral ========== */ -#define AT91C_UDP_NUM (AT91_REG(0xFFFB0000)) /* UDP Frame Number Register */ -#define AT91C_UDP_STAT (AT91_REG(0xFFFB0004)) /* UDP Global State Register */ -#define AT91C_UDP_FADDR (AT91_REG(0xFFFB0008)) /* UDP Function Address Register */ -#define AT91C_UDP_IER (AT91_REG(0xFFFB0010)) /* UDP Interrupt Enable Register */ -#define AT91C_UDP_IDR (AT91_REG(0xFFFB0014)) /* UDP Interrupt Disable Register */ -#define AT91C_UDP_IMR (AT91_REG(0xFFFB0018)) /* UDP Interrupt Mask Register */ -#define AT91C_UDP_ISR (AT91_REG(0xFFFB001C)) /* UDP Interrupt Status Register */ -#define AT91C_UDP_ICR (AT91_REG(0xFFFB0020)) /* UDP Interrupt Clear Register */ -#define AT91C_UDP_RSTEP (AT91_REG(0xFFFB0028)) /* UDP Reset Endpoint Register */ -#define AT91C_UDP_CSR0 (AT91_REG(0xFFFB0030)) /* UDP Endpoint Control and Status Register */ -#define AT91C_UDP_CSR(n) (*(&AT91C_UDP_CSR0 + n)) -#define AT91C_UDP_FDR0 (AT91_REG(0xFFFB0050)) /* UDP Endpoint FIFO Data Register */ -#define AT91C_UDP_FDR(n) (*(&AT91C_UDP_FDR0 + n)) -#define AT91C_UDP_TXVC (AT91_REG(0xFFFB0074)) /* UDP Transceiver Control Register */ +#define AT91C_UDP_NUM (AT91_REG(0xFFFB0000)) /* UDP Frame Number Register */ +#define AT91C_UDP_STAT (AT91_REG(0xFFFB0004)) /* UDP Global State Register */ +#define AT91C_UDP_FADDR (AT91_REG(0xFFFB0008)) /* UDP Function Address Register */ +#define AT91C_UDP_IER (AT91_REG(0xFFFB0010)) /* UDP Interrupt Enable Register */ +#define AT91C_UDP_IDR (AT91_REG(0xFFFB0014)) /* UDP Interrupt Disable Register */ +#define AT91C_UDP_IMR (AT91_REG(0xFFFB0018)) /* UDP Interrupt Mask Register */ +#define AT91C_UDP_ISR (AT91_REG(0xFFFB001C)) /* UDP Interrupt Status Register */ +#define AT91C_UDP_ICR (AT91_REG(0xFFFB0020)) /* UDP Interrupt Clear Register */ +#define AT91C_UDP_RSTEP (AT91_REG(0xFFFB0028)) /* UDP Reset Endpoint Register */ +#define AT91C_UDP_CSR0 (AT91_REG(0xFFFB0030)) /* UDP Endpoint Control and Status Register */ +#define AT91C_UDP_CSR(n) (*(&AT91C_UDP_CSR0 + n)) +#define AT91C_UDP_FDR0 (AT91_REG(0xFFFB0050)) /* UDP Endpoint FIFO Data Register */ +#define AT91C_UDP_FDR(n) (*(&AT91C_UDP_FDR0 + n)) +#define AT91C_UDP_TXVC (AT91_REG(0xFFFB0074)) /* UDP Transceiver Control Register */ /* ========== Register definition for US0 peripheral ========== */ -#define AT91C_US0_CR (AT91_REG(0xFFFC0000)) /* US0 Control Register */ -#define AT91C_US0_MR (AT91_REG(0xFFFC0004)) /* US0 Mode Register */ -#define AT91C_US0_IER (AT91_REG(0xFFFC0008)) /* US0 Interrupt Enable Register */ -#define AT91C_US0_IDR (AT91_REG(0xFFFC000C)) /* US0 Interrupt Disable Register */ -#define AT91C_US0_IMR (AT91_REG(0xFFFC0010)) /* US0 Interrupt Mask Register */ -#define AT91C_US0_CSR (AT91_REG(0xFFFC0014)) /* US0 Channel Status Register */ -#define AT91C_US0_RHR (AT91_REG(0xFFFC0018)) /* US0 Receiver Holding Register */ -#define AT91C_US0_THR (AT91_REG(0xFFFC001C)) /* US0 Transmitter Holding Register */ -#define AT91C_US0_BRGR (AT91_REG(0xFFFC0020)) /* US0 Baud Rate Generator Register */ -#define AT91C_US0_RTOR (AT91_REG(0xFFFC0024)) /* US0 Receiver Time-out Register */ -#define AT91C_US0_TTGR (AT91_REG(0xFFFC0028)) /* US0 Transmitter Time-guard Register */ -#define AT91C_US0_NER (AT91_REG(0xFFFC0044)) /* US0 Nb Errors Register */ -#define AT91C_US0_FIDI (AT91_REG(0xFFFC0040)) /* US0 FI_DI_Ratio Register */ -#define AT91C_US0_IF (AT91_REG(0xFFFC004C)) /* US0 IRDA_FILTER Register */ +#define AT91C_US0_CR (AT91_REG(0xFFFC0000)) /* US0 Control Register */ +#define AT91C_US0_MR (AT91_REG(0xFFFC0004)) /* US0 Mode Register */ +#define AT91C_US0_IER (AT91_REG(0xFFFC0008)) /* US0 Interrupt Enable Register */ +#define AT91C_US0_IDR (AT91_REG(0xFFFC000C)) /* US0 Interrupt Disable Register */ +#define AT91C_US0_IMR (AT91_REG(0xFFFC0010)) /* US0 Interrupt Mask Register */ +#define AT91C_US0_CSR (AT91_REG(0xFFFC0014)) /* US0 Channel Status Register */ +#define AT91C_US0_RHR (AT91_REG(0xFFFC0018)) /* US0 Receiver Holding Register */ +#define AT91C_US0_THR (AT91_REG(0xFFFC001C)) /* US0 Transmitter Holding Register */ +#define AT91C_US0_BRGR (AT91_REG(0xFFFC0020)) /* US0 Baud Rate Generator Register */ +#define AT91C_US0_RTOR (AT91_REG(0xFFFC0024)) /* US0 Receiver Time-out Register */ +#define AT91C_US0_TTGR (AT91_REG(0xFFFC0028)) /* US0 Transmitter Time-guard Register */ +#define AT91C_US0_NER (AT91_REG(0xFFFC0044)) /* US0 Nb Errors Register */ +#define AT91C_US0_FIDI (AT91_REG(0xFFFC0040)) /* US0 FI_DI_Ratio Register */ +#define AT91C_US0_IF (AT91_REG(0xFFFC004C)) /* US0 IRDA_FILTER Register */ /* ========== Register definition for AIC peripheral ========== */ -#define AT91C_AIC_SMR0 (AT91_REG(0xFFFFF000)) /* AIC Source Mode Register */ -#define AT91C_AIC_SMR(n) (*(&AT91C_AIC_SMR0 + n)) -#define AT91C_AIC_SVR0 (AT91_REG(0xFFFFF080)) /* AIC Source Vector Register */ -#define AT91C_AIC_SVR(n) (*(&AT91C_AIC_SVR0 + n)) -#define AT91C_AIC_IVR (AT91_REG(0xFFFFF100)) /* AIC Interrupt Vector Register */ -#define AT91C_AIC_FVR (AT91_REG(0xFFFFF104)) /* AIC FIQ Vector Register */ -#define AT91C_AIC_ISR (AT91_REG(0xFFFFF108)) /* AIC Interrupt Status Register */ -#define AT91C_AIC_IPR (AT91_REG(0xFFFFF10C)) /* AIC Interrupt Pending Register */ -#define AT91C_AIC_IMR (AT91_REG(0xFFFFF110)) /* AIC Interrupt Mask Register */ -#define AT91C_AIC_CISR (AT91_REG(0xFFFFF114)) /* AIC Core Interrupt Status Register */ -#define AT91C_AIC_IECR (AT91_REG(0xFFFFF120)) /* AIC Interrupt Enable Command Register */ -#define AT91C_AIC_IDCR (AT91_REG(0xFFFFF124)) /* AIC Interrupt Disable Command Register */ -#define AT91C_AIC_ICCR (AT91_REG(0xFFFFF128)) /* AIC Interrupt Clear Command Register */ -#define AT91C_AIC_ISCR (AT91_REG(0xFFFFF12C)) /* AIC Interrupt Set Command Register */ -#define AT91C_AIC_EOICR (AT91_REG(0xFFFFF130)) /* AIC End of Interrupt Command Register */ -#define AT91C_AIC_SPU (AT91_REG(0xFFFFF134)) /* AIC Spurious Vector Register */ -#define AT91C_AIC_DCR (AT91_REG(0xFFFFF138)) /* AIC Debug Control Register (Protect) */ -#define AT91C_AIC_FFER (AT91_REG(0xFFFFF140)) /* AIC Fast Forcing Enable Register */ -#define AT91C_AIC_FFDR (AT91_REG(0xFFFFF144)) /* AIC Fast Forcing Disable Register */ -#define AT91C_AIC_FFSR (AT91_REG(0xFFFFF148)) /* AIC Fast Forcing Status Register */ +#define AT91C_AIC_SMR0 (AT91_REG(0xFFFFF000)) /* AIC Source Mode Register */ +#define AT91C_AIC_SMR(n) (*(&AT91C_AIC_SMR0 + n)) +#define AT91C_AIC_SVR0 (AT91_REG(0xFFFFF080)) /* AIC Source Vector Register */ +#define AT91C_AIC_SVR(n) (*(&AT91C_AIC_SVR0 + n)) +#define AT91C_AIC_IVR (AT91_REG(0xFFFFF100)) /* AIC Interrupt Vector Register */ +#define AT91C_AIC_FVR (AT91_REG(0xFFFFF104)) /* AIC FIQ Vector Register */ +#define AT91C_AIC_ISR (AT91_REG(0xFFFFF108)) /* AIC Interrupt Status Register */ +#define AT91C_AIC_IPR (AT91_REG(0xFFFFF10C)) /* AIC Interrupt Pending Register */ +#define AT91C_AIC_IMR (AT91_REG(0xFFFFF110)) /* AIC Interrupt Mask Register */ +#define AT91C_AIC_CISR (AT91_REG(0xFFFFF114)) /* AIC Core Interrupt Status Register */ +#define AT91C_AIC_IECR (AT91_REG(0xFFFFF120)) /* AIC Interrupt Enable Command Register */ +#define AT91C_AIC_IDCR (AT91_REG(0xFFFFF124)) /* AIC Interrupt Disable Command Register */ +#define AT91C_AIC_ICCR (AT91_REG(0xFFFFF128)) /* AIC Interrupt Clear Command Register */ +#define AT91C_AIC_ISCR (AT91_REG(0xFFFFF12C)) /* AIC Interrupt Set Command Register */ +#define AT91C_AIC_EOICR (AT91_REG(0xFFFFF130)) /* AIC End of Interrupt Command Register */ +#define AT91C_AIC_SPU (AT91_REG(0xFFFFF134)) /* AIC Spurious Vector Register */ +#define AT91C_AIC_DCR (AT91_REG(0xFFFFF138)) /* AIC Debug Control Register (Protect) */ +#define AT91C_AIC_FFER (AT91_REG(0xFFFFF140)) /* AIC Fast Forcing Enable Register */ +#define AT91C_AIC_FFDR (AT91_REG(0xFFFFF144)) /* AIC Fast Forcing Disable Register */ +#define AT91C_AIC_FFSR (AT91_REG(0xFFFFF148)) /* AIC Fast Forcing Status Register */ /* ========== Register definition for DBGU peripheral ========== */ -#define AT91C_DBGU_EXID (AT91_REG(0xFFFFF244)) /* DBGU Chip ID Extension Register */ -#define AT91C_DBGU_BRGR (AT91_REG(0xFFFFF220)) /* DBGU Baud Rate Generator Register */ -#define AT91C_DBGU_IDR (AT91_REG(0xFFFFF20C)) /* DBGU Interrupt Disable Register */ -#define AT91C_DBGU_CSR (AT91_REG(0xFFFFF214)) /* DBGU Channel Status Register */ -#define AT91C_DBGU_CIDR (AT91_REG(0xFFFFF240)) /* DBGU Chip ID Register */ -#define AT91C_DBGU_MR (AT91_REG(0xFFFFF204)) /* DBGU Mode Register */ -#define AT91C_DBGU_IMR (AT91_REG(0xFFFFF210)) /* DBGU Interrupt Mask Register */ -#define AT91C_DBGU_CR (AT91_REG(0xFFFFF200)) /* DBGU Control Register */ -#define AT91C_DBGU_FNTR (AT91_REG(0xFFFFF248)) /* DBGU Force NTRST Register */ -#define AT91C_DBGU_THR (AT91_REG(0xFFFFF21C)) /* DBGU Transmitter Holding Register */ -#define AT91C_DBGU_RHR (AT91_REG(0xFFFFF218)) /* DBGU Receiver Holding Register */ -#define AT91C_DBGU_IER (AT91_REG(0xFFFFF208)) /* DBGU Interrupt Enable Register */ +#define AT91C_DBGU_EXID (AT91_REG(0xFFFFF244)) /* DBGU Chip ID Extension Register */ +#define AT91C_DBGU_BRGR (AT91_REG(0xFFFFF220)) /* DBGU Baud Rate Generator Register */ +#define AT91C_DBGU_IDR (AT91_REG(0xFFFFF20C)) /* DBGU Interrupt Disable Register */ +#define AT91C_DBGU_CSR (AT91_REG(0xFFFFF214)) /* DBGU Channel Status Register */ +#define AT91C_DBGU_CIDR (AT91_REG(0xFFFFF240)) /* DBGU Chip ID Register */ +#define AT91C_DBGU_MR (AT91_REG(0xFFFFF204)) /* DBGU Mode Register */ +#define AT91C_DBGU_IMR (AT91_REG(0xFFFFF210)) /* DBGU Interrupt Mask Register */ +#define AT91C_DBGU_CR (AT91_REG(0xFFFFF200)) /* DBGU Control Register */ +#define AT91C_DBGU_FNTR (AT91_REG(0xFFFFF248)) /* DBGU Force NTRST Register */ +#define AT91C_DBGU_THR (AT91_REG(0xFFFFF21C)) /* DBGU Transmitter Holding Register */ +#define AT91C_DBGU_RHR (AT91_REG(0xFFFFF218)) /* DBGU Receiver Holding Register */ +#define AT91C_DBGU_IER (AT91_REG(0xFFFFF208)) /* DBGU Interrupt Enable Register */ /* ========== Register definition for PIO peripheral ========== */ -#define AT91C_PIO_ODR (AT91_REG(0xFFFFF414)) /* PIOA Output Disable Registerr */ -#define AT91C_PIO_SODR (AT91_REG(0xFFFFF430)) /* PIOA Set Output Data Register */ -#define AT91C_PIO_ISR (AT91_REG(0xFFFFF44C)) /* PIOA Interrupt Status Register */ -#define AT91C_PIO_ABSR (AT91_REG(0xFFFFF478)) /* PIOA AB Select Status Register */ -#define AT91C_PIO_IER (AT91_REG(0xFFFFF440)) /* PIOA Interrupt Enable Register */ -#define AT91C_PIO_PPUDR (AT91_REG(0xFFFFF460)) /* PIOA Pull-up Disable Register */ -#define AT91C_PIO_IMR (AT91_REG(0xFFFFF448)) /* PIOA Interrupt Mask Register */ -#define AT91C_PIO_PER (AT91_REG(0xFFFFF400)) /* PIOA PIO Enable Register */ -#define AT91C_PIO_IFDR (AT91_REG(0xFFFFF424)) /* PIOA Input Filter Disable Register */ -#define AT91C_PIO_OWDR (AT91_REG(0xFFFFF4A4)) /* PIOA Output Write Disable Register */ -#define AT91C_PIO_MDSR (AT91_REG(0xFFFFF458)) /* PIOA Multi-driver Status Register */ -#define AT91C_PIO_IDR (AT91_REG(0xFFFFF444)) /* PIOA Interrupt Disable Register */ -#define AT91C_PIO_ODSR (AT91_REG(0xFFFFF438)) /* PIOA Output Data Status Register */ -#define AT91C_PIO_PPUSR (AT91_REG(0xFFFFF468)) /* PIOA Pull-up Status Register */ -#define AT91C_PIO_OWSR (AT91_REG(0xFFFFF4A8)) /* PIOA Output Write Status Register */ -#define AT91C_PIO_BSR (AT91_REG(0xFFFFF474)) /* PIOA Select B Register */ -#define AT91C_PIO_OWER (AT91_REG(0xFFFFF4A0)) /* PIOA Output Write Enable Register */ -#define AT91C_PIO_IFER (AT91_REG(0xFFFFF420)) /* PIOA Input Filter Enable Register */ -#define AT91C_PIO_PDSR (AT91_REG(0xFFFFF43C)) /* PIOA Pin Data Status Register */ -#define AT91C_PIO_PPUER (AT91_REG(0xFFFFF464)) /* PIOA Pull-up Enable Register */ -#define AT91C_PIO_OSR (AT91_REG(0xFFFFF418)) /* PIOA Output Status Register */ -#define AT91C_PIO_ASR (AT91_REG(0xFFFFF470)) /* PIOA Select A Register */ -#define AT91C_PIO_MDDR (AT91_REG(0xFFFFF454)) /* PIOA Multi-driver Disable Register */ -#define AT91C_PIO_CODR (AT91_REG(0xFFFFF434)) /* PIOA Clear Output Data Register */ -#define AT91C_PIO_MDER (AT91_REG(0xFFFFF450)) /* PIOA Multi-driver Enable Register */ -#define AT91C_PIO_PDR (AT91_REG(0xFFFFF404)) /* PIOA PIO Disable Register */ -#define AT91C_PIO_IFSR (AT91_REG(0xFFFFF428)) /* PIOA Input Filter Status Register */ -#define AT91C_PIO_OER (AT91_REG(0xFFFFF410)) /* PIOA Output Enable Register */ -#define AT91C_PIO_PSR (AT91_REG(0xFFFFF408)) /* PIOA PIO Status Register */ +#define AT91C_PIO_ODR (AT91_REG(0xFFFFF414)) /* PIOA Output Disable Registerr */ +#define AT91C_PIO_SODR (AT91_REG(0xFFFFF430)) /* PIOA Set Output Data Register */ +#define AT91C_PIO_ISR (AT91_REG(0xFFFFF44C)) /* PIOA Interrupt Status Register */ +#define AT91C_PIO_ABSR (AT91_REG(0xFFFFF478)) /* PIOA AB Select Status Register */ +#define AT91C_PIO_IER (AT91_REG(0xFFFFF440)) /* PIOA Interrupt Enable Register */ +#define AT91C_PIO_PPUDR (AT91_REG(0xFFFFF460)) /* PIOA Pull-up Disable Register */ +#define AT91C_PIO_IMR (AT91_REG(0xFFFFF448)) /* PIOA Interrupt Mask Register */ +#define AT91C_PIO_PER (AT91_REG(0xFFFFF400)) /* PIOA PIO Enable Register */ +#define AT91C_PIO_IFDR (AT91_REG(0xFFFFF424)) /* PIOA Input Filter Disable Register */ +#define AT91C_PIO_OWDR (AT91_REG(0xFFFFF4A4)) /* PIOA Output Write Disable Register */ +#define AT91C_PIO_MDSR (AT91_REG(0xFFFFF458)) /* PIOA Multi-driver Status Register */ +#define AT91C_PIO_IDR (AT91_REG(0xFFFFF444)) /* PIOA Interrupt Disable Register */ +#define AT91C_PIO_ODSR (AT91_REG(0xFFFFF438)) /* PIOA Output Data Status Register */ +#define AT91C_PIO_PPUSR (AT91_REG(0xFFFFF468)) /* PIOA Pull-up Status Register */ +#define AT91C_PIO_OWSR (AT91_REG(0xFFFFF4A8)) /* PIOA Output Write Status Register */ +#define AT91C_PIO_BSR (AT91_REG(0xFFFFF474)) /* PIOA Select B Register */ +#define AT91C_PIO_OWER (AT91_REG(0xFFFFF4A0)) /* PIOA Output Write Enable Register */ +#define AT91C_PIO_IFER (AT91_REG(0xFFFFF420)) /* PIOA Input Filter Enable Register */ +#define AT91C_PIO_PDSR (AT91_REG(0xFFFFF43C)) /* PIOA Pin Data Status Register */ +#define AT91C_PIO_PPUER (AT91_REG(0xFFFFF464)) /* PIOA Pull-up Enable Register */ +#define AT91C_PIO_OSR (AT91_REG(0xFFFFF418)) /* PIOA Output Status Register */ +#define AT91C_PIO_ASR (AT91_REG(0xFFFFF470)) /* PIOA Select A Register */ +#define AT91C_PIO_MDDR (AT91_REG(0xFFFFF454)) /* PIOA Multi-driver Disable Register */ +#define AT91C_PIO_CODR (AT91_REG(0xFFFFF434)) /* PIOA Clear Output Data Register */ +#define AT91C_PIO_MDER (AT91_REG(0xFFFFF450)) /* PIOA Multi-driver Enable Register */ +#define AT91C_PIO_PDR (AT91_REG(0xFFFFF404)) /* PIOA PIO Disable Register */ +#define AT91C_PIO_IFSR (AT91_REG(0xFFFFF428)) /* PIOA Input Filter Status Register */ +#define AT91C_PIO_OER (AT91_REG(0xFFFFF410)) /* PIOA Output Enable Register */ +#define AT91C_PIO_PSR (AT91_REG(0xFFFFF408)) /* PIOA PIO Status Register */ // ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_IMR (AT91_REG(0xFFFFF448)) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_IER (AT91_REG(0xFFFFF440)) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_OWDR (AT91_REG(0xFFFFF4A4)) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_ISR (AT91_REG(0xFFFFF44C)) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_PPUDR (AT91_REG(0xFFFFF460)) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_MDSR (AT91_REG(0xFFFFF458)) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_MDER (AT91_REG(0xFFFFF450)) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PER (AT91_REG(0xFFFFF400)) // (PIOA) PIO Enable Register -#define AT91C_PIOA_PSR (AT91_REG(0xFFFFF408)) // (PIOA) PIO Status Register -#define AT91C_PIOA_OER (AT91_REG(0xFFFFF410)) // (PIOA) Output Enable Register -#define AT91C_PIOA_BSR (AT91_REG(0xFFFFF474)) // (PIOA) Select B Register -#define AT91C_PIOA_PPUER (AT91_REG(0xFFFFF464)) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_MDDR (AT91_REG(0xFFFFF454)) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_PDR (AT91_REG(0xFFFFF404)) // (PIOA) PIO Disable Register -#define AT91C_PIOA_ODR (AT91_REG(0xFFFFF414)) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_IFDR (AT91_REG(0xFFFFF424)) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_ABSR (AT91_REG(0xFFFFF478)) // (PIOA) AB Select Status Register -#define AT91C_PIOA_ASR (AT91_REG(0xFFFFF470)) // (PIOA) Select A Register -#define AT91C_PIOA_PPUSR (AT91_REG(0xFFFFF468)) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_ODSR (AT91_REG(0xFFFFF438)) // (PIOA) Output Data Status Register -#define AT91C_PIOA_SODR (AT91_REG(0xFFFFF430)) // (PIOA) Set Output Data Register -#define AT91C_PIOA_IFSR (AT91_REG(0xFFFFF428)) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_IFER (AT91_REG(0xFFFFF420)) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_OSR (AT91_REG(0xFFFFF418)) // (PIOA) Output Status Register -#define AT91C_PIOA_IDR (AT91_REG(0xFFFFF444)) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_PDSR (AT91_REG(0xFFFFF43C)) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_CODR (AT91_REG(0xFFFFF434)) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_OWSR (AT91_REG(0xFFFFF4A8)) // (PIOA) Output Write Status Register -#define AT91C_PIOA_OWER (AT91_REG(0xFFFFF4A0)) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IMR (AT91_REG(0xFFFFF448)) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_IER (AT91_REG(0xFFFFF440)) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_OWDR (AT91_REG(0xFFFFF4A4)) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_ISR (AT91_REG(0xFFFFF44C)) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_PPUDR (AT91_REG(0xFFFFF460)) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_MDSR (AT91_REG(0xFFFFF458)) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_MDER (AT91_REG(0xFFFFF450)) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PER (AT91_REG(0xFFFFF400)) // (PIOA) PIO Enable Register +#define AT91C_PIOA_PSR (AT91_REG(0xFFFFF408)) // (PIOA) PIO Status Register +#define AT91C_PIOA_OER (AT91_REG(0xFFFFF410)) // (PIOA) Output Enable Register +#define AT91C_PIOA_BSR (AT91_REG(0xFFFFF474)) // (PIOA) Select B Register +#define AT91C_PIOA_PPUER (AT91_REG(0xFFFFF464)) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_MDDR (AT91_REG(0xFFFFF454)) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_PDR (AT91_REG(0xFFFFF404)) // (PIOA) PIO Disable Register +#define AT91C_PIOA_ODR (AT91_REG(0xFFFFF414)) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_IFDR (AT91_REG(0xFFFFF424)) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_ABSR (AT91_REG(0xFFFFF478)) // (PIOA) AB Select Status Register +#define AT91C_PIOA_ASR (AT91_REG(0xFFFFF470)) // (PIOA) Select A Register +#define AT91C_PIOA_PPUSR (AT91_REG(0xFFFFF468)) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_ODSR (AT91_REG(0xFFFFF438)) // (PIOA) Output Data Status Register +#define AT91C_PIOA_SODR (AT91_REG(0xFFFFF430)) // (PIOA) Set Output Data Register +#define AT91C_PIOA_IFSR (AT91_REG(0xFFFFF428)) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_IFER (AT91_REG(0xFFFFF420)) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_OSR (AT91_REG(0xFFFFF418)) // (PIOA) Output Status Register +#define AT91C_PIOA_IDR (AT91_REG(0xFFFFF444)) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_PDSR (AT91_REG(0xFFFFF43C)) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_CODR (AT91_REG(0xFFFFF434)) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_OWSR (AT91_REG(0xFFFFF4A8)) // (PIOA) Output Write Status Register +#define AT91C_PIOA_OWER (AT91_REG(0xFFFFF4A0)) // (PIOA) Output Write Enable Register // ========== Register definition for PIOB peripheral ========== -#define AT91C_PIOB_OWSR (AT91_REG(0xFFFFF6A8)) // (PIOB) Output Write Status Register -#define AT91C_PIOB_PPUSR (AT91_REG(0xFFFFF668)) // (PIOB) Pull-up Status Register -#define AT91C_PIOB_PPUDR (AT91_REG(0xFFFFF660)) // (PIOB) Pull-up Disable Register -#define AT91C_PIOB_MDSR (AT91_REG(0xFFFFF658)) // (PIOB) Multi-driver Status Register -#define AT91C_PIOB_MDER (AT91_REG(0xFFFFF650)) // (PIOB) Multi-driver Enable Register -#define AT91C_PIOB_IMR (AT91_REG(0xFFFFF648)) // (PIOB) Interrupt Mask Register -#define AT91C_PIOB_OSR (AT91_REG(0xFFFFF618)) // (PIOB) Output Status Register -#define AT91C_PIOB_OER (AT91_REG(0xFFFFF610)) // (PIOB) Output Enable Register -#define AT91C_PIOB_PSR (AT91_REG(0xFFFFF608)) // (PIOB) PIO Status Register -#define AT91C_PIOB_PER (AT91_REG(0xFFFFF600)) // (PIOB) PIO Enable Register -#define AT91C_PIOB_BSR (AT91_REG(0xFFFFF674)) // (PIOB) Select B Register -#define AT91C_PIOB_PPUER (AT91_REG(0xFFFFF664)) // (PIOB) Pull-up Enable Register -#define AT91C_PIOB_IFDR (AT91_REG(0xFFFFF624)) // (PIOB) Input Filter Disable Register -#define AT91C_PIOB_ODR (AT91_REG(0xFFFFF614)) // (PIOB) Output Disable Registerr -#define AT91C_PIOB_ABSR (AT91_REG(0xFFFFF678)) // (PIOB) AB Select Status Register -#define AT91C_PIOB_ASR (AT91_REG(0xFFFFF670)) // (PIOB) Select A Register -#define AT91C_PIOB_IFER (AT91_REG(0xFFFFF620)) // (PIOB) Input Filter Enable Register -#define AT91C_PIOB_IFSR (AT91_REG(0xFFFFF628)) // (PIOB) Input Filter Status Register -#define AT91C_PIOB_SODR (AT91_REG(0xFFFFF630)) // (PIOB) Set Output Data Register -#define AT91C_PIOB_ODSR (AT91_REG(0xFFFFF638)) // (PIOB) Output Data Status Register -#define AT91C_PIOB_CODR (AT91_REG(0xFFFFF634)) // (PIOB) Clear Output Data Register -#define AT91C_PIOB_PDSR (AT91_REG(0xFFFFF63C)) // (PIOB) Pin Data Status Register -#define AT91C_PIOB_OWER (AT91_REG(0xFFFFF6A0)) // (PIOB) Output Write Enable Register -#define AT91C_PIOB_IER (AT91_REG(0xFFFFF640)) // (PIOB) Interrupt Enable Register -#define AT91C_PIOB_OWDR (AT91_REG(0xFFFFF6A4)) // (PIOB) Output Write Disable Register -#define AT91C_PIOB_MDDR (AT91_REG(0xFFFFF654)) // (PIOB) Multi-driver Disable Register -#define AT91C_PIOB_ISR (AT91_REG(0xFFFFF64C)) // (PIOB) Interrupt Status Register -#define AT91C_PIOB_IDR (AT91_REG(0xFFFFF644)) // (PIOB) Interrupt Disable Register -#define AT91C_PIOB_PDR (AT91_REG(0xFFFFF604)) // (PIOB) PIO Disable Register +#define AT91C_PIOB_OWSR (AT91_REG(0xFFFFF6A8)) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PPUSR (AT91_REG(0xFFFFF668)) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_PPUDR (AT91_REG(0xFFFFF660)) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_MDSR (AT91_REG(0xFFFFF658)) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_MDER (AT91_REG(0xFFFFF650)) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_IMR (AT91_REG(0xFFFFF648)) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_OSR (AT91_REG(0xFFFFF618)) // (PIOB) Output Status Register +#define AT91C_PIOB_OER (AT91_REG(0xFFFFF610)) // (PIOB) Output Enable Register +#define AT91C_PIOB_PSR (AT91_REG(0xFFFFF608)) // (PIOB) PIO Status Register +#define AT91C_PIOB_PER (AT91_REG(0xFFFFF600)) // (PIOB) PIO Enable Register +#define AT91C_PIOB_BSR (AT91_REG(0xFFFFF674)) // (PIOB) Select B Register +#define AT91C_PIOB_PPUER (AT91_REG(0xFFFFF664)) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_IFDR (AT91_REG(0xFFFFF624)) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_ODR (AT91_REG(0xFFFFF614)) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_ABSR (AT91_REG(0xFFFFF678)) // (PIOB) AB Select Status Register +#define AT91C_PIOB_ASR (AT91_REG(0xFFFFF670)) // (PIOB) Select A Register +#define AT91C_PIOB_IFER (AT91_REG(0xFFFFF620)) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_IFSR (AT91_REG(0xFFFFF628)) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_SODR (AT91_REG(0xFFFFF630)) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ODSR (AT91_REG(0xFFFFF638)) // (PIOB) Output Data Status Register +#define AT91C_PIOB_CODR (AT91_REG(0xFFFFF634)) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_PDSR (AT91_REG(0xFFFFF63C)) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_OWER (AT91_REG(0xFFFFF6A0)) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_IER (AT91_REG(0xFFFFF640)) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_OWDR (AT91_REG(0xFFFFF6A4)) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDDR (AT91_REG(0xFFFFF654)) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_ISR (AT91_REG(0xFFFFF64C)) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_IDR (AT91_REG(0xFFFFF644)) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_PDR (AT91_REG(0xFFFFF604)) // (PIOB) PIO Disable Register /* ========== Register definition for PMC peripheral ========== */ -#define AT91C_PMC_SCER (AT91_REG(0xFFFFFC00)) /* PMC System Clock Enable Register */ -#define AT91C_PMC_SCDR (AT91_REG(0xFFFFFC04)) /* PMC System Clock Disable Register */ -#define AT91C_PMC_SCSR (AT91_REG(0xFFFFFC08)) /* PMC System Clock Status Register */ -#define AT91C_PMC_PCER (AT91_REG(0xFFFFFC10)) /* PMC Peripheral Clock Enable Register */ -#define AT91C_PMC_PCDR (AT91_REG(0xFFFFFC14)) /* PMC Peripheral Clock Disable Register */ -#define AT91C_PMC_PCSR (AT91_REG(0xFFFFFC18)) /* PMC Peripheral Clock Status Register */ -#define AT91C_PMC_MOR (AT91_REG(0xFFFFFC20)) /* PMC Main Oscillator Register */ -#define AT91C_PMC_MCFR (AT91_REG(0xFFFFFC24)) /* PMC Main Clock Frequency Register */ -#define AT91C_PMC_PLLR (AT91_REG(0xFFFFFC2C)) /* PMC PLL Register */ -#define AT91C_PMC_MCKR (AT91_REG(0xFFFFFC30)) /* PMC Master Clock Register */ -#define AT91C_PMC_PCKR (AT91_REG(0xFFFFFC40)) /* PMC Programmable Clock Register */ -#define AT91C_PMC_IER (AT91_REG(0xFFFFFC60)) /* PMC Interrupt Enable Register */ -#define AT91C_PMC_IDR (AT91_REG(0xFFFFFC64)) /* PMC Interrupt Disable Register */ -#define AT91C_PMC_SR (AT91_REG(0xFFFFFC68)) /* PMC Status Register */ -#define AT91C_PMC_IMR (AT91_REG(0xFFFFFC6C)) /* PMC Interrupt Mask Register */ +#define AT91C_PMC_SCER (AT91_REG(0xFFFFFC00)) /* PMC System Clock Enable Register */ +#define AT91C_PMC_SCDR (AT91_REG(0xFFFFFC04)) /* PMC System Clock Disable Register */ +#define AT91C_PMC_SCSR (AT91_REG(0xFFFFFC08)) /* PMC System Clock Status Register */ +#define AT91C_PMC_PCER (AT91_REG(0xFFFFFC10)) /* PMC Peripheral Clock Enable Register */ +#define AT91C_PMC_PCDR (AT91_REG(0xFFFFFC14)) /* PMC Peripheral Clock Disable Register */ +#define AT91C_PMC_PCSR (AT91_REG(0xFFFFFC18)) /* PMC Peripheral Clock Status Register */ +#define AT91C_PMC_MOR (AT91_REG(0xFFFFFC20)) /* PMC Main Oscillator Register */ +#define AT91C_PMC_MCFR (AT91_REG(0xFFFFFC24)) /* PMC Main Clock Frequency Register */ +#define AT91C_PMC_PLLR (AT91_REG(0xFFFFFC2C)) /* PMC PLL Register */ +#define AT91C_PMC_MCKR (AT91_REG(0xFFFFFC30)) /* PMC Master Clock Register */ +#define AT91C_PMC_PCKR (AT91_REG(0xFFFFFC40)) /* PMC Programmable Clock Register */ +#define AT91C_PMC_IER (AT91_REG(0xFFFFFC60)) /* PMC Interrupt Enable Register */ +#define AT91C_PMC_IDR (AT91_REG(0xFFFFFC64)) /* PMC Interrupt Disable Register */ +#define AT91C_PMC_SR (AT91_REG(0xFFFFFC68)) /* PMC Status Register */ +#define AT91C_PMC_IMR (AT91_REG(0xFFFFFC6C)) /* PMC Interrupt Mask Register */ -// ========== Register definition for PDC_SPI1 peripheral ========== +// ========== Register definition for PDC_SPI1 peripheral ========== #define AT91C_SPI1_RNPR (AT91_REG(0xFFFE4110)) // (PDC_SPI1) Receive Next Pointer Register #define AT91C_SPI1_TPR (AT91_REG(0xFFFE4108)) // (PDC_SPI1) Transmit Pointer Register #define AT91C_SPI1_RPR (AT91_REG(0xFFFE4100)) // (PDC_SPI1) Receive Pointer Register @@ -252,7 +252,7 @@ extern "C" { #define AT91C_SPI1_TNCR (AT91_REG(0xFFFE411C)) // (PDC_SPI1) Transmit Next Counter Register #define AT91C_SPI1_TNPR (AT91_REG(0xFFFE4118)) // (PDC_SPI1) Transmit Next Pointer Register #define AT91C_SPI1_PTCR (AT91_REG(0xFFFE4120)) // (PDC_SPI1) PDC Transfer Control Register -// ========== Register definition for SPI1 peripheral ========== +// ========== Register definition for SPI1 peripheral ========== #define AT91C_SPI1_CSR (AT91_REG(0xFFFE4030)) // (SPI1) Chip Select Register #define AT91C_SPI1_IDR (AT91_REG(0xFFFE4018)) // (SPI1) Interrupt Disable Register #define AT91C_SPI1_SR (AT91_REG(0xFFFE4010)) // (SPI1) Status Register @@ -262,7 +262,7 @@ extern "C" { #define AT91C_SPI1_IER (AT91_REG(0xFFFE4014)) // (SPI1) Interrupt Enable Register #define AT91C_SPI1_TDR (AT91_REG(0xFFFE400C)) // (SPI1) Transmit Data Register #define AT91C_SPI1_MR (AT91_REG(0xFFFE4004)) // (SPI1) Mode Register -// ========== Register definition for PDC_SPI0 peripheral ========== +// ========== Register definition for PDC_SPI0 peripheral ========== #define AT91C_SPI0_PTCR (AT91_REG(0xFFFE0120)) // (PDC_SPI0) PDC Transfer Control Register #define AT91C_SPI0_TNPR (AT91_REG(0xFFFE0118)) // (PDC_SPI0) Transmit Next Pointer Register #define AT91C_SPI0_RNPR (AT91_REG(0xFFFE0110)) // (PDC_SPI0) Receive Next Pointer Register @@ -273,7 +273,7 @@ extern "C" { #define AT91C_SPI0_RNCR (AT91_REG(0xFFFE0114)) // (PDC_SPI0) Receive Next Counter Register #define AT91C_SPI0_TCR (AT91_REG(0xFFFE010C)) // (PDC_SPI0) Transmit Counter Register #define AT91C_SPI0_RCR (AT91_REG(0xFFFE0104)) // (PDC_SPI0) Receive Counter Register -// ========== Register definition for SPI0 peripheral ========== +// ========== Register definition for SPI0 peripheral ========== #define AT91C_SPI0_CSR (AT91_REG(0xFFFE0030)) // (SPI0) Chip Select Register #define AT91C_SPI0_IDR (AT91_REG(0xFFFE0018)) // (SPI0) Interrupt Disable Register #define AT91C_SPI0_SR (AT91_REG(0xFFFE0010)) // (SPI0) Status Register @@ -321,19 +321,19 @@ extern "C" { #define AT91C_ID_IRQ1 (31) /* Advanced Interrupt Controller (IRQ1) */ #define AT91C_ALL_INT (0xC00FFFFF) /* ALL VALID INTERRUPTS */ -#define MCK 48054857 +#define MCK 48054857 /*****************************/ /* CPU Mode */ /*****************************/ -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define ABORTMODE 0x17 -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define ABORTMODE 0x17 +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 #ifdef __cplusplus } diff --git a/bsp/sam7x/drivers/board.c b/bsp/sam7x/drivers/board.c index 1e13656f66..571e7e724c 100644 --- a/bsp/sam7x/drivers/board.c +++ b/bsp/sam7x/drivers/board.c @@ -35,40 +35,40 @@ static void rt_hw_board_led_init(void); */ void rt_hw_timer_handler(int vector, void* param) { - if (AT91C_BASE_PITC->PITC_PISR & 0x01) - { - /* increase a tick */ - rt_tick_increase(); - - /* ack interrupt */ - AT91C_BASE_AIC->AIC_EOICR = AT91C_BASE_PITC->PITC_PIVR; - } - else - { - /* end of interrupt */ - AT91C_BASE_AIC->AIC_EOICR = 0; - } + if (AT91C_BASE_PITC->PITC_PISR & 0x01) + { + /* increase a tick */ + rt_tick_increase(); + + /* ack interrupt */ + AT91C_BASE_AIC->AIC_EOICR = AT91C_BASE_PITC->PITC_PIVR; + } + else + { + /* end of interrupt */ + AT91C_BASE_AIC->AIC_EOICR = 0; + } } - /* PIO Flash PA PB PIN */ -#define LED1 (1 << 19) /* PA0 / PGMEN0 & PWM0 TIOA0 48 */ -#define LED2 (1 << 20) /* PA1 / PGMEN1 & PWM1 TIOB0 47 */ -#define LED3 (1 << 21) /* PA2 & PWM2 SCK0 44 */ -#define LED4 (1 << 22) /* PA3 & TWD NPCS3 43 */ -#define LED_MASK (LED1|LED2|LED3|LED4) + /* PIO Flash PA PB PIN */ +#define LED1 (1 << 19) /* PA0 / PGMEN0 & PWM0 TIOA0 48 */ +#define LED2 (1 << 20) /* PA1 / PGMEN1 & PWM1 TIOB0 47 */ +#define LED3 (1 << 21) /* PA2 & PWM2 SCK0 44 */ +#define LED4 (1 << 22) /* PA3 & TWD NPCS3 43 */ +#define LED_MASK (LED1|LED2|LED3|LED4) int leds[] = {LED1, LED2, LED3, LED4}; -/** +/** * This function will init led on the board */ static void rt_hw_board_led_init() { - /* enable the clock of the PIO A, PIO B */ - AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOA | 1 << AT91C_ID_PIOB; + /* enable the clock of the PIO A, PIO B */ + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOA | 1 << AT91C_ID_PIOB; - /* configure PIO as output for led */ - AT91C_BASE_PIOB->PIO_PER = LED_MASK; - AT91C_BASE_PIOB->PIO_OER = LED_MASK; + /* configure PIO as output for led */ + AT91C_BASE_PIOB->PIO_PER = LED_MASK; + AT91C_BASE_PIOB->PIO_OER = LED_MASK; } /** @@ -78,10 +78,10 @@ static void rt_hw_board_led_init() */ void rt_hw_board_led_on(int n) { - if (n >= 0 && n < 4) - { - AT91C_BASE_PIOB->PIO_CODR = leds[n]; - } + if (n >= 0 && n < 4) + { + AT91C_BASE_PIOB->PIO_CODR = leds[n]; + } } /** @@ -91,10 +91,10 @@ void rt_hw_board_led_on(int n) */ void rt_hw_board_led_off(int n) { - if (n >= 0 && n < 4) - { - AT91C_BASE_PIOB->PIO_SODR = leds[n]; - } + if (n >= 0 && n < 4) + { + AT91C_BASE_PIOB->PIO_SODR = leds[n]; + } } /* @@ -108,47 +108,47 @@ void rt_hw_board_led_off(int n) */ void rt_hw_console_output(const char* str) { - while (*str) - { - if (*str == '\n') - { - while (!(AT91C_BASE_US0->US_CSR & AT91C_US_TXRDY)); - AT91C_BASE_US0->US_THR = '\r'; - } - - /* Wait for Empty Tx Buffer */ - while (!(AT91C_BASE_US0->US_CSR & AT91C_US_TXRDY)); - /* Transmit Character */ - AT91C_BASE_US0->US_THR = *str; - - str ++; - } + while (*str) + { + if (*str == '\n') + { + while (!(AT91C_BASE_US0->US_CSR & AT91C_US_TXRDY)); + AT91C_BASE_US0->US_THR = '\r'; + } + + /* Wait for Empty Tx Buffer */ + while (!(AT91C_BASE_US0->US_CSR & AT91C_US_TXRDY)); + /* Transmit Character */ + AT91C_BASE_US0->US_THR = *str; + + str ++; + } } static void rt_hw_console_init() { - /* Enable Clock for USART0 */ - AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US0; - /* Enable RxD0 and TxD0 Pin */ - //AT91C_BASE_PIOA->PIO_PDR = (1 << 5) | (1 << 6); - AT91C_BASE_PIOA->PIO_PDR = 1 | (1 << 1);//fix bug 2010-3-9 - - AT91C_BASE_US0->US_CR = AT91C_US_RSTRX | /* Reset Receiver */ - AT91C_US_RSTTX | /* Reset Transmitter */ - AT91C_US_RXDIS | /* Receiver Disable */ - AT91C_US_TXDIS; /* Transmitter Disable */ - - AT91C_BASE_US0->US_MR = AT91C_US_USMODE_NORMAL | /* Normal Mode */ - AT91C_US_CLKS_CLOCK | /* Clock = MCK */ - AT91C_US_CHRL_8_BITS | /* 8-bit Data */ - AT91C_US_PAR_NONE | /* No Parity */ - AT91C_US_NBSTOP_1_BIT; /* 1 Stop Bit */ - - /* set baud rate divisor */ - AT91C_BASE_US0->US_BRGR = BRD; - - AT91C_BASE_US0->US_CR = AT91C_US_RXEN | /* Receiver Enable */ - AT91C_US_TXEN; /* Transmitter Enable */ + /* Enable Clock for USART0 */ + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US0; + /* Enable RxD0 and TxD0 Pin */ + //AT91C_BASE_PIOA->PIO_PDR = (1 << 5) | (1 << 6); + AT91C_BASE_PIOA->PIO_PDR = 1 | (1 << 1);//fix bug 2010-3-9 + + AT91C_BASE_US0->US_CR = AT91C_US_RSTRX | /* Reset Receiver */ + AT91C_US_RSTTX | /* Reset Transmitter */ + AT91C_US_RXDIS | /* Receiver Disable */ + AT91C_US_TXDIS; /* Transmitter Disable */ + + AT91C_BASE_US0->US_MR = AT91C_US_USMODE_NORMAL | /* Normal Mode */ + AT91C_US_CLKS_CLOCK | /* Clock = MCK */ + AT91C_US_CHRL_8_BITS | /* 8-bit Data */ + AT91C_US_PAR_NONE | /* No Parity */ + AT91C_US_NBSTOP_1_BIT; /* 1 Stop Bit */ + + /* set baud rate divisor */ + AT91C_BASE_US0->US_BRGR = BRD; + + AT91C_BASE_US0->US_CR = AT91C_US_RXEN | /* Receiver Enable */ + AT91C_US_TXEN; /* Transmitter Enable */ } /** @@ -156,20 +156,20 @@ static void rt_hw_console_init() */ void rt_hw_board_init(void) { - extern void rt_serial_init(void); - - /* init hardware console */ - rt_hw_console_init(); + extern void rt_serial_init(void); + + /* init hardware console */ + rt_hw_console_init(); - /* init led */ - rt_hw_board_led_init(); + /* init led */ + rt_hw_board_led_init(); - /* init PITC */ - AT91C_BASE_PITC->PITC_PIMR = (1 << 25) | (1 << 24) | PIV; + /* init PITC */ + AT91C_BASE_PITC->PITC_PIMR = (1 << 25) | (1 << 24) | PIV; - /* install timer handler */ - rt_hw_interrupt_install(AT91C_ID_SYS, rt_hw_timer_handler, RT_NULL, "tick"); - AT91C_BASE_AIC->AIC_SMR[AT91C_ID_SYS] = 0; - rt_hw_interrupt_umask(AT91C_ID_SYS); + /* install timer handler */ + rt_hw_interrupt_install(AT91C_ID_SYS, rt_hw_timer_handler, RT_NULL, "tick"); + AT91C_BASE_AIC->AIC_SMR[AT91C_ID_SYS] = 0; + rt_hw_interrupt_umask(AT91C_ID_SYS); } /*@}*/ diff --git a/bsp/sam7x/drivers/board.h b/bsp/sam7x/drivers/board.h index 97a1e449fc..fbabb628ba 100644 --- a/bsp/sam7x/drivers/board.h +++ b/bsp/sam7x/drivers/board.h @@ -19,9 +19,9 @@ #include -#define MCK 48054857 -#define BR 115200 /* Baud Rate */ -#define BRD (MCK/16/BR) /* Baud Rate Divisor */ +#define MCK 48054857 +#define BR 115200 /* Baud Rate */ +#define BRD (MCK/16/BR) /* Baud Rate Divisor */ void rt_hw_board_led_on(int n); void rt_hw_board_led_off(int n); diff --git a/bsp/sam7x/drivers/serial.c b/bsp/sam7x/drivers/serial.c index 48fe49fed8..0f6d04a648 100644 --- a/bsp/sam7x/drivers/serial.c +++ b/bsp/sam7x/drivers/serial.c @@ -28,46 +28,46 @@ typedef volatile rt_uint32_t REG32; struct rt_at91serial_hw { - REG32 US_CR; // Control Register - REG32 US_MR; // Mode Register - REG32 US_IER; // Interrupt Enable Register - REG32 US_IDR; // Interrupt Disable Register - REG32 US_IMR; // Interrupt Mask Register - REG32 US_CSR; // Channel Status Register - REG32 US_RHR; // Receiver Holding Register - REG32 US_THR; // Transmitter Holding Register - REG32 US_BRGR; // Baud Rate Generator Register - REG32 US_RTOR; // Receiver Time-out Register - REG32 US_TTGR; // Transmitter Time-guard Register - REG32 Reserved0[5]; // - REG32 US_FIDI; // FI_DI_Ratio Register - REG32 US_NER; // Nb Errors Register - REG32 Reserved1[1]; // - REG32 US_IF; // IRDA_FILTER Register - REG32 Reserved2[44]; // - REG32 US_RPR; // Receive Pointer Register - REG32 US_RCR; // Receive Counter Register - REG32 US_TPR; // Transmit Pointer Register - REG32 US_TCR; // Transmit Counter Register - REG32 US_RNPR; // Receive Next Pointer Register - REG32 US_RNCR; // Receive Next Counter Register - REG32 US_TNPR; // Transmit Next Pointer Register - REG32 US_TNCR; // Transmit Next Counter Register - REG32 US_PTCR; // PDC Transfer Control Register - REG32 US_PTSR; // PDC Transfer Status Register + REG32 US_CR; // Control Register + REG32 US_MR; // Mode Register + REG32 US_IER; // Interrupt Enable Register + REG32 US_IDR; // Interrupt Disable Register + REG32 US_IMR; // Interrupt Mask Register + REG32 US_CSR; // Channel Status Register + REG32 US_RHR; // Receiver Holding Register + REG32 US_THR; // Transmitter Holding Register + REG32 US_BRGR; // Baud Rate Generator Register + REG32 US_RTOR; // Receiver Time-out Register + REG32 US_TTGR; // Transmitter Time-guard Register + REG32 Reserved0[5]; // + REG32 US_FIDI; // FI_DI_Ratio Register + REG32 US_NER; // Nb Errors Register + REG32 Reserved1[1]; // + REG32 US_IF; // IRDA_FILTER Register + REG32 Reserved2[44]; // + REG32 US_RPR; // Receive Pointer Register + REG32 US_RCR; // Receive Counter Register + REG32 US_TPR; // Transmit Pointer Register + REG32 US_TCR; // Transmit Counter Register + REG32 US_RNPR; // Receive Next Pointer Register + REG32 US_RNCR; // Receive Next Counter Register + REG32 US_TNPR; // Transmit Next Pointer Register + REG32 US_TNCR; // Transmit Next Counter Register + REG32 US_PTCR; // PDC Transfer Control Register + REG32 US_PTSR; // PDC Transfer Status Register }; struct rt_at91serial { - struct rt_device parent; + struct rt_device parent; - struct rt_at91serial_hw* hw_base; - rt_uint16_t peripheral_id; - rt_uint32_t baudrate; + struct rt_at91serial_hw* hw_base; + rt_uint16_t peripheral_id; + rt_uint32_t baudrate; - /* reception field */ - rt_uint16_t save_index, read_index; - rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; + /* reception field */ + rt_uint16_t save_index, read_index; + rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; }; #ifdef RT_USING_UART1 struct rt_at91serial serial1; @@ -78,312 +78,312 @@ struct rt_at91serial serial2; static void rt_hw_serial_isr(int irqno, void* param) { - rt_base_t level; - struct rt_device* device; - struct rt_at91serial* serial = (struct rt_at91serial*)param; + rt_base_t level; + struct rt_device* device; + struct rt_at91serial* serial = (struct rt_at91serial*)param; - RT_ASSERT(serial != RT_NULL); + RT_ASSERT(serial != RT_NULL); - /* get generic device object */ - device = (rt_device_t)serial; + /* get generic device object */ + device = (rt_device_t)serial; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - /* get received character */ - serial->rx_buffer[serial->save_index] = serial->hw_base->US_RHR; + /* get received character */ + serial->rx_buffer[serial->save_index] = serial->hw_base->US_RHR; - /* move to next position */ - serial->save_index ++; - if (serial->save_index >= RT_UART_RX_BUFFER_SIZE) - serial->save_index = 0; + /* move to next position */ + serial->save_index ++; + if (serial->save_index >= RT_UART_RX_BUFFER_SIZE) + serial->save_index = 0; - /* if the next position is read index, discard this 'read char' */ - if (serial->save_index == serial->read_index) - { - serial->read_index ++; - if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) - serial->read_index = 0; - } + /* if the next position is read index, discard this 'read char' */ + if (serial->save_index == serial->read_index) + { + serial->read_index ++; + if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) + serial->read_index = 0; + } - /* enable interrupt */ - rt_hw_interrupt_enable(level); + /* enable interrupt */ + rt_hw_interrupt_enable(level); - /* indicate to upper layer application */ - if (device->rx_indicate != RT_NULL) - device->rx_indicate(device, 1); + /* indicate to upper layer application */ + if (device->rx_indicate != RT_NULL) + device->rx_indicate(device, 1); - /* ack interrupt */ - AT91C_AIC_EOICR = 1; + /* ack interrupt */ + AT91C_AIC_EOICR = 1; } static rt_err_t rt_serial_init (rt_device_t dev) { - rt_uint32_t bd; - struct rt_at91serial* serial = (struct rt_at91serial*) dev; - - RT_ASSERT(serial != RT_NULL); - /* must be US0 or US1 */ - RT_ASSERT((serial->peripheral_id == AT91C_ID_US0) || - (serial->peripheral_id == AT91C_ID_US1)); - - /* Enable Clock for USART */ - AT91C_PMC_PCER = 1 << serial->peripheral_id; - - /* Enable RxD0 and TxDO Pin */ - if (serial->peripheral_id == AT91C_ID_US0) - { - /* set pinmux */ - //AT91C_PIO_PDR = (1 << 5) | (1 << 6); - AT91C_PIO_PDR = 1 | (1 << 1); //fix bug 2010-3-9 - } - else if (serial->peripheral_id == AT91C_ID_US1) - { - /* set pinmux */ - //AT91C_PIO_PDR = (1 << 21) | (1 << 22); - AT91C_PIO_PDR = (1 << 5) | (1 << 6); //fix bug 2010-3-9 - } - - serial->hw_base->US_CR = AT91C_US_RSTRX | /* Reset Receiver */ - AT91C_US_RSTTX | /* Reset Transmitter */ - AT91C_US_RXDIS | /* Receiver Disable */ - AT91C_US_TXDIS; /* Transmitter Disable */ - - serial->hw_base->US_MR = AT91C_US_USMODE_NORMAL | /* Normal Mode */ - AT91C_US_CLKS_CLOCK | /* Clock = MCK */ - AT91C_US_CHRL_8_BITS | /* 8-bit Data */ - AT91C_US_PAR_NONE | /* No Parity */ - AT91C_US_NBSTOP_1_BIT; /* 1 Stop Bit */ - - /* set baud rate divisor */ - bd = ((MCK*10)/(serial->baudrate * 16)); - if ((bd % 10) >= 5) bd = (bd / 10) + 1; - else bd /= 10; - - serial->hw_base->US_BRGR = bd; - serial->hw_base->US_CR = AT91C_US_RXEN | /* Receiver Enable */ - AT91C_US_TXEN; /* Transmitter Enable */ - - /* reset rx index */ - serial->save_index = 0; - serial->read_index = 0; - - /* reset rx buffer */ - rt_memset(serial->rx_buffer, 0, RT_UART_RX_BUFFER_SIZE); - - return RT_EOK; + rt_uint32_t bd; + struct rt_at91serial* serial = (struct rt_at91serial*) dev; + + RT_ASSERT(serial != RT_NULL); + /* must be US0 or US1 */ + RT_ASSERT((serial->peripheral_id == AT91C_ID_US0) || + (serial->peripheral_id == AT91C_ID_US1)); + + /* Enable Clock for USART */ + AT91C_PMC_PCER = 1 << serial->peripheral_id; + + /* Enable RxD0 and TxDO Pin */ + if (serial->peripheral_id == AT91C_ID_US0) + { + /* set pinmux */ + //AT91C_PIO_PDR = (1 << 5) | (1 << 6); + AT91C_PIO_PDR = 1 | (1 << 1); //fix bug 2010-3-9 + } + else if (serial->peripheral_id == AT91C_ID_US1) + { + /* set pinmux */ + //AT91C_PIO_PDR = (1 << 21) | (1 << 22); + AT91C_PIO_PDR = (1 << 5) | (1 << 6); //fix bug 2010-3-9 + } + + serial->hw_base->US_CR = AT91C_US_RSTRX | /* Reset Receiver */ + AT91C_US_RSTTX | /* Reset Transmitter */ + AT91C_US_RXDIS | /* Receiver Disable */ + AT91C_US_TXDIS; /* Transmitter Disable */ + + serial->hw_base->US_MR = AT91C_US_USMODE_NORMAL | /* Normal Mode */ + AT91C_US_CLKS_CLOCK | /* Clock = MCK */ + AT91C_US_CHRL_8_BITS | /* 8-bit Data */ + AT91C_US_PAR_NONE | /* No Parity */ + AT91C_US_NBSTOP_1_BIT; /* 1 Stop Bit */ + + /* set baud rate divisor */ + bd = ((MCK*10)/(serial->baudrate * 16)); + if ((bd % 10) >= 5) bd = (bd / 10) + 1; + else bd /= 10; + + serial->hw_base->US_BRGR = bd; + serial->hw_base->US_CR = AT91C_US_RXEN | /* Receiver Enable */ + AT91C_US_TXEN; /* Transmitter Enable */ + + /* reset rx index */ + serial->save_index = 0; + serial->read_index = 0; + + /* reset rx buffer */ + rt_memset(serial->rx_buffer, 0, RT_UART_RX_BUFFER_SIZE); + + return RT_EOK; } static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) { - struct rt_at91serial *serial = (struct rt_at91serial*)dev; - RT_ASSERT(serial != RT_NULL); + struct rt_at91serial *serial = (struct rt_at91serial*)dev; + RT_ASSERT(serial != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* enable UART rx interrupt */ - serial->hw_base->US_IER = 1 << 0; /* RxReady interrupt */ + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* enable UART rx interrupt */ + serial->hw_base->US_IER = 1 << 0; /* RxReady interrupt */ // US_IMR is a READ-ONLY register! - //serial->hw_base->US_IMR |= 1 << 0; /* umask RxReady interrupt */ - - /* install UART handler */ - rt_hw_interrupt_install(serial->peripheral_id, rt_hw_serial_isr, serial, "uart"); - // SAM7X Datasheet 30.5.3: - // It is notrecommended to use the USART interrupt line in edge sensitive mode - //AT91C_AIC_SMR(serial->peripheral_id) = 5 | (0x01 << 5); - AT91C_AIC_SMR(serial->peripheral_id) = 5; - rt_hw_interrupt_umask(serial->peripheral_id); - } - - return RT_EOK; + //serial->hw_base->US_IMR |= 1 << 0; /* umask RxReady interrupt */ + + /* install UART handler */ + rt_hw_interrupt_install(serial->peripheral_id, rt_hw_serial_isr, serial, "uart"); + // SAM7X Datasheet 30.5.3: + // It is notrecommended to use the USART interrupt line in edge sensitive mode + //AT91C_AIC_SMR(serial->peripheral_id) = 5 | (0x01 << 5); + AT91C_AIC_SMR(serial->peripheral_id) = 5; + rt_hw_interrupt_umask(serial->peripheral_id); + } + + return RT_EOK; } static rt_err_t rt_serial_close(rt_device_t dev) { - struct rt_at91serial *serial = (struct rt_at91serial*)dev; - RT_ASSERT(serial != RT_NULL); - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* disable interrupt */ - serial->hw_base->US_IDR = 1 << 0; /* RxReady interrupt */ - //serial->hw_base->US_IMR &= ~(1 << 0); /* mask RxReady interrupt */ - } - - serial->hw_base->US_CR = AT91C_US_RSTRX | /* Reset Receiver */ - AT91C_US_RSTTX | /* Reset Transmitter */ - AT91C_US_RXDIS | /* Receiver Disable */ - AT91C_US_TXDIS; /* Transmitter Disable */ - - return RT_EOK; + struct rt_at91serial *serial = (struct rt_at91serial*)dev; + RT_ASSERT(serial != RT_NULL); + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* disable interrupt */ + serial->hw_base->US_IDR = 1 << 0; /* RxReady interrupt */ + //serial->hw_base->US_IMR &= ~(1 << 0); /* mask RxReady interrupt */ + } + + serial->hw_base->US_CR = AT91C_US_RSTRX | /* Reset Receiver */ + AT91C_US_RSTTX | /* Reset Transmitter */ + AT91C_US_RXDIS | /* Receiver Disable */ + AT91C_US_TXDIS; /* Transmitter Disable */ + + return RT_EOK; } static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - struct rt_at91serial *serial = (struct rt_at91serial*)dev; - RT_ASSERT(serial != RT_NULL); - - /* point to buffer */ - ptr = (rt_uint8_t*) buffer; - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - while (size) - { - /* interrupt receive */ - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - if (serial->read_index != serial->save_index) - { - *ptr = serial->rx_buffer[serial->read_index]; - - serial->read_index ++; - if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) - serial->read_index = 0; - } - else - { - /* no data in rx buffer */ - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - break; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - - ptr ++; - size --; - } - - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; - } - else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) - { - /* not support right now */ - RT_ASSERT(0); - } - else - { - /* poll mode */ - while (size) - { - /* Wait for Full Rx Buffer */ - while (!(serial->hw_base->US_CSR & AT91C_US_RXRDY)); - - /* Read Character */ - *ptr = serial->hw_base->US_RHR; - ptr ++; - size --; - } - - return (rt_size_t)ptr - (rt_size_t)buffer; - } - - return 0; + rt_uint8_t* ptr; + struct rt_at91serial *serial = (struct rt_at91serial*)dev; + RT_ASSERT(serial != RT_NULL); + + /* point to buffer */ + ptr = (rt_uint8_t*) buffer; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + while (size) + { + /* interrupt receive */ + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + if (serial->read_index != serial->save_index) + { + *ptr = serial->rx_buffer[serial->read_index]; + + serial->read_index ++; + if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) + serial->read_index = 0; + } + else + { + /* no data in rx buffer */ + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + ptr ++; + size --; + } + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) + { + /* not support right now */ + RT_ASSERT(0); + } + else + { + /* poll mode */ + while (size) + { + /* Wait for Full Rx Buffer */ + while (!(serial->hw_base->US_CSR & AT91C_US_RXRDY)); + + /* Read Character */ + *ptr = serial->hw_base->US_RHR; + ptr ++; + size --; + } + + return (rt_size_t)ptr - (rt_size_t)buffer; + } + + return 0; } static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - struct rt_at91serial *serial = (struct rt_at91serial*)dev; - RT_ASSERT(serial != RT_NULL); - - ptr = (rt_uint8_t*) buffer; - if (dev->open_flag & RT_DEVICE_OFLAG_WRONLY) - { - if (dev->flag & RT_DEVICE_FLAG_STREAM) - { - /* it's a stream mode device */ - while (size) - { - /* stream mode */ - if (*ptr == '\n') - { - while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); - serial->hw_base->US_THR = '\r'; - } - - /* Wait for Empty Tx Buffer */ - while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); - - /* Transmit Character */ - serial->hw_base->US_THR = *ptr; - ptr ++; - size --; - } - } - else - { - while (size) - { - /* Wait for Empty Tx Buffer */ - while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); - - /* Transmit Character */ - serial->hw_base->US_THR = *ptr; - ptr ++; - size --; - } - } - } - - return (rt_size_t)ptr - (rt_size_t)buffer; + rt_uint8_t* ptr; + struct rt_at91serial *serial = (struct rt_at91serial*)dev; + RT_ASSERT(serial != RT_NULL); + + ptr = (rt_uint8_t*) buffer; + if (dev->open_flag & RT_DEVICE_OFLAG_WRONLY) + { + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* it's a stream mode device */ + while (size) + { + /* stream mode */ + if (*ptr == '\n') + { + while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); + serial->hw_base->US_THR = '\r'; + } + + /* Wait for Empty Tx Buffer */ + while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); + + /* Transmit Character */ + serial->hw_base->US_THR = *ptr; + ptr ++; + size --; + } + } + else + { + while (size) + { + /* Wait for Empty Tx Buffer */ + while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); + + /* Transmit Character */ + serial->hw_base->US_THR = *ptr; + ptr ++; + size --; + } + } + } + + return (rt_size_t)ptr - (rt_size_t)buffer; } static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) { - return RT_EOK; + return RT_EOK; } rt_err_t rt_hw_serial_init() { - rt_device_t device; + rt_device_t device; #ifdef RT_USING_UART1 - device = (rt_device_t) &serial1; - - /* init serial device private data */ - serial1.hw_base = (struct rt_at91serial_hw*)AT91C_BASE_US0; - serial1.peripheral_id = AT91C_ID_US0; - serial1.baudrate = 115200; - - /* set device virtual interface */ - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; - - /* register uart1 on device subsystem */ - rt_device_register(device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); + device = (rt_device_t) &serial1; + + /* init serial device private data */ + serial1.hw_base = (struct rt_at91serial_hw*)AT91C_BASE_US0; + serial1.peripheral_id = AT91C_ID_US0; + serial1.baudrate = 115200; + + /* set device virtual interface */ + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; + + /* register uart1 on device subsystem */ + rt_device_register(device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); #endif #ifdef RT_USING_UART2 - device = (rt_device_t) &serial2; - - serial2.hw_base = (struct rt_at91serial_hw*)AT91C_BASE_US1; - serial2.peripheral_id = AT91C_ID_US1; - serial2.baudrate = 115200; - - /* set device virtual interface */ - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; - - /* register uart2 on device subsystem */ - rt_device_register(device, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); + device = (rt_device_t) &serial2; + + serial2.hw_base = (struct rt_at91serial_hw*)AT91C_BASE_US1; + serial2.peripheral_id = AT91C_ID_US1; + serial2.baudrate = 115200; + + /* set device virtual interface */ + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; + + /* register uart2 on device subsystem */ + rt_device_register(device, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); #endif - return RT_EOK; + return RT_EOK; } /*@}*/ diff --git a/bsp/sam7x/rtconfig.h b/bsp/sam7x/rtconfig.h index bb3e3546d0..222daa14e2 100644 --- a/bsp/sam7x/rtconfig.h +++ b/bsp/sam7x/rtconfig.h @@ -3,16 +3,16 @@ #define __RTTHREAD_CFG_H__ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX*/ -#define RT_THREAD_PRIORITY_MAX 32 +#define RT_THREAD_PRIORITY_MAX 32 /* Tick per Second*/ -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 /* SECTION: RT_DEBUG */ /* Thread Debug*/ @@ -58,12 +58,12 @@ /* Using Device System*/ #define RT_USING_DEVICE #define RT_USING_UART1 -#define RT_UART_RX_BUFFER_SIZE 128 +#define RT_UART_RX_BUFFER_SIZE 128 /* SECTION: Console options */ #define RT_USING_CONSOLE /* the buffer size of console*/ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 /* SECTION: FinSH shell options */ /* Using FinSH as Shell*/ @@ -88,14 +88,14 @@ /* #define RT_LWIP_DEBUG */ /* LwIP tcp thread option */ -#define RT_LWIP_TCPTHREAD_PRIORITY 8 -#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 32 +#define RT_LWIP_TCPTHREAD_PRIORITY 8 +#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 32 /* LwIP eth thread option */ -#define RT_LWIP_ETHTHREAD_PRIORITY 15 -#define RT_LWIP_ETHTHREAD_STACKSIZE 1024 -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define RT_LWIP_ETHTHREAD_PRIORITY 15 +#define RT_LWIP_ETHTHREAD_STACKSIZE 1024 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 /* Enable ICMP protocol*/ #define RT_LWIP_ICMP @@ -110,7 +110,7 @@ #define RT_LWIP_TCP /* the number of simulatenously active TCP connections*/ -#define RT_LWIP_TCP_PCB_NUM 5 +#define RT_LWIP_TCP_PCB_NUM 5 /* Enable SNMP protocol*/ /* #define RT_LWIP_SNMP */ @@ -130,10 +130,10 @@ /* SECTION: DFS options */ //#define RT_USING_DFS /* the max number of mounted filesystem */ -#define DFS_FILESYSTEMS_MAX 1 -/* the max number of opened files */ -#define DFS_FD_MAX 2 -/* the max number of cached sector */ -#define DFS_CACHE_MAX_NUM 4 +#define DFS_FILESYSTEMS_MAX 1 +/* the max number of opened files */ +#define DFS_FD_MAX 2 +/* the max number of cached sector */ +#define DFS_CACHE_MAX_NUM 4 #endif diff --git a/bsp/samd21/rtconfig.h b/bsp/samd21/rtconfig.h index 99fe288e3a..0d9991b743 100644 --- a/bsp/samd21/rtconfig.h +++ b/bsp/samd21/rtconfig.h @@ -3,16 +3,16 @@ #define __RTTHREAD_CFG_H__ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 6 +#define RT_NAME_MAX 6 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 8 +#define RT_THREAD_PRIORITY_MAX 8 /* Tick per Second */ -#define RT_TICK_PER_SECOND 200 +#define RT_TICK_PER_SECOND 200 /* SECTION: RT_DEBUG */ /* Thread Debug */ @@ -24,13 +24,13 @@ /* Using Hook */ #define RT_USING_HOOK -#define IDLE_THREAD_STACK_SIZE 512 +#define IDLE_THREAD_STACK_SIZE 512 /* Using Software Timer */ /* #define RT_USING_TIMER_SOFT */ -#define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 512 -#define RT_TIMER_TICK_PER_SECOND 100 +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_TICK_PER_SECOND 100 /* SECTION: IPC */ /* Using Semaphore*/ @@ -74,9 +74,9 @@ /* SECTION: Console options */ #define RT_USING_CONSOLE /* the buffer size of console*/ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 // -#define RT_CONSOLE_DEVICE_NAME "uart3" +#define RT_CONSOLE_DEVICE_NAME "uart3" // #define RT_USING_SPI @@ -84,8 +84,8 @@ // #define RT_USING_FINSH /* configure finsh parameters */ #define FINSH_THREAD_PRIORITY 6 -#define FINSH_THREAD_STACK_SIZE 512 -#define FINSH_HISTORY_LINES 1 +#define FINSH_THREAD_STACK_SIZE 512 +#define FINSH_HISTORY_LINES 1 /* Using symbol table */ // #define FINSH_USING_SYMTAB // #define FINSH_USING_DESCRIPTION diff --git a/bsp/sep6200/application/application.c b/bsp/sep6200/application/application.c index ea1889d33e..5a032933b4 100644 --- a/bsp/sep6200/application/application.c +++ b/bsp/sep6200/application/application.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes + * Date Author Notes * 2013-7-14 Peng Fan Simple application */ @@ -45,31 +45,31 @@ void rt_test2_thread_entry(void *parameter) int rt_application_init(void) { - rt_thread_t init_thread; - rt_thread_t test1_thread; - rt_thread_t test2_thread; + rt_thread_t init_thread; + rt_thread_t test1_thread; + rt_thread_t test2_thread; - init_thread = rt_thread_create("init", - rt_init_thread_entry, RT_NULL, - RT_INIT_THREAD_STACK_SIZE, 8, 20); + init_thread = rt_thread_create("init", + rt_init_thread_entry, RT_NULL, + RT_INIT_THREAD_STACK_SIZE, 8, 20); - test1_thread = rt_thread_create("test1", - rt_test1_thread_entry, RT_NULL, - 512, 200, 20); - test2_thread = rt_thread_create("test2", - rt_test2_thread_entry, RT_NULL, - 512, 200, 20); + test1_thread = rt_thread_create("test1", + rt_test1_thread_entry, RT_NULL, + 512, 200, 20); + test2_thread = rt_thread_create("test2", + rt_test2_thread_entry, RT_NULL, + 512, 200, 20); - if (init_thread != RT_NULL) - rt_thread_startup(init_thread); + if (init_thread != RT_NULL) + rt_thread_startup(init_thread); - if (test1_thread != RT_NULL) - rt_thread_startup(test1_thread); + if (test1_thread != RT_NULL) + rt_thread_startup(test1_thread); - if (test2_thread != RT_NULL) - rt_thread_startup(test2_thread); + if (test2_thread != RT_NULL) + rt_thread_startup(test2_thread); - return 0; + return 0; } /*@}*/ diff --git a/bsp/sep6200/application/startup.c b/bsp/sep6200/application/startup.c index 8805642d23..4a839d41a6 100644 --- a/bsp/sep6200/application/startup.c +++ b/bsp/sep6200/application/startup.c @@ -40,50 +40,50 @@ extern void sd_init(void); void rtthread_startup() { - /* init hardware interrupt */ - rt_hw_interrupt_init(); + /* init hardware interrupt */ + rt_hw_interrupt_init(); - /* init board */ - rt_hw_board_init(); + /* init board */ + rt_hw_board_init(); - /* show version */ - rt_show_version(); + /* show version */ + rt_show_version(); - /* init tick */ - rt_system_tick_init(); + /* init tick */ + rt_system_tick_init(); - /* init kernel object */ - rt_system_object_init(); + /* init kernel object */ + rt_system_object_init(); - /* init timer system */ - rt_system_timer_init(); + /* init timer system */ + rt_system_timer_init(); - /* init heap memory system */ - rt_system_heap_init(&__bss_end, (void*)0x45000000); + /* init heap memory system */ + rt_system_heap_init(&__bss_end, (void*)0x45000000); - /* init scheduler system */ - rt_system_scheduler_init(); + /* init scheduler system */ + rt_system_scheduler_init(); - /* init application */ - rt_application_init(); + /* init application */ + rt_application_init(); #ifdef RT_USING_FINSH - /* init finsh */ - finsh_system_init(); + /* init finsh */ + finsh_system_init(); #ifdef RT_USING_DEVICE - finsh_set_device("uart0"); + finsh_set_device("uart0"); #endif #endif rt_system_timer_thread_init(); - /* init idle thread */ - rt_thread_idle_init(); + /* init idle thread */ + rt_thread_idle_init(); - /* start scheduler */ - rt_system_scheduler_start(); + /* start scheduler */ + rt_system_scheduler_start(); - /* never reach here */ - return ; + /* never reach here */ + return ; } diff --git a/bsp/sep6200/drivers/board.c b/bsp/sep6200/drivers/board.c index 6b68d0297b..3a1ade2752 100644 --- a/bsp/sep6200/drivers/board.c +++ b/bsp/sep6200/drivers/board.c @@ -22,14 +22,14 @@ void rt_hw_serial_putc(const char c); -#define UART0 ((struct uartport *)SEP6200_UART0_BASE) +#define UART0 ((struct uartport *)SEP6200_UART0_BASE) struct rt_device uart0_device; struct serial_int_rx uart0_int_rx; struct serial_device uart0 = { - UART0, - &uart0_int_rx, + UART0, + &uart0_int_rx, RT_NULL }; @@ -38,13 +38,13 @@ struct serial_device uart0 = */ void rt_timer_handler(int vector, void *param) { - rt_uint32_t clear_int; + rt_uint32_t clear_int; - /* clear timer interrupt */ - if (read_reg(SEP6200_TIMER_T2IMSR) & 0x1) - clear_int = read_reg(SEP6200_TIMER_T2ISCR); + /* clear timer interrupt */ + if (read_reg(SEP6200_TIMER_T2IMSR) & 0x1) + clear_int = read_reg(SEP6200_TIMER_T2ISCR); - rt_tick_increase(); + rt_tick_increase(); } /* @@ -52,47 +52,47 @@ void rt_timer_handler(int vector, void *param) */ void rt_serial_handler(int vector, void *param) { - rt_uint32_t num; - switch (vector) { - case INTSRC_UART0: + rt_uint32_t num; + switch (vector) { + case INTSRC_UART0: /*No interrupt*/ - if ((*(RP)SEP6200_UART0_IIR & 0x1)) - return; + if ((*(RP)SEP6200_UART0_IIR & 0x1)) + return; /*Get the serial interrupt num*/ - num = (*(RP)SEP6200_UART0_IIR >> 1) & 0x7; + num = (*(RP)SEP6200_UART0_IIR >> 1) & 0x7; /*Receive or timeout*/ if ((num == 6) || (num == 2)) - rt_hw_serial_isr(&uart0_device); - break; - /*1,2,3 not implemented now, do in future*/ - case INTSRC_UART1: - break; - case INTSRC_UART2: - break; - case INTSRC_UART3: - break; - } + rt_hw_serial_isr(&uart0_device); + break; + /*1,2,3 not implemented now, do in future*/ + case INTSRC_UART1: + break; + case INTSRC_UART2: + break; + case INTSRC_UART3: + break; + } } /* * This function will init timer2 for system ticks */ -#define BUS4_FREQ 320000000UL -#define TIMER_CLK BUS4_FREQ +#define BUS4_FREQ 320000000UL +#define TIMER_CLK BUS4_FREQ #define HZ 100 void rt_hw_timer_init(void) { - *(RP)SEP6200_TIMER_T2LCR = (TIMER_CLK + HZ / 2) / HZ; - *(RP)SEP6200_TIMER_T2CR = 0x6; + *(RP)SEP6200_TIMER_T2LCR = (TIMER_CLK + HZ / 2) / HZ; + *(RP)SEP6200_TIMER_T2CR = 0x6; - rt_hw_interrupt_install(INTSRC_TIMER1, rt_timer_handler, RT_NULL, "timer"); - rt_hw_interrupt_umask(INTSRC_TIMER1); + rt_hw_interrupt_install(INTSRC_TIMER1, rt_timer_handler, RT_NULL, "timer"); + rt_hw_interrupt_umask(INTSRC_TIMER1); - /* start the timer */ - *(RP)SEP6200_TIMER_T2CR |= 0x1; + /* start the timer */ + *(RP)SEP6200_TIMER_T2CR |= 0x1; } /* @@ -101,35 +101,35 @@ void rt_hw_timer_init(void) #define UART_CLK 60000000UL void rt_hw_uart_init(void) { - const rt_uint32_t uartclk = UART_CLK; + const rt_uint32_t uartclk = UART_CLK; - *(RP)(SEP6200_UART0_LCR) = 0x83; - *(RP)(SEP6200_UART0_DLBH) = (uartclk/16/115200) >> 8; - *(RP)(SEP6200_UART0_DLBL) = (uartclk/16/115200) & 0xff; - *(RP)(SEP6200_UART0_LCR) = 0x83 & (~(0x1 << 7)); + *(RP)(SEP6200_UART0_LCR) = 0x83; + *(RP)(SEP6200_UART0_DLBH) = (uartclk/16/115200) >> 8; + *(RP)(SEP6200_UART0_DLBL) = (uartclk/16/115200) & 0xff; + *(RP)(SEP6200_UART0_LCR) = 0x83 & (~(0x1 << 7)); - *(RP)(SEP6200_UART0_FCR) = 0x0; - *(RP)(SEP6200_UART0_MCR) = 0x0; + *(RP)(SEP6200_UART0_FCR) = 0x0; + *(RP)(SEP6200_UART0_MCR) = 0x0; - *(RP)(SEP6200_UART0_IER) = 0x0; - /* Enable rx interrupt*/ - *(RP)(SEP6200_UART0_IER) |= 0x1; - /* Disable tx interrupt*/ - *(RP)(SEP6200_UART0_IER) &= ~(0x1 << 1); + *(RP)(SEP6200_UART0_IER) = 0x0; + /* Enable rx interrupt*/ + *(RP)(SEP6200_UART0_IER) |= 0x1; + /* Disable tx interrupt*/ + *(RP)(SEP6200_UART0_IER) &= ~(0x1 << 1); - rt_hw_interrupt_install(INTSRC_UART0, rt_serial_handler, RT_NULL, "uart0"); - rt_hw_interrupt_umask(INTSRC_UART0); + rt_hw_interrupt_install(INTSRC_UART0, rt_serial_handler, RT_NULL, "uart0"); + rt_hw_interrupt_umask(INTSRC_UART0); - rt_hw_serial_register(&uart0_device, "uart0", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart0); + rt_hw_serial_register(&uart0_device, "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart0); } void rt_hw_board_init(void) { int i = 0; - rt_hw_uart_init(); - rt_hw_timer_init(); + rt_hw_uart_init(); + rt_hw_timer_init(); } /* @@ -137,12 +137,12 @@ void rt_hw_board_init(void) */ void rt_hw_serial_putc(const char c) { - if (c == '\n') - rt_hw_serial_putc('\r'); + if (c == '\n') + rt_hw_serial_putc('\r'); - while (!((*(RP)SEP6200_UART0_LSR) & 0x40)); + while (!((*(RP)SEP6200_UART0_LSR) & 0x40)); - *(RP)(SEP6200_UART0_TXFIFO) = c; + *(RP)(SEP6200_UART0_TXFIFO) = c; } /** diff --git a/bsp/sep6200/rtconfig.h b/bsp/sep6200/rtconfig.h index c078a6b5a2..84c0ba574b 100644 --- a/bsp/sep6200/rtconfig.h +++ b/bsp/sep6200/rtconfig.h @@ -14,16 +14,16 @@ /* #define RT_DEBUG_IPC 1 */ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 256 +#define RT_THREAD_PRIORITY_MAX 256 /* Tick per Second */ -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 /* SECTION: RT_DEBUG */ /* Thread Debug */ @@ -38,9 +38,9 @@ /* Using Software Timer */ #define RT_USING_TIMER_SOFT -#define RT_TIMER_THREAD_PRIO 8 -#define RT_TIMER_THREAD_STACK_SIZE 512 -#define RT_TIMER_TICK_PER_SECOND 10 +#define RT_TIMER_THREAD_PRIO 8 +#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_TICK_PER_SECOND 10 /* SECTION: IPC */ /* Using Semaphore */ @@ -78,7 +78,7 @@ /* SECTION: Console options */ /* the buffer size of console */ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 /* SECTION: finsh, a C-Express shell */ /* Using FinSH as Shell*/ @@ -105,11 +105,11 @@ /* #define DFS_USING_WORKDIR */ /* the max number of mounted filesystem */ -#define DFS_FILESYSTEMS_MAX 2 -/* the max number of opened files */ -#define DFS_FD_MAX 16 -/* the max number of cached sector */ -#define DFS_CACHE_MAX_NUM 4 +#define DFS_FILESYSTEMS_MAX 2 +/* the max number of opened files */ +#define DFS_FD_MAX 16 +/* the max number of cached sector */ +#define DFS_CACHE_MAX_NUM 4 /* SECTION: lwip, a lighwight TCP/IP protocol stack */ /* Using lighweight TCP/IP protocol stack */ @@ -132,13 +132,13 @@ #define RT_LWIP_TCP /* the number of simulatenously active TCP connections*/ -#define RT_LWIP_TCP_PCB_NUM 5 +#define RT_LWIP_TCP_PCB_NUM 5 /* TCP sender buffer space */ -#define RT_LWIP_TCP_SND_BUF 1024*10 +#define RT_LWIP_TCP_SND_BUF 1024*10 /* TCP receive window. */ -#define RT_LWIP_TCP_WND 1024 +#define RT_LWIP_TCP_WND 1024 /* Enable SNMP protocol */ /* #define RT_LWIP_SNMP */ @@ -147,50 +147,50 @@ /* #define RT_LWIP_DHCP */ /* ip address of target */ -#define RT_LWIP_IPADDR0 192 -#define RT_LWIP_IPADDR1 168 -#define RT_LWIP_IPADDR2 1 -#define RT_LWIP_IPADDR3 30 +#define RT_LWIP_IPADDR0 192 +#define RT_LWIP_IPADDR1 168 +#define RT_LWIP_IPADDR2 1 +#define RT_LWIP_IPADDR3 30 /* gateway address of target */ -#define RT_LWIP_GWADDR0 192 -#define RT_LWIP_GWADDR1 168 -#define RT_LWIP_GWADDR2 1 -#define RT_LWIP_GWADDR3 1 +#define RT_LWIP_GWADDR0 192 +#define RT_LWIP_GWADDR1 168 +#define RT_LWIP_GWADDR2 1 +#define RT_LWIP_GWADDR3 1 /* mask address of target */ -#define RT_LWIP_MSKADDR0 255 -#define RT_LWIP_MSKADDR1 255 -#define RT_LWIP_MSKADDR2 255 -#define RT_LWIP_MSKADDR3 0 +#define RT_LWIP_MSKADDR0 255 +#define RT_LWIP_MSKADDR1 255 +#define RT_LWIP_MSKADDR2 255 +#define RT_LWIP_MSKADDR3 0 /* the number of blocks for pbuf */ -#define RT_LWIP_PBUF_NUM 16 +#define RT_LWIP_PBUF_NUM 16 /* thread priority of tcpip thread */ -#define RT_LWIP_TCPTHREAD_PRIORITY 128 +#define RT_LWIP_TCPTHREAD_PRIORITY 128 /* mail box size of tcpip thread to wait for */ -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 /* thread stack size of tcpip thread */ -#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 +#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 /* thread priority of ethnetif thread */ -#define RT_LWIP_ETHTHREAD_PRIORITY 144 +#define RT_LWIP_ETHTHREAD_PRIORITY 144 /* mail box size of ethnetif thread to wait for */ -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 32 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 32 /* thread stack size of ethnetif thread */ -#define RT_LWIP_ETHTHREAD_STACKSIZE 1024 +#define RT_LWIP_ETHTHREAD_STACKSIZE 1024 /* SECTION: RTGUI support */ /* using RTGUI support */ /* #define RT_USING_RTGUI */ /* name length of RTGUI object */ -#define RTGUI_NAME_MAX 16 +#define RTGUI_NAME_MAX 16 /* support 16 weight font */ #define RTGUI_USING_FONT16 /* support 16 weight font */ diff --git a/bsp/simulator/applications/application.c b/bsp/simulator/applications/application.c index 429c04dd39..5f8ef3204e 100755 --- a/bsp/simulator/applications/application.c +++ b/bsp/simulator/applications/application.c @@ -23,7 +23,7 @@ void rt_init_thread_entry(void *parameter) platform_init(); mnt_init(); - platform_post_init(); + platform_post_init(); #if defined(PKG_USING_GUIENGINE) && defined(GUIENGINE_USING_DEMO) { diff --git a/bsp/simulator/drivers/module_win32.c b/bsp/simulator/drivers/module_win32.c index 6f4461e75b..81a98eca87 100644 --- a/bsp/simulator/drivers/module_win32.c +++ b/bsp/simulator/drivers/module_win32.c @@ -126,7 +126,7 @@ void rt_module_unload_sethook(void (*hook)(rt_module_t module)) */ int rt_system_module_init(void) { - return 0; + return 0; } /** @@ -236,9 +236,9 @@ rt_module_t rt_module_open(const char *path) struct dfs_filesystem *fs; appentry_t fptr; HINSTANCE hinstlib; - rt_module_t module; + rt_module_t module; - char * winpath = RT_NULL; + char * winpath = RT_NULL; char * name = RT_NULL; RT_DEBUG_NOT_IN_INTERRUPT; @@ -349,60 +349,60 @@ FINSH_FUNCTION_EXPORT_ALIAS(rt_module_open, exec, exec module from a file); #define RT_MODULE_ARG_MAX 8 static int _rt_module_split_arg(char* cmd, rt_size_t length, char* argv[]) { - int argc = 0; - char *ptr = cmd; - - while ((ptr - cmd) < length) - { - /* strip bank and tab */ - while ((*ptr == ' ' || *ptr == '\t') && (ptr -cmd)< length) - *ptr++ = '\0'; - /* check whether it's the end of line */ - if ((ptr - cmd)>= length) break; - - /* handle string with quote */ - if (*ptr == '"') - { - argv[argc++] = ++ptr; - - /* skip this string */ - while (*ptr != '"' && (ptr-cmd) < length) - if (*ptr ++ == '\\') ptr ++; - if ((ptr - cmd) >= length) break; - - /* skip '"' */ - *ptr ++ = '\0'; - } - else - { - argv[argc++] = ptr; - while ((*ptr != ' ' && *ptr != '\t') && (ptr - cmd) < length) - ptr ++; - } - - if (argc >= RT_MODULE_ARG_MAX) break; - } - - return argc; + int argc = 0; + char *ptr = cmd; + + while ((ptr - cmd) < length) + { + /* strip bank and tab */ + while ((*ptr == ' ' || *ptr == '\t') && (ptr -cmd)< length) + *ptr++ = '\0'; + /* check whether it's the end of line */ + if ((ptr - cmd)>= length) break; + + /* handle string with quote */ + if (*ptr == '"') + { + argv[argc++] = ++ptr; + + /* skip this string */ + while (*ptr != '"' && (ptr-cmd) < length) + if (*ptr ++ == '\\') ptr ++; + if ((ptr - cmd) >= length) break; + + /* skip '"' */ + *ptr ++ = '\0'; + } + else + { + argv[argc++] = ptr; + while ((*ptr != ' ' && *ptr != '\t') && (ptr - cmd) < length) + ptr ++; + } + + if (argc >= RT_MODULE_ARG_MAX) break; + } + + return argc; } /* module main thread entry */ static void module_main_entry(void* parameter) { - int argc; - char *argv[RT_MODULE_ARG_MAX]; - typedef int (*main_func_t)(int argc, char** argv); + int argc; + char *argv[RT_MODULE_ARG_MAX]; + typedef int (*main_func_t)(int argc, char** argv); - rt_module_t module = (rt_module_t) parameter; - if (module == RT_NULL || module->module_cmd_line == RT_NULL) return; + rt_module_t module = (rt_module_t) parameter; + if (module == RT_NULL || module->module_cmd_line == RT_NULL) return; - rt_memset(argv, 0x00, sizeof(argv)); - argc = _rt_module_split_arg((char*)module->module_cmd_line, module->module_cmd_size, argv); - if (argc == 0) return ; + rt_memset(argv, 0x00, sizeof(argv)); + argc = _rt_module_split_arg((char*)module->module_cmd_line, module->module_cmd_size, argv); + if (argc == 0) return ; - /* do the main function */ - ((main_func_t)module->module_entry)(argc, argv); - return; + /* do the main function */ + ((main_func_t)module->module_entry)(argc, argv); + return; } /** @@ -419,25 +419,25 @@ rt_module_t rt_module_exec_cmd(const char *path, const char* cmd_line, int line_ struct dfs_filesystem *fs; appentry_t fptr; HINSTANCE hinstlib; - rt_module_t module; + rt_module_t module; - char * winpath = RT_NULL; + char * winpath = RT_NULL; char * name = RT_NULL; - char *full_path = RT_NULL; + char *full_path = RT_NULL; RT_DEBUG_NOT_IN_INTERRUPT; /* check parameters */ RT_ASSERT(path != RT_NULL); - if (*path != '/') - { - full_path = dfs_normalize_path(RT_NULL, path); - } - else - { - full_path = (const char*)path; - } + if (*path != '/') + { + full_path = dfs_normalize_path(RT_NULL, path); + } + else + { + full_path = (const char*)path; + } /* app module should only in DFS_WIN32 */ fs = dfs_filesystem_lookup(full_path); @@ -452,14 +452,14 @@ rt_module_t rt_module_exec_cmd(const char *path, const char* cmd_line, int line_ if ((winpath = dfs_win32_dirdup((char *)full_path)) == RT_NULL) { rt_kprintf("out of memory, exit", path); - goto __exit; + goto __exit; } hinstlib = LoadLibrary(winpath); if (hinstlib == NULL) { rt_kprintf("error: unable to open %s\n", winpath); - goto __exit; + goto __exit; } fptr = (appentry_t)GetProcAddress(hinstlib, "main"); @@ -467,21 +467,21 @@ rt_module_t rt_module_exec_cmd(const char *path, const char* cmd_line, int line_ { rt_kprintf("error: unable to find function in %s\n", winpath); FreeLibrary(hinstlib); - goto __exit; + goto __exit; } - /* release winpath */ - rt_free(winpath); + /* release winpath */ + rt_free(winpath); /* get the name of the module */ name = _module_name(path); /* allocate module */ module = (struct rt_module *)rt_object_allocate(RT_Object_Class_Module, name); - if (!module) - { - goto __exit; - } + if (!module) + { + goto __exit; + } module->nref = 0; module->module_entry = fptr; @@ -494,11 +494,11 @@ rt_module_t rt_module_exec_cmd(const char *path, const char* cmd_line, int line_ if (module->module_entry != 0) { - /* set module argument */ - module->module_cmd_line = (rt_uint8_t*)rt_malloc(line_size + 1); - rt_memcpy(module->module_cmd_line, cmd_line, line_size); - module->module_cmd_line[line_size] = '\0'; - module->module_cmd_size = line_size; + /* set module argument */ + module->module_cmd_line = (rt_uint8_t*)rt_malloc(line_size + 1); + rt_memcpy(module->module_cmd_line, cmd_line, line_size); + module->module_cmd_line[line_size] = '\0'; + module->module_cmd_size = line_size; #ifdef RT_USING_SLAB /* init module memory allocator */ @@ -510,10 +510,10 @@ rt_module_t rt_module_exec_cmd(const char *path, const char* cmd_line, int line_ module->page_cnt = 0; #endif - /* create module thread */ - module->module_thread = rt_thread_create(name, - module_main_entry, module, - 2048, RT_THREAD_PRIORITY_MAX - 2, 10); + /* create module thread */ + module->module_thread = rt_thread_create(name, + module_main_entry, module, + 2048, RT_THREAD_PRIORITY_MAX - 2, 10); /* set module id */ module->module_thread->module_id = (void *)module; @@ -539,11 +539,11 @@ rt_module_t rt_module_exec_cmd(const char *path, const char* cmd_line, int line_ return module; __exit: - if (full_path != path) rt_free(full_path); - if (name != RT_NULL) rt_free(full_path); - if (winpath != RT_NULL)rt_free(winpath); + if (full_path != path) rt_free(full_path); + if (name != RT_NULL) rt_free(full_path); + if (winpath != RT_NULL)rt_free(winpath); - return RT_NULL; + return RT_NULL; /* FreeLibrary(hinstlib); */ } diff --git a/bsp/simulator/pcap/pcap_netif.c b/bsp/simulator/pcap/pcap_netif.c index 3d9d76dfcf..0aef477185 100644 --- a/bsp/simulator/pcap/pcap_netif.c +++ b/bsp/simulator/pcap/pcap_netif.c @@ -33,12 +33,12 @@ struct pcap_netif { - /* inherit from ethernet device */ - struct eth_device parent; + /* inherit from ethernet device */ + struct eth_device parent; pcap_t *tap; - /* interface address info. */ - rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ + /* interface address info. */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ }; static struct pcap_netif pcap_netif_device; static struct rt_semaphore sem_lock; @@ -57,7 +57,7 @@ static void pcap_thread_entry(void* parameter) /* Open the adapter */ if ((tap = pcap_open_live(netif->name, - 65536, // portion of the packet to capture. + 65536, // portion of the packet to capture. 1, // promiscuous mode (nonzero means promiscuous) 1, // read timeout, 0 blocked, -1 no timeout errbuf )) == NULL) @@ -84,7 +84,7 @@ static void pcap_thread_entry(void* parameter) p = pbuf_alloc(PBUF_LINK, header->len, PBUF_RAM); pbuf_take(p, pkt_data, header->len); - + /* send to packet mailbox */ rt_mb_send_wait(packet_mb, (rt_uint32_t)p, RT_WAITING_FOREVER); /* notify eth rx thread to receive packet */ @@ -130,7 +130,7 @@ static rt_err_t pcap_netif_init(rt_device_t dev) { rt_kprintf("Select (%s) as network interface\n", d->description); packet_mb = rt_mb_create("pcap", 64, RT_IPC_FLAG_FIFO); - tid = rt_thread_create("pcap", pcap_thread_entry, d, + tid = rt_thread_create("pcap", pcap_thread_entry, d, 2048, RT_THREAD_PRIORITY_MAX - 1, 10); if (tid != RT_NULL) { @@ -147,7 +147,7 @@ static rt_err_t pcap_netif_init(rt_device_t dev) static rt_err_t pcap_netif_open(rt_device_t dev, rt_uint16_t oflag) { - return RT_EOK; + return RT_EOK; } static rt_err_t pcap_netif_close(rt_device_t dev) @@ -157,42 +157,42 @@ static rt_err_t pcap_netif_close(rt_device_t dev) tap = NETIF_PCAP(dev); pcap_close(tap); - return RT_EOK; + return RT_EOK; } static rt_size_t pcap_netif_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_size_t pcap_netif_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_err_t pcap_netif_control(rt_device_t dev, int cmd, void *args) { - switch (cmd) - { - case NIOCTL_GADDR: - /* get mac address */ - if (args) rt_memcpy(args, pcap_netif_device.dev_addr, 6); - else return -RT_ERROR; - break; - - default : - break; - } - - return RT_EOK; + switch (cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if (args) rt_memcpy(args, pcap_netif_device.dev_addr, 6); + else return -RT_ERROR; + break; + + default : + break; + } + + return RT_EOK; } rt_err_t pcap_netif_tx( rt_device_t dev, struct pbuf* p) { - struct pbuf *q; - rt_uint8_t *ptr; + struct pbuf *q; + rt_uint8_t *ptr; rt_uint8_t buf[2048]; rt_err_t result = RT_EOK; pcap_t *tap; @@ -200,18 +200,18 @@ rt_err_t pcap_netif_tx( rt_device_t dev, struct pbuf* p) tap = NETIF_PCAP(dev); - /* lock EMAC device */ - rt_sem_take(&sem_lock, RT_WAITING_FOREVER); + /* lock EMAC device */ + rt_sem_take(&sem_lock, RT_WAITING_FOREVER); - /* copy data to tx buffer */ - q = p; - ptr = (rt_uint8_t*)buf; - while (q) - { - memcpy(ptr, q->payload, q->len); - ptr += q->len; - q = q->next; - } + /* copy data to tx buffer */ + q = p; + ptr = (rt_uint8_t*)buf; + while (q) + { + memcpy(ptr, q->payload, q->len); + ptr += q->len; + q = q->next; + } rt_enter_critical(); res = pcap_sendpacket(tap, buf, p->tot_len); @@ -223,15 +223,15 @@ rt_err_t pcap_netif_tx( rt_device_t dev, struct pbuf* p) result = -RT_ERROR; } - /* unlock EMAC device */ - rt_sem_release(&sem_lock); + /* unlock EMAC device */ + rt_sem_release(&sem_lock); return result; } struct pbuf *pcap_netif_rx(rt_device_t dev) { - struct pbuf* p = RT_NULL; + struct pbuf* p = RT_NULL; rt_mb_recv(packet_mb, (rt_uint32_t*)&p, 0); @@ -240,28 +240,28 @@ struct pbuf *pcap_netif_rx(rt_device_t dev) void pcap_netif_hw_init(void) { - rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO); - - pcap_netif_device.dev_addr[0] = 0x00; - pcap_netif_device.dev_addr[1] = 0x60; - pcap_netif_device.dev_addr[2] = 0x37; - /* set mac address: (only for test) */ - pcap_netif_device.dev_addr[3] = 0x12; - pcap_netif_device.dev_addr[4] = 0x34; - pcap_netif_device.dev_addr[5] = 0x56; - - pcap_netif_device.parent.parent.init = pcap_netif_init; - pcap_netif_device.parent.parent.open = pcap_netif_open; - pcap_netif_device.parent.parent.close = pcap_netif_close; - pcap_netif_device.parent.parent.read = pcap_netif_read; - pcap_netif_device.parent.parent.write = pcap_netif_write; - pcap_netif_device.parent.parent.control = pcap_netif_control; - pcap_netif_device.parent.parent.user_data = RT_NULL; - - pcap_netif_device.parent.eth_rx = pcap_netif_rx; - pcap_netif_device.parent.eth_tx = pcap_netif_tx; - - eth_device_init(&(pcap_netif_device.parent), "e0"); + rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO); + + pcap_netif_device.dev_addr[0] = 0x00; + pcap_netif_device.dev_addr[1] = 0x60; + pcap_netif_device.dev_addr[2] = 0x37; + /* set mac address: (only for test) */ + pcap_netif_device.dev_addr[3] = 0x12; + pcap_netif_device.dev_addr[4] = 0x34; + pcap_netif_device.dev_addr[5] = 0x56; + + pcap_netif_device.parent.parent.init = pcap_netif_init; + pcap_netif_device.parent.parent.open = pcap_netif_open; + pcap_netif_device.parent.parent.close = pcap_netif_close; + pcap_netif_device.parent.parent.read = pcap_netif_read; + pcap_netif_device.parent.parent.write = pcap_netif_write; + pcap_netif_device.parent.parent.control = pcap_netif_control; + pcap_netif_device.parent.parent.user_data = RT_NULL; + + pcap_netif_device.parent.eth_rx = pcap_netif_rx; + pcap_netif_device.parent.eth_tx = pcap_netif_tx; + + eth_device_init(&(pcap_netif_device.parent), "e0"); } #include diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f0/adc_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f0/adc_config.h index 3615ebab52..1c432ca978 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f0/adc_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f0/adc_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f0/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f0/dma_config.h index a8d177801c..077e03896f 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f0/dma_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f0/dma_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -27,7 +27,7 @@ extern "C" { #define UART1_RX_DMA_INSTANCE DMA1_Channel3 #define UART1_RX_DMA_IRQ DMA1_Ch2_3_DMA2_Ch1_2_IRQn #elif defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) -#define SPI1_DMA_RX_TX_IRQHandler DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler +#define SPI1_DMA_RX_TX_IRQHandler DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler #define SPI1_RX_DMA_RCC RCC_AHBENR_DMA1EN #define SPI1_RX_DMA_INSTANCE DMA1_Channel2 #define SPI1_RX_DMA_IRQ DMA1_Ch2_3_DMA2_Ch1_2_IRQn diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f0/pwm_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f0/pwm_config.h index 9ade01dfa5..3a91b88dc9 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f0/pwm_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f0/pwm_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f0/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f0/spi_config.h index 3d66d703e8..79523e704d 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f0/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f0/spi_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -27,7 +27,7 @@ extern "C" { } #endif /* SPI1_BUS_CONFIG */ #endif /* BSP_USING_SPI1 */ - + #ifdef BSP_SPI1_TX_USING_DMA #ifndef SPI1_TX_DMA_CONFIG #define SPI1_TX_DMA_CONFIG \ @@ -59,7 +59,7 @@ extern "C" { } #endif /* SPI2_BUS_CONFIG */ #endif /* BSP_USING_SPI2 */ - + #ifdef BSP_SPI2_TX_USING_DMA #ifndef SPI2_TX_DMA_CONFIG #define SPI2_TX_DMA_CONFIG \ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f0/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f0/tim_config.h index 0bba70cd43..ca37509e02 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f0/tim_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f0/tim_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f0/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f0/uart_config.h index ea5e767aed..649ec1f4ec 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f0/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f0/uart_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -49,7 +49,7 @@ extern "C" { } #endif /* UART2_CONFIG */ #endif /* BSP_USING_UART2 */ - + #if defined(BSP_UART2_RX_USING_DMA) #ifndef UART2_DMA_RX_CONFIG #define UART2_DMA_RX_CONFIG \ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f1/adc_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f1/adc_config.h index ac0a7ca373..825aaf102e 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f1/adc_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f1/adc_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -29,7 +29,7 @@ extern "C" { .Init.DiscontinuousConvMode = DISABLE, \ .Init.NbrOfDiscConversion = 1, \ .Init.ExternalTrigConv = ADC_SOFTWARE_START, \ - } + } #endif /* ADC1_CONFIG */ #endif /* BSP_USING_ADC1 */ @@ -45,7 +45,7 @@ extern "C" { .Init.DiscontinuousConvMode = DISABLE, \ .Init.NbrOfDiscConversion = 1, \ .Init.ExternalTrigConv = ADC_SOFTWARE_START, \ - } + } #endif /* ADC2_CONFIG */ #endif /* BSP_USING_ADC2 */ @@ -61,7 +61,7 @@ extern "C" { .Init.DiscontinuousConvMode = DISABLE, \ .Init.NbrOfDiscConversion = 1, \ .Init.ExternalTrigConv = ADC_SOFTWARE_START, \ - } + } #endif /* ADC3_CONFIG */ #endif /* BSP_USING_ADC3 */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f1/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f1/dma_config.h index 20205c43d7..65e136a2c3 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f1/dma_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f1/dma_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f1/pulse_encoder_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f1/pulse_encoder_config.h index 94dd8fcd70..1de5c72b26 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f1/pulse_encoder_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f1/pulse_encoder_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f1/pwm_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f1/pwm_config.h index 50ea3791b6..c4d4bcf202 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f1/pwm_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f1/pwm_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f1/sdio_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f1/sdio_config.h index b68d5ce6ba..16d3526188 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f1/sdio_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f1/sdio_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f1/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f1/spi_config.h index c4bbe3708d..bf28c2fc72 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f1/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f1/spi_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -27,7 +27,7 @@ extern "C" { } #endif /* SPI1_BUS_CONFIG */ #endif /* BSP_USING_SPI1 */ - + #ifdef BSP_SPI1_TX_USING_DMA #ifndef SPI1_TX_DMA_CONFIG #define SPI1_TX_DMA_CONFIG \ @@ -59,7 +59,7 @@ extern "C" { } #endif /* SPI2_BUS_CONFIG */ #endif /* BSP_USING_SPI2 */ - + #ifdef BSP_SPI2_TX_USING_DMA #ifndef SPI2_TX_DMA_CONFIG #define SPI2_TX_DMA_CONFIG \ @@ -91,7 +91,7 @@ extern "C" { } #endif /* SPI3_BUS_CONFIG */ #endif /* BSP_USING_SPI3 */ - + #ifdef BSP_SPI3_TX_USING_DMA #ifndef SPI3_TX_DMA_CONFIG #define SPI3_TX_DMA_CONFIG \ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f1/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f1/tim_config.h index 1d3b245dc8..07478f1465 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f1/tim_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f1/tim_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f1/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f1/uart_config.h index a08196e996..8605d9089c 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f1/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f1/uart_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f1/usbd_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f1/usbd_config.h index d58b86f6d3..686055a70a 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f1/usbd_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f1/usbd_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f2/adc_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f2/adc_config.h index bda1a06485..711dd21bbd 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f2/adc_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f2/adc_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f2/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f2/dma_config.h index cd2161276f..df88830382 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f2/dma_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f2/dma_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -134,7 +134,7 @@ extern "C" { #endif /* DMA2 stream3 */ -#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) +#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) #define SPI1_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler #define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN #define SPI1_TX_DMA_INSTANCE DMA2_Stream3 diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f2/pwm_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f2/pwm_config.h index 1a5575de0c..b8ef2d37f7 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f2/pwm_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f2/pwm_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f2/sdio_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f2/sdio_config.h index 26fb77e260..c17ef65faf 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f2/sdio_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f2/sdio_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f2/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f2/spi_config.h index cf1e8bcea8..b3e9507b19 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f2/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f2/spi_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -27,7 +27,7 @@ extern "C" { } #endif /* SPI1_BUS_CONFIG */ #endif /* BSP_USING_SPI1 */ - + #ifdef BSP_SPI1_TX_USING_DMA #ifndef SPI1_TX_DMA_CONFIG #define SPI1_TX_DMA_CONFIG \ @@ -61,7 +61,7 @@ extern "C" { } #endif /* SPI2_BUS_CONFIG */ #endif /* BSP_USING_SPI2 */ - + #ifdef BSP_SPI2_TX_USING_DMA #ifndef SPI2_TX_DMA_CONFIG #define SPI2_TX_DMA_CONFIG \ @@ -95,7 +95,7 @@ extern "C" { } #endif /* SPI3_BUS_CONFIG */ #endif /* BSP_USING_SPI3 */ - + #ifdef BSP_SPI3_TX_USING_DMA #ifndef SPI3_TX_DMA_CONFIG #define SPI3_TX_DMA_CONFIG \ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f2/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f2/tim_config.h index a5b47af3a6..4484a20427 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f2/tim_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f2/tim_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f2/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f2/uart_config.h index 6d8655fc2e..118143a82c 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f2/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f2/uart_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -8,7 +8,7 @@ * 2018-10-30 SummerGift first version * 2019-01-03 zylx modify dma support */ - + #ifndef __UART_CONFIG_H__ #define __UART_CONFIG_H__ @@ -27,7 +27,7 @@ extern "C" { .irq_type = USART1_IRQn, \ } #endif /* UART1_CONFIG */ - + #if defined(BSP_UART1_RX_USING_DMA) #ifndef UART1_DMA_RX_CONFIG #define UART1_DMA_RX_CONFIG \ @@ -74,7 +74,7 @@ extern "C" { } #endif /* UART2_DMA_RX_CONFIG */ #endif /* BSP_UART2_RX_USING_DMA */ - + #if defined(BSP_UART2_TX_USING_DMA) #ifndef UART2_DMA_TX_CONFIG #define UART2_DMA_TX_CONFIG \ @@ -109,7 +109,7 @@ extern "C" { } #endif /* UART3_DMA_RX_CONFIG */ #endif /* BSP_UART3_RX_USING_DMA */ - + #if defined(BSP_UART3_TX_USING_DMA) #ifndef UART3_DMA_TX_CONFIG #define UART3_DMA_TX_CONFIG \ @@ -179,7 +179,7 @@ extern "C" { } #endif /* UART5_DMA_RX_CONFIG */ #endif /* BSP_UART5_RX_USING_DMA */ - + #if defined(BSP_UART5_TX_USING_DMA) #ifndef UART5_DMA_TX_CONFIG #define UART5_DMA_TX_CONFIG \ @@ -214,7 +214,7 @@ extern "C" { } #endif /* UART6_DMA_RX_CONFIG */ #endif /* BSP_UART6_RX_USING_DMA */ - + #if defined(BSP_UART6_TX_USING_DMA) #ifndef UART6_DMA_TX_CONFIG #define UART6_DMA_TX_CONFIG \ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/adc_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/adc_config.h index bda1a06485..711dd21bbd 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f4/adc_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/adc_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/dma_config.h index 17768c9a04..80d45afc79 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f4/dma_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/dma_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/pulse_encoder_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/pulse_encoder_config.h index 53320efda1..f9534e0a4c 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f4/pulse_encoder_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/pulse_encoder_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/pwm_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/pwm_config.h index 3803303493..c23abe0aec 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f4/pwm_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/pwm_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/qspi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/qspi_config.h index 8450dc257f..5089a10bdf 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f4/qspi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/qspi_config.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2018-12-22 zylx first version + * 2018-12-22 zylx first version */ #ifndef __QSPI_CONFIG_H__ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/sdio_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/sdio_config.h index a8328b1da4..d26002000c 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f4/sdio_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/sdio_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/spi_config.h index 34b0590eb3..d03b31ce8a 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f4/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/spi_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -27,7 +27,7 @@ extern "C" { } #endif /* SPI1_BUS_CONFIG */ #endif /* BSP_USING_SPI1 */ - + #ifdef BSP_SPI1_TX_USING_DMA #ifndef SPI1_TX_DMA_CONFIG #define SPI1_TX_DMA_CONFIG \ @@ -61,7 +61,7 @@ extern "C" { } #endif /* SPI2_BUS_CONFIG */ #endif /* BSP_USING_SPI2 */ - + #ifdef BSP_SPI2_TX_USING_DMA #ifndef SPI2_TX_DMA_CONFIG #define SPI2_TX_DMA_CONFIG \ @@ -95,7 +95,7 @@ extern "C" { } #endif /* SPI3_BUS_CONFIG */ #endif /* BSP_USING_SPI3 */ - + #ifdef BSP_SPI3_TX_USING_DMA #ifndef SPI3_TX_DMA_CONFIG #define SPI3_TX_DMA_CONFIG \ @@ -129,7 +129,7 @@ extern "C" { } #endif /* SPI4_BUS_CONFIG */ #endif /* BSP_USING_SPI4 */ - + #ifdef BSP_SPI4_TX_USING_DMA #ifndef SPI4_TX_DMA_CONFIG #define SPI4_TX_DMA_CONFIG \ @@ -163,7 +163,7 @@ extern "C" { } #endif /* SPI5_BUS_CONFIG */ #endif /* BSP_USING_SPI5 */ - + #ifdef BSP_SPI5_TX_USING_DMA #ifndef SPI5_TX_DMA_CONFIG #define SPI5_TX_DMA_CONFIG \ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/tim_config.h index bc08f219b9..72e0239ded 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f4/tim_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/tim_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/uart_config.h index e42b5a1a9a..acde141c67 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f4/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/uart_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -8,7 +8,7 @@ * 2018-10-30 SummerGift first version * 2019-01-03 zylx modify dma support */ - + #ifndef __UART_CONFIG_H__ #define __UART_CONFIG_H__ @@ -27,7 +27,7 @@ extern "C" { .irq_type = USART1_IRQn, \ } #endif /* UART1_CONFIG */ - + #if defined(BSP_UART1_RX_USING_DMA) #ifndef UART1_DMA_RX_CONFIG #define UART1_DMA_RX_CONFIG \ @@ -74,7 +74,7 @@ extern "C" { } #endif /* UART2_DMA_RX_CONFIG */ #endif /* BSP_UART2_RX_USING_DMA */ - + #if defined(BSP_UART2_TX_USING_DMA) #ifndef UART2_DMA_TX_CONFIG #define UART2_DMA_TX_CONFIG \ @@ -109,7 +109,7 @@ extern "C" { } #endif /* UART3_DMA_RX_CONFIG */ #endif /* BSP_UART3_RX_USING_DMA */ - + #if defined(BSP_UART3_TX_USING_DMA) #ifndef UART3_DMA_TX_CONFIG #define UART3_DMA_TX_CONFIG \ @@ -179,7 +179,7 @@ extern "C" { } #endif /* UART5_DMA_RX_CONFIG */ #endif /* BSP_UART5_RX_USING_DMA */ - + #if defined(BSP_UART5_TX_USING_DMA) #ifndef UART5_DMA_TX_CONFIG #define UART5_DMA_TX_CONFIG \ @@ -214,7 +214,7 @@ extern "C" { } #endif /* UART6_DMA_RX_CONFIG */ #endif /* BSP_UART6_RX_USING_DMA */ - + #if defined(BSP_UART6_TX_USING_DMA) #ifndef UART6_DMA_TX_CONFIG #define UART6_DMA_TX_CONFIG \ @@ -249,7 +249,7 @@ extern "C" { } #endif /* UART7_DMA_RX_CONFIG */ #endif /* BSP_UART7_RX_USING_DMA */ - + #if defined(BSP_UART7_TX_USING_DMA) #ifndef UART7_DMA_TX_CONFIG #define UART7_DMA_TX_CONFIG \ @@ -284,7 +284,7 @@ extern "C" { } #endif /* UART8_DMA_RX_CONFIG */ #endif /* BSP_UART8_RX_USING_DMA */ - + #if defined(BSP_UART8_TX_USING_DMA) #ifndef UART8_DMA_TX_CONFIG #define UART8_DMA_TX_CONFIG \ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/usbd_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/usbd_config.h index a6fc9a4c4d..31a648ad12 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f4/usbd_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/usbd_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f7/adc_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f7/adc_config.h index bda1a06485..711dd21bbd 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f7/adc_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f7/adc_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f7/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f7/dma_config.h index f716e23765..43a9955e54 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f7/dma_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f7/dma_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f7/pwm_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f7/pwm_config.h index 1a5575de0c..b8ef2d37f7 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f7/pwm_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f7/pwm_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f7/qspi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f7/qspi_config.h index f4477f498b..bee2eb5d82 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f7/qspi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f7/qspi_config.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2018-12-22 zylx first version + * 2018-12-22 zylx first version */ #ifndef __QSPI_CONFIG_H__ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f7/sdio_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f7/sdio_config.h index ae1e4bbf6e..bea45515c3 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f7/sdio_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f7/sdio_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f7/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f7/spi_config.h index ef32a32f4f..26f230d9b1 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f7/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f7/spi_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -26,7 +26,7 @@ extern "C" { } #endif /* SPI1_BUS_CONFIG */ #endif /* BSP_USING_SPI1 */ - + #ifdef BSP_SPI1_TX_USING_DMA #ifndef SPI1_TX_DMA_CONFIG #define SPI1_TX_DMA_CONFIG \ @@ -60,7 +60,7 @@ extern "C" { } #endif /* SPI2_BUS_CONFIG */ #endif /* BSP_USING_SPI2 */ - + #ifdef BSP_SPI2_TX_USING_DMA #ifndef SPI2_TX_DMA_CONFIG #define SPI2_TX_DMA_CONFIG \ @@ -94,7 +94,7 @@ extern "C" { } #endif /* SPI3_BUS_CONFIG */ #endif /* BSP_USING_SPI3 */ - + #ifdef BSP_SPI3_TX_USING_DMA #ifndef SPI3_TX_DMA_CONFIG #define SPI3_TX_DMA_CONFIG \ @@ -128,7 +128,7 @@ extern "C" { } #endif /* SPI4_BUS_CONFIG */ #endif /* BSP_USING_SPI4 */ - + #ifdef BSP_SPI4_TX_USING_DMA #ifndef SPI4_TX_DMA_CONFIG #define SPI4_TX_DMA_CONFIG \ @@ -162,7 +162,7 @@ extern "C" { } #endif /* SPI5_BUS_CONFIG */ #endif /* BSP_USING_SPI5 */ - + #ifdef BSP_SPI5_TX_USING_DMA #ifndef SPI5_TX_DMA_CONFIG #define SPI5_TX_DMA_CONFIG \ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f7/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f7/tim_config.h index cd116d9e19..41ef9f9ee0 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f7/tim_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f7/tim_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f7/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f7/uart_config.h index 6c5b7c840d..7c6f38b697 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f7/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f7/uart_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -8,7 +8,7 @@ * 2018-10-30 SummerGift first version * 2019-01-05 zylx modify dma support */ - + #ifndef __UART_CONFIG_H__ #define __UART_CONFIG_H__ @@ -19,7 +19,7 @@ extern "C" { #endif #if defined(BSP_USING_UART1) -#ifndef UART1_CONFIG +#ifndef UART1_CONFIG #define UART1_CONFIG \ { \ .name = "uart1", \ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g0/adc_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g0/adc_config.h index 739598e7d0..9adaf25fe1 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/g0/adc_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/g0/adc_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g0/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g0/dma_config.h index 39a79dd536..1340f7c4b0 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/g0/dma_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/g0/dma_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g0/pwm_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g0/pwm_config.h index 834903f656..bc9c375b7a 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/g0/pwm_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/g0/pwm_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g0/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g0/spi_config.h index a09ec948a9..a33777977a 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/g0/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/g0/spi_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -27,7 +27,7 @@ extern "C" { } #endif /* SPI1_BUS_CONFIG */ #endif /* BSP_USING_SPI1 */ - + #ifdef BSP_SPI1_TX_USING_DMA #ifndef SPI1_TX_DMA_CONFIG #define SPI1_TX_DMA_CONFIG \ @@ -61,7 +61,7 @@ extern "C" { } #endif /* SPI2_BUS_CONFIG */ #endif /* BSP_USING_SPI2 */ - + #ifdef BSP_SPI2_TX_USING_DMA #ifndef SPI2_TX_DMA_CONFIG #define SPI2_TX_DMA_CONFIG \ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g0/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g0/tim_config.h index 01d3af18f1..ac6e402ac4 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/g0/tim_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/g0/tim_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g0/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g0/uart_config.h index f38baf0b63..3cbb77eefd 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/g0/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/g0/uart_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g4/adc_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g4/adc_config.h index bda1a06485..711dd21bbd 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/g4/adc_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/g4/adc_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g4/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g4/dma_config.h index 46411c5441..419dff4ae7 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/g4/dma_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/g4/dma_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g4/pulse_encoder_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g4/pulse_encoder_config.h index 53320efda1..f9534e0a4c 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/g4/pulse_encoder_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/g4/pulse_encoder_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g4/pwm_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g4/pwm_config.h index 14d4aa2aff..ca382e4742 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/g4/pwm_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/g4/pwm_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g4/qspi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g4/qspi_config.h index 8450dc257f..5089a10bdf 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/g4/qspi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/g4/qspi_config.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2018-12-22 zylx first version + * 2018-12-22 zylx first version */ #ifndef __QSPI_CONFIG_H__ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g4/sdio_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g4/sdio_config.h index 7d6837d74f..a61749ceaa 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/g4/sdio_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/g4/sdio_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g4/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g4/spi_config.h index 34b0590eb3..d03b31ce8a 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/g4/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/g4/spi_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -27,7 +27,7 @@ extern "C" { } #endif /* SPI1_BUS_CONFIG */ #endif /* BSP_USING_SPI1 */ - + #ifdef BSP_SPI1_TX_USING_DMA #ifndef SPI1_TX_DMA_CONFIG #define SPI1_TX_DMA_CONFIG \ @@ -61,7 +61,7 @@ extern "C" { } #endif /* SPI2_BUS_CONFIG */ #endif /* BSP_USING_SPI2 */ - + #ifdef BSP_SPI2_TX_USING_DMA #ifndef SPI2_TX_DMA_CONFIG #define SPI2_TX_DMA_CONFIG \ @@ -95,7 +95,7 @@ extern "C" { } #endif /* SPI3_BUS_CONFIG */ #endif /* BSP_USING_SPI3 */ - + #ifdef BSP_SPI3_TX_USING_DMA #ifndef SPI3_TX_DMA_CONFIG #define SPI3_TX_DMA_CONFIG \ @@ -129,7 +129,7 @@ extern "C" { } #endif /* SPI4_BUS_CONFIG */ #endif /* BSP_USING_SPI4 */ - + #ifdef BSP_SPI4_TX_USING_DMA #ifndef SPI4_TX_DMA_CONFIG #define SPI4_TX_DMA_CONFIG \ @@ -163,7 +163,7 @@ extern "C" { } #endif /* SPI5_BUS_CONFIG */ #endif /* BSP_USING_SPI5 */ - + #ifdef BSP_SPI5_TX_USING_DMA #ifndef SPI5_TX_DMA_CONFIG #define SPI5_TX_DMA_CONFIG \ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g4/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g4/tim_config.h index cd116d9e19..41ef9f9ee0 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/g4/tim_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/g4/tim_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g4/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g4/uart_config.h index 5a77643a55..54a2cc380f 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/g4/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/g4/uart_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -9,7 +9,7 @@ * 2019-01-03 zylx modify dma support * 2019-10-03 xuzhuoyi modify for STM32G4 */ - + #ifndef __UART_CONFIG_H__ #define __UART_CONFIG_H__ @@ -50,7 +50,7 @@ extern "C" { .irq_type = USART1_IRQn, \ } #endif /* UART1_CONFIG */ - + #if defined(BSP_UART1_RX_USING_DMA) #ifndef UART1_DMA_RX_CONFIG #define UART1_DMA_RX_CONFIG \ @@ -97,7 +97,7 @@ extern "C" { } #endif /* UART2_DMA_RX_CONFIG */ #endif /* BSP_UART2_RX_USING_DMA */ - + #if defined(BSP_UART2_TX_USING_DMA) #ifndef UART2_DMA_TX_CONFIG #define UART2_DMA_TX_CONFIG \ @@ -132,7 +132,7 @@ extern "C" { } #endif /* UART3_DMA_RX_CONFIG */ #endif /* BSP_UART3_RX_USING_DMA */ - + #if defined(BSP_UART3_TX_USING_DMA) #ifndef UART3_DMA_TX_CONFIG #define UART3_DMA_TX_CONFIG \ @@ -202,7 +202,7 @@ extern "C" { } #endif /* UART5_DMA_RX_CONFIG */ #endif /* BSP_UART5_RX_USING_DMA */ - + #if defined(BSP_UART5_TX_USING_DMA) #ifndef UART5_DMA_TX_CONFIG #define UART5_DMA_TX_CONFIG \ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g4/usbd_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g4/usbd_config.h index a6fc9a4c4d..31a648ad12 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/g4/usbd_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/g4/usbd_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/h7/adc_config.h b/bsp/stm32/libraries/HAL_Drivers/config/h7/adc_config.h index 0a51a07719..28e31f133a 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/h7/adc_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/h7/adc_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/h7/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/h7/dma_config.h index fd8a3d2371..2164bf74f3 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/h7/dma_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/h7/dma_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/h7/pwm_config.h b/bsp/stm32/libraries/HAL_Drivers/config/h7/pwm_config.h index 1a5575de0c..b8ef2d37f7 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/h7/pwm_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/h7/pwm_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/h7/qspi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/h7/qspi_config.h index f4477f498b..bee2eb5d82 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/h7/qspi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/h7/qspi_config.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2018-12-22 zylx first version + * 2018-12-22 zylx first version */ #ifndef __QSPI_CONFIG_H__ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/h7/sdio_config.h b/bsp/stm32/libraries/HAL_Drivers/config/h7/sdio_config.h index 220a615c47..eee9d103ba 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/h7/sdio_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/h7/sdio_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/h7/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/h7/spi_config.h index ef32a32f4f..26f230d9b1 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/h7/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/h7/spi_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -26,7 +26,7 @@ extern "C" { } #endif /* SPI1_BUS_CONFIG */ #endif /* BSP_USING_SPI1 */ - + #ifdef BSP_SPI1_TX_USING_DMA #ifndef SPI1_TX_DMA_CONFIG #define SPI1_TX_DMA_CONFIG \ @@ -60,7 +60,7 @@ extern "C" { } #endif /* SPI2_BUS_CONFIG */ #endif /* BSP_USING_SPI2 */ - + #ifdef BSP_SPI2_TX_USING_DMA #ifndef SPI2_TX_DMA_CONFIG #define SPI2_TX_DMA_CONFIG \ @@ -94,7 +94,7 @@ extern "C" { } #endif /* SPI3_BUS_CONFIG */ #endif /* BSP_USING_SPI3 */ - + #ifdef BSP_SPI3_TX_USING_DMA #ifndef SPI3_TX_DMA_CONFIG #define SPI3_TX_DMA_CONFIG \ @@ -128,7 +128,7 @@ extern "C" { } #endif /* SPI4_BUS_CONFIG */ #endif /* BSP_USING_SPI4 */ - + #ifdef BSP_SPI4_TX_USING_DMA #ifndef SPI4_TX_DMA_CONFIG #define SPI4_TX_DMA_CONFIG \ @@ -162,7 +162,7 @@ extern "C" { } #endif /* SPI5_BUS_CONFIG */ #endif /* BSP_USING_SPI5 */ - + #ifdef BSP_SPI5_TX_USING_DMA #ifndef SPI5_TX_DMA_CONFIG #define SPI5_TX_DMA_CONFIG \ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/h7/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/config/h7/tim_config.h index cd116d9e19..41ef9f9ee0 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/h7/tim_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/h7/tim_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/h7/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/h7/uart_config.h index f60d2be196..871cddd2db 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/h7/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/h7/uart_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -8,7 +8,7 @@ * 2018-10-30 SummerGift first version * 2019-01-05 zylx modify dma support */ - + #ifndef __UART_CONFIG_H__ #define __UART_CONFIG_H__ @@ -19,7 +19,7 @@ extern "C" { #endif #if defined(BSP_USING_UART1) -#ifndef UART1_CONFIG +#ifndef UART1_CONFIG #define UART1_CONFIG \ { \ .name = "uart1", \ @@ -74,7 +74,7 @@ extern "C" { } #endif /* UART2_DMA_TX_CONFIG */ #endif /* BSP_UART2_TX_USING_DMA */ - + #if defined(BSP_USING_UART3) #ifndef UART3_CONFIG #define UART3_CONFIG \ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/h7/usbd_config.h b/bsp/stm32/libraries/HAL_Drivers/config/h7/usbd_config.h index a6fc9a4c4d..31a648ad12 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/h7/usbd_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/h7/usbd_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l0/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l0/dma_config.h index 803e4706ef..9477886ba5 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/l0/dma_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/l0/dma_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l0/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l0/uart_config.h index ea5e767aed..649ec1f4ec 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/l0/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/l0/uart_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -49,7 +49,7 @@ extern "C" { } #endif /* UART2_CONFIG */ #endif /* BSP_USING_UART2 */ - + #if defined(BSP_UART2_RX_USING_DMA) #ifndef UART2_DMA_RX_CONFIG #define UART2_DMA_RX_CONFIG \ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/adc_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/adc_config.h index 47fe0139b1..cb3ac94524 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/l4/adc_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/adc_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/dma_config.h index c86148bf7d..0762f9048d 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/l4/dma_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/dma_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/pwm_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/pwm_config.h index 50ea3791b6..c4d4bcf202 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/l4/pwm_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/pwm_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/qspi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/qspi_config.h index 4714c119f0..fa8228c6d4 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/l4/qspi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/qspi_config.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2018-12-22 zylx first version + * 2018-12-22 zylx first version */ #ifndef __QSPI_CONFIG_H__ @@ -28,7 +28,7 @@ extern "C" { } #endif /* QSPI_BUS_CONFIG */ #endif /* BSP_USING_QSPI */ - + #ifdef BSP_QSPI_USING_DMA #ifndef QSPI_DMA_CONFIG #define QSPI_DMA_CONFIG \ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/sdio_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/sdio_config.h index 71811dba84..fa066e5cfc 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/l4/sdio_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/sdio_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/spi_config.h index d7518805b3..d510ca379d 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/l4/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/spi_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/tim_config.h index 4df13ca087..b90879c155 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/l4/tim_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/tim_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/uart_config.h index aa71112655..297ab30d56 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/l4/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/uart_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -60,7 +60,7 @@ extern "C" { .dma_irq = UART1_RX_DMA_IRQ, \ } #endif /* UART1_DMA_RX_CONFIG */ -#endif /* BSP_UART1_RX_USING_DMA */ +#endif /* BSP_UART1_RX_USING_DMA */ #if defined(BSP_UART1_TX_USING_DMA) #ifndef UART1_DMA_TX_CONFIG @@ -146,6 +146,6 @@ extern "C" { #ifdef __cplusplus } -#endif +#endif #endif diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/usbd_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/usbd_config.h index a6fc9a4c4d..31a648ad12 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/l4/usbd_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/usbd_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_adc.c b/bsp/stm32/libraries/HAL_Drivers/drv_adc.c index 97ddc4d818..edf704f653 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_adc.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_adc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_can.c b/bsp/stm32/libraries/HAL_Drivers/drv_can.c index c7d0428d48..83d58ec800 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_can.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_can.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -305,8 +305,8 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg) { drv_can->FilterConfig.FilterBank = filter_cfg->items[i].hdr; drv_can->FilterConfig.FilterIdHigh = (filter_cfg->items[i].id >> 13) & 0xFFFF; - drv_can->FilterConfig.FilterIdLow = ((filter_cfg->items[i].id << 3) | - (filter_cfg->items[i].ide << 2) | + drv_can->FilterConfig.FilterIdLow = ((filter_cfg->items[i].id << 3) | + (filter_cfg->items[i].ide << 2) | (filter_cfg->items[i].rtr << 1)) & 0xFFFF; drv_can->FilterConfig.FilterMaskIdHigh = (filter_cfg->items[i].mask >> 16) & 0xFFFF; drv_can->FilterConfig.FilterMaskIdLow = filter_cfg->items[i].mask & 0xFFFF; diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_can.h b/bsp/stm32/libraries/HAL_Drivers/drv_can.h index b0ae3072e6..900793a153 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_can.h +++ b/bsp/stm32/libraries/HAL_Drivers/drv_can.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_common.c b/bsp/stm32/libraries/HAL_Drivers/drv_common.c index 083c1e4c3d..d01fafdda6 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_common.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_common.h b/bsp/stm32/libraries/HAL_Drivers/drv_common.h index bffedddcd0..c45041129d 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_common.h +++ b/bsp/stm32/libraries/HAL_Drivers/drv_common.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_config.h b/bsp/stm32/libraries/HAL_Drivers/drv_config.h index cc1c3f5bde..5be22fc56a 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drv_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-10-30 SummerGift first version */ - + #ifndef __DRV_CONFIG_H__ #define __DRV_CONFIG_H__ @@ -42,7 +42,7 @@ extern "C" { #include "f2/adc_config.h" #include "f2/tim_config.h" #include "f2/sdio_config.h" -#include "f2/pwm_config.h" +#include "f2/pwm_config.h" #elif defined(SOC_SERIES_STM32F4) #include "f4/dma_config.h" #include "f4/uart_config.h" diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_dma.h b/bsp/stm32/libraries/HAL_Drivers/drv_dma.h index 256068d5e1..d22a3b23d7 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_dma.h +++ b/bsp/stm32/libraries/HAL_Drivers/drv_dma.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -19,10 +19,10 @@ extern "C" { #endif #if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L0) \ - || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) + || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) #define DMA_INSTANCE_TYPE DMA_Channel_TypeDef #elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)\ - || defined(SOC_SERIES_STM32H7) + || defined(SOC_SERIES_STM32H7) #define DMA_INSTANCE_TYPE DMA_Stream_TypeDef #endif /* defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_eth.c b/bsp/stm32/libraries/HAL_Drivers/drv_eth.c index 8b191453cb..0506f6495c 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_eth.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_eth.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_eth.h b/bsp/stm32/libraries/HAL_Drivers/drv_eth.h index 07f25b107e..44eb75bbb8 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_eth.h +++ b/bsp/stm32/libraries/HAL_Drivers/drv_eth.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash.h b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash.h index 3a9d5be061..8243e80bbf 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash.h +++ b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f0.c b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f0.c index b8d42c8492..778fbe1a84 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f0.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f0.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f1.c b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f1.c index 81625f0fa1..f17f2867ae 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f1.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f1.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -153,7 +153,7 @@ int stm32_flash_erase_bank(uint32_t bank, rt_uint32_t addr, size_t size) EraseInitStruct.PageAddress = GetPage(addr); EraseInitStruct.NbPages = (size + FLASH_PAGE_SIZE - 1) / FLASH_PAGE_SIZE; EraseInitStruct.Banks = bank; - + if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK) { result = -RT_ERROR; @@ -184,8 +184,8 @@ __exit: */ int stm32_flash_erase(rt_uint32_t addr, size_t size) { -#if defined(FLASH_BANK2_END) - rt_err_t result = RT_EOK; +#if defined(FLASH_BANK2_END) + rt_err_t result = RT_EOK; rt_uint32_t addr_bank1 = 0; rt_uint32_t size_bank1 = 0; rt_uint32_t addr_bank2 = 0; @@ -201,7 +201,7 @@ int stm32_flash_erase(rt_uint32_t addr, size_t size) { size_bank1 = 0; addr_bank2 = addr; - size_bank2 = size; + size_bank2 = size; } else { @@ -220,7 +220,7 @@ int stm32_flash_erase(rt_uint32_t addr, size_t size) goto __exit; } } - + if(size_bank2) { LOG_D("bank2: addr (0x%p), size %d", (void *)addr_bank2, size_bank2); @@ -231,12 +231,12 @@ int stm32_flash_erase(rt_uint32_t addr, size_t size) } } -__exit: +__exit: if(result != RT_EOK) { return result; } - + return size_bank1 + size_bank2; #else return stm32_flash_erase_bank(FLASH_BANK_1, addr, size); diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f2.c b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f2.c index b3ddf1ae6c..d716b46ffe 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f2.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f2.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f4.c b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f4.c index a9ed886c32..c65ecb20f3 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f4.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f4.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f7.c b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f7.c index 276c9ba0b9..522dc8e6a7 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f7.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f7.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -43,7 +43,7 @@ static rt_uint32_t GetSector(rt_uint32_t Address) { uint32_t sector = 0; - + #if defined (FLASH_OPTCR_nDBANK) FLASH_OBProgramInitTypeDef OBInit; uint32_t nbank = 0; @@ -53,7 +53,7 @@ static rt_uint32_t GetSector(rt_uint32_t Address) nbank = ((OBInit.USERConfig & 0x20000000U) >> 29); //1:single bank mode if (1 == nbank) - { + { if ((Address < ADDR_FLASH_SECTOR_1) && (Address >= ADDR_FLASH_SECTOR_0)) { sector = FLASH_SECTOR_0; @@ -98,7 +98,7 @@ static rt_uint32_t GetSector(rt_uint32_t Address) { sector = FLASH_SECTOR_10; } - else + else { sector = FLASH_SECTOR_11; } @@ -153,7 +153,7 @@ static rt_uint32_t GetSector(rt_uint32_t Address) { sector = FLASH_SECTOR_10; } - else + else { sector = FLASH_SECTOR_11; } diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_l4.c b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_l4.c index 00f84711f5..4da4207961 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_l4.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_l4.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_gpio.c b/bsp/stm32/libraries/HAL_Drivers/drv_gpio.c index fb906a242f..dffce87f5f 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_gpio.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_gpio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -71,7 +71,7 @@ static const struct pin_irq_map pin_irq_map[] = {GPIO_PIN_12, EXTI4_15_IRQn}, {GPIO_PIN_13, EXTI4_15_IRQn}, {GPIO_PIN_14, EXTI4_15_IRQn}, - {GPIO_PIN_15, EXTI4_15_IRQn}, + {GPIO_PIN_15, EXTI4_15_IRQn}, #else {GPIO_PIN_0, EXTI0_IRQn}, {GPIO_PIN_1, EXTI1_IRQn}, diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_gpio.h b/bsp/stm32/libraries/HAL_Drivers/drv_gpio.h index 52d4d9a2a9..13b51389bb 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_gpio.h +++ b/bsp/stm32/libraries/HAL_Drivers/drv_gpio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c b/bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c index ce1140eb77..92944510e2 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -173,10 +173,10 @@ static void pclkx_doubler_get(rt_uint32_t *pclk1_doubler, rt_uint32_t *pclk2_dou } if (RCC_ClkInitStruct.APB2_Div != RCC_APB2_DIV1) { - *pclk2_doubler = 2; + *pclk2_doubler = 2; } #else - if (RCC_ClkInitStruct.APB1CLKDivider != RCC_HCLK_DIV1) + if (RCC_ClkInitStruct.APB1CLKDivider != RCC_HCLK_DIV1) { *pclk1_doubler = 2; } @@ -282,7 +282,7 @@ static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_ { tim->Instance->CR1 &= (~TIM_OPMODE_SINGLE); } - + /* start timer */ if (HAL_TIM_Base_Start_IT(tim) != HAL_OK) { diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_lcd.c b/bsp/stm32/libraries/HAL_Drivers/drv_lcd.c index 1eee5b69a0..5d170016b8 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_lcd.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_lcd.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -258,7 +258,7 @@ void turn_on_lcd_backlight(void) #else void turn_on_lcd_backlight(void) { - + } #endif diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_lcd_mipi.c b/bsp/stm32/libraries/HAL_Drivers/drv_lcd_mipi.c index 3928353153..275a18e925 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_lcd_mipi.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_lcd_mipi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2019-05-23 WillianChan first version */ - + #include #ifdef BSP_USING_LCD_MIPI @@ -23,7 +23,7 @@ struct stm32_lcd struct rt_device parent; struct rt_device_graphic_info info; }; -static struct stm32_lcd lcd; +static struct stm32_lcd lcd; extern void stm32_mipi_lcd_init(void); extern void stm32_mipi_lcd_config(rt_uint32_t pixel_format); @@ -32,14 +32,14 @@ extern void stm32_mipi_display_off(void); rt_err_t ltdc_init(void) { - uint32_t lcd_clock = 27429; + uint32_t lcd_clock = 27429; uint32_t lanebyte_clock = 62500; - + uint32_t HSA = LCD_HSYNC, HFP = LCD_HFP, HBP = LCD_HBP, HACT = LCD_WIDTH; uint32_t VSA = LCD_VSYNC, VFP = LCD_VFP, VBP = LCD_VBP, VACT = LCD_HEIGHT; stm32_mipi_lcd_init(); - + __HAL_RCC_LTDC_CLK_ENABLE(); __HAL_RCC_LTDC_FORCE_RESET(); __HAL_RCC_LTDC_RELEASE_RESET(); @@ -47,92 +47,92 @@ rt_err_t ltdc_init(void) __HAL_RCC_DSI_CLK_ENABLE(); __HAL_RCC_DSI_FORCE_RESET(); __HAL_RCC_DSI_RELEASE_RESET(); - + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; - + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC; PeriphClkInitStruct.PLLSAI.PLLSAIN = 384; PeriphClkInitStruct.PLLSAI.PLLSAIR = 7; PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_2; HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); - + HAL_NVIC_SetPriority(LTDC_IRQn, 3, 0); HAL_NVIC_SetPriority(DSI_IRQn, 3, 0); HAL_NVIC_EnableIRQ(LTDC_IRQn); HAL_NVIC_EnableIRQ(DSI_IRQn); - + DSI_PLLInitTypeDef dsi_pll; - - hdsi.Instance = DSI; + + hdsi.Instance = DSI; hdsi.Init.NumberOfLanes = DSI_TWO_DATA_LANES; hdsi.Init.TXEscapeCkdiv = lanebyte_clock / 15620; - + dsi_pll.PLLNDIV = 125; dsi_pll.PLLIDF = DSI_PLL_IN_DIV2; - dsi_pll.PLLODF = DSI_PLL_OUT_DIV1; - + dsi_pll.PLLODF = DSI_PLL_OUT_DIV1; + HAL_DSI_DeInit(&hdsi); - HAL_DSI_Init(&hdsi, &dsi_pll); - + HAL_DSI_Init(&hdsi, &dsi_pll); + hdsi_video.VirtualChannelID = 0; hdsi_video.ColorCoding = DSI_RGB888; hdsi_video.VSPolarity = DSI_VSYNC_ACTIVE_HIGH; hdsi_video.HSPolarity = DSI_HSYNC_ACTIVE_HIGH; hdsi_video.DEPolarity = DSI_DATA_ENABLE_ACTIVE_HIGH; - hdsi_video.Mode = DSI_VID_MODE_BURST; + hdsi_video.Mode = DSI_VID_MODE_BURST; hdsi_video.NullPacketSize = 0xFFF; hdsi_video.NumberOfChunks = 0; - hdsi_video.PacketSize = HACT; + hdsi_video.PacketSize = HACT; hdsi_video.HorizontalSyncActive = (HSA * lanebyte_clock) / lcd_clock; hdsi_video.HorizontalBackPorch = (HBP * lanebyte_clock) / lcd_clock; - hdsi_video.HorizontalLine = ((HACT + HSA + HBP + HFP) * lanebyte_clock) / lcd_clock; + hdsi_video.HorizontalLine = ((HACT + HSA + HBP + HFP) * lanebyte_clock) / lcd_clock; hdsi_video.VerticalSyncActive = VSA; hdsi_video.VerticalBackPorch = VBP; hdsi_video.VerticalFrontPorch = VFP; - hdsi_video.VerticalActive = VACT; - hdsi_video.LPCommandEnable = DSI_LP_COMMAND_ENABLE; + hdsi_video.VerticalActive = VACT; + hdsi_video.LPCommandEnable = DSI_LP_COMMAND_ENABLE; hdsi_video.LPLargestPacketSize = 16; hdsi_video.LPVACTLargestPacketSize = 0; - hdsi_video.LPHorizontalFrontPorchEnable = DSI_LP_HFP_ENABLE; - hdsi_video.LPHorizontalBackPorchEnable = DSI_LP_HBP_ENABLE; - hdsi_video.LPVerticalActiveEnable = DSI_LP_VACT_ENABLE; - hdsi_video.LPVerticalFrontPorchEnable = DSI_LP_VFP_ENABLE; - hdsi_video.LPVerticalBackPorchEnable = DSI_LP_VBP_ENABLE; - hdsi_video.LPVerticalSyncActiveEnable = DSI_LP_VSYNC_ENABLE; - HAL_DSI_ConfigVideoMode(&hdsi, &hdsi_video); - + hdsi_video.LPHorizontalFrontPorchEnable = DSI_LP_HFP_ENABLE; + hdsi_video.LPHorizontalBackPorchEnable = DSI_LP_HBP_ENABLE; + hdsi_video.LPVerticalActiveEnable = DSI_LP_VACT_ENABLE; + hdsi_video.LPVerticalFrontPorchEnable = DSI_LP_VFP_ENABLE; + hdsi_video.LPVerticalBackPorchEnable = DSI_LP_VBP_ENABLE; + hdsi_video.LPVerticalSyncActiveEnable = DSI_LP_VSYNC_ENABLE; + HAL_DSI_ConfigVideoMode(&hdsi, &hdsi_video); + DSI_PHY_TimerTypeDef dsi_phy; - + dsi_phy.ClockLaneHS2LPTime = 35; dsi_phy.ClockLaneLP2HSTime = 35; dsi_phy.DataLaneHS2LPTime = 35; dsi_phy.DataLaneLP2HSTime = 35; dsi_phy.DataLaneMaxReadTime = 0; dsi_phy.StopWaitTime = 10; - HAL_DSI_ConfigPhyTimer(&hdsi, &dsi_phy); - + HAL_DSI_ConfigPhyTimer(&hdsi, &dsi_phy); + hltdc.Instance = LTDC; - + hltdc.Init.PCPolarity = LTDC_PCPOLARITY_IPC; hltdc.Init.HorizontalSync = (HSA - 1); hltdc.Init.AccumulatedHBP = (HSA + HBP - 1); hltdc.Init.AccumulatedActiveW = (LCD_WIDTH + HSA + HBP - 1); hltdc.Init.TotalWidth = (LCD_WIDTH + HSA + HBP + HFP - 1); - + hltdc.LayerCfg->ImageWidth = LCD_WIDTH; - hltdc.LayerCfg->ImageHeight = LCD_HEIGHT; + hltdc.LayerCfg->ImageHeight = LCD_HEIGHT; hltdc.Init.Backcolor.Blue = 0x00; hltdc.Init.Backcolor.Green = 0x00; hltdc.Init.Backcolor.Red = 0x00; - HAL_LTDCEx_StructInitFromVideoConfig(&hltdc, &(hdsi_video)); + HAL_LTDCEx_StructInitFromVideoConfig(&hltdc, &(hdsi_video)); HAL_LTDC_Init(&(hltdc)); - - HAL_DSI_Start(&(hdsi)); + + HAL_DSI_Start(&(hdsi)); stm32_mipi_lcd_config(RTGRAPHIC_PIXEL_FORMAT_ARGB888); - - return RT_EOK; + + return RT_EOK; } void ltdc_layer_init(uint16_t index, uint32_t framebuffer) @@ -140,7 +140,7 @@ void ltdc_layer_init(uint16_t index, uint32_t framebuffer) LTDC_LayerCfgTypeDef layer_cfg; layer_cfg.WindowX0 = 0; - layer_cfg.WindowX1 = LCD_WIDTH; + layer_cfg.WindowX1 = LCD_WIDTH; layer_cfg.WindowY0 = 0; layer_cfg.WindowY1 = LCD_HEIGHT; layer_cfg.PixelFormat = LTDC_PIXEL_FORMAT_ARGB8888; @@ -161,7 +161,7 @@ void ltdc_layer_init(uint16_t index, uint32_t framebuffer) void LTDC_IRQHandler(void) { rt_interrupt_enter(); - HAL_LTDC_IRQHandler(&hltdc); + HAL_LTDC_IRQHandler(&hltdc); rt_interrupt_leave(); } @@ -171,11 +171,11 @@ static rt_err_t stm32_lcd_init(rt_device_t device) lcd.info.height = LCD_HEIGHT; lcd.info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_ARGB888; lcd.info.bits_per_pixel = 32; - lcd.info.framebuffer = (void *)rt_malloc_align(LCD_WIDTH * LCD_HEIGHT * (lcd.info.bits_per_pixel / 8), 32); + lcd.info.framebuffer = (void *)rt_malloc_align(LCD_WIDTH * LCD_HEIGHT * (lcd.info.bits_per_pixel / 8), 32); memset(lcd.info.framebuffer, 0, LCD_WIDTH * LCD_HEIGHT * (lcd.info.bits_per_pixel / 8)); ltdc_init(); - ltdc_layer_init(0, (uint32_t)lcd.info.framebuffer); - + ltdc_layer_init(0, (uint32_t)lcd.info.framebuffer); + return RT_EOK; } @@ -186,12 +186,12 @@ static rt_err_t stm32_lcd_control(rt_device_t device, int cmd, void *args) case RTGRAPHIC_CTRL_RECT_UPDATE: break; - case RTGRAPHIC_CTRL_POWERON: - stm32_mipi_display_on(); + case RTGRAPHIC_CTRL_POWERON: + stm32_mipi_display_on(); break; - case RTGRAPHIC_CTRL_POWEROFF: - stm32_mipi_display_off(); + case RTGRAPHIC_CTRL_POWEROFF: + stm32_mipi_display_off(); break; case RTGRAPHIC_CTRL_GET_INFO: @@ -210,9 +210,9 @@ static rt_err_t stm32_lcd_control(rt_device_t device, int cmd, void *args) int rt_hw_lcd_init(void) { - rt_err_t ret; - - rt_memset(&lcd, 0x00, sizeof(lcd)); + rt_err_t ret; + + rt_memset(&lcd, 0x00, sizeof(lcd)); lcd.parent.type = RT_Device_Class_Graphic; lcd.parent.init = stm32_lcd_init; diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_log.h b/bsp/stm32/libraries/HAL_Drivers/drv_log.h index 7e0bfee5b4..3fe511789b 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_log.h +++ b/bsp/stm32/libraries/HAL_Drivers/drv_log.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_lptim.c b/bsp/stm32/libraries/HAL_Drivers/drv_lptim.c index 25af1fb578..7986a247d0 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_lptim.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_lptim.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_lptim.h b/bsp/stm32/libraries/HAL_Drivers/drv_lptim.h index 0fd51b5eac..b9fa2952ac 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_lptim.h +++ b/bsp/stm32/libraries/HAL_Drivers/drv_lptim.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_pm.c b/bsp/stm32/libraries/HAL_Drivers/drv_pm.c index 8f3890474e..2c3b9276f0 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_pm.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_pulse_encoder.c b/bsp/stm32/libraries/HAL_Drivers/drv_pulse_encoder.c index 55e7bf45e1..d6f85f25eb 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_pulse_encoder.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_pulse_encoder.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_pwm.c b/bsp/stm32/libraries/HAL_Drivers/drv_pwm.c index 95e3711fa8..6173d208f4 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_pwm.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_pwm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -205,7 +205,7 @@ static rt_err_t drv_pwm_get(TIM_HandleTypeDef *htim, struct rt_pwm_configuration tim_clock = HAL_RCC_GetPCLK1Freq() * 2; #endif } - + if (__HAL_TIM_GET_CLOCKDIVISION(htim) == TIM_CLOCKDIVISION_DIV2) { tim_clock = tim_clock / 2; diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_qspi.c b/bsp/stm32/libraries/HAL_Drivers/drv_qspi.c index 52c184290e..24e7f57a34 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_qspi.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_qspi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -104,7 +104,7 @@ static int stm32_qspi_init(struct rt_qspi_device *device, struct rt_qspi_configu { __HAL_RCC_DMA2_CLK_ENABLE(); } - + HAL_DMA_DeInit(qspi_bus->QSPI_Handler.hdma); DMA_HandleTypeDef hdma_quadspi_config = QSPI_DMA_CONFIG; qspi_bus->hdma_quadspi = hdma_quadspi_config; diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_qspi.h b/bsp/stm32/libraries/HAL_Drivers/drv_qspi.h index 5f274d6cc6..fb48dd45b7 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_qspi.h +++ b/bsp/stm32/libraries/HAL_Drivers/drv_qspi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-11-27 zylx first version */ - + #ifndef __DRV_QSPI_H__ #define __DRV_QSPI_H__ diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_rtc.c b/bsp/stm32/libraries/HAL_Drivers/drv_rtc.c index e3689de023..a6a9d2f015 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_rtc.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_rtc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_sdio.c b/bsp/stm32/libraries/HAL_Drivers/drv_sdio.c index 78928105cb..d7241e912b 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_sdio.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_sdio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_sdio.h b/bsp/stm32/libraries/HAL_Drivers/drv_sdio.h index 565a4bed00..920808f9d6 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_sdio.h +++ b/bsp/stm32/libraries/HAL_Drivers/drv_sdio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_sdram.c b/bsp/stm32/libraries/HAL_Drivers/drv_sdram.c index 97731ff3b1..4ae336c3fe 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_sdram.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_sdram.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_soft_i2c.c b/bsp/stm32/libraries/HAL_Drivers/drv_soft_i2c.c index af89ae703a..871686650b 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_soft_i2c.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_soft_i2c.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -207,10 +207,10 @@ int rt_hw_i2c_init(void) result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c2_bus, soft_i2c_config[i].bus_name); RT_ASSERT(result == RT_EOK); stm32_i2c_bus_unlock(&soft_i2c_config[i]); - + LOG_D("software simulation %s init done, pin scl: %d, pin sda %d", - soft_i2c_config[i].bus_name, - soft_i2c_config[i].scl, + soft_i2c_config[i].bus_name, + soft_i2c_config[i].scl, soft_i2c_config[i].sda); } diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_soft_i2c.h b/bsp/stm32/libraries/HAL_Drivers/drv_soft_i2c.h index 31cba68f92..a9683e3e21 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_soft_i2c.h +++ b/bsp/stm32/libraries/HAL_Drivers/drv_soft_i2c.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -37,7 +37,7 @@ struct stm32_i2c .bus_name = "i2c1", \ } #endif - + #ifdef BSP_USING_I2C2 #define I2C2_BUS_CONFIG \ { \ @@ -46,7 +46,7 @@ struct stm32_i2c .bus_name = "i2c2", \ } #endif - + #ifdef BSP_USING_I2C3 #define I2C3_BUS_CONFIG \ { \ @@ -55,7 +55,7 @@ struct stm32_i2c .bus_name = "i2c3", \ } #endif - + #ifdef BSP_USING_I2C4 #define I2C4_BUS_CONFIG \ { \ diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_spi.c b/bsp/stm32/libraries/HAL_Drivers/drv_spi.c index 506eaad8ae..6de9dafd28 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_spi.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_spi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -310,7 +310,7 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message * already_send_length = message->length - send_length - message_length; send_buf = (rt_uint8_t *)message->send_buf + already_send_length; recv_buf = (rt_uint8_t *)message->recv_buf + already_send_length; - + /* start once data exchange in DMA mode */ if (message->send_buf && message->recv_buf) { @@ -885,23 +885,23 @@ static void stm32_get_dma_info(void) } #if defined(SOC_SERIES_STM32F0) -void SPI1_DMA_RX_TX_IRQHandler(void) +void SPI1_DMA_RX_TX_IRQHandler(void) { #if defined(BSP_USING_SPI1) && defined(BSP_SPI1_TX_USING_DMA) SPI1_DMA_TX_IRQHandler(); #endif - + #if defined(BSP_USING_SPI1) && defined(BSP_SPI1_RX_USING_DMA) SPI1_DMA_RX_IRQHandler(); #endif } -void SPI2_DMA_RX_TX_IRQHandler(void) +void SPI2_DMA_RX_TX_IRQHandler(void) { #if defined(BSP_USING_SPI2) && defined(BSP_SPI2_TX_USING_DMA) SPI2_DMA_TX_IRQHandler(); #endif - + #if defined(BSP_USING_SPI2) && defined(BSP_SPI2_RX_USING_DMA) SPI2_DMA_RX_IRQHandler(); #endif diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_spi.h b/bsp/stm32/libraries/HAL_Drivers/drv_spi.h index b4567b8e83..f30d97f777 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_spi.h +++ b/bsp/stm32/libraries/HAL_Drivers/drv_spi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -62,7 +62,7 @@ struct stm32_spi DMA_HandleTypeDef handle_rx; DMA_HandleTypeDef handle_tx; } dma; - + rt_uint8_t spi_dma_flag; struct rt_spi_bus spi_bus; }; diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_usart.c b/bsp/stm32/libraries/HAL_Drivers/drv_usart.c index 2c34eee15f..6a94e64f11 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_usart.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_usart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -205,7 +205,7 @@ static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *ar /* enable interrupt */ case RT_DEVICE_CTRL_SET_INT: /* enable rx irq */ - HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0); + HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0); HAL_NVIC_EnableIRQ(uart->config->irq_type); /* enable interrupt */ __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_RXNE); @@ -273,12 +273,12 @@ static rt_size_t stm32_dma_transmit(struct rt_serial_device *serial, rt_uint8_t RT_ASSERT(serial != RT_NULL); RT_ASSERT(buf != RT_NULL); uart = rt_container_of(serial, struct stm32_uart, serial); - + if (size == 0) { return 0; } - + if (RT_SERIAL_DMA_TX == direction) { if (HAL_UART_Transmit_DMA(&uart->handle, buf, size) == HAL_OK) @@ -867,7 +867,7 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) #if (defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)) && defined(DMAMUX1) /* enable DMAMUX clock for L4+ and G4 */ - __HAL_RCC_DMAMUX1_CLK_ENABLE(); + __HAL_RCC_DMAMUX1_CLK_ENABLE(); #elif defined(SOC_SERIES_STM32MP1) __HAL_RCC_DMAMUX_CLK_ENABLE(); __HAL_RCC_DMA2_CLK_ENABLE(); @@ -1018,7 +1018,7 @@ static void _dma_tx_complete(struct rt_serial_device *serial) /** * @brief HAL_UART_TxCpltCallback * @param huart: UART handle - * @note This callback can be called by two functions, first in UART_EndTransmit_IT when + * @note This callback can be called by two functions, first in UART_EndTransmit_IT when * UART Tx complete and second in UART_DMATransmitCplt function in DMA Circular mode. * @retval None */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_usart.h b/bsp/stm32/libraries/HAL_Drivers/drv_usart.h index f8b0703a33..2f6b37217d 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_usart.h +++ b/bsp/stm32/libraries/HAL_Drivers/drv_usart.h @@ -1,12 +1,12 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2018.10.30 SummerGift first version - * 2019.03.05 whj4674672 add stm32h7 + * 2019.03.05 whj4674672 add stm32h7 */ #ifndef __DRV_USART_H__ @@ -50,7 +50,7 @@ struct stm32_uart { UART_HandleTypeDef handle; struct stm32_uart_config *config; - + #ifdef RT_SERIAL_USING_DMA struct { diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_usbd.c b/bsp/stm32/libraries/HAL_Drivers/drv_usbd.c index 19e8d7f3d4..4f8f08fef3 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_usbd.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_usbd.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_wdt.c b/bsp/stm32/libraries/HAL_Drivers/drv_wdt.c index fe5d20c757..01319fb22b 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_wdt.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_wdt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/templates/stm32f0xx/applications/main.c b/bsp/stm32/libraries/templates/stm32f0xx/applications/main.c index 68a938bbeb..79ae25a186 100644 --- a/bsp/stm32/libraries/templates/stm32f0xx/applications/main.c +++ b/bsp/stm32/libraries/templates/stm32f0xx/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/templates/stm32f0xx/board/board.c b/bsp/stm32/libraries/templates/stm32f0xx/board/board.c index 9115460e72..8a6b2d18f4 100644 --- a/bsp/stm32/libraries/templates/stm32f0xx/board/board.c +++ b/bsp/stm32/libraries/templates/stm32f0xx/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-12-21 zylx first version */ - + #include "board.h" void SystemClock_Config(void) @@ -16,7 +16,7 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -28,7 +28,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1; diff --git a/bsp/stm32/libraries/templates/stm32f0xx/board/board.h b/bsp/stm32/libraries/templates/stm32f0xx/board/board.h index fbc2af5ebe..7559754ae0 100644 --- a/bsp/stm32/libraries/templates/stm32f0xx/board/board.h +++ b/bsp/stm32/libraries/templates/stm32f0xx/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/templates/stm32f10x/applications/main.c b/bsp/stm32/libraries/templates/stm32f10x/applications/main.c index 487ddf44f6..6d19a46edb 100644 --- a/bsp/stm32/libraries/templates/stm32f10x/applications/main.c +++ b/bsp/stm32/libraries/templates/stm32f10x/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/templates/stm32f10x/board/board.c b/bsp/stm32/libraries/templates/stm32f10x/board/board.c index 9f1ba0ddab..8493439409 100644 --- a/bsp/stm32/libraries/templates/stm32f10x/board/board.c +++ b/bsp/stm32/libraries/templates/stm32f10x/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-11-06 SummerGift first version */ - + #include "board.h" void SystemClock_Config(void) @@ -15,7 +15,7 @@ void SystemClock_Config(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -28,7 +28,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/libraries/templates/stm32f10x/board/board.h b/bsp/stm32/libraries/templates/stm32f10x/board/board.h index fc435ee029..1be364929a 100644 --- a/bsp/stm32/libraries/templates/stm32f10x/board/board.h +++ b/bsp/stm32/libraries/templates/stm32f10x/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/templates/stm32f2xx/applications/main.c b/bsp/stm32/libraries/templates/stm32f2xx/applications/main.c index 487ddf44f6..6d19a46edb 100644 --- a/bsp/stm32/libraries/templates/stm32f2xx/applications/main.c +++ b/bsp/stm32/libraries/templates/stm32f2xx/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/templates/stm32f2xx/board/board.c b/bsp/stm32/libraries/templates/stm32f2xx/board/board.c index 91fd907220..00cc73299c 100644 --- a/bsp/stm32/libraries/templates/stm32f2xx/board/board.c +++ b/bsp/stm32/libraries/templates/stm32f2xx/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-11-06 SummerGift first version */ - + #include "board.h" void SystemClock_Config(void) @@ -15,7 +15,7 @@ void SystemClock_Config(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -29,7 +29,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/libraries/templates/stm32f2xx/board/board.h b/bsp/stm32/libraries/templates/stm32f2xx/board/board.h index b93a301f4e..34b46a390c 100644 --- a/bsp/stm32/libraries/templates/stm32f2xx/board/board.h +++ b/bsp/stm32/libraries/templates/stm32f2xx/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/templates/stm32f4xx/applications/main.c b/bsp/stm32/libraries/templates/stm32f4xx/applications/main.c index 487ddf44f6..6d19a46edb 100644 --- a/bsp/stm32/libraries/templates/stm32f4xx/applications/main.c +++ b/bsp/stm32/libraries/templates/stm32f4xx/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/templates/stm32f4xx/board/board.c b/bsp/stm32/libraries/templates/stm32f4xx/board/board.c index ef1f24cbb5..190ca080cf 100644 --- a/bsp/stm32/libraries/templates/stm32f4xx/board/board.c +++ b/bsp/stm32/libraries/templates/stm32f4xx/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,11 +15,11 @@ void SystemClock_Config(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -33,7 +33,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/libraries/templates/stm32f4xx/board/board.h b/bsp/stm32/libraries/templates/stm32f4xx/board/board.h index 514155b823..f68ddcac3f 100644 --- a/bsp/stm32/libraries/templates/stm32f4xx/board/board.h +++ b/bsp/stm32/libraries/templates/stm32f4xx/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/templates/stm32f7xx/applications/main.c b/bsp/stm32/libraries/templates/stm32f7xx/applications/main.c index 5a4bbf9f42..881793e674 100644 --- a/bsp/stm32/libraries/templates/stm32f7xx/applications/main.c +++ b/bsp/stm32/libraries/templates/stm32f7xx/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/templates/stm32f7xx/board/board.c b/bsp/stm32/libraries/templates/stm32f7xx/board/board.c index 4194e6db1e..72d9f50faf 100644 --- a/bsp/stm32/libraries/templates/stm32f7xx/board/board.c +++ b/bsp/stm32/libraries/templates/stm32f7xx/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,11 +16,11 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -34,13 +34,13 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Activate the Over-Drive mode + /**Activate the Over-Drive mode */ if (HAL_PWREx_EnableOverDrive() != HAL_OK) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/libraries/templates/stm32f7xx/board/board.h b/bsp/stm32/libraries/templates/stm32f7xx/board/board.h index 2951235675..7d4c7c4bad 100644 --- a/bsp/stm32/libraries/templates/stm32f7xx/board/board.h +++ b/bsp/stm32/libraries/templates/stm32f7xx/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/templates/stm32h7xx/applications/main.c b/bsp/stm32/libraries/templates/stm32h7xx/applications/main.c index 19a43a12e6..376d3c78ff 100644 --- a/bsp/stm32/libraries/templates/stm32h7xx/applications/main.c +++ b/bsp/stm32/libraries/templates/stm32h7xx/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -18,9 +18,9 @@ int main(void) { int count = 1; - /* set LED0 pin mode to output */ - rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - + /* set LED0 pin mode to output */ + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); + while (count++) { rt_pin_write(LED0_PIN, PIN_HIGH); diff --git a/bsp/stm32/libraries/templates/stm32h7xx/board/board.c b/bsp/stm32/libraries/templates/stm32h7xx/board/board.c index 2e4fab6c8c..6b975ea956 100644 --- a/bsp/stm32/libraries/templates/stm32h7xx/board/board.c +++ b/bsp/stm32/libraries/templates/stm32h7xx/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,18 +16,18 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - /**Supply configuration update enable + /**Supply configuration update enable */ MODIFY_REG(PWR->CR3, PWR_CR3_SCUEN, 0); - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - while ((PWR->D3CR & (PWR_D3CR_VOSRDY)) != PWR_D3CR_VOSRDY) + while ((PWR->D3CR & (PWR_D3CR_VOSRDY)) != PWR_D3CR_VOSRDY) { - + } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -45,7 +45,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 diff --git a/bsp/stm32/libraries/templates/stm32h7xx/board/board.h b/bsp/stm32/libraries/templates/stm32h7xx/board/board.h index 72d84ff29d..32eb25f147 100644 --- a/bsp/stm32/libraries/templates/stm32h7xx/board/board.h +++ b/bsp/stm32/libraries/templates/stm32h7xx/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/templates/stm32l4xx/applications/main.c b/bsp/stm32/libraries/templates/stm32l4xx/applications/main.c index 487ddf44f6..6d19a46edb 100644 --- a/bsp/stm32/libraries/templates/stm32l4xx/applications/main.c +++ b/bsp/stm32/libraries/templates/stm32l4xx/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/libraries/templates/stm32l4xx/board/board.c b/bsp/stm32/libraries/templates/stm32l4xx/board/board.c index 7797c23379..bc32bedd1d 100644 --- a/bsp/stm32/libraries/templates/stm32l4xx/board/board.c +++ b/bsp/stm32/libraries/templates/stm32l4xx/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,7 +16,7 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -31,7 +31,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; @@ -50,7 +50,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) { diff --git a/bsp/stm32/libraries/templates/stm32l4xx/board/board.h b/bsp/stm32/libraries/templates/stm32l4xx/board/board.h index b5120ac476..a8e6ad850f 100644 --- a/bsp/stm32/libraries/templates/stm32l4xx/board/board.h +++ b/bsp/stm32/libraries/templates/stm32l4xx/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f072-st-nucleo/applications/main.c b/bsp/stm32/stm32f072-st-nucleo/applications/main.c index 81b03091e1..486ed61283 100644 --- a/bsp/stm32/stm32f072-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32f072-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f072-st-nucleo/board/board.c b/bsp/stm32/stm32f072-st-nucleo/board/board.c index 8adbcd7bdd..5f06e3253d 100644 --- a/bsp/stm32/stm32f072-st-nucleo/board/board.c +++ b/bsp/stm32/stm32f072-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-12-21 zylx first version */ - + #include "board.h" void SystemClock_Config(void) @@ -16,7 +16,7 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48; RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; @@ -25,7 +25,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1; diff --git a/bsp/stm32/stm32f072-st-nucleo/board/board.h b/bsp/stm32/stm32f072-st-nucleo/board/board.h index bfd0371048..51a9f80edd 100644 --- a/bsp/stm32/stm32f072-st-nucleo/board/board.h +++ b/bsp/stm32/stm32f072-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f091-st-nucleo/applications/main.c b/bsp/stm32/stm32f091-st-nucleo/applications/main.c index 421f897bc4..9783d01e55 100644 --- a/bsp/stm32/stm32f091-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32f091-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f091-st-nucleo/board/board.c b/bsp/stm32/stm32f091-st-nucleo/board/board.c index db5c101a9d..ec74fe9af0 100644 --- a/bsp/stm32/stm32f091-st-nucleo/board/board.c +++ b/bsp/stm32/stm32f091-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-12-21 zylx first version */ - + #include "board.h" void SystemClock_Config(void) @@ -16,11 +16,11 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /**Configure LSE Drive Capability + /**Configure LSE Drive Capability */ HAL_PWR_EnableBkUpAccess(); __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_HIGH); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSI14 |RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_LSE; @@ -38,7 +38,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1; diff --git a/bsp/stm32/stm32f091-st-nucleo/board/board.h b/bsp/stm32/stm32f091-st-nucleo/board/board.h index 7a78136471..a9ba91377d 100644 --- a/bsp/stm32/stm32f091-st-nucleo/board/board.h +++ b/bsp/stm32/stm32f091-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f091-st-nucleo/board/ports/fal_cfg.h b/bsp/stm32/stm32f091-st-nucleo/board/ports/fal_cfg.h index 78bf24d251..b9964e0154 100644 --- a/bsp/stm32/stm32f091-st-nucleo/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32f091-st-nucleo/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-atk-nano/applications/main.c b/bsp/stm32/stm32f103-atk-nano/applications/main.c index 6d75fd13ce..be493624c1 100644 --- a/bsp/stm32/stm32f103-atk-nano/applications/main.c +++ b/bsp/stm32/stm32f103-atk-nano/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-atk-nano/board/board.c b/bsp/stm32/stm32f103-atk-nano/board/board.c index bb35832bfa..de585efe32 100644 --- a/bsp/stm32/stm32f103-atk-nano/board/board.c +++ b/bsp/stm32/stm32f103-atk-nano/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-11-06 balanceTWK first version */ - + #include "board.h" void SystemClock_Config(void) @@ -16,7 +16,7 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE |RCC_OSCILLATORTYPE_LSE; @@ -32,7 +32,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f103-atk-nano/board/board.h b/bsp/stm32/stm32f103-atk-nano/board/board.h index a33ef3cd5e..498459073e 100644 --- a/bsp/stm32/stm32f103-atk-nano/board/board.h +++ b/bsp/stm32/stm32f103-atk-nano/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-atk-nano/board/ports/fal_cfg.h b/bsp/stm32/stm32f103-atk-nano/board/ports/fal_cfg.h index 0ca9acb3ea..3eb4fd7c0d 100644 --- a/bsp/stm32/stm32f103-atk-nano/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32f103-atk-nano/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-atk-nano/board/ports/spi_flash_init.c b/bsp/stm32/stm32f103-atk-nano/board/ports/spi_flash_init.c index 43f726525b..7892489436 100644 --- a/bsp/stm32/stm32f103-atk-nano/board/ports/spi_flash_init.c +++ b/bsp/stm32/stm32f103-atk-nano/board/ports/spi_flash_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-atk-warshipv3/applications/main.c b/bsp/stm32/stm32f103-atk-warshipv3/applications/main.c index ab323bcb8c..df0457fad5 100644 --- a/bsp/stm32/stm32f103-atk-warshipv3/applications/main.c +++ b/bsp/stm32/stm32f103-atk-warshipv3/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-atk-warshipv3/board/board.c b/bsp/stm32/stm32f103-atk-warshipv3/board/board.c index 17bfd29f27..2dc4c9cabf 100644 --- a/bsp/stm32/stm32f103-atk-warshipv3/board/board.c +++ b/bsp/stm32/stm32f103-atk-warshipv3/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-11-06 SummerGift first version */ - + #include "board.h" void SystemClock_Config(void) @@ -15,7 +15,7 @@ void SystemClock_Config(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -28,7 +28,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f103-atk-warshipv3/board/board.h b/bsp/stm32/stm32f103-atk-warshipv3/board/board.h index 68ac34f5f7..80c80984bf 100644 --- a/bsp/stm32/stm32f103-atk-warshipv3/board/board.h +++ b/bsp/stm32/stm32f103-atk-warshipv3/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-dofly-M3S/applications/main.c b/bsp/stm32/stm32f103-dofly-M3S/applications/main.c index 7b7f00c8ee..0ec4930664 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/applications/main.c +++ b/bsp/stm32/stm32f103-dofly-M3S/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-dofly-M3S/applications/nrf24l01_init.c b/bsp/stm32/stm32f103-dofly-M3S/applications/nrf24l01_init.c index 038725b78d..695510d1ac 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/applications/nrf24l01_init.c +++ b/bsp/stm32/stm32f103-dofly-M3S/applications/nrf24l01_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-dofly-M3S/board/board.c b/bsp/stm32/stm32f103-dofly-M3S/board/board.c index 7b6a3ea947..d32a5096b6 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/board/board.c +++ b/bsp/stm32/stm32f103-dofly-M3S/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -8,7 +8,7 @@ * 2018-11-06 SummerGift first version * 2019-04-09 WillianChan add stm32f103-dofly-M3S BSP */ - + #include "board.h" void SystemClock_Config(void) @@ -16,7 +16,7 @@ void SystemClock_Config(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -29,7 +29,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f103-dofly-M3S/board/board.h b/bsp/stm32/stm32f103-dofly-M3S/board/board.h index 62f9030426..8662bff0f5 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/board/board.h +++ b/bsp/stm32/stm32f103-dofly-M3S/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-dofly-M3S/board/ports/drv_sdcard.c b/bsp/stm32/stm32f103-dofly-M3S/board/ports/drv_sdcard.c index 5ffa50ba1d..13d235b694 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/board/ports/drv_sdcard.c +++ b/bsp/stm32/stm32f103-dofly-M3S/board/ports/drv_sdcard.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-dofly-M3S/board/ports/fal_cfg.h b/bsp/stm32/stm32f103-dofly-M3S/board/ports/fal_cfg.h index 5f83366ea0..0f0183422a 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32f103-dofly-M3S/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-dofly-M3S/board/ports/spi_flash_init.c b/bsp/stm32/stm32f103-dofly-M3S/board/ports/spi_flash_init.c index 060c6d59b4..e22efac3c9 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/board/ports/spi_flash_init.c +++ b/bsp/stm32/stm32f103-dofly-M3S/board/ports/spi_flash_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-dofly-lyc8/applications/main.c b/bsp/stm32/stm32f103-dofly-lyc8/applications/main.c index 18dbaac95c..dc4e9cbb7e 100644 --- a/bsp/stm32/stm32f103-dofly-lyc8/applications/main.c +++ b/bsp/stm32/stm32f103-dofly-lyc8/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-dofly-lyc8/board/board.c b/bsp/stm32/stm32f103-dofly-lyc8/board/board.c index 9f1ba0ddab..8493439409 100644 --- a/bsp/stm32/stm32f103-dofly-lyc8/board/board.c +++ b/bsp/stm32/stm32f103-dofly-lyc8/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-11-06 SummerGift first version */ - + #include "board.h" void SystemClock_Config(void) @@ -15,7 +15,7 @@ void SystemClock_Config(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -28,7 +28,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f103-dofly-lyc8/board/board.h b/bsp/stm32/stm32f103-dofly-lyc8/board/board.h index ae6f2c67e8..8d8cc4643a 100644 --- a/bsp/stm32/stm32f103-dofly-lyc8/board/board.h +++ b/bsp/stm32/stm32f103-dofly-lyc8/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-fire-arbitrary/applications/main.c b/bsp/stm32/stm32f103-fire-arbitrary/applications/main.c index 5f0f0db8ed..7ddaa5ee96 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/applications/main.c +++ b/bsp/stm32/stm32f103-fire-arbitrary/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-11-5 SummerGift first version */ - + #include #include #include diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/board.c b/bsp/stm32/stm32f103-fire-arbitrary/board/board.c index 080a22ff49..abbc74be30 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/board.c +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-11-06 balanceTWK first version */ - + #include #include "board.h" @@ -17,7 +17,7 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE |RCC_OSCILLATORTYPE_LSE; @@ -33,7 +33,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/board.h b/bsp/stm32/stm32f103-fire-arbitrary/board/board.h index 968ac8e2e5..7aa3c0f703 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/board.h +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/fal_cfg.h b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/fal_cfg.h index 5f83366ea0..0f0183422a 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/sdcard_port.c b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/sdcard_port.c index bf5f3e10a7..55baa2c263 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/sdcard_port.c +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/sdcard_port.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/spi_flash_init.c b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/spi_flash_init.c index 96b2034f24..519080ae05 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/spi_flash_init.c +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/spi_flash_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/w5500_device.c b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/w5500_device.c index 68348d2bac..378d8f8274 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/w5500_device.c +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/w5500_device.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-gizwits-gokitv21/applications/main.c b/bsp/stm32/stm32f103-gizwits-gokitv21/applications/main.c index 70f60f3f8b..bf9e60aae9 100644 --- a/bsp/stm32/stm32f103-gizwits-gokitv21/applications/main.c +++ b/bsp/stm32/stm32f103-gizwits-gokitv21/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-gizwits-gokitv21/board/board.c b/bsp/stm32/stm32f103-gizwits-gokitv21/board/board.c index 66a0c7f737..55faf0d89f 100644 --- a/bsp/stm32/stm32f103-gizwits-gokitv21/board/board.c +++ b/bsp/stm32/stm32f103-gizwits-gokitv21/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-11-06 SummerGift first version */ - + #include "board.h" /** @@ -19,7 +19,7 @@ void SystemClock_Config(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -32,7 +32,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f103-gizwits-gokitv21/board/board.h b/bsp/stm32/stm32f103-gizwits-gokitv21/board/board.h index 7f0ae67d48..cdb13091cd 100644 --- a/bsp/stm32/stm32f103-gizwits-gokitv21/board/board.h +++ b/bsp/stm32/stm32f103-gizwits-gokitv21/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-hw100k-ibox/applications/main.c b/bsp/stm32/stm32f103-hw100k-ibox/applications/main.c index d0ab2cc6ed..096b4df406 100644 --- a/bsp/stm32/stm32f103-hw100k-ibox/applications/main.c +++ b/bsp/stm32/stm32f103-hw100k-ibox/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-hw100k-ibox/board/board.c b/bsp/stm32/stm32f103-hw100k-ibox/board/board.c index 0598b6af0d..779d731980 100644 --- a/bsp/stm32/stm32f103-hw100k-ibox/board/board.c +++ b/bsp/stm32/stm32f103-hw100k-ibox/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-11-06 SummerGift first version */ - + #include "board.h" void SystemClock_Config(void) @@ -16,7 +16,7 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE |RCC_OSCILLATORTYPE_LSE; @@ -32,7 +32,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f103-hw100k-ibox/board/board.h b/bsp/stm32/stm32f103-hw100k-ibox/board/board.h index fe3ea19e77..239f0afdd6 100644 --- a/bsp/stm32/stm32f103-hw100k-ibox/board/board.h +++ b/bsp/stm32/stm32f103-hw100k-ibox/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-hw100k-ibox/board/ports/esp02_device.c b/bsp/stm32/stm32f103-hw100k-ibox/board/ports/esp02_device.c index 0de060a35a..f18b6318bb 100644 --- a/bsp/stm32/stm32f103-hw100k-ibox/board/ports/esp02_device.c +++ b/bsp/stm32/stm32f103-hw100k-ibox/board/ports/esp02_device.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -21,6 +21,6 @@ int esp_02_device_init() rt_pin_write(ESP8266_CH_PD_Pin,PIN_HIGH) ; rt_pin_write(ESP8266_RST,PIN_HIGH) ; - return RT_EOK ; + return RT_EOK ; } INIT_DEVICE_EXPORT(esp_02_device_init); diff --git a/bsp/stm32/stm32f103-hw100k-ibox/board/ports/fal_cfg.h b/bsp/stm32/stm32f103-hw100k-ibox/board/ports/fal_cfg.h index 5f83366ea0..0f0183422a 100644 --- a/bsp/stm32/stm32f103-hw100k-ibox/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32f103-hw100k-ibox/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-hw100k-ibox/board/ports/on_chip_flash_init.c b/bsp/stm32/stm32f103-hw100k-ibox/board/ports/on_chip_flash_init.c index be8978c63d..ae0660b29a 100644 --- a/bsp/stm32/stm32f103-hw100k-ibox/board/ports/on_chip_flash_init.c +++ b/bsp/stm32/stm32f103-hw100k-ibox/board/ports/on_chip_flash_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-hw100k-ibox/board/ports/w5500_device.c b/bsp/stm32/stm32f103-hw100k-ibox/board/ports/w5500_device.c index a0174bbb0c..59d139a8ac 100644 --- a/bsp/stm32/stm32f103-hw100k-ibox/board/ports/w5500_device.c +++ b/bsp/stm32/stm32f103-hw100k-ibox/board/ports/w5500_device.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-mini-system/applications/main.c b/bsp/stm32/stm32f103-mini-system/applications/main.c index c5fa5a5958..8c68b17b8f 100644 --- a/bsp/stm32/stm32f103-mini-system/applications/main.c +++ b/bsp/stm32/stm32f103-mini-system/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-mini-system/board/board.c b/bsp/stm32/stm32f103-mini-system/board/board.c index b7ca2b8461..0b7edacbd0 100644 --- a/bsp/stm32/stm32f103-mini-system/board/board.c +++ b/bsp/stm32/stm32f103-mini-system/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2019-03-08 obito0 first version */ - + #include "board.h" void SystemClock_Config(void) @@ -15,7 +15,7 @@ void SystemClock_Config(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -28,7 +28,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f103-mini-system/board/board.h b/bsp/stm32/stm32f103-mini-system/board/board.h index 7f0ae67d48..cdb13091cd 100644 --- a/bsp/stm32/stm32f103-mini-system/board/board.h +++ b/bsp/stm32/stm32f103-mini-system/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-yf-ufun/applications/main.c b/bsp/stm32/stm32f103-yf-ufun/applications/main.c index 737c362b23..ffe4955e19 100644 --- a/bsp/stm32/stm32f103-yf-ufun/applications/main.c +++ b/bsp/stm32/stm32f103-yf-ufun/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-yf-ufun/board/board.c b/bsp/stm32/stm32f103-yf-ufun/board/board.c index 4df20fbd48..5271b59c71 100644 --- a/bsp/stm32/stm32f103-yf-ufun/board/board.c +++ b/bsp/stm32/stm32f103-yf-ufun/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-11-06 SummerGift first version */ - + #include "board.h" void SystemClock_Config(void) @@ -15,7 +15,7 @@ void SystemClock_Config(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -28,7 +28,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f103-yf-ufun/board/board.h b/bsp/stm32/stm32f103-yf-ufun/board/board.h index 8c0aa1d769..738f37080a 100644 --- a/bsp/stm32/stm32f103-yf-ufun/board/board.h +++ b/bsp/stm32/stm32f103-yf-ufun/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f107-uc-eval/applications/main.c b/bsp/stm32/stm32f107-uc-eval/applications/main.c index 11587e49d0..9dca242b10 100644 --- a/bsp/stm32/stm32f107-uc-eval/applications/main.c +++ b/bsp/stm32/stm32f107-uc-eval/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f107-uc-eval/board/board.c b/bsp/stm32/stm32f107-uc-eval/board/board.c index a63b070167..f053579c2f 100644 --- a/bsp/stm32/stm32f107-uc-eval/board/board.c +++ b/bsp/stm32/stm32f107-uc-eval/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f107-uc-eval/board/board.h b/bsp/stm32/stm32f107-uc-eval/board/board.h index 98df6d51ff..44a96208c6 100644 --- a/bsp/stm32/stm32f107-uc-eval/board/board.h +++ b/bsp/stm32/stm32f107-uc-eval/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f401-st-nucleo/applications/main.c b/bsp/stm32/stm32f401-st-nucleo/applications/main.c index 86c4508d12..48009f1c78 100644 --- a/bsp/stm32/stm32f401-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32f401-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f401-st-nucleo/board/board.c b/bsp/stm32/stm32f401-st-nucleo/board/board.c index 942d080c5b..9c33cdbba5 100644 --- a/bsp/stm32/stm32f401-st-nucleo/board/board.c +++ b/bsp/stm32/stm32f401-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,11 +15,11 @@ void SystemClock_Config(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - /** Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; @@ -34,7 +34,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f401-st-nucleo/board/board.h b/bsp/stm32/stm32f401-st-nucleo/board/board.h index 4c6f84d170..82647a83a4 100644 --- a/bsp/stm32/stm32f401-st-nucleo/board/board.h +++ b/bsp/stm32/stm32f401-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f405-smdz-breadfruit/applications/main.c b/bsp/stm32/stm32f405-smdz-breadfruit/applications/main.c index 453681a90a..47358c8a61 100644 --- a/bsp/stm32/stm32f405-smdz-breadfruit/applications/main.c +++ b/bsp/stm32/stm32f405-smdz-breadfruit/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f405-smdz-breadfruit/board/board.c b/bsp/stm32/stm32f405-smdz-breadfruit/board/board.c index ef1f24cbb5..190ca080cf 100644 --- a/bsp/stm32/stm32f405-smdz-breadfruit/board/board.c +++ b/bsp/stm32/stm32f405-smdz-breadfruit/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,11 +15,11 @@ void SystemClock_Config(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -33,7 +33,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f405-smdz-breadfruit/board/board.h b/bsp/stm32/stm32f405-smdz-breadfruit/board/board.h index 5b30f605d9..844f5e35e6 100644 --- a/bsp/stm32/stm32f405-smdz-breadfruit/board/board.h +++ b/bsp/stm32/stm32f405-smdz-breadfruit/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f407-atk-explorer/applications/main.c b/bsp/stm32/stm32f407-atk-explorer/applications/main.c index e3ae33205f..2fc9307caf 100644 --- a/bsp/stm32/stm32f407-atk-explorer/applications/main.c +++ b/bsp/stm32/stm32f407-atk-explorer/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f407-atk-explorer/board/board.c b/bsp/stm32/stm32f407-atk-explorer/board/board.c index c2c90a5e86..02a3a3d53f 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/board.c +++ b/bsp/stm32/stm32f407-atk-explorer/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,11 +16,11 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE |RCC_OSCILLATORTYPE_LSE; @@ -37,7 +37,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f407-atk-explorer/board/board.h b/bsp/stm32/stm32f407-atk-explorer/board/board.h index 70a4c0ed19..6d80e38f78 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/board.h +++ b/bsp/stm32/stm32f407-atk-explorer/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f407-atk-explorer/board/ports/fal_cfg.h b/bsp/stm32/stm32f407-atk-explorer/board/ports/fal_cfg.h index a587e207ce..995136cd54 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32f407-atk-explorer/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f407-atk-explorer/board/ports/phy_reset.c b/bsp/stm32/stm32f407-atk-explorer/board/ports/phy_reset.c index 838216ffaa..ec5c61f1b0 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/ports/phy_reset.c +++ b/bsp/stm32/stm32f407-atk-explorer/board/ports/phy_reset.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f407-atk-explorer/board/ports/sdcard_port.c b/bsp/stm32/stm32f407-atk-explorer/board/ports/sdcard_port.c index 0a9c36fd42..bc7e8b676e 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/ports/sdcard_port.c +++ b/bsp/stm32/stm32f407-atk-explorer/board/ports/sdcard_port.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f407-atk-explorer/board/ports/spi_flash_init.c b/bsp/stm32/stm32f407-atk-explorer/board/ports/spi_flash_init.c index 4705cc0112..b92344fa43 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/ports/spi_flash_init.c +++ b/bsp/stm32/stm32f407-atk-explorer/board/ports/spi_flash_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f407-st-discovery/applications/main.c b/bsp/stm32/stm32f407-st-discovery/applications/main.c index c7ffc240cb..2651a75073 100644 --- a/bsp/stm32/stm32f407-st-discovery/applications/main.c +++ b/bsp/stm32/stm32f407-st-discovery/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f407-st-discovery/board/board.c b/bsp/stm32/stm32f407-st-discovery/board/board.c index 8a3dbd9937..5fff5426fe 100644 --- a/bsp/stm32/stm32f407-st-discovery/board/board.c +++ b/bsp/stm32/stm32f407-st-discovery/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,11 +15,11 @@ void SystemClock_Config(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -33,7 +33,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f407-st-discovery/board/board.h b/bsp/stm32/stm32f407-st-discovery/board/board.h index 7ba6c79dee..539e3abf45 100644 --- a/bsp/stm32/stm32f407-st-discovery/board/board.h +++ b/bsp/stm32/stm32f407-st-discovery/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f411-st-nucleo/applications/main.c b/bsp/stm32/stm32f411-st-nucleo/applications/main.c index b29630d930..0e109663ae 100644 --- a/bsp/stm32/stm32f411-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32f411-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f411-st-nucleo/board/board.c b/bsp/stm32/stm32f411-st-nucleo/board/board.c index e9e6ffb5e7..1d83386719 100644 --- a/bsp/stm32/stm32f411-st-nucleo/board/board.c +++ b/bsp/stm32/stm32f411-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,11 +16,11 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; @@ -35,7 +35,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f411-st-nucleo/board/board.h b/bsp/stm32/stm32f411-st-nucleo/board/board.h index e05c785128..062038ffdb 100644 --- a/bsp/stm32/stm32f411-st-nucleo/board/board.h +++ b/bsp/stm32/stm32f411-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f412-st-nucleo/applications/main.c b/bsp/stm32/stm32f412-st-nucleo/applications/main.c index 317bc60514..2cf35c5bc6 100644 --- a/bsp/stm32/stm32f412-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32f412-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f412-st-nucleo/board/board.c b/bsp/stm32/stm32f412-st-nucleo/board/board.c index 504407b161..b8f8168dfa 100644 --- a/bsp/stm32/stm32f412-st-nucleo/board/board.c +++ b/bsp/stm32/stm32f412-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,11 +16,11 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; @@ -35,7 +35,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f412-st-nucleo/board/board.h b/bsp/stm32/stm32f412-st-nucleo/board/board.h index 3e2d7384c8..5c463d04e8 100644 --- a/bsp/stm32/stm32f412-st-nucleo/board/board.h +++ b/bsp/stm32/stm32f412-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f427-robomaster-a/applications/main.c b/bsp/stm32/stm32f427-robomaster-a/applications/main.c index 7c21823832..6cef3cbb34 100644 --- a/bsp/stm32/stm32f427-robomaster-a/applications/main.c +++ b/bsp/stm32/stm32f427-robomaster-a/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f427-robomaster-a/board/board.c b/bsp/stm32/stm32f427-robomaster-a/board/board.c index a0901feba9..780e089fcd 100644 --- a/bsp/stm32/stm32f427-robomaster-a/board/board.c +++ b/bsp/stm32/stm32f427-robomaster-a/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -19,11 +19,11 @@ void SystemClock_Config(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - /** Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -37,13 +37,13 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Activate the Over-Drive mode + /** Activate the Over-Drive mode */ if (HAL_PWREx_EnableOverDrive() != HAL_OK) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f427-robomaster-a/board/board.h b/bsp/stm32/stm32f427-robomaster-a/board/board.h index 57c8e4a954..72cb49ec3a 100644 --- a/bsp/stm32/stm32f427-robomaster-a/board/board.h +++ b/bsp/stm32/stm32f427-robomaster-a/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f427-robomaster-a/board/ports/sdcard_port.c b/bsp/stm32/stm32f427-robomaster-a/board/ports/sdcard_port.c index b46537d311..6a79c83523 100644 --- a/bsp/stm32/stm32f427-robomaster-a/board/ports/sdcard_port.c +++ b/bsp/stm32/stm32f427-robomaster-a/board/ports/sdcard_port.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-armfly-v6/applications/main.c b/bsp/stm32/stm32f429-armfly-v6/applications/main.c index 70c2a3b0f7..21b7c14ec0 100644 --- a/bsp/stm32/stm32f429-armfly-v6/applications/main.c +++ b/bsp/stm32/stm32f429-armfly-v6/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -18,10 +18,10 @@ int main(void) int count = 1; HC574_SetPin(LED1,0); - HC574_SetPin(LED2,0); + HC574_SetPin(LED2,0); HC574_SetPin(LED3,0); HC574_SetPin(LED4,0); - + while (count++) { HC574_SetPin(LED1,1); @@ -29,6 +29,6 @@ int main(void) HC574_SetPin(LED1,0); rt_thread_mdelay(500); } - + return RT_EOK; } diff --git a/bsp/stm32/stm32f429-armfly-v6/board/board.c b/bsp/stm32/stm32f429-armfly-v6/board/board.c index f314b7c45a..2d37e631e3 100644 --- a/bsp/stm32/stm32f429-armfly-v6/board/board.c +++ b/bsp/stm32/stm32f429-armfly-v6/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,12 +17,12 @@ void SystemClock_Config(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - - /**Configure the main internal regulator output voltage + + /**Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE |RCC_OSCILLATORTYPE_LSE; @@ -39,13 +39,13 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Activate the Over-Drive mode + /**Activate the Over-Drive mode */ if (HAL_PWREx_EnableOverDrive() != HAL_OK) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; @@ -53,7 +53,7 @@ void SystemClock_Config(void) RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { Error_Handler(); diff --git a/bsp/stm32/stm32f429-armfly-v6/board/board.h b/bsp/stm32/stm32f429-armfly-v6/board/board.h index f0ea803bb0..c0d30df246 100644 --- a/bsp/stm32/stm32f429-armfly-v6/board/board.h +++ b/bsp/stm32/stm32f429-armfly-v6/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-armfly-v6/board/ports/drv_ext_io.h b/bsp/stm32/stm32f429-armfly-v6/board/ports/drv_ext_io.h index 09740d3571..3f336dd7ab 100644 --- a/bsp/stm32/stm32f429-armfly-v6/board/ports/drv_ext_io.h +++ b/bsp/stm32/stm32f429-armfly-v6/board/ports/drv_ext_io.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,64 +13,64 @@ #include "rtthread.h" /* - armfly STM32-V6 Development board Extend IO - D0 - GPRS_RERM_ON - D1 - GPRS_RESET - D2 - NRF24L01_CE - D3 - NRF905_TX_EN - D4 - NRF905_TRX_CE/VS1053_XDCS - D5 - NRF905_PWR_UP - D6 - ESP8266_G0 - D7 - ESP8266_G2 - - D8 - LED1 - D9 - LED2 - D10 - LED3 - D11 - LED4 - D12 - TP_NRST - D13 - AD7606_OS0 - D14 - AD7606_OS1 - D15 - AD7606_OS2 - - GPIO can output 5V - D16 - Y50_0 - D17 - Y50_1 - D18 - Y50_2 - D19 - Y50_3 - D20 - Y50_4 - D21 - Y50_5 - D22 - Y50_6 - D23 - Y50_7 + armfly STM32-V6 Development board Extend IO + D0 - GPRS_RERM_ON + D1 - GPRS_RESET + D2 - NRF24L01_CE + D3 - NRF905_TX_EN + D4 - NRF905_TRX_CE/VS1053_XDCS + D5 - NRF905_PWR_UP + D6 - ESP8266_G0 + D7 - ESP8266_G2 - GPIO can output 3.3V - D24 - AD7606_RESET - D25 - AD7606_RAGE - D26 - Y33_2 - D27 - Y33_3 - D28 - Y33_4 - D29 - Y33_5 - D30 - Y33_6 - D31 - Y33_7 + D8 - LED1 + D9 - LED2 + D10 - LED3 + D11 - LED4 + D12 - TP_NRST + D13 - AD7606_OS0 + D14 - AD7606_OS1 + D15 - AD7606_OS2 + + GPIO can output 5V + D16 - Y50_0 + D17 - Y50_1 + D18 - Y50_2 + D19 - Y50_3 + D20 - Y50_4 + D21 - Y50_5 + D22 - Y50_6 + D23 - Y50_7 + + GPIO can output 3.3V + D24 - AD7606_RESET + D25 - AD7606_RAGE + D26 - Y33_2 + D27 - Y33_3 + D28 - Y33_4 + D29 - Y33_5 + D30 - Y33_6 + D31 - Y33_7 */ #ifndef GPIO_Pin_0 - #define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ - #define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ - #define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ - #define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ - #define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ - #define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ - #define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ - #define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ - #define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ - #define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ - #define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ - #define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ - #define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ - #define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ - #define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ - #define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ -#endif + #define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ + #define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ + #define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ + #define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ + #define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ + #define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ + #define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ + #define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ + #define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ + #define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ + #define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ + #define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ + #define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ + #define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ + #define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ + #define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#endif #define GPIO_Pin_16 ((uint32_t)0x00010000) /* Pin 0 selected */ #define GPIO_Pin_17 ((uint32_t)0x00020000) /* Pin 1 selected */ @@ -90,42 +90,42 @@ #define GPIO_Pin_31 ((uint32_t)0x80000000) /* Pin 15 selected */ /* Rename the macro for the sake of memory */ -#define GPRS_TERM_ON GPIO_Pin_0 -#define GPRS_RESET GPIO_Pin_1 -#define NRF24L01_CE GPIO_Pin_2 -#define NRF905_TX_EN GPIO_Pin_3 -#define NRF905_TRX_CE GPIO_Pin_4 +#define GPRS_TERM_ON GPIO_Pin_0 +#define GPRS_RESET GPIO_Pin_1 +#define NRF24L01_CE GPIO_Pin_2 +#define NRF905_TX_EN GPIO_Pin_3 +#define NRF905_TRX_CE GPIO_Pin_4 #define VS1053_XDCS GPIO_Pin_4 -#define NRF905_PWR_UP GPIO_Pin_5 -#define ESP8266_G0 GPIO_Pin_6 -#define ESP8266_G2 GPIO_Pin_7 - -#define LED1 GPIO_Pin_8 -#define LED2 GPIO_Pin_9 -#define LED3 GPIO_Pin_10 -#define LED4 GPIO_Pin_11 -#define TP_NRST GPIO_Pin_12 -#define AD7606_OS0 GPIO_Pin_13 -#define AD7606_OS1 GPIO_Pin_14 -#define AD7606_OS2 GPIO_Pin_15 - -#define Y50_0 GPIO_Pin_16 -#define Y50_1 GPIO_Pin_17 -#define Y50_2 GPIO_Pin_18 -#define Y50_3 GPIO_Pin_19 -#define Y50_4 GPIO_Pin_20 -#define Y50_5 GPIO_Pin_21 -#define Y50_6 GPIO_Pin_22 -#define Y50_7 GPIO_Pin_23 +#define NRF905_PWR_UP GPIO_Pin_5 +#define ESP8266_G0 GPIO_Pin_6 +#define ESP8266_G2 GPIO_Pin_7 + +#define LED1 GPIO_Pin_8 +#define LED2 GPIO_Pin_9 +#define LED3 GPIO_Pin_10 +#define LED4 GPIO_Pin_11 +#define TP_NRST GPIO_Pin_12 +#define AD7606_OS0 GPIO_Pin_13 +#define AD7606_OS1 GPIO_Pin_14 +#define AD7606_OS2 GPIO_Pin_15 + +#define Y50_0 GPIO_Pin_16 +#define Y50_1 GPIO_Pin_17 +#define Y50_2 GPIO_Pin_18 +#define Y50_3 GPIO_Pin_19 +#define Y50_4 GPIO_Pin_20 +#define Y50_5 GPIO_Pin_21 +#define Y50_6 GPIO_Pin_22 +#define Y50_7 GPIO_Pin_23 -#define AD7606_RESET GPIO_Pin_24 -#define AD7606_RANGE GPIO_Pin_25 -#define Y33_2 GPIO_Pin_26 -#define Y33_3 GPIO_Pin_27 -#define Y33_4 GPIO_Pin_28 -#define Y33_5 GPIO_Pin_29 -#define Y33_6 GPIO_Pin_30 -#define Y33_7 GPIO_Pin_31 +#define AD7606_RESET GPIO_Pin_24 +#define AD7606_RANGE GPIO_Pin_25 +#define Y33_2 GPIO_Pin_26 +#define Y33_3 GPIO_Pin_27 +#define Y33_4 GPIO_Pin_28 +#define Y33_5 GPIO_Pin_29 +#define Y33_6 GPIO_Pin_30 +#define Y33_7 GPIO_Pin_31 void HC574_SetPin(rt_uint32_t _pin, uint8_t _value); rt_uint8_t HC574_GetPin(rt_uint32_t _pin); diff --git a/bsp/stm32/stm32f429-armfly-v6/board/ports/fal_cfg.h b/bsp/stm32/stm32f429-armfly-v6/board/ports/fal_cfg.h index a587e207ce..995136cd54 100644 --- a/bsp/stm32/stm32f429-armfly-v6/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32f429-armfly-v6/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-armfly-v6/board/ports/lcd_port.h b/bsp/stm32/stm32f429-armfly-v6/board/ports/lcd_port.h index 31e2b9a392..0fda729291 100644 --- a/bsp/stm32/stm32f429-armfly-v6/board/ports/lcd_port.h +++ b/bsp/stm32/stm32f429-armfly-v6/board/ports/lcd_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-armfly-v6/board/ports/phy_reset.c b/bsp/stm32/stm32f429-armfly-v6/board/ports/phy_reset.c index 36296b486a..6d97b5a979 100644 --- a/bsp/stm32/stm32f429-armfly-v6/board/ports/phy_reset.c +++ b/bsp/stm32/stm32f429-armfly-v6/board/ports/phy_reset.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-armfly-v6/board/ports/sdcard_port.c b/bsp/stm32/stm32f429-armfly-v6/board/ports/sdcard_port.c index b46537d311..6a79c83523 100644 --- a/bsp/stm32/stm32f429-armfly-v6/board/ports/sdcard_port.c +++ b/bsp/stm32/stm32f429-armfly-v6/board/ports/sdcard_port.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-armfly-v6/board/ports/sdram_port.h b/bsp/stm32/stm32f429-armfly-v6/board/ports/sdram_port.h index 1e57acb19f..9b5a363b6f 100644 --- a/bsp/stm32/stm32f429-armfly-v6/board/ports/sdram_port.h +++ b/bsp/stm32/stm32f429-armfly-v6/board/ports/sdram_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-armfly-v6/board/ports/spi_flash_init.c b/bsp/stm32/stm32f429-armfly-v6/board/ports/spi_flash_init.c index 526835b59a..21ac8bf319 100644 --- a/bsp/stm32/stm32f429-armfly-v6/board/ports/spi_flash_init.c +++ b/bsp/stm32/stm32f429-armfly-v6/board/ports/spi_flash_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-atk-apollo/applications/main.c b/bsp/stm32/stm32f429-atk-apollo/applications/main.c index 487ddf44f6..6d19a46edb 100644 --- a/bsp/stm32/stm32f429-atk-apollo/applications/main.c +++ b/bsp/stm32/stm32f429-atk-apollo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-atk-apollo/board/board.c b/bsp/stm32/stm32f429-atk-apollo/board/board.c index c13619f753..36d2ff17d3 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/board.c +++ b/bsp/stm32/stm32f429-atk-apollo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -18,11 +18,11 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE |RCC_OSCILLATORTYPE_LSE; @@ -39,13 +39,13 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Activate the Over-Drive mode + /**Activate the Over-Drive mode */ if (HAL_PWREx_EnableOverDrive() != HAL_OK) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f429-atk-apollo/board/board.h b/bsp/stm32/stm32f429-atk-apollo/board/board.h index 9173f50c46..077b0af713 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/board.h +++ b/bsp/stm32/stm32f429-atk-apollo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.c b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.c index ce1021fb60..889c5b0dee 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.c +++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -86,7 +86,7 @@ void SAIB_config_set(struct rt_audio_configure config) SAIB_samplerate_set(config.samplerate); SAIB_samplebits_set(config.samplebits); } - + static void SAIB_config_init() { _sai_b.hsai.Instance = SAI1_Block_B; diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.h b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.h index 8aeede498c..0cc55f7aa9 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.h +++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -8,10 +8,10 @@ * 2019-07-28 Ernest the first version */ -#ifndef __DRV_MIC_H_ -#define __DRV_MIC_H_ +#ifndef __DRV_MIC_H_ +#define __DRV_MIC_H_ -#include +#include #include #endif diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.c b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.c index 4a51ef6347..f564cc1b84 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.c +++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,7 +16,7 @@ #define DBG_LVL DBG_INFO #include -#define CODEC_I2C_NAME ("i2c1") +#define CODEC_I2C_NAME ("i2c1") #define TX_DMA_FIFO_SIZE (2048) @@ -49,7 +49,7 @@ void SAIA_samplerate_set(rt_uint32_t freq) { RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; int i; - + /* check frequence */ for (i = 0; i < (sizeof(SAI_PSC_TBL) / sizeof(SAI_PSC_TBL[0])); i++) { @@ -60,12 +60,12 @@ void SAIA_samplerate_set(rt_uint32_t freq) LOG_E("Can not support this frequence: %d.", freq); return; } - + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SAI_PLLI2S; PeriphClkInitStruct.PLLI2S.PLLI2SN = SAI_PSC_TBL[i][1]; PeriphClkInitStruct.PLLI2S.PLLI2SQ = SAI_PSC_TBL[i][2]; PeriphClkInitStruct.PLLI2SDivQ = SAI_PSC_TBL[i][3] + 1; - + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(RCC_SAIACLKSOURCE_PLLI2S); diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.h b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.h index 216481444f..28a1ea210d 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.h +++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.h @@ -1,19 +1,19 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2019-07-28 Ernest the first version + * 2019-07-28 Ernest the first version */ -#ifndef __DRV_SOUND_H_ -#define __DRV_SOUND_H_ +#ifndef __DRV_SOUND_H_ +#define __DRV_SOUND_H_ -#include +#include #include -#include +#include #define AUDIO_FREQUENCY_048K ((rt_uint32_t) 48000) #define AUDIO_FREQUENCY_044K ((rt_uint32_t) 44100) diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.c b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.c index 5c7b8084c4..0f650538f9 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.c +++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -763,8 +763,8 @@ rt_err_t wm8978_init(struct rt_i2c_bus_device *dev) wm8978_interface_cfg(dev, I2S_FOMAT_SELECT, 16); wm8978_mic_enabled(dev, 0); - - return RT_EOK; + + return RT_EOK; } void wm8978_DAC_enabled(struct rt_i2c_bus_device *dev, rt_bool_t bool) diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.h b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.h index d385255f9c..fe476ec0bb 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.h +++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/fal_cfg.h b/bsp/stm32/stm32f429-atk-apollo/board/ports/fal_cfg.h index a587e207ce..995136cd54 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/phy_reset.c b/bsp/stm32/stm32f429-atk-apollo/board/ports/phy_reset.c index 666d053b25..826f8c7ded 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/ports/phy_reset.c +++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/phy_reset.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,8 +16,8 @@ #include #define ETH_RESET_IO 7 //PHY RESET PIN -#define I2C_BUS_NAME "i2c1" -#define PCF8574_ADDR 0x20 +#define I2C_BUS_NAME "i2c1" +#define PCF8574_ADDR 0x20 /* pcf8574 hardware init */ pcf8574_device_t pcf8574_hw_init(char * dev_name, int addr) diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/sdcard_port.c b/bsp/stm32/stm32f429-atk-apollo/board/ports/sdcard_port.c index 0a9c36fd42..bc7e8b676e 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/ports/sdcard_port.c +++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/sdcard_port.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/sdram_port.h b/bsp/stm32/stm32f429-atk-apollo/board/ports/sdram_port.h index ff948cb61e..85697210fa 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/ports/sdram_port.h +++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/sdram_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/spi_flash_init.c b/bsp/stm32/stm32f429-atk-apollo/board/ports/spi_flash_init.c index 26a9b2d2a8..7e35a36c86 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/ports/spi_flash_init.c +++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/spi_flash_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-fire-challenger/applications/main.c b/bsp/stm32/stm32f429-fire-challenger/applications/main.c index 1078b64286..64e40b75c8 100644 --- a/bsp/stm32/stm32f429-fire-challenger/applications/main.c +++ b/bsp/stm32/stm32f429-fire-challenger/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-fire-challenger/board/board.c b/bsp/stm32/stm32f429-fire-challenger/board/board.c index ec47ab0d3a..5ca583d599 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/board.c +++ b/bsp/stm32/stm32f429-fire-challenger/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-fire-challenger/board/board.h b/bsp/stm32/stm32f429-fire-challenger/board/board.h index ab9e1733e9..c51f6a93cc 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/board.h +++ b/bsp/stm32/stm32f429-fire-challenger/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-fire-challenger/board/ports/fal_cfg.h b/bsp/stm32/stm32f429-fire-challenger/board/ports/fal_cfg.h index a587e207ce..995136cd54 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32f429-fire-challenger/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-fire-challenger/board/ports/lcd_port.h b/bsp/stm32/stm32f429-fire-challenger/board/ports/lcd_port.h index 2660f3931b..8d297ec915 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/ports/lcd_port.h +++ b/bsp/stm32/stm32f429-fire-challenger/board/ports/lcd_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-fire-challenger/board/ports/phy_reset.c b/bsp/stm32/stm32f429-fire-challenger/board/ports/phy_reset.c index 298dd14e29..8eaf6dcd5a 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/ports/phy_reset.c +++ b/bsp/stm32/stm32f429-fire-challenger/board/ports/phy_reset.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-fire-challenger/board/ports/sdcard_port.c b/bsp/stm32/stm32f429-fire-challenger/board/ports/sdcard_port.c index d7b740ae47..01111ab4d3 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/ports/sdcard_port.c +++ b/bsp/stm32/stm32f429-fire-challenger/board/ports/sdcard_port.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-fire-challenger/board/ports/sdram_port.h b/bsp/stm32/stm32f429-fire-challenger/board/ports/sdram_port.h index 72d7c8d06d..1e5978871b 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/ports/sdram_port.h +++ b/bsp/stm32/stm32f429-fire-challenger/board/ports/sdram_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-fire-challenger/board/ports/spi_flash_init.c b/bsp/stm32/stm32f429-fire-challenger/board/ports/spi_flash_init.c index 5a1a4a2585..94a550cf37 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/ports/spi_flash_init.c +++ b/bsp/stm32/stm32f429-fire-challenger/board/ports/spi_flash_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-st-disco/applications/lcd_init.c b/bsp/stm32/stm32f429-st-disco/applications/lcd_init.c index 277a754ae6..2660e6ef7c 100644 --- a/bsp/stm32/stm32f429-st-disco/applications/lcd_init.c +++ b/bsp/stm32/stm32f429-st-disco/applications/lcd_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-st-disco/applications/main.c b/bsp/stm32/stm32f429-st-disco/applications/main.c index 8e6e8caef1..992f2b5d74 100644 --- a/bsp/stm32/stm32f429-st-disco/applications/main.c +++ b/bsp/stm32/stm32f429-st-disco/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-st-disco/board/board.c b/bsp/stm32/stm32f429-st-disco/board/board.c index ca12c3724e..5e9e6f4c77 100644 --- a/bsp/stm32/stm32f429-st-disco/board/board.c +++ b/bsp/stm32/stm32f429-st-disco/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,11 +17,11 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - /** Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -35,7 +35,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f429-st-disco/board/board.h b/bsp/stm32/stm32f429-st-disco/board/board.h index 47e439a260..2d2b2088a3 100644 --- a/bsp/stm32/stm32f429-st-disco/board/board.h +++ b/bsp/stm32/stm32f429-st-disco/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-st-disco/board/ports/fal_cfg.h b/bsp/stm32/stm32f429-st-disco/board/ports/fal_cfg.h index 46ecb322c4..ac75718bc7 100644 --- a/bsp/stm32/stm32f429-st-disco/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32f429-st-disco/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -57,7 +57,7 @@ extern struct fal_flash_dev nor_flash0; &nor_flash0, \ } -#define ONCHIP_FLASH_PART_TABLE +#define ONCHIP_FLASH_PART_TABLE #define QSPI_FLASH_PART_TABLE \ {FAL_PART_MAGIC_WROD, "qspiflash", FAL_USING_NOR_FLASH_DEV_NAME, 0 , (16 * 1024 * 1024), 0}, @@ -76,7 +76,7 @@ extern struct fal_flash_dev nor_flash0; {FAL_PART_MAGIC_WROD, "param", "onchip_flash_64k", 0 , FLASH_SIZE_GRANULARITY_64K , 0}, \ {FAL_PART_MAGIC_WROD, "app", "onchip_flash_128k", 0 , FLASH_SIZE_GRANULARITY_128K, 0}, -#define QSPI_FLASH_PART_TABLE +#define QSPI_FLASH_PART_TABLE #else diff --git a/bsp/stm32/stm32f429-st-disco/board/ports/touch/drv_touch.c b/bsp/stm32/stm32f429-st-disco/board/ports/touch/drv_touch.c index 8559b69f98..d70e444ef4 100644 --- a/bsp/stm32/stm32f429-st-disco/board/ports/touch/drv_touch.c +++ b/bsp/stm32/stm32f429-st-disco/board/ports/touch/drv_touch.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -154,7 +154,7 @@ int32_t touch_get_state(struct touch_state *state) res = touch_read(STMPE811_TSC_CTRL, &val); if (res < 0) return -1; state->pressed = (val & (1 << 7)) ? 1 : 0; - + if (state->pressed) { val = STMPE811_TSC_DATA; @@ -218,7 +218,7 @@ static int rt_hw_touch_init(void) /* register touch device to RT-Thread */ rt_device_register(&touch, "touch", RT_DEVICE_FLAG_RDWR); - + return RT_EOK; } INIT_BOARD_EXPORT(rt_hw_touch_init); diff --git a/bsp/stm32/stm32f429-st-disco/board/ports/touch/drv_touch.h b/bsp/stm32/stm32f429-st-disco/board/ports/touch/drv_touch.h index 68c8f92b7f..a7b6328f17 100644 --- a/bsp/stm32/stm32f429-st-disco/board/ports/touch/drv_touch.h +++ b/bsp/stm32/stm32f429-st-disco/board/ports/touch/drv_touch.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f446-st-nucleo/applications/main.c b/bsp/stm32/stm32f446-st-nucleo/applications/main.c index 0f283769a9..897c6eec1c 100644 --- a/bsp/stm32/stm32f446-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32f446-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f446-st-nucleo/board/board.c b/bsp/stm32/stm32f446-st-nucleo/board/board.c index aba3df89e1..a2500ee68a 100644 --- a/bsp/stm32/stm32f446-st-nucleo/board/board.c +++ b/bsp/stm32/stm32f446-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,11 +16,11 @@ void SystemClock_Config(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -35,13 +35,13 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Activate the Over-Drive mode + /**Activate the Over-Drive mode */ if (HAL_PWREx_EnableOverDrive() != HAL_OK) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f446-st-nucleo/board/board.h b/bsp/stm32/stm32f446-st-nucleo/board/board.h index 1800e44079..8cb4438f8b 100644 --- a/bsp/stm32/stm32f446-st-nucleo/board/board.h +++ b/bsp/stm32/stm32f446-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f469-st-disco/applications/lcd_init.c b/bsp/stm32/stm32f469-st-disco/applications/lcd_init.c index 277a754ae6..2660e6ef7c 100644 --- a/bsp/stm32/stm32f469-st-disco/applications/lcd_init.c +++ b/bsp/stm32/stm32f469-st-disco/applications/lcd_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f469-st-disco/applications/main.c b/bsp/stm32/stm32f469-st-disco/applications/main.c index 8feca19928..759572d376 100644 --- a/bsp/stm32/stm32f469-st-disco/applications/main.c +++ b/bsp/stm32/stm32f469-st-disco/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f469-st-disco/board/board.c b/bsp/stm32/stm32f469-st-disco/board/board.c index 8c4c361dcc..fefb07fafd 100644 --- a/bsp/stm32/stm32f469-st-disco/board/board.c +++ b/bsp/stm32/stm32f469-st-disco/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,11 +17,11 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - /** Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -36,13 +36,13 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Activate the Over-Drive mode + /** Activate the Over-Drive mode */ if (HAL_PWREx_EnableOverDrive() != HAL_OK) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f469-st-disco/board/board.h b/bsp/stm32/stm32f469-st-disco/board/board.h index 0880c1f384..607aa3877d 100644 --- a/bsp/stm32/stm32f469-st-disco/board/board.h +++ b/bsp/stm32/stm32f469-st-disco/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/drv_otm8009a.c b/bsp/stm32/stm32f469-st-disco/board/ports/drv_otm8009a.c index 84202f84c8..8fde3a56ae 100644 --- a/bsp/stm32/stm32f469-st-disco/board/ports/drv_otm8009a.c +++ b/bsp/stm32/stm32f469-st-disco/board/ports/drv_otm8009a.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2019-05-23 WillianChan first version */ - + #include #ifdef BSP_USING_LCD_OTM8009A extern DSI_HandleTypeDef hdsi; @@ -93,9 +93,9 @@ const rt_uint8_t RDS49[] = {0xF5, 0x06}; const rt_uint8_t RDS50[] = {0x00, 0xB1}; const rt_uint8_t RDS51[] = {0xC6, 0x06}; -void otm8009a_reset(void) +void otm8009a_reset(void) { - rt_pin_mode (GET_PIN(H, 7), PIN_MODE_OUTPUT); + rt_pin_mode (GET_PIN(H, 7), PIN_MODE_OUTPUT); rt_pin_write(GET_PIN(H, 7), PIN_LOW); rt_thread_delay(rt_tick_from_millisecond(20)); rt_pin_write(GET_PIN(H, 7), PIN_HIGH); @@ -116,7 +116,7 @@ static void otm8009a_write_cmd(uint8_t *p, uint32_t num) static void otm8009a_delay(uint32_t d) { - rt_thread_delay(rt_tick_from_millisecond(d)); + rt_thread_delay(rt_tick_from_millisecond(d)); } static void otm8009a_config(rt_uint32_t pixel_format) @@ -127,11 +127,11 @@ static void otm8009a_config(rt_uint32_t pixel_format) otm8009a_write_cmd((rt_uint8_t *)RDL02, 2); otm8009a_write_cmd((rt_uint8_t *)RDS02, 0); otm8009a_write_cmd((rt_uint8_t *)RDS03, 0); - otm8009a_delay(10); + otm8009a_delay(10); otm8009a_write_cmd((rt_uint8_t *)RDS04, 0); otm8009a_write_cmd((rt_uint8_t *)RDS05, 0); - otm8009a_delay(10); + otm8009a_delay(10); otm8009a_write_cmd((rt_uint8_t *)RDS06, 0); otm8009a_write_cmd((rt_uint8_t *)RDS07, 0); @@ -215,8 +215,8 @@ static void otm8009a_config(rt_uint32_t pixel_format) otm8009a_write_cmd((rt_uint8_t *)RDS01, 0); otm8009a_write_cmd((rt_uint8_t *)RDL04, 16); otm8009a_write_cmd((rt_uint8_t *)RDS36, 0); - otm8009a_delay(120); - + otm8009a_delay(120); + switch (pixel_format) { case RTGRAPHIC_PIXEL_FORMAT_RGB565: @@ -248,7 +248,7 @@ void stm32_mipi_lcd_init(void) void stm32_mipi_lcd_config(rt_uint32_t pixel_format) { - otm8009a_config(pixel_format); + otm8009a_config(pixel_format); } void stm32_mipi_display_on(void) diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/drv_qspi_flash.c b/bsp/stm32/stm32f469-st-disco/board/ports/drv_qspi_flash.c index f5fe27d6e1..ff1b11e34c 100644 --- a/bsp/stm32/stm32f469-st-disco/board/ports/drv_qspi_flash.c +++ b/bsp/stm32/stm32f469-st-disco/board/ports/drv_qspi_flash.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -8,7 +8,7 @@ * 2018-11-27 zylx first version * 2019-04-11 ZYH port from stm32f7serial */ - + #include #include #include @@ -64,7 +64,7 @@ void n25qxxa_enter_qspi_mode(struct rt_qspi_device *device) static int rt_hw_qspi_flash_with_sfud_init(void) { stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, n25qxxa_enter_qspi_mode, RT_NULL); - + /* init n25qxx */ if (RT_NULL == rt_sfud_flash_probe(FAL_USING_NOR_FLASH_DEV_NAME, "qspi10")) { diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/drv_sdcard.c b/bsp/stm32/stm32f469-st-disco/board/ports/drv_sdcard.c index cfe6f59e1e..9fd2d11fd4 100644 --- a/bsp/stm32/stm32f469-st-disco/board/ports/drv_sdcard.c +++ b/bsp/stm32/stm32f469-st-disco/board/ports/drv_sdcard.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -29,7 +29,7 @@ static void _sdcard_mount(void) { rt_device_t device; - + device = rt_device_find("sd0"); if (device == NULL) { @@ -56,7 +56,7 @@ static void _sdcard_unmount(void) rt_thread_mdelay(200); dfs_unmount("/"); LOG_I("Unmount \"/\""); - + mmcsd_wait_cd_changed(0); stm32_mmcsd_change(); mmcsd_wait_cd_changed(RT_WAITING_FOREVER); @@ -65,7 +65,7 @@ static void _sdcard_unmount(void) static void sd_mount(void *parameter) { rt_uint8_t re_sd_check_pin = 1; - + while (1) { rt_thread_mdelay(200); @@ -73,7 +73,7 @@ static void sd_mount(void *parameter) { _sdcard_mount(); } - + if (!re_sd_check_pin && (re_sd_check_pin = rt_pin_read(SD_CHECK_PIN)) != 0) { _sdcard_unmount(); @@ -84,7 +84,7 @@ static void sd_mount(void *parameter) int stm32_sdcard_mount(void) { rt_thread_t tid; - + rt_pin_mode(SD_CHECK_PIN, PIN_MODE_INPUT_PULLUP); tid = rt_thread_create("sd_mount", sd_mount, RT_NULL, diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/fal_cfg.h b/bsp/stm32/stm32f469-st-disco/board/ports/fal_cfg.h index 46ecb322c4..ac75718bc7 100644 --- a/bsp/stm32/stm32f469-st-disco/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32f469-st-disco/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -57,7 +57,7 @@ extern struct fal_flash_dev nor_flash0; &nor_flash0, \ } -#define ONCHIP_FLASH_PART_TABLE +#define ONCHIP_FLASH_PART_TABLE #define QSPI_FLASH_PART_TABLE \ {FAL_PART_MAGIC_WROD, "qspiflash", FAL_USING_NOR_FLASH_DEV_NAME, 0 , (16 * 1024 * 1024), 0}, @@ -76,7 +76,7 @@ extern struct fal_flash_dev nor_flash0; {FAL_PART_MAGIC_WROD, "param", "onchip_flash_64k", 0 , FLASH_SIZE_GRANULARITY_64K , 0}, \ {FAL_PART_MAGIC_WROD, "app", "onchip_flash_128k", 0 , FLASH_SIZE_GRANULARITY_128K, 0}, -#define QSPI_FLASH_PART_TABLE +#define QSPI_FLASH_PART_TABLE #else diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/lcd_port.h b/bsp/stm32/stm32f469-st-disco/board/ports/lcd_port.h index d5ee2b13b4..b23a970538 100644 --- a/bsp/stm32/stm32f469-st-disco/board/ports/lcd_port.h +++ b/bsp/stm32/stm32f469-st-disco/board/ports/lcd_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,19 +7,19 @@ * Date Author Notes * 2018-07-28 liu2guang the first version for STM32F469NI-Discovery. */ - -#ifndef __DRV_LCD_H_ -#define __DRV_LCD_H_ -#include +#ifndef __DRV_LCD_H_ +#define __DRV_LCD_H_ + +#include #include -#include +#include #define LCD_WIDTH (800U) #define LCD_HEIGHT (480U) #define LCD_HSYNC (1U) -#define LCD_HBP (15U) +#define LCD_HBP (15U) #define LCD_HFP (16U) #define LCD_VSYNC (2U) #define LCD_VBP (34U) diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/qspi_mnt.c b/bsp/stm32/stm32f469-st-disco/board/ports/qspi_mnt.c index f90b468463..5b311a391a 100644 --- a/bsp/stm32/stm32f469-st-disco/board/ports/qspi_mnt.c +++ b/bsp/stm32/stm32f469-st-disco/board/ports/qspi_mnt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/sdram_port.h b/bsp/stm32/stm32f469-st-disco/board/ports/sdram_port.h index 14d44f7115..7b33d36362 100644 --- a/bsp/stm32/stm32f469-st-disco/board/ports/sdram_port.h +++ b/bsp/stm32/stm32f469-st-disco/board/ports/sdram_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch.c b/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch.c index 1ff29544ff..53437f34ef 100644 --- a/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch.c +++ b/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-02-08 Zhangyihong the first version */ - + #include "drv_touch.h" #include #ifdef BSP_USING_TOUCH @@ -105,7 +105,7 @@ static void touch_thread_entry(void *parameter) { continue; } - + while(touch->ops->read_point(&msg) == RT_EOK) { switch (msg.event) diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch.h b/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch.h index a8fea21d54..21bea39f83 100644 --- a/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch.h +++ b/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-02-08 Zhangyihong the first version */ - + #ifndef __DRV_TOUCH_H__ #define __DRV_TOUCH_H__ diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch_ft.c b/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch_ft.c index a7e9275441..e85e793573 100644 --- a/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch_ft.c +++ b/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch_ft.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -109,7 +109,7 @@ static rt_err_t ft_read_point(touch_msg_t msg) { return RT_ERROR; } - + if (point_num == 0) { if (s_tp_down) @@ -121,7 +121,7 @@ static rt_err_t ft_read_point(touch_msg_t msg) msg->event = TOUCH_EVENT_NONE; return RT_ERROR; } - + ret = ft_read(ft_i2c_bus, 0x03, point, 6); if (ret < 0) { @@ -130,7 +130,7 @@ static rt_err_t ft_read_point(touch_msg_t msg) msg->y = (point[0]&0x0F) << 8 | point[1]; msg->x = (point[2]&0x0F) << 8 | point[3]; - + if (s_tp_down) { msg->event = TOUCH_EVENT_MOVE; @@ -138,7 +138,7 @@ static rt_err_t ft_read_point(touch_msg_t msg) } msg->event = TOUCH_EVENT_DOWN; s_tp_down = 1; - + return RT_EOK; } diff --git a/bsp/stm32/stm32f746-st-disco/applications/main.c b/bsp/stm32/stm32f746-st-disco/applications/main.c index 669d889e58..0024ce1c0a 100644 --- a/bsp/stm32/stm32f746-st-disco/applications/main.c +++ b/bsp/stm32/stm32f746-st-disco/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f746-st-disco/board/board.c b/bsp/stm32/stm32f746-st-disco/board/board.c index bf92d115e7..da2564d515 100644 --- a/bsp/stm32/stm32f746-st-disco/board/board.c +++ b/bsp/stm32/stm32f746-st-disco/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,14 +20,14 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - /**Configure LSE Drive Capability + /**Configure LSE Drive Capability */ HAL_PWR_EnableBkUpAccess(); - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -42,13 +42,13 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Activate the Over-Drive mode + /**Activate the Over-Drive mode */ if (HAL_PWREx_EnableOverDrive() != HAL_OK) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f746-st-disco/board/board.h b/bsp/stm32/stm32f746-st-disco/board/board.h index 98e3799e00..b0c120fb41 100644 --- a/bsp/stm32/stm32f746-st-disco/board/board.h +++ b/bsp/stm32/stm32f746-st-disco/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f746-st-disco/board/ports/drv_qspi_flash.c b/bsp/stm32/stm32f746-st-disco/board/ports/drv_qspi_flash.c index ca7641f866..4e37f4ec2f 100644 --- a/bsp/stm32/stm32f746-st-disco/board/ports/drv_qspi_flash.c +++ b/bsp/stm32/stm32f746-st-disco/board/ports/drv_qspi_flash.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2019-01-26 jinsheng first version */ - + #include #include #include @@ -63,7 +63,7 @@ void n25qxx_enter_qspi_mode(struct rt_qspi_device *device) static int rt_hw_qspi_flash_with_sfud_init(void) { stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, n25qxx_enter_qspi_mode, RT_NULL); - + /* init n25q128 */ if (RT_NULL == rt_sfud_flash_probe("n25q128", "qspi10")) { diff --git a/bsp/stm32/stm32f746-st-disco/board/ports/fal_cfg.h b/bsp/stm32/stm32f746-st-disco/board/ports/fal_cfg.h index c886dab45d..d7ce293475 100644 --- a/bsp/stm32/stm32f746-st-disco/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32f746-st-disco/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f746-st-disco/board/ports/lcd_port.h b/bsp/stm32/stm32f746-st-disco/board/ports/lcd_port.h index f534e50522..8ea00b0ed4 100644 --- a/bsp/stm32/stm32f746-st-disco/board/ports/lcd_port.h +++ b/bsp/stm32/stm32f746-st-disco/board/ports/lcd_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f746-st-disco/board/ports/phy_reset.c b/bsp/stm32/stm32f746-st-disco/board/ports/phy_reset.c index 3d5f75c7f0..5825f775cc 100644 --- a/bsp/stm32/stm32f746-st-disco/board/ports/phy_reset.c +++ b/bsp/stm32/stm32f746-st-disco/board/ports/phy_reset.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f746-st-disco/board/ports/sdcard_port.c b/bsp/stm32/stm32f746-st-disco/board/ports/sdcard_port.c index 0797f9326c..66e8dfefab 100644 --- a/bsp/stm32/stm32f746-st-disco/board/ports/sdcard_port.c +++ b/bsp/stm32/stm32f746-st-disco/board/ports/sdcard_port.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f746-st-disco/board/ports/sdram_port.h b/bsp/stm32/stm32f746-st-disco/board/ports/sdram_port.h index 4c49e0f217..91bb91b01b 100644 --- a/bsp/stm32/stm32f746-st-disco/board/ports/sdram_port.h +++ b/bsp/stm32/stm32f746-st-disco/board/ports/sdram_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f767-atk-apollo/applications/main.c b/bsp/stm32/stm32f767-atk-apollo/applications/main.c index 7d7440f05c..71e6132ea2 100644 --- a/bsp/stm32/stm32f767-atk-apollo/applications/main.c +++ b/bsp/stm32/stm32f767-atk-apollo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f767-atk-apollo/board/board.c b/bsp/stm32/stm32f767-atk-apollo/board/board.c index d9959f9301..726b7783b7 100644 --- a/bsp/stm32/stm32f767-atk-apollo/board/board.c +++ b/bsp/stm32/stm32f767-atk-apollo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,15 +16,15 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - /** Configure LSE Drive Capability + /** Configure LSE Drive Capability */ HAL_PWR_EnableBkUpAccess(); __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); - /** Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE |RCC_OSCILLATORTYPE_LSE; @@ -41,13 +41,13 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Activate the Over-Drive mode + /** Activate the Over-Drive mode */ if (HAL_PWREx_EnableOverDrive() != HAL_OK) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f767-atk-apollo/board/board.h b/bsp/stm32/stm32f767-atk-apollo/board/board.h index 3d986024ae..e91271055e 100644 --- a/bsp/stm32/stm32f767-atk-apollo/board/board.h +++ b/bsp/stm32/stm32f767-atk-apollo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f767-atk-apollo/board/ports/drv_qspi_flash.c b/bsp/stm32/stm32f767-atk-apollo/board/ports/drv_qspi_flash.c index 5cabc9d4d2..72e589aea4 100644 --- a/bsp/stm32/stm32f767-atk-apollo/board/ports/drv_qspi_flash.c +++ b/bsp/stm32/stm32f767-atk-apollo/board/ports/drv_qspi_flash.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-11-27 zylx first version */ - + #include #include #include @@ -63,7 +63,7 @@ void w25qxx_enter_qspi_mode(struct rt_qspi_device *device) static int rt_hw_qspi_flash_with_sfud_init(void) { stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, w25qxx_enter_qspi_mode, RT_NULL); - + /* init W25Q256 */ if (RT_NULL == rt_sfud_flash_probe("W25Q256", "qspi10")) { diff --git a/bsp/stm32/stm32f767-atk-apollo/board/ports/fal_cfg.h b/bsp/stm32/stm32f767-atk-apollo/board/ports/fal_cfg.h index 891beb2010..5ddddaa2cd 100644 --- a/bsp/stm32/stm32f767-atk-apollo/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32f767-atk-apollo/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f767-atk-apollo/board/ports/lcd_port.h b/bsp/stm32/stm32f767-atk-apollo/board/ports/lcd_port.h index ca894bb045..156ba2e2cf 100644 --- a/bsp/stm32/stm32f767-atk-apollo/board/ports/lcd_port.h +++ b/bsp/stm32/stm32f767-atk-apollo/board/ports/lcd_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f767-atk-apollo/board/ports/phy_reset.c b/bsp/stm32/stm32f767-atk-apollo/board/ports/phy_reset.c index d00e6c06e0..18bed5f8e4 100644 --- a/bsp/stm32/stm32f767-atk-apollo/board/ports/phy_reset.c +++ b/bsp/stm32/stm32f767-atk-apollo/board/ports/phy_reset.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f767-atk-apollo/board/ports/sdcard_port.c b/bsp/stm32/stm32f767-atk-apollo/board/ports/sdcard_port.c index 0a9c36fd42..bc7e8b676e 100644 --- a/bsp/stm32/stm32f767-atk-apollo/board/ports/sdcard_port.c +++ b/bsp/stm32/stm32f767-atk-apollo/board/ports/sdcard_port.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f767-atk-apollo/board/ports/sdram_port.h b/bsp/stm32/stm32f767-atk-apollo/board/ports/sdram_port.h index ff948cb61e..85697210fa 100644 --- a/bsp/stm32/stm32f767-atk-apollo/board/ports/sdram_port.h +++ b/bsp/stm32/stm32f767-atk-apollo/board/ports/sdram_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f767-fire-challenger/applications/main.c b/bsp/stm32/stm32f767-fire-challenger/applications/main.c index 9ed6529712..4cf67f2e9e 100644 --- a/bsp/stm32/stm32f767-fire-challenger/applications/main.c +++ b/bsp/stm32/stm32f767-fire-challenger/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f767-fire-challenger/board/board.c b/bsp/stm32/stm32f767-fire-challenger/board/board.c index f5b0c783c7..de621405e1 100644 --- a/bsp/stm32/stm32f767-fire-challenger/board/board.c +++ b/bsp/stm32/stm32f767-fire-challenger/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,11 +16,11 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -34,13 +34,13 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Activate the Over-Drive mode + /**Activate the Over-Drive mode */ if (HAL_PWREx_EnableOverDrive() != HAL_OK) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f767-fire-challenger/board/board.h b/bsp/stm32/stm32f767-fire-challenger/board/board.h index 1beb8c5f87..e9a1277849 100644 --- a/bsp/stm32/stm32f767-fire-challenger/board/board.h +++ b/bsp/stm32/stm32f767-fire-challenger/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f767-fire-challenger/board/ports/drv_qspi_flash.c b/bsp/stm32/stm32f767-fire-challenger/board/ports/drv_qspi_flash.c index 36ecb754e9..a3091fd2eb 100644 --- a/bsp/stm32/stm32f767-fire-challenger/board/ports/drv_qspi_flash.c +++ b/bsp/stm32/stm32f767-fire-challenger/board/ports/drv_qspi_flash.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-11-27 zylx first version */ - + #include #include #include @@ -63,7 +63,7 @@ void w25qxx_enter_qspi_mode(struct rt_qspi_device *device) static int rt_hw_qspi_flash_with_sfud_init(void) { stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, w25qxx_enter_qspi_mode, RT_NULL); - + /* init w25q128 */ if (RT_NULL == rt_sfud_flash_probe("W25Q128", "qspi10")) { diff --git a/bsp/stm32/stm32f767-fire-challenger/board/ports/fal_cfg.h b/bsp/stm32/stm32f767-fire-challenger/board/ports/fal_cfg.h index 891beb2010..5ddddaa2cd 100644 --- a/bsp/stm32/stm32f767-fire-challenger/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32f767-fire-challenger/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f767-fire-challenger/board/ports/lcd_port.h b/bsp/stm32/stm32f767-fire-challenger/board/ports/lcd_port.h index 2660f3931b..8d297ec915 100644 --- a/bsp/stm32/stm32f767-fire-challenger/board/ports/lcd_port.h +++ b/bsp/stm32/stm32f767-fire-challenger/board/ports/lcd_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f767-fire-challenger/board/ports/phy_reset.c b/bsp/stm32/stm32f767-fire-challenger/board/ports/phy_reset.c index 298dd14e29..8eaf6dcd5a 100644 --- a/bsp/stm32/stm32f767-fire-challenger/board/ports/phy_reset.c +++ b/bsp/stm32/stm32f767-fire-challenger/board/ports/phy_reset.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f767-fire-challenger/board/ports/sdcard_port.c b/bsp/stm32/stm32f767-fire-challenger/board/ports/sdcard_port.c index 615ad6e06e..f1a7b8c27f 100644 --- a/bsp/stm32/stm32f767-fire-challenger/board/ports/sdcard_port.c +++ b/bsp/stm32/stm32f767-fire-challenger/board/ports/sdcard_port.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f767-fire-challenger/board/ports/sdram_port.h b/bsp/stm32/stm32f767-fire-challenger/board/ports/sdram_port.h index 0d9c7e6918..7f9485aa4a 100644 --- a/bsp/stm32/stm32f767-fire-challenger/board/ports/sdram_port.h +++ b/bsp/stm32/stm32f767-fire-challenger/board/ports/sdram_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f767-st-nucleo/applications/main.c b/bsp/stm32/stm32f767-st-nucleo/applications/main.c index ed3fc2c341..a0967c1326 100644 --- a/bsp/stm32/stm32f767-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32f767-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -30,5 +30,5 @@ int main(void) rt_thread_mdelay(500); } - return RT_EOK; + return RT_EOK; } diff --git a/bsp/stm32/stm32f767-st-nucleo/board/board.c b/bsp/stm32/stm32f767-st-nucleo/board/board.c index 0c63bfe489..4e00f26886 100644 --- a/bsp/stm32/stm32f767-st-nucleo/board/board.c +++ b/bsp/stm32/stm32f767-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -21,14 +21,14 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - /**Configure LSE Drive Capability + /**Configure LSE Drive Capability */ HAL_PWR_EnableBkUpAccess(); - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; @@ -42,13 +42,13 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Activate the Over-Drive mode + /**Activate the Over-Drive mode */ if (HAL_PWREx_EnableOverDrive() != HAL_OK) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f767-st-nucleo/board/board.h b/bsp/stm32/stm32f767-st-nucleo/board/board.h index 1d1e1d1106..1d82defe0d 100644 --- a/bsp/stm32/stm32f767-st-nucleo/board/board.h +++ b/bsp/stm32/stm32f767-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f767-st-nucleo/board/ports/phy_reset.c b/bsp/stm32/stm32f767-st-nucleo/board/ports/phy_reset.c index 8a833eec2a..79b8fecc16 100644 --- a/bsp/stm32/stm32f767-st-nucleo/board/ports/phy_reset.c +++ b/bsp/stm32/stm32f767-st-nucleo/board/ports/phy_reset.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,6 +16,6 @@ void phy_reset(void) * The PHY reset pin of NUCLEO-F767ZI is connected to the MCU reset pin, * so no additional reset is required. */ - + return ; } diff --git a/bsp/stm32/stm32f769-st-disco/applications/main.c b/bsp/stm32/stm32f769-st-disco/applications/main.c index 14a2f68f81..d61afe14c3 100644 --- a/bsp/stm32/stm32f769-st-disco/applications/main.c +++ b/bsp/stm32/stm32f769-st-disco/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f769-st-disco/board/board.c b/bsp/stm32/stm32f769-st-disco/board/board.c index 97bbbe3076..55126435b1 100644 --- a/bsp/stm32/stm32f769-st-disco/board/board.c +++ b/bsp/stm32/stm32f769-st-disco/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,14 +20,14 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - /** Configure LSE Drive Capability + /** Configure LSE Drive Capability */ HAL_PWR_EnableBkUpAccess(); - /** Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; @@ -42,13 +42,13 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Activate the Over-Drive mode + /** Activate the Over-Drive mode */ if (HAL_PWREx_EnableOverDrive() != HAL_OK) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f769-st-disco/board/board.h b/bsp/stm32/stm32f769-st-disco/board/board.h index 85c900e4c8..813dd5b27e 100644 --- a/bsp/stm32/stm32f769-st-disco/board/board.h +++ b/bsp/stm32/stm32f769-st-disco/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32g071-st-nucleo/applications/main.c b/bsp/stm32/stm32g071-st-nucleo/applications/main.c index 8541bd3b9f..5f22fcae65 100644 --- a/bsp/stm32/stm32g071-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32g071-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32g071-st-nucleo/board/board.c b/bsp/stm32/stm32g071-st-nucleo/board/board.c index 5d634db15e..28d4e56e46 100644 --- a/bsp/stm32/stm32g071-st-nucleo/board/board.c +++ b/bsp/stm32/stm32g071-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,10 +16,10 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; @@ -36,7 +36,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1; @@ -48,7 +48,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Initializes the peripherals clocks + /**Initializes the peripherals clocks */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1; diff --git a/bsp/stm32/stm32g071-st-nucleo/board/board.h b/bsp/stm32/stm32g071-st-nucleo/board/board.h index f0345a1293..d36387892b 100644 --- a/bsp/stm32/stm32g071-st-nucleo/board/board.h +++ b/bsp/stm32/stm32g071-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32g071-st-nucleo/board/ports/fal_cfg.h b/bsp/stm32/stm32g071-st-nucleo/board/ports/fal_cfg.h index ee65e188d9..277b98ba70 100644 --- a/bsp/stm32/stm32g071-st-nucleo/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32g071-st-nucleo/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32g431-st-nucleo/applications/main.c b/bsp/stm32/stm32g431-st-nucleo/applications/main.c index aad9acb9b9..fa4fd35a6e 100644 --- a/bsp/stm32/stm32g431-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32g431-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32g431-st-nucleo/board/board.c b/bsp/stm32/stm32g431-st-nucleo/board/board.c index f025a3e234..7aeb088632 100644 --- a/bsp/stm32/stm32g431-st-nucleo/board/board.c +++ b/bsp/stm32/stm32g431-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,10 +17,10 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /** Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST); - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; @@ -36,7 +36,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; @@ -49,7 +49,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the peripherals clocks + /** Initializes the peripherals clocks */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1; PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; diff --git a/bsp/stm32/stm32g431-st-nucleo/board/board.h b/bsp/stm32/stm32g431-st-nucleo/board/board.h index 9b91078b0f..6fd0c97890 100644 --- a/bsp/stm32/stm32g431-st-nucleo/board/board.h +++ b/bsp/stm32/stm32g431-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32h743-atk-apollo/applications/main.c b/bsp/stm32/stm32h743-atk-apollo/applications/main.c index 19a43a12e6..376d3c78ff 100644 --- a/bsp/stm32/stm32h743-atk-apollo/applications/main.c +++ b/bsp/stm32/stm32h743-atk-apollo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -18,9 +18,9 @@ int main(void) { int count = 1; - /* set LED0 pin mode to output */ - rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - + /* set LED0 pin mode to output */ + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); + while (count++) { rt_pin_write(LED0_PIN, PIN_HIGH); diff --git a/bsp/stm32/stm32h743-atk-apollo/board/board.c b/bsp/stm32/stm32h743-atk-apollo/board/board.c index 1180633282..0b0dc623f2 100644 --- a/bsp/stm32/stm32h743-atk-apollo/board/board.c +++ b/bsp/stm32/stm32h743-atk-apollo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,22 +16,22 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - /** Supply configuration update enable + /** Supply configuration update enable */ HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); - /** Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} - /** Configure LSE Drive Capability + /** Configure LSE Drive Capability */ HAL_PWR_EnableBkUpAccess(); __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); - /** Macro to configure the PLL clock source + /** Macro to configure the PLL clock source */ __HAL_RCC_PLL_PLLSOURCE_CONFIG(RCC_PLLSOURCE_HSE); - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE |RCC_OSCILLATORTYPE_LSE; @@ -52,7 +52,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 diff --git a/bsp/stm32/stm32h743-atk-apollo/board/board.h b/bsp/stm32/stm32h743-atk-apollo/board/board.h index ffb9772ee7..c9ec7a30d9 100644 --- a/bsp/stm32/stm32h743-atk-apollo/board/board.h +++ b/bsp/stm32/stm32h743-atk-apollo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,7 +20,7 @@ extern "C" { #endif -#if !defined (LSI_VALUE) +#if !defined (LSI_VALUE) #define LSI_VALUE ((uint32_t)32000) #endif diff --git a/bsp/stm32/stm32h743-atk-apollo/board/drv_mpu.c b/bsp/stm32/stm32h743-atk-apollo/board/drv_mpu.c index 088d7a0bb7..1d5e13f9cf 100644 --- a/bsp/stm32/stm32h743-atk-apollo/board/drv_mpu.c +++ b/bsp/stm32/stm32h743-atk-apollo/board/drv_mpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_qspi_flash.c b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_qspi_flash.c index 5cabc9d4d2..72e589aea4 100644 --- a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_qspi_flash.c +++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_qspi_flash.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-11-27 zylx first version */ - + #include #include #include @@ -63,7 +63,7 @@ void w25qxx_enter_qspi_mode(struct rt_qspi_device *device) static int rt_hw_qspi_flash_with_sfud_init(void) { stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, w25qxx_enter_qspi_mode, RT_NULL); - + /* init W25Q256 */ if (RT_NULL == rt_sfud_flash_probe("W25Q256", "qspi10")) { diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/lcd_port.h b/bsp/stm32/stm32h743-atk-apollo/board/ports/lcd_port.h index ca894bb045..156ba2e2cf 100644 --- a/bsp/stm32/stm32h743-atk-apollo/board/ports/lcd_port.h +++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/lcd_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/sdram_port.h b/bsp/stm32/stm32h743-atk-apollo/board/ports/sdram_port.h index 5784f79036..50804561eb 100644 --- a/bsp/stm32/stm32h743-atk-apollo/board/ports/sdram_port.h +++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/sdram_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32h743-st-nucleo/applications/main.c b/bsp/stm32/stm32h743-st-nucleo/applications/main.c index 2a4d35d4d8..9a8ac51bb5 100644 --- a/bsp/stm32/stm32h743-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32h743-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32h743-st-nucleo/board/board.c b/bsp/stm32/stm32h743-st-nucleo/board/board.c index dc2e79d04f..b5a5a4245d 100644 --- a/bsp/stm32/stm32h743-st-nucleo/board/board.c +++ b/bsp/stm32/stm32h743-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32h743-st-nucleo/board/board.h b/bsp/stm32/stm32h743-st-nucleo/board/board.h index 72d84ff29d..32eb25f147 100644 --- a/bsp/stm32/stm32h743-st-nucleo/board/board.h +++ b/bsp/stm32/stm32h743-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32h750-armfly-h7-tool/applications/main.c b/bsp/stm32/stm32h750-armfly-h7-tool/applications/main.c index 73691fa783..b19e338dc5 100644 --- a/bsp/stm32/stm32h750-armfly-h7-tool/applications/main.c +++ b/bsp/stm32/stm32h750-armfly-h7-tool/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32h750-armfly-h7-tool/board/board.c b/bsp/stm32/stm32h750-armfly-h7-tool/board/board.c index 7783d407a8..6426138e1e 100644 --- a/bsp/stm32/stm32h750-armfly-h7-tool/board/board.c +++ b/bsp/stm32/stm32h750-armfly-h7-tool/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,18 +20,18 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - /** Supply configuration update enable + /** Supply configuration update enable */ HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); - /** Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} - /** Macro to configure the PLL clock source + /** Macro to configure the PLL clock source */ __HAL_RCC_PLL_PLLSOURCE_CONFIG(RCC_PLLSOURCE_HSE); - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -50,7 +50,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 diff --git a/bsp/stm32/stm32h750-armfly-h7-tool/board/board.h b/bsp/stm32/stm32h750-armfly-h7-tool/board/board.h index a0455aec76..b41ed17e43 100644 --- a/bsp/stm32/stm32h750-armfly-h7-tool/board/board.h +++ b/bsp/stm32/stm32h750-armfly-h7-tool/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l053-st-nucleo/applications/main.c b/bsp/stm32/stm32l053-st-nucleo/applications/main.c index 8541bd3b9f..5f22fcae65 100644 --- a/bsp/stm32/stm32l053-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32l053-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l053-st-nucleo/board/board.c b/bsp/stm32/stm32l053-st-nucleo/board/board.c index 858d59660f..62621eed0a 100644 --- a/bsp/stm32/stm32l053-st-nucleo/board/board.c +++ b/bsp/stm32/stm32l053-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,11 +17,11 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_PeriphCLKInitTypeDef PeriphClkInit; - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; @@ -35,7 +35,7 @@ void SystemClock_Config(void) _Error_Handler(__FILE__, __LINE__); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; @@ -56,11 +56,11 @@ void SystemClock_Config(void) _Error_Handler(__FILE__, __LINE__); } - /**Configure the Systick interrupt time + /**Configure the Systick interrupt time */ HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); - /**Configure the Systick + /**Configure the Systick */ HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); diff --git a/bsp/stm32/stm32l053-st-nucleo/board/board.h b/bsp/stm32/stm32l053-st-nucleo/board/board.h index 016e4ec4e3..f88ee51946 100644 --- a/bsp/stm32/stm32l053-st-nucleo/board/board.h +++ b/bsp/stm32/stm32l053-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l432-st-nucleo/applications/main.c b/bsp/stm32/stm32l432-st-nucleo/applications/main.c index e1755ec81e..336347c11e 100644 --- a/bsp/stm32/stm32l432-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32l432-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l432-st-nucleo/board/board.c b/bsp/stm32/stm32l432-st-nucleo/board/board.c index 79f7c0344f..93000dc18c 100644 --- a/bsp/stm32/stm32l432-st-nucleo/board/board.c +++ b/bsp/stm32/stm32l432-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,13 +17,13 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_PeriphCLKInitTypeDef PeriphClkInit; - /**Configure LSE Drive Capability + /**Configure LSE Drive Capability */ HAL_PWR_EnableBkUpAccess(); __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI; RCC_OscInitStruct.LSEState = RCC_LSE_ON; @@ -42,7 +42,7 @@ void SystemClock_Config(void) _Error_Handler(__FILE__, __LINE__); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; @@ -63,22 +63,22 @@ void SystemClock_Config(void) _Error_Handler(__FILE__, __LINE__); } - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) { _Error_Handler(__FILE__, __LINE__); } - /**Configure the Systick interrupt time + /**Configure the Systick interrupt time */ HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); - /**Configure the Systick + /**Configure the Systick */ HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); - /**Enable MSI Auto calibration + /**Enable MSI Auto calibration */ HAL_RCCEx_EnableMSIPLLMode(); diff --git a/bsp/stm32/stm32l432-st-nucleo/board/board.h b/bsp/stm32/stm32l432-st-nucleo/board/board.h index 3b3a77e103..77db7fce6e 100644 --- a/bsp/stm32/stm32l432-st-nucleo/board/board.h +++ b/bsp/stm32/stm32l432-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l452-st-nucleo/applications/main.c b/bsp/stm32/stm32l452-st-nucleo/applications/main.c index aad9acb9b9..fa4fd35a6e 100644 --- a/bsp/stm32/stm32l452-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32l452-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l452-st-nucleo/board/board.c b/bsp/stm32/stm32l452-st-nucleo/board/board.c index 5ab9da967a..d6c090b6b8 100644 --- a/bsp/stm32/stm32l452-st-nucleo/board/board.c +++ b/bsp/stm32/stm32l452-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,7 +20,7 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; @@ -36,7 +36,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; @@ -55,7 +55,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) { diff --git a/bsp/stm32/stm32l452-st-nucleo/board/board.h b/bsp/stm32/stm32l452-st-nucleo/board/board.h index 1ea1e6be9c..0c9006dc40 100644 --- a/bsp/stm32/stm32l452-st-nucleo/board/board.h +++ b/bsp/stm32/stm32l452-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l452-st-nucleo/board/ports/fal_cfg.h b/bsp/stm32/stm32l452-st-nucleo/board/ports/fal_cfg.h index db782a5991..09c420dae9 100644 --- a/bsp/stm32/stm32l452-st-nucleo/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32l452-st-nucleo/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,9 +20,9 @@ extern const struct fal_flash_dev stm32_onchip_flash; /* ========================= Device Configuration ========================== */ #ifdef BSP_USING_ON_CHIP_FLASH -#define ONCHIP_FLASH_DEV &stm32_onchip_flash, +#define ONCHIP_FLASH_DEV &stm32_onchip_flash, #else -#define ONCHIP_FLASH_DEV +#define ONCHIP_FLASH_DEV #endif /* BSP_USING_ON_CHIP_FLASH */ /* flash device table */ diff --git a/bsp/stm32/stm32l475-atk-pandora/applications/main.c b/bsp/stm32/stm32l475-atk-pandora/applications/main.c index 97e08a7d42..dfad8c68c1 100644 --- a/bsp/stm32/stm32l475-atk-pandora/applications/main.c +++ b/bsp/stm32/stm32l475-atk-pandora/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l475-atk-pandora/applications/nrf24l01_init.c b/bsp/stm32/stm32l475-atk-pandora/applications/nrf24l01_init.c index 59c27ee558..e291154233 100644 --- a/bsp/stm32/stm32l475-atk-pandora/applications/nrf24l01_init.c +++ b/bsp/stm32/stm32l475-atk-pandora/applications/nrf24l01_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l475-atk-pandora/board/board.c b/bsp/stm32/stm32l475-atk-pandora/board/board.c index 3925f7924c..6e2be4bf42 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/board.c +++ b/bsp/stm32/stm32l475-atk-pandora/board/board.c @@ -18,11 +18,11 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /** Configure LSE Drive Capability + /** Configure LSE Drive Capability */ HAL_PWR_EnableBkUpAccess(); __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE |RCC_OSCILLATORTYPE_LSE; @@ -40,7 +40,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; @@ -72,7 +72,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) { diff --git a/bsp/stm32/stm32l475-atk-pandora/board/board.h b/bsp/stm32/stm32l475-atk-pandora/board/board.h index ee516b50db..a1029a3e99 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/board.h +++ b/bsp/stm32/stm32l475-atk-pandora/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_es8388.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_es8388.c index fe115eb593..5d9844c6bd 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_es8388.c +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_es8388.c @@ -1,6 +1,6 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team - * + * Copyright (c) 2006-2021, RT-Thread Development Team + * * SPDX-License-Identifier: Apache-2.0 * * Date Author Notes diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_es8388.h b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_es8388.h index 472c844fca..ac758960f8 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_es8388.h +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_es8388.h @@ -1,6 +1,6 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team - * + * Copyright (c) 2006-2021, RT-Thread Development Team + * * SPDX-License-Identifier: Apache-2.0 * * Date Author Notes diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_mic.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_mic.c index c4ea570dd7..ac604875f0 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_mic.c +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_mic.c @@ -1,6 +1,6 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team - * + * Copyright (c) 2006-2021, RT-Thread Development Team + * * SPDX-License-Identifier: Apache-2.0 * * Date Author Notes diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_sound.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_sound.c index bccf9c62db..b19d584d3d 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_sound.c +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_sound.c @@ -1,6 +1,6 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team - * + * Copyright (c) 2006-2021, RT-Thread Development Team + * * SPDX-License-Identifier: Apache-2.0 * * Date Author Notes diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_sound.h b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_sound.h index 4dc76631c7..d573b0dee5 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_sound.h +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_sound.h @@ -1,6 +1,6 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team - * + * Copyright (c) 2006-2021, RT-Thread Development Team + * * SPDX-License-Identifier: Apache-2.0 * * Date Author Notes diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.c index 65bdcd85f9..f80ca3a4b2 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.c +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -955,7 +955,7 @@ rt_err_t lcd_show_qrcode(rt_uint16_t x, rt_uint16_t y, rt_uint8_t version, rt_ui { enlargement_factor = enlargement; } - + /* malloc memory for quick display of qrcode */ qrcode_buf = rt_malloc(qrcode.size * 2 * enlargement_factor * enlargement_factor); if (qrcode_buf == RT_NULL) diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.h b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.h index ca4c28595f..394305012e 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.h +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.h @@ -1,12 +1,12 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2018-08-14 flybreak the first version - * 2018-09-18 balanceTWK add sleep mode function + * 2018-09-18 balanceTWK add sleep mode function */ #ifndef __DRV_LCD_H__ diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_qspi_flash.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_qspi_flash.c index aef2226239..f866d2741c 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_qspi_flash.c +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_qspi_flash.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-11-27 zylx first version */ - + #include #include #include @@ -63,7 +63,7 @@ void w25qxx_enter_qspi_mode(struct rt_qspi_device *device) static int rt_hw_qspi_flash_with_sfud_init(void) { stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, w25qxx_enter_qspi_mode, RT_NULL); - + /* init w25q128 */ if (RT_NULL == rt_sfud_flash_probe("W25Q128", "qspi10")) { diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/fal_cfg.h b/bsp/stm32/stm32l475-atk-pandora/board/ports/fal_cfg.h index a1575859ac..b96477b816 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -24,15 +24,15 @@ extern struct fal_flash_dev nor_flash0; /* ========================= Device Configuration ========================== */ #ifdef BSP_USING_ON_CHIP_FLASH -#define ONCHIP_FLASH_DEV &stm32_onchip_flash, +#define ONCHIP_FLASH_DEV &stm32_onchip_flash, #else -#define ONCHIP_FLASH_DEV +#define ONCHIP_FLASH_DEV #endif /* BSP_USING_ON_CHIP_FLASH */ #ifdef BSP_USING_QSPI_FLASH -#define SPI_FLASH_DEV &nor_flash0, +#define SPI_FLASH_DEV &nor_flash0, #else -#define SPI_FLASH_DEV +#define SPI_FLASH_DEV #endif /* BSP_USING_QSPI_FLASH */ /* flash device table */ @@ -55,7 +55,7 @@ extern struct fal_flash_dev nor_flash0; #ifdef BSP_USING_QSPI_FLASH #define SPI_FLASH_PARTITION {FAL_PART_MAGIC_WROD, "filesystem", "W25Q128", 9 * 1024 * 1024, 16 * 1024 * 1024, 0}, #else -#define SPI_FLASH_PARTITION +#define SPI_FLASH_PARTITION #endif /* partition table */ diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/sdcard_port.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/sdcard_port.c index e1af109455..9db3ec01f1 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/sdcard_port.c +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/sdcard_port.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/sensor_port.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/sensor_port.c index d253cc179e..fac1209a63 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/sensor_port.c +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/sensor_port.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l475-st-discovery/applications/main.c b/bsp/stm32/stm32l475-st-discovery/applications/main.c index 2c4ca35a6b..bddb8abe63 100644 --- a/bsp/stm32/stm32l475-st-discovery/applications/main.c +++ b/bsp/stm32/stm32l475-st-discovery/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l475-st-discovery/board/board.c b/bsp/stm32/stm32l475-st-discovery/board/board.c index bdd1307a91..cd2f9a5989 100644 --- a/bsp/stm32/stm32l475-st-discovery/board/board.c +++ b/bsp/stm32/stm32l475-st-discovery/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,7 +16,7 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; @@ -32,7 +32,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; @@ -51,7 +51,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) { diff --git a/bsp/stm32/stm32l475-st-discovery/board/board.h b/bsp/stm32/stm32l475-st-discovery/board/board.h index e49d71c68c..2b5f830eb9 100644 --- a/bsp/stm32/stm32l475-st-discovery/board/board.h +++ b/bsp/stm32/stm32l475-st-discovery/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l476-st-nucleo/applications/main.c b/bsp/stm32/stm32l476-st-nucleo/applications/main.c index e92ed8da71..b22a8b8e8d 100644 --- a/bsp/stm32/stm32l476-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32l476-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l476-st-nucleo/board/board.c b/bsp/stm32/stm32l476-st-nucleo/board/board.c index 88600d4b4f..0d279e679a 100644 --- a/bsp/stm32/stm32l476-st-nucleo/board/board.c +++ b/bsp/stm32/stm32l476-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l476-st-nucleo/board/board.h b/bsp/stm32/stm32l476-st-nucleo/board/board.h index b59fe1b3b6..c0b6a905ff 100644 --- a/bsp/stm32/stm32l476-st-nucleo/board/board.h +++ b/bsp/stm32/stm32l476-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l496-ali-developer/applications/main.c b/bsp/stm32/stm32l496-ali-developer/applications/main.c index d4926deb07..86d1cf72dd 100644 --- a/bsp/stm32/stm32l496-ali-developer/applications/main.c +++ b/bsp/stm32/stm32l496-ali-developer/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l496-ali-developer/board/board.c b/bsp/stm32/stm32l496-ali-developer/board/board.c index 4ed0e24cb6..9622e73038 100644 --- a/bsp/stm32/stm32l496-ali-developer/board/board.c +++ b/bsp/stm32/stm32l496-ali-developer/board/board.c @@ -16,11 +16,11 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /**Configure LSE Drive Capability + /**Configure LSE Drive Capability */ HAL_PWR_EnableBkUpAccess(); __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_LSE |RCC_OSCILLATORTYPE_MSI; @@ -40,7 +40,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; @@ -73,7 +73,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) { diff --git a/bsp/stm32/stm32l496-ali-developer/board/board.h b/bsp/stm32/stm32l496-ali-developer/board/board.h index 78cc07314b..6d99022522 100644 --- a/bsp/stm32/stm32l496-ali-developer/board/board.h +++ b/bsp/stm32/stm32l496-ali-developer/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l496-ali-developer/board/ports/drv_spi_lcd.c b/bsp/stm32/stm32l496-ali-developer/board/ports/drv_spi_lcd.c index e37a67f4a1..be6c2a5744 100644 --- a/bsp/stm32/stm32l496-ali-developer/board/ports/drv_spi_lcd.c +++ b/bsp/stm32/stm32l496-ali-developer/board/ports/drv_spi_lcd.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-11-27 zylx first version */ - + #include #include #include diff --git a/bsp/stm32/stm32l496-ali-developer/board/ports/fal_cfg.h b/bsp/stm32/stm32l496-ali-developer/board/ports/fal_cfg.h index d7a1db25e9..a0598e9d83 100644 --- a/bsp/stm32/stm32l496-ali-developer/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32l496-ali-developer/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l496-ali-developer/board/ports/sdcard_port.c b/bsp/stm32/stm32l496-ali-developer/board/ports/sdcard_port.c index 8a2c1cade7..6abc52c3ba 100644 --- a/bsp/stm32/stm32l496-ali-developer/board/ports/sdcard_port.c +++ b/bsp/stm32/stm32l496-ali-developer/board/ports/sdcard_port.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l4r5-st-nucleo/applications/main.c b/bsp/stm32/stm32l4r5-st-nucleo/applications/main.c index df59d02ff9..2dbb2b2c81 100644 --- a/bsp/stm32/stm32l4r5-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32l4r5-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -19,12 +19,12 @@ /* defined the LED3 pin: PB14 */ #define LED3_PIN GET_PIN(B, 14) -#define LED_RUN_PIN LED3_PIN +#define LED_RUN_PIN LED3_PIN int main(void) { int count = 1; - + rt_pin_mode(LED_RUN_PIN, PIN_MODE_OUTPUT); while (count++) diff --git a/bsp/stm32/stm32l4r5-st-nucleo/board/board.c b/bsp/stm32/stm32l4r5-st-nucleo/board/board.c index 7ab82ccd58..4b1fccdb4e 100644 --- a/bsp/stm32/stm32l4r5-st-nucleo/board/board.c +++ b/bsp/stm32/stm32l4r5-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,13 +16,13 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /** Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; @@ -38,7 +38,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32l4r5-st-nucleo/board/board.h b/bsp/stm32/stm32l4r5-st-nucleo/board/board.h index 095f503423..b90222c6e3 100644 --- a/bsp/stm32/stm32l4r5-st-nucleo/board/board.h +++ b/bsp/stm32/stm32l4r5-st-nucleo/board/board.h @@ -1,12 +1,12 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2018-11-5 SummerGift first version - * 2019-04-09 jhb + * 2019-04-09 jhb */ #ifndef __BOARD_H__ diff --git a/bsp/stm32/stm32l4r9-st-eval/applications/main.c b/bsp/stm32/stm32l4r9-st-eval/applications/main.c index ee74c2edd2..c53f70fb97 100644 --- a/bsp/stm32/stm32l4r9-st-eval/applications/main.c +++ b/bsp/stm32/stm32l4r9-st-eval/applications/main.c @@ -1,12 +1,12 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2018-11-06 SummerGift first version - * 2019-04-09 jhb + * 2019-04-09 jhb */ #include diff --git a/bsp/stm32/stm32l4r9-st-eval/board/board.c b/bsp/stm32/stm32l4r9-st-eval/board/board.c index af69f12729..cf4231f00c 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/board.c +++ b/bsp/stm32/stm32l4r9-st-eval/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,13 +16,13 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -37,7 +37,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; @@ -63,5 +63,5 @@ void SystemClock_Config(void) if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { Error_Handler(); - } + } } diff --git a/bsp/stm32/stm32l4r9-st-eval/board/board.h b/bsp/stm32/stm32l4r9-st-eval/board/board.h index f9f8adbcf8..7d85022bb4 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/board.h +++ b/bsp/stm32/stm32l4r9-st-eval/board/board.h @@ -1,12 +1,12 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2018-11-5 SummerGift first version - * 2019-04-09 jhb + * 2019-04-09 jhb */ #ifndef __BOARD_H__ diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_lcd_dsi.c b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_lcd_dsi.c index 8e926d7e2d..e00616eaac 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_lcd_dsi.c +++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_lcd_dsi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -706,17 +706,17 @@ void line() lcd = (struct drv_lcd_dsi_device *)rt_device_find("lcd_dsi"); rt_uint8_t *ptr = lcd->lcd_info.framebuffer; - /* red */ - for (unsigned long long i = LCD_DSI_BUF_SIZE/4/2; i parent, RTGRAPHIC_CTRL_RECT_UPDATE, RT_NULL); - - + /* red */ + for (unsigned long long i = LCD_DSI_BUF_SIZE/4/2; i parent, RTGRAPHIC_CTRL_RECT_UPDATE, RT_NULL); + + } MSH_CMD_EXPORT(line, line); diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_sram.c b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_sram.c index f77fa05aee..416e6863a7 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_sram.c +++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_sram.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch.c b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch.c index 314b1d707f..dc24066f51 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch.c +++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch_ft.c b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch_ft.c index 726be84e0d..0d3904444f 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch_ft.c +++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch_ft.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -119,7 +119,7 @@ static rt_err_t ft_read_point(touch_msg_t msg) { return RT_ERROR; } - + if (point_num == 0) { if (s_tp_down) @@ -131,7 +131,7 @@ static rt_err_t ft_read_point(touch_msg_t msg) msg->event = TOUCH_EVENT_NONE; return RT_ERROR; } - + ret = ft_read(ft_i2c_bus, 0x03, point, 6); if (ret < 0) { @@ -147,7 +147,7 @@ static rt_err_t ft_read_point(touch_msg_t msg) } msg->event = TOUCH_EVENT_DOWN; s_tp_down = 1; - + return RT_EOK; } diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/include/drv_touch.h b/bsp/stm32/stm32l4r9-st-eval/board/ports/include/drv_touch.h index 0e0cfae502..b70dd3eb25 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/ports/include/drv_touch.h +++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/include/drv_touch.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/include/lcd_port_dsi.h b/bsp/stm32/stm32l4r9-st-eval/board/ports/include/lcd_port_dsi.h index fbc56b4a44..4d602fc344 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/ports/include/lcd_port_dsi.h +++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/include/lcd_port_dsi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/include/sram_port.h b/bsp/stm32/stm32l4r9-st-eval/board/ports/include/sram_port.h index a5d89f1d80..f02a735dc4 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/ports/include/sram_port.h +++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/include/sram_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/taihu/applications/application.c b/bsp/taihu/applications/application.c index 6fa54e269f..24165d38a7 100644 --- a/bsp/taihu/applications/application.c +++ b/bsp/taihu/applications/application.c @@ -10,7 +10,7 @@ #include -#define THREAD_STACK_SIZE 1024 +#define THREAD_STACK_SIZE 1024 #if 0 struct rt_semaphore sem1, sem2; @@ -23,44 +23,44 @@ static rt_uint8_t thread2_stack[THREAD_STACK_SIZE]; static void thread1_entry(void* parameter) { - while (1) - { - rt_sem_release(&sem2); - rt_kprintf("thread1..: %s\n", rt_thread_self()->name); - rt_sem_take(&sem1, RT_WAITING_FOREVER); - rt_kprintf("get semaphore: %s!\n", rt_thread_self()->name); - } + while (1) + { + rt_sem_release(&sem2); + rt_kprintf("thread1..: %s\n", rt_thread_self()->name); + rt_sem_take(&sem1, RT_WAITING_FOREVER); + rt_kprintf("get semaphore: %s!\n", rt_thread_self()->name); + } } static void thread2_entry(void* parameter) { - while (1) - { - rt_sem_take(&sem2, RT_WAITING_FOREVER); - rt_kprintf("thread2--->: %s\n", rt_thread_self()->name); - rt_sem_release(&sem1); - } + while (1) + { + rt_sem_take(&sem2, RT_WAITING_FOREVER); + rt_kprintf("thread2--->: %s\n", rt_thread_self()->name); + rt_sem_release(&sem1); + } } /* user application */ int rt_application_init() { - rt_err_t result; + rt_err_t result; - rt_sem_init(&sem1, "s1", 0, RT_IPC_FLAG_FIFO); - rt_sem_init(&sem2, "s2", 0, RT_IPC_FLAG_FIFO); + rt_sem_init(&sem1, "s1", 0, RT_IPC_FLAG_FIFO); + rt_sem_init(&sem2, "s2", 0, RT_IPC_FLAG_FIFO); - result = rt_thread_init(&thread1, "t1", thread1_entry, RT_NULL, - &thread1_stack[0], sizeof(thread1_stack), 10, 10); - if (result == RT_EOK) - rt_thread_startup(&thread1); + result = rt_thread_init(&thread1, "t1", thread1_entry, RT_NULL, + &thread1_stack[0], sizeof(thread1_stack), 10, 10); + if (result == RT_EOK) + rt_thread_startup(&thread1); - result = rt_thread_init(&thread2, "t2", thread2_entry, RT_NULL, - &thread2_stack[0], sizeof(thread2_stack), 18, 10); - if (result == RT_EOK) - rt_thread_startup(&thread2); + result = rt_thread_init(&thread2, "t2", thread2_entry, RT_NULL, + &thread2_stack[0], sizeof(thread2_stack), 18, 10); + if (result == RT_EOK) + rt_thread_startup(&thread2); - return 0; + return 0; } #else static struct rt_thread thread1; @@ -70,27 +70,27 @@ rt_timer_t ttimer; static void thread1_entry(void* parameter) { - rt_uint32_t count = 0; - while (1) - { - rt_kprintf("%s: count = %d\n", rt_thread_self()->name, count ++); + rt_uint32_t count = 0; + while (1) + { + rt_kprintf("%s: count = %d\n", rt_thread_self()->name, count ++); - rt_thread_delay(10); - } + rt_thread_delay(10); + } } /* user application */ int rt_application_init() { - rt_err_t result; + rt_err_t result; - result = rt_thread_init(&thread1, "t1", thread1_entry, RT_NULL, - &thread1_stack[0], sizeof(thread1_stack), 10, 10); + result = rt_thread_init(&thread1, "t1", thread1_entry, RT_NULL, + &thread1_stack[0], sizeof(thread1_stack), 10, 10); - ttimer = &(thread1.thread_timer); - if (result == RT_EOK) - rt_thread_startup(&thread1); + ttimer = &(thread1.thread_timer); + if (result == RT_EOK) + rt_thread_startup(&thread1); - return 0; + return 0; } #endif diff --git a/bsp/taihu/applications/board.c b/bsp/taihu/applications/board.c index 03f5862c73..51b1658bd4 100644 --- a/bsp/taihu/applications/board.c +++ b/bsp/taihu/applications/board.c @@ -15,6 +15,6 @@ void rt_hw_board_init() { - rt_hw_serial_init(); - rt_console_set_device("uart1"); + rt_hw_serial_init(); + rt_console_set_device("uart1"); } diff --git a/bsp/taihu/applications/startup.c b/bsp/taihu/applications/startup.c index 897947dae8..95b5c59cb7 100644 --- a/bsp/taihu/applications/startup.c +++ b/bsp/taihu/applications/startup.c @@ -29,45 +29,45 @@ extern int __heap_end; */ void rtthread_startup(void) { - /* init hardware interrupt */ - rt_hw_interrupt_init(); + /* init hardware interrupt */ + rt_hw_interrupt_init(); - /* init board */ - rt_hw_board_init(); - rt_show_version(); + /* init board */ + rt_hw_board_init(); + rt_show_version(); - /* init tick */ - rt_system_tick_init(); + /* init tick */ + rt_system_tick_init(); - /* init timer system */ - rt_system_timer_init(); + /* init timer system */ + rt_system_timer_init(); - /* init memory system */ + /* init memory system */ #ifdef RT_USING_HEAP - rt_system_heap_init((void*)&__heap_start, (void*)&__heap_end); + rt_system_heap_init((void*)&__heap_start, (void*)&__heap_end); #endif - /* init scheduler system */ - rt_system_scheduler_init(); + /* init scheduler system */ + rt_system_scheduler_init(); - /* init application */ - rt_application_init(); + /* init application */ + rt_application_init(); #ifdef RT_USING_FINSH - /* init finsh */ - finsh_system_init(); - finsh_set_device("uart1"); + /* init finsh */ + finsh_system_init(); + finsh_set_device("uart1"); #endif - /* init soft timer thread */ - rt_system_timer_thread_init(); + /* init soft timer thread */ + rt_system_timer_thread_init(); - /* init idle thread */ - rt_thread_idle_init(); + /* init idle thread */ + rt_thread_idle_init(); - /* start scheduler */ - rt_system_scheduler_start(); + /* start scheduler */ + rt_system_scheduler_start(); - /* never reach here */ - return ; + /* never reach here */ + return ; } diff --git a/bsp/taihu/rtconfig.h b/bsp/taihu/rtconfig.h index 2437f6b2a3..161f74337a 100644 --- a/bsp/taihu/rtconfig.h +++ b/bsp/taihu/rtconfig.h @@ -3,19 +3,19 @@ #define __RTTHREAD_CFG_H__ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX*/ -#define RT_THREAD_PRIORITY_MAX 32 -#define IDLE_THREAD_STACK_SIZE 1024 +#define RT_THREAD_PRIORITY_MAX 32 +#define IDLE_THREAD_STACK_SIZE 1024 /* Tick per Second*/ -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 /* CPU Frequency 200MHz */ -#define RT_CPU_FREQ 200 +#define RT_CPU_FREQ 200 /* SECTION: RT_DEBUG */ /* open debug for system assert */ @@ -60,12 +60,12 @@ /* Using Device System*/ #define RT_USING_DEVICE #define RT_USING_UART1 -#define RT_UART_RX_BUFFER_SIZE 64 +#define RT_UART_RX_BUFFER_SIZE 64 /* SECTION: Console options */ #define RT_USING_CONSOLE /* the buffer size of console*/ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 /* SECTION: FinSH shell options */ /* Using FinSH as Shell*/ @@ -86,34 +86,34 @@ #define RT_LWIP_DNS /* the number of simulatenously active TCP connections*/ -#define RT_LWIP_TCP_PCB_NUM 5 +#define RT_LWIP_TCP_PCB_NUM 5 /* ip address of target*/ -#define RT_LWIP_IPADDR0 192 -#define RT_LWIP_IPADDR1 168 -#define RT_LWIP_IPADDR2 1 -#define RT_LWIP_IPADDR3 30 +#define RT_LWIP_IPADDR0 192 +#define RT_LWIP_IPADDR1 168 +#define RT_LWIP_IPADDR2 1 +#define RT_LWIP_IPADDR3 30 /* gateway address of target*/ -#define RT_LWIP_GWADDR0 192 -#define RT_LWIP_GWADDR1 168 -#define RT_LWIP_GWADDR2 1 -#define RT_LWIP_GWADDR3 1 +#define RT_LWIP_GWADDR0 192 +#define RT_LWIP_GWADDR1 168 +#define RT_LWIP_GWADDR2 1 +#define RT_LWIP_GWADDR3 1 /* mask address of target*/ -#define RT_LWIP_MSKADDR0 255 -#define RT_LWIP_MSKADDR1 255 -#define RT_LWIP_MSKADDR2 255 -#define RT_LWIP_MSKADDR3 0 +#define RT_LWIP_MSKADDR0 255 +#define RT_LWIP_MSKADDR1 255 +#define RT_LWIP_MSKADDR2 255 +#define RT_LWIP_MSKADDR3 0 /* tcp thread options */ -#define RT_LWIP_TCPTHREAD_PRIORITY 12 -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4 -#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4 +#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 /* ethernet if thread options */ -#define RT_LWIP_ETHTHREAD_PRIORITY 15 -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4 -#define RT_LWIP_ETHTHREAD_STACKSIZE 512 +#define RT_LWIP_ETHTHREAD_PRIORITY 15 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4 +#define RT_LWIP_ETHTHREAD_STACKSIZE 512 #endif diff --git a/bsp/tm4c129x/applications/board.c b/bsp/tm4c129x/applications/board.c index 84e6898652..202b9ec6f6 100644 --- a/bsp/tm4c129x/applications/board.c +++ b/bsp/tm4c129x/applications/board.c @@ -64,10 +64,10 @@ void rt_hw_board_init() int rt_hw_cpu_init(void) { MAP_IntMasterDisable(); - IntRegister(FAULT_HARD, HardFault_Handler); + IntRegister(FAULT_HARD, HardFault_Handler); IntRegister(FAULT_PENDSV, PendSV_Handler); IntRegister(FAULT_SYSTICK, SysTick_Handler); - + // Enable lazy stacking for interrupt handlers. This allows floating-point // instructions to be used within interrupt handlers, but at the expense of // extra stack usage. @@ -83,7 +83,7 @@ int rt_hw_cpu_init(void) MAP_SysTickDisable(); MAP_SysTickPeriodSet(SystemCoreClock/ RT_TICK_PER_SECOND - 1); MAP_SysTickIntEnable(); - MAP_SysTickEnable(); + MAP_SysTickEnable(); return 0; } diff --git a/bsp/tm4c129x/drivers/drv_eth.c b/bsp/tm4c129x/drivers/drv_eth.c index 15c469989d..12d9f88f3e 100644 --- a/bsp/tm4c129x/drivers/drv_eth.c +++ b/bsp/tm4c129x/drivers/drv_eth.c @@ -242,7 +242,7 @@ volatile uint32_t g_ui32AbnormalInts; ((uint32_t)(ptr) < 0x20070000)) -typedef struct +typedef struct { /* inherit from ethernet device */ struct eth_device parent; @@ -250,7 +250,7 @@ typedef struct /* for rx_thread async get pbuf */ rt_mailbox_t rx_pbuf_mb; } net_device; -typedef net_device* net_device_t; +typedef net_device* net_device_t; static char rx_pbuf_mb_pool[8*4]; static struct rt_mailbox eth_rx_pbuf_mb; @@ -566,7 +566,7 @@ tivaif_transmit(net_device_t dev, struct pbuf *p) /* Get our state data from the netif structure we were passed. */ //pIF = (tStellarisIF *)psNetif->state; pIF = dev->dma_if; - + /* Make sure that the transmit descriptors are not all in use */ pDesc = &(pIF->pTxDescList->pDescriptors[pIF->pTxDescList->ui32Write]); if(pDesc->pBuf) @@ -951,7 +951,7 @@ tivaif_process_phy_interrupt(net_device_t dev) */ ui16Val = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR1); - /* + /* * Dummy read PHY REG EPHY_BMSR, it will force update the EPHY_STS register */ EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_BMSR); @@ -1166,38 +1166,38 @@ void lwIPEthernetIntHandler(void) } -// OUI:00-12-37 (hex) Texas Instruments, only for test +// OUI:00-12-37 (hex) Texas Instruments, only for test static int tiva_eth_mac_addr_init(void) { - int retVal =0; + int retVal =0; uint32_t ulUser[2]; uint8_t mac_addr[6]; - + MAP_FlashUserGet(&ulUser[0], &ulUser[1]); if((ulUser[0] == 0xffffffff) || (ulUser[1] == 0xffffffff)) { rt_kprintf("Fail to get mac address from eeprom.\n"); rt_kprintf("Using default mac address\n"); - // OUI:00-12-37 (hex) Texas Instruments, only for test - // Configure the hardware MAC address + // OUI:00-12-37 (hex) Texas Instruments, only for test + // Configure the hardware MAC address ulUser[0] = 0x00371200; ulUser[1] = 0x00563412; - //FlashUserSet(ulUser0, ulUser1); + //FlashUserSet(ulUser0, ulUser1); retVal =-1; } - - + + //Convert the 24/24 split MAC address from NV ram into a 32/16 split MAC //address needed to program the hardware registers, then program the MAC //address into the Ethernet Controller registers. - + mac_addr[0] = ((ulUser[0] >> 0) & 0xff); mac_addr[1] = ((ulUser[0] >> 8) & 0xff); mac_addr[2] = ((ulUser[0] >> 16) & 0xff); mac_addr[3] = ((ulUser[1] >> 0) & 0xff); mac_addr[4] = ((ulUser[1] >> 8) & 0xff); mac_addr[5] = ((ulUser[1] >> 16) & 0xff); - + // // Program the hardware with its MAC address (for filtering). // @@ -1215,7 +1215,7 @@ static int tiva_eth_mac_addr_init(void) MAP_GPIOPinConfigure(GPIO_PF4_EN0LED1); GPIOPinTypeEthernetLED(GPIO_PORTF_BASE, GPIO_PIN_0); GPIOPinTypeEthernetLED(GPIO_PORTF_BASE, GPIO_PIN_4); - + // // Enable the ethernet peripheral. // @@ -1284,7 +1284,7 @@ static int tiva_eth_mac_addr_init(void) EMAC_MODE_TX_STORE_FORWARD | EMAC_MODE_TX_THRESHOLD_64_BYTES | EMAC_MODE_RX_THRESHOLD_64_BYTES), 0); - + EMACIntRegister(EMAC0_BASE, lwIPEthernetIntHandler); } @@ -1293,7 +1293,7 @@ static rt_err_t eth_dev_init(rt_device_t device) { net_device_t net_dev = (net_device_t)device; struct netif *psNetif = (net_dev->parent.netif); - + LWIP_ASSERT("psNetif != NULL", (psNetif != NULL)); #if LWIP_NETIF_HOSTNAME @@ -1307,7 +1307,7 @@ static rt_err_t eth_dev_init(rt_device_t device) * of bits per second. */ //NETIF_INIT_SNMP(psNetif, snmp_ifType_ethernet_csmacd, 1000000); - + net_dev->dma_if = &g_StellarisIFData; /* Remember our MAC address. */ @@ -1325,9 +1325,9 @@ static rt_err_t eth_dev_control(rt_device_t dev, int cmd, void *args) { case NIOCTL_GADDR: /* get mac address */ - if(args) + if(args) MAP_EMACAddrGet(EMAC0_BASE, 0, (uint8_t*)args); - else + else return -RT_ERROR; break; @@ -1375,7 +1375,7 @@ static struct pbuf* eth_dev_rx(rt_device_t dev) rt_uint32_t temp =0; net_device_t net_dev = (net_device_t)dev; result = rt_mb_recv(net_dev->rx_pbuf_mb, (rt_ubase_t *)&temp, RT_WAITING_NO); - + return (result == RT_EOK)? (struct pbuf*)temp : RT_NULL; } @@ -1384,7 +1384,7 @@ int rt_hw_tiva_eth_init(void) rt_err_t result; /* Clock GPIO and etc */ - tiva_eth_lowlevel_init(); + tiva_eth_lowlevel_init(); tiva_eth_mac_addr_init(); /* init rt-thread device interface */ @@ -1396,14 +1396,14 @@ int rt_hw_tiva_eth_init(void) eth_dev->parent.parent.control = eth_dev_control; eth_dev->parent.eth_rx = eth_dev_rx; eth_dev->parent.eth_tx = eth_dev_tx; - + result = rt_mb_init(ð_rx_pbuf_mb, "epbuf", &rx_pbuf_mb_pool[0], sizeof(rx_pbuf_mb_pool)/4, RT_IPC_FLAG_FIFO); RT_ASSERT(result == RT_EOK); eth_dev->rx_pbuf_mb = ð_rx_pbuf_mb; - - + + result = eth_device_init(&(eth_dev->parent), "e0"); return result; } @@ -1429,13 +1429,13 @@ void PHY_Write(uint8_t addr , uint16_t data) } FINSH_FUNCTION_EXPORT(PHY_Write, (add, data)); -void PHY_SetAdd(uint8_t addr0, uint8_t addr1, uint8_t addr2, +void PHY_SetAdd(uint8_t addr0, uint8_t addr1, uint8_t addr2, uint8_t addr3, uint8_t addr4, uint8_t addr5) { uint32_t ulUser[2]; ulUser[0] = (((addr2<<8)|addr1)<<8)|addr0; ulUser[1] = (((addr5<<8)|addr4)<<8)|addr3; - + MAP_FlashUserSet(ulUser[0], ulUser[1]); MAP_FlashUserSave(); rt_kprintf("Save to EEPROM. please reboot."); diff --git a/bsp/tm4c129x/drivers/drv_eth.h b/bsp/tm4c129x/drivers/drv_eth.h index 3c2fefefbf..2fa81e4f04 100644 --- a/bsp/tm4c129x/drivers/drv_eth.h +++ b/bsp/tm4c129x/drivers/drv_eth.h @@ -7,7 +7,7 @@ * Date Author Notes * 2014-07-25 ArdaFu Port to TM4C129X */ - + #ifndef __TIVA_ETH_H__ #define __TIVA_ETH_H__ diff --git a/bsp/tm4c129x/drivers/drv_uart.c b/bsp/tm4c129x/drivers/drv_uart.c index 4b7ca48e6e..d1b26f3002 100644 --- a/bsp/tm4c129x/drivers/drv_uart.c +++ b/bsp/tm4c129x/drivers/drv_uart.c @@ -30,75 +30,75 @@ typedef struct hw_uart_device #define mUartGetHwPtr(serial) ((hw_uart_t*)(serial->parent.user_data)) static rt_err_t hw_configure(struct rt_serial_device *serial, struct serial_configure *cfg) -{ - uint32_t config = 0; - hw_uart_t* uart; +{ + uint32_t config = 0; + hw_uart_t* uart; RT_ASSERT(serial != RT_NULL); uart = mUartGetHwPtr(serial); - MAP_UARTDisable(uart->hw_base); - // build UART Configuration parameter structure + MAP_UARTDisable(uart->hw_base); + // build UART Configuration parameter structure switch(cfg->data_bits) - { - case DATA_BITS_9: - // enable 9bit address mode and set DATA_BIT_8 - MAP_UART9BitEnable(uart->hw_base); - case DATA_BITS_8: - config |= UART_CONFIG_WLEN_8; - break; - case DATA_BITS_7: - config |= UART_CONFIG_WLEN_7; - break; - case DATA_BITS_6: - config |= UART_CONFIG_WLEN_6; - break; - case DATA_BITS_5: - config |= UART_CONFIG_WLEN_5; - break; - default: - RT_ASSERT(0); - break; - } - switch(cfg->parity) - { - case PARITY_ODD: - config |= UART_CONFIG_PAR_ODD; - break; - case PARITY_EVEN: - config |= UART_CONFIG_PAR_EVEN; - break; - case PARITY_NONE: - config |= UART_CONFIG_PAR_NONE; - break; - default: - RT_ASSERT(0); - break; - } - switch(cfg->stop_bits) - { - case STOP_BITS_1: - config |= UART_CONFIG_STOP_ONE; - break; - case STOP_BITS_2: - config |= UART_CONFIG_STOP_TWO; - break; - default: - RT_ASSERT(0); - break; - } - - // Initialize UART0 peripheral with given to corresponding parameter + { + case DATA_BITS_9: + // enable 9bit address mode and set DATA_BIT_8 + MAP_UART9BitEnable(uart->hw_base); + case DATA_BITS_8: + config |= UART_CONFIG_WLEN_8; + break; + case DATA_BITS_7: + config |= UART_CONFIG_WLEN_7; + break; + case DATA_BITS_6: + config |= UART_CONFIG_WLEN_6; + break; + case DATA_BITS_5: + config |= UART_CONFIG_WLEN_5; + break; + default: + RT_ASSERT(0); + break; + } + switch(cfg->parity) + { + case PARITY_ODD: + config |= UART_CONFIG_PAR_ODD; + break; + case PARITY_EVEN: + config |= UART_CONFIG_PAR_EVEN; + break; + case PARITY_NONE: + config |= UART_CONFIG_PAR_NONE; + break; + default: + RT_ASSERT(0); + break; + } + switch(cfg->stop_bits) + { + case STOP_BITS_1: + config |= UART_CONFIG_STOP_ONE; + break; + case STOP_BITS_2: + config |= UART_CONFIG_STOP_TWO; + break; + default: + RT_ASSERT(0); + break; + } + + // Initialize UART0 peripheral with given to corresponding parameter MAP_UARTConfigSetExpClk(uart->hw_base, SystemCoreClock, cfg->baud_rate, config); - MAP_UARTFIFOEnable(uart->hw_base); + MAP_UARTFIFOEnable(uart->hw_base); - // Enable the UART. - MAP_UARTEnable(uart->hw_base); + // Enable the UART. + MAP_UARTEnable(uart->hw_base); return RT_EOK; } static rt_err_t hw_control(struct rt_serial_device *serial, int cmd, void *arg) { - hw_uart_t* uart; + hw_uart_t* uart; RT_ASSERT(serial != RT_NULL); uart = mUartGetHwPtr(serial); @@ -119,21 +119,21 @@ static rt_err_t hw_control(struct rt_serial_device *serial, int cmd, void *arg) static int hw_putc(struct rt_serial_device *serial, char c) { - hw_uart_t* uart; + hw_uart_t* uart; RT_ASSERT(serial != RT_NULL); uart = mUartGetHwPtr(serial); - + MAP_UARTCharPut(uart->hw_base, *((uint8_t *)&c)); return 1; } static int hw_getc(struct rt_serial_device *serial) { - hw_uart_t* uart; + hw_uart_t* uart; RT_ASSERT(serial != RT_NULL); uart = mUartGetHwPtr(serial); - - return MAP_UARTCharGetNonBlocking(uart->hw_base); + + return MAP_UARTCharGetNonBlocking(uart->hw_base); } static const struct rt_uart_ops hw_uart_ops = @@ -154,7 +154,7 @@ hw_uart_t uart0 = void UART0_IRQHandler(void) { - uint32_t intsrc; + uint32_t intsrc; hw_uart_t *uart = &uart0; /* enter interrupt */ @@ -169,7 +169,7 @@ void UART0_IRQHandler(void) MAP_UARTIntClear(uart->hw_base, intsrc); rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND); } - + /* leave interrupt */ rt_interrupt_leave(); } @@ -187,7 +187,7 @@ int rt_hw_uart_init(void) config.stop_bits = STOP_BITS_1; config.invert = NRZ_NORMAL; config.bufsz = RT_SERIAL_RB_BUFSZ; - + #ifdef RT_USING_UART0 uart = &uart0; serial0.ops = &hw_uart_ops; @@ -196,7 +196,7 @@ int rt_hw_uart_init(void) MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); MAP_GPIOPinConfigure(GPIO_PA0_U0RX); MAP_GPIOPinConfigure(GPIO_PA1_U0TX); - + MAP_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); @@ -204,15 +204,15 @@ int rt_hw_uart_init(void) //IntPrioritySet(INT_UART0, ((0x01 << 5) | 0x01)); /* Enable Interrupt for UART channel */ - UARTIntRegister(uart->hw_base, UART0_IRQHandler); - MAP_IntEnable(INT_UART0); - MAP_UARTEnable(uart->hw_base); + UARTIntRegister(uart->hw_base, UART0_IRQHandler); + MAP_IntEnable(INT_UART0); + MAP_UARTEnable(uart->hw_base); /* register UART0 device */ rt_hw_serial_register(&serial0, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif - return 0; + return 0; } INIT_BOARD_EXPORT(rt_hw_uart_init); diff --git a/bsp/tms320f28379d/applications/application.c b/bsp/tms320f28379d/applications/application.c index 5c7b769a4d..4a155ea5eb 100644 --- a/bsp/tms320f28379d/applications/application.c +++ b/bsp/tms320f28379d/applications/application.c @@ -1,12 +1,12 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2009-01-05 Bernard the first version - * 2014-04-27 Bernard make code cleanup. + * 2014-04-27 Bernard make code cleanup. */ #include diff --git a/bsp/tms320f28379d/applications/startup.c b/bsp/tms320f28379d/applications/startup.c index 301e63a00a..0aaf0094d6 100644 --- a/bsp/tms320f28379d/applications/startup.c +++ b/bsp/tms320f28379d/applications/startup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/tms320f28379d/drivers/board.c b/bsp/tms320f28379d/drivers/board.c index b83cb7a966..7124f5d715 100644 --- a/bsp/tms320f28379d/drivers/board.c +++ b/bsp/tms320f28379d/drivers/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/tms320f28379d/drivers/board.h b/bsp/tms320f28379d/drivers/board.h index 9f2a057850..5f68b99e88 100644 --- a/bsp/tms320f28379d/drivers/board.h +++ b/bsp/tms320f28379d/drivers/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/tms320f28379d/drivers/drv_sci.c b/bsp/tms320f28379d/drivers/drv_sci.c index b9f23acc48..f1323b4616 100644 --- a/bsp/tms320f28379d/drivers/drv_sci.c +++ b/bsp/tms320f28379d/drivers/drv_sci.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/tms320f28379d/drivers/drv_sci.h b/bsp/tms320f28379d/drivers/drv_sci.h index 60fb12bd9b..ee696570eb 100644 --- a/bsp/tms320f28379d/drivers/drv_sci.h +++ b/bsp/tms320f28379d/drivers/drv_sci.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/tms320f28379d/rtconfig_project.h b/bsp/tms320f28379d/rtconfig_project.h index df4eb0c1cd..2de98b7f7c 100644 --- a/bsp/tms320f28379d/rtconfig_project.h +++ b/bsp/tms320f28379d/rtconfig_project.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/upd70f3454/applications/startup.c b/bsp/upd70f3454/applications/startup.c index c3fefc1ba9..2975a440d6 100644 --- a/bsp/upd70f3454/applications/startup.c +++ b/bsp/upd70f3454/applications/startup.c @@ -48,10 +48,10 @@ void rtthread_startup(void) /* init tick */ rt_system_tick_init(); - + /* init kernel object */ rt_system_object_init(); - + /* init timer system */ rt_system_timer_init(); @@ -93,7 +93,7 @@ int main(void) /* init system setting */ TAB0_Start(); - + /* startup RT-Thread RTOS */ rtthread_startup(); diff --git a/bsp/upd70f3454/drivers/board.h b/bsp/upd70f3454/drivers/board.h index 27ec7cacc4..51fbf2feee 100644 --- a/bsp/upd70f3454/drivers/board.h +++ b/bsp/upd70f3454/drivers/board.h @@ -26,7 +26,7 @@ #define UP_KEY 0x1b #define DOWN_KEY 0x17 #define LEFT_KEY 0x0f -#define RIGHT_KEY 0x1e +#define RIGHT_KEY 0x1e void rt_hw_board_init(void); rt_uint8_t get_key(void); diff --git a/bsp/upd70f3454/drivers/uart.c b/bsp/upd70f3454/drivers/uart.c index aa5930bf10..d452092497 100644 --- a/bsp/upd70f3454/drivers/uart.c +++ b/bsp/upd70f3454/drivers/uart.c @@ -192,7 +192,7 @@ static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer while (UA1TSF == 1U) ; UA1TX = *ptr; - + ptr ++; size --; } diff --git a/bsp/upd70f3454/rtconfig.h b/bsp/upd70f3454/rtconfig.h index 894bc5beff..a9a92e709e 100644 --- a/bsp/upd70f3454/rtconfig.h +++ b/bsp/upd70f3454/rtconfig.h @@ -3,16 +3,16 @@ #define __RTTHREAD_CFG_H__ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 32 +#define RT_THREAD_PRIORITY_MAX 32 /* Tick per Second */ -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 /* SECTION: RT_DEBUG */ /* Thread Debug */ @@ -27,9 +27,9 @@ /* Using Software Timer */ /* #define RT_USING_TIMER_SOFT */ -#define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 512 -#define RT_TIMER_TICK_PER_SECOND 10 +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_TICK_PER_SECOND 10 /* SECTION: IPC */ /* Using Semaphore */ @@ -62,12 +62,12 @@ #define RT_USING_DEVICE /* RT_USING_UART */ #define RT_USING_UART0 -#define RT_UART_RX_BUFFER_SIZE 64 +#define RT_UART_RX_BUFFER_SIZE 64 /* SECTION: Console options */ #define RT_USING_CONSOLE /* the buffer size of console */ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 /* SECTION: finsh, a C-Express shell */ /* Using FinSH as Shell*/ @@ -81,10 +81,10 @@ ///#define RT_USING_DFS_ELMFAT /* the max number of mounted filesystem */ -///#define DFS_FILESYSTEMS_MAX 2 -/* the max number of opened files */ -///#define DFS_FD_MAX 4 -/* the max number of cached sector */ -///#define DFS_CACHE_MAX_NUM 4 +///#define DFS_FILESYSTEMS_MAX 2 +/* the max number of opened files */ +///#define DFS_FD_MAX 4 +/* the max number of cached sector */ +///#define DFS_CACHE_MAX_NUM 4 #endif diff --git a/bsp/w60x/drivers/drv_soft_i2c.c b/bsp/w60x/drivers/drv_soft_i2c.c index b2e0b5b508..1e44d52662 100644 --- a/bsp/w60x/drivers/drv_soft_i2c.c +++ b/bsp/w60x/drivers/drv_soft_i2c.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -198,8 +198,8 @@ int rt_soft_i2c_init(void) w60x_i2c_bus_unlock(&soft_i2c_config[i]); LOG_D("software simulation %s init done, pin scl: %d, pin sda %d", - soft_i2c_config[i].bus_name, - soft_i2c_config[i].scl, + soft_i2c_config[i].bus_name, + soft_i2c_config[i].scl, soft_i2c_config[i].sda); } diff --git a/bsp/w60x/drivers/drv_soft_i2c.h b/bsp/w60x/drivers/drv_soft_i2c.h index ee50abea71..9901a5958f 100644 --- a/bsp/w60x/drivers/drv_soft_i2c.h +++ b/bsp/w60x/drivers/drv_soft_i2c.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/w60x/drivers/pin_config.h b/bsp/w60x/drivers/pin_config.h index cf1eb774c3..c704fafb22 100644 --- a/bsp/w60x/drivers/pin_config.h +++ b/bsp/w60x/drivers/pin_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/w60x/oneshot/oneshot.c b/bsp/w60x/oneshot/oneshot.c index ee60a0b907..21beeeb90d 100644 --- a/bsp/w60x/oneshot/oneshot.c +++ b/bsp/w60x/oneshot/oneshot.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,37 +16,37 @@ /* start oneshot */ int wm_oneshot_start(WM_ONESHOT_MODE mode, wm_oneshot_callback callback) { - tls_wifi_oneshot_callback_register(callback); - if(mode == WM_UDP) - { - tls_wifi_set_oneshot_config_mode(0); - } + tls_wifi_oneshot_callback_register(callback); + if(mode == WM_UDP) + { + tls_wifi_set_oneshot_config_mode(0); + } else if (mode == WM_APSOCKET) { tls_wifi_set_oneshot_config_mode(1); - } - else if(mode == WM_APWEB) - { - tls_wifi_set_oneshot_config_mode(2); - } - else - { - return -1; - } - tls_wifi_set_oneshot_flag(1); - return 0; + } + else if(mode == WM_APWEB) + { + tls_wifi_set_oneshot_config_mode(2); + } + else + { + return -1; + } + tls_wifi_set_oneshot_flag(1); + return 0; } /* stop oneshot */ int wm_oneshot_stop(void) { - tls_wifi_oneshot_callback_delete(); - tls_wifi_set_oneshot_flag(0); - return 0; + tls_wifi_oneshot_callback_delete(); + tls_wifi_set_oneshot_flag(0); + return 0; } /* get status */ int wm_oneshot_get(void) { - return tls_wifi_get_oneshot_flag(); + return tls_wifi_get_oneshot_flag(); } diff --git a/bsp/w60x/oneshot/oneshot.h b/bsp/w60x/oneshot/oneshot.h index f9bd638c1a..26f25d0735 100644 --- a/bsp/w60x/oneshot/oneshot.h +++ b/bsp/w60x/oneshot/oneshot.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,9 +12,9 @@ #define DRV_ONESHOT_H__ typedef enum{ - WM_UDP, + WM_UDP, WM_APSOCKET, - WM_APWEB + WM_APWEB }WM_ONESHOT_MODE; diff --git a/bsp/w60x/oneshot/oneshot_demo.c b/bsp/w60x/oneshot/oneshot_demo.c index 7012b5af5b..b40e121f16 100644 --- a/bsp/w60x/oneshot/oneshot_demo.c +++ b/bsp/w60x/oneshot/oneshot_demo.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/wh44b0/application.c b/bsp/wh44b0/application.c index 3c74a8df9e..42c9b56fa8 100644 --- a/bsp/wh44b0/application.c +++ b/bsp/wh44b0/application.c @@ -20,7 +20,7 @@ /* application start function */ int rt_application_init() { - return 0; /* empty */ + return 0; /* empty */ } /** @} */ diff --git a/bsp/wh44b0/board.c b/bsp/wh44b0/board.c index e1fc3e31ee..628f85abd8 100644 --- a/bsp/wh44b0/board.c +++ b/bsp/wh44b0/board.c @@ -32,82 +32,82 @@ extern void rt_serial_putc(const char ch); void rt_timer_handler(int vector) { #ifdef BOARD_DEBUG - rt_kprintf("timer handler, increase a tick\n"); + rt_kprintf("timer handler, increase a tick\n"); #endif - rt_tick_increase(); + rt_tick_increase(); } void rt_hw_port_init(void) { - /* PORT A GROUP */ - /* BIT 9 8 7 6 5 4 3 2 1 0 */ - /* A24 A23 A22 A21 A20 A19 A18 A17 A16 A0 */ - /* 1 1 1 1 1 1 1 1 1 1 */ - PCONA = 0x1ff; - PDATA = 0x2db; - - /* PORT B GROUP */ - /* BIT 10 9 8 7 6 5 4 3 2 1 0 */ - /* /CS5 /CS4 /CS3 /CS2 /CS1 nWBE3 nWBE2 /SRAS /SCAS SCLS SCKE */ - /* NC NC RTL8019 USBD12 NV_Flash NC NC Sdram Sdram Sdram Sdram*/ - /* 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 1 */ - PDATB = 0x4f; - PCONB = 0x7cf; - - /* PORT C GROUP */ - /* BUSWIDTH=16 */ - /* PC15 14 13 12 11 10 9 8 */ - /* o o RXD1 TXD1 o o o o */ - /* NC NC Uart1 Uart1 NC NC NC NC */ - /* 01 01 11 11 01 01 01 00 */ - - /* PC7 6 5 4 3 2 1 0 */ - /* o o o o o o o o */ - /* NC NC NC NC NFALE NFCLE NFCE NFRB*/ - /* 01 01 01 01 01 01 01 00 */ - PDATC = 0x3001; /* All IO is low */ - PCONC = 0x5f555555; - PUPC = 0x3000; /* PULL UP RESISTOR should be enabled to I/O */ - - /* PORT D GROUP */ - /* PORT D GROUP(I/O OR LCD) */ - /* BIT7 6 5 4 3 2 1 0 */ - /* VF VM VLINE VCLK VD3 VD2 VD1 VD0 */ - /* 01 01 01 01 01 01 01 01 */ - PDATD= 0x0; - PCOND= 0xaaaa; - PUPD = 0x00; /* These pins must be set only after CPU's internal LCD controller is enable */ - - /* PORT E GROUP */ - /* Bit 8 7 6 5 4 3 2 1 0 */ - /* ENDLAN LED3 LED2 LED1 LED0 BEEP RXD0 TXD0 CLKOUT */ - /* 00 01 01 01 01 01 10 10 11 */ - PCONE = 0x556b; /*0->input, 1 2->TXD0 RXD0, 3 4->input, 5->led, 6->buzzer, 7->led, 8->CODECLK */ - PDATE = 0x57; - PUPE = 0x006; /* disable all pull-up */ - - /* PORT F GROUP */ - /* Bit8 7 6 5 4 3 2 1 0 */ - /* IISCLK IISDI IISDO IISLRCK Input Input Input IICSDA IICSCL */ - /* 100 010 010 001 00 01 01 10 10 */ - PDATF = 0x2f; - PCONF = 0x24900a; - PUPF = 0x1d3; - - /* PORT G GROUP */ - /* BIT7 6 5 4 3 2 1 0 */ - /* INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 */ - /* S3 S4 S5 S6 NIC EXT IDE USB */ - /* 11 11 11 11 11 11 11 11 */ - PDATG = 0xfc; - PCONG = 0x000f; /* eint1 is eth interrupt in WH44B0 */ - PUPG = 0x00; /* should be enabled */ - - SPUCR=0x7; /* D15-D0 pull-up disable */ - - /* all external interrupts are triggered by low level */ - EXTINT=0x0; + /* PORT A GROUP */ + /* BIT 9 8 7 6 5 4 3 2 1 0 */ + /* A24 A23 A22 A21 A20 A19 A18 A17 A16 A0 */ + /* 1 1 1 1 1 1 1 1 1 1 */ + PCONA = 0x1ff; + PDATA = 0x2db; + + /* PORT B GROUP */ + /* BIT 10 9 8 7 6 5 4 3 2 1 0 */ + /* /CS5 /CS4 /CS3 /CS2 /CS1 nWBE3 nWBE2 /SRAS /SCAS SCLS SCKE */ + /* NC NC RTL8019 USBD12 NV_Flash NC NC Sdram Sdram Sdram Sdram*/ + /* 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 1 */ + PDATB = 0x4f; + PCONB = 0x7cf; + + /* PORT C GROUP */ + /* BUSWIDTH=16 */ + /* PC15 14 13 12 11 10 9 8 */ + /* o o RXD1 TXD1 o o o o */ + /* NC NC Uart1 Uart1 NC NC NC NC */ + /* 01 01 11 11 01 01 01 00 */ + + /* PC7 6 5 4 3 2 1 0 */ + /* o o o o o o o o */ + /* NC NC NC NC NFALE NFCLE NFCE NFRB*/ + /* 01 01 01 01 01 01 01 00 */ + PDATC = 0x3001; /* All IO is low */ + PCONC = 0x5f555555; + PUPC = 0x3000; /* PULL UP RESISTOR should be enabled to I/O */ + + /* PORT D GROUP */ + /* PORT D GROUP(I/O OR LCD) */ + /* BIT7 6 5 4 3 2 1 0 */ + /* VF VM VLINE VCLK VD3 VD2 VD1 VD0 */ + /* 01 01 01 01 01 01 01 01 */ + PDATD= 0x0; + PCOND= 0xaaaa; + PUPD = 0x00; /* These pins must be set only after CPU's internal LCD controller is enable */ + + /* PORT E GROUP */ + /* Bit 8 7 6 5 4 3 2 1 0 */ + /* ENDLAN LED3 LED2 LED1 LED0 BEEP RXD0 TXD0 CLKOUT */ + /* 00 01 01 01 01 01 10 10 11 */ + PCONE = 0x556b; /*0->input, 1 2->TXD0 RXD0, 3 4->input, 5->led, 6->buzzer, 7->led, 8->CODECLK */ + PDATE = 0x57; + PUPE = 0x006; /* disable all pull-up */ + + /* PORT F GROUP */ + /* Bit8 7 6 5 4 3 2 1 0 */ + /* IISCLK IISDI IISDO IISLRCK Input Input Input IICSDA IICSCL */ + /* 100 010 010 001 00 01 01 10 10 */ + PDATF = 0x2f; + PCONF = 0x24900a; + PUPF = 0x1d3; + + /* PORT G GROUP */ + /* BIT7 6 5 4 3 2 1 0 */ + /* INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 */ + /* S3 S4 S5 S6 NIC EXT IDE USB */ + /* 11 11 11 11 11 11 11 11 */ + PDATG = 0xfc; + PCONG = 0x000f; /* eint1 is eth interrupt in WH44B0 */ + PUPG = 0x00; /* should be enabled */ + + SPUCR=0x7; /* D15-D0 pull-up disable */ + + /* all external interrupts are triggered by low level */ + EXTINT=0x0; } /** @@ -115,90 +115,90 @@ void rt_hw_port_init(void) */ void rt_hw_board_init() { - /* init port setting */ - rt_hw_port_init(); + /* init port setting */ + rt_hw_port_init(); - /* set timer0 register */ - /* stop timer */ - TCON &= ~(0x00000001); + /* set timer0 register */ + /* stop timer */ + TCON &= ~(0x00000001); - /* dead zone = 0, pre = 150 */ - TCFG0 = 0x00000095; - /* all are interrupt mode */ - TCFG1 = 0x00000003; + /* dead zone = 0, pre = 150 */ + TCFG0 = 0x00000095; + /* all are interrupt mode */ + TCFG1 = 0x00000003; - TCNTB0 = DATA_COUNT; - TCMPB0 = 0; + TCNTB0 = DATA_COUNT; + TCMPB0 = 0; - /* manual update */ - TCON |= 0x00000002; + /* manual update */ + TCON |= 0x00000002; - /* auto reload on,output inverter off */ - TCON &= ~(0x0000000f); - TCON |= (0x00000008); + /* auto reload on,output inverter off */ + TCON &= ~(0x0000000f); + TCON |= (0x00000008); - /* install timer handler */ - rt_hw_interrupt_install(INT_TIMER0, rt_timer_handler, RT_NULL); - rt_hw_interrupt_umask(INT_TIMER0); + /* install timer handler */ + rt_hw_interrupt_install(INT_TIMER0, rt_timer_handler, RT_NULL); + rt_hw_interrupt_umask(INT_TIMER0); - /* start timer */ - TCON |=(0x00000001); + /* start timer */ + TCON |=(0x00000001); } void rt_hw_led_set(rt_uint32_t led) { - if((led & 0x01)==0x01) /* D1 */ - PDATC = PDATC | (1<<1) ; - else - PDATC = PDATC & (~(1<<1)) ; - - if((led & 0x02)==0x02) /* D2 */ - PDATC = PDATC | (1<<2) ; - else - PDATC = PDATC & (~(1<<2)) ; - - if((led & 0x04)==0x04) /* D3 */ - PDATC = PDATC | (1<<3) ; - else - PDATC = PDATC & (~(1<<3)) ; + if((led & 0x01)==0x01) /* D1 */ + PDATC = PDATC | (1<<1) ; + else + PDATC = PDATC & (~(1<<1)) ; + + if((led & 0x02)==0x02) /* D2 */ + PDATC = PDATC | (1<<2) ; + else + PDATC = PDATC & (~(1<<2)) ; + + if((led & 0x04)==0x04) /* D3 */ + PDATC = PDATC | (1<<3) ; + else + PDATC = PDATC & (~(1<<3)) ; } /* led loop */ void rt_hw_led_flash(void) { - register int i; - - rt_hw_led_set(0x01); - for ( i = 0; i < 2000000; i++); - - rt_hw_led_set(0x02); - for ( i = 0; i < 2000000; i++); - - rt_hw_led_set(0x04); - for ( i = 0; i < 2000000; i++); + register int i; + + rt_hw_led_set(0x01); + for ( i = 0; i < 2000000; i++); + + rt_hw_led_set(0x02); + for ( i = 0; i < 2000000; i++); + + rt_hw_led_set(0x04); + for ( i = 0; i < 2000000; i++); } #ifdef RT_USING_FINSH extern void finsh_notify(void); void rt_serial_isr(int vector) { - finsh_notify(); + finsh_notify(); } void rt_hw_finsh_init() { - /* install UART isr */ - rt_hw_interrupt_install(INT_URXD0, rt_serial_isr, RT_NULL); - rt_hw_interrupt_umask(INT_URXD0); + /* install UART isr */ + rt_hw_interrupt_install(INT_URXD0, rt_serial_isr, RT_NULL); + rt_hw_interrupt_umask(INT_URXD0); } #endif void rt_hw_console_output(const char* string) { - while (*string) - { - rt_serial_putc(*string++); - } + while (*string) + { + rt_serial_putc(*string++); + } } /*@}*/ diff --git a/bsp/wh44b0/rtconfig.h b/bsp/wh44b0/rtconfig.h index 32364bbc4a..0f981e1be7 100644 --- a/bsp/wh44b0/rtconfig.h +++ b/bsp/wh44b0/rtconfig.h @@ -3,16 +3,16 @@ #define __RTTHREAD_CFG_H__ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX*/ -#define RT_THREAD_PRIORITY_MAX 256 +#define RT_THREAD_PRIORITY_MAX 256 /* Tick per Second*/ -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 /* SECTION: RT_DEBUG */ /* Thread Debug*/ @@ -59,7 +59,7 @@ /* SECTION: Console options */ /* the buffer size of console*/ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 /* SECTION: FinSH shell options */ /* Using FinSH as Shell*/ @@ -99,21 +99,21 @@ /* #define RT_LWIP_DHCP */ /* ip address of target*/ -#define RT_LWIP_IPADDR0 192 -#define RT_LWIP_IPADDR1 168 -#define RT_LWIP_IPADDR2 0 -#define RT_LWIP_IPADDR3 30 +#define RT_LWIP_IPADDR0 192 +#define RT_LWIP_IPADDR1 168 +#define RT_LWIP_IPADDR2 0 +#define RT_LWIP_IPADDR3 30 /* gateway address of target*/ -#define RT_LWIP_GWADDR0 192 -#define RT_LWIP_GWADDR1 168 -#define RT_LWIP_GWADDR2 0 -#define RT_LWIP_GWADDR3 1 +#define RT_LWIP_GWADDR0 192 +#define RT_LWIP_GWADDR1 168 +#define RT_LWIP_GWADDR2 0 +#define RT_LWIP_GWADDR3 1 /* mask address of target*/ -#define RT_LWIP_MSKADDR0 255 -#define RT_LWIP_MSKADDR1 255 -#define RT_LWIP_MSKADDR2 255 -#define RT_LWIP_MSKADDR3 0 +#define RT_LWIP_MSKADDR0 255 +#define RT_LWIP_MSKADDR1 255 +#define RT_LWIP_MSKADDR2 255 +#define RT_LWIP_MSKADDR3 0 #endif diff --git a/bsp/wh44b0/startup.c b/bsp/wh44b0/startup.c index 4ea7a4f03d..1f92b416c1 100644 --- a/bsp/wh44b0/startup.c +++ b/bsp/wh44b0/startup.c @@ -44,74 +44,74 @@ extern int rt_application_init(void); */ void rtthread_startup(void) { - /* enable cpu cache */ - rt_hw_cpu_icache_enable(); + /* enable cpu cache */ + rt_hw_cpu_icache_enable(); - /* init hardware interrupt */ - rt_hw_interrupt_init(); + /* init hardware interrupt */ + rt_hw_interrupt_init(); - /* init board */ - rt_hw_board_init(); + /* init board */ + rt_hw_board_init(); - /* init hardware serial */ - rt_serial_init(); + /* init hardware serial */ + rt_serial_init(); - rt_show_version(); + rt_show_version(); - /* init tick */ - rt_system_tick_init(); + /* init tick */ + rt_system_tick_init(); - /* init kernel object */ - rt_system_object_init(); + /* init kernel object */ + rt_system_object_init(); - /* init timer system */ - rt_system_timer_init(); + /* init timer system */ + rt_system_timer_init(); - /* init memory system */ + /* init memory system */ #ifdef RT_USING_HEAP #ifdef __CC_ARM - rt_system_heap_init((void*)&Image$$RW_RAM1$$ZI$$Limit, (void*)0xD000000); + rt_system_heap_init((void*)&Image$$RW_RAM1$$ZI$$Limit, (void*)0xD000000); #else - rt_system_heap_init((void*)&__bss_end, (void*)0xD000000); + rt_system_heap_init((void*)&__bss_end, (void*)0xD000000); #endif #endif - /* init scheduler system */ - rt_system_scheduler_init(); + /* init scheduler system */ + rt_system_scheduler_init(); #ifdef RT_USING_HOOK - /* set idle thread hook */ - rt_thread_idle_sethook(rt_hw_led_flash); + /* set idle thread hook */ + rt_thread_idle_sethook(rt_hw_led_flash); #endif - /* init application */ - rt_application_init(); + /* init application */ + rt_application_init(); #ifdef RT_USING_FINSH - /* init the finsh input */ - rt_hw_finsh_init(); + /* init the finsh input */ + rt_hw_finsh_init(); - /* init finsh */ - finsh_system_init(); + /* init finsh */ + finsh_system_init(); #endif - /* init idle thread */ - rt_thread_idle_init(); + /* init idle thread */ + rt_thread_idle_init(); - /* unmask interrupt */ - rt_hw_interrupt_umask(INT_GLOBAL); + /* unmask interrupt */ + rt_hw_interrupt_umask(INT_GLOBAL); - /* start scheduler */ - rt_system_scheduler_start(); + /* start scheduler */ + rt_system_scheduler_start(); - /* never reach here */ - return ; + /* never reach here */ + return ; } int main(void) { - /* invoke rtthread startup */ - rtthread_startup(); + /* invoke rtthread startup */ + rtthread_startup(); } /*@}*/ diff --git a/bsp/x86/applications/application.c b/bsp/x86/applications/application.c index e15e10e6b0..cdf889699e 100644 --- a/bsp/x86/applications/application.c +++ b/bsp/x86/applications/application.c @@ -24,17 +24,17 @@ extern int elm_init(void); void components_init(void) { #ifdef RT_USING_DFS - rt_floppy_init(); - /* initialize the device file system */ - dfs_init(); + rt_floppy_init(); + /* initialize the device file system */ + dfs_init(); #ifdef RT_USING_DFS_ELMFAT - /* initialize the elm chan FatFS file system*/ - elm_init(); + /* initialize the elm chan FatFS file system*/ + elm_init(); #endif #ifdef RT_USING_MODULE - rt_system_dlmodule_init(); + rt_system_dlmodule_init(); #endif #endif } diff --git a/bsp/x86/drivers/board.c b/bsp/x86/drivers/board.c index 0c0d0222f7..cb92a3a0bf 100644 --- a/bsp/x86/drivers/board.c +++ b/bsp/x86/drivers/board.c @@ -21,13 +21,13 @@ static void rt_timer_handler(int vector, void* param) { - rt_tick_increase(); + rt_tick_increase(); } #ifdef RT_USING_HOOK static void idle_hook(void) { - asm volatile("sti; hlt": : :"memory"); + asm volatile("sti; hlt": : :"memory"); } #endif @@ -37,17 +37,17 @@ static void idle_hook(void) */ void rt_hw_board_init(void) { - /* initialize 8253 clock to interrupt 1000 times/sec */ - outb(TIMER_MODE, TIMER_SEL0|TIMER_RATEGEN|TIMER_16BIT); - outb(IO_TIMER1, TIMER_DIV(RT_TICK_PER_SECOND) % 256); - outb(IO_TIMER1, TIMER_DIV(RT_TICK_PER_SECOND) / 256); + /* initialize 8253 clock to interrupt 1000 times/sec */ + outb(TIMER_MODE, TIMER_SEL0|TIMER_RATEGEN|TIMER_16BIT); + outb(IO_TIMER1, TIMER_DIV(RT_TICK_PER_SECOND) % 256); + outb(IO_TIMER1, TIMER_DIV(RT_TICK_PER_SECOND) / 256); - /* install interrupt handler */ - rt_hw_interrupt_install(INTTIMER0, rt_timer_handler, RT_NULL, "tick"); - rt_hw_interrupt_umask(INTTIMER0); + /* install interrupt handler */ + rt_hw_interrupt_install(INTTIMER0, rt_timer_handler, RT_NULL, "tick"); + rt_hw_interrupt_umask(INTTIMER0); #ifdef RT_USING_HOOK - rt_thread_idle_sethook(idle_hook); + rt_thread_idle_sethook(idle_hook); #endif } diff --git a/bsp/x86/drivers/console.c b/bsp/x86/drivers/console.c index e8fc66093a..6741efb714 100644 --- a/bsp/x86/drivers/console.c +++ b/bsp/x86/drivers/console.c @@ -87,7 +87,7 @@ static void rt_cga_putc(int c) break; case '\n': crt_pos += CRT_COLS; - /* cascade */ + /* cascade */ case '\r': crt_pos -= (crt_pos % CRT_COLS); break; @@ -99,7 +99,7 @@ static void rt_cga_putc(int c) rt_console_putc(' '); break; default: - crt_buf[crt_pos++] = c; /* write the character */ + crt_buf[crt_pos++] = c; /* write the character */ break; } @@ -214,47 +214,47 @@ static rt_size_t rt_console_read(rt_device_t dev, rt_off_t pos, void* buffer, rt static void rt_console_isr(int vector, void* param) { char c; - rt_bool_t ret; + rt_bool_t ret; rt_base_t level; - if(INTUART0_RX == vector) - { - c = rt_serial_getc(); - ret = RT_TRUE; - } - else - { - rt_keyboard_isr(); - - ret = rt_keyboard_getc(&c); - } - - if(ret == RT_FALSE) - { - /* do nothing */ - } - else - { - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - /* save character */ - rx_buffer[save_index] = c; - save_index ++; - if (save_index >= CONSOLE_RX_BUFFER_SIZE) - save_index = 0; - - /* if the next position is read index, discard this 'read char' */ - if (save_index == read_index) - { - read_index ++; - if (read_index >= CONSOLE_RX_BUFFER_SIZE) - read_index = 0; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } + if(INTUART0_RX == vector) + { + c = rt_serial_getc(); + ret = RT_TRUE; + } + else + { + rt_keyboard_isr(); + + ret = rt_keyboard_getc(&c); + } + + if(ret == RT_FALSE) + { + /* do nothing */ + } + else + { + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + /* save character */ + rx_buffer[save_index] = c; + save_index ++; + if (save_index >= CONSOLE_RX_BUFFER_SIZE) + save_index = 0; + + /* if the next position is read index, discard this 'read char' */ + if (save_index == read_index) + { + read_index ++; + if (read_index >= CONSOLE_RX_BUFFER_SIZE) + read_index = 0; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } /* invoke callback */ if (console_device.rx_indicate != RT_NULL) @@ -263,8 +263,8 @@ static void rt_console_isr(int vector, void* param) /* get rx length */ rx_length = read_index > save_index ? - CONSOLE_RX_BUFFER_SIZE - read_index + save_index : - save_index - read_index; + CONSOLE_RX_BUFFER_SIZE - read_index + save_index : + save_index - read_index; if(rx_length > 0) { @@ -284,8 +284,8 @@ static void rt_console_isr(int vector, void* param) void rt_hw_console_init(void) { rt_cga_init(); - rt_serial_init(); - init_keyboard(); + rt_serial_init(); + init_keyboard(); /* install keyboard isr */ rt_hw_interrupt_install(INTKEYBOARD, rt_console_isr, RT_NULL, "kbd"); @@ -294,14 +294,14 @@ void rt_hw_console_init(void) rt_hw_interrupt_install(INTUART0_RX, rt_console_isr, RT_NULL, "COM1"); rt_hw_interrupt_umask(INTUART0_RX); - console_device.type = RT_Device_Class_Char; + console_device.type = RT_Device_Class_Char; console_device.rx_indicate = RT_NULL; console_device.tx_complete = RT_NULL; - console_device.init = rt_console_init; - console_device.open = rt_console_open; - console_device.close = rt_console_close; - console_device.read = rt_console_read; - console_device.write = rt_console_write; + console_device.init = rt_console_init; + console_device.open = rt_console_open; + console_device.close = rt_console_close; + console_device.read = rt_console_read; + console_device.write = rt_console_write; console_device.control = rt_console_control; console_device.user_data = RT_NULL; @@ -318,8 +318,8 @@ void rt_hw_console_init(void) * @param str the displayed string * * Modified: - * caoxl 2009-10-14 - * the name is change to rt_hw_console_output in the v0.3.0 + * caoxl 2009-10-14 + * the name is change to rt_hw_console_output in the v0.3.0 * */ void rt_hw_console_output(const char* str) diff --git a/bsp/x86/drivers/include/bsp.h b/bsp/x86/drivers/include/bsp.h index 724f518c6e..3c7960ed1c 100644 --- a/bsp/x86/drivers/include/bsp.h +++ b/bsp/x86/drivers/include/bsp.h @@ -19,127 +19,127 @@ #ifdef __cplusplus extern "C" { #endif - + /*******************************************************************/ /* Timer Register */ /*******************************************************************/ -#define TIMER_CNTR0 (IO_TIMER1 + 0) /* timer 0 counter port */ -#define TIMER_CNTR1 (IO_TIMER1 + 1) /* timer 1 counter port */ -#define TIMER_CNTR2 (IO_TIMER1 + 2) /* timer 2 counter port */ -#define TIMER_MODE (IO_TIMER1 + 3) /* timer mode port */ -#define TIMER_SEL0 0x00 /* select counter 0 */ -#define TIMER_SEL1 0x40 /* select counter 1 */ -#define TIMER_INTTC 0x00 /* mode 0, intr on terminal cnt */ -#define TIMER_ONESHOT 0x02 /* mode 1, one shot */ -#define TIMER_RATEGEN 0x04 /* mode 2, rate generator */ -#define TIMER_SQWAVE 0x06 /* mode 3, square wave */ -#define TIMER_SWSTROBE 0x08 /* mode 4, s/w triggered strobe */ -#define TIMER_HWSTROBE 0x0a /* mode 5, h/w triggered strobe */ -#define TIMER_LATCH 0x00 /* latch counter for reading */ -#define TIMER_LSB 0x10 /* r/w counter LSB */ -#define TIMER_MSB 0x20 /* r/w counter MSB */ -#define TIMER_16BIT 0x30 /* r/w counter 16 bits, LSB first */ -#define TIMER_BCD 0x01 /* count in BCD */ - -#define TIMER_FREQ 1193182 -#define TIMER_DIV(x) ((TIMER_FREQ+(x)/2)/(x)) - -#define IO_TIMER1 0x040 /* 8253 Timer #1 */ +#define TIMER_CNTR0 (IO_TIMER1 + 0) /* timer 0 counter port */ +#define TIMER_CNTR1 (IO_TIMER1 + 1) /* timer 1 counter port */ +#define TIMER_CNTR2 (IO_TIMER1 + 2) /* timer 2 counter port */ +#define TIMER_MODE (IO_TIMER1 + 3) /* timer mode port */ +#define TIMER_SEL0 0x00 /* select counter 0 */ +#define TIMER_SEL1 0x40 /* select counter 1 */ +#define TIMER_INTTC 0x00 /* mode 0, intr on terminal cnt */ +#define TIMER_ONESHOT 0x02 /* mode 1, one shot */ +#define TIMER_RATEGEN 0x04 /* mode 2, rate generator */ +#define TIMER_SQWAVE 0x06 /* mode 3, square wave */ +#define TIMER_SWSTROBE 0x08 /* mode 4, s/w triggered strobe */ +#define TIMER_HWSTROBE 0x0a /* mode 5, h/w triggered strobe */ +#define TIMER_LATCH 0x00 /* latch counter for reading */ +#define TIMER_LSB 0x10 /* r/w counter LSB */ +#define TIMER_MSB 0x20 /* r/w counter MSB */ +#define TIMER_16BIT 0x30 /* r/w counter 16 bits, LSB first */ +#define TIMER_BCD 0x01 /* count in BCD */ + +#define TIMER_FREQ 1193182 +#define TIMER_DIV(x) ((TIMER_FREQ+(x)/2)/(x)) + +#define IO_TIMER1 0x040 /* 8253 Timer #1 */ /*******************************************************************/ /* Interrupt Controller */ /*******************************************************************/ /* these are processor defined */ -#define T_DIVIDE 0 /* divide error */ -#define T_DEBUG 1 /* debug exception */ -#define T_NMI 2 /* non-maskable interrupt */ -#define T_BRKPT 3 /* breakpoint */ -#define T_OFLOW 4 /* overflow */ -#define T_BOUND 5 /* bounds check */ -#define T_ILLOP 6 /* illegal opcode */ -#define T_DEVICE 7 /* device not available */ -#define T_DBLFLT 8 /* double fault */ +#define T_DIVIDE 0 /* divide error */ +#define T_DEBUG 1 /* debug exception */ +#define T_NMI 2 /* non-maskable interrupt */ +#define T_BRKPT 3 /* breakpoint */ +#define T_OFLOW 4 /* overflow */ +#define T_BOUND 5 /* bounds check */ +#define T_ILLOP 6 /* illegal opcode */ +#define T_DEVICE 7 /* device not available */ +#define T_DBLFLT 8 /* double fault */ /* 9 is reserved */ -#define T_TSS 10 /* invalid task switch segment */ -#define T_SEGNP 11 /* segment not present */ -#define T_STACK 12 /* stack exception */ -#define T_GPFLT 13 /* genernal protection fault */ -#define T_PGFLT 14 /* page fault */ +#define T_TSS 10 /* invalid task switch segment */ +#define T_SEGNP 11 /* segment not present */ +#define T_STACK 12 /* stack exception */ +#define T_GPFLT 13 /* genernal protection fault */ +#define T_PGFLT 14 /* page fault */ /* 15 is reserved */ -#define T_FPERR 16 /* floating point error */ -#define T_ALIGN 17 /* aligment check */ -#define T_MCHK 18 /* machine check */ -#define T_DEFAULT 500 /* catchall */ - -#define INTTIMER0 0 -#define INTKEYBOARD 1 -#define INTUART0_RX 4 -#define CLOCK_IRQ 0 -#define KEYBOARD_IRQ 1 -#define CASCADE_IRQ 2 /* cascade enable for 2nd AT controller */ -#define ETHER_IRQ 3 /* default ethernet interrupt vector */ -#define SECONDARY_IRQ 3 /* RS232 interrupt vector for port 2 */ -#define RS232_IRQ 4 /* RS232 interrupt vector for port 1 */ -#define XT_WINI_IRQ 5 /* xt winchester */ -#define FLOPPY_IRQ 6 /* floppy disk */ -#define PRINTER_IRQ 7 -#define AT_WINI_IRQ 14 /* at winchester */ +#define T_FPERR 16 /* floating point error */ +#define T_ALIGN 17 /* aligment check */ +#define T_MCHK 18 /* machine check */ +#define T_DEFAULT 500 /* catchall */ + +#define INTTIMER0 0 +#define INTKEYBOARD 1 +#define INTUART0_RX 4 +#define CLOCK_IRQ 0 +#define KEYBOARD_IRQ 1 +#define CASCADE_IRQ 2 /* cascade enable for 2nd AT controller */ +#define ETHER_IRQ 3 /* default ethernet interrupt vector */ +#define SECONDARY_IRQ 3 /* RS232 interrupt vector for port 2 */ +#define RS232_IRQ 4 /* RS232 interrupt vector for port 1 */ +#define XT_WINI_IRQ 5 /* xt winchester */ +#define FLOPPY_IRQ 6 /* floppy disk */ +#define PRINTER_IRQ 7 +#define AT_WINI_IRQ 14 /* at winchester */ /* I/O Addresses of the two 8259A programmable interrupt controllers */ -#define IO_PIC1 0x20 /* Master(IRQs 0-7) */ -#define IO_PIC2 0xa0 /* Slave(IRQs 8-15) */ -#define IRQ_SLAVE 0x2 /* IRQ at which slave connects to master */ -#define IRQ_OFFSET 0x20 /* IRQ 0 corresponds to int IRQ_OFFSET */ +#define IO_PIC1 0x20 /* Master(IRQs 0-7) */ +#define IO_PIC2 0xa0 /* Slave(IRQs 8-15) */ +#define IRQ_SLAVE 0x2 /* IRQ at which slave connects to master */ +#define IRQ_OFFSET 0x20 /* IRQ 0 corresponds to int IRQ_OFFSET */ -#define MAX_HANDLERS 16 /*max number of isr handler*/ +#define MAX_HANDLERS 16 /*max number of isr handler*/ /*******************************************************************/ /* CRT Register */ /*******************************************************************/ -#define MONO_BASE 0x3b4 -#define MONO_BUF 0xb0000 -#define CGA_BASE 0x3d4 -#define CGA_BUF 0xb8000 +#define MONO_BASE 0x3b4 +#define MONO_BUF 0xb0000 +#define CGA_BASE 0x3d4 +#define CGA_BUF 0xb8000 -#define CRT_ROWS 25 -#define CRT_COLS 80 -#define CRT_SIZE (CRT_ROWS * CRT_COLS) +#define CRT_ROWS 25 +#define CRT_COLS 80 +#define CRT_SIZE (CRT_ROWS * CRT_COLS) /*******************************************************************/ /* Keyboard Register */ /*******************************************************************/ -#define KBSTATP 0x64 /* kbd controller status port(I) */ -#define KBS_DIB 0x01 /* kbd data in buffer */ -#define KBDATAP 0x60 /* kbd data port(I) */ +#define KBSTATP 0x64 /* kbd controller status port(I) */ +#define KBS_DIB 0x01 /* kbd data in buffer */ +#define KBDATAP 0x60 /* kbd data port(I) */ /* AT keyboard */ /* 8042 ports */ -#define KB_DATA 0x60 /* I/O port for keyboard data - Read : Read Output Buffer - Write: Write Input Buffer(8042 Data&8048 Command) */ -#define KB_CMD 0x64 /* I/O port for keyboard command - Read : Read Status Register - Write: Write Input Buffer(8042 Command) */ -#define LED_CODE 0xED -#define KB_ACK 0xFA +#define KB_DATA 0x60 /* I/O port for keyboard data + Read : Read Output Buffer + Write: Write Input Buffer(8042 Data&8048 Command) */ +#define KB_CMD 0x64 /* I/O port for keyboard command + Read : Read Status Register + Write: Write Input Buffer(8042 Command) */ +#define LED_CODE 0xED +#define KB_ACK 0xFA /*******************************************************************/ /* Serial Register */ /*******************************************************************/ /*Serial I/O code */ -#define COM1 0x3F8 -#define COMSTATUS 5 -#define COMDATA 0x01 -#define COMREAD 0 -#define COMWRITE 0 +#define COM1 0x3F8 +#define COMSTATUS 5 +#define COMDATA 0x01 +#define COMREAD 0 +#define COMWRITE 0 /* Bits definition of the Line Status Register (LSR)*/ -#define DR 0x01 /* Data Ready */ -#define OE 0x02 /* Overrun Error */ -#define PE 0x04 /* Parity Error */ -#define FE 0x08 /* Framing Error */ -#define BI 0x10 /* Break Interrupt */ -#define THRE 0x20 /* Transmitter Holding Register Empty */ -#define TEMT 0x40 /* Transmitter Empty */ -#define ERFIFO 0x80 /* Error receive Fifo */ +#define DR 0x01 /* Data Ready */ +#define OE 0x02 /* Overrun Error */ +#define PE 0x04 /* Parity Error */ +#define FE 0x08 /* Framing Error */ +#define BI 0x10 /* Break Interrupt */ +#define THRE 0x20 /* Transmitter Holding Register Empty */ +#define TEMT 0x40 /* Transmitter Empty */ +#define ERFIFO 0x80 /* Error receive Fifo */ #ifdef __cplusplus } diff --git a/bsp/x86/drivers/include/grub.h b/bsp/x86/drivers/include/grub.h index dcfa36b819..f50edbe8a2 100644 --- a/bsp/x86/drivers/include/grub.h +++ b/bsp/x86/drivers/include/grub.h @@ -9,7 +9,7 @@ * * Change Logs: * Date Author Notes - * 2006-10-09 Bernard the grub related definitions + * 2006-10-09 Bernard the grub related definitions * (multiboot) */ @@ -17,75 +17,75 @@ #define __GRUB_H__ /* the magic number for the multiboot header. */ -#define MULTIBOOT_HEADER_MAGIC 0x1BADB002 +#define MULTIBOOT_HEADER_MAGIC 0x1BADB002 /* the flags for the multiboot header. */ -#define MULTIBOOT_HEADER_FLAGS 0x00000003 +#define MULTIBOOT_HEADER_FLAGS 0x00000003 /* the magic number passed by a multiboot-compliant boot loader. */ -#define MULTIBOOT_BOOTLOADER_MAGIC 0x2BADB002 +#define MULTIBOOT_BOOTLOADER_MAGIC 0x2BADB002 #ifndef __ASM__ /* the multiboot header. */ typedef struct multiboot_header { - unsigned long magic; - unsigned long flags; - unsigned long checksum; - unsigned long header_addr; - unsigned long load_addr; - unsigned long load_end_addr; - unsigned long bss_end_addr; - unsigned long entry_addr; + unsigned long magic; + unsigned long flags; + unsigned long checksum; + unsigned long header_addr; + unsigned long load_addr; + unsigned long load_end_addr; + unsigned long bss_end_addr; + unsigned long entry_addr; } multiboot_header_t; /* the section header table for elf. */ typedef struct elf_section_header_table { - unsigned long num; - unsigned long size; - unsigned long addr; - unsigned long shndx; + unsigned long num; + unsigned long size; + unsigned long addr; + unsigned long shndx; } elf_section_header_table_t; /* the multiboot information. */ typedef struct multiboot_info { - unsigned long flags; - unsigned long mem_lower; - unsigned long mem_upper; - unsigned long boot_device; - unsigned long cmdline; - unsigned long mods_count; - unsigned long mods_addr; - union - { - aout_symbol_table_t aout_sym; - elf_section_header_table_t elf_sec; - } u; - unsigned long mmap_length; - unsigned long mmap_addr; + unsigned long flags; + unsigned long mem_lower; + unsigned long mem_upper; + unsigned long boot_device; + unsigned long cmdline; + unsigned long mods_count; + unsigned long mods_addr; + union + { + aout_symbol_table_t aout_sym; + elf_section_header_table_t elf_sec; + } u; + unsigned long mmap_length; + unsigned long mmap_addr; } multiboot_info_t; /* the module structure. */ typedef struct module { - unsigned long mod_start; - unsigned long mod_end; - unsigned long string; - unsigned long reserved; + unsigned long mod_start; + unsigned long mod_end; + unsigned long string; + unsigned long reserved; } module_t; /* the memory map. be careful that the offset 0 is base_addr_low but no size. */ typedef struct memory_map { - unsigned long size; - unsigned long base_addr_low; - unsigned long base_addr_high; - unsigned long length_low; - unsigned long length_high; - unsigned long type; + unsigned long size; + unsigned long base_addr_low; + unsigned long base_addr_high; + unsigned long length_low; + unsigned long length_high; + unsigned long type; } memory_map_t; #endif diff --git a/bsp/x86/drivers/keyboard.c b/bsp/x86/drivers/keyboard.c index 61f2846dc6..4890db380b 100644 --- a/bsp/x86/drivers/keyboard.c +++ b/bsp/x86/drivers/keyboard.c @@ -19,290 +19,290 @@ #define FALSE RT_FALSE #define TRUE RT_TRUE #define PRIVATE static -#define PUBLIC +#define PUBLIC #define t_bool rt_bool_t #define t_8 rt_uint8_t #define t_32 rt_uint32_t -PRIVATE KB_INPUT kb_in; -PRIVATE t_bool code_with_E0 = FALSE; -PRIVATE t_bool shift_l; /* l shift state */ -PRIVATE t_bool shift_r; /* r shift state */ -PRIVATE t_bool alt_l; /* l alt state */ -PRIVATE t_bool alt_r; /* r left state */ -PRIVATE t_bool ctrl_l; /* l ctrl state */ -PRIVATE t_bool ctrl_r; /* l ctrl state */ -PRIVATE t_bool caps_lock; /* Caps Lock */ -PRIVATE t_bool num_lock; /* Num Lock */ -PRIVATE t_bool scroll_lock; /* Scroll Lock */ -PRIVATE int column = 0; /* keyrow[column] is one value of keymap */ - -PRIVATE t_8 get_byte_from_kb_buf(); -PRIVATE void set_leds(); -PRIVATE void kb_wait(); -PRIVATE void kb_ack(); +PRIVATE KB_INPUT kb_in; +PRIVATE t_bool code_with_E0 = FALSE; +PRIVATE t_bool shift_l; /* l shift state */ +PRIVATE t_bool shift_r; /* r shift state */ +PRIVATE t_bool alt_l; /* l alt state */ +PRIVATE t_bool alt_r; /* r left state */ +PRIVATE t_bool ctrl_l; /* l ctrl state */ +PRIVATE t_bool ctrl_r; /* l ctrl state */ +PRIVATE t_bool caps_lock; /* Caps Lock */ +PRIVATE t_bool num_lock; /* Num Lock */ +PRIVATE t_bool scroll_lock; /* Scroll Lock */ +PRIVATE int column = 0; /* keyrow[column] is one value of keymap */ + +PRIVATE t_8 get_byte_from_kb_buf(); +PRIVATE void set_leds(); +PRIVATE void kb_wait(); +PRIVATE void kb_ack(); PUBLIC void init_keyboard() { - kb_in.count = 0; - kb_in.p_head = kb_in.p_tail = kb_in.buf; + kb_in.count = 0; + kb_in.p_head = kb_in.p_tail = kb_in.buf; - caps_lock = 0; - num_lock = 1; - scroll_lock = 0; + caps_lock = 0; + num_lock = 1; + scroll_lock = 0; - set_leds(); + set_leds(); } PUBLIC rt_bool_t keyboard_read(rt_uint32_t *pkey) { - t_8 scan_code; - t_bool make; /* TRUE : make */ - /* FALSE: break */ - t_32 key = 0; - t_32* keyrow; - - if(kb_in.count > 0){ - code_with_E0 = FALSE; - scan_code = get_byte_from_kb_buf(); - - /* start scan */ - if (scan_code == 0xE1) { - int i; - static const t_8 pausebreak_scan_code[] = {0xE1, 0x1D, 0x45, 0xE1, 0x9D, 0xC5}; - t_bool is_pausebreak = TRUE; - for(i=1;i<6;i++){ - if (get_byte_from_kb_buf() != pausebreak_scan_code[i]) { - is_pausebreak = FALSE; - break; - } - } - if (is_pausebreak) { - key = PAUSEBREAK; - } - } - else if (scan_code == 0xE0) { - code_with_E0 = TRUE; - scan_code = get_byte_from_kb_buf(); - - /* PrintScreen pressed */ - if (scan_code == 0x2A) { - code_with_E0 = FALSE; - if ((scan_code = get_byte_from_kb_buf()) == 0xE0) { - code_with_E0 = TRUE; - if ((scan_code = get_byte_from_kb_buf()) == 0x37) { - key = PRINTSCREEN; - make = TRUE; - } - } - } - /* PrintScreen released */ - else if (scan_code == 0xB7) { - code_with_E0 = FALSE; - if ((scan_code = get_byte_from_kb_buf()) == 0xE0) { - code_with_E0 = TRUE; - if ((scan_code = get_byte_from_kb_buf()) == 0xAA) { - key = PRINTSCREEN; - make = FALSE; - } - } - } - } /* if is not PrintScreen, scan_code is the one after 0xE0 */ - if ((key != PAUSEBREAK) && (key != PRINTSCREEN)) { - /* is Make Code or Break Code */ - make = (scan_code & FLAG_BREAK ? FALSE : TRUE); - - keyrow = &keymap[(scan_code & 0x7F) * MAP_COLS]; - - column = 0; - - t_bool caps = shift_l || shift_r; - if (caps_lock) { - if ((keyrow[0] >= 'a') && (keyrow[0] <= 'z')){ - caps = !caps; - } - } - if (caps) { - column = 1; - } - - if (code_with_E0) { - column = 2; - } - - key = keyrow[column]; - - switch(key) { - case SHIFT_L: - shift_l = make; - break; - case SHIFT_R: - shift_r = make; - break; - case CTRL_L: - ctrl_l = make; - break; - case CTRL_R: - ctrl_r = make; - break; - case ALT_L: - alt_l = make; - break; - case ALT_R: - alt_l = make; - break; - case CAPS_LOCK: - if (make) { - caps_lock = !caps_lock; - set_leds(); - } - break; - case NUM_LOCK: - if (make) { - num_lock = !num_lock; - set_leds(); - } - break; - case SCROLL_LOCK: - if (make) { - scroll_lock = !scroll_lock; - set_leds(); - } - break; - default: - break; - } - } - - if(make){ /* ignore Break Code */ - t_bool pad = FALSE; - - /* handle the small pad first */ - if ((key >= PAD_SLASH) && (key <= PAD_9)) { - pad = TRUE; - switch(key) { /* '/', '*', '-', '+', and 'Enter' in num pad */ - case PAD_SLASH: - key = '/'; - break; - case PAD_STAR: - key = '*'; - break; - case PAD_MINUS: - key = '-'; - break; - case PAD_PLUS: - key = '+'; - break; - case PAD_ENTER: - key = ENTER; - break; - default: /* keys whose value depends on the NumLock */ - if (num_lock) { /* '0' ~ '9' and '.' in num pad */ - if ((key >= PAD_0) && (key <= PAD_9)) { - key = key - PAD_0 + '0'; - } - else if (key == PAD_DOT) { - key = '.'; - } - } - else{ - switch(key) { - case PAD_HOME: - key = HOME; - break; - case PAD_END: - key = END; - break; - case PAD_PAGEUP: - key = PAGEUP; - break; - case PAD_PAGEDOWN: - key = PAGEDOWN; - break; - case PAD_INS: - key = INSERT; - break; - case PAD_UP: - key = UP; - break; - case PAD_DOWN: - key = DOWN; - break; - case PAD_LEFT: - key = LEFT; - break; - case PAD_RIGHT: - key = RIGHT; - break; - case PAD_DOT: - key = DELETE; - break; - default: - break; - } - } - break; - } - } - key |= shift_l ? FLAG_SHIFT_L : 0; - key |= shift_r ? FLAG_SHIFT_R : 0; - key |= ctrl_l ? FLAG_CTRL_L : 0; - key |= ctrl_r ? FLAG_CTRL_R : 0; - key |= alt_l ? FLAG_ALT_L : 0; - key |= alt_r ? FLAG_ALT_R : 0; - key |= pad ? FLAG_PAD : 0; - - *pkey = key; - return TRUE; - } - } - - return FALSE; + t_8 scan_code; + t_bool make; /* TRUE : make */ + /* FALSE: break */ + t_32 key = 0; + t_32* keyrow; + + if(kb_in.count > 0){ + code_with_E0 = FALSE; + scan_code = get_byte_from_kb_buf(); + + /* start scan */ + if (scan_code == 0xE1) { + int i; + static const t_8 pausebreak_scan_code[] = {0xE1, 0x1D, 0x45, 0xE1, 0x9D, 0xC5}; + t_bool is_pausebreak = TRUE; + for(i=1;i<6;i++){ + if (get_byte_from_kb_buf() != pausebreak_scan_code[i]) { + is_pausebreak = FALSE; + break; + } + } + if (is_pausebreak) { + key = PAUSEBREAK; + } + } + else if (scan_code == 0xE0) { + code_with_E0 = TRUE; + scan_code = get_byte_from_kb_buf(); + + /* PrintScreen pressed */ + if (scan_code == 0x2A) { + code_with_E0 = FALSE; + if ((scan_code = get_byte_from_kb_buf()) == 0xE0) { + code_with_E0 = TRUE; + if ((scan_code = get_byte_from_kb_buf()) == 0x37) { + key = PRINTSCREEN; + make = TRUE; + } + } + } + /* PrintScreen released */ + else if (scan_code == 0xB7) { + code_with_E0 = FALSE; + if ((scan_code = get_byte_from_kb_buf()) == 0xE0) { + code_with_E0 = TRUE; + if ((scan_code = get_byte_from_kb_buf()) == 0xAA) { + key = PRINTSCREEN; + make = FALSE; + } + } + } + } /* if is not PrintScreen, scan_code is the one after 0xE0 */ + if ((key != PAUSEBREAK) && (key != PRINTSCREEN)) { + /* is Make Code or Break Code */ + make = (scan_code & FLAG_BREAK ? FALSE : TRUE); + + keyrow = &keymap[(scan_code & 0x7F) * MAP_COLS]; + + column = 0; + + t_bool caps = shift_l || shift_r; + if (caps_lock) { + if ((keyrow[0] >= 'a') && (keyrow[0] <= 'z')){ + caps = !caps; + } + } + if (caps) { + column = 1; + } + + if (code_with_E0) { + column = 2; + } + + key = keyrow[column]; + + switch(key) { + case SHIFT_L: + shift_l = make; + break; + case SHIFT_R: + shift_r = make; + break; + case CTRL_L: + ctrl_l = make; + break; + case CTRL_R: + ctrl_r = make; + break; + case ALT_L: + alt_l = make; + break; + case ALT_R: + alt_l = make; + break; + case CAPS_LOCK: + if (make) { + caps_lock = !caps_lock; + set_leds(); + } + break; + case NUM_LOCK: + if (make) { + num_lock = !num_lock; + set_leds(); + } + break; + case SCROLL_LOCK: + if (make) { + scroll_lock = !scroll_lock; + set_leds(); + } + break; + default: + break; + } + } + + if(make){ /* ignore Break Code */ + t_bool pad = FALSE; + + /* handle the small pad first */ + if ((key >= PAD_SLASH) && (key <= PAD_9)) { + pad = TRUE; + switch(key) { /* '/', '*', '-', '+', and 'Enter' in num pad */ + case PAD_SLASH: + key = '/'; + break; + case PAD_STAR: + key = '*'; + break; + case PAD_MINUS: + key = '-'; + break; + case PAD_PLUS: + key = '+'; + break; + case PAD_ENTER: + key = ENTER; + break; + default: /* keys whose value depends on the NumLock */ + if (num_lock) { /* '0' ~ '9' and '.' in num pad */ + if ((key >= PAD_0) && (key <= PAD_9)) { + key = key - PAD_0 + '0'; + } + else if (key == PAD_DOT) { + key = '.'; + } + } + else{ + switch(key) { + case PAD_HOME: + key = HOME; + break; + case PAD_END: + key = END; + break; + case PAD_PAGEUP: + key = PAGEUP; + break; + case PAD_PAGEDOWN: + key = PAGEDOWN; + break; + case PAD_INS: + key = INSERT; + break; + case PAD_UP: + key = UP; + break; + case PAD_DOWN: + key = DOWN; + break; + case PAD_LEFT: + key = LEFT; + break; + case PAD_RIGHT: + key = RIGHT; + break; + case PAD_DOT: + key = DELETE; + break; + default: + break; + } + } + break; + } + } + key |= shift_l ? FLAG_SHIFT_L : 0; + key |= shift_r ? FLAG_SHIFT_R : 0; + key |= ctrl_l ? FLAG_CTRL_L : 0; + key |= ctrl_r ? FLAG_CTRL_R : 0; + key |= alt_l ? FLAG_ALT_L : 0; + key |= alt_r ? FLAG_ALT_R : 0; + key |= pad ? FLAG_PAD : 0; + + *pkey = key; + return TRUE; + } + } + + return FALSE; } PRIVATE t_8 get_byte_from_kb_buf() { - t_8 scan_code; + t_8 scan_code; - RT_ASSERT(kb_in.count>0); - scan_code = *(kb_in.p_tail); - kb_in.p_tail++; - if (kb_in.p_tail == kb_in.buf + KB_IN_BYTES) { - kb_in.p_tail = kb_in.buf; - } - kb_in.count--; + RT_ASSERT(kb_in.count>0); + scan_code = *(kb_in.p_tail); + kb_in.p_tail++; + if (kb_in.p_tail == kb_in.buf + KB_IN_BYTES) { + kb_in.p_tail = kb_in.buf; + } + kb_in.count--; - return scan_code; + return scan_code; } PRIVATE void kb_wait() /* wait inpit cache of 8042 */ { - t_8 kb_stat; + t_8 kb_stat; - do { - kb_stat = inb(KB_CMD); - } while (kb_stat & 0x02); + do { + kb_stat = inb(KB_CMD); + } while (kb_stat & 0x02); } PRIVATE void kb_ack() { - t_8 kb_read; + t_8 kb_read; - do { - kb_read = inb(KB_DATA); - } while (kb_read != KB_ACK); + do { + kb_read = inb(KB_DATA); + } while (kb_read != KB_ACK); } PRIVATE void set_leds() { - t_8 leds = (caps_lock << 2) | (num_lock << 1) | scroll_lock; + t_8 leds = (caps_lock << 2) | (num_lock << 1) | scroll_lock; - kb_wait(); - outb(KB_DATA, LED_CODE); - kb_ack(); + kb_wait(); + outb(KB_DATA, LED_CODE); + kb_ack(); - kb_wait(); - outb(KB_DATA, leds); - kb_ack(); + kb_wait(); + outb(KB_DATA, leds); + kb_ack(); } /** @@ -312,51 +312,51 @@ PRIVATE void set_leds() void rt_keyboard_isr(void) { - rt_uint8_t data; + rt_uint8_t data; - if ((inb(KBSTATP) & KBS_DIB) == 0) - return ; + if ((inb(KBSTATP) & KBS_DIB) == 0) + return ; - data = inb(KBDATAP); + data = inb(KBDATAP); - if (kb_in.count < KB_IN_BYTES) { - *(kb_in.p_head) = data; - kb_in.p_head++; - if (kb_in.p_head == kb_in.buf + KB_IN_BYTES) { - kb_in.p_head = kb_in.buf; - } - kb_in.count++; - } + if (kb_in.count < KB_IN_BYTES) { + *(kb_in.p_head) = data; + kb_in.p_head++; + if (kb_in.p_head == kb_in.buf + KB_IN_BYTES) { + kb_in.p_head = kb_in.buf; + } + kb_in.count++; + } } /* generally, this should be called in task level for all key inpit support, but here only support a key that is composed of 2 bytes */ rt_bool_t rt_keyboard_getc(char* c) { - if(kb_in.count>=2) - { - rt_uint32_t key = 0; - rt_bool_t rv=keyboard_read(&key); - - switch(key) - { - case TAB: - *c = '\t'; - break; - case ENTER: - *c = '\n'; - break; - case BACKSPACE: - *c = '\b'; - break; - default: - *c = key; - break; - } - - return rv; - } - - return RT_FALSE; + if(kb_in.count>=2) + { + rt_uint32_t key = 0; + rt_bool_t rv=keyboard_read(&key); + + switch(key) + { + case TAB: + *c = '\t'; + break; + case ENTER: + *c = '\n'; + break; + case BACKSPACE: + *c = '\b'; + break; + default: + *c = key; + break; + } + + return rv; + } + + return RT_FALSE; } /*@}*/ diff --git a/bsp/x86/drivers/serial.c b/bsp/x86/drivers/serial.c index f5510ae0d5..3ed8d6fed5 100644 --- a/bsp/x86/drivers/serial.c +++ b/bsp/x86/drivers/serial.c @@ -8,7 +8,7 @@ * 2006-09-15 QiuYi the first version * 2006-10-10 Bernard use keyboard instead of serial */ - + #include #include @@ -24,26 +24,26 @@ */ void rt_serial_init(void) { - outb(COM1+3,0x80); /* set DLAB of line control reg */ - outb(COM1,0x0c); /* LS of divisor (48 -> 2400 bps */ - outb(COM1+1,0x00); /* MS of divisor */ - outb(COM1+3,0x03); /* reset DLAB */ - outb(COM1+4,0x0b); /* set DTR,RTS, OUT_2 */ - outb(COM1+1,0x0d); /* enable all intrs but writes */ - inb(COM1); /* read data port to reset things (?) */ + outb(COM1+3,0x80); /* set DLAB of line control reg */ + outb(COM1,0x0c); /* LS of divisor (48 -> 2400 bps */ + outb(COM1+1,0x00); /* MS of divisor */ + outb(COM1+3,0x03); /* reset DLAB */ + outb(COM1+4,0x0b); /* set DTR,RTS, OUT_2 */ + outb(COM1+1,0x0d); /* enable all intrs but writes */ + inb(COM1); /* read data port to reset things (?) */ } /** - * This function read a character from serial without interrupt enable mode + * This function read a character from serial without interrupt enable mode * * @return the read char */ char rt_serial_getc(void) { - while(!(inb(COM1+COMSTATUS) & COMDATA)); - - return inb(COM1+COMREAD); + while(!(inb(COM1+COMSTATUS) & COMDATA)); + + return inb(COM1+COMREAD); } @@ -54,15 +54,15 @@ char rt_serial_getc(void) */ void rt_serial_putc(const char c) { - int val; - - while(1) - { - if ((val = inb(COM1+COMSTATUS)) & THRE) - break; - } - - outb(COM1+COMWRITE, c&0xff); + int val; + + while(1) + { + if ((val = inb(COM1+COMSTATUS)) & THRE) + break; + } + + outb(COM1+COMWRITE, c&0xff); } /*@}*/ diff --git a/bsp/x86/rtconfig.h b/bsp/x86/rtconfig.h index c4cdac1fdc..0353449d56 100644 --- a/bsp/x86/rtconfig.h +++ b/bsp/x86/rtconfig.h @@ -3,16 +3,16 @@ #define __RTTHREAD_CFG_H__ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 8 +#define RT_ALIGN_SIZE 8 /* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 32 +#define RT_THREAD_PRIORITY_MAX 32 /* Tick per Second */ -#define RT_TICK_PER_SECOND 1000 +#define RT_TICK_PER_SECOND 1000 /* SECTION: RT_DEBUG */ /* Thread Debug */ @@ -27,9 +27,9 @@ /* Using Software Timer */ /* #define RT_USING_TIMER_SOFT */ -#define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 512 -#define RT_TIMER_TICK_PER_SECOND 10 +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_TICK_PER_SECOND 10 /* SECTION: IPC */ /* Using Semaphore*/ @@ -64,7 +64,7 @@ /* SECTION: Console options */ #define RT_USING_CONSOLE /* the buffer size of console*/ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 #define IDLE_THREAD_STACK_SIZE 1024 /* idle stack 1K */ @@ -87,16 +87,16 @@ /* Reentrancy (thread safe) of the FatFs module. */ #define RT_DFS_ELM_REENTRANT /* Number of volumes (logical drives) to be used. */ -#define RT_DFS_ELM_DRIVES 2 -/* #define RT_DFS_ELM_USE_LFN 1 */ -#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +/* #define RT_DFS_ELM_USE_LFN 1 */ +#define RT_DFS_ELM_MAX_LFN 255 /* Maximum sector size to be handled. */ #define RT_DFS_ELM_MAX_SECTOR_SIZE 512 /* the max number of mounted filesystem */ -#define DFS_FILESYSTEMS_MAX 2 -/* the max number of opened files */ -#define DFS_FD_MAX 4 +#define DFS_FILESYSTEMS_MAX 2 +/* the max number of opened files */ +#define DFS_FD_MAX 4 #define RT_USING_DFS_DEVFS @@ -112,49 +112,49 @@ #define RT_LWIP_DNS /* the number of simulatenously active TCP connections*/ -#define RT_LWIP_TCP_PCB_NUM 5 +#define RT_LWIP_TCP_PCB_NUM 5 /* Using DHCP */ /* #define RT_LWIP_DHCP */ /* ip address of target*/ -#define RT_LWIP_IPADDR0 192 -#define RT_LWIP_IPADDR1 168 -#define RT_LWIP_IPADDR2 1 -#define RT_LWIP_IPADDR3 30 +#define RT_LWIP_IPADDR0 192 +#define RT_LWIP_IPADDR1 168 +#define RT_LWIP_IPADDR2 1 +#define RT_LWIP_IPADDR3 30 /* gateway address of target*/ -#define RT_LWIP_GWADDR0 192 -#define RT_LWIP_GWADDR1 168 -#define RT_LWIP_GWADDR2 1 -#define RT_LWIP_GWADDR3 1 +#define RT_LWIP_GWADDR0 192 +#define RT_LWIP_GWADDR1 168 +#define RT_LWIP_GWADDR2 1 +#define RT_LWIP_GWADDR3 1 /* mask address of target*/ -#define RT_LWIP_MSKADDR0 255 -#define RT_LWIP_MSKADDR1 255 -#define RT_LWIP_MSKADDR2 255 -#define RT_LWIP_MSKADDR3 0 +#define RT_LWIP_MSKADDR0 255 +#define RT_LWIP_MSKADDR1 255 +#define RT_LWIP_MSKADDR2 255 +#define RT_LWIP_MSKADDR3 0 /* tcp thread options */ -#define RT_LWIP_TCPTHREAD_PRIORITY 12 -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 10 -#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 10 +#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 /* ethernet if thread options */ -#define RT_LWIP_ETHTHREAD_PRIORITY 15 -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 10 -#define RT_LWIP_ETHTHREAD_STACKSIZE 512 +#define RT_LWIP_ETHTHREAD_PRIORITY 15 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 10 +#define RT_LWIP_ETHTHREAD_STACKSIZE 512 /* TCP sender buffer space */ -#define RT_LWIP_TCP_SND_BUF 8192 +#define RT_LWIP_TCP_SND_BUF 8192 /* TCP receive window. */ -#define RT_LWIP_TCP_WND 8192 +#define RT_LWIP_TCP_WND 8192 /* SECTION: RT-Thread/GUI */ /* #define RT_USING_RTGUI */ /* name length of RTGUI object */ -#define RTGUI_NAME_MAX 12 +#define RTGUI_NAME_MAX 12 /* support 16 weight font */ #define RTGUI_USING_FONT16 /* support Chinese font */ @@ -170,7 +170,7 @@ /* use mouse cursor */ /* #define RTGUI_USING_MOUSE_CURSOR */ /* default font size in RTGUI */ -#define RTGUI_DEFAULT_FONT_SIZE 16 +#define RTGUI_DEFAULT_FONT_SIZE 16 /* image support */ /* #define RTGUI_IMAGE_XPM */ diff --git a/bsp/xplorer4330/drivers/drv_uart.c b/bsp/xplorer4330/drivers/drv_uart.c index d220cf7546..ed928426a9 100644 --- a/bsp/xplorer4330/drivers/drv_uart.c +++ b/bsp/xplorer4330/drivers/drv_uart.c @@ -208,8 +208,8 @@ void rt_hw_uart_init(void) config.parity = PARITY_NONE; config.stop_bits = STOP_BITS_1; config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; - + config.bufsz = RT_SERIAL_RB_BUFSZ; + serial0.ops = &lpc_uart_ops; serial0.config = config; @@ -240,7 +240,7 @@ void rt_hw_uart_init(void) LPC_USART0->DLM = 0x00; LPC_USART0->FDR = 0xC1; LPC_USART0->LCR = 0x03; /* DLAB = 0 */ - + /* preemption = 1, sub-priority = 1 */ NVIC_SetPriority(uart->USART_IRQn, ((0x01 << 3) | 0x01)); @@ -260,7 +260,7 @@ void rt_hw_uart_init(void) config.parity = PARITY_NONE; config.stop_bits = STOP_BITS_1; config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; + config.bufsz = RT_SERIAL_RB_BUFSZ; serial2.ops = &lpc_uart_ops; serial2.config = config; diff --git a/components/cplusplus/Lock.h b/components/cplusplus/Lock.h index 08d57c4850..c3cc1d2dae 100644 --- a/components/cplusplus/Lock.h +++ b/components/cplusplus/Lock.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/cplusplus/Mail.h b/components/cplusplus/Mail.h index a4c98e4007..ae3bfb5c41 100644 --- a/components/cplusplus/Mail.h +++ b/components/cplusplus/Mail.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/cplusplus/Mutex.h b/components/cplusplus/Mutex.h index 6fee315155..63efb4a6ea 100644 --- a/components/cplusplus/Mutex.h +++ b/components/cplusplus/Mutex.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/cplusplus/Queue.h b/components/cplusplus/Queue.h index 23a4638798..f6b91e1a21 100644 --- a/components/cplusplus/Queue.h +++ b/components/cplusplus/Queue.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/cplusplus/Semaphore.h b/components/cplusplus/Semaphore.h index cebaf91234..45c916e169 100644 --- a/components/cplusplus/Semaphore.h +++ b/components/cplusplus/Semaphore.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/cplusplus/Thread.h b/components/cplusplus/Thread.h index b578659489..0e681e5c2a 100644 --- a/components/cplusplus/Thread.h +++ b/components/cplusplus/Thread.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/cplusplus/crt.h b/components/cplusplus/crt.h index 84e5a4b820..903d4c86cd 100644 --- a/components/cplusplus/crt.h +++ b/components/cplusplus/crt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/cplusplus/crt_init.c b/components/cplusplus/crt_init.c index fe12932457..a799f36e66 100755 --- a/components/cplusplus/crt_init.c +++ b/components/cplusplus/crt_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/cplusplus/cxx_Mutex.cpp b/components/cplusplus/cxx_Mutex.cpp index 229e842446..293e12e686 100644 --- a/components/cplusplus/cxx_Mutex.cpp +++ b/components/cplusplus/cxx_Mutex.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/cplusplus/cxx_Semaphore.cpp b/components/cplusplus/cxx_Semaphore.cpp index c977a27c1a..c6e3647673 100644 --- a/components/cplusplus/cxx_Semaphore.cpp +++ b/components/cplusplus/cxx_Semaphore.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/cplusplus/cxx_Thread.cpp b/components/cplusplus/cxx_Thread.cpp index b21fbdce1f..c75e566026 100644 --- a/components/cplusplus/cxx_Thread.cpp +++ b/components/cplusplus/cxx_Thread.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/cplusplus/cxx_crt.cpp b/components/cplusplus/cxx_crt.cpp index d4cb84f77c..fa9f2f6022 100644 --- a/components/cplusplus/cxx_crt.cpp +++ b/components/cplusplus/cxx_crt.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/dfs/filesystems/devfs/devfs.c b/components/dfs/filesystems/devfs/devfs.c index e457f18727..2e2248d5cc 100644 --- a/components/dfs/filesystems/devfs/devfs.c +++ b/components/dfs/filesystems/devfs/devfs.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -271,7 +271,7 @@ int dfs_device_fs_getdents(struct dfs_fd *file, struct dirent *dirp, uint32_t co if (count == 0) return -EINVAL; - for (index = 0; index < count && index + root_dirent->read_index < root_dirent->device_count; + for (index = 0; index < count && index + root_dirent->read_index < root_dirent->device_count; index ++) { object = (rt_object_t)root_dirent->devices[root_dirent->read_index + index]; diff --git a/components/dfs/filesystems/devfs/devfs.h b/components/dfs/filesystems/devfs/devfs.h index ab2134043c..30a9482a35 100644 --- a/components/dfs/filesystems/devfs/devfs.h +++ b/components/dfs/filesystems/devfs/devfs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/dfs/filesystems/elmfat/dfs_elm.c b/components/dfs/filesystems/elmfat/dfs_elm.c index b4c4c627aa..c554003eb9 100644 --- a/components/dfs/filesystems/elmfat/dfs_elm.c +++ b/components/dfs/filesystems/elmfat/dfs_elm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/dfs/filesystems/elmfat/dfs_elm.h b/components/dfs/filesystems/elmfat/dfs_elm.h index 1e9f577062..36a49bf18e 100644 --- a/components/dfs/filesystems/elmfat/dfs_elm.h +++ b/components/dfs/filesystems/elmfat/dfs_elm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/dfs/filesystems/nfs/dfs_nfs.c b/components/dfs/filesystems/nfs/dfs_nfs.c index e60f6f98c0..e7ad488f7d 100644 --- a/components/dfs/filesystems/nfs/dfs_nfs.c +++ b/components/dfs/filesystems/nfs/dfs_nfs.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/dfs/filesystems/nfs/dfs_nfs.h b/components/dfs/filesystems/nfs/dfs_nfs.h index d607776ef1..460027410d 100644 --- a/components/dfs/filesystems/nfs/dfs_nfs.h +++ b/components/dfs/filesystems/nfs/dfs_nfs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/dfs/filesystems/nfs/mount.h b/components/dfs/filesystems/nfs/mount.h index aac0fd6bed..ff0cec76fb 100644 --- a/components/dfs/filesystems/nfs/mount.h +++ b/components/dfs/filesystems/nfs/mount.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,7 +12,7 @@ */ #ifndef _MOUNT_H_RPCGEN -#define _MOUNT_H_RPCGEN +#define _MOUNT_H_RPCGEN #include @@ -23,13 +23,13 @@ extern "C" { /* This file is copied from RFC1813 * Copyright 1995 Sun Micrososystems (I assume) */ -#define MNTPATHLEN 1024 -#define MNTNAMLEN 255 -#define FHSIZE3 64 +#define MNTPATHLEN 1024 +#define MNTNAMLEN 255 +#define FHSIZE3 64 typedef struct { - unsigned int fhandle3_len; - char *fhandle3_val; + unsigned int fhandle3_len; + char *fhandle3_val; } fhandle3; typedef char *dirpath; @@ -43,70 +43,70 @@ typedef struct groupnode *groups; typedef struct mountbody *mountlist; enum mountstat3 { - MNT3_OK = 0, - MNT3ERR_PERM = 1, - MNT3ERR_NOENT = 2, - MNT3ERR_IO = 5, - MNT3ERR_ACCES = 13, - MNT3ERR_NOTDIR = 20, - MNT3ERR_INVAL = 22, - MNT3ERR_NAMETOOLONG = 63, - MNT3ERR_NOTSUPP = 10004, - MNT3ERR_SERVERFAULT = 10006 + MNT3_OK = 0, + MNT3ERR_PERM = 1, + MNT3ERR_NOENT = 2, + MNT3ERR_IO = 5, + MNT3ERR_ACCES = 13, + MNT3ERR_NOTDIR = 20, + MNT3ERR_INVAL = 22, + MNT3ERR_NAMETOOLONG = 63, + MNT3ERR_NOTSUPP = 10004, + MNT3ERR_SERVERFAULT = 10006 }; typedef enum mountstat3 mountstat3; struct mountres3_ok { - fhandle3 fhandle; - struct { - unsigned int auth_flavors_len; - int *auth_flavors_val; - } auth_flavors; + fhandle3 fhandle; + struct { + unsigned int auth_flavors_len; + int *auth_flavors_val; + } auth_flavors; }; typedef struct mountres3_ok mountres3_ok; struct mountres3 { - mountstat3 fhs_status; - union { - mountres3_ok mountinfo; - } mountres3_u; + mountstat3 fhs_status; + union { + mountres3_ok mountinfo; + } mountres3_u; }; typedef struct mountres3 mountres3; struct mountbody { - name ml_hostname; - dirpath ml_directory; - mountlist ml_next; + name ml_hostname; + dirpath ml_directory; + mountlist ml_next; }; typedef struct mountbody mountbody; struct groupnode { - name gr_name; - groups gr_next; + name gr_name; + groups gr_next; }; typedef struct groupnode groupnode; struct exportnode { - dirpath ex_dir; - groups ex_groups; - exports ex_next; + dirpath ex_dir; + groups ex_groups; + exports ex_next; }; typedef struct exportnode exportnode; -#define MOUNT_PROGRAM 100005 -#define MOUNT_V3 3 +#define MOUNT_PROGRAM 100005 +#define MOUNT_V3 3 -#define MOUNTPROC3_NULL 0 +#define MOUNTPROC3_NULL 0 extern enum clnt_stat mountproc3_null_3(void *, CLIENT *); -#define MOUNTPROC3_MNT 1 +#define MOUNTPROC3_MNT 1 extern enum clnt_stat mountproc3_mnt_3(dirpath , mountres3 *, CLIENT *); -#define MOUNTPROC3_DUMP 2 +#define MOUNTPROC3_DUMP 2 extern enum clnt_stat mountproc3_dump_3(mountlist *, CLIENT *); -#define MOUNTPROC3_UMNT 3 +#define MOUNTPROC3_UMNT 3 extern enum clnt_stat mountproc3_umnt_3(dirpath , void *, CLIENT *); -#define MOUNTPROC3_UMNTALL 4 +#define MOUNTPROC3_UMNTALL 4 extern enum clnt_stat mountproc3_umntall_3(void *, CLIENT *); -#define MOUNTPROC3_EXPORT 5 +#define MOUNTPROC3_EXPORT 5 extern enum clnt_stat mountproc3_export_3(exports *, CLIENT *); /* the xdr functions */ diff --git a/components/dfs/filesystems/nfs/mount_clnt.c b/components/dfs/filesystems/nfs/mount_clnt.c index 5c65e75aa5..9e05f7ee61 100644 --- a/components/dfs/filesystems/nfs/mount_clnt.c +++ b/components/dfs/filesystems/nfs/mount_clnt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -23,56 +23,56 @@ typedef char* caddr_t; /* Default timeout can be changed using clnt_control() */ static struct timeval TIMEOUT = { 25, 0 }; -enum clnt_stat +enum clnt_stat mountproc3_null_3(void *clnt_res, CLIENT *clnt) { - return (clnt_call(clnt, MOUNTPROC3_NULL, - (xdrproc_t) xdr_void, (caddr_t) NULL, - (xdrproc_t) xdr_void, (caddr_t) clnt_res, - TIMEOUT)); + return (clnt_call(clnt, MOUNTPROC3_NULL, + (xdrproc_t) xdr_void, (caddr_t) NULL, + (xdrproc_t) xdr_void, (caddr_t) clnt_res, + TIMEOUT)); } -enum clnt_stat +enum clnt_stat mountproc3_mnt_3(dirpath arg1, mountres3 *clnt_res, CLIENT *clnt) { - return (clnt_call(clnt, MOUNTPROC3_MNT, - (xdrproc_t) xdr_dirpath, (caddr_t) &arg1, - (xdrproc_t) xdr_mountres3, (caddr_t) clnt_res, - TIMEOUT)); + return (clnt_call(clnt, MOUNTPROC3_MNT, + (xdrproc_t) xdr_dirpath, (caddr_t) &arg1, + (xdrproc_t) xdr_mountres3, (caddr_t) clnt_res, + TIMEOUT)); } -enum clnt_stat +enum clnt_stat mountproc3_dump_3(mountlist *clnt_res, CLIENT *clnt) { - return (clnt_call(clnt, MOUNTPROC3_DUMP, - (xdrproc_t) xdr_void, (caddr_t) NULL, - (xdrproc_t) xdr_mountlist, (caddr_t) clnt_res, - TIMEOUT)); + return (clnt_call(clnt, MOUNTPROC3_DUMP, + (xdrproc_t) xdr_void, (caddr_t) NULL, + (xdrproc_t) xdr_mountlist, (caddr_t) clnt_res, + TIMEOUT)); } -enum clnt_stat +enum clnt_stat mountproc3_umnt_3(dirpath arg1, void *clnt_res, CLIENT *clnt) { - return (clnt_call(clnt, MOUNTPROC3_UMNT, - (xdrproc_t) xdr_dirpath, (caddr_t) &arg1, - (xdrproc_t) xdr_void, (caddr_t) clnt_res, - TIMEOUT)); + return (clnt_call(clnt, MOUNTPROC3_UMNT, + (xdrproc_t) xdr_dirpath, (caddr_t) &arg1, + (xdrproc_t) xdr_void, (caddr_t) clnt_res, + TIMEOUT)); } -enum clnt_stat +enum clnt_stat mountproc3_umntall_3(void *clnt_res, CLIENT *clnt) { - return (clnt_call(clnt, MOUNTPROC3_UMNTALL, - (xdrproc_t) xdr_void, (caddr_t) NULL, - (xdrproc_t) xdr_void, (caddr_t) clnt_res, - TIMEOUT)); + return (clnt_call(clnt, MOUNTPROC3_UMNTALL, + (xdrproc_t) xdr_void, (caddr_t) NULL, + (xdrproc_t) xdr_void, (caddr_t) clnt_res, + TIMEOUT)); } -enum clnt_stat +enum clnt_stat mountproc3_export_3(exports *clnt_res, CLIENT *clnt) { - return (clnt_call(clnt, MOUNTPROC3_EXPORT, - (xdrproc_t) xdr_void, (caddr_t) NULL, - (xdrproc_t) xdr_exports, (caddr_t) clnt_res, - TIMEOUT)); + return (clnt_call(clnt, MOUNTPROC3_EXPORT, + (xdrproc_t) xdr_void, (caddr_t) NULL, + (xdrproc_t) xdr_exports, (caddr_t) clnt_res, + TIMEOUT)); } diff --git a/components/dfs/filesystems/nfs/mount_xdr.c b/components/dfs/filesystems/nfs/mount_xdr.c index 04faa3bb7a..e1e797000f 100644 --- a/components/dfs/filesystems/nfs/mount_xdr.c +++ b/components/dfs/filesystems/nfs/mount_xdr.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -19,124 +19,124 @@ bool_t xdr_fhandle3(register XDR *xdrs, fhandle3 *objp) { - if (!xdr_bytes(xdrs, (char **)&objp->fhandle3_val, (unsigned int *) &objp->fhandle3_len, FHSIZE3)) - return (FALSE); - return (TRUE); + if (!xdr_bytes(xdrs, (char **)&objp->fhandle3_val, (unsigned int *) &objp->fhandle3_len, FHSIZE3)) + return (FALSE); + return (TRUE); } bool_t xdr_dirpath(register XDR *xdrs, dirpath *objp) { - if (!xdr_string(xdrs, objp, MNTPATHLEN)) - return (FALSE); - return (TRUE); + if (!xdr_string(xdrs, objp, MNTPATHLEN)) + return (FALSE); + return (TRUE); } bool_t xdr_name(register XDR *xdrs, name *objp) { - if (!xdr_string(xdrs, objp, MNTNAMLEN)) - return (FALSE); - return (TRUE); + if (!xdr_string(xdrs, objp, MNTNAMLEN)) + return (FALSE); + return (TRUE); } bool_t xdr_exports(register XDR *xdrs, exports *objp) { - if (!xdr_pointer(xdrs, (char **)objp, sizeof (struct exportnode), (xdrproc_t) xdr_exportnode)) - return (FALSE); - return (TRUE); + if (!xdr_pointer(xdrs, (char **)objp, sizeof (struct exportnode), (xdrproc_t) xdr_exportnode)) + return (FALSE); + return (TRUE); } bool_t xdr_groups(register XDR *xdrs, groups *objp) { - if (!xdr_pointer(xdrs, (char **)objp, sizeof (struct groupnode), (xdrproc_t) xdr_groupnode)) - return (FALSE); - return (TRUE); + if (!xdr_pointer(xdrs, (char **)objp, sizeof (struct groupnode), (xdrproc_t) xdr_groupnode)) + return (FALSE); + return (TRUE); } bool_t xdr_mountlist(register XDR *xdrs, mountlist *objp) { - if (!xdr_pointer(xdrs, (char **)objp, sizeof (struct mountbody), (xdrproc_t) xdr_mountbody)) - return (FALSE); - return (TRUE); + if (!xdr_pointer(xdrs, (char **)objp, sizeof (struct mountbody), (xdrproc_t) xdr_mountbody)) + return (FALSE); + return (TRUE); } bool_t xdr_mountstat3(register XDR *xdrs, mountstat3 *objp) { - int enum_objp; + int enum_objp; - enum_objp = *objp; + enum_objp = *objp; - if (!xdr_enum(xdrs, (enum_t *)&enum_objp)) - { - *objp = (mountstat3)enum_objp; - return (FALSE); - } + if (!xdr_enum(xdrs, (enum_t *)&enum_objp)) + { + *objp = (mountstat3)enum_objp; + return (FALSE); + } - return (TRUE); + return (TRUE); } bool_t xdr_mountres3_ok(register XDR *xdrs, mountres3_ok *objp) { - if (!xdr_fhandle3(xdrs, &objp->fhandle)) - return (FALSE); - if (!xdr_array(xdrs, (char **)&objp->auth_flavors.auth_flavors_val, (unsigned int *) &objp->auth_flavors.auth_flavors_len, ~0, - sizeof (int), (xdrproc_t) xdr_int)) - return (FALSE); - return (TRUE); + if (!xdr_fhandle3(xdrs, &objp->fhandle)) + return (FALSE); + if (!xdr_array(xdrs, (char **)&objp->auth_flavors.auth_flavors_val, (unsigned int *) &objp->auth_flavors.auth_flavors_len, ~0, + sizeof (int), (xdrproc_t) xdr_int)) + return (FALSE); + return (TRUE); } bool_t xdr_mountres3(register XDR *xdrs, mountres3 *objp) { - if (!xdr_mountstat3(xdrs, &objp->fhs_status)) - return (FALSE); - switch (objp->fhs_status) { - case MNT3_OK: - if (!xdr_mountres3_ok(xdrs, &objp->mountres3_u.mountinfo)) - return (FALSE); - break; - default : - return (FALSE); - } - return (TRUE); + if (!xdr_mountstat3(xdrs, &objp->fhs_status)) + return (FALSE); + switch (objp->fhs_status) { + case MNT3_OK: + if (!xdr_mountres3_ok(xdrs, &objp->mountres3_u.mountinfo)) + return (FALSE); + break; + default : + return (FALSE); + } + return (TRUE); } bool_t xdr_mountbody(register XDR *xdrs, mountbody *objp) { - if (!xdr_name(xdrs, &objp->ml_hostname)) - return (FALSE); - if (!xdr_dirpath(xdrs, &objp->ml_directory)) - return (FALSE); - if (!xdr_mountlist(xdrs, &objp->ml_next)) - return (FALSE); - return (TRUE); + if (!xdr_name(xdrs, &objp->ml_hostname)) + return (FALSE); + if (!xdr_dirpath(xdrs, &objp->ml_directory)) + return (FALSE); + if (!xdr_mountlist(xdrs, &objp->ml_next)) + return (FALSE); + return (TRUE); } bool_t xdr_groupnode(register XDR *xdrs, groupnode *objp) { - if (!xdr_name(xdrs, &objp->gr_name)) - return (FALSE); - if (!xdr_groups(xdrs, &objp->gr_next)) - return (FALSE); - return (TRUE); + if (!xdr_name(xdrs, &objp->gr_name)) + return (FALSE); + if (!xdr_groups(xdrs, &objp->gr_next)) + return (FALSE); + return (TRUE); } bool_t xdr_exportnode(register XDR *xdrs, exportnode *objp) { - if (!xdr_dirpath(xdrs, &objp->ex_dir)) - return (FALSE); - if (!xdr_groups(xdrs, &objp->ex_groups)) - return (FALSE); - if (!xdr_exports(xdrs, &objp->ex_next)) - return (FALSE); - return (TRUE); + if (!xdr_dirpath(xdrs, &objp->ex_dir)) + return (FALSE); + if (!xdr_groups(xdrs, &objp->ex_groups)) + return (FALSE); + if (!xdr_exports(xdrs, &objp->ex_next)) + return (FALSE); + return (TRUE); } diff --git a/components/dfs/filesystems/nfs/nfs.h b/components/dfs/filesystems/nfs/nfs.h index 34054b0084..8c417ec7f4 100644 --- a/components/dfs/filesystems/nfs/nfs.h +++ b/components/dfs/filesystems/nfs/nfs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,7 +12,7 @@ */ #ifndef _NFS_H_RPCGEN -#define _NFS_H_RPCGEN +#define _NFS_H_RPCGEN #include @@ -23,20 +23,20 @@ extern "C" { /* This file is copied from RFC1813 * Copyright 1995 Sun Micrososystems (I assume) */ -#define NFS3_FHSIZE 64 -#define NFS3_COOKIEVERFSIZE 8 -#define NFS3_CREATEVERFSIZE 8 -#define NFS3_WRITEVERFSIZE 8 -#define ACCESS3_READ 0x0001 -#define ACCESS3_LOOKUP 0x0002 -#define ACCESS3_MODIFY 0x0004 -#define ACCESS3_EXTEND 0x0008 -#define ACCESS3_DELETE 0x0010 -#define ACCESS3_EXECUTE 0x0020 -#define FSF3_LINK 0x0001 -#define FSF3_SYMLINK 0x0002 -#define FSF3_HOMOGENEOUS 0x0008 -#define FSF3_CANSETTIME 0x0010 +#define NFS3_FHSIZE 64 +#define NFS3_COOKIEVERFSIZE 8 +#define NFS3_CREATEVERFSIZE 8 +#define NFS3_WRITEVERFSIZE 8 +#define ACCESS3_READ 0x0001 +#define ACCESS3_LOOKUP 0x0002 +#define ACCESS3_MODIFY 0x0004 +#define ACCESS3_EXTEND 0x0008 +#define ACCESS3_DELETE 0x0010 +#define ACCESS3_EXECUTE 0x0020 +#define FSF3_LINK 0x0001 +#define FSF3_SYMLINK 0x0002 +#define FSF3_HOMOGENEOUS 0x0008 +#define FSF3_CANSETTIME 0x0010 typedef unsigned long long uint64; @@ -73,900 +73,900 @@ typedef uint32 mode3; typedef uint32 count3; enum nfsstat3 { - NFS3_OK = 0, - NFS3ERR_PERM = 1, - NFS3ERR_NOENT = 2, - NFS3ERR_IO = 5, - NFS3ERR_NXIO = 6, - NFS3ERR_ACCES = 13, - NFS3ERR_EXIST = 17, - NFS3ERR_XDEV = 18, - NFS3ERR_NODEV = 19, - NFS3ERR_NOTDIR = 20, - NFS3ERR_ISDIR = 21, - NFS3ERR_INVAL = 22, - NFS3ERR_FBIG = 27, - NFS3ERR_NOSPC = 28, - NFS3ERR_ROFS = 30, - NFS3ERR_MLINK = 31, - NFS3ERR_NAMETOOLONG = 63, - NFS3ERR_NOTEMPTY = 66, - NFS3ERR_DQUOT = 69, - NFS3ERR_STALE = 70, - NFS3ERR_REMOTE = 71, - NFS3ERR_BADHANDLE = 10001, - NFS3ERR_NOT_SYNC = 10002, - NFS3ERR_BAD_COOKIE = 10003, - NFS3ERR_NOTSUPP = 10004, - NFS3ERR_TOOSMALL = 10005, - NFS3ERR_SERVERFAULT = 10006, - NFS3ERR_BADTYPE = 10007, - NFS3ERR_JUKEBOX = 10008 + NFS3_OK = 0, + NFS3ERR_PERM = 1, + NFS3ERR_NOENT = 2, + NFS3ERR_IO = 5, + NFS3ERR_NXIO = 6, + NFS3ERR_ACCES = 13, + NFS3ERR_EXIST = 17, + NFS3ERR_XDEV = 18, + NFS3ERR_NODEV = 19, + NFS3ERR_NOTDIR = 20, + NFS3ERR_ISDIR = 21, + NFS3ERR_INVAL = 22, + NFS3ERR_FBIG = 27, + NFS3ERR_NOSPC = 28, + NFS3ERR_ROFS = 30, + NFS3ERR_MLINK = 31, + NFS3ERR_NAMETOOLONG = 63, + NFS3ERR_NOTEMPTY = 66, + NFS3ERR_DQUOT = 69, + NFS3ERR_STALE = 70, + NFS3ERR_REMOTE = 71, + NFS3ERR_BADHANDLE = 10001, + NFS3ERR_NOT_SYNC = 10002, + NFS3ERR_BAD_COOKIE = 10003, + NFS3ERR_NOTSUPP = 10004, + NFS3ERR_TOOSMALL = 10005, + NFS3ERR_SERVERFAULT = 10006, + NFS3ERR_BADTYPE = 10007, + NFS3ERR_JUKEBOX = 10008 }; typedef enum nfsstat3 nfsstat3; enum ftype3 { - NFS3REG = 1, - NFS3DIR = 2, - NFS3BLK = 3, - NFS3CHR = 4, - NFS3LNK = 5, - NFS3SOCK = 6, - NFS3FIFO = 7 + NFS3REG = 1, + NFS3DIR = 2, + NFS3BLK = 3, + NFS3CHR = 4, + NFS3LNK = 5, + NFS3SOCK = 6, + NFS3FIFO = 7 }; typedef enum ftype3 ftype3; enum stable_how { - UNSTABLE = 0, - DATA_SYNC = 1, - FILE_SYNC = 2 + UNSTABLE = 0, + DATA_SYNC = 1, + FILE_SYNC = 2 }; typedef enum stable_how stable_how; enum createmode3 { - UNCHECKED = 0, - GUARDED = 1, - EXCLUSIVE = 2 + UNCHECKED = 0, + GUARDED = 1, + EXCLUSIVE = 2 }; typedef enum createmode3 createmode3; struct specdata3 { - uint32 specdata1; - uint32 specdata2; + uint32 specdata1; + uint32 specdata2; }; typedef struct specdata3 specdata3; struct nfs_fh3 { - struct { - unsigned int data_len; - char *data_val; - } data; + struct { + unsigned int data_len; + char *data_val; + } data; }; typedef struct nfs_fh3 nfs_fh3; struct nfstime3 { - uint32 seconds; - uint32 nseconds; + uint32 seconds; + uint32 nseconds; }; typedef struct nfstime3 nfstime3; struct fattr3 { - ftype3 type; - mode3 mode; - uint32 nlink; - uid3 uid; - gid3 gid; - size3 size; - size3 used; - specdata3 rdev; - uint64 fsid; - fileid3 fileid; - nfstime3 atime; - nfstime3 mtime; - nfstime3 ctime; + ftype3 type; + mode3 mode; + uint32 nlink; + uid3 uid; + gid3 gid; + size3 size; + size3 used; + specdata3 rdev; + uint64 fsid; + fileid3 fileid; + nfstime3 atime; + nfstime3 mtime; + nfstime3 ctime; }; typedef struct fattr3 fattr3; struct post_op_attr { - bool_t attributes_follow; - union { - fattr3 attributes; - } post_op_attr_u; + bool_t attributes_follow; + union { + fattr3 attributes; + } post_op_attr_u; }; typedef struct post_op_attr post_op_attr; struct wcc_attr { - size3 size; - nfstime3 mtime; - nfstime3 ctime; + size3 size; + nfstime3 mtime; + nfstime3 ctime; }; typedef struct wcc_attr wcc_attr; struct pre_op_attr { - bool_t attributes_follow; - union { - wcc_attr attributes; - } pre_op_attr_u; + bool_t attributes_follow; + union { + wcc_attr attributes; + } pre_op_attr_u; }; typedef struct pre_op_attr pre_op_attr; struct wcc_data { - pre_op_attr before; - post_op_attr after; + pre_op_attr before; + post_op_attr after; }; typedef struct wcc_data wcc_data; struct post_op_fh3 { - bool_t handle_follows; - union { - nfs_fh3 handle; - } post_op_fh3_u; + bool_t handle_follows; + union { + nfs_fh3 handle; + } post_op_fh3_u; }; typedef struct post_op_fh3 post_op_fh3; enum time_how { - DONT_CHANGE = 0, - SET_TO_SERVER_TIME = 1, - SET_TO_CLIENT_TIME = 2 + DONT_CHANGE = 0, + SET_TO_SERVER_TIME = 1, + SET_TO_CLIENT_TIME = 2 }; typedef enum time_how time_how; struct set_mode3 { - bool_t set_it; - union { - mode3 mode; - } set_mode3_u; + bool_t set_it; + union { + mode3 mode; + } set_mode3_u; }; typedef struct set_mode3 set_mode3; struct set_uid3 { - bool_t set_it; - union { - uid3 uid; - } set_uid3_u; + bool_t set_it; + union { + uid3 uid; + } set_uid3_u; }; typedef struct set_uid3 set_uid3; struct set_gid3 { - bool_t set_it; - union { - gid3 gid; - } set_gid3_u; + bool_t set_it; + union { + gid3 gid; + } set_gid3_u; }; typedef struct set_gid3 set_gid3; struct set_size3 { - bool_t set_it; - union { - size3 size; - } set_size3_u; + bool_t set_it; + union { + size3 size; + } set_size3_u; }; typedef struct set_size3 set_size3; struct set_atime { - time_how set_it; - union { - nfstime3 atime; - } set_atime_u; + time_how set_it; + union { + nfstime3 atime; + } set_atime_u; }; typedef struct set_atime set_atime; struct set_mtime { - time_how set_it; - union { - nfstime3 mtime; - } set_mtime_u; + time_how set_it; + union { + nfstime3 mtime; + } set_mtime_u; }; typedef struct set_mtime set_mtime; struct sattr3 { - set_mode3 mode; - set_uid3 uid; - set_gid3 gid; - set_size3 size; - set_atime atime; - set_mtime mtime; + set_mode3 mode; + set_uid3 uid; + set_gid3 gid; + set_size3 size; + set_atime atime; + set_mtime mtime; }; typedef struct sattr3 sattr3; struct diropargs3 { - nfs_fh3 dir; - filename3 name; + nfs_fh3 dir; + filename3 name; }; typedef struct diropargs3 diropargs3; struct GETATTR3args { - nfs_fh3 object; + nfs_fh3 object; }; typedef struct GETATTR3args GETATTR3args; struct GETATTR3resok { - fattr3 obj_attributes; + fattr3 obj_attributes; }; typedef struct GETATTR3resok GETATTR3resok; struct GETATTR3res { - nfsstat3 status; - union { - GETATTR3resok resok; - } GETATTR3res_u; + nfsstat3 status; + union { + GETATTR3resok resok; + } GETATTR3res_u; }; typedef struct GETATTR3res GETATTR3res; struct sattrguard3 { - bool_t check; - union { - nfstime3 obj_ctime; - } sattrguard3_u; + bool_t check; + union { + nfstime3 obj_ctime; + } sattrguard3_u; }; typedef struct sattrguard3 sattrguard3; struct SETATTR3args { - nfs_fh3 object; - sattr3 new_attributes; - sattrguard3 guard; + nfs_fh3 object; + sattr3 new_attributes; + sattrguard3 guard; }; typedef struct SETATTR3args SETATTR3args; struct SETATTR3resok { - wcc_data obj_wcc; + wcc_data obj_wcc; }; typedef struct SETATTR3resok SETATTR3resok; struct SETATTR3resfail { - wcc_data obj_wcc; + wcc_data obj_wcc; }; typedef struct SETATTR3resfail SETATTR3resfail; struct SETATTR3res { - nfsstat3 status; - union { - SETATTR3resok resok; - SETATTR3resfail resfail; - } SETATTR3res_u; + nfsstat3 status; + union { + SETATTR3resok resok; + SETATTR3resfail resfail; + } SETATTR3res_u; }; typedef struct SETATTR3res SETATTR3res; struct LOOKUP3args { - diropargs3 what; + diropargs3 what; }; typedef struct LOOKUP3args LOOKUP3args; struct LOOKUP3resok { - nfs_fh3 object; - post_op_attr obj_attributes; - post_op_attr dir_attributes; + nfs_fh3 object; + post_op_attr obj_attributes; + post_op_attr dir_attributes; }; typedef struct LOOKUP3resok LOOKUP3resok; struct LOOKUP3resfail { - post_op_attr dir_attributes; + post_op_attr dir_attributes; }; typedef struct LOOKUP3resfail LOOKUP3resfail; struct LOOKUP3res { - nfsstat3 status; - union { - LOOKUP3resok resok; - LOOKUP3resfail resfail; - } LOOKUP3res_u; + nfsstat3 status; + union { + LOOKUP3resok resok; + LOOKUP3resfail resfail; + } LOOKUP3res_u; }; typedef struct LOOKUP3res LOOKUP3res; struct ACCESS3args { - nfs_fh3 object; - uint32 access; + nfs_fh3 object; + uint32 access; }; typedef struct ACCESS3args ACCESS3args; struct ACCESS3resok { - post_op_attr obj_attributes; - uint32 access; + post_op_attr obj_attributes; + uint32 access; }; typedef struct ACCESS3resok ACCESS3resok; struct ACCESS3resfail { - post_op_attr obj_attributes; + post_op_attr obj_attributes; }; typedef struct ACCESS3resfail ACCESS3resfail; struct ACCESS3res { - nfsstat3 status; - union { - ACCESS3resok resok; - ACCESS3resfail resfail; - } ACCESS3res_u; + nfsstat3 status; + union { + ACCESS3resok resok; + ACCESS3resfail resfail; + } ACCESS3res_u; }; typedef struct ACCESS3res ACCESS3res; struct READLINK3args { - nfs_fh3 symlink; + nfs_fh3 symlink; }; typedef struct READLINK3args READLINK3args; struct READLINK3resok { - post_op_attr symlink_attributes; - nfspath3 data; + post_op_attr symlink_attributes; + nfspath3 data; }; typedef struct READLINK3resok READLINK3resok; struct READLINK3resfail { - post_op_attr symlink_attributes; + post_op_attr symlink_attributes; }; typedef struct READLINK3resfail READLINK3resfail; struct READLINK3res { - nfsstat3 status; - union { - READLINK3resok resok; - READLINK3resfail resfail; - } READLINK3res_u; + nfsstat3 status; + union { + READLINK3resok resok; + READLINK3resfail resfail; + } READLINK3res_u; }; typedef struct READLINK3res READLINK3res; struct READ3args { - nfs_fh3 file; - offset3 offset; - count3 count; + nfs_fh3 file; + offset3 offset; + count3 count; }; typedef struct READ3args READ3args; struct READ3resok { - post_op_attr file_attributes; - count3 count; - bool_t eof; - struct { - unsigned int data_len; - char *data_val; - } data; + post_op_attr file_attributes; + count3 count; + bool_t eof; + struct { + unsigned int data_len; + char *data_val; + } data; }; typedef struct READ3resok READ3resok; struct READ3resfail { - post_op_attr file_attributes; + post_op_attr file_attributes; }; typedef struct READ3resfail READ3resfail; struct READ3res { - nfsstat3 status; - union { - READ3resok resok; - READ3resfail resfail; - } READ3res_u; + nfsstat3 status; + union { + READ3resok resok; + READ3resfail resfail; + } READ3res_u; }; typedef struct READ3res READ3res; struct WRITE3args { - nfs_fh3 file; - offset3 offset; - count3 count; - stable_how stable; - struct { - unsigned int data_len; - char *data_val; - } data; + nfs_fh3 file; + offset3 offset; + count3 count; + stable_how stable; + struct { + unsigned int data_len; + char *data_val; + } data; }; typedef struct WRITE3args WRITE3args; struct WRITE3resok { - wcc_data file_wcc; - count3 count; - stable_how committed; - writeverf3 verf; + wcc_data file_wcc; + count3 count; + stable_how committed; + writeverf3 verf; }; typedef struct WRITE3resok WRITE3resok; struct WRITE3resfail { - wcc_data file_wcc; + wcc_data file_wcc; }; typedef struct WRITE3resfail WRITE3resfail; struct WRITE3res { - nfsstat3 status; - union { - WRITE3resok resok; - WRITE3resfail resfail; - } WRITE3res_u; + nfsstat3 status; + union { + WRITE3resok resok; + WRITE3resfail resfail; + } WRITE3res_u; }; typedef struct WRITE3res WRITE3res; struct createhow3 { - createmode3 mode; - union { - sattr3 obj_attributes; - createverf3 verf; - } createhow3_u; + createmode3 mode; + union { + sattr3 obj_attributes; + createverf3 verf; + } createhow3_u; }; typedef struct createhow3 createhow3; struct CREATE3args { - diropargs3 where; - createhow3 how; + diropargs3 where; + createhow3 how; }; typedef struct CREATE3args CREATE3args; struct CREATE3resok { - post_op_fh3 obj; - post_op_attr obj_attributes; - wcc_data dir_wcc; + post_op_fh3 obj; + post_op_attr obj_attributes; + wcc_data dir_wcc; }; typedef struct CREATE3resok CREATE3resok; struct CREATE3resfail { - wcc_data dir_wcc; + wcc_data dir_wcc; }; typedef struct CREATE3resfail CREATE3resfail; struct CREATE3res { - nfsstat3 status; - union { - CREATE3resok resok; - CREATE3resfail resfail; - } CREATE3res_u; + nfsstat3 status; + union { + CREATE3resok resok; + CREATE3resfail resfail; + } CREATE3res_u; }; typedef struct CREATE3res CREATE3res; struct MKDIR3args { - diropargs3 where; - sattr3 attributes; + diropargs3 where; + sattr3 attributes; }; typedef struct MKDIR3args MKDIR3args; struct MKDIR3resok { - post_op_fh3 obj; - post_op_attr obj_attributes; - wcc_data dir_wcc; + post_op_fh3 obj; + post_op_attr obj_attributes; + wcc_data dir_wcc; }; typedef struct MKDIR3resok MKDIR3resok; struct MKDIR3resfail { - wcc_data dir_wcc; + wcc_data dir_wcc; }; typedef struct MKDIR3resfail MKDIR3resfail; struct MKDIR3res { - nfsstat3 status; - union { - MKDIR3resok resok; - MKDIR3resfail resfail; - } MKDIR3res_u; + nfsstat3 status; + union { + MKDIR3resok resok; + MKDIR3resfail resfail; + } MKDIR3res_u; }; typedef struct MKDIR3res MKDIR3res; struct symlinkdata3 { - sattr3 symlink_attributes; - nfspath3 symlink_data; + sattr3 symlink_attributes; + nfspath3 symlink_data; }; typedef struct symlinkdata3 symlinkdata3; struct SYMLINK3args { - diropargs3 where; - symlinkdata3 symlink; + diropargs3 where; + symlinkdata3 symlink; }; typedef struct SYMLINK3args SYMLINK3args; struct SYMLINK3resok { - post_op_fh3 obj; - post_op_attr obj_attributes; - wcc_data dir_wcc; + post_op_fh3 obj; + post_op_attr obj_attributes; + wcc_data dir_wcc; }; typedef struct SYMLINK3resok SYMLINK3resok; struct SYMLINK3resfail { - wcc_data dir_wcc; + wcc_data dir_wcc; }; typedef struct SYMLINK3resfail SYMLINK3resfail; struct SYMLINK3res { - nfsstat3 status; - union { - SYMLINK3resok resok; - SYMLINK3resfail resfail; - } SYMLINK3res_u; + nfsstat3 status; + union { + SYMLINK3resok resok; + SYMLINK3resfail resfail; + } SYMLINK3res_u; }; typedef struct SYMLINK3res SYMLINK3res; struct devicedata3 { - sattr3 dev_attributes; - specdata3 spec; + sattr3 dev_attributes; + specdata3 spec; }; typedef struct devicedata3 devicedata3; struct mknoddata3 { - ftype3 type; - union { - devicedata3 device; - sattr3 pipe_attributes; - } mknoddata3_u; + ftype3 type; + union { + devicedata3 device; + sattr3 pipe_attributes; + } mknoddata3_u; }; typedef struct mknoddata3 mknoddata3; struct MKNOD3args { - diropargs3 where; - mknoddata3 what; + diropargs3 where; + mknoddata3 what; }; typedef struct MKNOD3args MKNOD3args; struct MKNOD3resok { - post_op_fh3 obj; - post_op_attr obj_attributes; - wcc_data dir_wcc; + post_op_fh3 obj; + post_op_attr obj_attributes; + wcc_data dir_wcc; }; typedef struct MKNOD3resok MKNOD3resok; struct MKNOD3resfail { - wcc_data dir_wcc; + wcc_data dir_wcc; }; typedef struct MKNOD3resfail MKNOD3resfail; struct MKNOD3res { - nfsstat3 status; - union { - MKNOD3resok resok; - MKNOD3resfail resfail; - } MKNOD3res_u; + nfsstat3 status; + union { + MKNOD3resok resok; + MKNOD3resfail resfail; + } MKNOD3res_u; }; typedef struct MKNOD3res MKNOD3res; struct REMOVE3args { - diropargs3 object; + diropargs3 object; }; typedef struct REMOVE3args REMOVE3args; struct REMOVE3resok { - wcc_data dir_wcc; + wcc_data dir_wcc; }; typedef struct REMOVE3resok REMOVE3resok; struct REMOVE3resfail { - wcc_data dir_wcc; + wcc_data dir_wcc; }; typedef struct REMOVE3resfail REMOVE3resfail; struct REMOVE3res { - nfsstat3 status; - union { - REMOVE3resok resok; - REMOVE3resfail resfail; - } REMOVE3res_u; + nfsstat3 status; + union { + REMOVE3resok resok; + REMOVE3resfail resfail; + } REMOVE3res_u; }; typedef struct REMOVE3res REMOVE3res; struct RMDIR3args { - diropargs3 object; + diropargs3 object; }; typedef struct RMDIR3args RMDIR3args; struct RMDIR3resok { - wcc_data dir_wcc; + wcc_data dir_wcc; }; typedef struct RMDIR3resok RMDIR3resok; struct RMDIR3resfail { - wcc_data dir_wcc; + wcc_data dir_wcc; }; typedef struct RMDIR3resfail RMDIR3resfail; struct RMDIR3res { - nfsstat3 status; - union { - RMDIR3resok resok; - RMDIR3resfail resfail; - } RMDIR3res_u; + nfsstat3 status; + union { + RMDIR3resok resok; + RMDIR3resfail resfail; + } RMDIR3res_u; }; typedef struct RMDIR3res RMDIR3res; struct RENAME3args { - diropargs3 from; - diropargs3 to; + diropargs3 from; + diropargs3 to; }; typedef struct RENAME3args RENAME3args; struct RENAME3resok { - wcc_data fromdir_wcc; - wcc_data todir_wcc; + wcc_data fromdir_wcc; + wcc_data todir_wcc; }; typedef struct RENAME3resok RENAME3resok; struct RENAME3resfail { - wcc_data fromdir_wcc; - wcc_data todir_wcc; + wcc_data fromdir_wcc; + wcc_data todir_wcc; }; typedef struct RENAME3resfail RENAME3resfail; struct RENAME3res { - nfsstat3 status; - union { - RENAME3resok resok; - RENAME3resfail resfail; - } RENAME3res_u; + nfsstat3 status; + union { + RENAME3resok resok; + RENAME3resfail resfail; + } RENAME3res_u; }; typedef struct RENAME3res RENAME3res; struct LINK3args { - nfs_fh3 file; - diropargs3 link; + nfs_fh3 file; + diropargs3 link; }; typedef struct LINK3args LINK3args; struct LINK3resok { - post_op_attr file_attributes; - wcc_data linkdir_wcc; + post_op_attr file_attributes; + wcc_data linkdir_wcc; }; typedef struct LINK3resok LINK3resok; struct LINK3resfail { - post_op_attr file_attributes; - wcc_data linkdir_wcc; + post_op_attr file_attributes; + wcc_data linkdir_wcc; }; typedef struct LINK3resfail LINK3resfail; struct LINK3res { - nfsstat3 status; - union { - LINK3resok resok; - LINK3resfail resfail; - } LINK3res_u; + nfsstat3 status; + union { + LINK3resok resok; + LINK3resfail resfail; + } LINK3res_u; }; typedef struct LINK3res LINK3res; struct READDIR3args { - nfs_fh3 dir; - cookie3 cookie; - cookieverf3 cookieverf; - count3 count; + nfs_fh3 dir; + cookie3 cookie; + cookieverf3 cookieverf; + count3 count; }; typedef struct READDIR3args READDIR3args; struct entry3 { - fileid3 fileid; - filename3 name; - cookie3 cookie; - struct entry3 *nextentry; + fileid3 fileid; + filename3 name; + cookie3 cookie; + struct entry3 *nextentry; }; typedef struct entry3 entry3; struct dirlist3 { - entry3 *entries; - bool_t eof; + entry3 *entries; + bool_t eof; }; typedef struct dirlist3 dirlist3; struct READDIR3resok { - post_op_attr dir_attributes; - cookieverf3 cookieverf; - dirlist3 reply; + post_op_attr dir_attributes; + cookieverf3 cookieverf; + dirlist3 reply; }; typedef struct READDIR3resok READDIR3resok; struct READDIR3resfail { - post_op_attr dir_attributes; + post_op_attr dir_attributes; }; typedef struct READDIR3resfail READDIR3resfail; struct READDIR3res { - nfsstat3 status; - union { - READDIR3resok resok; - READDIR3resfail resfail; - } READDIR3res_u; + nfsstat3 status; + union { + READDIR3resok resok; + READDIR3resfail resfail; + } READDIR3res_u; }; typedef struct READDIR3res READDIR3res; struct READDIRPLUS3args { - nfs_fh3 dir; - cookie3 cookie; - cookieverf3 cookieverf; - count3 dircount; - count3 maxcount; + nfs_fh3 dir; + cookie3 cookie; + cookieverf3 cookieverf; + count3 dircount; + count3 maxcount; }; typedef struct READDIRPLUS3args READDIRPLUS3args; struct entryplus3 { - fileid3 fileid; - filename3 name; - cookie3 cookie; - post_op_attr name_attributes; - post_op_fh3 name_handle; - struct entryplus3 *nextentry; + fileid3 fileid; + filename3 name; + cookie3 cookie; + post_op_attr name_attributes; + post_op_fh3 name_handle; + struct entryplus3 *nextentry; }; typedef struct entryplus3 entryplus3; struct dirlistplus3 { - entryplus3 *entries; - bool_t eof; + entryplus3 *entries; + bool_t eof; }; typedef struct dirlistplus3 dirlistplus3; struct READDIRPLUS3resok { - post_op_attr dir_attributes; - cookieverf3 cookieverf; - dirlistplus3 reply; + post_op_attr dir_attributes; + cookieverf3 cookieverf; + dirlistplus3 reply; }; typedef struct READDIRPLUS3resok READDIRPLUS3resok; struct READDIRPLUS3resfail { - post_op_attr dir_attributes; + post_op_attr dir_attributes; }; typedef struct READDIRPLUS3resfail READDIRPLUS3resfail; struct READDIRPLUS3res { - nfsstat3 status; - union { - READDIRPLUS3resok resok; - READDIRPLUS3resfail resfail; - } READDIRPLUS3res_u; + nfsstat3 status; + union { + READDIRPLUS3resok resok; + READDIRPLUS3resfail resfail; + } READDIRPLUS3res_u; }; typedef struct READDIRPLUS3res READDIRPLUS3res; struct FSSTAT3args { - nfs_fh3 fsroot; + nfs_fh3 fsroot; }; typedef struct FSSTAT3args FSSTAT3args; struct FSSTAT3resok { - post_op_attr obj_attributes; - size3 tbytes; - size3 fbytes; - size3 abytes; - size3 tfiles; - size3 ffiles; - size3 afiles; - uint32 invarsec; + post_op_attr obj_attributes; + size3 tbytes; + size3 fbytes; + size3 abytes; + size3 tfiles; + size3 ffiles; + size3 afiles; + uint32 invarsec; }; typedef struct FSSTAT3resok FSSTAT3resok; struct FSSTAT3resfail { - post_op_attr obj_attributes; + post_op_attr obj_attributes; }; typedef struct FSSTAT3resfail FSSTAT3resfail; struct FSSTAT3res { - nfsstat3 status; - union { - FSSTAT3resok resok; - FSSTAT3resfail resfail; - } FSSTAT3res_u; + nfsstat3 status; + union { + FSSTAT3resok resok; + FSSTAT3resfail resfail; + } FSSTAT3res_u; }; typedef struct FSSTAT3res FSSTAT3res; struct FSINFO3args { - nfs_fh3 fsroot; + nfs_fh3 fsroot; }; typedef struct FSINFO3args FSINFO3args; struct FSINFO3resok { - post_op_attr obj_attributes; - uint32 rtmax; - uint32 rtpref; - uint32 rtmult; - uint32 wtmax; - uint32 wtpref; - uint32 wtmult; - uint32 dtpref; - size3 maxfilesize; - nfstime3 time_delta; - uint32 properties; + post_op_attr obj_attributes; + uint32 rtmax; + uint32 rtpref; + uint32 rtmult; + uint32 wtmax; + uint32 wtpref; + uint32 wtmult; + uint32 dtpref; + size3 maxfilesize; + nfstime3 time_delta; + uint32 properties; }; typedef struct FSINFO3resok FSINFO3resok; struct FSINFO3resfail { - post_op_attr obj_attributes; + post_op_attr obj_attributes; }; typedef struct FSINFO3resfail FSINFO3resfail; struct FSINFO3res { - nfsstat3 status; - union { - FSINFO3resok resok; - FSINFO3resfail resfail; - } FSINFO3res_u; + nfsstat3 status; + union { + FSINFO3resok resok; + FSINFO3resfail resfail; + } FSINFO3res_u; }; typedef struct FSINFO3res FSINFO3res; struct PATHCONF3args { - nfs_fh3 object; + nfs_fh3 object; }; typedef struct PATHCONF3args PATHCONF3args; struct PATHCONF3resok { - post_op_attr obj_attributes; - uint32 linkmax; - uint32 name_max; - bool_t no_trunc; - bool_t chown_restricted; - bool_t case_insensitive; - bool_t case_preserving; + post_op_attr obj_attributes; + uint32 linkmax; + uint32 name_max; + bool_t no_trunc; + bool_t chown_restricted; + bool_t case_insensitive; + bool_t case_preserving; }; typedef struct PATHCONF3resok PATHCONF3resok; struct PATHCONF3resfail { - post_op_attr obj_attributes; + post_op_attr obj_attributes; }; typedef struct PATHCONF3resfail PATHCONF3resfail; struct PATHCONF3res { - nfsstat3 status; - union { - PATHCONF3resok resok; - PATHCONF3resfail resfail; - } PATHCONF3res_u; + nfsstat3 status; + union { + PATHCONF3resok resok; + PATHCONF3resfail resfail; + } PATHCONF3res_u; }; typedef struct PATHCONF3res PATHCONF3res; struct COMMIT3args { - nfs_fh3 file; - offset3 offset; - count3 count; + nfs_fh3 file; + offset3 offset; + count3 count; }; typedef struct COMMIT3args COMMIT3args; struct COMMIT3resok { - wcc_data file_wcc; - writeverf3 verf; + wcc_data file_wcc; + writeverf3 verf; }; typedef struct COMMIT3resok COMMIT3resok; struct COMMIT3resfail { - wcc_data file_wcc; + wcc_data file_wcc; }; typedef struct COMMIT3resfail COMMIT3resfail; struct COMMIT3res { - nfsstat3 status; - union { - COMMIT3resok resok; - COMMIT3resfail resfail; - } COMMIT3res_u; + nfsstat3 status; + union { + COMMIT3resok resok; + COMMIT3resfail resfail; + } COMMIT3res_u; }; typedef struct COMMIT3res COMMIT3res; -#define NFS_PROGRAM 100003 -#define NFS_V3 3 +#define NFS_PROGRAM 100003 +#define NFS_V3 3 -#define NFSPROC3_NULL 0 +#define NFSPROC3_NULL 0 extern enum clnt_stat nfsproc3_null_3(void *, CLIENT *); -#define NFSPROC3_GETATTR 1 +#define NFSPROC3_GETATTR 1 extern enum clnt_stat nfsproc3_getattr_3(GETATTR3args , GETATTR3res *, CLIENT *); -#define NFSPROC3_SETATTR 2 +#define NFSPROC3_SETATTR 2 extern enum clnt_stat nfsproc3_setattr_3(SETATTR3args , SETATTR3res *, CLIENT *); -#define NFSPROC3_LOOKUP 3 +#define NFSPROC3_LOOKUP 3 extern enum clnt_stat nfsproc3_lookup_3(LOOKUP3args , LOOKUP3res *, CLIENT *); -#define NFSPROC3_ACCESS 4 +#define NFSPROC3_ACCESS 4 extern enum clnt_stat nfsproc3_access_3(ACCESS3args , ACCESS3res *, CLIENT *); -#define NFSPROC3_READLINK 5 +#define NFSPROC3_READLINK 5 extern enum clnt_stat nfsproc3_readlink_3(READLINK3args , READLINK3res *, CLIENT *); -#define NFSPROC3_READ 6 +#define NFSPROC3_READ 6 extern enum clnt_stat nfsproc3_read_3(READ3args , READ3res *, CLIENT *); -#define NFSPROC3_WRITE 7 +#define NFSPROC3_WRITE 7 extern enum clnt_stat nfsproc3_write_3(WRITE3args , WRITE3res *, CLIENT *); -#define NFSPROC3_CREATE 8 +#define NFSPROC3_CREATE 8 extern enum clnt_stat nfsproc3_create_3(CREATE3args , CREATE3res *, CLIENT *); -#define NFSPROC3_MKDIR 9 +#define NFSPROC3_MKDIR 9 extern enum clnt_stat nfsproc3_mkdir_3(MKDIR3args , MKDIR3res *, CLIENT *); -#define NFSPROC3_SYMLINK 10 +#define NFSPROC3_SYMLINK 10 extern enum clnt_stat nfsproc3_symlink_3(SYMLINK3args , SYMLINK3res *, CLIENT *); -#define NFSPROC3_MKNOD 11 +#define NFSPROC3_MKNOD 11 extern enum clnt_stat nfsproc3_mknod_3(MKNOD3args , MKNOD3res *, CLIENT *); -#define NFSPROC3_REMOVE 12 +#define NFSPROC3_REMOVE 12 extern enum clnt_stat nfsproc3_remove_3(REMOVE3args , REMOVE3res *, CLIENT *); -#define NFSPROC3_RMDIR 13 +#define NFSPROC3_RMDIR 13 extern enum clnt_stat nfsproc3_rmdir_3(RMDIR3args , RMDIR3res *, CLIENT *); -#define NFSPROC3_RENAME 14 +#define NFSPROC3_RENAME 14 extern enum clnt_stat nfsproc3_rename_3(RENAME3args , RENAME3res *, CLIENT *); -#define NFSPROC3_LINK 15 +#define NFSPROC3_LINK 15 extern enum clnt_stat nfsproc3_link_3(LINK3args , LINK3res *, CLIENT *); -#define NFSPROC3_READDIR 16 +#define NFSPROC3_READDIR 16 extern enum clnt_stat nfsproc3_readdir_3(READDIR3args , READDIR3res *, CLIENT *); -#define NFSPROC3_READDIRPLUS 17 +#define NFSPROC3_READDIRPLUS 17 extern enum clnt_stat nfsproc3_readdirplus_3(READDIRPLUS3args , READDIRPLUS3res *, CLIENT *); -#define NFSPROC3_FSSTAT 18 +#define NFSPROC3_FSSTAT 18 extern enum clnt_stat nfsproc3_fsstat_3(FSSTAT3args , FSSTAT3res *, CLIENT *); -#define NFSPROC3_FSINFO 19 +#define NFSPROC3_FSINFO 19 extern enum clnt_stat nfsproc3_fsinfo_3(FSINFO3args , FSINFO3res *, CLIENT *); -#define NFSPROC3_PATHCONF 20 +#define NFSPROC3_PATHCONF 20 extern enum clnt_stat nfsproc3_pathconf_3(PATHCONF3args , PATHCONF3res *, CLIENT *); -#define NFSPROC3_COMMIT 21 +#define NFSPROC3_COMMIT 21 extern enum clnt_stat nfsproc3_commit_3(COMMIT3args , COMMIT3res *, CLIENT *); /* the xdr functions */ diff --git a/components/dfs/filesystems/nfs/nfs_auth.c b/components/dfs/filesystems/nfs/nfs_auth.c index c65a1126a6..4b6be8d498 100644 --- a/components/dfs/filesystems/nfs/nfs_auth.c +++ b/components/dfs/filesystems/nfs/nfs_auth.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/dfs/filesystems/nfs/nfs_clnt.c b/components/dfs/filesystems/nfs/nfs_clnt.c index c17fee9e80..b50cf7ff1d 100644 --- a/components/dfs/filesystems/nfs/nfs_clnt.c +++ b/components/dfs/filesystems/nfs/nfs_clnt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -23,200 +23,200 @@ typedef char* caddr_t; /* Default timeout can be changed using clnt_control() */ static struct timeval TIMEOUT = { 25, 0 }; -enum clnt_stat +enum clnt_stat nfsproc3_null_3(void *clnt_res, CLIENT *clnt) { - return (clnt_call(clnt, NFSPROC3_NULL, - (xdrproc_t) xdr_void, (caddr_t) NULL, - (xdrproc_t) xdr_void, (caddr_t) clnt_res, - TIMEOUT)); + return (clnt_call(clnt, NFSPROC3_NULL, + (xdrproc_t) xdr_void, (caddr_t) NULL, + (xdrproc_t) xdr_void, (caddr_t) clnt_res, + TIMEOUT)); } -enum clnt_stat +enum clnt_stat nfsproc3_getattr_3(GETATTR3args arg1, GETATTR3res *clnt_res, CLIENT *clnt) { - return (clnt_call(clnt, NFSPROC3_GETATTR, - (xdrproc_t) xdr_GETATTR3args, (caddr_t) &arg1, - (xdrproc_t) xdr_GETATTR3res, (caddr_t) clnt_res, - TIMEOUT)); + return (clnt_call(clnt, NFSPROC3_GETATTR, + (xdrproc_t) xdr_GETATTR3args, (caddr_t) &arg1, + (xdrproc_t) xdr_GETATTR3res, (caddr_t) clnt_res, + TIMEOUT)); } -enum clnt_stat +enum clnt_stat nfsproc3_setattr_3(SETATTR3args arg1, SETATTR3res *clnt_res, CLIENT *clnt) { - return (clnt_call(clnt, NFSPROC3_SETATTR, - (xdrproc_t) xdr_SETATTR3args, (caddr_t) &arg1, - (xdrproc_t) xdr_SETATTR3res, (caddr_t) clnt_res, - TIMEOUT)); + return (clnt_call(clnt, NFSPROC3_SETATTR, + (xdrproc_t) xdr_SETATTR3args, (caddr_t) &arg1, + (xdrproc_t) xdr_SETATTR3res, (caddr_t) clnt_res, + TIMEOUT)); } -enum clnt_stat +enum clnt_stat nfsproc3_lookup_3(LOOKUP3args arg1, LOOKUP3res *clnt_res, CLIENT *clnt) { - return (clnt_call(clnt, NFSPROC3_LOOKUP, - (xdrproc_t) xdr_LOOKUP3args, (caddr_t) &arg1, - (xdrproc_t) xdr_LOOKUP3res, (caddr_t) clnt_res, - TIMEOUT)); + return (clnt_call(clnt, NFSPROC3_LOOKUP, + (xdrproc_t) xdr_LOOKUP3args, (caddr_t) &arg1, + (xdrproc_t) xdr_LOOKUP3res, (caddr_t) clnt_res, + TIMEOUT)); } -enum clnt_stat +enum clnt_stat nfsproc3_access_3(ACCESS3args arg1, ACCESS3res *clnt_res, CLIENT *clnt) { - return (clnt_call(clnt, NFSPROC3_ACCESS, - (xdrproc_t) xdr_ACCESS3args, (caddr_t) &arg1, - (xdrproc_t) xdr_ACCESS3res, (caddr_t) clnt_res, - TIMEOUT)); + return (clnt_call(clnt, NFSPROC3_ACCESS, + (xdrproc_t) xdr_ACCESS3args, (caddr_t) &arg1, + (xdrproc_t) xdr_ACCESS3res, (caddr_t) clnt_res, + TIMEOUT)); } -enum clnt_stat +enum clnt_stat nfsproc3_readlink_3(READLINK3args arg1, READLINK3res *clnt_res, CLIENT *clnt) { - return (clnt_call(clnt, NFSPROC3_READLINK, - (xdrproc_t) xdr_READLINK3args, (caddr_t) &arg1, - (xdrproc_t) xdr_READLINK3res, (caddr_t) clnt_res, - TIMEOUT)); + return (clnt_call(clnt, NFSPROC3_READLINK, + (xdrproc_t) xdr_READLINK3args, (caddr_t) &arg1, + (xdrproc_t) xdr_READLINK3res, (caddr_t) clnt_res, + TIMEOUT)); } -enum clnt_stat +enum clnt_stat nfsproc3_read_3(READ3args arg1, READ3res *clnt_res, CLIENT *clnt) { - return (clnt_call(clnt, NFSPROC3_READ, - (xdrproc_t) xdr_READ3args, (caddr_t) &arg1, - (xdrproc_t) xdr_READ3res, (caddr_t) clnt_res, - TIMEOUT)); + return (clnt_call(clnt, NFSPROC3_READ, + (xdrproc_t) xdr_READ3args, (caddr_t) &arg1, + (xdrproc_t) xdr_READ3res, (caddr_t) clnt_res, + TIMEOUT)); } -enum clnt_stat +enum clnt_stat nfsproc3_write_3(WRITE3args arg1, WRITE3res *clnt_res, CLIENT *clnt) { - return (clnt_call(clnt, NFSPROC3_WRITE, - (xdrproc_t) xdr_WRITE3args, (caddr_t) &arg1, - (xdrproc_t) xdr_WRITE3res, (caddr_t) clnt_res, - TIMEOUT)); + return (clnt_call(clnt, NFSPROC3_WRITE, + (xdrproc_t) xdr_WRITE3args, (caddr_t) &arg1, + (xdrproc_t) xdr_WRITE3res, (caddr_t) clnt_res, + TIMEOUT)); } -enum clnt_stat +enum clnt_stat nfsproc3_create_3(CREATE3args arg1, CREATE3res *clnt_res, CLIENT *clnt) { - return (clnt_call(clnt, NFSPROC3_CREATE, - (xdrproc_t) xdr_CREATE3args, (caddr_t) &arg1, - (xdrproc_t) xdr_CREATE3res, (caddr_t) clnt_res, - TIMEOUT)); + return (clnt_call(clnt, NFSPROC3_CREATE, + (xdrproc_t) xdr_CREATE3args, (caddr_t) &arg1, + (xdrproc_t) xdr_CREATE3res, (caddr_t) clnt_res, + TIMEOUT)); } -enum clnt_stat +enum clnt_stat nfsproc3_mkdir_3(MKDIR3args arg1, MKDIR3res *clnt_res, CLIENT *clnt) { - return (clnt_call(clnt, NFSPROC3_MKDIR, - (xdrproc_t) xdr_MKDIR3args, (caddr_t) &arg1, - (xdrproc_t) xdr_MKDIR3res, (caddr_t) clnt_res, - TIMEOUT)); + return (clnt_call(clnt, NFSPROC3_MKDIR, + (xdrproc_t) xdr_MKDIR3args, (caddr_t) &arg1, + (xdrproc_t) xdr_MKDIR3res, (caddr_t) clnt_res, + TIMEOUT)); } -enum clnt_stat +enum clnt_stat nfsproc3_symlink_3(SYMLINK3args arg1, SYMLINK3res *clnt_res, CLIENT *clnt) { - return (clnt_call(clnt, NFSPROC3_SYMLINK, - (xdrproc_t) xdr_SYMLINK3args, (caddr_t) &arg1, - (xdrproc_t) xdr_SYMLINK3res, (caddr_t) clnt_res, - TIMEOUT)); + return (clnt_call(clnt, NFSPROC3_SYMLINK, + (xdrproc_t) xdr_SYMLINK3args, (caddr_t) &arg1, + (xdrproc_t) xdr_SYMLINK3res, (caddr_t) clnt_res, + TIMEOUT)); } -enum clnt_stat +enum clnt_stat nfsproc3_mknod_3(MKNOD3args arg1, MKNOD3res *clnt_res, CLIENT *clnt) { - return (clnt_call(clnt, NFSPROC3_MKNOD, - (xdrproc_t) xdr_MKNOD3args, (caddr_t) &arg1, - (xdrproc_t) xdr_MKNOD3res, (caddr_t) clnt_res, - TIMEOUT)); + return (clnt_call(clnt, NFSPROC3_MKNOD, + (xdrproc_t) xdr_MKNOD3args, (caddr_t) &arg1, + (xdrproc_t) xdr_MKNOD3res, (caddr_t) clnt_res, + TIMEOUT)); } -enum clnt_stat +enum clnt_stat nfsproc3_remove_3(REMOVE3args arg1, REMOVE3res *clnt_res, CLIENT *clnt) { - return (clnt_call(clnt, NFSPROC3_REMOVE, - (xdrproc_t) xdr_REMOVE3args, (caddr_t) &arg1, - (xdrproc_t) xdr_REMOVE3res, (caddr_t) clnt_res, - TIMEOUT)); + return (clnt_call(clnt, NFSPROC3_REMOVE, + (xdrproc_t) xdr_REMOVE3args, (caddr_t) &arg1, + (xdrproc_t) xdr_REMOVE3res, (caddr_t) clnt_res, + TIMEOUT)); } -enum clnt_stat +enum clnt_stat nfsproc3_rmdir_3(RMDIR3args arg1, RMDIR3res *clnt_res, CLIENT *clnt) { - return (clnt_call(clnt, NFSPROC3_RMDIR, - (xdrproc_t) xdr_RMDIR3args, (caddr_t) &arg1, - (xdrproc_t) xdr_RMDIR3res, (caddr_t) clnt_res, - TIMEOUT)); + return (clnt_call(clnt, NFSPROC3_RMDIR, + (xdrproc_t) xdr_RMDIR3args, (caddr_t) &arg1, + (xdrproc_t) xdr_RMDIR3res, (caddr_t) clnt_res, + TIMEOUT)); } -enum clnt_stat +enum clnt_stat nfsproc3_rename_3(RENAME3args arg1, RENAME3res *clnt_res, CLIENT *clnt) { - return (clnt_call(clnt, NFSPROC3_RENAME, - (xdrproc_t) xdr_RENAME3args, (caddr_t) &arg1, - (xdrproc_t) xdr_RENAME3res, (caddr_t) clnt_res, - TIMEOUT)); + return (clnt_call(clnt, NFSPROC3_RENAME, + (xdrproc_t) xdr_RENAME3args, (caddr_t) &arg1, + (xdrproc_t) xdr_RENAME3res, (caddr_t) clnt_res, + TIMEOUT)); } -enum clnt_stat +enum clnt_stat nfsproc3_link_3(LINK3args arg1, LINK3res *clnt_res, CLIENT *clnt) { - return (clnt_call(clnt, NFSPROC3_LINK, - (xdrproc_t) xdr_LINK3args, (caddr_t) &arg1, - (xdrproc_t) xdr_LINK3res, (caddr_t) clnt_res, - TIMEOUT)); + return (clnt_call(clnt, NFSPROC3_LINK, + (xdrproc_t) xdr_LINK3args, (caddr_t) &arg1, + (xdrproc_t) xdr_LINK3res, (caddr_t) clnt_res, + TIMEOUT)); } -enum clnt_stat +enum clnt_stat nfsproc3_readdir_3(READDIR3args arg1, READDIR3res *clnt_res, CLIENT *clnt) { - return (clnt_call(clnt, NFSPROC3_READDIR, - (xdrproc_t) xdr_READDIR3args, (caddr_t) &arg1, - (xdrproc_t) xdr_READDIR3res, (caddr_t) clnt_res, - TIMEOUT)); + return (clnt_call(clnt, NFSPROC3_READDIR, + (xdrproc_t) xdr_READDIR3args, (caddr_t) &arg1, + (xdrproc_t) xdr_READDIR3res, (caddr_t) clnt_res, + TIMEOUT)); } -enum clnt_stat +enum clnt_stat nfsproc3_readdirplus_3(READDIRPLUS3args arg1, READDIRPLUS3res *clnt_res, CLIENT *clnt) { - return (clnt_call(clnt, NFSPROC3_READDIRPLUS, - (xdrproc_t) xdr_READDIRPLUS3args, (caddr_t) &arg1, - (xdrproc_t) xdr_READDIRPLUS3res, (caddr_t) clnt_res, - TIMEOUT)); + return (clnt_call(clnt, NFSPROC3_READDIRPLUS, + (xdrproc_t) xdr_READDIRPLUS3args, (caddr_t) &arg1, + (xdrproc_t) xdr_READDIRPLUS3res, (caddr_t) clnt_res, + TIMEOUT)); } -enum clnt_stat +enum clnt_stat nfsproc3_fsstat_3(FSSTAT3args arg1, FSSTAT3res *clnt_res, CLIENT *clnt) { - return (clnt_call(clnt, NFSPROC3_FSSTAT, - (xdrproc_t) xdr_FSSTAT3args, (caddr_t) &arg1, - (xdrproc_t) xdr_FSSTAT3res, (caddr_t) clnt_res, - TIMEOUT)); + return (clnt_call(clnt, NFSPROC3_FSSTAT, + (xdrproc_t) xdr_FSSTAT3args, (caddr_t) &arg1, + (xdrproc_t) xdr_FSSTAT3res, (caddr_t) clnt_res, + TIMEOUT)); } -enum clnt_stat +enum clnt_stat nfsproc3_fsinfo_3(FSINFO3args arg1, FSINFO3res *clnt_res, CLIENT *clnt) { - return (clnt_call(clnt, NFSPROC3_FSINFO, - (xdrproc_t) xdr_FSINFO3args, (caddr_t) &arg1, - (xdrproc_t) xdr_FSINFO3res, (caddr_t) clnt_res, - TIMEOUT)); + return (clnt_call(clnt, NFSPROC3_FSINFO, + (xdrproc_t) xdr_FSINFO3args, (caddr_t) &arg1, + (xdrproc_t) xdr_FSINFO3res, (caddr_t) clnt_res, + TIMEOUT)); } -enum clnt_stat +enum clnt_stat nfsproc3_pathconf_3(PATHCONF3args arg1, PATHCONF3res *clnt_res, CLIENT *clnt) { - return (clnt_call(clnt, NFSPROC3_PATHCONF, - (xdrproc_t) xdr_PATHCONF3args, (caddr_t) &arg1, - (xdrproc_t) xdr_PATHCONF3res, (caddr_t) clnt_res, - TIMEOUT)); + return (clnt_call(clnt, NFSPROC3_PATHCONF, + (xdrproc_t) xdr_PATHCONF3args, (caddr_t) &arg1, + (xdrproc_t) xdr_PATHCONF3res, (caddr_t) clnt_res, + TIMEOUT)); } -enum clnt_stat +enum clnt_stat nfsproc3_commit_3(COMMIT3args arg1, COMMIT3res *clnt_res, CLIENT *clnt) { - return (clnt_call(clnt, NFSPROC3_COMMIT, - (xdrproc_t) xdr_COMMIT3args, (caddr_t) &arg1, - (xdrproc_t) xdr_COMMIT3res, (caddr_t) clnt_res, - TIMEOUT)); + return (clnt_call(clnt, NFSPROC3_COMMIT, + (xdrproc_t) xdr_COMMIT3args, (caddr_t) &arg1, + (xdrproc_t) xdr_COMMIT3res, (caddr_t) clnt_res, + TIMEOUT)); } diff --git a/components/dfs/filesystems/nfs/nfs_xdr.c b/components/dfs/filesystems/nfs/nfs_xdr.c index 33563976c3..2662a17df6 100644 --- a/components/dfs/filesystems/nfs/nfs_xdr.c +++ b/components/dfs/filesystems/nfs/nfs_xdr.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -19,1604 +19,1604 @@ bool_t xdr_uint64(register XDR *xdrs, uint64 *objp) { - if (!xdr_u_longlong_t(xdrs, objp)) - return (FALSE); - return (TRUE); + if (!xdr_u_longlong_t(xdrs, objp)) + return (FALSE); + return (TRUE); } bool_t xdr_int64(register XDR *xdrs, int64 *objp) { - if (!xdr_longlong_t(xdrs, objp)) - return (FALSE); - return (TRUE); + if (!xdr_longlong_t(xdrs, objp)) + return (FALSE); + return (TRUE); } bool_t xdr_uint32(register XDR *xdrs, uint32 *objp) { - if (!xdr_u_long(xdrs, objp)) - return (FALSE); - return (TRUE); + if (!xdr_u_long(xdrs, objp)) + return (FALSE); + return (TRUE); } bool_t xdr_int32(register XDR *xdrs, int32 *objp) { - if (!xdr_long(xdrs, objp)) - return (FALSE); - return (TRUE); + if (!xdr_long(xdrs, objp)) + return (FALSE); + return (TRUE); } bool_t xdr_filename3(register XDR *xdrs, filename3 *objp) { - if (!xdr_string(xdrs, objp, ~0)) - return (FALSE); - return (TRUE); + if (!xdr_string(xdrs, objp, ~0)) + return (FALSE); + return (TRUE); } bool_t xdr_nfspath3(register XDR *xdrs, nfspath3 *objp) { - if (!xdr_string(xdrs, objp, ~0)) - return (FALSE); - return (TRUE); + if (!xdr_string(xdrs, objp, ~0)) + return (FALSE); + return (TRUE); } bool_t xdr_fileid3(register XDR *xdrs, fileid3 *objp) { - if (!xdr_uint64(xdrs, objp)) - return (FALSE); - return (TRUE); + if (!xdr_uint64(xdrs, objp)) + return (FALSE); + return (TRUE); } bool_t xdr_cookie3(register XDR *xdrs, cookie3 *objp) { - if (!xdr_uint64(xdrs, objp)) - return (FALSE); - return (TRUE); + if (!xdr_uint64(xdrs, objp)) + return (FALSE); + return (TRUE); } bool_t xdr_cookieverf3(register XDR *xdrs, cookieverf3 objp) { - if (!xdr_opaque(xdrs, objp, NFS3_COOKIEVERFSIZE)) - return (FALSE); - return (TRUE); + if (!xdr_opaque(xdrs, objp, NFS3_COOKIEVERFSIZE)) + return (FALSE); + return (TRUE); } bool_t xdr_createverf3(register XDR *xdrs, createverf3 objp) { - if (!xdr_opaque(xdrs, objp, NFS3_CREATEVERFSIZE)) - return (FALSE); - return (TRUE); + if (!xdr_opaque(xdrs, objp, NFS3_CREATEVERFSIZE)) + return (FALSE); + return (TRUE); } bool_t xdr_writeverf3(register XDR *xdrs, writeverf3 objp) { - if (!xdr_opaque(xdrs, objp, NFS3_WRITEVERFSIZE)) - return (FALSE); - return (TRUE); + if (!xdr_opaque(xdrs, objp, NFS3_WRITEVERFSIZE)) + return (FALSE); + return (TRUE); } bool_t xdr_uid3(register XDR *xdrs, uid3 *objp) { - if (!xdr_uint32(xdrs, objp)) - return (FALSE); - return (TRUE); + if (!xdr_uint32(xdrs, objp)) + return (FALSE); + return (TRUE); } bool_t xdr_gid3(register XDR *xdrs, gid3 *objp) { - if (!xdr_uint32(xdrs, objp)) - return (FALSE); - return (TRUE); + if (!xdr_uint32(xdrs, objp)) + return (FALSE); + return (TRUE); } bool_t xdr_size3(register XDR *xdrs, size3 *objp) { - if (!xdr_uint64(xdrs, objp)) - return (FALSE); - return (TRUE); + if (!xdr_uint64(xdrs, objp)) + return (FALSE); + return (TRUE); } bool_t xdr_offset3(register XDR *xdrs, offset3 *objp) { - if (!xdr_uint64(xdrs, objp)) - return (FALSE); - return (TRUE); + if (!xdr_uint64(xdrs, objp)) + return (FALSE); + return (TRUE); } bool_t xdr_mode3(register XDR *xdrs, mode3 *objp) { - if (!xdr_uint32(xdrs, objp)) - return (FALSE); - return (TRUE); + if (!xdr_uint32(xdrs, objp)) + return (FALSE); + return (TRUE); } bool_t xdr_count3(register XDR *xdrs, count3 *objp) { - if (!xdr_uint32(xdrs, objp)) - return (FALSE); - return (TRUE); + if (!xdr_uint32(xdrs, objp)) + return (FALSE); + return (TRUE); } bool_t xdr_nfsstat3(register XDR *xdrs, nfsstat3 *objp) { - int enum_objp; - enum_objp = *objp; - if (!xdr_enum(xdrs, (enum_t *)objp)) - { - *objp = (nfsstat3)enum_objp; - return (FALSE); - } + int enum_objp; + enum_objp = *objp; + if (!xdr_enum(xdrs, (enum_t *)objp)) + { + *objp = (nfsstat3)enum_objp; + return (FALSE); + } - return (TRUE); + return (TRUE); } bool_t xdr_ftype3(register XDR *xdrs, ftype3 *objp) { - int enum_objp; - enum_objp = *objp; - if (!xdr_enum(xdrs, (enum_t *)objp)) - { - *objp = (ftype3)enum_objp; - return (FALSE); - } - - return (TRUE); + int enum_objp; + enum_objp = *objp; + if (!xdr_enum(xdrs, (enum_t *)objp)) + { + *objp = (ftype3)enum_objp; + return (FALSE); + } + + return (TRUE); } bool_t xdr_stable_how(register XDR *xdrs, stable_how *objp) { - int enum_objp; - enum_objp = *objp; - if (!xdr_enum(xdrs, (enum_t *)objp)) - { - *objp = (stable_how)enum_objp; - return (FALSE); - } - - return (TRUE); + int enum_objp; + enum_objp = *objp; + if (!xdr_enum(xdrs, (enum_t *)objp)) + { + *objp = (stable_how)enum_objp; + return (FALSE); + } + + return (TRUE); } bool_t xdr_createmode3(register XDR *xdrs, createmode3 *objp) { - int enum_objp; - enum_objp = *objp; - if (!xdr_enum(xdrs, (enum_t *)objp)) - { - *objp = (createmode3)enum_objp; - return (FALSE); - } - - return (TRUE); + int enum_objp; + enum_objp = *objp; + if (!xdr_enum(xdrs, (enum_t *)objp)) + { + *objp = (createmode3)enum_objp; + return (FALSE); + } + + return (TRUE); } bool_t xdr_specdata3(register XDR *xdrs, specdata3 *objp) { - if (!xdr_uint32(xdrs, &objp->specdata1)) - return (FALSE); - if (!xdr_uint32(xdrs, &objp->specdata2)) - return (FALSE); - return (TRUE); + if (!xdr_uint32(xdrs, &objp->specdata1)) + return (FALSE); + if (!xdr_uint32(xdrs, &objp->specdata2)) + return (FALSE); + return (TRUE); } bool_t xdr_nfs_fh3(register XDR *xdrs, nfs_fh3 *objp) { - if (!xdr_bytes(xdrs, (char **)&objp->data.data_val, (unsigned int *) &objp->data.data_len, NFS3_FHSIZE)) - return (FALSE); - return (TRUE); + if (!xdr_bytes(xdrs, (char **)&objp->data.data_val, (unsigned int *) &objp->data.data_len, NFS3_FHSIZE)) + return (FALSE); + return (TRUE); } bool_t xdr_nfstime3(register XDR *xdrs, nfstime3 *objp) { - if (!xdr_uint32(xdrs, &objp->seconds)) - return (FALSE); - if (!xdr_uint32(xdrs, &objp->nseconds)) - return (FALSE); - return (TRUE); + if (!xdr_uint32(xdrs, &objp->seconds)) + return (FALSE); + if (!xdr_uint32(xdrs, &objp->nseconds)) + return (FALSE); + return (TRUE); } bool_t xdr_fattr3(register XDR *xdrs, fattr3 *objp) { - if (!xdr_ftype3(xdrs, &objp->type)) - return (FALSE); - if (!xdr_mode3(xdrs, &objp->mode)) - return (FALSE); - if (!xdr_uint32(xdrs, &objp->nlink)) - return (FALSE); - if (!xdr_uid3(xdrs, &objp->uid)) - return (FALSE); - if (!xdr_gid3(xdrs, &objp->gid)) - return (FALSE); - if (!xdr_size3(xdrs, &objp->size)) - return (FALSE); - if (!xdr_size3(xdrs, &objp->used)) - return (FALSE); - if (!xdr_specdata3(xdrs, &objp->rdev)) - return (FALSE); - if (!xdr_uint64(xdrs, &objp->fsid)) - return (FALSE); - if (!xdr_fileid3(xdrs, &objp->fileid)) - return (FALSE); - if (!xdr_nfstime3(xdrs, &objp->atime)) - return (FALSE); - if (!xdr_nfstime3(xdrs, &objp->mtime)) - return (FALSE); - if (!xdr_nfstime3(xdrs, &objp->ctime)) - return (FALSE); - return (TRUE); + if (!xdr_ftype3(xdrs, &objp->type)) + return (FALSE); + if (!xdr_mode3(xdrs, &objp->mode)) + return (FALSE); + if (!xdr_uint32(xdrs, &objp->nlink)) + return (FALSE); + if (!xdr_uid3(xdrs, &objp->uid)) + return (FALSE); + if (!xdr_gid3(xdrs, &objp->gid)) + return (FALSE); + if (!xdr_size3(xdrs, &objp->size)) + return (FALSE); + if (!xdr_size3(xdrs, &objp->used)) + return (FALSE); + if (!xdr_specdata3(xdrs, &objp->rdev)) + return (FALSE); + if (!xdr_uint64(xdrs, &objp->fsid)) + return (FALSE); + if (!xdr_fileid3(xdrs, &objp->fileid)) + return (FALSE); + if (!xdr_nfstime3(xdrs, &objp->atime)) + return (FALSE); + if (!xdr_nfstime3(xdrs, &objp->mtime)) + return (FALSE); + if (!xdr_nfstime3(xdrs, &objp->ctime)) + return (FALSE); + return (TRUE); } bool_t xdr_post_op_attr(register XDR *xdrs, post_op_attr *objp) { - if (!xdr_bool(xdrs, &objp->attributes_follow)) - return (FALSE); - switch (objp->attributes_follow) { - case TRUE: - if (!xdr_fattr3(xdrs, &objp->post_op_attr_u.attributes)) - return (FALSE); - break; - case FALSE: - break; - default: - return (FALSE); - } - return (TRUE); + if (!xdr_bool(xdrs, &objp->attributes_follow)) + return (FALSE); + switch (objp->attributes_follow) { + case TRUE: + if (!xdr_fattr3(xdrs, &objp->post_op_attr_u.attributes)) + return (FALSE); + break; + case FALSE: + break; + default: + return (FALSE); + } + return (TRUE); } bool_t xdr_wcc_attr(register XDR *xdrs, wcc_attr *objp) { - if (!xdr_size3(xdrs, &objp->size)) - return (FALSE); - if (!xdr_nfstime3(xdrs, &objp->mtime)) - return (FALSE); - if (!xdr_nfstime3(xdrs, &objp->ctime)) - return (FALSE); - return (TRUE); + if (!xdr_size3(xdrs, &objp->size)) + return (FALSE); + if (!xdr_nfstime3(xdrs, &objp->mtime)) + return (FALSE); + if (!xdr_nfstime3(xdrs, &objp->ctime)) + return (FALSE); + return (TRUE); } bool_t xdr_pre_op_attr(register XDR *xdrs, pre_op_attr *objp) { - if (!xdr_bool(xdrs, &objp->attributes_follow)) - return (FALSE); - switch (objp->attributes_follow) { - case TRUE: - if (!xdr_wcc_attr(xdrs, &objp->pre_op_attr_u.attributes)) - return (FALSE); - break; - case FALSE: - break; - default: - return (FALSE); - } - return (TRUE); + if (!xdr_bool(xdrs, &objp->attributes_follow)) + return (FALSE); + switch (objp->attributes_follow) { + case TRUE: + if (!xdr_wcc_attr(xdrs, &objp->pre_op_attr_u.attributes)) + return (FALSE); + break; + case FALSE: + break; + default: + return (FALSE); + } + return (TRUE); } bool_t xdr_wcc_data(register XDR *xdrs, wcc_data *objp) { - if (!xdr_pre_op_attr(xdrs, &objp->before)) - return (FALSE); - if (!xdr_post_op_attr(xdrs, &objp->after)) - return (FALSE); - return (TRUE); + if (!xdr_pre_op_attr(xdrs, &objp->before)) + return (FALSE); + if (!xdr_post_op_attr(xdrs, &objp->after)) + return (FALSE); + return (TRUE); } bool_t xdr_post_op_fh3(register XDR *xdrs, post_op_fh3 *objp) { - if (!xdr_bool(xdrs, &objp->handle_follows)) - return (FALSE); - switch (objp->handle_follows) { - case TRUE: - if (!xdr_nfs_fh3(xdrs, &objp->post_op_fh3_u.handle)) - return (FALSE); - break; - case FALSE: - break; - default: - return (FALSE); - } - return (TRUE); + if (!xdr_bool(xdrs, &objp->handle_follows)) + return (FALSE); + switch (objp->handle_follows) { + case TRUE: + if (!xdr_nfs_fh3(xdrs, &objp->post_op_fh3_u.handle)) + return (FALSE); + break; + case FALSE: + break; + default: + return (FALSE); + } + return (TRUE); } bool_t xdr_time_how(register XDR *xdrs, time_how *objp) { - int enum_objp; - enum_objp = *objp; - if (!xdr_enum(xdrs, (enum_t *)objp)) - { - *objp = (time_how)enum_objp; - return (FALSE); - } - - return (TRUE); + int enum_objp; + enum_objp = *objp; + if (!xdr_enum(xdrs, (enum_t *)objp)) + { + *objp = (time_how)enum_objp; + return (FALSE); + } + + return (TRUE); } bool_t xdr_set_mode3(register XDR *xdrs, set_mode3 *objp) { - if (!xdr_bool(xdrs, &objp->set_it)) - return (FALSE); - switch (objp->set_it) { - case TRUE: - if (!xdr_mode3(xdrs, &objp->set_mode3_u.mode)) - return (FALSE); - break; - } - return (TRUE); + if (!xdr_bool(xdrs, &objp->set_it)) + return (FALSE); + switch (objp->set_it) { + case TRUE: + if (!xdr_mode3(xdrs, &objp->set_mode3_u.mode)) + return (FALSE); + break; + } + return (TRUE); } bool_t xdr_set_uid3(register XDR *xdrs, set_uid3 *objp) { - if (!xdr_bool(xdrs, &objp->set_it)) - return (FALSE); - switch (objp->set_it) { - case TRUE: - if (!xdr_uid3(xdrs, &objp->set_uid3_u.uid)) - return (FALSE); - break; - } - return (TRUE); + if (!xdr_bool(xdrs, &objp->set_it)) + return (FALSE); + switch (objp->set_it) { + case TRUE: + if (!xdr_uid3(xdrs, &objp->set_uid3_u.uid)) + return (FALSE); + break; + } + return (TRUE); } bool_t xdr_set_gid3(register XDR *xdrs, set_gid3 *objp) { - if (!xdr_bool(xdrs, &objp->set_it)) - return (FALSE); - switch (objp->set_it) { - case TRUE: - if (!xdr_gid3(xdrs, &objp->set_gid3_u.gid)) - return (FALSE); - break; - } - return (TRUE); + if (!xdr_bool(xdrs, &objp->set_it)) + return (FALSE); + switch (objp->set_it) { + case TRUE: + if (!xdr_gid3(xdrs, &objp->set_gid3_u.gid)) + return (FALSE); + break; + } + return (TRUE); } bool_t xdr_set_size3(register XDR *xdrs, set_size3 *objp) { - if (!xdr_bool(xdrs, &objp->set_it)) - return (FALSE); - switch (objp->set_it) { - case TRUE: - if (!xdr_size3(xdrs, &objp->set_size3_u.size)) - return (FALSE); - break; - } - return (TRUE); + if (!xdr_bool(xdrs, &objp->set_it)) + return (FALSE); + switch (objp->set_it) { + case TRUE: + if (!xdr_size3(xdrs, &objp->set_size3_u.size)) + return (FALSE); + break; + } + return (TRUE); } bool_t xdr_set_atime(register XDR *xdrs, set_atime *objp) { - if (!xdr_time_how(xdrs, &objp->set_it)) - return (FALSE); - switch (objp->set_it) { - case SET_TO_CLIENT_TIME: - if (!xdr_nfstime3(xdrs, &objp->set_atime_u.atime)) - return (FALSE); - break; - } - return (TRUE); + if (!xdr_time_how(xdrs, &objp->set_it)) + return (FALSE); + switch (objp->set_it) { + case SET_TO_CLIENT_TIME: + if (!xdr_nfstime3(xdrs, &objp->set_atime_u.atime)) + return (FALSE); + break; + } + return (TRUE); } bool_t xdr_set_mtime(register XDR *xdrs, set_mtime *objp) { - if (!xdr_time_how(xdrs, &objp->set_it)) - return (FALSE); - switch (objp->set_it) { - case SET_TO_CLIENT_TIME: - if (!xdr_nfstime3(xdrs, &objp->set_mtime_u.mtime)) - return (FALSE); - break; - } - return (TRUE); + if (!xdr_time_how(xdrs, &objp->set_it)) + return (FALSE); + switch (objp->set_it) { + case SET_TO_CLIENT_TIME: + if (!xdr_nfstime3(xdrs, &objp->set_mtime_u.mtime)) + return (FALSE); + break; + } + return (TRUE); } bool_t xdr_sattr3(register XDR *xdrs, sattr3 *objp) { - if (!xdr_set_mode3(xdrs, &objp->mode)) - return (FALSE); - if (!xdr_set_uid3(xdrs, &objp->uid)) - return (FALSE); - if (!xdr_set_gid3(xdrs, &objp->gid)) - return (FALSE); - if (!xdr_set_size3(xdrs, &objp->size)) - return (FALSE); - if (!xdr_set_atime(xdrs, &objp->atime)) - return (FALSE); - if (!xdr_set_mtime(xdrs, &objp->mtime)) - return (FALSE); - return (TRUE); + if (!xdr_set_mode3(xdrs, &objp->mode)) + return (FALSE); + if (!xdr_set_uid3(xdrs, &objp->uid)) + return (FALSE); + if (!xdr_set_gid3(xdrs, &objp->gid)) + return (FALSE); + if (!xdr_set_size3(xdrs, &objp->size)) + return (FALSE); + if (!xdr_set_atime(xdrs, &objp->atime)) + return (FALSE); + if (!xdr_set_mtime(xdrs, &objp->mtime)) + return (FALSE); + return (TRUE); } bool_t xdr_diropargs3(register XDR *xdrs, diropargs3 *objp) { - if (!xdr_nfs_fh3(xdrs, &objp->dir)) - return (FALSE); - if (!xdr_filename3(xdrs, &objp->name)) - return (FALSE); - return (TRUE); + if (!xdr_nfs_fh3(xdrs, &objp->dir)) + return (FALSE); + if (!xdr_filename3(xdrs, &objp->name)) + return (FALSE); + return (TRUE); } bool_t xdr_GETATTR3args(register XDR *xdrs, GETATTR3args *objp) { - if (!xdr_nfs_fh3(xdrs, &objp->object)) - return (FALSE); - return (TRUE); + if (!xdr_nfs_fh3(xdrs, &objp->object)) + return (FALSE); + return (TRUE); } bool_t xdr_GETATTR3resok(register XDR *xdrs, GETATTR3resok *objp) { - if (!xdr_fattr3(xdrs, &objp->obj_attributes)) - return (FALSE); - return (TRUE); + if (!xdr_fattr3(xdrs, &objp->obj_attributes)) + return (FALSE); + return (TRUE); } bool_t xdr_GETATTR3res(register XDR *xdrs, GETATTR3res *objp) { - if (!xdr_nfsstat3(xdrs, &objp->status)) - return (FALSE); - switch (objp->status) { - case NFS3_OK: - if (!xdr_GETATTR3resok(xdrs, &objp->GETATTR3res_u.resok)) - return (FALSE); - break; - default : - return (FALSE); - } - return (TRUE); + if (!xdr_nfsstat3(xdrs, &objp->status)) + return (FALSE); + switch (objp->status) { + case NFS3_OK: + if (!xdr_GETATTR3resok(xdrs, &objp->GETATTR3res_u.resok)) + return (FALSE); + break; + default : + return (FALSE); + } + return (TRUE); } bool_t xdr_sattrguard3(register XDR *xdrs, sattrguard3 *objp) { - if (!xdr_bool(xdrs, &objp->check)) - return (FALSE); - switch (objp->check) { - case TRUE: - if (!xdr_nfstime3(xdrs, &objp->sattrguard3_u.obj_ctime)) - return (FALSE); - break; - case FALSE: - break; - default: - return (FALSE); - } - return (TRUE); + if (!xdr_bool(xdrs, &objp->check)) + return (FALSE); + switch (objp->check) { + case TRUE: + if (!xdr_nfstime3(xdrs, &objp->sattrguard3_u.obj_ctime)) + return (FALSE); + break; + case FALSE: + break; + default: + return (FALSE); + } + return (TRUE); } bool_t xdr_SETATTR3args(register XDR *xdrs, SETATTR3args *objp) { - if (!xdr_nfs_fh3(xdrs, &objp->object)) - return (FALSE); - if (!xdr_sattr3(xdrs, &objp->new_attributes)) - return (FALSE); - if (!xdr_sattrguard3(xdrs, &objp->guard)) - return (FALSE); - return (TRUE); + if (!xdr_nfs_fh3(xdrs, &objp->object)) + return (FALSE); + if (!xdr_sattr3(xdrs, &objp->new_attributes)) + return (FALSE); + if (!xdr_sattrguard3(xdrs, &objp->guard)) + return (FALSE); + return (TRUE); } bool_t xdr_SETATTR3resok(register XDR *xdrs, SETATTR3resok *objp) { - if (!xdr_wcc_data(xdrs, &objp->obj_wcc)) - return (FALSE); - return (TRUE); + if (!xdr_wcc_data(xdrs, &objp->obj_wcc)) + return (FALSE); + return (TRUE); } bool_t xdr_SETATTR3resfail(register XDR *xdrs, SETATTR3resfail *objp) { - if (!xdr_wcc_data(xdrs, &objp->obj_wcc)) - return (FALSE); - return (TRUE); + if (!xdr_wcc_data(xdrs, &objp->obj_wcc)) + return (FALSE); + return (TRUE); } bool_t xdr_SETATTR3res(register XDR *xdrs, SETATTR3res *objp) { - if (!xdr_nfsstat3(xdrs, &objp->status)) - return (FALSE); - switch (objp->status) { - case NFS3_OK: - if (!xdr_SETATTR3resok(xdrs, &objp->SETATTR3res_u.resok)) - return (FALSE); - break; - default: - if (!xdr_SETATTR3resfail(xdrs, &objp->SETATTR3res_u.resfail)) - return (FALSE); - break; - } - return (TRUE); + if (!xdr_nfsstat3(xdrs, &objp->status)) + return (FALSE); + switch (objp->status) { + case NFS3_OK: + if (!xdr_SETATTR3resok(xdrs, &objp->SETATTR3res_u.resok)) + return (FALSE); + break; + default: + if (!xdr_SETATTR3resfail(xdrs, &objp->SETATTR3res_u.resfail)) + return (FALSE); + break; + } + return (TRUE); } bool_t xdr_LOOKUP3args(register XDR *xdrs, LOOKUP3args *objp) { - if (!xdr_diropargs3(xdrs, &objp->what)) - return (FALSE); - return (TRUE); + if (!xdr_diropargs3(xdrs, &objp->what)) + return (FALSE); + return (TRUE); } bool_t xdr_LOOKUP3resok(register XDR *xdrs, LOOKUP3resok *objp) { - if (!xdr_nfs_fh3(xdrs, &objp->object)) - return (FALSE); - if (!xdr_post_op_attr(xdrs, &objp->obj_attributes)) - return (FALSE); - if (!xdr_post_op_attr(xdrs, &objp->dir_attributes)) - return (FALSE); - return (TRUE); + if (!xdr_nfs_fh3(xdrs, &objp->object)) + return (FALSE); + if (!xdr_post_op_attr(xdrs, &objp->obj_attributes)) + return (FALSE); + if (!xdr_post_op_attr(xdrs, &objp->dir_attributes)) + return (FALSE); + return (TRUE); } bool_t xdr_LOOKUP3resfail(register XDR *xdrs, LOOKUP3resfail *objp) { - if (!xdr_post_op_attr(xdrs, &objp->dir_attributes)) - return (FALSE); - return (TRUE); + if (!xdr_post_op_attr(xdrs, &objp->dir_attributes)) + return (FALSE); + return (TRUE); } bool_t xdr_LOOKUP3res(register XDR *xdrs, LOOKUP3res *objp) { - if (!xdr_nfsstat3(xdrs, &objp->status)) - return (FALSE); - switch (objp->status) { - case NFS3_OK: - if (!xdr_LOOKUP3resok(xdrs, &objp->LOOKUP3res_u.resok)) - return (FALSE); - break; - default: - if (!xdr_LOOKUP3resfail(xdrs, &objp->LOOKUP3res_u.resfail)) - return (FALSE); - break; - } - return (TRUE); + if (!xdr_nfsstat3(xdrs, &objp->status)) + return (FALSE); + switch (objp->status) { + case NFS3_OK: + if (!xdr_LOOKUP3resok(xdrs, &objp->LOOKUP3res_u.resok)) + return (FALSE); + break; + default: + if (!xdr_LOOKUP3resfail(xdrs, &objp->LOOKUP3res_u.resfail)) + return (FALSE); + break; + } + return (TRUE); } bool_t xdr_ACCESS3args(register XDR *xdrs, ACCESS3args *objp) { - if (!xdr_nfs_fh3(xdrs, &objp->object)) - return (FALSE); - if (!xdr_uint32(xdrs, &objp->access)) - return (FALSE); - return (TRUE); + if (!xdr_nfs_fh3(xdrs, &objp->object)) + return (FALSE); + if (!xdr_uint32(xdrs, &objp->access)) + return (FALSE); + return (TRUE); } bool_t xdr_ACCESS3resok(register XDR *xdrs, ACCESS3resok *objp) { - if (!xdr_post_op_attr(xdrs, &objp->obj_attributes)) - return (FALSE); - if (!xdr_uint32(xdrs, &objp->access)) - return (FALSE); - return (TRUE); + if (!xdr_post_op_attr(xdrs, &objp->obj_attributes)) + return (FALSE); + if (!xdr_uint32(xdrs, &objp->access)) + return (FALSE); + return (TRUE); } bool_t xdr_ACCESS3resfail(register XDR *xdrs, ACCESS3resfail *objp) { - if (!xdr_post_op_attr(xdrs, &objp->obj_attributes)) - return (FALSE); - return (TRUE); + if (!xdr_post_op_attr(xdrs, &objp->obj_attributes)) + return (FALSE); + return (TRUE); } bool_t xdr_ACCESS3res(register XDR *xdrs, ACCESS3res *objp) { - if (!xdr_nfsstat3(xdrs, &objp->status)) - return (FALSE); - switch (objp->status) { - case NFS3_OK: - if (!xdr_ACCESS3resok(xdrs, &objp->ACCESS3res_u.resok)) - return (FALSE); - break; - default: - if (!xdr_ACCESS3resfail(xdrs, &objp->ACCESS3res_u.resfail)) - return (FALSE); - break; - } - return (TRUE); + if (!xdr_nfsstat3(xdrs, &objp->status)) + return (FALSE); + switch (objp->status) { + case NFS3_OK: + if (!xdr_ACCESS3resok(xdrs, &objp->ACCESS3res_u.resok)) + return (FALSE); + break; + default: + if (!xdr_ACCESS3resfail(xdrs, &objp->ACCESS3res_u.resfail)) + return (FALSE); + break; + } + return (TRUE); } bool_t xdr_READLINK3args(register XDR *xdrs, READLINK3args *objp) { - if (!xdr_nfs_fh3(xdrs, &objp->symlink)) - return (FALSE); - return (TRUE); + if (!xdr_nfs_fh3(xdrs, &objp->symlink)) + return (FALSE); + return (TRUE); } bool_t xdr_READLINK3resok(register XDR *xdrs, READLINK3resok *objp) { - if (!xdr_post_op_attr(xdrs, &objp->symlink_attributes)) - return (FALSE); - if (!xdr_nfspath3(xdrs, &objp->data)) - return (FALSE); - return (TRUE); + if (!xdr_post_op_attr(xdrs, &objp->symlink_attributes)) + return (FALSE); + if (!xdr_nfspath3(xdrs, &objp->data)) + return (FALSE); + return (TRUE); } bool_t xdr_READLINK3resfail(register XDR *xdrs, READLINK3resfail *objp) { - if (!xdr_post_op_attr(xdrs, &objp->symlink_attributes)) - return (FALSE); - return (TRUE); + if (!xdr_post_op_attr(xdrs, &objp->symlink_attributes)) + return (FALSE); + return (TRUE); } bool_t xdr_READLINK3res(register XDR *xdrs, READLINK3res *objp) { - if (!xdr_nfsstat3(xdrs, &objp->status)) - return (FALSE); - switch (objp->status) { - case NFS3_OK: - if (!xdr_READLINK3resok(xdrs, &objp->READLINK3res_u.resok)) - return (FALSE); - break; - default: - if (!xdr_READLINK3resfail(xdrs, &objp->READLINK3res_u.resfail)) - return (FALSE); - break; - } - return (TRUE); + if (!xdr_nfsstat3(xdrs, &objp->status)) + return (FALSE); + switch (objp->status) { + case NFS3_OK: + if (!xdr_READLINK3resok(xdrs, &objp->READLINK3res_u.resok)) + return (FALSE); + break; + default: + if (!xdr_READLINK3resfail(xdrs, &objp->READLINK3res_u.resfail)) + return (FALSE); + break; + } + return (TRUE); } bool_t xdr_READ3args(register XDR *xdrs, READ3args *objp) { - if (!xdr_nfs_fh3(xdrs, &objp->file)) - return (FALSE); - if (!xdr_offset3(xdrs, &objp->offset)) - return (FALSE); - if (!xdr_count3(xdrs, &objp->count)) - return (FALSE); - return (TRUE); + if (!xdr_nfs_fh3(xdrs, &objp->file)) + return (FALSE); + if (!xdr_offset3(xdrs, &objp->offset)) + return (FALSE); + if (!xdr_count3(xdrs, &objp->count)) + return (FALSE); + return (TRUE); } bool_t xdr_READ3resok(register XDR *xdrs, READ3resok *objp) { - if (!xdr_post_op_attr(xdrs, &objp->file_attributes)) - return (FALSE); - if (!xdr_count3(xdrs, &objp->count)) - return (FALSE); - if (!xdr_bool(xdrs, &objp->eof)) - return (FALSE); - if (!xdr_bytes(xdrs, (char **)&objp->data.data_val, (unsigned int *) &objp->data.data_len, ~0)) - return (FALSE); - return (TRUE); + if (!xdr_post_op_attr(xdrs, &objp->file_attributes)) + return (FALSE); + if (!xdr_count3(xdrs, &objp->count)) + return (FALSE); + if (!xdr_bool(xdrs, &objp->eof)) + return (FALSE); + if (!xdr_bytes(xdrs, (char **)&objp->data.data_val, (unsigned int *) &objp->data.data_len, ~0)) + return (FALSE); + return (TRUE); } bool_t xdr_READ3resfail(register XDR *xdrs, READ3resfail *objp) { - if (!xdr_post_op_attr(xdrs, &objp->file_attributes)) - return (FALSE); - return (TRUE); + if (!xdr_post_op_attr(xdrs, &objp->file_attributes)) + return (FALSE); + return (TRUE); } bool_t xdr_READ3res(register XDR *xdrs, READ3res *objp) { - if (!xdr_nfsstat3(xdrs, &objp->status)) - return (FALSE); - switch (objp->status) { - case NFS3_OK: - if (!xdr_READ3resok(xdrs, &objp->READ3res_u.resok)) - return (FALSE); - break; - default: - if (!xdr_READ3resfail(xdrs, &objp->READ3res_u.resfail)) - return (FALSE); - break; - } - return (TRUE); + if (!xdr_nfsstat3(xdrs, &objp->status)) + return (FALSE); + switch (objp->status) { + case NFS3_OK: + if (!xdr_READ3resok(xdrs, &objp->READ3res_u.resok)) + return (FALSE); + break; + default: + if (!xdr_READ3resfail(xdrs, &objp->READ3res_u.resfail)) + return (FALSE); + break; + } + return (TRUE); } bool_t xdr_WRITE3args(register XDR *xdrs, WRITE3args *objp) { - if (!xdr_nfs_fh3(xdrs, &objp->file)) - return (FALSE); - if (!xdr_offset3(xdrs, &objp->offset)) - return (FALSE); - if (!xdr_count3(xdrs, &objp->count)) - return (FALSE); - if (!xdr_stable_how(xdrs, &objp->stable)) - return (FALSE); - if (!xdr_bytes(xdrs, (char **)&objp->data.data_val, (unsigned int *) &objp->data.data_len, ~0)) - return (FALSE); - return (TRUE); + if (!xdr_nfs_fh3(xdrs, &objp->file)) + return (FALSE); + if (!xdr_offset3(xdrs, &objp->offset)) + return (FALSE); + if (!xdr_count3(xdrs, &objp->count)) + return (FALSE); + if (!xdr_stable_how(xdrs, &objp->stable)) + return (FALSE); + if (!xdr_bytes(xdrs, (char **)&objp->data.data_val, (unsigned int *) &objp->data.data_len, ~0)) + return (FALSE); + return (TRUE); } bool_t xdr_WRITE3resok(register XDR *xdrs, WRITE3resok *objp) { - if (!xdr_wcc_data(xdrs, &objp->file_wcc)) - return (FALSE); - if (!xdr_count3(xdrs, &objp->count)) - return (FALSE); - if (!xdr_stable_how(xdrs, &objp->committed)) - return (FALSE); - if (!xdr_writeverf3(xdrs, objp->verf)) - return (FALSE); - return (TRUE); + if (!xdr_wcc_data(xdrs, &objp->file_wcc)) + return (FALSE); + if (!xdr_count3(xdrs, &objp->count)) + return (FALSE); + if (!xdr_stable_how(xdrs, &objp->committed)) + return (FALSE); + if (!xdr_writeverf3(xdrs, objp->verf)) + return (FALSE); + return (TRUE); } bool_t xdr_WRITE3resfail(register XDR *xdrs, WRITE3resfail *objp) { - if (!xdr_wcc_data(xdrs, &objp->file_wcc)) - return (FALSE); - return (TRUE); + if (!xdr_wcc_data(xdrs, &objp->file_wcc)) + return (FALSE); + return (TRUE); } bool_t xdr_WRITE3res(register XDR *xdrs, WRITE3res *objp) { - if (!xdr_nfsstat3(xdrs, &objp->status)) - return (FALSE); - switch (objp->status) { - case NFS3_OK: - if (!xdr_WRITE3resok(xdrs, &objp->WRITE3res_u.resok)) - return (FALSE); - break; - default: - if (!xdr_WRITE3resfail(xdrs, &objp->WRITE3res_u.resfail)) - return (FALSE); - break; - } - return (TRUE); + if (!xdr_nfsstat3(xdrs, &objp->status)) + return (FALSE); + switch (objp->status) { + case NFS3_OK: + if (!xdr_WRITE3resok(xdrs, &objp->WRITE3res_u.resok)) + return (FALSE); + break; + default: + if (!xdr_WRITE3resfail(xdrs, &objp->WRITE3res_u.resfail)) + return (FALSE); + break; + } + return (TRUE); } bool_t xdr_createhow3(register XDR *xdrs, createhow3 *objp) { - if (!xdr_createmode3(xdrs, &objp->mode)) - return (FALSE); - switch (objp->mode) { - case UNCHECKED: - case GUARDED: - if (!xdr_sattr3(xdrs, &objp->createhow3_u.obj_attributes)) - return (FALSE); - break; - case EXCLUSIVE: - if (!xdr_createverf3(xdrs, objp->createhow3_u.verf)) - return (FALSE); - break; - default: - return (FALSE); - } - return (TRUE); + if (!xdr_createmode3(xdrs, &objp->mode)) + return (FALSE); + switch (objp->mode) { + case UNCHECKED: + case GUARDED: + if (!xdr_sattr3(xdrs, &objp->createhow3_u.obj_attributes)) + return (FALSE); + break; + case EXCLUSIVE: + if (!xdr_createverf3(xdrs, objp->createhow3_u.verf)) + return (FALSE); + break; + default: + return (FALSE); + } + return (TRUE); } bool_t xdr_CREATE3args(register XDR *xdrs, CREATE3args *objp) { - if (!xdr_diropargs3(xdrs, &objp->where)) - return (FALSE); - if (!xdr_createhow3(xdrs, &objp->how)) - return (FALSE); - return (TRUE); + if (!xdr_diropargs3(xdrs, &objp->where)) + return (FALSE); + if (!xdr_createhow3(xdrs, &objp->how)) + return (FALSE); + return (TRUE); } bool_t xdr_CREATE3resok(register XDR *xdrs, CREATE3resok *objp) { - if (!xdr_post_op_fh3(xdrs, &objp->obj)) - return (FALSE); - if (!xdr_post_op_attr(xdrs, &objp->obj_attributes)) - return (FALSE); - if (!xdr_wcc_data(xdrs, &objp->dir_wcc)) - return (FALSE); - return (TRUE); + if (!xdr_post_op_fh3(xdrs, &objp->obj)) + return (FALSE); + if (!xdr_post_op_attr(xdrs, &objp->obj_attributes)) + return (FALSE); + if (!xdr_wcc_data(xdrs, &objp->dir_wcc)) + return (FALSE); + return (TRUE); } bool_t xdr_CREATE3resfail(register XDR *xdrs, CREATE3resfail *objp) { - if (!xdr_wcc_data(xdrs, &objp->dir_wcc)) - return (FALSE); - return (TRUE); + if (!xdr_wcc_data(xdrs, &objp->dir_wcc)) + return (FALSE); + return (TRUE); } bool_t xdr_CREATE3res(register XDR *xdrs, CREATE3res *objp) { - if (!xdr_nfsstat3(xdrs, &objp->status)) - return (FALSE); - switch (objp->status) { - case NFS3_OK: - if (!xdr_CREATE3resok(xdrs, &objp->CREATE3res_u.resok)) - return (FALSE); - break; - default: - if (!xdr_CREATE3resfail(xdrs, &objp->CREATE3res_u.resfail)) - return (FALSE); - break; - } - return (TRUE); + if (!xdr_nfsstat3(xdrs, &objp->status)) + return (FALSE); + switch (objp->status) { + case NFS3_OK: + if (!xdr_CREATE3resok(xdrs, &objp->CREATE3res_u.resok)) + return (FALSE); + break; + default: + if (!xdr_CREATE3resfail(xdrs, &objp->CREATE3res_u.resfail)) + return (FALSE); + break; + } + return (TRUE); } bool_t xdr_MKDIR3args(register XDR *xdrs, MKDIR3args *objp) { - if (!xdr_diropargs3(xdrs, &objp->where)) - return (FALSE); - if (!xdr_sattr3(xdrs, &objp->attributes)) - return (FALSE); - return (TRUE); + if (!xdr_diropargs3(xdrs, &objp->where)) + return (FALSE); + if (!xdr_sattr3(xdrs, &objp->attributes)) + return (FALSE); + return (TRUE); } bool_t xdr_MKDIR3resok(register XDR *xdrs, MKDIR3resok *objp) { - if (!xdr_post_op_fh3(xdrs, &objp->obj)) - return (FALSE); - if (!xdr_post_op_attr(xdrs, &objp->obj_attributes)) - return (FALSE); - if (!xdr_wcc_data(xdrs, &objp->dir_wcc)) - return (FALSE); - return (TRUE); + if (!xdr_post_op_fh3(xdrs, &objp->obj)) + return (FALSE); + if (!xdr_post_op_attr(xdrs, &objp->obj_attributes)) + return (FALSE); + if (!xdr_wcc_data(xdrs, &objp->dir_wcc)) + return (FALSE); + return (TRUE); } bool_t xdr_MKDIR3resfail(register XDR *xdrs, MKDIR3resfail *objp) { - if (!xdr_wcc_data(xdrs, &objp->dir_wcc)) - return (FALSE); - return (TRUE); + if (!xdr_wcc_data(xdrs, &objp->dir_wcc)) + return (FALSE); + return (TRUE); } bool_t xdr_MKDIR3res(register XDR *xdrs, MKDIR3res *objp) { - if (!xdr_nfsstat3(xdrs, &objp->status)) - return (FALSE); - switch (objp->status) { - case NFS3_OK: - if (!xdr_MKDIR3resok(xdrs, &objp->MKDIR3res_u.resok)) - return (FALSE); - break; - default: - if (!xdr_MKDIR3resfail(xdrs, &objp->MKDIR3res_u.resfail)) - return (FALSE); - break; - } - return (TRUE); + if (!xdr_nfsstat3(xdrs, &objp->status)) + return (FALSE); + switch (objp->status) { + case NFS3_OK: + if (!xdr_MKDIR3resok(xdrs, &objp->MKDIR3res_u.resok)) + return (FALSE); + break; + default: + if (!xdr_MKDIR3resfail(xdrs, &objp->MKDIR3res_u.resfail)) + return (FALSE); + break; + } + return (TRUE); } bool_t xdr_symlinkdata3(register XDR *xdrs, symlinkdata3 *objp) { - if (!xdr_sattr3(xdrs, &objp->symlink_attributes)) - return (FALSE); - if (!xdr_nfspath3(xdrs, &objp->symlink_data)) - return (FALSE); - return (TRUE); + if (!xdr_sattr3(xdrs, &objp->symlink_attributes)) + return (FALSE); + if (!xdr_nfspath3(xdrs, &objp->symlink_data)) + return (FALSE); + return (TRUE); } bool_t xdr_SYMLINK3args(register XDR *xdrs, SYMLINK3args *objp) { - if (!xdr_diropargs3(xdrs, &objp->where)) - return (FALSE); - if (!xdr_symlinkdata3(xdrs, &objp->symlink)) - return (FALSE); - return (TRUE); + if (!xdr_diropargs3(xdrs, &objp->where)) + return (FALSE); + if (!xdr_symlinkdata3(xdrs, &objp->symlink)) + return (FALSE); + return (TRUE); } bool_t xdr_SYMLINK3resok(register XDR *xdrs, SYMLINK3resok *objp) { - if (!xdr_post_op_fh3(xdrs, &objp->obj)) - return (FALSE); - if (!xdr_post_op_attr(xdrs, &objp->obj_attributes)) - return (FALSE); - if (!xdr_wcc_data(xdrs, &objp->dir_wcc)) - return (FALSE); - return (TRUE); + if (!xdr_post_op_fh3(xdrs, &objp->obj)) + return (FALSE); + if (!xdr_post_op_attr(xdrs, &objp->obj_attributes)) + return (FALSE); + if (!xdr_wcc_data(xdrs, &objp->dir_wcc)) + return (FALSE); + return (TRUE); } bool_t xdr_SYMLINK3resfail(register XDR *xdrs, SYMLINK3resfail *objp) { - if (!xdr_wcc_data(xdrs, &objp->dir_wcc)) - return (FALSE); - return (TRUE); + if (!xdr_wcc_data(xdrs, &objp->dir_wcc)) + return (FALSE); + return (TRUE); } bool_t xdr_SYMLINK3res(register XDR *xdrs, SYMLINK3res *objp) { - if (!xdr_nfsstat3(xdrs, &objp->status)) - return (FALSE); - switch (objp->status) { - case NFS3_OK: - if (!xdr_SYMLINK3resok(xdrs, &objp->SYMLINK3res_u.resok)) - return (FALSE); - break; - default: - if (!xdr_SYMLINK3resfail(xdrs, &objp->SYMLINK3res_u.resfail)) - return (FALSE); - break; - } - return (TRUE); + if (!xdr_nfsstat3(xdrs, &objp->status)) + return (FALSE); + switch (objp->status) { + case NFS3_OK: + if (!xdr_SYMLINK3resok(xdrs, &objp->SYMLINK3res_u.resok)) + return (FALSE); + break; + default: + if (!xdr_SYMLINK3resfail(xdrs, &objp->SYMLINK3res_u.resfail)) + return (FALSE); + break; + } + return (TRUE); } bool_t xdr_devicedata3(register XDR *xdrs, devicedata3 *objp) { - if (!xdr_sattr3(xdrs, &objp->dev_attributes)) - return (FALSE); - if (!xdr_specdata3(xdrs, &objp->spec)) - return (FALSE); - return (TRUE); + if (!xdr_sattr3(xdrs, &objp->dev_attributes)) + return (FALSE); + if (!xdr_specdata3(xdrs, &objp->spec)) + return (FALSE); + return (TRUE); } bool_t xdr_mknoddata3(register XDR *xdrs, mknoddata3 *objp) { - if (!xdr_ftype3(xdrs, &objp->type)) - return (FALSE); - switch (objp->type) { - case NFS3CHR: - case NFS3BLK: - if (!xdr_devicedata3(xdrs, &objp->mknoddata3_u.device)) - return (FALSE); - break; - case NFS3SOCK: - case NFS3FIFO: - if (!xdr_sattr3(xdrs, &objp->mknoddata3_u.pipe_attributes)) - return (FALSE); - break; - } - return (TRUE); + if (!xdr_ftype3(xdrs, &objp->type)) + return (FALSE); + switch (objp->type) { + case NFS3CHR: + case NFS3BLK: + if (!xdr_devicedata3(xdrs, &objp->mknoddata3_u.device)) + return (FALSE); + break; + case NFS3SOCK: + case NFS3FIFO: + if (!xdr_sattr3(xdrs, &objp->mknoddata3_u.pipe_attributes)) + return (FALSE); + break; + } + return (TRUE); } bool_t xdr_MKNOD3args(register XDR *xdrs, MKNOD3args *objp) { - if (!xdr_diropargs3(xdrs, &objp->where)) - return (FALSE); - if (!xdr_mknoddata3(xdrs, &objp->what)) - return (FALSE); - return (TRUE); + if (!xdr_diropargs3(xdrs, &objp->where)) + return (FALSE); + if (!xdr_mknoddata3(xdrs, &objp->what)) + return (FALSE); + return (TRUE); } bool_t xdr_MKNOD3resok(register XDR *xdrs, MKNOD3resok *objp) { - if (!xdr_post_op_fh3(xdrs, &objp->obj)) - return (FALSE); - if (!xdr_post_op_attr(xdrs, &objp->obj_attributes)) - return (FALSE); - if (!xdr_wcc_data(xdrs, &objp->dir_wcc)) - return (FALSE); - return (TRUE); + if (!xdr_post_op_fh3(xdrs, &objp->obj)) + return (FALSE); + if (!xdr_post_op_attr(xdrs, &objp->obj_attributes)) + return (FALSE); + if (!xdr_wcc_data(xdrs, &objp->dir_wcc)) + return (FALSE); + return (TRUE); } bool_t xdr_MKNOD3resfail(register XDR *xdrs, MKNOD3resfail *objp) { - if (!xdr_wcc_data(xdrs, &objp->dir_wcc)) - return (FALSE); - return (TRUE); + if (!xdr_wcc_data(xdrs, &objp->dir_wcc)) + return (FALSE); + return (TRUE); } bool_t xdr_MKNOD3res(register XDR *xdrs, MKNOD3res *objp) { - if (!xdr_nfsstat3(xdrs, &objp->status)) - return (FALSE); - switch (objp->status) { - case NFS3_OK: - if (!xdr_MKNOD3resok(xdrs, &objp->MKNOD3res_u.resok)) - return (FALSE); - break; - default: - if (!xdr_MKNOD3resfail(xdrs, &objp->MKNOD3res_u.resfail)) - return (FALSE); - break; - } - return (TRUE); + if (!xdr_nfsstat3(xdrs, &objp->status)) + return (FALSE); + switch (objp->status) { + case NFS3_OK: + if (!xdr_MKNOD3resok(xdrs, &objp->MKNOD3res_u.resok)) + return (FALSE); + break; + default: + if (!xdr_MKNOD3resfail(xdrs, &objp->MKNOD3res_u.resfail)) + return (FALSE); + break; + } + return (TRUE); } bool_t xdr_REMOVE3args(register XDR *xdrs, REMOVE3args *objp) { - if (!xdr_diropargs3(xdrs, &objp->object)) - return (FALSE); - return (TRUE); + if (!xdr_diropargs3(xdrs, &objp->object)) + return (FALSE); + return (TRUE); } bool_t xdr_REMOVE3resok(register XDR *xdrs, REMOVE3resok *objp) { - if (!xdr_wcc_data(xdrs, &objp->dir_wcc)) - return (FALSE); - return (TRUE); + if (!xdr_wcc_data(xdrs, &objp->dir_wcc)) + return (FALSE); + return (TRUE); } bool_t xdr_REMOVE3resfail(register XDR *xdrs, REMOVE3resfail *objp) { - if (!xdr_wcc_data(xdrs, &objp->dir_wcc)) - return (FALSE); - return (TRUE); + if (!xdr_wcc_data(xdrs, &objp->dir_wcc)) + return (FALSE); + return (TRUE); } bool_t xdr_REMOVE3res(register XDR *xdrs, REMOVE3res *objp) { - if (!xdr_nfsstat3(xdrs, &objp->status)) - return (FALSE); - switch (objp->status) { - case NFS3_OK: - if (!xdr_REMOVE3resok(xdrs, &objp->REMOVE3res_u.resok)) - return (FALSE); - break; - default: - if (!xdr_REMOVE3resfail(xdrs, &objp->REMOVE3res_u.resfail)) - return (FALSE); - break; - } - return (TRUE); + if (!xdr_nfsstat3(xdrs, &objp->status)) + return (FALSE); + switch (objp->status) { + case NFS3_OK: + if (!xdr_REMOVE3resok(xdrs, &objp->REMOVE3res_u.resok)) + return (FALSE); + break; + default: + if (!xdr_REMOVE3resfail(xdrs, &objp->REMOVE3res_u.resfail)) + return (FALSE); + break; + } + return (TRUE); } bool_t xdr_RMDIR3args(register XDR *xdrs, RMDIR3args *objp) { - if (!xdr_diropargs3(xdrs, &objp->object)) - return (FALSE); - return (TRUE); + if (!xdr_diropargs3(xdrs, &objp->object)) + return (FALSE); + return (TRUE); } bool_t xdr_RMDIR3resok(register XDR *xdrs, RMDIR3resok *objp) { - if (!xdr_wcc_data(xdrs, &objp->dir_wcc)) - return (FALSE); - return (TRUE); + if (!xdr_wcc_data(xdrs, &objp->dir_wcc)) + return (FALSE); + return (TRUE); } bool_t xdr_RMDIR3resfail(register XDR *xdrs, RMDIR3resfail *objp) { - if (!xdr_wcc_data(xdrs, &objp->dir_wcc)) - return (FALSE); - return (TRUE); + if (!xdr_wcc_data(xdrs, &objp->dir_wcc)) + return (FALSE); + return (TRUE); } bool_t xdr_RMDIR3res(register XDR *xdrs, RMDIR3res *objp) { - if (!xdr_nfsstat3(xdrs, &objp->status)) - return (FALSE); - switch (objp->status) { - case NFS3_OK: - if (!xdr_RMDIR3resok(xdrs, &objp->RMDIR3res_u.resok)) - return (FALSE); - break; - default: - if (!xdr_RMDIR3resfail(xdrs, &objp->RMDIR3res_u.resfail)) - return (FALSE); - break; - } - return (TRUE); + if (!xdr_nfsstat3(xdrs, &objp->status)) + return (FALSE); + switch (objp->status) { + case NFS3_OK: + if (!xdr_RMDIR3resok(xdrs, &objp->RMDIR3res_u.resok)) + return (FALSE); + break; + default: + if (!xdr_RMDIR3resfail(xdrs, &objp->RMDIR3res_u.resfail)) + return (FALSE); + break; + } + return (TRUE); } bool_t xdr_RENAME3args(register XDR *xdrs, RENAME3args *objp) { - if (!xdr_diropargs3(xdrs, &objp->from)) - return (FALSE); - if (!xdr_diropargs3(xdrs, &objp->to)) - return (FALSE); - return (TRUE); + if (!xdr_diropargs3(xdrs, &objp->from)) + return (FALSE); + if (!xdr_diropargs3(xdrs, &objp->to)) + return (FALSE); + return (TRUE); } bool_t xdr_RENAME3resok(register XDR *xdrs, RENAME3resok *objp) { - if (!xdr_wcc_data(xdrs, &objp->fromdir_wcc)) - return (FALSE); - if (!xdr_wcc_data(xdrs, &objp->todir_wcc)) - return (FALSE); - return (TRUE); + if (!xdr_wcc_data(xdrs, &objp->fromdir_wcc)) + return (FALSE); + if (!xdr_wcc_data(xdrs, &objp->todir_wcc)) + return (FALSE); + return (TRUE); } bool_t xdr_RENAME3resfail(register XDR *xdrs, RENAME3resfail *objp) { - if (!xdr_wcc_data(xdrs, &objp->fromdir_wcc)) - return (FALSE); - if (!xdr_wcc_data(xdrs, &objp->todir_wcc)) - return (FALSE); - return (TRUE); + if (!xdr_wcc_data(xdrs, &objp->fromdir_wcc)) + return (FALSE); + if (!xdr_wcc_data(xdrs, &objp->todir_wcc)) + return (FALSE); + return (TRUE); } bool_t xdr_RENAME3res(register XDR *xdrs, RENAME3res *objp) { - if (!xdr_nfsstat3(xdrs, &objp->status)) - return (FALSE); - switch (objp->status) { - case NFS3_OK: - if (!xdr_RENAME3resok(xdrs, &objp->RENAME3res_u.resok)) - return (FALSE); - break; - default: - if (!xdr_RENAME3resfail(xdrs, &objp->RENAME3res_u.resfail)) - return (FALSE); - break; - } - return (TRUE); + if (!xdr_nfsstat3(xdrs, &objp->status)) + return (FALSE); + switch (objp->status) { + case NFS3_OK: + if (!xdr_RENAME3resok(xdrs, &objp->RENAME3res_u.resok)) + return (FALSE); + break; + default: + if (!xdr_RENAME3resfail(xdrs, &objp->RENAME3res_u.resfail)) + return (FALSE); + break; + } + return (TRUE); } bool_t xdr_LINK3args(register XDR *xdrs, LINK3args *objp) { - if (!xdr_nfs_fh3(xdrs, &objp->file)) - return (FALSE); - if (!xdr_diropargs3(xdrs, &objp->link)) - return (FALSE); - return (TRUE); + if (!xdr_nfs_fh3(xdrs, &objp->file)) + return (FALSE); + if (!xdr_diropargs3(xdrs, &objp->link)) + return (FALSE); + return (TRUE); } bool_t xdr_LINK3resok(register XDR *xdrs, LINK3resok *objp) { - if (!xdr_post_op_attr(xdrs, &objp->file_attributes)) - return (FALSE); - if (!xdr_wcc_data(xdrs, &objp->linkdir_wcc)) - return (FALSE); - return (TRUE); + if (!xdr_post_op_attr(xdrs, &objp->file_attributes)) + return (FALSE); + if (!xdr_wcc_data(xdrs, &objp->linkdir_wcc)) + return (FALSE); + return (TRUE); } bool_t xdr_LINK3resfail(register XDR *xdrs, LINK3resfail *objp) { - if (!xdr_post_op_attr(xdrs, &objp->file_attributes)) - return (FALSE); - if (!xdr_wcc_data(xdrs, &objp->linkdir_wcc)) - return (FALSE); - return (TRUE); + if (!xdr_post_op_attr(xdrs, &objp->file_attributes)) + return (FALSE); + if (!xdr_wcc_data(xdrs, &objp->linkdir_wcc)) + return (FALSE); + return (TRUE); } bool_t xdr_LINK3res(register XDR *xdrs, LINK3res *objp) { - if (!xdr_nfsstat3(xdrs, &objp->status)) - return (FALSE); - switch (objp->status) { - case NFS3_OK: - if (!xdr_LINK3resok(xdrs, &objp->LINK3res_u.resok)) - return (FALSE); - break; - default: - if (!xdr_LINK3resfail(xdrs, &objp->LINK3res_u.resfail)) - return (FALSE); - break; - } - return (TRUE); + if (!xdr_nfsstat3(xdrs, &objp->status)) + return (FALSE); + switch (objp->status) { + case NFS3_OK: + if (!xdr_LINK3resok(xdrs, &objp->LINK3res_u.resok)) + return (FALSE); + break; + default: + if (!xdr_LINK3resfail(xdrs, &objp->LINK3res_u.resfail)) + return (FALSE); + break; + } + return (TRUE); } bool_t xdr_READDIR3args(register XDR *xdrs, READDIR3args *objp) { - if (!xdr_nfs_fh3(xdrs, &objp->dir)) - return (FALSE); - if (!xdr_cookie3(xdrs, &objp->cookie)) - return (FALSE); - if (!xdr_cookieverf3(xdrs, objp->cookieverf)) - return (FALSE); - if (!xdr_count3(xdrs, &objp->count)) - return (FALSE); - return (TRUE); + if (!xdr_nfs_fh3(xdrs, &objp->dir)) + return (FALSE); + if (!xdr_cookie3(xdrs, &objp->cookie)) + return (FALSE); + if (!xdr_cookieverf3(xdrs, objp->cookieverf)) + return (FALSE); + if (!xdr_count3(xdrs, &objp->count)) + return (FALSE); + return (TRUE); } bool_t xdr_entry3(register XDR *xdrs, entry3 *objp) { - if (!xdr_fileid3(xdrs, &objp->fileid)) - return (FALSE); - if (!xdr_filename3(xdrs, &objp->name)) - return (FALSE); - if (!xdr_cookie3(xdrs, &objp->cookie)) - return (FALSE); - if (!xdr_pointer(xdrs, (char **)&objp->nextentry, sizeof (entry3), (xdrproc_t) xdr_entry3)) - return (FALSE); - return (TRUE); + if (!xdr_fileid3(xdrs, &objp->fileid)) + return (FALSE); + if (!xdr_filename3(xdrs, &objp->name)) + return (FALSE); + if (!xdr_cookie3(xdrs, &objp->cookie)) + return (FALSE); + if (!xdr_pointer(xdrs, (char **)&objp->nextentry, sizeof (entry3), (xdrproc_t) xdr_entry3)) + return (FALSE); + return (TRUE); } bool_t xdr_dirlist3(register XDR *xdrs, dirlist3 *objp) { - if (!xdr_pointer(xdrs, (char **)&objp->entries, sizeof (entry3), (xdrproc_t) xdr_entry3)) - return (FALSE); - if (!xdr_bool(xdrs, &objp->eof)) - return (FALSE); - return (TRUE); + if (!xdr_pointer(xdrs, (char **)&objp->entries, sizeof (entry3), (xdrproc_t) xdr_entry3)) + return (FALSE); + if (!xdr_bool(xdrs, &objp->eof)) + return (FALSE); + return (TRUE); } bool_t xdr_READDIR3resok(register XDR *xdrs, READDIR3resok *objp) { - if (!xdr_post_op_attr(xdrs, &objp->dir_attributes)) - return (FALSE); - if (!xdr_cookieverf3(xdrs, objp->cookieverf)) - return (FALSE); - if (!xdr_dirlist3(xdrs, &objp->reply)) - return (FALSE); - return (TRUE); + if (!xdr_post_op_attr(xdrs, &objp->dir_attributes)) + return (FALSE); + if (!xdr_cookieverf3(xdrs, objp->cookieverf)) + return (FALSE); + if (!xdr_dirlist3(xdrs, &objp->reply)) + return (FALSE); + return (TRUE); } bool_t xdr_READDIR3resfail(register XDR *xdrs, READDIR3resfail *objp) { - if (!xdr_post_op_attr(xdrs, &objp->dir_attributes)) - return (FALSE); - return (TRUE); + if (!xdr_post_op_attr(xdrs, &objp->dir_attributes)) + return (FALSE); + return (TRUE); } bool_t xdr_READDIR3res(register XDR *xdrs, READDIR3res *objp) { - if (!xdr_nfsstat3(xdrs, &objp->status)) - return (FALSE); - switch (objp->status) { - case NFS3_OK: - if (!xdr_READDIR3resok(xdrs, &objp->READDIR3res_u.resok)) - return (FALSE); - break; - default: - if (!xdr_READDIR3resfail(xdrs, &objp->READDIR3res_u.resfail)) - return (FALSE); - break; - } - return (TRUE); + if (!xdr_nfsstat3(xdrs, &objp->status)) + return (FALSE); + switch (objp->status) { + case NFS3_OK: + if (!xdr_READDIR3resok(xdrs, &objp->READDIR3res_u.resok)) + return (FALSE); + break; + default: + if (!xdr_READDIR3resfail(xdrs, &objp->READDIR3res_u.resfail)) + return (FALSE); + break; + } + return (TRUE); } bool_t xdr_READDIRPLUS3args(register XDR *xdrs, READDIRPLUS3args *objp) { - if (!xdr_nfs_fh3(xdrs, &objp->dir)) - return (FALSE); - if (!xdr_cookie3(xdrs, &objp->cookie)) - return (FALSE); - if (!xdr_cookieverf3(xdrs, objp->cookieverf)) - return (FALSE); - if (!xdr_count3(xdrs, &objp->dircount)) - return (FALSE); - if (!xdr_count3(xdrs, &objp->maxcount)) - return (FALSE); - return (TRUE); + if (!xdr_nfs_fh3(xdrs, &objp->dir)) + return (FALSE); + if (!xdr_cookie3(xdrs, &objp->cookie)) + return (FALSE); + if (!xdr_cookieverf3(xdrs, objp->cookieverf)) + return (FALSE); + if (!xdr_count3(xdrs, &objp->dircount)) + return (FALSE); + if (!xdr_count3(xdrs, &objp->maxcount)) + return (FALSE); + return (TRUE); } bool_t xdr_entryplus3(register XDR *xdrs, entryplus3 *objp) { - if (!xdr_fileid3(xdrs, &objp->fileid)) - return (FALSE); - if (!xdr_filename3(xdrs, &objp->name)) - return (FALSE); - if (!xdr_cookie3(xdrs, &objp->cookie)) - return (FALSE); - if (!xdr_post_op_attr(xdrs, &objp->name_attributes)) - return (FALSE); - if (!xdr_post_op_fh3(xdrs, &objp->name_handle)) - return (FALSE); - if (!xdr_pointer(xdrs, (char **)&objp->nextentry, sizeof (entryplus3), (xdrproc_t) xdr_entryplus3)) - return (FALSE); - return (TRUE); + if (!xdr_fileid3(xdrs, &objp->fileid)) + return (FALSE); + if (!xdr_filename3(xdrs, &objp->name)) + return (FALSE); + if (!xdr_cookie3(xdrs, &objp->cookie)) + return (FALSE); + if (!xdr_post_op_attr(xdrs, &objp->name_attributes)) + return (FALSE); + if (!xdr_post_op_fh3(xdrs, &objp->name_handle)) + return (FALSE); + if (!xdr_pointer(xdrs, (char **)&objp->nextentry, sizeof (entryplus3), (xdrproc_t) xdr_entryplus3)) + return (FALSE); + return (TRUE); } bool_t xdr_dirlistplus3(register XDR *xdrs, dirlistplus3 *objp) { - if (!xdr_pointer(xdrs, (char **)&objp->entries, sizeof (entryplus3), (xdrproc_t) xdr_entryplus3)) - return (FALSE); - if (!xdr_bool(xdrs, &objp->eof)) - return (FALSE); - return (TRUE); + if (!xdr_pointer(xdrs, (char **)&objp->entries, sizeof (entryplus3), (xdrproc_t) xdr_entryplus3)) + return (FALSE); + if (!xdr_bool(xdrs, &objp->eof)) + return (FALSE); + return (TRUE); } bool_t xdr_READDIRPLUS3resok(register XDR *xdrs, READDIRPLUS3resok *objp) { - if (!xdr_post_op_attr(xdrs, &objp->dir_attributes)) - return (FALSE); - if (!xdr_cookieverf3(xdrs, objp->cookieverf)) - return (FALSE); - if (!xdr_dirlistplus3(xdrs, &objp->reply)) - return (FALSE); - return (TRUE); + if (!xdr_post_op_attr(xdrs, &objp->dir_attributes)) + return (FALSE); + if (!xdr_cookieverf3(xdrs, objp->cookieverf)) + return (FALSE); + if (!xdr_dirlistplus3(xdrs, &objp->reply)) + return (FALSE); + return (TRUE); } bool_t xdr_READDIRPLUS3resfail(register XDR *xdrs, READDIRPLUS3resfail *objp) { - if (!xdr_post_op_attr(xdrs, &objp->dir_attributes)) - return (FALSE); - return (TRUE); + if (!xdr_post_op_attr(xdrs, &objp->dir_attributes)) + return (FALSE); + return (TRUE); } bool_t xdr_READDIRPLUS3res(register XDR *xdrs, READDIRPLUS3res *objp) { - if (!xdr_nfsstat3(xdrs, &objp->status)) - return (FALSE); - switch (objp->status) { - case NFS3_OK: - if (!xdr_READDIRPLUS3resok(xdrs, &objp->READDIRPLUS3res_u.resok)) - return (FALSE); - break; - default: - if (!xdr_READDIRPLUS3resfail(xdrs, &objp->READDIRPLUS3res_u.resfail)) - return (FALSE); - break; - } - return (TRUE); + if (!xdr_nfsstat3(xdrs, &objp->status)) + return (FALSE); + switch (objp->status) { + case NFS3_OK: + if (!xdr_READDIRPLUS3resok(xdrs, &objp->READDIRPLUS3res_u.resok)) + return (FALSE); + break; + default: + if (!xdr_READDIRPLUS3resfail(xdrs, &objp->READDIRPLUS3res_u.resfail)) + return (FALSE); + break; + } + return (TRUE); } bool_t xdr_FSSTAT3args(register XDR *xdrs, FSSTAT3args *objp) { - if (!xdr_nfs_fh3(xdrs, &objp->fsroot)) - return (FALSE); - return (TRUE); + if (!xdr_nfs_fh3(xdrs, &objp->fsroot)) + return (FALSE); + return (TRUE); } bool_t xdr_FSSTAT3resok(register XDR *xdrs, FSSTAT3resok *objp) { - if (!xdr_post_op_attr(xdrs, &objp->obj_attributes)) - return (FALSE); - if (!xdr_size3(xdrs, &objp->tbytes)) - return (FALSE); - if (!xdr_size3(xdrs, &objp->fbytes)) - return (FALSE); - if (!xdr_size3(xdrs, &objp->abytes)) - return (FALSE); - if (!xdr_size3(xdrs, &objp->tfiles)) - return (FALSE); - if (!xdr_size3(xdrs, &objp->ffiles)) - return (FALSE); - if (!xdr_size3(xdrs, &objp->afiles)) - return (FALSE); - if (!xdr_uint32(xdrs, &objp->invarsec)) - return (FALSE); - return (TRUE); + if (!xdr_post_op_attr(xdrs, &objp->obj_attributes)) + return (FALSE); + if (!xdr_size3(xdrs, &objp->tbytes)) + return (FALSE); + if (!xdr_size3(xdrs, &objp->fbytes)) + return (FALSE); + if (!xdr_size3(xdrs, &objp->abytes)) + return (FALSE); + if (!xdr_size3(xdrs, &objp->tfiles)) + return (FALSE); + if (!xdr_size3(xdrs, &objp->ffiles)) + return (FALSE); + if (!xdr_size3(xdrs, &objp->afiles)) + return (FALSE); + if (!xdr_uint32(xdrs, &objp->invarsec)) + return (FALSE); + return (TRUE); } bool_t xdr_FSSTAT3resfail(register XDR *xdrs, FSSTAT3resfail *objp) { - if (!xdr_post_op_attr(xdrs, &objp->obj_attributes)) - return (FALSE); - return (TRUE); + if (!xdr_post_op_attr(xdrs, &objp->obj_attributes)) + return (FALSE); + return (TRUE); } bool_t xdr_FSSTAT3res(register XDR *xdrs, FSSTAT3res *objp) { - if (!xdr_nfsstat3(xdrs, &objp->status)) - return (FALSE); - switch (objp->status) { - case NFS3_OK: - if (!xdr_FSSTAT3resok(xdrs, &objp->FSSTAT3res_u.resok)) - return (FALSE); - break; - default: - if (!xdr_FSSTAT3resfail(xdrs, &objp->FSSTAT3res_u.resfail)) - return (FALSE); - break; - } - return (TRUE); + if (!xdr_nfsstat3(xdrs, &objp->status)) + return (FALSE); + switch (objp->status) { + case NFS3_OK: + if (!xdr_FSSTAT3resok(xdrs, &objp->FSSTAT3res_u.resok)) + return (FALSE); + break; + default: + if (!xdr_FSSTAT3resfail(xdrs, &objp->FSSTAT3res_u.resfail)) + return (FALSE); + break; + } + return (TRUE); } bool_t xdr_FSINFO3args(register XDR *xdrs, FSINFO3args *objp) { - if (!xdr_nfs_fh3(xdrs, &objp->fsroot)) - return (FALSE); - return (TRUE); + if (!xdr_nfs_fh3(xdrs, &objp->fsroot)) + return (FALSE); + return (TRUE); } bool_t xdr_FSINFO3resok(register XDR *xdrs, FSINFO3resok *objp) { - if (!xdr_post_op_attr(xdrs, &objp->obj_attributes)) - return (FALSE); - if (!xdr_uint32(xdrs, &objp->rtmax)) - return (FALSE); - if (!xdr_uint32(xdrs, &objp->rtpref)) - return (FALSE); - if (!xdr_uint32(xdrs, &objp->rtmult)) - return (FALSE); - if (!xdr_uint32(xdrs, &objp->wtmax)) - return (FALSE); - if (!xdr_uint32(xdrs, &objp->wtpref)) - return (FALSE); - if (!xdr_uint32(xdrs, &objp->wtmult)) - return (FALSE); - if (!xdr_uint32(xdrs, &objp->dtpref)) - return (FALSE); - if (!xdr_size3(xdrs, &objp->maxfilesize)) - return (FALSE); - if (!xdr_nfstime3(xdrs, &objp->time_delta)) - return (FALSE); - if (!xdr_uint32(xdrs, &objp->properties)) - return (FALSE); - return (TRUE); + if (!xdr_post_op_attr(xdrs, &objp->obj_attributes)) + return (FALSE); + if (!xdr_uint32(xdrs, &objp->rtmax)) + return (FALSE); + if (!xdr_uint32(xdrs, &objp->rtpref)) + return (FALSE); + if (!xdr_uint32(xdrs, &objp->rtmult)) + return (FALSE); + if (!xdr_uint32(xdrs, &objp->wtmax)) + return (FALSE); + if (!xdr_uint32(xdrs, &objp->wtpref)) + return (FALSE); + if (!xdr_uint32(xdrs, &objp->wtmult)) + return (FALSE); + if (!xdr_uint32(xdrs, &objp->dtpref)) + return (FALSE); + if (!xdr_size3(xdrs, &objp->maxfilesize)) + return (FALSE); + if (!xdr_nfstime3(xdrs, &objp->time_delta)) + return (FALSE); + if (!xdr_uint32(xdrs, &objp->properties)) + return (FALSE); + return (TRUE); } bool_t xdr_FSINFO3resfail(register XDR *xdrs, FSINFO3resfail *objp) { - if (!xdr_post_op_attr(xdrs, &objp->obj_attributes)) - return (FALSE); - return (TRUE); + if (!xdr_post_op_attr(xdrs, &objp->obj_attributes)) + return (FALSE); + return (TRUE); } bool_t xdr_FSINFO3res(register XDR *xdrs, FSINFO3res *objp) { - if (!xdr_nfsstat3(xdrs, &objp->status)) - return (FALSE); - switch (objp->status) { - case NFS3_OK: - if (!xdr_FSINFO3resok(xdrs, &objp->FSINFO3res_u.resok)) - return (FALSE); - break; - default: - if (!xdr_FSINFO3resfail(xdrs, &objp->FSINFO3res_u.resfail)) - return (FALSE); - break; - } - return (TRUE); + if (!xdr_nfsstat3(xdrs, &objp->status)) + return (FALSE); + switch (objp->status) { + case NFS3_OK: + if (!xdr_FSINFO3resok(xdrs, &objp->FSINFO3res_u.resok)) + return (FALSE); + break; + default: + if (!xdr_FSINFO3resfail(xdrs, &objp->FSINFO3res_u.resfail)) + return (FALSE); + break; + } + return (TRUE); } bool_t xdr_PATHCONF3args(register XDR *xdrs, PATHCONF3args *objp) { - if (!xdr_nfs_fh3(xdrs, &objp->object)) - return (FALSE); - return (TRUE); + if (!xdr_nfs_fh3(xdrs, &objp->object)) + return (FALSE); + return (TRUE); } bool_t xdr_PATHCONF3resok(register XDR *xdrs, PATHCONF3resok *objp) { - if (!xdr_post_op_attr(xdrs, &objp->obj_attributes)) - return (FALSE); - if (!xdr_uint32(xdrs, &objp->linkmax)) - return (FALSE); - if (!xdr_uint32(xdrs, &objp->name_max)) - return (FALSE); - if (!xdr_bool(xdrs, &objp->no_trunc)) - return (FALSE); - if (!xdr_bool(xdrs, &objp->chown_restricted)) - return (FALSE); - if (!xdr_bool(xdrs, &objp->case_insensitive)) - return (FALSE); - if (!xdr_bool(xdrs, &objp->case_preserving)) - return (FALSE); - return (TRUE); + if (!xdr_post_op_attr(xdrs, &objp->obj_attributes)) + return (FALSE); + if (!xdr_uint32(xdrs, &objp->linkmax)) + return (FALSE); + if (!xdr_uint32(xdrs, &objp->name_max)) + return (FALSE); + if (!xdr_bool(xdrs, &objp->no_trunc)) + return (FALSE); + if (!xdr_bool(xdrs, &objp->chown_restricted)) + return (FALSE); + if (!xdr_bool(xdrs, &objp->case_insensitive)) + return (FALSE); + if (!xdr_bool(xdrs, &objp->case_preserving)) + return (FALSE); + return (TRUE); } bool_t xdr_PATHCONF3resfail(register XDR *xdrs, PATHCONF3resfail *objp) { - if (!xdr_post_op_attr(xdrs, &objp->obj_attributes)) - return (FALSE); - return (TRUE); + if (!xdr_post_op_attr(xdrs, &objp->obj_attributes)) + return (FALSE); + return (TRUE); } bool_t xdr_PATHCONF3res(register XDR *xdrs, PATHCONF3res *objp) { - if (!xdr_nfsstat3(xdrs, &objp->status)) - return (FALSE); - switch (objp->status) { - case NFS3_OK: - if (!xdr_PATHCONF3resok(xdrs, &objp->PATHCONF3res_u.resok)) - return (FALSE); - break; - default: - if (!xdr_PATHCONF3resfail(xdrs, &objp->PATHCONF3res_u.resfail)) - return (FALSE); - break; - } - return (TRUE); + if (!xdr_nfsstat3(xdrs, &objp->status)) + return (FALSE); + switch (objp->status) { + case NFS3_OK: + if (!xdr_PATHCONF3resok(xdrs, &objp->PATHCONF3res_u.resok)) + return (FALSE); + break; + default: + if (!xdr_PATHCONF3resfail(xdrs, &objp->PATHCONF3res_u.resfail)) + return (FALSE); + break; + } + return (TRUE); } bool_t xdr_COMMIT3args(register XDR *xdrs, COMMIT3args *objp) { - if (!xdr_nfs_fh3(xdrs, &objp->file)) - return (FALSE); - if (!xdr_offset3(xdrs, &objp->offset)) - return (FALSE); - if (!xdr_count3(xdrs, &objp->count)) - return (FALSE); - return (TRUE); + if (!xdr_nfs_fh3(xdrs, &objp->file)) + return (FALSE); + if (!xdr_offset3(xdrs, &objp->offset)) + return (FALSE); + if (!xdr_count3(xdrs, &objp->count)) + return (FALSE); + return (TRUE); } bool_t xdr_COMMIT3resok(register XDR *xdrs, COMMIT3resok *objp) { - if (!xdr_wcc_data(xdrs, &objp->file_wcc)) - return (FALSE); - if (!xdr_writeverf3(xdrs, objp->verf)) - return (FALSE); - return (TRUE); + if (!xdr_wcc_data(xdrs, &objp->file_wcc)) + return (FALSE); + if (!xdr_writeverf3(xdrs, objp->verf)) + return (FALSE); + return (TRUE); } bool_t xdr_COMMIT3resfail(register XDR *xdrs, COMMIT3resfail *objp) { - if (!xdr_wcc_data(xdrs, &objp->file_wcc)) - return (FALSE); - return (TRUE); + if (!xdr_wcc_data(xdrs, &objp->file_wcc)) + return (FALSE); + return (TRUE); } bool_t xdr_COMMIT3res(register XDR *xdrs, COMMIT3res *objp) { - if (!xdr_nfsstat3(xdrs, &objp->status)) - return (FALSE); - switch (objp->status) { - case NFS3_OK: - if (!xdr_COMMIT3resok(xdrs, &objp->COMMIT3res_u.resok)) - return (FALSE); - break; - default: - if (!xdr_COMMIT3resfail(xdrs, &objp->COMMIT3res_u.resfail)) - return (FALSE); - break; - } - return (TRUE); + if (!xdr_nfsstat3(xdrs, &objp->status)) + return (FALSE); + switch (objp->status) { + case NFS3_OK: + if (!xdr_COMMIT3resok(xdrs, &objp->COMMIT3res_u.resok)) + return (FALSE); + break; + default: + if (!xdr_COMMIT3resfail(xdrs, &objp->COMMIT3res_u.resfail)) + return (FALSE); + break; + } + return (TRUE); } diff --git a/components/dfs/filesystems/nfs/rpc/auth.h b/components/dfs/filesystems/nfs/rpc/auth.h index f7dd76c237..0dc947a887 100644 --- a/components/dfs/filesystems/nfs/rpc/auth.h +++ b/components/dfs/filesystems/nfs/rpc/auth.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,28 +15,28 @@ * Status returned from authentication check */ enum auth_stat { - AUTH_OK=0, - /* - * failed at remote end - */ - AUTH_BADCRED=1, /* bogus credentials (seal broken) */ - AUTH_REJECTEDCRED=2, /* client should begin new session */ - AUTH_BADVERF=3, /* bogus verifier (seal broken) */ - AUTH_REJECTEDVERF=4, /* verifier expired or was replayed */ - AUTH_TOOWEAK=5, /* rejected due to security reasons */ - /* - * failed locally - */ - AUTH_INVALIDRESP=6, /* bogus response verifier */ - AUTH_FAILED=7 /* some unknown reason */ + AUTH_OK=0, + /* + * failed at remote end + */ + AUTH_BADCRED=1, /* bogus credentials (seal broken) */ + AUTH_REJECTEDCRED=2, /* client should begin new session */ + AUTH_BADVERF=3, /* bogus verifier (seal broken) */ + AUTH_REJECTEDVERF=4, /* verifier expired or was replayed */ + AUTH_TOOWEAK=5, /* rejected due to security reasons */ + /* + * failed locally + */ + AUTH_INVALIDRESP=6, /* bogus response verifier */ + AUTH_FAILED=7 /* some unknown reason */ }; union des_block { - struct { - uint32_t high; - uint32_t low; - } key; - char c[8]; + struct { + uint32_t high; + uint32_t low; + } key; + char c[8]; }; typedef union des_block des_block; @@ -44,9 +44,9 @@ typedef union des_block des_block; * Authentication info. Opaque to client. */ struct opaque_auth { - enum_t oa_flavor; /* flavor of auth */ - char* oa_base; /* address of more auth stuff */ - unsigned int oa_length; /* not to exceed MAX_AUTH_BYTES */ + enum_t oa_flavor; /* flavor of auth */ + char* oa_base; /* address of more auth stuff */ + unsigned int oa_length; /* not to exceed MAX_AUTH_BYTES */ }; /* @@ -59,11 +59,11 @@ struct AUTH { union des_block ah_key; struct auth_ops { void (*ah_nextverf) (AUTH *); - int (*ah_marshal) (AUTH *, XDR *); /* nextverf & serialize */ + int (*ah_marshal) (AUTH *, XDR *); /* nextverf & serialize */ int (*ah_validate) (AUTH *, struct opaque_auth *); - /* validate verifier */ - int (*ah_refresh) (AUTH *); /* refresh credentials */ - void (*ah_destroy) (AUTH *); /* destroy this structure */ + /* validate verifier */ + int (*ah_refresh) (AUTH *); /* refresh credentials */ + void (*ah_destroy) (AUTH *); /* destroy this structure */ } *ah_ops; char* ah_private; }; @@ -75,37 +75,37 @@ extern struct opaque_auth _null_auth; * Authentication ops. * The ops and the auth handle provide the interface to the authenticators. * - * AUTH *auth; - * XDR *xdrs; + * AUTH *auth; + * XDR *xdrs; * struct opaque_auth verf; */ -#define AUTH_NEXTVERF(auth) \ - ((*((auth)->ah_ops->ah_nextverf))(auth)) -#define auth_nextverf(auth) \ - ((*((auth)->ah_ops->ah_nextverf))(auth)) +#define AUTH_NEXTVERF(auth) \ + ((*((auth)->ah_ops->ah_nextverf))(auth)) +#define auth_nextverf(auth) \ + ((*((auth)->ah_ops->ah_nextverf))(auth)) -#define AUTH_MARSHALL(auth, xdrs) \ - ((*((auth)->ah_ops->ah_marshal))(auth, xdrs)) -#define auth_marshall(auth, xdrs) \ - ((*((auth)->ah_ops->ah_marshal))(auth, xdrs)) +#define AUTH_MARSHALL(auth, xdrs) \ + ((*((auth)->ah_ops->ah_marshal))(auth, xdrs)) +#define auth_marshall(auth, xdrs) \ + ((*((auth)->ah_ops->ah_marshal))(auth, xdrs)) -#define AUTH_VALIDATE(auth, verfp) \ - ((*((auth)->ah_ops->ah_validate))((auth), verfp)) -#define auth_validate(auth, verfp) \ - ((*((auth)->ah_ops->ah_validate))((auth), verfp)) +#define AUTH_VALIDATE(auth, verfp) \ + ((*((auth)->ah_ops->ah_validate))((auth), verfp)) +#define auth_validate(auth, verfp) \ + ((*((auth)->ah_ops->ah_validate))((auth), verfp)) -#define AUTH_REFRESH(auth) \ - ((*((auth)->ah_ops->ah_refresh))(auth)) -#define auth_refresh(auth) \ - ((*((auth)->ah_ops->ah_refresh))(auth)) +#define AUTH_REFRESH(auth) \ + ((*((auth)->ah_ops->ah_refresh))(auth)) +#define auth_refresh(auth) \ + ((*((auth)->ah_ops->ah_refresh))(auth)) -#define AUTH_DESTROY(auth) \ - ((*((auth)->ah_ops->ah_destroy))(auth)) -#define auth_destroy(auth) \ - ((*((auth)->ah_ops->ah_destroy))(auth)) +#define AUTH_DESTROY(auth) \ + ((*((auth)->ah_ops->ah_destroy))(auth)) +#define auth_destroy(auth) \ + ((*((auth)->ah_ops->ah_destroy))(auth)) -#define MAX_AUTH_BYTES 400 -#define MAXNETNAMELEN 255 /* maximum length of network user's name */ +#define MAX_AUTH_BYTES 400 +#define MAXNETNAMELEN 255 /* maximum length of network user's name */ AUTH *authnone_create(void); diff --git a/components/dfs/filesystems/nfs/rpc/auth_none.c b/components/dfs/filesystems/nfs/rpc/auth_none.c index 9f5ad05002..7e22e7d864 100644 --- a/components/dfs/filesystems/nfs/rpc/auth_none.c +++ b/components/dfs/filesystems/nfs/rpc/auth_none.c @@ -1,12 +1,12 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes */ -/* @(#)auth_none.c 2.1 88/07/29 4.0 RPCSRC */ +/* @(#)auth_none.c 2.1 88/07/29 4.0 RPCSRC */ /* * Sun RPC is a product of Sun Microsystems, Inc. and is provided for * unrestricted use provided that this legend is included on all tape @@ -14,23 +14,23 @@ * may copy or modify Sun RPC without charge, but are not authorized * to license or distribute it to anyone else except as part of a product or * program developed by the user. - * + * * SUN RPC IS PROVIDED AS IS WITH NO WARRANTIES OF ANY KIND INCLUDING THE * WARRANTIES OF DESIGN, MERCHANTIBILITY AND FITNESS FOR A PARTICULAR * PURPOSE, OR ARISING FROM A COURSE OF DEALING, USAGE OR TRADE PRACTICE. - * + * * Sun RPC is provided with no support and without any obligation on the * part of Sun Microsystems, Inc. to assist in its use, correction, * modification or enhancement. - * + * * SUN MICROSYSTEMS, INC. SHALL HAVE NO LIABILITY WITH RESPECT TO THE * INFRINGEMENT OF COPYRIGHTS, TRADE SECRETS OR ANY PATENTS BY SUN RPC * OR ANY PART THEREOF. - * + * * In no event will Sun Microsystems, Inc. be liable for any lost revenue * or profits or other special, indirect and consequential damages, even if * Sun has been advised of the possibility of such damages. - * + * * Sun Microsystems, Inc. * 2550 Garcia Avenue * Mountain View, California 94043 @@ -38,15 +38,15 @@ #if !defined(lint) && defined(SCCSIDS) static char sccsid[] = - "@(#)auth_none.c 1.19 87/08/11 Copyr 1984 Sun Micro"; + "@(#)auth_none.c 1.19 87/08/11 Copyr 1984 Sun Micro"; #endif /* * auth_none.c - * Creates a client authentication handle for passing "null" - * credentials and verifiers to remote systems. - * - * Copyright (C) 1984, Sun Microsystems, Inc. + * Creates a client authentication handle for passing "null" + * credentials and verifiers to remote systems. + * + * Copyright (C) 1984, Sun Microsystems, Inc. */ #include @@ -63,55 +63,55 @@ static bool_t authnone_marshal(AUTH *client, XDR *xdrs); struct opaque_auth _null_auth; static struct auth_ops ops = { - authnone_verf, - authnone_marshal, - authnone_validate, - authnone_refresh, - authnone_destroy + authnone_verf, + authnone_marshal, + authnone_validate, + authnone_refresh, + authnone_destroy }; static struct authnone_private { - AUTH no_client; - char marshalled_client[MAX_MARSHEL_SIZE]; - unsigned int mcnt; + AUTH no_client; + char marshalled_client[MAX_MARSHEL_SIZE]; + unsigned int mcnt; } *authnone_private; AUTH *authnone_create() { - register struct authnone_private *ap = authnone_private; - XDR xdr_stream; - register XDR *xdrs; + register struct authnone_private *ap = authnone_private; + XDR xdr_stream; + register XDR *xdrs; extern bool_t xdr_opaque_auth(XDR *xdrs, struct opaque_auth *ap); - if (ap == 0) { - ap = (struct authnone_private *) rt_malloc (sizeof(*ap)); - if (ap == 0) return NULL; - memset(ap, 0, sizeof(*ap)); - authnone_private = ap; - } - if (!ap->mcnt) { - ap->no_client.ah_cred = ap->no_client.ah_verf = _null_auth; - ap->no_client.ah_ops = &ops; - xdrs = &xdr_stream; - xdrmem_create(xdrs, ap->marshalled_client, - (unsigned int) MAX_MARSHEL_SIZE, XDR_ENCODE); - (void) xdr_opaque_auth(xdrs, &ap->no_client.ah_cred); - (void) xdr_opaque_auth(xdrs, &ap->no_client.ah_verf); - ap->mcnt = XDR_GETPOS(xdrs); - XDR_DESTROY(xdrs); - } - return (&ap->no_client); + if (ap == 0) { + ap = (struct authnone_private *) rt_malloc (sizeof(*ap)); + if (ap == 0) return NULL; + memset(ap, 0, sizeof(*ap)); + authnone_private = ap; + } + if (!ap->mcnt) { + ap->no_client.ah_cred = ap->no_client.ah_verf = _null_auth; + ap->no_client.ah_ops = &ops; + xdrs = &xdr_stream; + xdrmem_create(xdrs, ap->marshalled_client, + (unsigned int) MAX_MARSHEL_SIZE, XDR_ENCODE); + (void) xdr_opaque_auth(xdrs, &ap->no_client.ah_cred); + (void) xdr_opaque_auth(xdrs, &ap->no_client.ah_verf); + ap->mcnt = XDR_GETPOS(xdrs); + XDR_DESTROY(xdrs); + } + return (&ap->no_client); } -/*ARGSUSED*/ +/*ARGSUSED*/ static bool_t authnone_marshal(AUTH *client, XDR *xdrs) { - register struct authnone_private *ap = authnone_private; + register struct authnone_private *ap = authnone_private; - if (ap == 0) - return (0); - return ((*xdrs->x_ops->x_putbytes) (xdrs, - ap->marshalled_client, ap->mcnt)); + if (ap == 0) + return (0); + return ((*xdrs->x_ops->x_putbytes) (xdrs, + ap->marshalled_client, ap->mcnt)); } static void authnone_verf(AUTH *x) @@ -121,13 +121,13 @@ static void authnone_verf(AUTH *x) static bool_t authnone_validate(AUTH *x, struct opaque_auth *x1) { - return (TRUE); + return (TRUE); } static bool_t authnone_refresh(AUTH *x) { - return (FALSE); + return (FALSE); } static void authnone_destroy(AUTH *x) diff --git a/components/dfs/filesystems/nfs/rpc/clnt.h b/components/dfs/filesystems/nfs/rpc/clnt.h index e86f8be789..1d27dee359 100644 --- a/components/dfs/filesystems/nfs/rpc/clnt.h +++ b/components/dfs/filesystems/nfs/rpc/clnt.h @@ -1,12 +1,12 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes */ -/* @(#)clnt.h 2.1 88/07/29 4.0 RPCSRC; from 1.31 88/02/08 SMI*/ +/* @(#)clnt.h 2.1 88/07/29 4.0 RPCSRC; from 1.31 88/02/08 SMI*/ /* * Sun RPC is a product of Sun Microsystems, Inc. and is provided for * unrestricted use provided that this legend is included on all tape @@ -43,7 +43,7 @@ */ #ifndef _RPC_CLNT_H -#define _RPC_CLNT_H 1 +#define _RPC_CLNT_H 1 #include #include @@ -55,47 +55,47 @@ * independent) list of errors. */ enum clnt_stat { - RPC_SUCCESS=0, /* call succeeded */ - /* - * local errors - */ - RPC_CANTENCODEARGS=1, /* can't encode arguments */ - RPC_CANTDECODERES=2, /* can't decode results */ - RPC_CANTSEND=3, /* failure in sending call */ - RPC_CANTRECV=4, /* failure in receiving result */ - RPC_TIMEDOUT=5, /* call timed out */ - /* - * remote errors - */ - RPC_VERSMISMATCH=6, /* rpc versions not compatible */ - RPC_AUTHERROR=7, /* authentication error */ - RPC_PROGUNAVAIL=8, /* program not available */ - RPC_PROGVERSMISMATCH=9, /* program version mismatched */ - RPC_PROCUNAVAIL=10, /* procedure unavailable */ - RPC_CANTDECODEARGS=11, /* decode arguments error */ - RPC_SYSTEMERROR=12, /* generic "other problem" */ - RPC_NOBROADCAST = 21, /* Broadcasting not supported */ - /* - * callrpc & clnt_create errors - */ - RPC_UNKNOWNHOST=13, /* unknown host name */ - RPC_UNKNOWNPROTO=17, /* unknown protocol */ - RPC_UNKNOWNADDR = 19, /* Remote address unknown */ + RPC_SUCCESS=0, /* call succeeded */ + /* + * local errors + */ + RPC_CANTENCODEARGS=1, /* can't encode arguments */ + RPC_CANTDECODERES=2, /* can't decode results */ + RPC_CANTSEND=3, /* failure in sending call */ + RPC_CANTRECV=4, /* failure in receiving result */ + RPC_TIMEDOUT=5, /* call timed out */ + /* + * remote errors + */ + RPC_VERSMISMATCH=6, /* rpc versions not compatible */ + RPC_AUTHERROR=7, /* authentication error */ + RPC_PROGUNAVAIL=8, /* program not available */ + RPC_PROGVERSMISMATCH=9, /* program version mismatched */ + RPC_PROCUNAVAIL=10, /* procedure unavailable */ + RPC_CANTDECODEARGS=11, /* decode arguments error */ + RPC_SYSTEMERROR=12, /* generic "other problem" */ + RPC_NOBROADCAST = 21, /* Broadcasting not supported */ + /* + * callrpc & clnt_create errors + */ + RPC_UNKNOWNHOST=13, /* unknown host name */ + RPC_UNKNOWNPROTO=17, /* unknown protocol */ + RPC_UNKNOWNADDR = 19, /* Remote address unknown */ - /* - * rpcbind errors - */ - RPC_RPCBFAILURE=14, /* portmapper failed in its call */ + /* + * rpcbind errors + */ + RPC_RPCBFAILURE=14, /* portmapper failed in its call */ #define RPC_PMAPFAILURE RPC_RPCBFAILURE - RPC_PROGNOTREGISTERED=15, /* remote program is not registered */ - RPC_N2AXLATEFAILURE = 22, /* Name to addr translation failed */ - /* - * unspecified error - */ - RPC_FAILED=16, - RPC_INTR=18, - RPC_TLIERROR=20, - RPC_UDERROR=23, + RPC_PROGNOTREGISTERED=15, /* remote program is not registered */ + RPC_N2AXLATEFAILURE = 22, /* Name to addr translation failed */ + /* + * unspecified error + */ + RPC_FAILED=16, + RPC_INTR=18, + RPC_TLIERROR=20, + RPC_UDERROR=23, /* * asynchronous errors */ @@ -110,21 +110,21 @@ enum clnt_stat { struct rpc_err { int re_status; union { - int RE_errno; /* related system error */ - int RE_why; /* why the auth error occurred */ + int RE_errno; /* related system error */ + int RE_why; /* why the auth error occurred */ struct { - unsigned long low; /* lowest verion supported */ - unsigned long high; /* highest verion supported */ + unsigned long low; /* lowest verion supported */ + unsigned long high; /* highest verion supported */ } RE_vers; - struct { /* maybe meaningful if RPC_FAILED */ + struct { /* maybe meaningful if RPC_FAILED */ long s1; long s2; - } RE_lb; /* life boot & debugging only */ + } RE_lb; /* life boot & debugging only */ } ru; -#define re_errno ru.RE_errno -#define re_why ru.RE_why -#define re_vers ru.RE_vers -#define re_lb ru.RE_lb +#define re_errno ru.RE_errno +#define re_why ru.RE_why +#define re_vers ru.RE_vers +#define re_lb ru.RE_lb }; @@ -135,21 +135,21 @@ struct rpc_err { */ typedef struct CLIENT CLIENT; struct CLIENT { - AUTH *cl_auth; /* authenticator */ + AUTH *cl_auth; /* authenticator */ struct clnt_ops { enum clnt_stat (*cl_call) (CLIENT *, unsigned long, xdrproc_t, char*, xdrproc_t, - char*, struct timeval); - /* call remote procedure */ - void (*cl_abort) (void); /* abort a call */ + char*, struct timeval); + /* call remote procedure */ + void (*cl_abort) (void); /* abort a call */ void (*cl_geterr) (CLIENT *, struct rpc_err *); - /* get specific error code */ + /* get specific error code */ bool_t (*cl_freeres) (CLIENT *, xdrproc_t, char*); - /* frees results */ + /* frees results */ void (*cl_destroy) (CLIENT *); /* destroy this structure */ bool_t (*cl_control) (CLIENT *, int, char *); - /* the ioctl() of rpc */ + /* the ioctl() of rpc */ } *cl_ops; - char* cl_private; /* private stuff */ + char* cl_private; /* private stuff */ }; @@ -163,45 +163,45 @@ struct CLIENT { /* * enum clnt_stat * CLNT_CALL(rh, proc, xargs, argsp, xres, resp, timeout) - * CLIENT *rh; - * unsigned long proc; - * xdrproc_t xargs; - * char* argsp; - * xdrproc_t xres; - * char* resp; - * struct timeval timeout; + * CLIENT *rh; + * unsigned long proc; + * xdrproc_t xargs; + * char* argsp; + * xdrproc_t xres; + * char* resp; + * struct timeval timeout; */ -#define CLNT_CALL(rh, proc, xargs, argsp, xres, resp, secs) \ - ((*(rh)->cl_ops->cl_call)(rh, proc, xargs, argsp, xres, resp, secs)) -#define clnt_call(rh, proc, xargs, argsp, xres, resp, secs) \ - ((*(rh)->cl_ops->cl_call)(rh, proc, xargs, argsp, xres, resp, secs)) +#define CLNT_CALL(rh, proc, xargs, argsp, xres, resp, secs) \ + ((*(rh)->cl_ops->cl_call)(rh, proc, xargs, argsp, xres, resp, secs)) +#define clnt_call(rh, proc, xargs, argsp, xres, resp, secs) \ + ((*(rh)->cl_ops->cl_call)(rh, proc, xargs, argsp, xres, resp, secs)) /* * void * CLNT_ABORT(rh); - * CLIENT *rh; + * CLIENT *rh; */ -#define CLNT_ABORT(rh) ((*(rh)->cl_ops->cl_abort)(rh)) -#define clnt_abort(rh) ((*(rh)->cl_ops->cl_abort)(rh)) +#define CLNT_ABORT(rh) ((*(rh)->cl_ops->cl_abort)(rh)) +#define clnt_abort(rh) ((*(rh)->cl_ops->cl_abort)(rh)) /* * struct rpc_err * CLNT_GETERR(rh); - * CLIENT *rh; + * CLIENT *rh; */ -#define CLNT_GETERR(rh,errp) ((*(rh)->cl_ops->cl_geterr)(rh, errp)) -#define clnt_geterr(rh,errp) ((*(rh)->cl_ops->cl_geterr)(rh, errp)) +#define CLNT_GETERR(rh,errp) ((*(rh)->cl_ops->cl_geterr)(rh, errp)) +#define clnt_geterr(rh,errp) ((*(rh)->cl_ops->cl_geterr)(rh, errp)) /* * bool_t * CLNT_FREERES(rh, xres, resp); - * CLIENT *rh; - * xdrproc_t xres; - * char* resp; + * CLIENT *rh; + * xdrproc_t xres; + * char* resp; */ -#define CLNT_FREERES(rh,xres,resp) ((*(rh)->cl_ops->cl_freeres)(rh,xres,resp)) -#define clnt_freeres(rh,xres,resp) ((*(rh)->cl_ops->cl_freeres)(rh,xres,resp)) +#define CLNT_FREERES(rh,xres,resp) ((*(rh)->cl_ops->cl_freeres)(rh,xres,resp)) +#define clnt_freeres(rh,xres,resp) ((*(rh)->cl_ops->cl_freeres)(rh,xres,resp)) /* * bool_t @@ -210,8 +210,8 @@ struct CLIENT { * unsigned int request; * char *info; */ -#define CLNT_CONTROL(cl,rq,in) ((*(cl)->cl_ops->cl_control)(cl,rq,in)) -#define clnt_control(cl,rq,in) ((*(cl)->cl_ops->cl_control)(cl,rq,in)) +#define CLNT_CONTROL(cl,rq,in) ((*(cl)->cl_ops->cl_control)(cl,rq,in)) +#define clnt_control(cl,rq,in) ((*(cl)->cl_ops->cl_control)(cl,rq,in)) /* * control operations that apply to all transports @@ -239,16 +239,16 @@ struct CLIENT { /* * Connectionless only control operations */ -#define CLSET_RETRY_TIMEOUT 4 /* set retry timeout (timeval) */ -#define CLGET_RETRY_TIMEOUT 5 /* get retry timeout (timeval) */ +#define CLSET_RETRY_TIMEOUT 4 /* set retry timeout (timeval) */ +#define CLGET_RETRY_TIMEOUT 5 /* get retry timeout (timeval) */ /* * void * CLNT_DESTROY(rh); - * CLIENT *rh; + * CLIENT *rh; */ -#define CLNT_DESTROY(rh) ((*(rh)->cl_ops->cl_destroy)(rh)) -#define clnt_destroy(rh) ((*(rh)->cl_ops->cl_destroy)(rh)) +#define CLNT_DESTROY(rh) ((*(rh)->cl_ops->cl_destroy)(rh)) +#define clnt_destroy(rh) ((*(rh)->cl_ops->cl_destroy)(rh)) /* @@ -257,10 +257,10 @@ struct CLIENT { * and network administration. */ -#define RPCTEST_PROGRAM ((unsigned long)1) -#define RPCTEST_VERSION ((unsigned long)1) -#define RPCTEST_NULL_PROC ((unsigned long)2) -#define RPCTEST_NULL_BATCH_PROC ((unsigned long)3) +#define RPCTEST_PROGRAM ((unsigned long)1) +#define RPCTEST_VERSION ((unsigned long)1) +#define RPCTEST_NULL_PROC ((unsigned long)2) +#define RPCTEST_NULL_BATCH_PROC ((unsigned long)3) /* * By convention, procedure 0 takes null arguments and returns them @@ -279,51 +279,51 @@ struct CLIENT { * "unix" * CLIENT * * clnt_create(host, prog, vers, prot) - * char *host; -- hostname - * unsigned long prog; -- program number - * u_ong vers; -- version number - * char *prot; -- protocol + * char *host; -- hostname + * unsigned long prog; -- program number + * u_ong vers; -- version number + * char *prot; -- protocol */ extern CLIENT *clnt_create (const char *__host, const unsigned long __prog, - const unsigned long __vers, const char *__prot) + const unsigned long __vers, const char *__prot) ; /* * UDP based rpc. * CLIENT * * clntudp_create(raddr, program, version, wait, sockp) - * struct sockaddr_in *raddr; - * unsigned long program; - * unsigned long version; - * struct timeval wait_resend; - * int *sockp; + * struct sockaddr_in *raddr; + * unsigned long program; + * unsigned long version; + * struct timeval wait_resend; + * int *sockp; * * Same as above, but you specify max packet sizes. * CLIENT * * clntudp_bufcreate(raddr, program, version, wait, sockp, sendsz, recvsz) - * struct sockaddr_in *raddr; - * unsigned long program; - * unsigned long version; - * struct timeval wait_resend; - * int *sockp; - * unsigned int sendsz; - * unsigned int recvsz; + * struct sockaddr_in *raddr; + * unsigned long program; + * unsigned long version; + * struct timeval wait_resend; + * int *sockp; + * unsigned int sendsz; + * unsigned int recvsz; */ extern CLIENT *clntudp_create (struct sockaddr_in *__raddr, unsigned long __program, - unsigned long __version, struct timeval __wait_resend, - int *__sockp); + unsigned long __version, struct timeval __wait_resend, + int *__sockp); extern CLIENT *clntudp_bufcreate (struct sockaddr_in *__raddr, - unsigned long __program, unsigned long __version, - struct timeval __wait_resend, int *__sockp, - unsigned int __sendsz, unsigned int __recvsz); + unsigned long __program, unsigned long __version, + struct timeval __wait_resend, int *__sockp, + unsigned int __sendsz, unsigned int __recvsz); extern int callrpc (const char *__host, const unsigned long __prognum, - const unsigned long __versnum, const unsigned long __procnum, - const xdrproc_t __inproc, const char *__in, - const xdrproc_t __outproc, char *__out); + const unsigned long __versnum, const unsigned long __procnum, + const xdrproc_t __inproc, const char *__in, + const xdrproc_t __outproc, char *__out); -#define UDPMSGSIZE 8800 /* rpc imposed limit on udp msg size */ -#define RPCSMALLMSGSIZE 400 /* a more reasonable packet size */ +#define UDPMSGSIZE 8800 /* rpc imposed limit on udp msg size */ +#define RPCSMALLMSGSIZE 400 /* a more reasonable packet size */ void clnt_perror(CLIENT *rpch, const char *s); diff --git a/components/dfs/filesystems/nfs/rpc/clnt_generic.c b/components/dfs/filesystems/nfs/rpc/clnt_generic.c index bd241b5835..bbcd8011ef 100644 --- a/components/dfs/filesystems/nfs/rpc/clnt_generic.c +++ b/components/dfs/filesystems/nfs/rpc/clnt_generic.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/dfs/filesystems/nfs/rpc/clnt_udp.c b/components/dfs/filesystems/nfs/rpc/clnt_udp.c index 6b4f7bfb13..17933539da 100644 --- a/components/dfs/filesystems/nfs/rpc/clnt_udp.c +++ b/components/dfs/filesystems/nfs/rpc/clnt_udp.c @@ -1,12 +1,12 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes */ -/* @(#)clnt_udp.c 2.2 88/08/01 4.0 RPCSRC */ +/* @(#)clnt_udp.c 2.2 88/08/01 4.0 RPCSRC */ /* * Sun RPC is a product of Sun Microsystems, Inc. and is provided for * unrestricted use provided that this legend is included on all tape @@ -53,12 +53,12 @@ static char sccsid[] = "@(#)clnt_udp.c 1.39 87/08/11 Copyr 1984 Sun Micro"; * UDP bases client side rpc operations */ static enum clnt_stat clntudp_call(register CLIENT *cl, /* client handle */ - unsigned long proc, /* procedure number */ - xdrproc_t xargs, /* xdr routine for args */ - char* argsp, /* pointer to args */ - xdrproc_t xresults, /* xdr routine for results */ - char* resultsp, /* pointer to results */ - struct timeval utimeout); + unsigned long proc, /* procedure number */ + xdrproc_t xargs, /* xdr routine for args */ + char* argsp, /* pointer to args */ + xdrproc_t xresults, /* xdr routine for results */ + char* resultsp, /* pointer to results */ + struct timeval utimeout); static void clntudp_abort(void); static void clntudp_geterr(CLIENT *, struct rpc_err *); @@ -68,12 +68,12 @@ static void clntudp_destroy(CLIENT *); static struct clnt_ops udp_ops = { - clntudp_call, - clntudp_abort, - clntudp_geterr, - clntudp_freeres, - clntudp_destroy, - clntudp_control + clntudp_call, + clntudp_abort, + clntudp_geterr, + clntudp_freeres, + clntudp_destroy, + clntudp_control }; /* @@ -81,19 +81,19 @@ static struct clnt_ops udp_ops = */ struct cu_data { - int cu_sock; - bool_t cu_closeit; - struct sockaddr_in cu_raddr; - int cu_rlen; - struct timeval cu_wait; - struct timeval cu_total; - struct rpc_err cu_error; - XDR cu_outxdrs; - unsigned int cu_xdrpos; - unsigned int cu_sendsz; - char *cu_outbuf; - unsigned int cu_recvsz; - char cu_inbuf[1]; + int cu_sock; + bool_t cu_closeit; + struct sockaddr_in cu_raddr; + int cu_rlen; + struct timeval cu_wait; + struct timeval cu_total; + struct rpc_err cu_error; + XDR cu_outxdrs; + unsigned int cu_xdrpos; + unsigned int cu_sendsz; + char *cu_outbuf; + unsigned int cu_recvsz; + char cu_inbuf[1]; }; /* @@ -112,241 +112,241 @@ struct cu_data * sendsz and recvsz are the maximum allowable packet sizes that can be * sent and received. */ -CLIENT *clntudp_bufcreate(struct sockaddr_in *raddr, - unsigned long program, - unsigned long version, - struct timeval wait, - int *sockp, - unsigned int sendsz, - unsigned int recvsz) +CLIENT *clntudp_bufcreate(struct sockaddr_in *raddr, + unsigned long program, + unsigned long version, + struct timeval wait, + int *sockp, + unsigned int sendsz, + unsigned int recvsz) { - CLIENT *cl; - register struct cu_data *cu = NULL; - struct rpc_msg call_msg; - static int xid_count = 0; - - cl = (CLIENT *) rt_malloc (sizeof(CLIENT)); - if (cl == NULL) - { - rt_kprintf("clntudp_create: out of memory\n"); - goto fooy; - } - sendsz = ((sendsz + 3) / 4) * 4; - recvsz = ((recvsz + 3) / 4) * 4; - cu = (struct cu_data *) rt_malloc (sizeof(*cu) + sendsz + recvsz); - if (cu == NULL) - { - rt_kprintf("clntudp_create: out of memory\n"); - goto fooy; - } - cu->cu_outbuf = &cu->cu_inbuf[recvsz]; - - if (raddr->sin_port == 0) { - unsigned short port; - extern unsigned short pmap_getport(struct sockaddr_in *address, - unsigned long program, - unsigned long version, - unsigned int protocol); - - if ((port = - pmap_getport(raddr, program, version, IPPROTO_UDP)) == 0) { - goto fooy; - } - raddr->sin_port = htons(port); - } - - cl->cl_ops = &udp_ops; - cl->cl_private = (char*) cu; - cu->cu_raddr = *raddr; - cu->cu_rlen = sizeof(cu->cu_raddr); - cu->cu_wait = wait; - cu->cu_total.tv_sec = -1; - cu->cu_total.tv_usec = -1; - cu->cu_sendsz = sendsz; - cu->cu_recvsz = recvsz; - call_msg.rm_xid = ((unsigned long)rt_thread_self()) ^ ((unsigned long)rt_tick_get()) ^ (xid_count++); - call_msg.rm_direction = CALL; - call_msg.rm_call.cb_rpcvers = RPC_MSG_VERSION; - call_msg.rm_call.cb_prog = program; - call_msg.rm_call.cb_vers = version; - xdrmem_create(&(cu->cu_outxdrs), cu->cu_outbuf, sendsz, XDR_ENCODE); - if (!xdr_callhdr(&(cu->cu_outxdrs), &call_msg)) - { - goto fooy; - } - cu->cu_xdrpos = XDR_GETPOS(&(cu->cu_outxdrs)); - if (*sockp < 0) - { - *sockp = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP); - if (*sockp < 0) - { - rt_kprintf("create socket error\n"); - goto fooy; - } - cu->cu_closeit = TRUE; - } - else - { - cu->cu_closeit = FALSE; - } - cu->cu_sock = *sockp; - cl->cl_auth = authnone_create(); - return (cl); + CLIENT *cl; + register struct cu_data *cu = NULL; + struct rpc_msg call_msg; + static int xid_count = 0; + + cl = (CLIENT *) rt_malloc (sizeof(CLIENT)); + if (cl == NULL) + { + rt_kprintf("clntudp_create: out of memory\n"); + goto fooy; + } + sendsz = ((sendsz + 3) / 4) * 4; + recvsz = ((recvsz + 3) / 4) * 4; + cu = (struct cu_data *) rt_malloc (sizeof(*cu) + sendsz + recvsz); + if (cu == NULL) + { + rt_kprintf("clntudp_create: out of memory\n"); + goto fooy; + } + cu->cu_outbuf = &cu->cu_inbuf[recvsz]; + + if (raddr->sin_port == 0) { + unsigned short port; + extern unsigned short pmap_getport(struct sockaddr_in *address, + unsigned long program, + unsigned long version, + unsigned int protocol); + + if ((port = + pmap_getport(raddr, program, version, IPPROTO_UDP)) == 0) { + goto fooy; + } + raddr->sin_port = htons(port); + } + + cl->cl_ops = &udp_ops; + cl->cl_private = (char*) cu; + cu->cu_raddr = *raddr; + cu->cu_rlen = sizeof(cu->cu_raddr); + cu->cu_wait = wait; + cu->cu_total.tv_sec = -1; + cu->cu_total.tv_usec = -1; + cu->cu_sendsz = sendsz; + cu->cu_recvsz = recvsz; + call_msg.rm_xid = ((unsigned long)rt_thread_self()) ^ ((unsigned long)rt_tick_get()) ^ (xid_count++); + call_msg.rm_direction = CALL; + call_msg.rm_call.cb_rpcvers = RPC_MSG_VERSION; + call_msg.rm_call.cb_prog = program; + call_msg.rm_call.cb_vers = version; + xdrmem_create(&(cu->cu_outxdrs), cu->cu_outbuf, sendsz, XDR_ENCODE); + if (!xdr_callhdr(&(cu->cu_outxdrs), &call_msg)) + { + goto fooy; + } + cu->cu_xdrpos = XDR_GETPOS(&(cu->cu_outxdrs)); + if (*sockp < 0) + { + *sockp = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP); + if (*sockp < 0) + { + rt_kprintf("create socket error\n"); + goto fooy; + } + cu->cu_closeit = TRUE; + } + else + { + cu->cu_closeit = FALSE; + } + cu->cu_sock = *sockp; + cl->cl_auth = authnone_create(); + return (cl); fooy: - if (cu) rt_free(cu); - if (cl) rt_free(cl); + if (cu) rt_free(cu); + if (cl) rt_free(cl); - return ((CLIENT *) NULL); + return ((CLIENT *) NULL); } -CLIENT *clntudp_create(struct sockaddr_in *raddr, - unsigned long program, - unsigned long version, - struct timeval wait, - int *sockp) +CLIENT *clntudp_create(struct sockaddr_in *raddr, + unsigned long program, + unsigned long version, + struct timeval wait, + int *sockp) { - return (clntudp_bufcreate(raddr, program, version, wait, sockp, - UDPMSGSIZE, UDPMSGSIZE)); + return (clntudp_bufcreate(raddr, program, version, wait, sockp, + UDPMSGSIZE, UDPMSGSIZE)); } -static enum clnt_stat clntudp_call(CLIENT *cl, unsigned long proc, - xdrproc_t xargs, char* argsp, - xdrproc_t xresults, char* resultsp, - struct timeval utimeout) +static enum clnt_stat clntudp_call(CLIENT *cl, unsigned long proc, + xdrproc_t xargs, char* argsp, + xdrproc_t xresults, char* resultsp, + struct timeval utimeout) { - register struct cu_data *cu = (struct cu_data *) cl->cl_private; - register XDR *xdrs; - register int outlen; - register int inlen; - socklen_t fromlen; - - struct sockaddr_in from; - struct rpc_msg reply_msg; - XDR reply_xdrs; - bool_t ok; - int nrefreshes = 2; /* number of times to refresh cred */ + register struct cu_data *cu = (struct cu_data *) cl->cl_private; + register XDR *xdrs; + register int outlen; + register int inlen; + socklen_t fromlen; + + struct sockaddr_in from; + struct rpc_msg reply_msg; + XDR reply_xdrs; + bool_t ok; + int nrefreshes = 2; /* number of times to refresh cred */ call_again: - xdrs = &(cu->cu_outxdrs); - xdrs->x_op = XDR_ENCODE; - XDR_SETPOS(xdrs, cu->cu_xdrpos); + xdrs = &(cu->cu_outxdrs); + xdrs->x_op = XDR_ENCODE; + XDR_SETPOS(xdrs, cu->cu_xdrpos); - /* - * the transaction is the first thing in the out buffer - */ - (*(unsigned long *) (cu->cu_outbuf))++; + /* + * the transaction is the first thing in the out buffer + */ + (*(unsigned long *) (cu->cu_outbuf))++; - if ((!XDR_PUTLONG(xdrs, (long *) &proc)) || - (!AUTH_MARSHALL(cl->cl_auth, xdrs)) || (!(*xargs) (xdrs, argsp))) + if ((!XDR_PUTLONG(xdrs, (long *) &proc)) || + (!AUTH_MARSHALL(cl->cl_auth, xdrs)) || (!(*xargs) (xdrs, argsp))) { cu->cu_error.re_status = RPC_CANTENCODEARGS; - return RPC_CANTENCODEARGS; + return RPC_CANTENCODEARGS; } - outlen = (int) XDR_GETPOS(xdrs); + outlen = (int) XDR_GETPOS(xdrs); send_again: - if (sendto(cu->cu_sock, cu->cu_outbuf, outlen, 0, - (struct sockaddr *) &(cu->cu_raddr), cu->cu_rlen) - != outlen) - { - cu->cu_error.re_errno = errno; + if (sendto(cu->cu_sock, cu->cu_outbuf, outlen, 0, + (struct sockaddr *) &(cu->cu_raddr), cu->cu_rlen) + != outlen) + { + cu->cu_error.re_errno = errno; cu->cu_error.re_status = RPC_CANTSEND; - - return RPC_CANTSEND; - } - - /* - * sub-optimal code appears here because we have - * some clock time to spare while the packets are in flight. - * (We assume that this is actually only executed once.) - */ - reply_msg.acpted_rply.ar_verf = _null_auth; - reply_msg.acpted_rply.ar_results.where = resultsp; - reply_msg.acpted_rply.ar_results.proc = xresults; - - /* do recv */ - do - { - fromlen = sizeof(struct sockaddr); - - inlen = recvfrom(cu->cu_sock, cu->cu_inbuf, - (int) cu->cu_recvsz, 0, - (struct sockaddr *) &from, &fromlen); - }while (inlen < 0 && errno == EINTR); - - if (inlen < 4) - { - rt_kprintf("recv error, len %d\n", inlen); - cu->cu_error.re_errno = errno; - cu->cu_error.re_status = RPC_CANTRECV; - - return RPC_CANTRECV; - } - - /* see if reply transaction id matches sent id */ - if (*((uint32_t *) (cu->cu_inbuf)) != *((uint32_t *) (cu->cu_outbuf))) - goto send_again; - - /* we now assume we have the proper reply */ - - /* - * now decode and validate the response - */ - xdrmem_create(&reply_xdrs, cu->cu_inbuf, (unsigned int) inlen, XDR_DECODE); - ok = xdr_replymsg(&reply_xdrs, &reply_msg); - /* XDR_DESTROY(&reply_xdrs); save a few cycles on noop destroy */ - if (ok) - { - _seterr_reply(&reply_msg, &(cu->cu_error)); - if (cu->cu_error.re_status == RPC_SUCCESS) - { - if (!AUTH_VALIDATE(cl->cl_auth, - &reply_msg.acpted_rply.ar_verf)) - { - cu->cu_error.re_status = RPC_AUTHERROR; - cu->cu_error.re_why = AUTH_INVALIDRESP; - } - if (reply_msg.acpted_rply.ar_verf.oa_base != NULL) - { - extern bool_t xdr_opaque_auth(XDR *xdrs, struct opaque_auth *ap); - - xdrs->x_op = XDR_FREE; - (void) xdr_opaque_auth(xdrs, &(reply_msg.acpted_rply.ar_verf)); - } - } /* end successful completion */ - else - { - /* maybe our credentials need to be refreshed ... */ - if (nrefreshes > 0 && AUTH_REFRESH(cl->cl_auth)) - { - nrefreshes--; - goto call_again; - } - } /* end of unsuccessful completion */ - } /* end of valid reply message */ - else - { - cu->cu_error.re_status = RPC_CANTDECODERES; - } - - return (enum clnt_stat)(cu->cu_error.re_status); + + return RPC_CANTSEND; + } + + /* + * sub-optimal code appears here because we have + * some clock time to spare while the packets are in flight. + * (We assume that this is actually only executed once.) + */ + reply_msg.acpted_rply.ar_verf = _null_auth; + reply_msg.acpted_rply.ar_results.where = resultsp; + reply_msg.acpted_rply.ar_results.proc = xresults; + + /* do recv */ + do + { + fromlen = sizeof(struct sockaddr); + + inlen = recvfrom(cu->cu_sock, cu->cu_inbuf, + (int) cu->cu_recvsz, 0, + (struct sockaddr *) &from, &fromlen); + }while (inlen < 0 && errno == EINTR); + + if (inlen < 4) + { + rt_kprintf("recv error, len %d\n", inlen); + cu->cu_error.re_errno = errno; + cu->cu_error.re_status = RPC_CANTRECV; + + return RPC_CANTRECV; + } + + /* see if reply transaction id matches sent id */ + if (*((uint32_t *) (cu->cu_inbuf)) != *((uint32_t *) (cu->cu_outbuf))) + goto send_again; + + /* we now assume we have the proper reply */ + + /* + * now decode and validate the response + */ + xdrmem_create(&reply_xdrs, cu->cu_inbuf, (unsigned int) inlen, XDR_DECODE); + ok = xdr_replymsg(&reply_xdrs, &reply_msg); + /* XDR_DESTROY(&reply_xdrs); save a few cycles on noop destroy */ + if (ok) + { + _seterr_reply(&reply_msg, &(cu->cu_error)); + if (cu->cu_error.re_status == RPC_SUCCESS) + { + if (!AUTH_VALIDATE(cl->cl_auth, + &reply_msg.acpted_rply.ar_verf)) + { + cu->cu_error.re_status = RPC_AUTHERROR; + cu->cu_error.re_why = AUTH_INVALIDRESP; + } + if (reply_msg.acpted_rply.ar_verf.oa_base != NULL) + { + extern bool_t xdr_opaque_auth(XDR *xdrs, struct opaque_auth *ap); + + xdrs->x_op = XDR_FREE; + (void) xdr_opaque_auth(xdrs, &(reply_msg.acpted_rply.ar_verf)); + } + } /* end successful completion */ + else + { + /* maybe our credentials need to be refreshed ... */ + if (nrefreshes > 0 && AUTH_REFRESH(cl->cl_auth)) + { + nrefreshes--; + goto call_again; + } + } /* end of unsuccessful completion */ + } /* end of valid reply message */ + else + { + cu->cu_error.re_status = RPC_CANTDECODERES; + } + + return (enum clnt_stat)(cu->cu_error.re_status); } static void clntudp_geterr(CLIENT *cl, struct rpc_err *errp) { - register struct cu_data *cu = (struct cu_data *) cl->cl_private; + register struct cu_data *cu = (struct cu_data *) cl->cl_private; - *errp = cu->cu_error; + *errp = cu->cu_error; } static bool_t clntudp_freeres(CLIENT *cl, xdrproc_t xdr_res, char* res_ptr) { - register struct cu_data *cu = (struct cu_data *) cl->cl_private; - register XDR *xdrs = &(cu->cu_outxdrs); + register struct cu_data *cu = (struct cu_data *) cl->cl_private; + register XDR *xdrs = &(cu->cu_outxdrs); - xdrs->x_op = XDR_FREE; - return ((*xdr_res) (xdrs, res_ptr)); + xdrs->x_op = XDR_FREE; + return ((*xdr_res) (xdrs, res_ptr)); } static void clntudp_abort() @@ -355,50 +355,50 @@ static void clntudp_abort() static bool_t clntudp_control(CLIENT *cl, int request, char *info) { - register struct cu_data *cu = (struct cu_data *) cl->cl_private; - - switch (request) - { - case CLSET_TIMEOUT: - { - int mtimeout; - - cu->cu_total = *(struct timeval *) info; - mtimeout = ((cu->cu_total.tv_sec * 1000) + ((cu->cu_total.tv_usec + 500)/1000)); - - /* set socket option, note: lwip only support msecond timeout */ - setsockopt(cu->cu_sock, SOL_SOCKET, SO_RCVTIMEO, - &mtimeout, sizeof(mtimeout)); - } - break; - case CLGET_TIMEOUT: - *(struct timeval *) info = cu->cu_total; - break; - case CLSET_RETRY_TIMEOUT: - cu->cu_wait = *(struct timeval *) info; - break; - case CLGET_RETRY_TIMEOUT: - *(struct timeval *) info = cu->cu_wait; - break; - case CLGET_SERVER_ADDR: - *(struct sockaddr_in *) info = cu->cu_raddr; - break; - default: - return (FALSE); - } - return (TRUE); + register struct cu_data *cu = (struct cu_data *) cl->cl_private; + + switch (request) + { + case CLSET_TIMEOUT: + { + int mtimeout; + + cu->cu_total = *(struct timeval *) info; + mtimeout = ((cu->cu_total.tv_sec * 1000) + ((cu->cu_total.tv_usec + 500)/1000)); + + /* set socket option, note: lwip only support msecond timeout */ + setsockopt(cu->cu_sock, SOL_SOCKET, SO_RCVTIMEO, + &mtimeout, sizeof(mtimeout)); + } + break; + case CLGET_TIMEOUT: + *(struct timeval *) info = cu->cu_total; + break; + case CLSET_RETRY_TIMEOUT: + cu->cu_wait = *(struct timeval *) info; + break; + case CLGET_RETRY_TIMEOUT: + *(struct timeval *) info = cu->cu_wait; + break; + case CLGET_SERVER_ADDR: + *(struct sockaddr_in *) info = cu->cu_raddr; + break; + default: + return (FALSE); + } + return (TRUE); } static void clntudp_destroy(CLIENT *cl) { - register struct cu_data *cu = (struct cu_data *) cl->cl_private; + register struct cu_data *cu = (struct cu_data *) cl->cl_private; - if (cu->cu_closeit) - { - lwip_close(cu->cu_sock); - } + if (cu->cu_closeit) + { + lwip_close(cu->cu_sock); + } - XDR_DESTROY(&(cu->cu_outxdrs)); - rt_free(cu); - rt_free(cl); + XDR_DESTROY(&(cu->cu_outxdrs)); + rt_free(cu); + rt_free(cl); } diff --git a/components/dfs/filesystems/nfs/rpc/pmap.c b/components/dfs/filesystems/nfs/rpc/pmap.c index dc5a2ccb8d..afa2583d09 100644 --- a/components/dfs/filesystems/nfs/rpc/pmap.c +++ b/components/dfs/filesystems/nfs/rpc/pmap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,11 +16,11 @@ static struct timeval tottimeout = { 60, 0 }; bool_t xdr_pmap(XDR *xdrs, struct pmap *regs) { - if (xdr_u_long(xdrs, ®s->pm_prog) && - xdr_u_long(xdrs, ®s->pm_vers) && - xdr_u_long(xdrs, ®s->pm_prot)) - return (xdr_u_long(xdrs, ®s->pm_port)); - return (FALSE); + if (xdr_u_long(xdrs, ®s->pm_prog) && + xdr_u_long(xdrs, ®s->pm_vers) && + xdr_u_long(xdrs, ®s->pm_prot)) + return (xdr_u_long(xdrs, ®s->pm_port)); + return (FALSE); } /* @@ -30,33 +30,33 @@ bool_t xdr_pmap(XDR *xdrs, struct pmap *regs) */ unsigned short pmap_getport(struct sockaddr_in *address, unsigned long program, unsigned long version, unsigned int protocol) { - unsigned short port = 0; - int socket = -1; - register CLIENT *client = RT_NULL; - struct pmap parms; - - address->sin_port = htons((unsigned short)PMAPPORT); - if (protocol == IPPROTO_UDP) - client = clntudp_bufcreate(address, PMAPPROG, PMAPVERS, timeout, - &socket, RPCSMALLMSGSIZE, - RPCSMALLMSGSIZE); - - if (client != (CLIENT *) NULL) - { - parms.pm_prog = program; - parms.pm_vers = version; - parms.pm_prot = protocol; - parms.pm_port = 0; /* not needed or used */ - if (CLNT_CALL(client, PMAPPROC_GETPORT, (xdrproc_t)xdr_pmap, (char*)&parms, - (xdrproc_t)xdr_u_short, (char*)&port, tottimeout) != RPC_SUCCESS) - { - rt_kprintf("pmap failure\n"); - } - CLNT_DESTROY(client); - } - - (void) lwip_close(socket); - address->sin_port = 0; - - return (port); + unsigned short port = 0; + int socket = -1; + register CLIENT *client = RT_NULL; + struct pmap parms; + + address->sin_port = htons((unsigned short)PMAPPORT); + if (protocol == IPPROTO_UDP) + client = clntudp_bufcreate(address, PMAPPROG, PMAPVERS, timeout, + &socket, RPCSMALLMSGSIZE, + RPCSMALLMSGSIZE); + + if (client != (CLIENT *) NULL) + { + parms.pm_prog = program; + parms.pm_vers = version; + parms.pm_prot = protocol; + parms.pm_port = 0; /* not needed or used */ + if (CLNT_CALL(client, PMAPPROC_GETPORT, (xdrproc_t)xdr_pmap, (char*)&parms, + (xdrproc_t)xdr_u_short, (char*)&port, tottimeout) != RPC_SUCCESS) + { + rt_kprintf("pmap failure\n"); + } + CLNT_DESTROY(client); + } + + (void) lwip_close(socket); + address->sin_port = 0; + + return (port); } diff --git a/components/dfs/filesystems/nfs/rpc/pmap.h b/components/dfs/filesystems/nfs/rpc/pmap.h index 8ae706c0aa..3a0305a6b8 100644 --- a/components/dfs/filesystems/nfs/rpc/pmap.h +++ b/components/dfs/filesystems/nfs/rpc/pmap.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,51 +14,51 @@ /* The following procedures are supported by the protocol: * * PMAPPROC_NULL() returns () - * takes nothing, returns nothing + * takes nothing, returns nothing * * PMAPPROC_SET(struct pmap) returns (bool_t) - * TRUE is success, FALSE is failure. Registers the tuple - * [prog, vers, prot, port]. + * TRUE is success, FALSE is failure. Registers the tuple + * [prog, vers, prot, port]. * * PMAPPROC_UNSET(struct pmap) returns (bool_t) - * TRUE is success, FALSE is failure. Un-registers pair - * [prog, vers]. prot and port are ignored. + * TRUE is success, FALSE is failure. Un-registers pair + * [prog, vers]. prot and port are ignored. * * PMAPPROC_GETPORT(struct pmap) returns (long unsigned). - * 0 is failure. Otherwise returns the port number where the pair - * [prog, vers] is registered. It may lie! + * 0 is failure. Otherwise returns the port number where the pair + * [prog, vers] is registered. It may lie! * * PMAPPROC_DUMP() RETURNS (struct pmaplist *) * * PMAPPROC_CALLIT(unsigned, unsigned, unsigned, string<>) - * RETURNS (port, string<>); + * RETURNS (port, string<>); * usage: encapsulatedresults = PMAPPROC_CALLIT(prog, vers, proc, encapsulatedargs); - * Calls the procedure on the local machine. If it is not registered, - * this procedure is quite; ie it does not return error information!!! - * This procedure only is supported on rpc/udp and calls via - * rpc/udp. This routine only passes null authentication parameters. - * This file has no interface to xdr routines for PMAPPROC_CALLIT. + * Calls the procedure on the local machine. If it is not registered, + * this procedure is quite; ie it does not return error information!!! + * This procedure only is supported on rpc/udp and calls via + * rpc/udp. This routine only passes null authentication parameters. + * This file has no interface to xdr routines for PMAPPROC_CALLIT. * * The service supports remote procedure calls on udp/ip or tcp/ip socket 111. */ -#define PMAPPORT ((unsigned short)111) -#define PMAPPROG ((unsigned long)100000) -#define PMAPVERS ((unsigned long)2) -#define PMAPVERS_PROTO ((unsigned long)2) -#define PMAPVERS_ORIG ((unsigned long)1) -#define PMAPPROC_NULL ((unsigned long)0) -#define PMAPPROC_SET ((unsigned long)1) -#define PMAPPROC_UNSET ((unsigned long)2) -#define PMAPPROC_GETPORT ((unsigned long)3) -#define PMAPPROC_DUMP ((unsigned long)4) -#define PMAPPROC_CALLIT ((unsigned long)5) +#define PMAPPORT ((unsigned short)111) +#define PMAPPROG ((unsigned long)100000) +#define PMAPVERS ((unsigned long)2) +#define PMAPVERS_PROTO ((unsigned long)2) +#define PMAPVERS_ORIG ((unsigned long)1) +#define PMAPPROC_NULL ((unsigned long)0) +#define PMAPPROC_SET ((unsigned long)1) +#define PMAPPROC_UNSET ((unsigned long)2) +#define PMAPPROC_GETPORT ((unsigned long)3) +#define PMAPPROC_DUMP ((unsigned long)4) +#define PMAPPROC_CALLIT ((unsigned long)5) struct pmap { - long unsigned pm_prog; - long unsigned pm_vers; - long unsigned pm_prot; - long unsigned pm_port; + long unsigned pm_prog; + long unsigned pm_vers; + long unsigned pm_prot; + long unsigned pm_port; }; extern bool_t xdr_pmap (XDR *__xdrs, struct pmap *__regs); diff --git a/components/dfs/filesystems/nfs/rpc/rpc.h b/components/dfs/filesystems/nfs/rpc/rpc.h index 7256d336a1..12d2477ef6 100644 --- a/components/dfs/filesystems/nfs/rpc/rpc.h +++ b/components/dfs/filesystems/nfs/rpc/rpc.h @@ -1,12 +1,12 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes */ -/* @(#)rpc.h 2.3 88/08/10 4.0 RPCSRC; from 1.9 88/02/08 SMI */ +/* @(#)rpc.h 2.3 88/08/10 4.0 RPCSRC; from 1.9 88/02/08 SMI */ /* * Sun RPC is a product of Sun Microsystems, Inc. and is provided for * unrestricted use provided that this legend is included on all tape @@ -46,17 +46,17 @@ #ifndef _RPC_RPC_H #define _RPC_RPC_H 1 -#include /* some typedefs */ +#include /* some typedefs */ /* external data representation interfaces */ -#include /* generic (de)serializer */ +#include /* generic (de)serializer */ #include /* Client side (mostly) remote procedure call */ -#include /* generic rpc stuff */ +#include /* generic rpc stuff */ /* semi-private protocol headers */ -#include /* protocol for rpc messages */ +#include /* protocol for rpc messages */ #endif diff --git a/components/dfs/filesystems/nfs/rpc/rpc_msg.h b/components/dfs/filesystems/nfs/rpc/rpc_msg.h index a21ca1ce7d..358c3f7903 100644 --- a/components/dfs/filesystems/nfs/rpc/rpc_msg.h +++ b/components/dfs/filesystems/nfs/rpc/rpc_msg.h @@ -1,12 +1,12 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes */ -/* @(#)rpc_msg.h 2.1 88/07/29 4.0 RPCSRC */ +/* @(#)rpc_msg.h 2.1 88/07/29 4.0 RPCSRC */ /* * Sun RPC is a product of Sun Microsystems, Inc. and is provided for * unrestricted use provided that this legend is included on all tape @@ -50,8 +50,8 @@ * Copyright (C) 1984, Sun Microsystems, Inc. */ -#define RPC_MSG_VERSION ((unsigned long) 2) -#define RPC_SERVICE_PORT ((unsigned short) 2048) +#define RPC_MSG_VERSION ((unsigned long) 2) +#define RPC_SERVICE_PORT ((unsigned short) 2048) /* * Bottom up definition of an rpc message. @@ -60,27 +60,27 @@ */ enum msg_type { - CALL=0, - REPLY=1 + CALL=0, + REPLY=1 }; enum reply_stat { - MSG_ACCEPTED=0, - MSG_DENIED=1 + MSG_ACCEPTED=0, + MSG_DENIED=1 }; enum accept_stat { - SUCCESS=0, - PROG_UNAVAIL=1, - PROG_MISMATCH=2, - PROC_UNAVAIL=3, - GARBAGE_ARGS=4, - SYSTEM_ERR=5 + SUCCESS=0, + PROG_UNAVAIL=1, + PROG_MISMATCH=2, + PROC_UNAVAIL=3, + GARBAGE_ARGS=4, + SYSTEM_ERR=5 }; enum reject_stat { - RPC_MISMATCH=0, - AUTH_ERROR=1 + RPC_MISMATCH=0, + AUTH_ERROR=1 }; /* @@ -93,111 +93,111 @@ enum reject_stat { * accepted. */ struct accepted_reply { - struct opaque_auth ar_verf; - int ar_stat; - union { - struct { - unsigned long low; - unsigned long high; - } AR_versions; - struct { - char* where; - xdrproc_t proc; - } AR_results; - /* and many other null cases */ - } ru; -#define ar_results ru.AR_results -#define ar_vers ru.AR_versions + struct opaque_auth ar_verf; + int ar_stat; + union { + struct { + unsigned long low; + unsigned long high; + } AR_versions; + struct { + char* where; + xdrproc_t proc; + } AR_results; + /* and many other null cases */ + } ru; +#define ar_results ru.AR_results +#define ar_vers ru.AR_versions }; /* * Reply to an rpc request that was rejected by the server. */ struct rejected_reply { - int rj_stat; - union { - struct { - unsigned long low; - unsigned long high; - } RJ_versions; - int RJ_why; /* why authentication did not work */ - } ru; -#define rj_vers ru.RJ_versions -#define rj_why ru.RJ_why + int rj_stat; + union { + struct { + unsigned long low; + unsigned long high; + } RJ_versions; + int RJ_why; /* why authentication did not work */ + } ru; +#define rj_vers ru.RJ_versions +#define rj_why ru.RJ_why }; /* * Body of a reply to an rpc request. */ struct reply_body { - int rp_stat; - union { - struct accepted_reply RP_ar; - struct rejected_reply RP_dr; - } ru; -#define rp_acpt ru.RP_ar -#define rp_rjct ru.RP_dr + int rp_stat; + union { + struct accepted_reply RP_ar; + struct rejected_reply RP_dr; + } ru; +#define rp_acpt ru.RP_ar +#define rp_rjct ru.RP_dr }; /* * Body of an rpc request call. */ struct call_body { - unsigned long cb_rpcvers; /* must be equal to two */ - unsigned long cb_prog; - unsigned long cb_vers; - unsigned long cb_proc; - struct opaque_auth cb_cred; - struct opaque_auth cb_verf; /* protocol specific - provided by client */ + unsigned long cb_rpcvers; /* must be equal to two */ + unsigned long cb_prog; + unsigned long cb_vers; + unsigned long cb_proc; + struct opaque_auth cb_cred; + struct opaque_auth cb_verf; /* protocol specific - provided by client */ }; /* * The rpc message */ struct rpc_msg { - unsigned long rm_xid; - int rm_direction; - union { - struct call_body RM_cmb; - struct reply_body RM_rmb; - } ru; -#define rm_call ru.RM_cmb -#define rm_reply ru.RM_rmb + unsigned long rm_xid; + int rm_direction; + union { + struct call_body RM_cmb; + struct reply_body RM_rmb; + } ru; +#define rm_call ru.RM_cmb +#define rm_reply ru.RM_rmb }; -#define acpted_rply ru.RM_rmb.ru.RP_ar -#define rjcted_rply ru.RM_rmb.ru.RP_dr +#define acpted_rply ru.RM_rmb.ru.RP_ar +#define rjcted_rply ru.RM_rmb.ru.RP_dr /* * XDR routine to handle a rpc message. * xdr_callmsg(xdrs, cmsg) - * XDR *xdrs; - * struct rpc_msg *cmsg; + * XDR *xdrs; + * struct rpc_msg *cmsg; */ -extern bool_t xdr_callmsg (XDR *__xdrs, struct rpc_msg *__cmsg); +extern bool_t xdr_callmsg (XDR *__xdrs, struct rpc_msg *__cmsg); /* * XDR routine to pre-serialize the static part of a rpc message. * xdr_callhdr(xdrs, cmsg) - * XDR *xdrs; - * struct rpc_msg *cmsg; + * XDR *xdrs; + * struct rpc_msg *cmsg; */ -extern bool_t xdr_callhdr (XDR *__xdrs, struct rpc_msg *__cmsg); +extern bool_t xdr_callhdr (XDR *__xdrs, struct rpc_msg *__cmsg); /* * XDR routine to handle a rpc reply. * xdr_replymsg(xdrs, rmsg) - * XDR *xdrs; - * struct rpc_msg *rmsg; + * XDR *xdrs; + * struct rpc_msg *rmsg; */ -extern bool_t xdr_replymsg (XDR *__xdrs, struct rpc_msg *__rmsg); +extern bool_t xdr_replymsg (XDR *__xdrs, struct rpc_msg *__rmsg); /* * Fills in the error part of a reply message. * _seterr_reply(msg, error) - * struct rpc_msg *msg; - * struct rpc_err *error; + * struct rpc_msg *msg; + * struct rpc_err *error; */ -extern void _seterr_reply (struct rpc_msg *__msg, struct rpc_err *__error); +extern void _seterr_reply (struct rpc_msg *__msg, struct rpc_err *__error); #endif /* rpc/rpc_msg.h */ diff --git a/components/dfs/filesystems/nfs/rpc/rpc_prot.c b/components/dfs/filesystems/nfs/rpc/rpc_prot.c index 427d7a11e4..61cb6cbc85 100644 --- a/components/dfs/filesystems/nfs/rpc/rpc_prot.c +++ b/components/dfs/filesystems/nfs/rpc/rpc_prot.c @@ -1,12 +1,12 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes */ -/* @(#)rpc_prot.c 2.3 88/08/07 4.0 RPCSRC */ +/* @(#)rpc_prot.c 2.3 88/08/07 4.0 RPCSRC */ /* * Sun RPC is a product of Sun Microsystems, Inc. and is provided for * unrestricted use provided that this legend is included on all tape @@ -14,23 +14,23 @@ * may copy or modify Sun RPC without charge, but are not authorized * to license or distribute it to anyone else except as part of a product or * program developed by the user. - * + * * SUN RPC IS PROVIDED AS IS WITH NO WARRANTIES OF ANY KIND INCLUDING THE * WARRANTIES OF DESIGN, MERCHANTIBILITY AND FITNESS FOR A PARTICULAR * PURPOSE, OR ARISING FROM A COURSE OF DEALING, USAGE OR TRADE PRACTICE. - * + * * Sun RPC is provided with no support and without any obligation on the * part of Sun Microsystems, Inc. to assist in its use, correction, * modification or enhancement. - * + * * SUN MICROSYSTEMS, INC. SHALL HAVE NO LIABILITY WITH RESPECT TO THE * INFRINGEMENT OF COPYRIGHTS, TRADE SECRETS OR ANY PATENTS BY SUN RPC * OR ANY PART THEREOF. - * + * * In no event will Sun Microsystems, Inc. be liable for any lost revenue * or profits or other special, indirect and consequential damages, even if * Sun has been advised of the possibility of such damages. - * + * * Sun Microsystems, Inc. * 2550 Garcia Avenue * Mountain View, California 94043 @@ -63,10 +63,10 @@ static char sccsid[] = "@(#)rpc_prot.c 1.36 87/08/11 Copyr 1984 Sun Micro"; bool_t xdr_opaque_auth(XDR *xdrs, struct opaque_auth *ap) { - if (xdr_enum(xdrs, &(ap->oa_flavor))) - return (xdr_bytes(xdrs, &ap->oa_base, - &ap->oa_length, MAX_AUTH_BYTES)); - return (FALSE); + if (xdr_enum(xdrs, &(ap->oa_flavor))) + return (xdr_bytes(xdrs, &ap->oa_base, + &ap->oa_length, MAX_AUTH_BYTES)); + return (FALSE); } /* @@ -74,7 +74,7 @@ bool_t xdr_opaque_auth(XDR *xdrs, struct opaque_auth *ap) */ bool_t xdr_des_block(XDR *xdrs, des_block *blkp) { - return (xdr_opaque(xdrs, (char*) blkp, sizeof(des_block))); + return (xdr_opaque(xdrs, (char*) blkp, sizeof(des_block))); } /* * * * * * * * * * * * * * XDR RPC MESSAGE * * * * * * * * * * * * * * * */ @@ -85,22 +85,22 @@ bool_t xdr_des_block(XDR *xdrs, des_block *blkp) static bool_t xdr_accepted_reply(XDR *xdrs, struct accepted_reply *ar) { - /* personalized union, rather than calling xdr_union */ - if (!xdr_opaque_auth(xdrs, &(ar->ar_verf))) - return (FALSE); - if (!xdr_enum(xdrs, (enum_t *) & (ar->ar_stat))) - return (FALSE); - switch (ar->ar_stat) { - - case SUCCESS: - return ((*(ar->ar_results.proc)) (xdrs, ar->ar_results.where)); - - case PROG_MISMATCH: - if (!xdr_u_long(xdrs, &(ar->ar_vers.low))) - return (FALSE); - return (xdr_u_long(xdrs, &(ar->ar_vers.high))); - } - return (TRUE); /* TRUE => open ended set of problems */ + /* personalized union, rather than calling xdr_union */ + if (!xdr_opaque_auth(xdrs, &(ar->ar_verf))) + return (FALSE); + if (!xdr_enum(xdrs, (enum_t *) & (ar->ar_stat))) + return (FALSE); + switch (ar->ar_stat) { + + case SUCCESS: + return ((*(ar->ar_results.proc)) (xdrs, ar->ar_results.where)); + + case PROG_MISMATCH: + if (!xdr_u_long(xdrs, &(ar->ar_vers.low))) + return (FALSE); + return (xdr_u_long(xdrs, &(ar->ar_vers.high))); + } + return (TRUE); /* TRUE => open ended set of problems */ } /* @@ -109,26 +109,26 @@ static bool_t xdr_accepted_reply(XDR *xdrs, struct accepted_reply *ar) static bool_t xdr_rejected_reply(XDR *xdrs, struct rejected_reply *rr) { - /* personalized union, rather than calling xdr_union */ - if (!xdr_enum(xdrs, (enum_t *) & (rr->rj_stat))) - return (FALSE); - switch (rr->rj_stat) { + /* personalized union, rather than calling xdr_union */ + if (!xdr_enum(xdrs, (enum_t *) & (rr->rj_stat))) + return (FALSE); + switch (rr->rj_stat) { - case RPC_MISMATCH: - if (!xdr_u_long(xdrs, &(rr->rj_vers.low))) - return (FALSE); - return (xdr_u_long(xdrs, &(rr->rj_vers.high))); + case RPC_MISMATCH: + if (!xdr_u_long(xdrs, &(rr->rj_vers.low))) + return (FALSE); + return (xdr_u_long(xdrs, &(rr->rj_vers.high))); - case AUTH_ERROR: - return (xdr_enum(xdrs, (enum_t *) & (rr->rj_why))); - } - return (FALSE); + case AUTH_ERROR: + return (xdr_enum(xdrs, (enum_t *) & (rr->rj_why))); + } + return (FALSE); } static struct xdr_discrim reply_dscrm[3] = { - {(int) MSG_ACCEPTED, (xdrproc_t)xdr_accepted_reply}, - {(int) MSG_DENIED, (xdrproc_t)xdr_rejected_reply}, - {__dontcare__, NULL_xdrproc_t} + {(int) MSG_ACCEPTED, (xdrproc_t)xdr_accepted_reply}, + {(int) MSG_DENIED, (xdrproc_t)xdr_rejected_reply}, + {__dontcare__, NULL_xdrproc_t} }; /* @@ -136,13 +136,13 @@ static struct xdr_discrim reply_dscrm[3] = { */ bool_t xdr_replymsg(XDR *xdrs, struct rpc_msg *rmsg) { - if (xdr_u_long(xdrs, &(rmsg->rm_xid)) && - xdr_enum(xdrs, (enum_t *) & (rmsg->rm_direction)) && - (rmsg->rm_direction == REPLY)) - return (xdr_union(xdrs, (enum_t *) & (rmsg->rm_reply.rp_stat), - (char*) & (rmsg->rm_reply.ru), reply_dscrm, - NULL_xdrproc_t)); - return (FALSE); + if (xdr_u_long(xdrs, &(rmsg->rm_xid)) && + xdr_enum(xdrs, (enum_t *) & (rmsg->rm_direction)) && + (rmsg->rm_direction == REPLY)) + return (xdr_union(xdrs, (enum_t *) & (rmsg->rm_reply.rp_stat), + (char*) & (rmsg->rm_reply.ru), reply_dscrm, + NULL_xdrproc_t)); + return (FALSE); } @@ -154,16 +154,16 @@ bool_t xdr_replymsg(XDR *xdrs, struct rpc_msg *rmsg) bool_t xdr_callhdr(XDR *xdrs, struct rpc_msg *cmsg) { - cmsg->rm_direction = CALL; - cmsg->rm_call.cb_rpcvers = RPC_MSG_VERSION; - if ( - (xdrs->x_op == XDR_ENCODE) && - xdr_u_long(xdrs, &(cmsg->rm_xid)) && - xdr_enum(xdrs, (enum_t *) & (cmsg->rm_direction)) && - xdr_u_long(xdrs, &(cmsg->rm_call.cb_rpcvers)) && - xdr_u_long(xdrs, &(cmsg->rm_call.cb_prog))) - return (xdr_u_long(xdrs, &(cmsg->rm_call.cb_vers))); - return (FALSE); + cmsg->rm_direction = CALL; + cmsg->rm_call.cb_rpcvers = RPC_MSG_VERSION; + if ( + (xdrs->x_op == XDR_ENCODE) && + xdr_u_long(xdrs, &(cmsg->rm_xid)) && + xdr_enum(xdrs, (enum_t *) & (cmsg->rm_direction)) && + xdr_u_long(xdrs, &(cmsg->rm_call.cb_rpcvers)) && + xdr_u_long(xdrs, &(cmsg->rm_call.cb_prog))) + return (xdr_u_long(xdrs, &(cmsg->rm_call.cb_vers))); + return (FALSE); } /* ************************** Client utility routine ************* */ @@ -171,55 +171,55 @@ bool_t xdr_callhdr(XDR *xdrs, struct rpc_msg *cmsg) static void accepted(enum accept_stat acpt_stat, struct rpc_err *error) { - switch (acpt_stat) { + switch (acpt_stat) { - case PROG_UNAVAIL: - error->re_status = RPC_PROGUNAVAIL; - return; + case PROG_UNAVAIL: + error->re_status = RPC_PROGUNAVAIL; + return; - case PROG_MISMATCH: - error->re_status = RPC_PROGVERSMISMATCH; - return; + case PROG_MISMATCH: + error->re_status = RPC_PROGVERSMISMATCH; + return; - case PROC_UNAVAIL: - error->re_status = RPC_PROCUNAVAIL; - return; + case PROC_UNAVAIL: + error->re_status = RPC_PROCUNAVAIL; + return; - case GARBAGE_ARGS: - error->re_status = RPC_CANTDECODEARGS; - return; + case GARBAGE_ARGS: + error->re_status = RPC_CANTDECODEARGS; + return; - case SYSTEM_ERR: - error->re_status = RPC_SYSTEMERROR; - return; + case SYSTEM_ERR: + error->re_status = RPC_SYSTEMERROR; + return; - case SUCCESS: - error->re_status = RPC_SUCCESS; - return; - } - /* something's wrong, but we don't know what ... */ - error->re_status = RPC_FAILED; - error->re_lb.s1 = (long) MSG_ACCEPTED; - error->re_lb.s2 = (long) acpt_stat; + case SUCCESS: + error->re_status = RPC_SUCCESS; + return; + } + /* something's wrong, but we don't know what ... */ + error->re_status = RPC_FAILED; + error->re_lb.s1 = (long) MSG_ACCEPTED; + error->re_lb.s2 = (long) acpt_stat; } static void rejected(enum reject_stat rjct_stat, struct rpc_err *error) { - switch (rjct_stat) { + switch (rjct_stat) { - case RPC_VERSMISMATCH: - error->re_status = RPC_VERSMISMATCH; - return; + case RPC_VERSMISMATCH: + error->re_status = RPC_VERSMISMATCH; + return; - case AUTH_ERROR: - error->re_status = RPC_AUTHERROR; - return; - } - /* something's wrong, but we don't know what ... */ - error->re_status = RPC_FAILED; - error->re_lb.s1 = (long) MSG_DENIED; - error->re_lb.s2 = (long) rjct_stat; + case AUTH_ERROR: + error->re_status = RPC_AUTHERROR; + return; + } + /* something's wrong, but we don't know what ... */ + error->re_status = RPC_FAILED; + error->re_lb.s1 = (long) MSG_DENIED; + error->re_lb.s2 = (long) rjct_stat; } /* @@ -228,40 +228,40 @@ static void rejected(enum reject_stat rjct_stat, struct rpc_err *error) void _seterr_reply(struct rpc_msg *msg, struct rpc_err *error) { - /* optimized for normal, SUCCESSful case */ - switch (msg->rm_reply.rp_stat) { - - case MSG_ACCEPTED: - if (msg->acpted_rply.ar_stat == SUCCESS) { - error->re_status = RPC_SUCCESS; - return; - }; - accepted((enum accept_stat)msg->acpted_rply.ar_stat, error); - break; - - case MSG_DENIED: - rejected((enum reject_stat)msg->rjcted_rply.rj_stat, error); - break; - - default: - error->re_status = RPC_FAILED; - error->re_lb.s1 = (long) (msg->rm_reply.rp_stat); - break; - } - switch (error->re_status) { - - case RPC_VERSMISMATCH: - error->re_vers.low = msg->rjcted_rply.rj_vers.low; - error->re_vers.high = msg->rjcted_rply.rj_vers.high; - break; - - case RPC_AUTHERROR: - error->re_why = msg->rjcted_rply.rj_why; - break; - - case RPC_PROGVERSMISMATCH: - error->re_vers.low = msg->acpted_rply.ar_vers.low; - error->re_vers.high = msg->acpted_rply.ar_vers.high; - break; - } + /* optimized for normal, SUCCESSful case */ + switch (msg->rm_reply.rp_stat) { + + case MSG_ACCEPTED: + if (msg->acpted_rply.ar_stat == SUCCESS) { + error->re_status = RPC_SUCCESS; + return; + }; + accepted((enum accept_stat)msg->acpted_rply.ar_stat, error); + break; + + case MSG_DENIED: + rejected((enum reject_stat)msg->rjcted_rply.rj_stat, error); + break; + + default: + error->re_status = RPC_FAILED; + error->re_lb.s1 = (long) (msg->rm_reply.rp_stat); + break; + } + switch (error->re_status) { + + case RPC_VERSMISMATCH: + error->re_vers.low = msg->rjcted_rply.rj_vers.low; + error->re_vers.high = msg->rjcted_rply.rj_vers.high; + break; + + case RPC_AUTHERROR: + error->re_why = msg->rjcted_rply.rj_why; + break; + + case RPC_PROGVERSMISMATCH: + error->re_vers.low = msg->acpted_rply.ar_vers.low; + error->re_vers.high = msg->acpted_rply.ar_vers.high; + break; + } } diff --git a/components/dfs/filesystems/nfs/rpc/types.h b/components/dfs/filesystems/nfs/rpc/types.h index 254fcd339c..4e50c53842 100644 --- a/components/dfs/filesystems/nfs/rpc/types.h +++ b/components/dfs/filesystems/nfs/rpc/types.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/dfs/filesystems/nfs/rpc/xdr.c b/components/dfs/filesystems/nfs/rpc/xdr.c index a6b1b67afb..fa3b12ef00 100644 --- a/components/dfs/filesystems/nfs/rpc/xdr.c +++ b/components/dfs/filesystems/nfs/rpc/xdr.c @@ -1,12 +1,12 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes */ -/* @(#)xdr.c 2.1 88/07/29 4.0 RPCSRC */ +/* @(#)xdr.c 2.1 88/07/29 4.0 RPCSRC */ /* * Sun RPC is a product of Sun Microsystems, Inc. and is provided for * unrestricted use provided that this legend is included on all tape @@ -14,23 +14,23 @@ * may copy or modify Sun RPC without charge, but are not authorized * to license or distribute it to anyone else except as part of a product or * program developed by the user. - * + * * SUN RPC IS PROVIDED AS IS WITH NO WARRANTIES OF ANY KIND INCLUDING THE * WARRANTIES OF DESIGN, MERCHANTIBILITY AND FITNESS FOR A PARTICULAR * PURPOSE, OR ARISING FROM A COURSE OF DEALING, USAGE OR TRADE PRACTICE. - * + * * Sun RPC is provided with no support and without any obligation on the * part of Sun Microsystems, Inc. to assist in its use, correction, * modification or enhancement. - * + * * SUN MICROSYSTEMS, INC. SHALL HAVE NO LIABILITY WITH RESPECT TO THE * INFRINGEMENT OF COPYRIGHTS, TRADE SECRETS OR ANY PATENTS BY SUN RPC * OR ANY PART THEREOF. - * + * * In no event will Sun Microsystems, Inc. be liable for any lost revenue * or profits or other special, indirect and consequential damages, even if * Sun has been advised of the possibility of such damages. - * + * * Sun Microsystems, Inc. * 2550 Garcia Avenue * Mountain View, California 94043 @@ -58,9 +58,9 @@ static char sccsid[] = "@(#)xdr.c 1.35 87/08/12"; /* * constants specific to the xdr "protocol" */ -#define XDR_FALSE ((long) 0) -#define XDR_TRUE ((long) 1) -#define LASTUNSIGNED ((unsigned int) 0-1) +#define XDR_FALSE ((long) 0) +#define XDR_TRUE ((long) 1) +#define LASTUNSIGNED ((unsigned int) 0-1) /* * for unit alignment @@ -73,21 +73,21 @@ static char xdr_zero[BYTES_PER_XDR_UNIT] = { 0, 0, 0, 0 }; */ void xdr_free(xdrproc_t proc, char* objp) { - XDR x; + XDR x; - x.x_op = XDR_FREE; - (*proc) (&x, objp); + x.x_op = XDR_FREE; + (*proc) (&x, objp); } /* * XDR nothing */ bool_t xdr_void( /* xdrs, addr */ ) - /* XDR *xdrs; */ - /* char* addr; */ + /* XDR *xdrs; */ + /* char* addr; */ { - return (TRUE); + return (TRUE); } /* @@ -95,25 +95,25 @@ bool_t xdr_void( /* xdrs, addr */ ) */ bool_t xdr_int(XDR* xdrs, int* ip) { - if (sizeof(int) == sizeof(long)) { - return (xdr_long(xdrs, (long *) ip)); - } else if (sizeof(int) < sizeof(long)) { - long l; - switch (xdrs->x_op) { - case XDR_ENCODE: - l = (long) *ip; - return XDR_PUTLONG(xdrs, &l); - case XDR_DECODE: - if (!XDR_GETLONG(xdrs, &l)) - return FALSE; - *ip = (int) l; - case XDR_FREE: - return TRUE; - } - return FALSE; - } else { - return (xdr_short(xdrs, (short *) ip)); - } + if (sizeof(int) == sizeof(long)) { + return (xdr_long(xdrs, (long *) ip)); + } else if (sizeof(int) < sizeof(long)) { + long l; + switch (xdrs->x_op) { + case XDR_ENCODE: + l = (long) *ip; + return XDR_PUTLONG(xdrs, &l); + case XDR_DECODE: + if (!XDR_GETLONG(xdrs, &l)) + return FALSE; + *ip = (int) l; + case XDR_FREE: + return TRUE; + } + return FALSE; + } else { + return (xdr_short(xdrs, (short *) ip)); + } } /* @@ -121,25 +121,25 @@ bool_t xdr_int(XDR* xdrs, int* ip) */ bool_t xdr_u_int(XDR* xdrs, unsigned int* up) { - if (sizeof(unsigned int) == sizeof(unsigned long)) { - return (xdr_u_long(xdrs, (unsigned long *) up)); - } else if (sizeof(unsigned int) < sizeof(unsigned long)) { - unsigned long l; - switch (xdrs->x_op) { - case XDR_ENCODE: - l = (unsigned long) *up; - return XDR_PUTLONG(xdrs, (long*)&l); - case XDR_DECODE: - if (!XDR_GETLONG(xdrs, (long*)&l)) - return FALSE; - *up = (unsigned int) l; - case XDR_FREE: - return TRUE; - } - return FALSE; - } else { - return (xdr_short(xdrs, (short *) up)); - } + if (sizeof(unsigned int) == sizeof(unsigned long)) { + return (xdr_u_long(xdrs, (unsigned long *) up)); + } else if (sizeof(unsigned int) < sizeof(unsigned long)) { + unsigned long l; + switch (xdrs->x_op) { + case XDR_ENCODE: + l = (unsigned long) *up; + return XDR_PUTLONG(xdrs, (long*)&l); + case XDR_DECODE: + if (!XDR_GETLONG(xdrs, (long*)&l)) + return FALSE; + *up = (unsigned int) l; + case XDR_FREE: + return TRUE; + } + return FALSE; + } else { + return (xdr_short(xdrs, (short *) up)); + } } /* @@ -149,18 +149,18 @@ bool_t xdr_u_int(XDR* xdrs, unsigned int* up) bool_t xdr_long(XDR* xdrs, long* lp) { - if (xdrs->x_op == XDR_ENCODE - && (sizeof(int32_t) == sizeof(long) - || (int32_t) *lp == *lp)) - return (XDR_PUTLONG(xdrs, lp)); + if (xdrs->x_op == XDR_ENCODE + && (sizeof(int32_t) == sizeof(long) + || (int32_t) *lp == *lp)) + return (XDR_PUTLONG(xdrs, lp)); - if (xdrs->x_op == XDR_DECODE) - return (XDR_GETLONG(xdrs, lp)); + if (xdrs->x_op == XDR_DECODE) + return (XDR_GETLONG(xdrs, lp)); - if (xdrs->x_op == XDR_FREE) - return (TRUE); + if (xdrs->x_op == XDR_FREE) + return (TRUE); - return (FALSE); + return (FALSE); } /* @@ -171,25 +171,25 @@ bool_t xdr_u_long(XDR* xdrs, unsigned long* ulp) { if (xdrs->x_op == XDR_DECODE) { - long l; - if (XDR_GETLONG(xdrs, &l) == FALSE) - return FALSE; - *ulp = (uint32_t) l; - return TRUE; + long l; + if (XDR_GETLONG(xdrs, &l) == FALSE) + return FALSE; + *ulp = (uint32_t) l; + return TRUE; } if (xdrs->x_op == XDR_ENCODE) { - if (sizeof(uint32_t) != sizeof(unsigned long) - && (uint32_t) *ulp != *ulp) - return FALSE; + if (sizeof(uint32_t) != sizeof(unsigned long) + && (uint32_t) *ulp != *ulp) + return FALSE; - return (XDR_PUTLONG(xdrs, (long *) ulp)); + return (XDR_PUTLONG(xdrs, (long *) ulp)); } - if (xdrs->x_op == XDR_FREE) - return (TRUE); + if (xdrs->x_op == XDR_FREE) + return (TRUE); - return (FALSE); + return (FALSE); } @@ -254,25 +254,25 @@ bool_t xdr_u_longlong_t (XDR * xdrs, unsigned long long* ullp) */ bool_t xdr_short(XDR* xdrs, short* sp) { - long l; + long l; - switch (xdrs->x_op) { + switch (xdrs->x_op) { - case XDR_ENCODE: - l = (long) *sp; - return (XDR_PUTLONG(xdrs, &l)); + case XDR_ENCODE: + l = (long) *sp; + return (XDR_PUTLONG(xdrs, &l)); - case XDR_DECODE: - if (!XDR_GETLONG(xdrs, &l)) { - return (FALSE); - } - *sp = (short) l; - return (TRUE); + case XDR_DECODE: + if (!XDR_GETLONG(xdrs, &l)) { + return (FALSE); + } + *sp = (short) l; + return (TRUE); - case XDR_FREE: - return (TRUE); - } - return (FALSE); + case XDR_FREE: + return (TRUE); + } + return (FALSE); } /* @@ -280,25 +280,25 @@ bool_t xdr_short(XDR* xdrs, short* sp) */ bool_t xdr_u_short(XDR* xdrs, unsigned short* usp) { - unsigned long l; + unsigned long l; - switch (xdrs->x_op) { + switch (xdrs->x_op) { - case XDR_ENCODE: - l = (unsigned long) * usp; - return (XDR_PUTLONG(xdrs, (long*)&l)); + case XDR_ENCODE: + l = (unsigned long) * usp; + return (XDR_PUTLONG(xdrs, (long*)&l)); - case XDR_DECODE: - if (!XDR_GETLONG(xdrs, (long*)&l)) { - return (FALSE); - } - *usp = (unsigned short) l; - return (TRUE); + case XDR_DECODE: + if (!XDR_GETLONG(xdrs, (long*)&l)) { + return (FALSE); + } + *usp = (unsigned short) l; + return (TRUE); - case XDR_FREE: - return (TRUE); - } - return (FALSE); + case XDR_FREE: + return (TRUE); + } + return (FALSE); } @@ -307,14 +307,14 @@ bool_t xdr_u_short(XDR* xdrs, unsigned short* usp) */ bool_t xdr_char(XDR* xdrs, char* cp) { - int i; - - i = (*cp); - if (!xdr_int(xdrs, &i)) { - return (FALSE); - } - *cp = i; - return (TRUE); + int i; + + i = (*cp); + if (!xdr_int(xdrs, &i)) { + return (FALSE); + } + *cp = i; + return (TRUE); } /* @@ -322,14 +322,14 @@ bool_t xdr_char(XDR* xdrs, char* cp) */ bool_t xdr_u_char(XDR* xdrs, unsigned char* cp) { - unsigned int u; - - u = (*cp); - if (!xdr_u_int(xdrs, &u)) { - return (FALSE); - } - *cp = u; - return (TRUE); + unsigned int u; + + u = (*cp); + if (!xdr_u_int(xdrs, &u)) { + return (FALSE); + } + *cp = u; + return (TRUE); } /* @@ -337,25 +337,25 @@ bool_t xdr_u_char(XDR* xdrs, unsigned char* cp) */ bool_t xdr_bool(XDR *xdrs, bool_t *bp) { - long lb; + long lb; - switch (xdrs->x_op) { + switch (xdrs->x_op) { - case XDR_ENCODE: - lb = *bp ? XDR_TRUE : XDR_FALSE; - return (XDR_PUTLONG(xdrs, &lb)); + case XDR_ENCODE: + lb = *bp ? XDR_TRUE : XDR_FALSE; + return (XDR_PUTLONG(xdrs, &lb)); - case XDR_DECODE: - if (!XDR_GETLONG(xdrs, &lb)) { - return (FALSE); - } - *bp = (lb == XDR_FALSE) ? FALSE : TRUE; - return (TRUE); + case XDR_DECODE: + if (!XDR_GETLONG(xdrs, &lb)) { + return (FALSE); + } + *bp = (lb == XDR_FALSE) ? FALSE : TRUE; + return (TRUE); - case XDR_FREE: - return (TRUE); - } - return (FALSE); + case XDR_FREE: + return (TRUE); + } + return (FALSE); } /* @@ -363,10 +363,10 @@ bool_t xdr_bool(XDR *xdrs, bool_t *bp) */ bool_t xdr_enum(XDR *xdrs, enum_t *ep) { - /* - * enums are treated as ints - */ - return (xdr_long(xdrs, (long *) ep)); + /* + * enums are treated as ints + */ + return (xdr_long(xdrs, (long *) ep)); } /* @@ -376,45 +376,45 @@ bool_t xdr_enum(XDR *xdrs, enum_t *ep) */ bool_t xdr_opaque(XDR *xdrs, char* cp, unsigned int cnt) { - register unsigned int rndup; - static char crud[BYTES_PER_XDR_UNIT]; - - /* - * if no data we are done - */ - if (cnt == 0) - return (TRUE); - - /* - * round byte count to full xdr units - */ - rndup = cnt % BYTES_PER_XDR_UNIT; - if (rndup > 0) - rndup = BYTES_PER_XDR_UNIT - rndup; - - if (xdrs->x_op == XDR_DECODE) { - if (!XDR_GETBYTES(xdrs, cp, cnt)) { - return (FALSE); - } - if (rndup == 0) - return (TRUE); - return (XDR_GETBYTES(xdrs, crud, rndup)); - } - - if (xdrs->x_op == XDR_ENCODE) { - if (!XDR_PUTBYTES(xdrs, cp, cnt)) { - return (FALSE); - } - if (rndup == 0) - return (TRUE); - return (XDR_PUTBYTES(xdrs, xdr_zero, rndup)); - } - - if (xdrs->x_op == XDR_FREE) { - return (TRUE); - } - - return (FALSE); + register unsigned int rndup; + static char crud[BYTES_PER_XDR_UNIT]; + + /* + * if no data we are done + */ + if (cnt == 0) + return (TRUE); + + /* + * round byte count to full xdr units + */ + rndup = cnt % BYTES_PER_XDR_UNIT; + if (rndup > 0) + rndup = BYTES_PER_XDR_UNIT - rndup; + + if (xdrs->x_op == XDR_DECODE) { + if (!XDR_GETBYTES(xdrs, cp, cnt)) { + return (FALSE); + } + if (rndup == 0) + return (TRUE); + return (XDR_GETBYTES(xdrs, crud, rndup)); + } + + if (xdrs->x_op == XDR_ENCODE) { + if (!XDR_PUTBYTES(xdrs, cp, cnt)) { + return (FALSE); + } + if (rndup == 0) + return (TRUE); + return (XDR_PUTBYTES(xdrs, xdr_zero, rndup)); + } + + if (xdrs->x_op == XDR_FREE) { + return (TRUE); + } + + return (FALSE); } /* @@ -424,49 +424,49 @@ bool_t xdr_opaque(XDR *xdrs, char* cp, unsigned int cnt) */ bool_t xdr_bytes(XDR *xdrs, char** cpp, unsigned int *sizep, unsigned int maxsize) { - register char *sp = *cpp; /* sp is the actual string pointer */ - register unsigned int nodesize; - - /* - * first deal with the length since xdr bytes are counted - */ - if (!xdr_u_int(xdrs, sizep)) { - return (FALSE); - } - nodesize = *sizep; - if ((nodesize > maxsize) && (xdrs->x_op != XDR_FREE)) { - return (FALSE); - } - - /* - * now deal with the actual bytes - */ - switch (xdrs->x_op) { - - case XDR_DECODE: - if (nodesize == 0) { - return (TRUE); - } - if (sp == NULL) { - *cpp = sp = (char *) rt_malloc(nodesize); - } - if (sp == NULL) { - rt_kprintf("xdr_bytes: out of memory\n"); - return (FALSE); - } - /* fall into ... */ - - case XDR_ENCODE: - return (xdr_opaque(xdrs, sp, nodesize)); - - case XDR_FREE: - if (sp != NULL) { - rt_free(sp); - *cpp = NULL; - } - return (TRUE); - } - return (FALSE); + register char *sp = *cpp; /* sp is the actual string pointer */ + register unsigned int nodesize; + + /* + * first deal with the length since xdr bytes are counted + */ + if (!xdr_u_int(xdrs, sizep)) { + return (FALSE); + } + nodesize = *sizep; + if ((nodesize > maxsize) && (xdrs->x_op != XDR_FREE)) { + return (FALSE); + } + + /* + * now deal with the actual bytes + */ + switch (xdrs->x_op) { + + case XDR_DECODE: + if (nodesize == 0) { + return (TRUE); + } + if (sp == NULL) { + *cpp = sp = (char *) rt_malloc(nodesize); + } + if (sp == NULL) { + rt_kprintf("xdr_bytes: out of memory\n"); + return (FALSE); + } + /* fall into ... */ + + case XDR_ENCODE: + return (xdr_opaque(xdrs, sp, nodesize)); + + case XDR_FREE: + if (sp != NULL) { + rt_free(sp); + *cpp = NULL; + } + return (TRUE); + } + return (FALSE); } /* @@ -474,7 +474,7 @@ bool_t xdr_bytes(XDR *xdrs, char** cpp, unsigned int *sizep, unsigned int maxsiz */ bool_t xdr_netobj(XDR *xdrs, struct netobj *np) { - return (xdr_bytes(xdrs, &np->n_bytes, &np->n_len, MAX_NETOBJ_SZ)); + return (xdr_bytes(xdrs, &np->n_bytes, &np->n_len, MAX_NETOBJ_SZ)); } /* @@ -490,30 +490,30 @@ bool_t xdr_netobj(XDR *xdrs, struct netobj *np) */ bool_t xdr_union(XDR* xdrs, enum_t* dscmp, char* unp, const struct xdr_discrim* choices, xdrproc_t dfault) { - register enum_t dscm; - - /* - * we deal with the discriminator; it's an enum - */ - if (!xdr_enum(xdrs, dscmp)) { - return (FALSE); - } - dscm = *dscmp; - - /* - * search choices for a value that matches the discriminator. - * if we find one, execute the xdr routine for that value. - */ - for (; choices->proc != NULL_xdrproc_t; choices++) { - if (choices->value == dscm) - return ((*(choices->proc)) (xdrs, unp, LASTUNSIGNED)); - } - - /* - * no match - execute the default xdr routine if there is one - */ - return ((dfault == NULL_xdrproc_t) ? FALSE : - (*dfault) (xdrs, unp, LASTUNSIGNED)); + register enum_t dscm; + + /* + * we deal with the discriminator; it's an enum + */ + if (!xdr_enum(xdrs, dscmp)) { + return (FALSE); + } + dscm = *dscmp; + + /* + * search choices for a value that matches the discriminator. + * if we find one, execute the xdr routine for that value. + */ + for (; choices->proc != NULL_xdrproc_t; choices++) { + if (choices->value == dscm) + return ((*(choices->proc)) (xdrs, unp, LASTUNSIGNED)); + } + + /* + * no match - execute the default xdr routine if there is one + */ + return ((dfault == NULL_xdrproc_t) ? FALSE : + (*dfault) (xdrs, unp, LASTUNSIGNED)); } @@ -533,70 +533,70 @@ bool_t xdr_union(XDR* xdrs, enum_t* dscmp, char* unp, const struct xdr_discrim* */ bool_t xdr_string(XDR *xdrs, char **cpp, unsigned int maxsize) { - register char *sp = *cpp; /* sp is the actual string pointer */ - unsigned int size; - unsigned int nodesize; - - /* - * first deal with the length since xdr strings are counted-strings - */ - switch (xdrs->x_op) { - case XDR_FREE: - if (sp == NULL) { - return (TRUE); /* already free */ - } - /* fall through... */ - case XDR_ENCODE: - size = strlen(sp); - break; - } - if (!xdr_u_int(xdrs, &size)) { - return (FALSE); - } - if (size > maxsize) { - return (FALSE); - } - nodesize = size + 1; - - /* - * now deal with the actual bytes - */ - switch (xdrs->x_op) { - - case XDR_DECODE: - if (nodesize == 0) { - return (TRUE); - } - if (sp == NULL) - *cpp = sp = (char *) rt_malloc(nodesize); - if (sp == NULL) { - rt_kprintf("xdr_string: out of memory\n"); - return (FALSE); - } - sp[size] = 0; - /* fall into ... */ - - case XDR_ENCODE: - return (xdr_opaque(xdrs, sp, size)); - - case XDR_FREE: - rt_free(sp); - *cpp = NULL; - return (TRUE); - } - return (FALSE); + register char *sp = *cpp; /* sp is the actual string pointer */ + unsigned int size; + unsigned int nodesize; + + /* + * first deal with the length since xdr strings are counted-strings + */ + switch (xdrs->x_op) { + case XDR_FREE: + if (sp == NULL) { + return (TRUE); /* already free */ + } + /* fall through... */ + case XDR_ENCODE: + size = strlen(sp); + break; + } + if (!xdr_u_int(xdrs, &size)) { + return (FALSE); + } + if (size > maxsize) { + return (FALSE); + } + nodesize = size + 1; + + /* + * now deal with the actual bytes + */ + switch (xdrs->x_op) { + + case XDR_DECODE: + if (nodesize == 0) { + return (TRUE); + } + if (sp == NULL) + *cpp = sp = (char *) rt_malloc(nodesize); + if (sp == NULL) { + rt_kprintf("xdr_string: out of memory\n"); + return (FALSE); + } + sp[size] = 0; + /* fall into ... */ + + case XDR_ENCODE: + return (xdr_opaque(xdrs, sp, size)); + + case XDR_FREE: + rt_free(sp); + *cpp = NULL; + return (TRUE); + } + return (FALSE); } -/* - * Wrapper for xdr_string that can be called directly from +/* + * Wrapper for xdr_string that can be called directly from * routines like clnt_call */ bool_t xdr_wrapstring(XDR *xdrs, char **cpp) { - if (xdr_string(xdrs, cpp, LASTUNSIGNED)) { - return (TRUE); - } - return (FALSE); + if (xdr_string(xdrs, cpp, LASTUNSIGNED)) { + return (TRUE); + } + return (FALSE); } /* @@ -608,69 +608,69 @@ bool_t xdr_wrapstring(XDR *xdrs, char **cpp) */ bool_t xdr_array(XDR *xdrs, char **addrp, unsigned int *sizep, unsigned int maxsize, unsigned int elsize, xdrproc_t elproc) { - register unsigned int i; - register char* target = *addrp; - register unsigned int c; /* the actual element count */ - register bool_t stat = TRUE; - register unsigned int nodesize; - - /* like strings, arrays are really counted arrays */ - if (!xdr_u_int(xdrs, sizep)) { - return (FALSE); - } - c = *sizep; - if ((c > maxsize) && (xdrs->x_op != XDR_FREE)) { - return (FALSE); - } - /* duh, look for integer overflow (fefe) */ - { - unsigned int i; - nodesize = 0; - for (i=c; i; --i) { - unsigned int tmp=nodesize+elsize; - if (tmpx_op) { - case XDR_DECODE: - if (c == 0) - return (TRUE); - *addrp = target = rt_malloc(nodesize); - if (target == NULL) { - rt_kprintf("xdr_array: out of memory\n"); - return (FALSE); - } - memset(target, 0, nodesize); - break; - - case XDR_FREE: - return (TRUE); - } - - /* - * now we xdr each element of array - */ - for (i = 0; (i < c) && stat; i++) { - stat = (*elproc) (xdrs, target, LASTUNSIGNED); - target += elsize; - } - - /* - * the array may need freeing - */ - if (xdrs->x_op == XDR_FREE) { - rt_free(*addrp); - *addrp = NULL; - } - return (stat); + register unsigned int i; + register char* target = *addrp; + register unsigned int c; /* the actual element count */ + register bool_t stat = TRUE; + register unsigned int nodesize; + + /* like strings, arrays are really counted arrays */ + if (!xdr_u_int(xdrs, sizep)) { + return (FALSE); + } + c = *sizep; + if ((c > maxsize) && (xdrs->x_op != XDR_FREE)) { + return (FALSE); + } + /* duh, look for integer overflow (fefe) */ + { + unsigned int i; + nodesize = 0; + for (i=c; i; --i) { + unsigned int tmp=nodesize+elsize; + if (tmpx_op) { + case XDR_DECODE: + if (c == 0) + return (TRUE); + *addrp = target = rt_malloc(nodesize); + if (target == NULL) { + rt_kprintf("xdr_array: out of memory\n"); + return (FALSE); + } + memset(target, 0, nodesize); + break; + + case XDR_FREE: + return (TRUE); + } + + /* + * now we xdr each element of array + */ + for (i = 0; (i < c) && stat; i++) { + stat = (*elproc) (xdrs, target, LASTUNSIGNED); + target += elsize; + } + + /* + * the array may need freeing + */ + if (xdrs->x_op == XDR_FREE) { + rt_free(*addrp); + *addrp = NULL; + } + return (stat); } /* @@ -685,17 +685,17 @@ bool_t xdr_array(XDR *xdrs, char **addrp, unsigned int *sizep, unsigned int maxs */ bool_t xdr_vector(XDR *xdrs, char *basep, unsigned int nelem, unsigned int elemsize, xdrproc_t xdr_elem) { - register unsigned int i; - register char *elptr; - - elptr = basep; - for (i = 0; i < nelem; i++) { - if (!(*xdr_elem) (xdrs, elptr, LASTUNSIGNED)) { - return (FALSE); - } - elptr += elemsize; - } - return (TRUE); + register unsigned int i; + register char *elptr; + + elptr = basep; + for (i = 0; i < nelem; i++) { + if (!(*xdr_elem) (xdrs, elptr, LASTUNSIGNED)) { + return (FALSE); + } + elptr += elemsize; + } + return (TRUE); } @@ -710,31 +710,31 @@ bool_t xdr_vector(XDR *xdrs, char *basep, unsigned int nelem, unsigned int elems */ bool_t xdr_reference(XDR *xdrs, char **pp, unsigned int size, xdrproc_t proc) { - register char* loc = *pp; - register bool_t stat; - - if (loc == NULL) - switch (xdrs->x_op) { - case XDR_FREE: - return (TRUE); - - case XDR_DECODE: - *pp = loc = (char*) rt_malloc(size); - if (loc == NULL) { - rt_kprintf("xdr_reference: out of memory\n"); - return (FALSE); - } - memset(loc, 0, (int) size); - break; - } - - stat = (*proc) (xdrs, loc, LASTUNSIGNED); - - if (xdrs->x_op == XDR_FREE) { - rt_free(loc); - *pp = NULL; - } - return (stat); + register char* loc = *pp; + register bool_t stat; + + if (loc == NULL) + switch (xdrs->x_op) { + case XDR_FREE: + return (TRUE); + + case XDR_DECODE: + *pp = loc = (char*) rt_malloc(size); + if (loc == NULL) { + rt_kprintf("xdr_reference: out of memory\n"); + return (FALSE); + } + memset(loc, 0, (int) size); + break; + } + + stat = (*proc) (xdrs, loc, LASTUNSIGNED); + + if (xdrs->x_op == XDR_FREE) { + rt_free(loc); + *pp = NULL; + } + return (stat); } @@ -760,15 +760,15 @@ bool_t xdr_reference(XDR *xdrs, char **pp, unsigned int size, xdrproc_t proc) bool_t xdr_pointer(XDR *xdrs, char **objpp, unsigned int obj_size, xdrproc_t xdr_obj) { - bool_t more_data; - - more_data = (*objpp != NULL); - if (!xdr_bool(xdrs, &more_data)) { - return (FALSE); - } - if (!more_data) { - *objpp = NULL; - return (TRUE); - } - return (xdr_reference(xdrs, objpp, obj_size, xdr_obj)); + bool_t more_data; + + more_data = (*objpp != NULL); + if (!xdr_bool(xdrs, &more_data)) { + return (FALSE); + } + if (!more_data) { + *objpp = NULL; + return (TRUE); + } + return (xdr_reference(xdrs, objpp, obj_size, xdr_obj)); } diff --git a/components/dfs/filesystems/nfs/rpc/xdr.h b/components/dfs/filesystems/nfs/rpc/xdr.h index fe38c4d120..d938f0eaa8 100644 --- a/components/dfs/filesystems/nfs/rpc/xdr.h +++ b/components/dfs/filesystems/nfs/rpc/xdr.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -93,7 +93,7 @@ enum xdr_op { /* * This is the number of bytes per unit of external data. */ -#define BYTES_PER_XDR_UNIT (4) +#define BYTES_PER_XDR_UNIT (4) /* * This only works if the above is a power of 2. But it's defined to be * 4 by the appropriate RFCs. So it will work. And it's normally quicker @@ -110,35 +110,35 @@ enum xdr_op { typedef struct XDR XDR; struct XDR { - enum xdr_op x_op; /* operation; fast additional param */ + enum xdr_op x_op; /* operation; fast additional param */ struct xdr_ops { - bool_t (*x_getlong) (XDR *__xdrs, long *__lp); - /* get a long from underlying stream */ - bool_t (*x_putlong) (XDR *__xdrs, const long *__lp); - /* put a long to " */ - bool_t (*x_getbytes) (XDR *__xdrs, char* __addr, unsigned int __len); - /* get some bytes from " */ - bool_t (*x_putbytes) (XDR *__xdrs, const char *__addr, unsigned int __len); - /* put some bytes to " */ - unsigned int (*x_getpostn) (const XDR *__xdrs); - /* returns bytes off from beginning */ - bool_t (*x_setpostn) (XDR *__xdrs, unsigned int __pos); - /* lets you reposition the stream */ - int32_t *(*x_inline) (XDR *__xdrs, unsigned int __len); - /* buf quick ptr to buffered data */ - void (*x_destroy) (XDR *__xdrs); - /* free privates of this xdr_stream */ - bool_t (*x_getint32) (XDR *__xdrs, int32_t *__ip); - /* get a int from underlying stream */ - bool_t (*x_putint32) (XDR *__xdrs, const int32_t *__ip); - /* put a int to " */ + bool_t (*x_getlong) (XDR *__xdrs, long *__lp); + /* get a long from underlying stream */ + bool_t (*x_putlong) (XDR *__xdrs, const long *__lp); + /* put a long to " */ + bool_t (*x_getbytes) (XDR *__xdrs, char* __addr, unsigned int __len); + /* get some bytes from " */ + bool_t (*x_putbytes) (XDR *__xdrs, const char *__addr, unsigned int __len); + /* put some bytes to " */ + unsigned int (*x_getpostn) (const XDR *__xdrs); + /* returns bytes off from beginning */ + bool_t (*x_setpostn) (XDR *__xdrs, unsigned int __pos); + /* lets you reposition the stream */ + int32_t *(*x_inline) (XDR *__xdrs, unsigned int __len); + /* buf quick ptr to buffered data */ + void (*x_destroy) (XDR *__xdrs); + /* free privates of this xdr_stream */ + bool_t (*x_getint32) (XDR *__xdrs, int32_t *__ip); + /* get a int from underlying stream */ + bool_t (*x_putint32) (XDR *__xdrs, const int32_t *__ip); + /* put a int to " */ } *x_ops; - char* x_public; /* users' data */ - char* x_private; /* pointer to private data */ - char* x_base; /* private used for position info */ - unsigned int x_handy; /* extra private word */ + char* x_public; /* users' data */ + char* x_private; /* pointer to private data */ + char* x_base; /* private used for position info */ + unsigned int x_handy; /* extra private word */ }; /* @@ -173,51 +173,51 @@ typedef bool_t (*xdrproc_t) (XDR *, void *,...); #define xdr_putint32(xdrs, int32p) \ (*(xdrs)->x_ops->x_putint32)(xdrs, int32p) -#define XDR_GETLONG(xdrs, longp) \ - (*(xdrs)->x_ops->x_getlong)(xdrs, longp) -#define xdr_getlong(xdrs, longp) \ - (*(xdrs)->x_ops->x_getlong)(xdrs, longp) - -#define XDR_PUTLONG(xdrs, longp) \ - (*(xdrs)->x_ops->x_putlong)(xdrs, longp) -#define xdr_putlong(xdrs, longp) \ - (*(xdrs)->x_ops->x_putlong)(xdrs, longp) - -#define XDR_GETBYTES(xdrs, addr, len) \ - (*(xdrs)->x_ops->x_getbytes)(xdrs, addr, len) -#define xdr_getbytes(xdrs, addr, len) \ - (*(xdrs)->x_ops->x_getbytes)(xdrs, addr, len) - -#define XDR_PUTBYTES(xdrs, addr, len) \ - (*(xdrs)->x_ops->x_putbytes)(xdrs, addr, len) -#define xdr_putbytes(xdrs, addr, len) \ - (*(xdrs)->x_ops->x_putbytes)(xdrs, addr, len) - -#define XDR_GETPOS(xdrs) \ - (*(xdrs)->x_ops->x_getpostn)(xdrs) -#define xdr_getpos(xdrs) \ - (*(xdrs)->x_ops->x_getpostn)(xdrs) - -#define XDR_SETPOS(xdrs, pos) \ - (*(xdrs)->x_ops->x_setpostn)(xdrs, pos) -#define xdr_setpos(xdrs, pos) \ - (*(xdrs)->x_ops->x_setpostn)(xdrs, pos) - -#define XDR_INLINE(xdrs, len) \ - (*(xdrs)->x_ops->x_inline)(xdrs, len) -#define xdr_inline(xdrs, len) \ - (*(xdrs)->x_ops->x_inline)(xdrs, len) - -#define XDR_DESTROY(xdrs) \ - do { \ - if ((xdrs)->x_ops->x_destroy) \ - (*(xdrs)->x_ops->x_destroy)(xdrs); \ - } while (0) -#define xdr_destroy(xdrs) \ - do { \ - if ((xdrs)->x_ops->x_destroy) \ - (*(xdrs)->x_ops->x_destroy)(xdrs); \ - } while (0) +#define XDR_GETLONG(xdrs, longp) \ + (*(xdrs)->x_ops->x_getlong)(xdrs, longp) +#define xdr_getlong(xdrs, longp) \ + (*(xdrs)->x_ops->x_getlong)(xdrs, longp) + +#define XDR_PUTLONG(xdrs, longp) \ + (*(xdrs)->x_ops->x_putlong)(xdrs, longp) +#define xdr_putlong(xdrs, longp) \ + (*(xdrs)->x_ops->x_putlong)(xdrs, longp) + +#define XDR_GETBYTES(xdrs, addr, len) \ + (*(xdrs)->x_ops->x_getbytes)(xdrs, addr, len) +#define xdr_getbytes(xdrs, addr, len) \ + (*(xdrs)->x_ops->x_getbytes)(xdrs, addr, len) + +#define XDR_PUTBYTES(xdrs, addr, len) \ + (*(xdrs)->x_ops->x_putbytes)(xdrs, addr, len) +#define xdr_putbytes(xdrs, addr, len) \ + (*(xdrs)->x_ops->x_putbytes)(xdrs, addr, len) + +#define XDR_GETPOS(xdrs) \ + (*(xdrs)->x_ops->x_getpostn)(xdrs) +#define xdr_getpos(xdrs) \ + (*(xdrs)->x_ops->x_getpostn)(xdrs) + +#define XDR_SETPOS(xdrs, pos) \ + (*(xdrs)->x_ops->x_setpostn)(xdrs, pos) +#define xdr_setpos(xdrs, pos) \ + (*(xdrs)->x_ops->x_setpostn)(xdrs, pos) + +#define XDR_INLINE(xdrs, len) \ + (*(xdrs)->x_ops->x_inline)(xdrs, len) +#define xdr_inline(xdrs, len) \ + (*(xdrs)->x_ops->x_inline)(xdrs, len) + +#define XDR_DESTROY(xdrs) \ + do { \ + if ((xdrs)->x_ops->x_destroy) \ + (*(xdrs)->x_ops->x_destroy)(xdrs); \ + } while (0) +#define xdr_destroy(xdrs) \ + do { \ + if ((xdrs)->x_ops->x_destroy) \ + (*(xdrs)->x_ops->x_destroy)(xdrs); \ + } while (0) /* * Support struct for discriminated unions. @@ -261,10 +261,10 @@ struct xdr_discrim * and shouldn't be used any longer. Code which use this defines or longs * in the RPC code will not work on 64bit Solaris platforms ! */ -#define IXDR_GET_LONG(buf) ((long)IXDR_GET_U_INT32(buf)) -#define IXDR_PUT_LONG(buf, v) ((long)IXDR_PUT_INT32(buf, (long)(v))) -#define IXDR_GET_U_LONG(buf) ((unsigned long)IXDR_GET_LONG(buf)) -#define IXDR_PUT_U_LONG(buf, v) IXDR_PUT_LONG(buf, (long)(v)) +#define IXDR_GET_LONG(buf) ((long)IXDR_GET_U_INT32(buf)) +#define IXDR_PUT_LONG(buf, v) ((long)IXDR_PUT_INT32(buf, (long)(v))) +#define IXDR_GET_U_LONG(buf) ((unsigned long)IXDR_GET_LONG(buf)) +#define IXDR_PUT_U_LONG(buf, v) IXDR_PUT_LONG(buf, (long)(v)) #define IXDR_GET_BOOL(buf) ((bool_t)IXDR_GET_LONG(buf)) @@ -305,24 +305,24 @@ extern bool_t xdr_uint64_t (XDR *__xdrs, uint64_t *__up); extern bool_t xdr_bool (XDR *__xdrs, bool_t *__bp); extern bool_t xdr_enum (XDR *__xdrs, enum_t *__ep); extern bool_t xdr_array (XDR * _xdrs, char* *__addrp, unsigned int *__sizep, - unsigned int __maxsize, unsigned int __elsize, xdrproc_t __elproc); + unsigned int __maxsize, unsigned int __elsize, xdrproc_t __elproc); extern bool_t xdr_bytes (XDR *xdrs, char **cpp, unsigned int *sizep, - unsigned int maxsize); + unsigned int maxsize); extern bool_t xdr_opaque (XDR *__xdrs, char* __cp, unsigned int __cnt); extern bool_t xdr_string (XDR *xdrs, char **cpp, unsigned int maxsize); extern bool_t xdr_union (XDR *__xdrs, enum_t *__dscmp, char *__unp, - const struct xdr_discrim *__choices, - xdrproc_t dfault); + const struct xdr_discrim *__choices, + xdrproc_t dfault); extern bool_t xdr_char (XDR *__xdrs, char *__cp); extern bool_t xdr_u_char (XDR *__xdrs, unsigned char *__cp); extern bool_t xdr_vector (XDR *__xdrs, char *__basep, unsigned int __nelem, - unsigned int __elemsize, xdrproc_t __xdr_elem); + unsigned int __elemsize, xdrproc_t __xdr_elem); extern bool_t xdr_float (XDR *__xdrs, float *__fp); extern bool_t xdr_double (XDR *__xdrs, double *__dp); extern bool_t xdr_reference (XDR *__xdrs, char* *__xpp, unsigned int __size, - xdrproc_t __proc); + xdrproc_t __proc); extern bool_t xdr_pointer (XDR *__xdrs, char **__objpp, - unsigned int __obj_size, xdrproc_t __xdr_obj); + unsigned int __obj_size, xdrproc_t __xdr_obj); extern bool_t xdr_wrapstring (XDR *__xdrs, char **cpp); extern unsigned long xdr_sizeof (xdrproc_t, void *); @@ -346,13 +346,13 @@ extern bool_t xdr_netobj (XDR *__xdrs, struct netobj *__np); /* XDR using memory buffers */ extern void xdrmem_create (XDR *__xdrs, const char* __addr, - unsigned int __size, enum xdr_op __xop); + unsigned int __size, enum xdr_op __xop); /* XDR pseudo records for tcp */ extern void xdrrec_create (XDR *__xdrs, unsigned int __sendsize, - unsigned int __recvsize, char* __tcp_handle, - int (*__readit) (char *, char *, int), - int (*__writeit) (char *, char *, int)); + unsigned int __recvsize, char* __tcp_handle, + int (*__readit) (char *, char *, int), + int (*__writeit) (char *, char *, int)); /* make end of xdr record */ extern bool_t xdrrec_endofrecord (XDR *__xdrs, bool_t __sendnow); diff --git a/components/dfs/filesystems/nfs/rpc/xdr_mem.c b/components/dfs/filesystems/nfs/rpc/xdr_mem.c index ca69ed3647..7bd4737e16 100644 --- a/components/dfs/filesystems/nfs/rpc/xdr_mem.c +++ b/components/dfs/filesystems/nfs/rpc/xdr_mem.c @@ -1,12 +1,12 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes */ -/* @(#)xdr_mem.c 2.1 88/07/29 4.0 RPCSRC */ +/* @(#)xdr_mem.c 2.1 88/07/29 4.0 RPCSRC */ /* * Sun RPC is a product of Sun Microsystems, Inc. and is provided for * unrestricted use provided that this legend is included on all tape @@ -14,23 +14,23 @@ * may copy or modify Sun RPC without charge, but are not authorized * to license or distribute it to anyone else except as part of a product or * program developed by the user. - * + * * SUN RPC IS PROVIDED AS IS WITH NO WARRANTIES OF ANY KIND INCLUDING THE * WARRANTIES OF DESIGN, MERCHANTIBILITY AND FITNESS FOR A PARTICULAR * PURPOSE, OR ARISING FROM A COURSE OF DEALING, USAGE OR TRADE PRACTICE. - * + * * Sun RPC is provided with no support and without any obligation on the * part of Sun Microsystems, Inc. to assist in its use, correction, * modification or enhancement. - * + * * SUN MICROSYSTEMS, INC. SHALL HAVE NO LIABILITY WITH RESPECT TO THE * INFRINGEMENT OF COPYRIGHTS, TRADE SECRETS OR ANY PATENTS BY SUN RPC * OR ANY PART THEREOF. - * + * * In no event will Sun Microsystems, Inc. be liable for any lost revenue * or profits or other special, indirect and consequential damages, even if * Sun has been advised of the possibility of such damages. - * + * * Sun Microsystems, Inc. * 2550 Garcia Avenue * Mountain View, California 94043 @@ -65,30 +65,30 @@ static int32_t *xdrmem_inline (XDR *, unsigned int); static void xdrmem_destroy (XDR *); static struct xdr_ops xdrmem_ops = { - xdrmem_getlong, - xdrmem_putlong, - xdrmem_getbytes, - xdrmem_putbytes, - xdrmem_getpos, - xdrmem_setpos, - xdrmem_inline, - xdrmem_destroy, - NULL, - NULL + xdrmem_getlong, + xdrmem_putlong, + xdrmem_getbytes, + xdrmem_putbytes, + xdrmem_getpos, + xdrmem_setpos, + xdrmem_inline, + xdrmem_destroy, + NULL, + NULL }; /* * The procedure xdrmem_create initializes a stream descriptor for a - * memory buffer. + * memory buffer. */ void xdrmem_create (XDR *xdrs, const char* addr, unsigned int size, enum xdr_op op) { - xdrs->x_op = op; - xdrs->x_ops = &xdrmem_ops; - xdrs->x_private = xdrs->x_base = (char*)addr; - xdrs->x_handy = size; + xdrs->x_op = op; + xdrs->x_ops = &xdrmem_ops; + xdrs->x_private = xdrs->x_base = (char*)addr; + xdrs->x_handy = size; } static void @@ -140,7 +140,7 @@ xdrmem_putbytes (XDR *xdrs, const char *addr, unsigned int len) static unsigned int xdrmem_getpos (const XDR *xdrs) { - return ((unsigned long) xdrs->x_private - (unsigned long) xdrs->x_base); + return ((unsigned long) xdrs->x_private - (unsigned long) xdrs->x_base); } static bool_t xdrmem_setpos(XDR *xdrs, unsigned int pos) @@ -149,9 +149,9 @@ static bool_t xdrmem_setpos(XDR *xdrs, unsigned int pos) register char* lastaddr = xdrs->x_private + xdrs->x_handy; if ((long) newaddr > (long) lastaddr - || (UINT_MAX < LONG_MAX - && (long) UINT_MAX < (long) lastaddr - (long) newaddr)) - return (FALSE); + || (UINT_MAX < LONG_MAX + && (long) UINT_MAX < (long) lastaddr - (long) newaddr)) + return (FALSE); xdrs->x_private = newaddr; xdrs->x_handy = (long) lastaddr - (long) newaddr; return (TRUE); @@ -160,13 +160,13 @@ static bool_t xdrmem_setpos(XDR *xdrs, unsigned int pos) static int32_t * xdrmem_inline (XDR *xdrs, unsigned int len) { - int32_t *buf = 0; - - if (xdrs->x_handy >= len) { - xdrs->x_handy -= len; - buf = (int32_t *) xdrs->x_private; - xdrs->x_private += len; - } - return (buf); + int32_t *buf = 0; + + if (xdrs->x_handy >= len) { + xdrs->x_handy -= len; + buf = (int32_t *) xdrs->x_private; + xdrs->x_private += len; + } + return (buf); } diff --git a/components/dfs/filesystems/ramfs/dfs_ramfs.c b/components/dfs/filesystems/ramfs/dfs_ramfs.c index aa85081e1e..cc58590de2 100644 --- a/components/dfs/filesystems/ramfs/dfs_ramfs.c +++ b/components/dfs/filesystems/ramfs/dfs_ramfs.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/dfs/filesystems/ramfs/dfs_ramfs.h b/components/dfs/filesystems/ramfs/dfs_ramfs.h index 4975ecb332..87adde99a5 100644 --- a/components/dfs/filesystems/ramfs/dfs_ramfs.h +++ b/components/dfs/filesystems/ramfs/dfs_ramfs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/dfs/filesystems/romfs/dfs_romfs.c b/components/dfs/filesystems/romfs/dfs_romfs.c index 17dbee52f5..1b2693fc3b 100644 --- a/components/dfs/filesystems/romfs/dfs_romfs.c +++ b/components/dfs/filesystems/romfs/dfs_romfs.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/dfs/filesystems/romfs/dfs_romfs.h b/components/dfs/filesystems/romfs/dfs_romfs.h index ba6a3d7dfa..affa4bf993 100644 --- a/components/dfs/filesystems/romfs/dfs_romfs.h +++ b/components/dfs/filesystems/romfs/dfs_romfs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/dfs/filesystems/romfs/romfs.c b/components/dfs/filesystems/romfs/romfs.c index cfce09a095..847fcc6e27 100644 --- a/components/dfs/filesystems/romfs/romfs.c +++ b/components/dfs/filesystems/romfs/romfs.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/dfs/filesystems/skeleton/skeleton.c b/components/dfs/filesystems/skeleton/skeleton.c index 0c20513e82..b8dc06e9b5 100644 --- a/components/dfs/filesystems/skeleton/skeleton.c +++ b/components/dfs/filesystems/skeleton/skeleton.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/dfs/filesystems/skeleton/skeleton.h b/components/dfs/filesystems/skeleton/skeleton.h index 8a783eace5..30c721d14f 100644 --- a/components/dfs/filesystems/skeleton/skeleton.h +++ b/components/dfs/filesystems/skeleton/skeleton.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/dfs/include/dfs.h b/components/dfs/include/dfs.h index 1158df93cb..80dc433787 100644 --- a/components/dfs/include/dfs.h +++ b/components/dfs/include/dfs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/dfs/include/dfs_file.h b/components/dfs/include/dfs_file.h index 2dfacd653e..df1013d69c 100644 --- a/components/dfs/include/dfs_file.h +++ b/components/dfs/include/dfs_file.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/dfs/include/dfs_fs.h b/components/dfs/include/dfs_fs.h index 58a9e5cf55..cbf2e9552b 100644 --- a/components/dfs/include/dfs_fs.h +++ b/components/dfs/include/dfs_fs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/dfs/include/dfs_poll.h b/components/dfs/include/dfs_poll.h index d9597a4364..096a5fe712 100644 --- a/components/dfs/include/dfs_poll.h +++ b/components/dfs/include/dfs_poll.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/dfs/include/dfs_posix.h b/components/dfs/include/dfs_posix.h index 87d5f0771e..0475460d95 100644 --- a/components/dfs/include/dfs_posix.h +++ b/components/dfs/include/dfs_posix.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/dfs/include/dfs_private.h b/components/dfs/include/dfs_private.h index fccd260ac0..e602c21730 100644 --- a/components/dfs/include/dfs_private.h +++ b/components/dfs/include/dfs_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/dfs/include/dfs_select.h b/components/dfs/include/dfs_select.h index 3ac5817874..458691df20 100644 --- a/components/dfs/include/dfs_select.h +++ b/components/dfs/include/dfs_select.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/dfs/src/dfs.c b/components/dfs/src/dfs.c index 7ace0bc160..8155b088f0 100644 --- a/components/dfs/src/dfs.c +++ b/components/dfs/src/dfs.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/dfs/src/dfs_file.c b/components/dfs/src/dfs_file.c index fd205f2f3a..aa6494457a 100644 --- a/components/dfs/src/dfs_file.c +++ b/components/dfs/src/dfs_file.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/dfs/src/dfs_fs.c b/components/dfs/src/dfs_fs.c index f380cd8997..611f035811 100644 --- a/components/dfs/src/dfs_fs.c +++ b/components/dfs/src/dfs_fs.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -522,16 +522,16 @@ INIT_ENV_EXPORT(dfs_mount_table); int dfs_mount_device(rt_device_t dev) { int index = 0; - + if(dev == RT_NULL) { rt_kprintf("the device is NULL to be mounted.\n"); return -RT_ERROR; } - + while (1) { if (mount_table[index].path == NULL) break; - + if(strcmp(mount_table[index].device_name, dev->parent.name) == 0) { if (dfs_mount(mount_table[index].device_name, mount_table[index].path, @@ -548,10 +548,10 @@ int dfs_mount_device(rt_device_t dev) return RT_EOK; } } - + index ++; } - + rt_kprintf("can't find device:%s to be mounted.\n", dev->parent.name); return -RT_ERROR; } diff --git a/components/dfs/src/dfs_posix.c b/components/dfs/src/dfs_posix.c index fc603df437..a7c306366f 100644 --- a/components/dfs/src/dfs_posix.c +++ b/components/dfs/src/dfs_posix.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/dfs/src/poll.c b/components/dfs/src/poll.c index fc48eca758..d1e0372494 100644 --- a/components/dfs/src/poll.c +++ b/components/dfs/src/poll.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -140,7 +140,7 @@ static int do_pollfd(struct pollfd *pollfd, rt_pollreq_t *req) /* dealwith the device return error -1*/ if (mask < 0) - { + { fd_put(f); pollfd->revents = 0; return mask; @@ -232,4 +232,4 @@ int poll(struct pollfd *fds, nfds_t nfds, int timeout) return num; } -#endif +#endif diff --git a/components/dfs/src/select.c b/components/dfs/src/select.c index 181855bc74..c9286ca97f 100644 --- a/components/dfs/src/select.c +++ b/components/dfs/src/select.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -180,4 +180,4 @@ int select(int nfds, fd_set *readfds, fd_set *writefds, fd_set *exceptfds, struc return ret; } -#endif +#endif diff --git a/components/drivers/audio/audio.c b/components/drivers/audio/audio.c index c3f8723db6..f9d42aeb5c 100644 --- a/components/drivers/audio/audio.c +++ b/components/drivers/audio/audio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/audio/audio_pipe.c b/components/drivers/audio/audio_pipe.c index e9de1ffb74..4dd1138610 100644 --- a/components/drivers/audio/audio_pipe.c +++ b/components/drivers/audio/audio_pipe.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/audio/audio_pipe.h b/components/drivers/audio/audio_pipe.h index 3ae3bc8498..6c4719d56d 100644 --- a/components/drivers/audio/audio_pipe.h +++ b/components/drivers/audio/audio_pipe.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/can/can.c b/components/drivers/can/can.c index 9f4612355b..55444c3a0e 100644 --- a/components/drivers/can/can.c +++ b/components/drivers/can/can.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/cputime/cputime.c b/components/drivers/cputime/cputime.c index 3ec860d5c5..4a9eee3a71 100644 --- a/components/drivers/cputime/cputime.c +++ b/components/drivers/cputime/cputime.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,7 +14,7 @@ static const struct rt_clock_cputime_ops *_cputime_ops = RT_NULL; /** - * The clock_cpu_getres() function shall return the resolution of CPU time, the + * The clock_cpu_getres() function shall return the resolution of CPU time, the * number of nanosecond per tick. * * @return the number of nanosecond per tick @@ -43,7 +43,7 @@ uint32_t clock_cpu_gettime(void) } /** - * The clock_cpu_microsecond() fucntion shall return the microsecond according to + * The clock_cpu_microsecond() fucntion shall return the microsecond according to * cpu_tick parameter. * * @param cpu_tick the cpu tick @@ -58,7 +58,7 @@ uint32_t clock_cpu_microsecond(uint32_t cpu_tick) } /** - * The clock_cpu_microsecond() fucntion shall return the millisecond according to + * The clock_cpu_microsecond() fucntion shall return the millisecond according to * cpu_tick parameter. * * @param cpu_tick the cpu tick @@ -74,7 +74,7 @@ uint32_t clock_cpu_millisecond(uint32_t cpu_tick) /** * The clock_cpu_seops() function shall set the ops of cpu time. - * + * * @return always return 0. */ int clock_cpu_setops(const struct rt_clock_cputime_ops *ops) diff --git a/components/drivers/cputime/cputime_cortexm.c b/components/drivers/cputime/cputime_cortexm.c index 05ed6ed447..071acfe9bb 100644 --- a/components/drivers/cputime/cputime_cortexm.c +++ b/components/drivers/cputime/cputime_cortexm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -19,7 +19,7 @@ static float cortexm_cputime_getres(void) { float ret = 1000 * 1000 * 1000; - + ret = ret / SystemCoreClock; return ret; } @@ -29,7 +29,7 @@ static uint32_t cortexm_cputime_gettime(void) return DWT->CYCCNT; } -const static struct rt_clock_cputime_ops _cortexm_ops = +const static struct rt_clock_cputime_ops _cortexm_ops = { cortexm_cputime_getres, cortexm_cputime_gettime @@ -38,13 +38,13 @@ const static struct rt_clock_cputime_ops _cortexm_ops = int cortexm_cputime_init(void) { /* check support bit */ - if ((DWT->CTRL & (1UL << DWT_CTRL_NOCYCCNT_Pos)) == 0) + if ((DWT->CTRL & (1UL << DWT_CTRL_NOCYCCNT_Pos)) == 0) { /* enable trace*/ CoreDebug->DEMCR |= (1UL << CoreDebug_DEMCR_TRCENA_Pos); - + /* whether cycle counter not enabled */ - if ((DWT->CTRL & (1UL << DWT_CTRL_CYCCNTENA_Pos)) == 0) + if ((DWT->CTRL & (1UL << DWT_CTRL_CYCCNTENA_Pos)) == 0) { /* enable cycle counter */ DWT->CTRL |= (1UL << DWT_CTRL_CYCCNTENA_Pos); diff --git a/components/drivers/hwcrypto/hw_bignum.c b/components/drivers/hwcrypto/hw_bignum.c index 88813566b1..0488a16f08 100644 --- a/components/drivers/hwcrypto/hw_bignum.c +++ b/components/drivers/hwcrypto/hw_bignum.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -56,7 +56,7 @@ rt_err_t rt_hwcrypto_bignum_default(struct rt_hwcrypto_device *device) /** * @brief Init bignum obj - * + * * @param n bignum obj */ void rt_hwcrypto_bignum_init(struct hw_bignum_mpi *n) @@ -87,9 +87,9 @@ void rt_hwcrypto_bignum_free(struct hw_bignum_mpi *n) /** * @brief Get length of bignum as an unsigned binary buffer - * + * * @param n bignum obj - * + * * @return binary buffer length */ int rt_hwcrypto_bignum_get_len(const struct hw_bignum_mpi *n) @@ -112,11 +112,11 @@ int rt_hwcrypto_bignum_get_len(const struct hw_bignum_mpi *n) /** * @brief Export n into unsigned binary data, big endian - * + * * @param n bignum obj * @param buf Buffer for the binary number * @param len Length of the buffer - * + * * @return export bin length */ int rt_hwcrypto_bignum_export_bin(struct hw_bignum_mpi *n, rt_uint8_t *buf, int len) @@ -139,11 +139,11 @@ int rt_hwcrypto_bignum_export_bin(struct hw_bignum_mpi *n, rt_uint8_t *buf, int /** * @brief Import n from unsigned binary data, big endian - * + * * @param n bignum obj * @param buf Buffer for the binary number * @param len Length of the buffer - * + * * @return RT_EOK on success. */ rt_err_t rt_hwcrypto_bignum_import_bin(struct hw_bignum_mpi *n, rt_uint8_t *buf, int len) @@ -179,11 +179,11 @@ rt_err_t rt_hwcrypto_bignum_import_bin(struct hw_bignum_mpi *n, rt_uint8_t *buf, /** * @brief x = a + b - * + * * @param a bignum obj * @param b bignum obj * @param c bignum obj - * + * * @return RT_EOK on success. */ rt_err_t rt_hwcrypto_bignum_add(struct hw_bignum_mpi *x, @@ -206,11 +206,11 @@ rt_err_t rt_hwcrypto_bignum_add(struct hw_bignum_mpi *x, /** * @brief x = a - b - * + * * @param a bignum obj * @param b bignum obj * @param c bignum obj - * + * * @return RT_EOK on success. */ rt_err_t rt_hwcrypto_bignum_sub(struct hw_bignum_mpi *x, @@ -233,11 +233,11 @@ rt_err_t rt_hwcrypto_bignum_sub(struct hw_bignum_mpi *x, /** * @brief x = a * b - * + * * @param a bignum obj * @param b bignum obj * @param c bignum obj - * + * * @return RT_EOK on success. */ rt_err_t rt_hwcrypto_bignum_mul(struct hw_bignum_mpi *x, @@ -260,11 +260,11 @@ rt_err_t rt_hwcrypto_bignum_mul(struct hw_bignum_mpi *x, /** * @brief x = a * b (mod c) - * + * * @param a bignum obj * @param b bignum obj * @param c bignum obj - * + * * @return RT_EOK on success. */ rt_err_t rt_hwcrypto_bignum_mulmod(struct hw_bignum_mpi *x, @@ -288,11 +288,11 @@ rt_err_t rt_hwcrypto_bignum_mulmod(struct hw_bignum_mpi *x, /** * @brief x = a ^ b (mod c) - * + * * @param a bignum obj * @param b bignum obj * @param c bignum obj - * + * * @return RT_EOK on success. */ rt_err_t rt_hwcrypto_bignum_exptmod(struct hw_bignum_mpi *x, diff --git a/components/drivers/hwcrypto/hw_bignum.h b/components/drivers/hwcrypto/hw_bignum.h index a1f567e68f..442b28f558 100644 --- a/components/drivers/hwcrypto/hw_bignum.h +++ b/components/drivers/hwcrypto/hw_bignum.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -83,42 +83,42 @@ void rt_hwcrypto_bignum_free(struct hw_bignum_mpi *n); /** * @brief Get length of bignum as an unsigned binary buffer - * + * * @param n bignum obj - * + * * @return binary buffer Length */ int rt_hwcrypto_bignum_get_len(const struct hw_bignum_mpi *n); /** * @brief Export n into unsigned binary data, big endian - * + * * @param n bignum obj * @param buf Buffer for the binary number * @param len Length of the buffer - * + * * @return export bin length */ int rt_hwcrypto_bignum_export_bin(struct hw_bignum_mpi *n, rt_uint8_t *buf, int len); /** * @brief Import n from unsigned binary data, big endian - * + * * @param n bignum obj * @param buf Buffer for the binary number * @param len Length of the buffer - * + * * @return RT_EOK on success. */ rt_err_t rt_hwcrypto_bignum_import_bin(struct hw_bignum_mpi *n, rt_uint8_t *buf, int len); /** * @brief x = a + b - * + * * @param a bignum obj * @param b bignum obj * @param c bignum obj - * + * * @return RT_EOK on success. */ rt_err_t rt_hwcrypto_bignum_add(struct hw_bignum_mpi *x, @@ -127,11 +127,11 @@ rt_err_t rt_hwcrypto_bignum_add(struct hw_bignum_mpi *x, /** * @brief x = a - b - * + * * @param a bignum obj * @param b bignum obj * @param c bignum obj - * + * * @return RT_EOK on success. */ rt_err_t rt_hwcrypto_bignum_sub(struct hw_bignum_mpi *x, @@ -140,11 +140,11 @@ rt_err_t rt_hwcrypto_bignum_sub(struct hw_bignum_mpi *x, /** * @brief x = a * b - * + * * @param a bignum obj * @param b bignum obj * @param c bignum obj - * + * * @return RT_EOK on success. */ rt_err_t rt_hwcrypto_bignum_mul(struct hw_bignum_mpi *x, @@ -153,11 +153,11 @@ rt_err_t rt_hwcrypto_bignum_mul(struct hw_bignum_mpi *x, /** * @brief x = a * b (mod c) - * + * * @param a bignum obj * @param b bignum obj * @param c bignum obj - * + * * @return RT_EOK on success. */ rt_err_t rt_hwcrypto_bignum_mulmod(struct hw_bignum_mpi *x, @@ -167,11 +167,11 @@ rt_err_t rt_hwcrypto_bignum_mulmod(struct hw_bignum_mpi *x, /** * @brief x = a ^ b (mod c) - * + * * @param a bignum obj * @param b bignum obj * @param c bignum obj - * + * * @return RT_EOK on success. */ rt_err_t rt_hwcrypto_bignum_exptmod(struct hw_bignum_mpi *x, diff --git a/components/drivers/hwcrypto/hw_crc.c b/components/drivers/hwcrypto/hw_crc.c index 20579711e2..a1d95793e2 100644 --- a/components/drivers/hwcrypto/hw_crc.c +++ b/components/drivers/hwcrypto/hw_crc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,7 +20,7 @@ * * @return CRC context */ -struct rt_hwcrypto_ctx *rt_hwcrypto_crc_create(struct rt_hwcrypto_device *device, +struct rt_hwcrypto_ctx *rt_hwcrypto_crc_create(struct rt_hwcrypto_device *device, hwcrypto_crc_mode mode) { struct hwcrypto_crc *crc_ctx; @@ -89,8 +89,8 @@ void rt_hwcrypto_crc_destroy(struct rt_hwcrypto_ctx *ctx) * * @return RT_EOK on success. */ -rt_uint32_t rt_hwcrypto_crc_update(struct rt_hwcrypto_ctx *ctx, - const rt_uint8_t *input, +rt_uint32_t rt_hwcrypto_crc_update(struct rt_hwcrypto_ctx *ctx, + const rt_uint8_t *input, rt_size_t length) { struct hwcrypto_crc *crc_ctx = (struct hwcrypto_crc *)ctx; @@ -107,7 +107,7 @@ rt_uint32_t rt_hwcrypto_crc_update(struct rt_hwcrypto_ctx *ctx, * @param ctx CRC context * @param cfg CRC config */ -void rt_hwcrypto_crc_cfg(struct rt_hwcrypto_ctx *ctx, +void rt_hwcrypto_crc_cfg(struct rt_hwcrypto_ctx *ctx, struct hwcrypto_crc_cfg *cfg) { if (cfg) diff --git a/components/drivers/hwcrypto/hw_crc.h b/components/drivers/hwcrypto/hw_crc.h index a6df92a2ef..8e0fcefccf 100644 --- a/components/drivers/hwcrypto/hw_crc.h +++ b/components/drivers/hwcrypto/hw_crc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -129,7 +129,7 @@ void rt_hwcrypto_crc_destroy(struct rt_hwcrypto_ctx *ctx); * * @return CRC value */ -rt_uint32_t rt_hwcrypto_crc_update(struct rt_hwcrypto_ctx *ctx, +rt_uint32_t rt_hwcrypto_crc_update(struct rt_hwcrypto_ctx *ctx, const rt_uint8_t *input, rt_size_t length); /** @@ -138,7 +138,7 @@ rt_uint32_t rt_hwcrypto_crc_update(struct rt_hwcrypto_ctx *ctx, * @param ctx CRC context * @param cfg CRC config */ -void rt_hwcrypto_crc_cfg(struct rt_hwcrypto_ctx *ctx, +void rt_hwcrypto_crc_cfg(struct rt_hwcrypto_ctx *ctx, struct hwcrypto_crc_cfg *cfg); #ifdef __cplusplus diff --git a/components/drivers/hwcrypto/hw_gcm.c b/components/drivers/hwcrypto/hw_gcm.c index 8d0f49149a..a8106694f9 100644 --- a/components/drivers/hwcrypto/hw_gcm.c +++ b/components/drivers/hwcrypto/hw_gcm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/hwcrypto/hw_gcm.h b/components/drivers/hwcrypto/hw_gcm.h index a73b2b0634..3a2f87bc30 100644 --- a/components/drivers/hwcrypto/hw_gcm.h +++ b/components/drivers/hwcrypto/hw_gcm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/hwcrypto/hw_hash.c b/components/drivers/hwcrypto/hw_hash.c index b20069ac0e..cf5ec8d70a 100644 --- a/components/drivers/hwcrypto/hw_hash.c +++ b/components/drivers/hwcrypto/hw_hash.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/hwcrypto/hw_hash.h b/components/drivers/hwcrypto/hw_hash.h index de0310e84c..41abd06c4c 100644 --- a/components/drivers/hwcrypto/hw_hash.h +++ b/components/drivers/hwcrypto/hw_hash.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/hwcrypto/hw_rng.c b/components/drivers/hwcrypto/hw_rng.c index 13a17cc6be..b6f62db347 100644 --- a/components/drivers/hwcrypto/hw_rng.c +++ b/components/drivers/hwcrypto/hw_rng.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -81,7 +81,7 @@ rt_err_t rt_hwcrypto_rng_default(struct rt_hwcrypto_device *device) * @brief Getting Random Numbers from RNG Context * * @param ctx RNG context - * + * * @return Random number */ rt_uint32_t rt_hwcrypto_rng_update_ctx(struct rt_hwcrypto_ctx *ctx) diff --git a/components/drivers/hwcrypto/hw_rng.h b/components/drivers/hwcrypto/hw_rng.h index fc28afdb1e..3c014f6bee 100644 --- a/components/drivers/hwcrypto/hw_rng.h +++ b/components/drivers/hwcrypto/hw_rng.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -60,7 +60,7 @@ rt_err_t rt_hwcrypto_rng_default(struct rt_hwcrypto_device *device); * @brief Getting Random Numbers from RNG Context * * @param ctx RNG context - * + * * @return Random number */ rt_uint32_t rt_hwcrypto_rng_update_ctx(struct rt_hwcrypto_ctx *ctx); diff --git a/components/drivers/hwcrypto/hw_symmetric.c b/components/drivers/hwcrypto/hw_symmetric.c index 789c5c1a2c..9398298fed 100644 --- a/components/drivers/hwcrypto/hw_symmetric.c +++ b/components/drivers/hwcrypto/hw_symmetric.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -215,7 +215,7 @@ void rt_hwcrypto_symmetric_get_ivoff(struct rt_hwcrypto_ctx *ctx, rt_int32_t *iv * * @param des The destination symmetric crypto context * @param src The symmetric crypto context to be copy - * + * * @return RT_EOK on success. */ rt_err_t rt_hwcrypto_symmetric_cpy(struct rt_hwcrypto_ctx *des, const struct rt_hwcrypto_ctx *src) diff --git a/components/drivers/hwcrypto/hw_symmetric.h b/components/drivers/hwcrypto/hw_symmetric.h index 12f4dbec30..f3f78fb21c 100644 --- a/components/drivers/hwcrypto/hw_symmetric.h +++ b/components/drivers/hwcrypto/hw_symmetric.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/hwcrypto/hwcrypto.c b/components/drivers/hwcrypto/hwcrypto.c index bbe1ff63fb..473b52fb9a 100644 --- a/components/drivers/hwcrypto/hwcrypto.c +++ b/components/drivers/hwcrypto/hwcrypto.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/hwcrypto/hwcrypto.h b/components/drivers/hwcrypto/hwcrypto.h index a428f4437d..cdf057c49d 100644 --- a/components/drivers/hwcrypto/hwcrypto.h +++ b/components/drivers/hwcrypto/hwcrypto.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/hwtimer/hwtimer.c b/components/drivers/hwtimer/hwtimer.c index 976d8bbf32..49a57be9af 100644 --- a/components/drivers/hwtimer/hwtimer.c +++ b/components/drivers/hwtimer/hwtimer.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -325,7 +325,7 @@ void rt_device_hwtimer_isr(rt_hwtimer_t *timer) } #ifdef RT_USING_DEVICE_OPS -const static struct rt_device_ops hwtimer_ops = +const static struct rt_device_ops hwtimer_ops = { rt_hwtimer_init, rt_hwtimer_open, diff --git a/components/drivers/i2c/i2c-bit-ops.c b/components/drivers/i2c/i2c-bit-ops.c index 96af567a1e..7e55f6da44 100644 --- a/components/drivers/i2c/i2c-bit-ops.c +++ b/components/drivers/i2c/i2c-bit-ops.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/i2c/i2c_core.c b/components/drivers/i2c/i2c_core.c index f358c2b758..87178e37d5 100644 --- a/components/drivers/i2c/i2c_core.c +++ b/components/drivers/i2c/i2c_core.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/i2c/i2c_dev.c b/components/drivers/i2c/i2c_dev.c index 59f728be09..4f567f8227 100644 --- a/components/drivers/i2c/i2c_dev.c +++ b/components/drivers/i2c/i2c_dev.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -97,9 +97,9 @@ static rt_err_t i2c_bus_device_control(rt_device_t dev, } #ifdef RT_USING_DEVICE_OPS -const static struct rt_device_ops i2c_ops = +const static struct rt_device_ops i2c_ops = { - RT_NULL, + RT_NULL, RT_NULL, RT_NULL, i2c_bus_device_read, diff --git a/components/drivers/include/drivers/adc.h b/components/drivers/include/drivers/adc.h index 8e3498e791..e2ce087fb9 100644 --- a/components/drivers/include/drivers/adc.h +++ b/components/drivers/include/drivers/adc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/include/drivers/alarm.h b/components/drivers/include/drivers/alarm.h index e59c4142c7..11637df949 100644 --- a/components/drivers/include/drivers/alarm.h +++ b/components/drivers/include/drivers/alarm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/include/drivers/audio.h b/components/drivers/include/drivers/audio.h index 86057e7626..45c31be2f3 100644 --- a/components/drivers/include/drivers/audio.h +++ b/components/drivers/include/drivers/audio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/include/drivers/can.h b/components/drivers/include/drivers/can.h index d4fcc845b4..bb05317d4f 100644 --- a/components/drivers/include/drivers/can.h +++ b/components/drivers/include/drivers/can.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/include/drivers/cputime.h b/components/drivers/include/drivers/cputime.h index 78c22fc1da..0141f24805 100644 --- a/components/drivers/include/drivers/cputime.h +++ b/components/drivers/include/drivers/cputime.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/include/drivers/crypto.h b/components/drivers/include/drivers/crypto.h index 5341d9ee48..8270a78b09 100644 --- a/components/drivers/include/drivers/crypto.h +++ b/components/drivers/include/drivers/crypto.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/include/drivers/hwtimer.h b/components/drivers/include/drivers/hwtimer.h index cbfeec2bf8..0bf4893790 100644 --- a/components/drivers/include/drivers/hwtimer.h +++ b/components/drivers/include/drivers/hwtimer.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -70,7 +70,7 @@ typedef struct rt_hwtimer_device rt_int32_t freq; /* counting frequency set by the user */ rt_int32_t overflow; /* timer overflows */ - float period_sec; + float period_sec; rt_int32_t cycles; /* how many times will generate a timeout event after overflow */ rt_int32_t reload; /* reload cycles(using in period mode) */ rt_hwtimer_mode_t mode; /* timing mode(oneshot/period) */ diff --git a/components/drivers/include/drivers/i2c-bit-ops.h b/components/drivers/include/drivers/i2c-bit-ops.h index ddf9a36d73..0d94de114a 100644 --- a/components/drivers/include/drivers/i2c-bit-ops.h +++ b/components/drivers/include/drivers/i2c-bit-ops.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/include/drivers/i2c.h b/components/drivers/include/drivers/i2c.h index d93e82fc2b..50ce021d53 100644 --- a/components/drivers/include/drivers/i2c.h +++ b/components/drivers/include/drivers/i2c.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/include/drivers/i2c_dev.h b/components/drivers/include/drivers/i2c_dev.h index 5ef9dd1a8c..94f110c055 100644 --- a/components/drivers/include/drivers/i2c_dev.h +++ b/components/drivers/include/drivers/i2c_dev.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/include/drivers/mmc.h b/components/drivers/include/drivers/mmc.h index 95dce7178a..d472bbbc5d 100644 --- a/components/drivers/include/drivers/mmc.h +++ b/components/drivers/include/drivers/mmc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,163 +22,163 @@ extern "C" { * EXT_CSD fields */ -#define EXT_CSD_FLUSH_CACHE 32 /* W */ -#define EXT_CSD_CACHE_CTRL 33 /* R/W */ -#define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W */ -#define EXT_CSD_PACKED_FAILURE_INDEX 35 /* RO */ -#define EXT_CSD_PACKED_CMD_STATUS 36 /* RO */ -#define EXT_CSD_EXP_EVENTS_STATUS 54 /* RO, 2 bytes */ -#define EXT_CSD_EXP_EVENTS_CTRL 56 /* R/W, 2 bytes */ -#define EXT_CSD_DATA_SECTOR_SIZE 61 /* R */ -#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */ -#define EXT_CSD_PARTITION_ATTRIBUTE 156 /* R/W */ -#define EXT_CSD_PARTITION_SUPPORT 160 /* RO */ -#define EXT_CSD_HPI_MGMT 161 /* R/W */ -#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */ -#define EXT_CSD_BKOPS_EN 163 /* R/W */ -#define EXT_CSD_BKOPS_START 164 /* W */ -#define EXT_CSD_SANITIZE_START 165 /* W */ -#define EXT_CSD_WR_REL_PARAM 166 /* RO */ -#define EXT_CSD_RPMB_MULT 168 /* RO */ -#define EXT_CSD_BOOT_WP 173 /* R/W */ -#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */ -#define EXT_CSD_PART_CONFIG 179 /* R/W */ -#define EXT_CSD_ERASED_MEM_CONT 181 /* RO */ -#define EXT_CSD_BUS_WIDTH 183 /* R/W */ -#define EXT_CSD_HS_TIMING 185 /* R/W */ -#define EXT_CSD_POWER_CLASS 187 /* R/W */ -#define EXT_CSD_REV 192 /* RO */ -#define EXT_CSD_STRUCTURE 194 /* RO */ -#define EXT_CSD_CARD_TYPE 196 /* RO */ -#define EXT_CSD_OUT_OF_INTERRUPT_TIME 198 /* RO */ +#define EXT_CSD_FLUSH_CACHE 32 /* W */ +#define EXT_CSD_CACHE_CTRL 33 /* R/W */ +#define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W */ +#define EXT_CSD_PACKED_FAILURE_INDEX 35 /* RO */ +#define EXT_CSD_PACKED_CMD_STATUS 36 /* RO */ +#define EXT_CSD_EXP_EVENTS_STATUS 54 /* RO, 2 bytes */ +#define EXT_CSD_EXP_EVENTS_CTRL 56 /* R/W, 2 bytes */ +#define EXT_CSD_DATA_SECTOR_SIZE 61 /* R */ +#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */ +#define EXT_CSD_PARTITION_ATTRIBUTE 156 /* R/W */ +#define EXT_CSD_PARTITION_SUPPORT 160 /* RO */ +#define EXT_CSD_HPI_MGMT 161 /* R/W */ +#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */ +#define EXT_CSD_BKOPS_EN 163 /* R/W */ +#define EXT_CSD_BKOPS_START 164 /* W */ +#define EXT_CSD_SANITIZE_START 165 /* W */ +#define EXT_CSD_WR_REL_PARAM 166 /* RO */ +#define EXT_CSD_RPMB_MULT 168 /* RO */ +#define EXT_CSD_BOOT_WP 173 /* R/W */ +#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */ +#define EXT_CSD_PART_CONFIG 179 /* R/W */ +#define EXT_CSD_ERASED_MEM_CONT 181 /* RO */ +#define EXT_CSD_BUS_WIDTH 183 /* R/W */ +#define EXT_CSD_HS_TIMING 185 /* R/W */ +#define EXT_CSD_POWER_CLASS 187 /* R/W */ +#define EXT_CSD_REV 192 /* RO */ +#define EXT_CSD_STRUCTURE 194 /* RO */ +#define EXT_CSD_CARD_TYPE 196 /* RO */ +#define EXT_CSD_OUT_OF_INTERRUPT_TIME 198 /* RO */ #define EXT_CSD_PART_SWITCH_TIME 199 /* RO */ -#define EXT_CSD_PWR_CL_52_195 200 /* RO */ -#define EXT_CSD_PWR_CL_26_195 201 /* RO */ -#define EXT_CSD_PWR_CL_52_360 202 /* RO */ -#define EXT_CSD_PWR_CL_26_360 203 /* RO */ -#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ -#define EXT_CSD_S_A_TIMEOUT 217 /* RO */ -#define EXT_CSD_REL_WR_SEC_C 222 /* RO */ -#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */ -#define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */ -#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ -#define EXT_CSD_BOOT_MULT 226 /* RO */ -#define EXT_CSD_SEC_TRIM_MULT 229 /* RO */ -#define EXT_CSD_SEC_ERASE_MULT 230 /* RO */ -#define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */ -#define EXT_CSD_TRIM_MULT 232 /* RO */ -#define EXT_CSD_PWR_CL_200_195 236 /* RO */ -#define EXT_CSD_PWR_CL_200_360 237 /* RO */ -#define EXT_CSD_PWR_CL_DDR_52_195 238 /* RO */ -#define EXT_CSD_PWR_CL_DDR_52_360 239 /* RO */ -#define EXT_CSD_BKOPS_STATUS 246 /* RO */ -#define EXT_CSD_POWER_OFF_LONG_TIME 247 /* RO */ -#define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */ -#define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */ -#define EXT_CSD_PWR_CL_DDR_200_360 253 /* RO */ -#define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */ -#define EXT_CSD_DATA_TAG_SUPPORT 499 /* RO */ -#define EXT_CSD_MAX_PACKED_WRITES 500 /* RO */ -#define EXT_CSD_MAX_PACKED_READS 501 /* RO */ -#define EXT_CSD_BKOPS_SUPPORT 502 /* RO */ -#define EXT_CSD_HPI_FEATURES 503 /* RO */ +#define EXT_CSD_PWR_CL_52_195 200 /* RO */ +#define EXT_CSD_PWR_CL_26_195 201 /* RO */ +#define EXT_CSD_PWR_CL_52_360 202 /* RO */ +#define EXT_CSD_PWR_CL_26_360 203 /* RO */ +#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ +#define EXT_CSD_S_A_TIMEOUT 217 /* RO */ +#define EXT_CSD_REL_WR_SEC_C 222 /* RO */ +#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */ +#define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */ +#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ +#define EXT_CSD_BOOT_MULT 226 /* RO */ +#define EXT_CSD_SEC_TRIM_MULT 229 /* RO */ +#define EXT_CSD_SEC_ERASE_MULT 230 /* RO */ +#define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */ +#define EXT_CSD_TRIM_MULT 232 /* RO */ +#define EXT_CSD_PWR_CL_200_195 236 /* RO */ +#define EXT_CSD_PWR_CL_200_360 237 /* RO */ +#define EXT_CSD_PWR_CL_DDR_52_195 238 /* RO */ +#define EXT_CSD_PWR_CL_DDR_52_360 239 /* RO */ +#define EXT_CSD_BKOPS_STATUS 246 /* RO */ +#define EXT_CSD_POWER_OFF_LONG_TIME 247 /* RO */ +#define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */ +#define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */ +#define EXT_CSD_PWR_CL_DDR_200_360 253 /* RO */ +#define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */ +#define EXT_CSD_DATA_TAG_SUPPORT 499 /* RO */ +#define EXT_CSD_MAX_PACKED_WRITES 500 /* RO */ +#define EXT_CSD_MAX_PACKED_READS 501 /* RO */ +#define EXT_CSD_BKOPS_SUPPORT 502 /* RO */ +#define EXT_CSD_HPI_FEATURES 503 /* RO */ /* * EXT_CSD field definitions */ -#define EXT_CSD_WR_REL_PARAM_EN (1<<2) +#define EXT_CSD_WR_REL_PARAM_EN (1<<2) -#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40) -#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10) -#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04) -#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01) +#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40) +#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10) +#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04) +#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01) -#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7) -#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1) -#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3) -#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4) +#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7) +#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1) +#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3) +#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4) -#define EXT_CSD_PART_SUPPORT_PART_EN (0x1) +#define EXT_CSD_PART_SUPPORT_PART_EN (0x1) -#define EXT_CSD_CMD_SET_NORMAL (1<<0) -#define EXT_CSD_CMD_SET_SECURE (1<<1) -#define EXT_CSD_CMD_SET_CPSECURE (1<<2) +#define EXT_CSD_CMD_SET_NORMAL (1<<0) +#define EXT_CSD_CMD_SET_SECURE (1<<1) +#define EXT_CSD_CMD_SET_CPSECURE (1<<2) -#define EXT_CSD_CARD_TYPE_HS_26 (1<<0) /* Card can run at 26MHz */ -#define EXT_CSD_CARD_TYPE_HS_52 (1<<1) /* Card can run at 52MHz */ -#define EXT_CSD_CARD_TYPE_HS (EXT_CSD_CARD_TYPE_HS_26 | \ +#define EXT_CSD_CARD_TYPE_HS_26 (1<<0) /* Card can run at 26MHz */ +#define EXT_CSD_CARD_TYPE_HS_52 (1<<1) /* Card can run at 52MHz */ +#define EXT_CSD_CARD_TYPE_HS (EXT_CSD_CARD_TYPE_HS_26 | \ EXT_CSD_CARD_TYPE_HS_52) #define EXT_CSD_CARD_TYPE_DDR_1_8V (1<<2) /* Card can run at 52MHz */ /* DDR mode @1.8V or 3V I/O */ #define EXT_CSD_CARD_TYPE_DDR_1_2V (1<<3) /* Card can run at 52MHz */ - /* DDR mode @1.2V I/O */ + /* DDR mode @1.2V I/O */ #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ | EXT_CSD_CARD_TYPE_DDR_1_2V) -#define EXT_CSD_CARD_TYPE_HS200_1_8V (1<<4) /* Card can run at 200MHz */ -#define EXT_CSD_CARD_TYPE_HS200_1_2V (1<<5) /* Card can run at 200MHz */ - /* SDR mode @1.2V I/O */ -#define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \ - EXT_CSD_CARD_TYPE_HS200_1_2V) -#define EXT_CSD_CARD_TYPE_HS400_1_8V (1<<6) /* Card can run at 200MHz DDR, 1.8V */ -#define EXT_CSD_CARD_TYPE_HS400_1_2V (1<<7) /* Card can run at 200MHz DDR, 1.2V */ -#define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \ - EXT_CSD_CARD_TYPE_HS400_1_2V) - -#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ -#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ -#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ -#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */ -#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */ - -#define EXT_CSD_TIMING_BC 0 /* Backwards compatility */ -#define EXT_CSD_TIMING_HS 1 /* High speed */ -#define EXT_CSD_TIMING_HS200 2 /* HS200 */ -#define EXT_CSD_TIMING_HS400 3 /* HS400 */ - -#define EXT_CSD_SEC_ER_EN BIT(0) -#define EXT_CSD_SEC_BD_BLK_EN BIT(2) -#define EXT_CSD_SEC_GB_CL_EN BIT(4) -#define EXT_CSD_SEC_SANITIZE BIT(6) /* v4.5 only */ - -#define EXT_CSD_RST_N_EN_MASK 0x3 -#define EXT_CSD_RST_N_ENABLED 1 /* RST_n is enabled on card */ - -#define EXT_CSD_NO_POWER_NOTIFICATION 0 -#define EXT_CSD_POWER_ON 1 -#define EXT_CSD_POWER_OFF_SHORT 2 -#define EXT_CSD_POWER_OFF_LONG 3 - -#define EXT_CSD_PWR_CL_8BIT_MASK 0xF0 /* 8 bit PWR CLS */ -#define EXT_CSD_PWR_CL_4BIT_MASK 0x0F /* 8 bit PWR CLS */ -#define EXT_CSD_PWR_CL_8BIT_SHIFT 4 -#define EXT_CSD_PWR_CL_4BIT_SHIFT 0 - -#define EXT_CSD_PACKED_EVENT_EN BIT(3) +#define EXT_CSD_CARD_TYPE_HS200_1_8V (1<<4) /* Card can run at 200MHz */ +#define EXT_CSD_CARD_TYPE_HS200_1_2V (1<<5) /* Card can run at 200MHz */ + /* SDR mode @1.2V I/O */ +#define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \ + EXT_CSD_CARD_TYPE_HS200_1_2V) +#define EXT_CSD_CARD_TYPE_HS400_1_8V (1<<6) /* Card can run at 200MHz DDR, 1.8V */ +#define EXT_CSD_CARD_TYPE_HS400_1_2V (1<<7) /* Card can run at 200MHz DDR, 1.2V */ +#define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \ + EXT_CSD_CARD_TYPE_HS400_1_2V) + +#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ +#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ +#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ +#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */ +#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */ + +#define EXT_CSD_TIMING_BC 0 /* Backwards compatility */ +#define EXT_CSD_TIMING_HS 1 /* High speed */ +#define EXT_CSD_TIMING_HS200 2 /* HS200 */ +#define EXT_CSD_TIMING_HS400 3 /* HS400 */ + +#define EXT_CSD_SEC_ER_EN BIT(0) +#define EXT_CSD_SEC_BD_BLK_EN BIT(2) +#define EXT_CSD_SEC_GB_CL_EN BIT(4) +#define EXT_CSD_SEC_SANITIZE BIT(6) /* v4.5 only */ + +#define EXT_CSD_RST_N_EN_MASK 0x3 +#define EXT_CSD_RST_N_ENABLED 1 /* RST_n is enabled on card */ + +#define EXT_CSD_NO_POWER_NOTIFICATION 0 +#define EXT_CSD_POWER_ON 1 +#define EXT_CSD_POWER_OFF_SHORT 2 +#define EXT_CSD_POWER_OFF_LONG 3 + +#define EXT_CSD_PWR_CL_8BIT_MASK 0xF0 /* 8 bit PWR CLS */ +#define EXT_CSD_PWR_CL_4BIT_MASK 0x0F /* 8 bit PWR CLS */ +#define EXT_CSD_PWR_CL_8BIT_SHIFT 4 +#define EXT_CSD_PWR_CL_4BIT_SHIFT 0 + +#define EXT_CSD_PACKED_EVENT_EN BIT(3) /* * EXCEPTION_EVENT_STATUS field */ -#define EXT_CSD_URGENT_BKOPS BIT(0) -#define EXT_CSD_DYNCAP_NEEDED BIT(1) -#define EXT_CSD_SYSPOOL_EXHAUSTED BIT(2) -#define EXT_CSD_PACKED_FAILURE BIT(3) +#define EXT_CSD_URGENT_BKOPS BIT(0) +#define EXT_CSD_DYNCAP_NEEDED BIT(1) +#define EXT_CSD_SYSPOOL_EXHAUSTED BIT(2) +#define EXT_CSD_PACKED_FAILURE BIT(3) -#define EXT_CSD_PACKED_GENERIC_ERROR BIT(0) -#define EXT_CSD_PACKED_INDEXED_ERROR BIT(1) +#define EXT_CSD_PACKED_GENERIC_ERROR BIT(0) +#define EXT_CSD_PACKED_INDEXED_ERROR BIT(1) /* * BKOPS status level */ -#define EXT_CSD_BKOPS_LEVEL_2 0x2 +#define EXT_CSD_BKOPS_LEVEL_2 0x2 /* * MMC_SWITCH access modes */ -#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ -#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits which are 1 in value */ -#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits which are 1 in value */ -#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */ - +#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ +#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits which are 1 in value */ +#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits which are 1 in value */ +#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */ + /* * extern function */ diff --git a/components/drivers/include/drivers/mmcsd_card.h b/components/drivers/include/drivers/mmcsd_card.h index 3ee5a20465..511cc1167d 100644 --- a/components/drivers/include/drivers/mmcsd_card.h +++ b/components/drivers/include/drivers/mmcsd_card.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-07-25 weety first version + * Date Author Notes + * 2011-07-25 weety first version */ #ifndef __MMCSD_CARD_H__ @@ -17,87 +17,87 @@ extern "C" { #endif -#define SD_SCR_BUS_WIDTH_1 (1 << 0) -#define SD_SCR_BUS_WIDTH_4 (1 << 2) +#define SD_SCR_BUS_WIDTH_1 (1 << 0) +#define SD_SCR_BUS_WIDTH_4 (1 << 2) struct rt_mmcsd_cid { - rt_uint8_t mid; /* ManufacturerID */ - rt_uint8_t prv; /* Product Revision */ - rt_uint16_t oid; /* OEM/Application ID */ - rt_uint32_t psn; /* Product Serial Number */ - rt_uint8_t pnm[5]; /* Product Name */ - rt_uint8_t reserved1;/* reserved */ - rt_uint16_t mdt; /* Manufacturing Date */ - rt_uint8_t crc; /* CID CRC */ - rt_uint8_t reserved2;/* not used, always 1 */ + rt_uint8_t mid; /* ManufacturerID */ + rt_uint8_t prv; /* Product Revision */ + rt_uint16_t oid; /* OEM/Application ID */ + rt_uint32_t psn; /* Product Serial Number */ + rt_uint8_t pnm[5]; /* Product Name */ + rt_uint8_t reserved1;/* reserved */ + rt_uint16_t mdt; /* Manufacturing Date */ + rt_uint8_t crc; /* CID CRC */ + rt_uint8_t reserved2;/* not used, always 1 */ }; struct rt_mmcsd_csd { - rt_uint8_t csd_structure; /* CSD register version */ - rt_uint8_t taac; - rt_uint8_t nsac; - rt_uint8_t tran_speed; /* max data transfer rate */ - rt_uint16_t card_cmd_class; /* card command classes */ - rt_uint8_t rd_blk_len; /* max read data block length */ - rt_uint8_t rd_blk_part; - rt_uint8_t wr_blk_misalign; - rt_uint8_t rd_blk_misalign; - rt_uint8_t dsr_imp; /* DSR implemented */ - rt_uint8_t c_size_mult; /* CSD 1.0 , device size multiplier */ - rt_uint32_t c_size; /* device size */ - rt_uint8_t r2w_factor; - rt_uint8_t wr_blk_len; /* max wtire data block length */ - rt_uint8_t wr_blk_partial; - rt_uint8_t csd_crc; - + rt_uint8_t csd_structure; /* CSD register version */ + rt_uint8_t taac; + rt_uint8_t nsac; + rt_uint8_t tran_speed; /* max data transfer rate */ + rt_uint16_t card_cmd_class; /* card command classes */ + rt_uint8_t rd_blk_len; /* max read data block length */ + rt_uint8_t rd_blk_part; + rt_uint8_t wr_blk_misalign; + rt_uint8_t rd_blk_misalign; + rt_uint8_t dsr_imp; /* DSR implemented */ + rt_uint8_t c_size_mult; /* CSD 1.0 , device size multiplier */ + rt_uint32_t c_size; /* device size */ + rt_uint8_t r2w_factor; + rt_uint8_t wr_blk_len; /* max wtire data block length */ + rt_uint8_t wr_blk_partial; + rt_uint8_t csd_crc; + }; struct rt_sd_scr { - rt_uint8_t sd_version; - rt_uint8_t sd_bus_widths; + rt_uint8_t sd_version; + rt_uint8_t sd_bus_widths; }; struct rt_sdio_cccr { - rt_uint8_t sdio_version; - rt_uint8_t sd_version; - rt_uint8_t direct_cmd:1, /* Card Supports Direct Commands during data transfer - only SD mode, not used for SPI mode */ - multi_block:1, /* Card Supports Multi-Block */ - read_wait:1, /* Card Supports Read Wait - only SD mode, not used for SPI mode */ - suspend_resume:1, /* Card supports Suspend/Resume - only SD mode, not used for SPI mode */ - s4mi:1, /* generate interrupts during a 4-bit - multi-block data transfer */ - e4mi:1, /* Enable the multi-block IRQ during - 4-bit transfer for the SDIO card */ - low_speed:1, /* Card is a Low-Speed card */ - low_speed_4:1; /* 4-bit support for Low-Speed cards */ - - rt_uint8_t bus_width:1, /* Support SDIO bus width, 1:4bit, 0:1bit */ - cd_disable:1, /* Connect[0]/Disconnect[1] the 10K-90K ohm pull-up - resistor on CD/DAT[3] (pin 1) of the card */ - power_ctrl:1, /* Support Master Power Control */ - high_speed:1; /* Support High-Speed */ - - + rt_uint8_t sdio_version; + rt_uint8_t sd_version; + rt_uint8_t direct_cmd:1, /* Card Supports Direct Commands during data transfer + only SD mode, not used for SPI mode */ + multi_block:1, /* Card Supports Multi-Block */ + read_wait:1, /* Card Supports Read Wait + only SD mode, not used for SPI mode */ + suspend_resume:1, /* Card supports Suspend/Resume + only SD mode, not used for SPI mode */ + s4mi:1, /* generate interrupts during a 4-bit + multi-block data transfer */ + e4mi:1, /* Enable the multi-block IRQ during + 4-bit transfer for the SDIO card */ + low_speed:1, /* Card is a Low-Speed card */ + low_speed_4:1; /* 4-bit support for Low-Speed cards */ + + rt_uint8_t bus_width:1, /* Support SDIO bus width, 1:4bit, 0:1bit */ + cd_disable:1, /* Connect[0]/Disconnect[1] the 10K-90K ohm pull-up + resistor on CD/DAT[3] (pin 1) of the card */ + power_ctrl:1, /* Support Master Power Control */ + high_speed:1; /* Support High-Speed */ + + }; struct rt_sdio_cis { - rt_uint16_t manufacturer; - rt_uint16_t product; - rt_uint16_t func0_blk_size; - rt_uint32_t max_tran_speed; + rt_uint16_t manufacturer; + rt_uint16_t product; + rt_uint16_t func0_blk_size; + rt_uint32_t max_tran_speed; }; /* * SDIO function CIS tuple (unknown to the core) */ struct rt_sdio_function_tuple { - struct rt_sdio_function_tuple *next; - rt_uint8_t code; - rt_uint8_t size; - rt_uint8_t *data; + struct rt_sdio_function_tuple *next; + rt_uint8_t code; + rt_uint8_t size; + rt_uint8_t *data; }; struct rt_sdio_function; @@ -107,60 +107,60 @@ typedef void (rt_sdio_irq_handler_t)(struct rt_sdio_function *); * SDIO function devices */ struct rt_sdio_function { - struct rt_mmcsd_card *card; /* the card this device belongs to */ - rt_sdio_irq_handler_t *irq_handler; /* IRQ callback */ - rt_uint8_t num; /* function number */ + struct rt_mmcsd_card *card; /* the card this device belongs to */ + rt_sdio_irq_handler_t *irq_handler; /* IRQ callback */ + rt_uint8_t num; /* function number */ + + rt_uint8_t func_code; /* Standard SDIO Function interface code */ + rt_uint16_t manufacturer; /* manufacturer id */ + rt_uint16_t product; /* product id */ - rt_uint8_t func_code; /* Standard SDIO Function interface code */ - rt_uint16_t manufacturer; /* manufacturer id */ - rt_uint16_t product; /* product id */ + rt_uint32_t max_blk_size; /* maximum block size */ + rt_uint32_t cur_blk_size; /* current block size */ - rt_uint32_t max_blk_size; /* maximum block size */ - rt_uint32_t cur_blk_size; /* current block size */ + rt_uint32_t enable_timeout_val; /* max enable timeout in msec */ - rt_uint32_t enable_timeout_val; /* max enable timeout in msec */ + struct rt_sdio_function_tuple *tuples; - struct rt_sdio_function_tuple *tuples; - void *priv; }; -#define SDIO_MAX_FUNCTIONS 7 +#define SDIO_MAX_FUNCTIONS 7 struct rt_mmcsd_card { - struct rt_mmcsd_host *host; - rt_uint32_t rca; /* card addr */ - rt_uint32_t resp_cid[4]; /* card CID register */ - rt_uint32_t resp_csd[4]; /* card CSD register */ - rt_uint32_t resp_scr[2]; /* card SCR register */ - - rt_uint16_t tacc_clks; /* data access time by ns */ - rt_uint32_t tacc_ns; /* data access time by clk cycles */ - rt_uint32_t max_data_rate; /* max data transfer rate */ - rt_uint32_t card_capacity; /* card capacity, unit:KB */ - rt_uint32_t card_blksize; /* card block size */ - rt_uint32_t erase_size; /* erase size in sectors */ - rt_uint16_t card_type; + struct rt_mmcsd_host *host; + rt_uint32_t rca; /* card addr */ + rt_uint32_t resp_cid[4]; /* card CID register */ + rt_uint32_t resp_csd[4]; /* card CSD register */ + rt_uint32_t resp_scr[2]; /* card SCR register */ + + rt_uint16_t tacc_clks; /* data access time by ns */ + rt_uint32_t tacc_ns; /* data access time by clk cycles */ + rt_uint32_t max_data_rate; /* max data transfer rate */ + rt_uint32_t card_capacity; /* card capacity, unit:KB */ + rt_uint32_t card_blksize; /* card block size */ + rt_uint32_t erase_size; /* erase size in sectors */ + rt_uint16_t card_type; #define CARD_TYPE_MMC 0 /* MMC card */ #define CARD_TYPE_SD 1 /* SD card */ #define CARD_TYPE_SDIO 2 /* SDIO card */ #define CARD_TYPE_SDIO_COMBO 3 /* SD combo (IO+mem) card */ - rt_uint16_t flags; + rt_uint16_t flags; #define CARD_FLAG_HIGHSPEED (1 << 0) /* SDIO bus speed 50MHz */ #define CARD_FLAG_SDHC (1 << 1) /* SDHC card */ #define CARD_FLAG_SDXC (1 << 2) /* SDXC card */ - struct rt_sd_scr scr; - struct rt_mmcsd_csd csd; - rt_uint32_t hs_max_data_rate; /* max data transfer rate in high speed mode */ + struct rt_sd_scr scr; + struct rt_mmcsd_csd csd; + rt_uint32_t hs_max_data_rate; /* max data transfer rate in high speed mode */ - rt_uint8_t sdio_function_num; /* totol number of SDIO functions */ - struct rt_sdio_cccr cccr; /* common card info */ - struct rt_sdio_cis cis; /* common tuple info */ - struct rt_sdio_function *sdio_function[SDIO_MAX_FUNCTIONS + 1]; /* SDIO functions (devices) */ + rt_uint8_t sdio_function_num; /* totol number of SDIO functions */ + struct rt_sdio_cccr cccr; /* common card info */ + struct rt_sdio_cis cis; /* common tuple info */ + struct rt_sdio_function *sdio_function[SDIO_MAX_FUNCTIONS + 1]; /* SDIO functions (devices) */ }; diff --git a/components/drivers/include/drivers/mmcsd_cmd.h b/components/drivers/include/drivers/mmcsd_cmd.h index 7c2f26e892..2993fe5406 100644 --- a/components/drivers/include/drivers/mmcsd_cmd.h +++ b/components/drivers/include/drivers/mmcsd_cmd.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-07-25 weety first version + * Date Author Notes + * 2011-07-25 weety first version */ #ifndef __CMD_H__ @@ -85,9 +85,9 @@ extern "C" { #define SD_APP_OP_COND 41 /* bcr [31:0] OCR R3 */ #define SD_APP_SEND_SCR 51 /* adtc R1 */ -#define SCR_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.01 */ -#define SCR_SPEC_VER_1 1 /* Implements system specification 1.10 */ -#define SCR_SPEC_VER_2 2 /* Implements system specification 2.00 */ +#define SCR_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.01 */ +#define SCR_SPEC_VER_1 1 /* Implements system specification 1.10 */ +#define SCR_SPEC_VER_2 2 /* Implements system specification 2.00 */ /* SDIO commands type argument response */ diff --git a/components/drivers/include/drivers/mmcsd_core.h b/components/drivers/include/drivers/mmcsd_core.h index 05a5af6d79..11b1386b23 100644 --- a/components/drivers/include/drivers/mmcsd_core.h +++ b/components/drivers/include/drivers/mmcsd_core.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-07-25 weety first version + * Date Author Notes + * 2011-07-25 weety first version */ #ifndef __CORE_H__ @@ -27,139 +27,139 @@ extern "C" { #endif struct rt_mmcsd_data { - rt_uint32_t blksize; - rt_uint32_t blks; - rt_uint32_t *buf; - rt_int32_t err; - rt_uint32_t flags; -#define DATA_DIR_WRITE (1 << 0) -#define DATA_DIR_READ (1 << 1) -#define DATA_STREAM (1 << 2) - - unsigned int bytes_xfered; - - struct rt_mmcsd_cmd *stop; /* stop command */ - struct rt_mmcsd_req *mrq; /* associated request */ - - rt_uint32_t timeout_ns; - rt_uint32_t timeout_clks; + rt_uint32_t blksize; + rt_uint32_t blks; + rt_uint32_t *buf; + rt_int32_t err; + rt_uint32_t flags; +#define DATA_DIR_WRITE (1 << 0) +#define DATA_DIR_READ (1 << 1) +#define DATA_STREAM (1 << 2) + + unsigned int bytes_xfered; + + struct rt_mmcsd_cmd *stop; /* stop command */ + struct rt_mmcsd_req *mrq; /* associated request */ + + rt_uint32_t timeout_ns; + rt_uint32_t timeout_clks; }; struct rt_mmcsd_cmd { - rt_uint32_t cmd_code; - rt_uint32_t arg; - rt_uint32_t resp[4]; - rt_uint32_t flags; -/*rsponse types + rt_uint32_t cmd_code; + rt_uint32_t arg; + rt_uint32_t resp[4]; + rt_uint32_t flags; +/*rsponse types *bits:0~3 */ -#define RESP_MASK (0xF) -#define RESP_NONE (0) -#define RESP_R1 (1 << 0) -#define RESP_R1B (2 << 0) -#define RESP_R2 (3 << 0) -#define RESP_R3 (4 << 0) -#define RESP_R4 (5 << 0) -#define RESP_R6 (6 << 0) -#define RESP_R7 (7 << 0) -#define RESP_R5 (8 << 0) /*SDIO command response type*/ -/*command types +#define RESP_MASK (0xF) +#define RESP_NONE (0) +#define RESP_R1 (1 << 0) +#define RESP_R1B (2 << 0) +#define RESP_R2 (3 << 0) +#define RESP_R3 (4 << 0) +#define RESP_R4 (5 << 0) +#define RESP_R6 (6 << 0) +#define RESP_R7 (7 << 0) +#define RESP_R5 (8 << 0) /*SDIO command response type*/ +/*command types *bits:4~5 */ -#define CMD_MASK (3 << 4) /* command type */ -#define CMD_AC (0 << 4) -#define CMD_ADTC (1 << 4) -#define CMD_BC (2 << 4) -#define CMD_BCR (3 << 4) +#define CMD_MASK (3 << 4) /* command type */ +#define CMD_AC (0 << 4) +#define CMD_ADTC (1 << 4) +#define CMD_BC (2 << 4) +#define CMD_BCR (3 << 4) -#define resp_type(cmd) ((cmd)->flags & RESP_MASK) +#define resp_type(cmd) ((cmd)->flags & RESP_MASK) -/*spi rsponse types +/*spi rsponse types *bits:6~8 */ -#define RESP_SPI_MASK (0x7 << 6) -#define RESP_SPI_R1 (1 << 6) -#define RESP_SPI_R1B (2 << 6) -#define RESP_SPI_R2 (3 << 6) -#define RESP_SPI_R3 (4 << 6) -#define RESP_SPI_R4 (5 << 6) -#define RESP_SPI_R5 (6 << 6) -#define RESP_SPI_R7 (7 << 6) - -#define spi_resp_type(cmd) ((cmd)->flags & RESP_SPI_MASK) +#define RESP_SPI_MASK (0x7 << 6) +#define RESP_SPI_R1 (1 << 6) +#define RESP_SPI_R1B (2 << 6) +#define RESP_SPI_R2 (3 << 6) +#define RESP_SPI_R3 (4 << 6) +#define RESP_SPI_R4 (5 << 6) +#define RESP_SPI_R5 (6 << 6) +#define RESP_SPI_R7 (7 << 6) + +#define spi_resp_type(cmd) ((cmd)->flags & RESP_SPI_MASK) /* * These are the command types. */ -#define cmd_type(cmd) ((cmd)->flags & CMD_MASK) - - rt_int32_t retries; /* max number of retries */ - rt_int32_t err; +#define cmd_type(cmd) ((cmd)->flags & CMD_MASK) - struct rt_mmcsd_data *data; - struct rt_mmcsd_req *mrq; /* associated request */ + rt_int32_t retries; /* max number of retries */ + rt_int32_t err; + + struct rt_mmcsd_data *data; + struct rt_mmcsd_req *mrq; /* associated request */ }; struct rt_mmcsd_req { - struct rt_mmcsd_data *data; - struct rt_mmcsd_cmd *cmd; - struct rt_mmcsd_cmd *stop; + struct rt_mmcsd_data *data; + struct rt_mmcsd_cmd *cmd; + struct rt_mmcsd_cmd *stop; }; /*the following is response bit*/ -#define R1_OUT_OF_RANGE (1 << 31) /* er, c */ -#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */ -#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */ -#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */ -#define R1_ERASE_PARAM (1 << 27) /* ex, c */ -#define R1_WP_VIOLATION (1 << 26) /* erx, c */ -#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */ -#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */ -#define R1_COM_CRC_ERROR (1 << 23) /* er, b */ -#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */ -#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */ -#define R1_CC_ERROR (1 << 20) /* erx, c */ -#define R1_ERROR (1 << 19) /* erx, c */ -#define R1_UNDERRUN (1 << 18) /* ex, c */ -#define R1_OVERRUN (1 << 17) /* ex, c */ -#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */ -#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */ -#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */ -#define R1_ERASE_RESET (1 << 13) /* sr, c */ +#define R1_OUT_OF_RANGE (1 << 31) /* er, c */ +#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */ +#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */ +#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */ +#define R1_ERASE_PARAM (1 << 27) /* ex, c */ +#define R1_WP_VIOLATION (1 << 26) /* erx, c */ +#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */ +#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */ +#define R1_COM_CRC_ERROR (1 << 23) /* er, b */ +#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */ +#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */ +#define R1_CC_ERROR (1 << 20) /* erx, c */ +#define R1_ERROR (1 << 19) /* erx, c */ +#define R1_UNDERRUN (1 << 18) /* ex, c */ +#define R1_OVERRUN (1 << 17) /* ex, c */ +#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */ +#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */ +#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */ +#define R1_ERASE_RESET (1 << 13) /* sr, c */ #define R1_STATUS(x) (x & 0xFFFFE000) -#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */ -#define R1_READY_FOR_DATA (1 << 8) /* sx, a */ -#define R1_APP_CMD (1 << 5) /* sr, c */ - - -#define R1_SPI_IDLE (1 << 0) -#define R1_SPI_ERASE_RESET (1 << 1) -#define R1_SPI_ILLEGAL_COMMAND (1 << 2) -#define R1_SPI_COM_CRC (1 << 3) -#define R1_SPI_ERASE_SEQ (1 << 4) -#define R1_SPI_ADDRESS (1 << 5) -#define R1_SPI_PARAMETER (1 << 6) +#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */ +#define R1_READY_FOR_DATA (1 << 8) /* sx, a */ +#define R1_APP_CMD (1 << 5) /* sr, c */ + + +#define R1_SPI_IDLE (1 << 0) +#define R1_SPI_ERASE_RESET (1 << 1) +#define R1_SPI_ILLEGAL_COMMAND (1 << 2) +#define R1_SPI_COM_CRC (1 << 3) +#define R1_SPI_ERASE_SEQ (1 << 4) +#define R1_SPI_ADDRESS (1 << 5) +#define R1_SPI_PARAMETER (1 << 6) /* R1 bit 7 is always zero */ -#define R2_SPI_CARD_LOCKED (1 << 8) -#define R2_SPI_WP_ERASE_SKIP (1 << 9) /* or lock/unlock fail */ -#define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP -#define R2_SPI_ERROR (1 << 10) -#define R2_SPI_CC_ERROR (1 << 11) -#define R2_SPI_CARD_ECC_ERROR (1 << 12) -#define R2_SPI_WP_VIOLATION (1 << 13) -#define R2_SPI_ERASE_PARAM (1 << 14) -#define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */ -#define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE - -#define CARD_BUSY 0x80000000 /* Card Power up status bit */ +#define R2_SPI_CARD_LOCKED (1 << 8) +#define R2_SPI_WP_ERASE_SKIP (1 << 9) /* or lock/unlock fail */ +#define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP +#define R2_SPI_ERROR (1 << 10) +#define R2_SPI_CC_ERROR (1 << 11) +#define R2_SPI_CARD_ECC_ERROR (1 << 12) +#define R2_SPI_WP_VIOLATION (1 << 13) +#define R2_SPI_ERASE_PARAM (1 << 14) +#define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */ +#define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE + +#define CARD_BUSY 0x80000000 /* Card Power up status bit */ /* R5 response bits */ -#define R5_COM_CRC_ERROR (1 << 15) -#define R5_ILLEGAL_COMMAND (1 << 14) -#define R5_ERROR (1 << 11) -#define R5_FUNCTION_NUMBER (1 << 9) -#define R5_OUT_OF_RANGE (1 << 8) -#define R5_STATUS(x) (x & 0xCB00) -#define R5_IO_CURRENT_STATE(x) ((x & 0x3000) >> 12) +#define R5_COM_CRC_ERROR (1 << 15) +#define R5_ILLEGAL_COMMAND (1 << 14) +#define R5_ERROR (1 << 11) +#define R5_FUNCTION_NUMBER (1 << 9) +#define R5_OUT_OF_RANGE (1 << 8) +#define R5_STATUS(x) (x & 0xCB00) +#define R5_IO_CURRENT_STATE(x) ((x & 0x3000) >> 12) @@ -173,36 +173,36 @@ struct rt_mmcsd_req { rt_inline rt_uint32_t __rt_fls(rt_uint32_t val) { - rt_uint32_t bit = 32; - - if (!val) - return 0; - if (!(val & 0xffff0000u)) - { - val <<= 16; - bit -= 16; - } - if (!(val & 0xff000000u)) - { - val <<= 8; - bit -= 8; - } - if (!(val & 0xf0000000u)) - { - val <<= 4; - bit -= 4; - } - if (!(val & 0xc0000000u)) - { - val <<= 2; - bit -= 2; - } - if (!(val & 0x80000000u)) - { - bit -= 1; - } - - return bit; + rt_uint32_t bit = 32; + + if (!val) + return 0; + if (!(val & 0xffff0000u)) + { + val <<= 16; + bit -= 16; + } + if (!(val & 0xff000000u)) + { + val <<= 8; + bit -= 8; + } + if (!(val & 0xf0000000u)) + { + val <<= 4; + bit -= 4; + } + if (!(val & 0xc0000000u)) + { + val <<= 2; + bit -= 2; + } + if (!(val & 0x80000000u)) + { + bit -= 1; + } + + return bit; } #define MMCSD_HOST_PLUGED 0 diff --git a/components/drivers/include/drivers/mmcsd_host.h b/components/drivers/include/drivers/mmcsd_host.h index 1253062aef..c7f673aeb1 100644 --- a/components/drivers/include/drivers/mmcsd_host.h +++ b/components/drivers/include/drivers/mmcsd_host.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-07-25 weety first version + * Date Author Notes + * 2011-07-25 weety first version */ #ifndef __HOST_H__ @@ -18,33 +18,33 @@ extern "C" { #endif struct rt_mmcsd_io_cfg { - rt_uint32_t clock; /* clock rate */ - rt_uint16_t vdd; + rt_uint32_t clock; /* clock rate */ + rt_uint16_t vdd; /* vdd stores the bit number of the selected voltage range from below. */ - rt_uint8_t bus_mode; /* command output mode */ + rt_uint8_t bus_mode; /* command output mode */ -#define MMCSD_BUSMODE_OPENDRAIN 1 -#define MMCSD_BUSMODE_PUSHPULL 2 +#define MMCSD_BUSMODE_OPENDRAIN 1 +#define MMCSD_BUSMODE_PUSHPULL 2 - rt_uint8_t chip_select; /* SPI chip select */ + rt_uint8_t chip_select; /* SPI chip select */ -#define MMCSD_CS_IGNORE 0 -#define MMCSD_CS_HIGH 1 -#define MMCSD_CS_LOW 2 +#define MMCSD_CS_IGNORE 0 +#define MMCSD_CS_HIGH 1 +#define MMCSD_CS_LOW 2 - rt_uint8_t power_mode; /* power supply mode */ + rt_uint8_t power_mode; /* power supply mode */ -#define MMCSD_POWER_OFF 0 -#define MMCSD_POWER_UP 1 -#define MMCSD_POWER_ON 2 +#define MMCSD_POWER_OFF 0 +#define MMCSD_POWER_UP 1 +#define MMCSD_POWER_ON 2 - rt_uint8_t bus_width; /* data bus width */ + rt_uint8_t bus_width; /* data bus width */ -#define MMCSD_BUS_WIDTH_1 0 -#define MMCSD_BUS_WIDTH_4 2 -#define MMCSD_BUS_WIDTH_8 3 +#define MMCSD_BUS_WIDTH_1 0 +#define MMCSD_BUS_WIDTH_4 2 +#define MMCSD_BUS_WIDTH_8 3 }; @@ -52,71 +52,71 @@ struct rt_mmcsd_host; struct rt_mmcsd_req; struct rt_mmcsd_host_ops { - void (*request)(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req); - void (*set_iocfg)(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg); - rt_int32_t (*get_card_status)(struct rt_mmcsd_host *host); - void (*enable_sdio_irq)(struct rt_mmcsd_host *host, rt_int32_t en); + void (*request)(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req); + void (*set_iocfg)(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg); + rt_int32_t (*get_card_status)(struct rt_mmcsd_host *host); + void (*enable_sdio_irq)(struct rt_mmcsd_host *host, rt_int32_t en); }; struct rt_mmcsd_host { - struct rt_mmcsd_card *card; - const struct rt_mmcsd_host_ops *ops; - rt_uint32_t freq_min; - rt_uint32_t freq_max; - struct rt_mmcsd_io_cfg io_cfg; - rt_uint32_t valid_ocr; /* current valid OCR */ -#define VDD_165_195 (1 << 7) /* VDD voltage 1.65 - 1.95 */ -#define VDD_20_21 (1 << 8) /* VDD voltage 2.0 ~ 2.1 */ -#define VDD_21_22 (1 << 9) /* VDD voltage 2.1 ~ 2.2 */ -#define VDD_22_23 (1 << 10) /* VDD voltage 2.2 ~ 2.3 */ -#define VDD_23_24 (1 << 11) /* VDD voltage 2.3 ~ 2.4 */ -#define VDD_24_25 (1 << 12) /* VDD voltage 2.4 ~ 2.5 */ -#define VDD_25_26 (1 << 13) /* VDD voltage 2.5 ~ 2.6 */ -#define VDD_26_27 (1 << 14) /* VDD voltage 2.6 ~ 2.7 */ -#define VDD_27_28 (1 << 15) /* VDD voltage 2.7 ~ 2.8 */ -#define VDD_28_29 (1 << 16) /* VDD voltage 2.8 ~ 2.9 */ -#define VDD_29_30 (1 << 17) /* VDD voltage 2.9 ~ 3.0 */ -#define VDD_30_31 (1 << 18) /* VDD voltage 3.0 ~ 3.1 */ -#define VDD_31_32 (1 << 19) /* VDD voltage 3.1 ~ 3.2 */ -#define VDD_32_33 (1 << 20) /* VDD voltage 3.2 ~ 3.3 */ -#define VDD_33_34 (1 << 21) /* VDD voltage 3.3 ~ 3.4 */ -#define VDD_34_35 (1 << 22) /* VDD voltage 3.4 ~ 3.5 */ -#define VDD_35_36 (1 << 23) /* VDD voltage 3.5 ~ 3.6 */ - rt_uint32_t flags; /* define device capabilities */ -#define MMCSD_BUSWIDTH_4 (1 << 0) -#define MMCSD_BUSWIDTH_8 (1 << 1) -#define MMCSD_MUTBLKWRITE (1 << 2) -#define MMCSD_HOST_IS_SPI (1 << 3) -#define controller_is_spi(host) (host->flags & MMCSD_HOST_IS_SPI) -#define MMCSD_SUP_SDIO_IRQ (1 << 4) /* support signal pending SDIO IRQs */ -#define MMCSD_SUP_HIGHSPEED (1 << 5) /* support high speed */ - - rt_uint32_t max_seg_size; /* maximum size of one dma segment */ - rt_uint32_t max_dma_segs; /* maximum number of dma segments in one request */ - rt_uint32_t max_blk_size; /* maximum block size */ - rt_uint32_t max_blk_count; /* maximum block count */ - - rt_uint32_t spi_use_crc; - struct rt_mutex bus_lock; - struct rt_semaphore sem_ack; - - rt_uint32_t sdio_irq_num; - struct rt_semaphore *sdio_irq_sem; - struct rt_thread *sdio_irq_thread; - - void *private_data; + struct rt_mmcsd_card *card; + const struct rt_mmcsd_host_ops *ops; + rt_uint32_t freq_min; + rt_uint32_t freq_max; + struct rt_mmcsd_io_cfg io_cfg; + rt_uint32_t valid_ocr; /* current valid OCR */ +#define VDD_165_195 (1 << 7) /* VDD voltage 1.65 - 1.95 */ +#define VDD_20_21 (1 << 8) /* VDD voltage 2.0 ~ 2.1 */ +#define VDD_21_22 (1 << 9) /* VDD voltage 2.1 ~ 2.2 */ +#define VDD_22_23 (1 << 10) /* VDD voltage 2.2 ~ 2.3 */ +#define VDD_23_24 (1 << 11) /* VDD voltage 2.3 ~ 2.4 */ +#define VDD_24_25 (1 << 12) /* VDD voltage 2.4 ~ 2.5 */ +#define VDD_25_26 (1 << 13) /* VDD voltage 2.5 ~ 2.6 */ +#define VDD_26_27 (1 << 14) /* VDD voltage 2.6 ~ 2.7 */ +#define VDD_27_28 (1 << 15) /* VDD voltage 2.7 ~ 2.8 */ +#define VDD_28_29 (1 << 16) /* VDD voltage 2.8 ~ 2.9 */ +#define VDD_29_30 (1 << 17) /* VDD voltage 2.9 ~ 3.0 */ +#define VDD_30_31 (1 << 18) /* VDD voltage 3.0 ~ 3.1 */ +#define VDD_31_32 (1 << 19) /* VDD voltage 3.1 ~ 3.2 */ +#define VDD_32_33 (1 << 20) /* VDD voltage 3.2 ~ 3.3 */ +#define VDD_33_34 (1 << 21) /* VDD voltage 3.3 ~ 3.4 */ +#define VDD_34_35 (1 << 22) /* VDD voltage 3.4 ~ 3.5 */ +#define VDD_35_36 (1 << 23) /* VDD voltage 3.5 ~ 3.6 */ + rt_uint32_t flags; /* define device capabilities */ +#define MMCSD_BUSWIDTH_4 (1 << 0) +#define MMCSD_BUSWIDTH_8 (1 << 1) +#define MMCSD_MUTBLKWRITE (1 << 2) +#define MMCSD_HOST_IS_SPI (1 << 3) +#define controller_is_spi(host) (host->flags & MMCSD_HOST_IS_SPI) +#define MMCSD_SUP_SDIO_IRQ (1 << 4) /* support signal pending SDIO IRQs */ +#define MMCSD_SUP_HIGHSPEED (1 << 5) /* support high speed */ + + rt_uint32_t max_seg_size; /* maximum size of one dma segment */ + rt_uint32_t max_dma_segs; /* maximum number of dma segments in one request */ + rt_uint32_t max_blk_size; /* maximum block size */ + rt_uint32_t max_blk_count; /* maximum block count */ + + rt_uint32_t spi_use_crc; + struct rt_mutex bus_lock; + struct rt_semaphore sem_ack; + + rt_uint32_t sdio_irq_num; + struct rt_semaphore *sdio_irq_sem; + struct rt_thread *sdio_irq_thread; + + void *private_data; }; rt_inline void mmcsd_delay_ms(rt_uint32_t ms) { - if (ms < 1000 / RT_TICK_PER_SECOND) - { - rt_thread_delay(1); - } - else - { - rt_thread_delay(ms/(1000 / RT_TICK_PER_SECOND)); - } + if (ms < 1000 / RT_TICK_PER_SECOND) + { + rt_thread_delay(1); + } + else + { + rt_thread_delay(ms/(1000 / RT_TICK_PER_SECOND)); + } } #ifdef __cplusplus diff --git a/components/drivers/include/drivers/mtd_nand.h b/components/drivers/include/drivers/mtd_nand.h index f7675aede6..a452da61dd 100644 --- a/components/drivers/include/drivers/mtd_nand.h +++ b/components/drivers/include/drivers/mtd_nand.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/include/drivers/mtd_nor.h b/components/drivers/include/drivers/mtd_nor.h index 32a952f374..2a3bb54f33 100644 --- a/components/drivers/include/drivers/mtd_nor.h +++ b/components/drivers/include/drivers/mtd_nor.h @@ -1,6 +1,6 @@ /* * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: @@ -14,54 +14,54 @@ #include struct rt_mtd_nor_driver_ops; -#define RT_MTD_NOR_DEVICE(device) ((struct rt_mtd_nor_device*)(device)) +#define RT_MTD_NOR_DEVICE(device) ((struct rt_mtd_nor_device*)(device)) struct rt_mtd_nor_device { - struct rt_device parent; + struct rt_device parent; - rt_uint32_t block_size; /* The Block size in the flash */ - rt_uint32_t block_start; /* The start of available block*/ - rt_uint32_t block_end; /* The end of available block */ + rt_uint32_t block_size; /* The Block size in the flash */ + rt_uint32_t block_start; /* The start of available block*/ + rt_uint32_t block_end; /* The end of available block */ - /* operations interface */ - const struct rt_mtd_nor_driver_ops* ops; + /* operations interface */ + const struct rt_mtd_nor_driver_ops* ops; }; struct rt_mtd_nor_driver_ops { - rt_err_t (*read_id) (struct rt_mtd_nor_device* device); + rt_err_t (*read_id) (struct rt_mtd_nor_device* device); - rt_size_t (*read) (struct rt_mtd_nor_device* device, rt_off_t offset, rt_uint8_t* data, rt_uint32_t length); - rt_size_t (*write) (struct rt_mtd_nor_device* device, rt_off_t offset, const rt_uint8_t* data, rt_uint32_t length); + rt_size_t (*read) (struct rt_mtd_nor_device* device, rt_off_t offset, rt_uint8_t* data, rt_uint32_t length); + rt_size_t (*write) (struct rt_mtd_nor_device* device, rt_off_t offset, const rt_uint8_t* data, rt_uint32_t length); - rt_err_t (*erase_block)(struct rt_mtd_nor_device* device, rt_off_t offset, rt_uint32_t length); + rt_err_t (*erase_block)(struct rt_mtd_nor_device* device, rt_off_t offset, rt_uint32_t length); }; rt_err_t rt_mtd_nor_register_device(const char* name, struct rt_mtd_nor_device* device); rt_inline rt_uint32_t rt_mtd_nor_read_id(struct rt_mtd_nor_device* device) { - return device->ops->read_id(device); + return device->ops->read_id(device); } rt_inline rt_size_t rt_mtd_nor_read( - struct rt_mtd_nor_device* device, - rt_off_t offset, rt_uint8_t* data, rt_uint32_t length) + struct rt_mtd_nor_device* device, + rt_off_t offset, rt_uint8_t* data, rt_uint32_t length) { - return device->ops->read(device, offset, data, length); + return device->ops->read(device, offset, data, length); } rt_inline rt_size_t rt_mtd_nor_write( - struct rt_mtd_nor_device* device, - rt_off_t offset, const rt_uint8_t* data, rt_uint32_t length) + struct rt_mtd_nor_device* device, + rt_off_t offset, const rt_uint8_t* data, rt_uint32_t length) { - return device->ops->write(device, offset, data, length); + return device->ops->write(device, offset, data, length); } rt_inline rt_err_t rt_mtd_nor_erase_block(struct rt_mtd_nor_device* device, rt_off_t offset, rt_size_t length) { - return device->ops->erase_block(device, offset, length); + return device->ops->erase_block(device, offset, length); } #endif diff --git a/components/drivers/include/drivers/pin.h b/components/drivers/include/drivers/pin.h index ca35407932..c624ddcb2a 100644 --- a/components/drivers/include/drivers/pin.h +++ b/components/drivers/include/drivers/pin.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/include/drivers/pm.h b/components/drivers/include/drivers/pm.h index dd5875aa1d..1a030dc0a0 100644 --- a/components/drivers/include/drivers/pm.h +++ b/components/drivers/include/drivers/pm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/include/drivers/pulse_encoder.h b/components/drivers/include/drivers/pulse_encoder.h index 0c7df04cd6..38ef7652b9 100644 --- a/components/drivers/include/drivers/pulse_encoder.h +++ b/components/drivers/include/drivers/pulse_encoder.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/include/drivers/rt_drv_pwm.h b/components/drivers/include/drivers/rt_drv_pwm.h index 16de4c6ab8..8f58052afc 100644 --- a/components/drivers/include/drivers/rt_drv_pwm.h +++ b/components/drivers/include/drivers/rt_drv_pwm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/include/drivers/rt_inputcapture.h b/components/drivers/include/drivers/rt_inputcapture.h index 40cd55883d..813ed3157b 100644 --- a/components/drivers/include/drivers/rt_inputcapture.h +++ b/components/drivers/include/drivers/rt_inputcapture.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/include/drivers/rtc.h b/components/drivers/include/drivers/rtc.h index 1cd88a7be3..4845937113 100644 --- a/components/drivers/include/drivers/rtc.h +++ b/components/drivers/include/drivers/rtc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/include/drivers/sd.h b/components/drivers/include/drivers/sd.h index e096df9372..450f23e65b 100644 --- a/components/drivers/include/drivers/sd.h +++ b/components/drivers/include/drivers/sd.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/include/drivers/sdio.h b/components/drivers/include/drivers/sdio.h index e4bf4a048f..212d8cfb52 100644 --- a/components/drivers/include/drivers/sdio.h +++ b/components/drivers/include/drivers/sdio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -174,10 +174,10 @@ rt_int32_t sdio_io_rw_extended_block(struct rt_sdio_function *func, rt_int32_t op_code, rt_uint8_t *buf, rt_uint32_t len); -rt_uint8_t sdio_io_readb(struct rt_sdio_function *func, +rt_uint8_t sdio_io_readb(struct rt_sdio_function *func, rt_uint32_t reg, rt_int32_t *err); -rt_int32_t sdio_io_writeb(struct rt_sdio_function *func, +rt_int32_t sdio_io_writeb(struct rt_sdio_function *func, rt_uint32_t reg, rt_uint8_t data); rt_uint16_t sdio_io_readw(struct rt_sdio_function *func, @@ -192,19 +192,19 @@ rt_uint32_t sdio_io_readl(struct rt_sdio_function *func, rt_int32_t sdio_io_writel(struct rt_sdio_function *func, rt_uint32_t data, rt_uint32_t addr); -rt_int32_t sdio_io_read_multi_fifo_b(struct rt_sdio_function *func, +rt_int32_t sdio_io_read_multi_fifo_b(struct rt_sdio_function *func, rt_uint32_t addr, rt_uint8_t *buf, rt_uint32_t len); -rt_int32_t sdio_io_write_multi_fifo_b(struct rt_sdio_function *func, +rt_int32_t sdio_io_write_multi_fifo_b(struct rt_sdio_function *func, rt_uint32_t addr, rt_uint8_t *buf, rt_uint32_t len); -rt_int32_t sdio_io_read_multi_incr_b(struct rt_sdio_function *func, +rt_int32_t sdio_io_read_multi_incr_b(struct rt_sdio_function *func, rt_uint32_t addr, rt_uint8_t *buf, rt_uint32_t len); -rt_int32_t sdio_io_write_multi_incr_b(struct rt_sdio_function *func, +rt_int32_t sdio_io_write_multi_incr_b(struct rt_sdio_function *func, rt_uint32_t addr, rt_uint8_t *buf, rt_uint32_t len); diff --git a/components/drivers/include/drivers/sdio_func_ids.h b/components/drivers/include/drivers/sdio_func_ids.h index 79085a5933..76502ff6ea 100644 --- a/components/drivers/include/drivers/sdio_func_ids.h +++ b/components/drivers/include/drivers/sdio_func_ids.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2012-02-26 weety first version */ - + #ifndef __SDIO_FUNC_IDS_H__ #define __SDIO_FUNC_IDS_H__ diff --git a/components/drivers/include/drivers/serial.h b/components/drivers/include/drivers/serial.h index 45095af63f..c2e951e9b1 100644 --- a/components/drivers/include/drivers/serial.h +++ b/components/drivers/include/drivers/serial.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -104,7 +104,7 @@ struct serial_configure }; /* - * Serial FIFO mode + * Serial FIFO mode */ struct rt_serial_rx_fifo { @@ -121,7 +121,7 @@ struct rt_serial_tx_fifo struct rt_completion completion; }; -/* +/* * Serial DMA mode */ struct rt_serial_rx_dma diff --git a/components/drivers/include/drivers/spi.h b/components/drivers/include/drivers/spi.h index d92518cd94..018d12139b 100644 --- a/components/drivers/include/drivers/spi.h +++ b/components/drivers/include/drivers/spi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -151,7 +151,7 @@ struct rt_qspi_configuration }; struct rt_qspi_device -{ +{ struct rt_spi_device parent; struct rt_qspi_configuration config; diff --git a/components/drivers/include/drivers/usb_common.h b/components/drivers/include/drivers/usb_common.h index 4d85a85e35..9c29a0d0df 100644 --- a/components/drivers/include/drivers/usb_common.h +++ b/components/drivers/include/drivers/usb_common.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -427,14 +427,14 @@ struct usb_os_proerty }; typedef struct usb_os_proerty * usb_os_proerty_t; -// Value Description -// 1 A NULL-terminated Unicode String (REG_SZ) -// 2 A NULL-terminated Unicode String that includes environment variables (REG_EXPAND_SZ) -// 3 Free-form binary (REG_BINARY) -// 4 A little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) -// 5 A big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) -// 6 A NULL-terminated Unicode string that contains a symbolic link (REG_LINK) -// 7 Multiple NULL-terminated Unicode strings (REG_MULTI_SZ) +// Value Description +// 1 A NULL-terminated Unicode String (REG_SZ) +// 2 A NULL-terminated Unicode String that includes environment variables (REG_EXPAND_SZ) +// 3 Free-form binary (REG_BINARY) +// 4 A little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) +// 5 A big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) +// 6 A NULL-terminated Unicode string that contains a symbolic link (REG_LINK) +// 7 Multiple NULL-terminated Unicode strings (REG_MULTI_SZ) #define USB_OS_PROPERTY_TYPE_REG_SZ 0x01UL #define USB_OS_PROPERTY_TYPE_REG_EXPAND_SZ 0x02UL #define USB_OS_PROPERTY_TYPE_REG_BINARY 0x03UL diff --git a/components/drivers/include/drivers/usb_device.h b/components/drivers/include/drivers/usb_device.h index 26f0c4cf4a..1e76477dbc 100644 --- a/components/drivers/include/drivers/usb_device.h +++ b/components/drivers/include/drivers/usb_device.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -62,12 +62,12 @@ struct ufunction; struct udevice; struct uendpoint; -typedef enum +typedef enum { /* request to read full count */ UIO_REQUEST_READ_FULL, /* request to read any count */ - UIO_REQUEST_READ_BEST, + UIO_REQUEST_READ_BEST, /* request to write full count */ UIO_REQUEST_WRITE, }UIO_REQUEST_TYPE; @@ -85,7 +85,7 @@ struct udcd_ops rt_size_t (*ep_write)(rt_uint8_t address, void *buffer, rt_size_t size); rt_err_t (*ep0_send_status)(void); rt_err_t (*suspend)(void); - rt_err_t (*wakeup)(void); + rt_err_t (*wakeup)(void); }; struct ep_id @@ -215,10 +215,10 @@ enum udev_msg_type USB_MSG_SETUP_NOTIFY, USB_MSG_DATA_NOTIFY, USB_MSG_EP0_OUT, - USB_MSG_EP_CLEAR_FEATURE, + USB_MSG_EP_CLEAR_FEATURE, USB_MSG_SOF, USB_MSG_RESET, - USB_MSG_PLUG_IN, + USB_MSG_PLUG_IN, /* we don't need to add a "PLUG_IN" event because after the cable is * plugged in(before any SETUP) the classed have nothing to do. If the host * is ready, it will send RESET and we will have USB_MSG_RESET. So, a RESET @@ -279,7 +279,7 @@ uintf_t rt_usbd_find_interface(udevice_t device, rt_uint8_t value, ufunction_t * uep_t rt_usbd_find_endpoint(udevice_t device, ufunction_t* pfunc, rt_uint8_t ep_addr); rt_size_t rt_usbd_io_request(udevice_t device, uep_t ep, uio_request_t req); rt_size_t rt_usbd_ep0_write(udevice_t device, void *buffer, rt_size_t size); -rt_size_t rt_usbd_ep0_read(udevice_t device, void *buffer, rt_size_t size, +rt_size_t rt_usbd_ep0_read(udevice_t device, void *buffer, rt_size_t size, rt_err_t (*rx_ind)(udevice_t device, rt_size_t size)); int rt_usbd_vcom_class_register(void); @@ -396,7 +396,7 @@ rt_inline rt_err_t dcd_ep0_send_status(udcd_t dcd) } rt_inline rt_err_t dcd_ep_set_stall(udcd_t dcd, rt_uint8_t address) -{ +{ RT_ASSERT(dcd != RT_NULL); RT_ASSERT(dcd->ops != RT_NULL); RT_ASSERT(dcd->ops->ep_set_stall != RT_NULL); diff --git a/components/drivers/include/drivers/usb_host.h b/components/drivers/include/drivers/usb_host.h index 2a68f4edb5..2031e2cdc0 100644 --- a/components/drivers/include/drivers/usb_host.h +++ b/components/drivers/include/drivers/usb_host.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -44,10 +44,10 @@ struct uclass_driver rt_list_t list; int class_code; int subclass_code; - + rt_err_t (*enable)(void* arg); rt_err_t (*disable)(void* arg); - + void* user_data; }; typedef struct uclass_driver* ucd_t; @@ -56,9 +56,9 @@ struct uprotocal { rt_list_t list; int pro_id; - + rt_err_t (*init)(void* arg); - rt_err_t (*callback)(void* arg); + rt_err_t (*callback)(void* arg); }; typedef struct uprotocal* uprotocal_t; @@ -77,13 +77,13 @@ struct uinstance rt_uint8_t status; rt_uint8_t type; rt_uint8_t index; - rt_uint8_t address; + rt_uint8_t address; rt_uint8_t speed; - rt_uint8_t max_packet_size; + rt_uint8_t max_packet_size; rt_uint8_t port; struct uhub* parent_hub; - struct uhintf* intf[USB_MAX_INTERFACE]; + struct uhintf* intf[USB_MAX_INTERFACE]; }; typedef struct uinstance* uinst_t; @@ -113,14 +113,14 @@ struct uhub struct uhub_descriptor hub_desc; rt_uint8_t num_ports; rt_uint32_t port_status[USB_HUB_PORT_NUM]; - struct uinstance* child[USB_HUB_PORT_NUM]; + struct uinstance* child[USB_HUB_PORT_NUM]; rt_bool_t is_roothub; - rt_uint8_t buffer[8]; + rt_uint8_t buffer[8]; struct uinstance* self; struct uhcd *hcd; -}; +}; typedef struct uhub* uhub_t; struct uhcd_ops @@ -128,7 +128,7 @@ struct uhcd_ops rt_err_t (*reset_port) (rt_uint8_t port); int (*pipe_xfer) (upipe_t pipe, rt_uint8_t token, void* buffer, int nbytes, int timeout); rt_err_t (*open_pipe) (upipe_t pipe); - rt_err_t (*close_pipe) (upipe_t pipe); + rt_err_t (*close_pipe) (upipe_t pipe); }; typedef struct uhcd_ops* uhcd_ops_t; struct uhcd @@ -136,7 +136,7 @@ struct uhcd struct rt_device parent; uhcd_ops_t ops; rt_uint8_t num_ports; - uhub_t roothub; + uhub_t roothub; }; typedef struct uhcd* uhcd_t; @@ -149,11 +149,11 @@ typedef enum uhost_msg_type uhost_msg_type; struct uhost_msg { - uhost_msg_type type; + uhost_msg_type type; union { struct uhub* hub; - struct + struct { func_callback function; void *context; @@ -193,14 +193,14 @@ ucd_t rt_usbh_class_driver_storage(void); /* usb hub interface */ -rt_err_t rt_usbh_hub_get_descriptor(struct uinstance* device, rt_uint8_t *buffer, +rt_err_t rt_usbh_hub_get_descriptor(struct uinstance* device, rt_uint8_t *buffer, rt_size_t size); rt_err_t rt_usbh_hub_get_status(struct uinstance* device, rt_uint32_t* buffer); -rt_err_t rt_usbh_hub_get_port_status(uhub_t uhub, rt_uint16_t port, +rt_err_t rt_usbh_hub_get_port_status(uhub_t uhub, rt_uint16_t port, rt_uint32_t* buffer); -rt_err_t rt_usbh_hub_clear_port_feature(uhub_t uhub, rt_uint16_t port, +rt_err_t rt_usbh_hub_clear_port_feature(uhub_t uhub, rt_uint16_t port, rt_uint16_t feature); -rt_err_t rt_usbh_hub_set_port_feature(uhub_t uhub, rt_uint16_t port, +rt_err_t rt_usbh_hub_set_port_feature(uhub_t uhub, rt_uint16_t port, rt_uint16_t feature); rt_err_t rt_usbh_hub_reset_port(uhub_t uhub, rt_uint16_t port); rt_err_t rt_usbh_event_signal(struct uhost_msg* msg); diff --git a/components/drivers/include/drivers/watchdog.h b/components/drivers/include/drivers/watchdog.h index f80ded58aa..1cf3dc741d 100644 --- a/components/drivers/include/drivers/watchdog.h +++ b/components/drivers/include/drivers/watchdog.h @@ -1,6 +1,6 @@ /* * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: diff --git a/components/drivers/include/drivers/wlan.h b/components/drivers/include/drivers/wlan.h index 724e61da78..b5b4f73586 100644 --- a/components/drivers/include/drivers/wlan.h +++ b/components/drivers/include/drivers/wlan.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/include/ipc/completion.h b/components/drivers/include/ipc/completion.h index acfcaa3995..087a9be813 100644 --- a/components/drivers/include/ipc/completion.h +++ b/components/drivers/include/ipc/completion.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/include/ipc/dataqueue.h b/components/drivers/include/ipc/dataqueue.h index 76203c404d..5dd94e55c0 100644 --- a/components/drivers/include/ipc/dataqueue.h +++ b/components/drivers/include/ipc/dataqueue.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/include/ipc/pipe.h b/components/drivers/include/ipc/pipe.h index 93ba95cd2c..a45e8ae002 100644 --- a/components/drivers/include/ipc/pipe.h +++ b/components/drivers/include/ipc/pipe.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/include/ipc/poll.h b/components/drivers/include/ipc/poll.h index 8c68a96af8..1574215c77 100644 --- a/components/drivers/include/ipc/poll.h +++ b/components/drivers/include/ipc/poll.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/include/ipc/ringblk_buf.h b/components/drivers/include/ipc/ringblk_buf.h index 94fc2cfff3..5b2971b800 100644 --- a/components/drivers/include/ipc/ringblk_buf.h +++ b/components/drivers/include/ipc/ringblk_buf.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/include/ipc/ringbuffer.h b/components/drivers/include/ipc/ringbuffer.h index 2afd2ca213..71c4801253 100644 --- a/components/drivers/include/ipc/ringbuffer.h +++ b/components/drivers/include/ipc/ringbuffer.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/include/ipc/waitqueue.h b/components/drivers/include/ipc/waitqueue.h index e26ec1e896..fbf5f93142 100644 --- a/components/drivers/include/ipc/waitqueue.h +++ b/components/drivers/include/ipc/waitqueue.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2018/06/26 Bernard Fix the wait queue issue when wakeup a soon + * 2018/06/26 Bernard Fix the wait queue issue when wakeup a soon * to blocked thread. */ diff --git a/components/drivers/include/ipc/workqueue.h b/components/drivers/include/ipc/workqueue.h index 23e256c420..25451d7e9b 100644 --- a/components/drivers/include/ipc/workqueue.h +++ b/components/drivers/include/ipc/workqueue.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/include/rtdevice.h b/components/drivers/include/rtdevice.h index 623c085430..782a679b02 100644 --- a/components/drivers/include/rtdevice.h +++ b/components/drivers/include/rtdevice.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/misc/adc.c b/components/drivers/misc/adc.c index 2d26beb243..d8f79e058b 100644 --- a/components/drivers/misc/adc.c +++ b/components/drivers/misc/adc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/misc/pin.c b/components/drivers/misc/pin.c index aca58ee21b..0456b909e0 100644 --- a/components/drivers/misc/pin.c +++ b/components/drivers/misc/pin.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/misc/pulse_encoder.c b/components/drivers/misc/pulse_encoder.c index 3145c24675..5afb12664a 100644 --- a/components/drivers/misc/pulse_encoder.c +++ b/components/drivers/misc/pulse_encoder.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/misc/rt_drv_pwm.c b/components/drivers/misc/rt_drv_pwm.c index 97d38d51b3..79fa1c4fbf 100644 --- a/components/drivers/misc/rt_drv_pwm.c +++ b/components/drivers/misc/rt_drv_pwm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/misc/rt_inputcapture.c b/components/drivers/misc/rt_inputcapture.c index d1886186d7..134bbcee96 100644 --- a/components/drivers/misc/rt_inputcapture.c +++ b/components/drivers/misc/rt_inputcapture.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/mtd/mtd_nand.c b/components/drivers/mtd/mtd_nand.c index ae5aa9c172..646625ade5 100644 --- a/components/drivers/mtd/mtd_nand.c +++ b/components/drivers/mtd/mtd_nand.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/mtd/mtd_nor.c b/components/drivers/mtd/mtd_nor.c index b941f9236d..0f6eadeb59 100644 --- a/components/drivers/mtd/mtd_nor.c +++ b/components/drivers/mtd/mtd_nor.c @@ -1,6 +1,6 @@ /* * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: @@ -52,7 +52,7 @@ static rt_err_t _mtd_control(rt_device_t dev, int cmd, void *args) } #ifdef RT_USING_DEVICE_OPS -const static struct rt_device_ops mtd_nor_ops = +const static struct rt_device_ops mtd_nor_ops = { _mtd_init, _mtd_open, diff --git a/components/drivers/pm/pm.c b/components/drivers/pm/pm.c index dd7cc2ae63..a7dbf42c13 100644 --- a/components/drivers/pm/pm.c +++ b/components/drivers/pm/pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -46,7 +46,7 @@ static int _pm_device_suspend(rt_uint8_t mode) { ret = _pm.device_pm[index].ops->suspend(_pm.device_pm[index].device, mode); if(ret != RT_EOK) - break; + break; } } diff --git a/components/drivers/rtc/alarm.c b/components/drivers/rtc/alarm.c index c497ebf727..4fa53dba9e 100644 --- a/components/drivers/rtc/alarm.c +++ b/components/drivers/rtc/alarm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/rtc/rtc.c b/components/drivers/rtc/rtc.c index e17c0fe7dd..3468bcdefe 100644 --- a/components/drivers/rtc/rtc.c +++ b/components/drivers/rtc/rtc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -164,7 +164,7 @@ int rt_rtc_ntp_sync_init(void) } init_ok = RT_TRUE; - + return RT_EOK; } INIT_COMPONENT_EXPORT(rt_rtc_ntp_sync_init); diff --git a/components/drivers/rtc/soft_rtc.c b/components/drivers/rtc/soft_rtc.c index adcbf81fe3..2d10bc51be 100644 --- a/components/drivers/rtc/soft_rtc.c +++ b/components/drivers/rtc/soft_rtc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -55,7 +55,7 @@ static rt_err_t soft_rtc_control(rt_device_t dev, int cmd, void *args) } #ifdef RT_USING_DEVICE_OPS -const static struct rt_device_ops soft_rtc_ops = +const static struct rt_device_ops soft_rtc_ops = { RT_NULL, RT_NULL, diff --git a/components/drivers/sdio/block_dev.c b/components/drivers/sdio/block_dev.c index 602acb9aa7..f2ce09a83f 100644 --- a/components/drivers/sdio/block_dev.c +++ b/components/drivers/sdio/block_dev.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -76,7 +76,7 @@ rt_int32_t mmcsd_num_wr_blocks(struct rt_mmcsd_card *card) timeout_us += data.timeout_clks * 1000 / (card->host->io_cfg.clock / 1000); - if (timeout_us > 100000) + if (timeout_us > 100000) { data.timeout_ns = 100000000; data.timeout_clks = 0; @@ -119,9 +119,9 @@ static rt_err_t rt_mmcsd_req_blk(struct rt_mmcsd_card *card, rt_memset(&data, 0, sizeof(struct rt_mmcsd_data)); req.cmd = &cmd; req.data = &data; - + cmd.arg = sector; - if (!(card->flags & CARD_FLAG_SDHC)) + if (!(card->flags & CARD_FLAG_SDHC)) { cmd.arg <<= 9; } @@ -130,7 +130,7 @@ static rt_err_t rt_mmcsd_req_blk(struct rt_mmcsd_card *card, data.blksize = SECTOR_SIZE; data.blks = blks; - if (blks > 1) + if (blks > 1) { if (!controller_is_spi(card->host) || !dir) { @@ -149,7 +149,7 @@ static rt_err_t rt_mmcsd_req_blk(struct rt_mmcsd_card *card, w_cmd = WRITE_BLOCK; } - if (!dir) + if (!dir) { cmd.cmd_code = r_cmd; data.flags |= DATA_DIR_READ; @@ -164,9 +164,9 @@ static rt_err_t rt_mmcsd_req_blk(struct rt_mmcsd_card *card, data.buf = buf; mmcsd_send_request(host, &req); - if (!controller_is_spi(card->host) && dir != 0) + if (!controller_is_spi(card->host) && dir != 0) { - do + do { rt_int32_t err; @@ -174,7 +174,7 @@ static rt_err_t rt_mmcsd_req_blk(struct rt_mmcsd_card *card, cmd.arg = card->rca << 16; cmd.flags = RESP_R1 | CMD_AC; err = mmcsd_send_cmd(card->host, &cmd, 5); - if (err) + if (err) { LOG_E("error %d requesting status", err); break; @@ -190,7 +190,7 @@ static rt_err_t rt_mmcsd_req_blk(struct rt_mmcsd_card *card, mmcsd_host_unlock(host); - if (cmd.err || data.err || stop.err) + if (cmd.err || data.err || stop.err) { LOG_E("mmcsd request blocks error"); LOG_E("%d,%d,%d, 0x%08x,0x%08x", @@ -264,7 +264,7 @@ static rt_size_t rt_mmcsd_read(rt_device_t dev, rt_sem_release(part->lock); /* the length of reading must align to SECTOR SIZE */ - if (err) + if (err) { rt_set_errno(-EIO); return 0; @@ -305,7 +305,7 @@ static rt_size_t rt_mmcsd_write(rt_device_t dev, rt_sem_release(part->lock); /* the length of reading must align to SECTOR SIZE */ - if (err) + if (err) { rt_set_errno(-EIO); @@ -330,7 +330,7 @@ static rt_int32_t mmcsd_set_blksize(struct rt_mmcsd_card *card) err = mmcsd_send_cmd(card->host, &cmd, 5); mmcsd_host_unlock(card->host); - if (err) + if (err) { LOG_E("MMCSD: unable to set block size to %d: %d", cmd.arg, err); @@ -341,7 +341,7 @@ static rt_int32_t mmcsd_set_blksize(struct rt_mmcsd_card *card) } #ifdef RT_USING_DEVICE_OPS -const static struct rt_device_ops mmcsd_blk_ops = +const static struct rt_device_ops mmcsd_blk_ops = { rt_mmcsd_init, rt_mmcsd_open, @@ -362,7 +362,7 @@ rt_int32_t rt_mmcsd_blk_probe(struct rt_mmcsd_card *card) struct mmcsd_blk_device *blk_dev = RT_NULL; err = mmcsd_set_blksize(card); - if(err) + if(err) { return err; } @@ -384,15 +384,15 @@ rt_int32_t rt_mmcsd_blk_probe(struct rt_mmcsd_card *card) for (i = 0; i < RT_MMCSD_MAX_PARTITION; i++) { blk_dev = rt_calloc(1, sizeof(struct mmcsd_blk_device)); - if (!blk_dev) + if (!blk_dev) { LOG_E("mmcsd:malloc memory failed!"); break; } - blk_dev->max_req_size = BLK_MIN((card->host->max_dma_segs * - card->host->max_seg_size) >> 9, - (card->host->max_blk_count * + blk_dev->max_req_size = BLK_MIN((card->host->max_dma_segs * + card->host->max_seg_size) >> 9, + (card->host->max_blk_count * card->host->max_blk_size) >> 9); /* get the first partition */ @@ -402,7 +402,7 @@ rt_int32_t rt_mmcsd_blk_probe(struct rt_mmcsd_card *card) rt_snprintf(dname, 4, "sd%d", i); rt_snprintf(sname, 8, "sem_sd%d", i); blk_dev->part.lock = rt_sem_create(sname, 1, RT_IPC_FLAG_FIFO); - + /* register mmcsd device */ blk_dev->dev.type = RT_Device_Class_Block; #ifdef RT_USING_DEVICE_OPS @@ -418,11 +418,11 @@ rt_int32_t rt_mmcsd_blk_probe(struct rt_mmcsd_card *card) blk_dev->dev.user_data = blk_dev; blk_dev->card = card; - + blk_dev->geometry.bytes_per_sector = 1<<9; blk_dev->geometry.block_size = card->card_blksize; blk_dev->geometry.sector_count = blk_dev->part.size; - + rt_device_register(&blk_dev->dev, dname, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE); rt_list_insert_after(&blk_devices, &blk_dev->list); @@ -435,7 +435,7 @@ rt_int32_t rt_mmcsd_blk_probe(struct rt_mmcsd_card *card) blk_dev->part.offset = 0; blk_dev->part.size = 0; blk_dev->part.lock = rt_sem_create("sem_sd0", 1, RT_IPC_FLAG_FIFO); - + /* register mmcsd device */ blk_dev->dev.type = RT_Device_Class_Block; #ifdef RT_USING_DEVICE_OPS @@ -454,9 +454,9 @@ rt_int32_t rt_mmcsd_blk_probe(struct rt_mmcsd_card *card) blk_dev->geometry.bytes_per_sector = 1<<9; blk_dev->geometry.block_size = card->card_blksize; - blk_dev->geometry.sector_count = + blk_dev->geometry.sector_count = card->card_capacity * (1024 / 512); - + rt_device_register(&blk_dev->dev, "sd0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE); rt_list_insert_after(&blk_devices, &blk_dev->list); @@ -472,9 +472,9 @@ rt_int32_t rt_mmcsd_blk_probe(struct rt_mmcsd_card *card) #ifdef RT_USING_DFS_MNTTABLE if (blk_dev) { - LOG_I("try to mount file system!"); - /* try to mount file system on this block device */ - dfs_mount_device(&(blk_dev->dev)); + LOG_I("try to mount file system!"); + /* try to mount file system on this block device */ + dfs_mount_device(&(blk_dev->dev)); } #endif } @@ -484,10 +484,10 @@ rt_int32_t rt_mmcsd_blk_probe(struct rt_mmcsd_card *card) LOG_E("read mmcsd first sector failed"); err = -RT_ERROR; } - + /* release sector buffer */ rt_free(sector); - + return err; } @@ -499,15 +499,15 @@ void rt_mmcsd_blk_remove(struct rt_mmcsd_card *card) for (l = (&blk_devices)->next, n = l->next; l != &blk_devices; l = n) { blk_dev = (struct mmcsd_blk_device *)rt_list_entry(l, struct mmcsd_blk_device, list); - if (blk_dev->card == card) + if (blk_dev->card == card) { - /* unmount file system */ - const char * mounted_path = dfs_filesystem_get_mounted_path(&(blk_dev->dev)); - if (mounted_path) - { + /* unmount file system */ + const char * mounted_path = dfs_filesystem_get_mounted_path(&(blk_dev->dev)); + if (mounted_path) + { dfs_unmount(mounted_path); LOG_D("unmount file system %s for device %s.\r\n", mounted_path, blk_dev->dev.parent.name); - } + } rt_sem_delete(blk_dev->part.lock); rt_device_unregister(&blk_dev->dev); rt_list_remove(&blk_dev->list); diff --git a/components/drivers/sdio/mmc.c b/components/drivers/sdio/mmc.c index c1c56d37fd..5aba3dba7a 100644 --- a/components/drivers/sdio/mmc.c +++ b/components/drivers/sdio/mmc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -45,9 +45,9 @@ static const rt_uint8_t tacc_value[] = rt_inline rt_uint32_t GET_BITS(rt_uint32_t *resp, rt_uint32_t start, rt_uint32_t size) -{ +{ const rt_int32_t __size = size; - const rt_uint32_t __mask = (__size < 32 ? 1 << __size : 0) - 1; + const rt_uint32_t __mask = (__size < 32 ? 1 << __size : 0) - 1; const rt_int32_t __off = 3 - ((start) / 32); const rt_int32_t __shft = (start) & 31; rt_uint32_t __res; @@ -67,7 +67,7 @@ static rt_int32_t mmcsd_parse_csd(struct rt_mmcsd_card *card) rt_uint32_t a, b; struct rt_mmcsd_csd *csd = &card->csd; rt_uint32_t *resp = card->resp_csd; - + /* * We only understand CSD structure v1.1 and v1.2. * v1.2 has extra information in bits 15, 11 and 10. @@ -76,10 +76,10 @@ static rt_int32_t mmcsd_parse_csd(struct rt_mmcsd_card *card) csd->csd_structure = GET_BITS(resp, 126, 2); if (csd->csd_structure == 0) { LOG_E("unrecognised CSD structure version %d!", csd->csd_structure); - + return -RT_ERROR; } - + csd->taac = GET_BITS(resp, 112, 8); csd->nsac = GET_BITS(resp, 104, 8); csd->tran_speed = GET_BITS(resp, 96, 8); @@ -95,7 +95,7 @@ static rt_int32_t mmcsd_parse_csd(struct rt_mmcsd_card *card) csd->wr_blk_len = GET_BITS(resp, 22, 4); csd->wr_blk_partial = GET_BITS(resp, 21, 1); csd->csd_crc = GET_BITS(resp, 1, 7); - + card->card_blksize = 1 << csd->rd_blk_len; card->tacc_clks = csd->nsac * 100; card->tacc_ns = (tacc_uint[csd->taac&0x07] * tacc_value[(csd->taac&0x78)>>3] + 9) / 10; @@ -106,7 +106,7 @@ static rt_int32_t mmcsd_parse_csd(struct rt_mmcsd_card *card) card->erase_size = (a + 1) * (b + 1); card->erase_size <<= csd->wr_blk_len - 9; } - + return 0; } @@ -119,12 +119,12 @@ static int mmc_get_ext_csd(struct rt_mmcsd_card *card, rt_uint8_t **new_ext_csd) struct rt_mmcsd_req req; struct rt_mmcsd_cmd cmd; struct rt_mmcsd_data data; - + *new_ext_csd = RT_NULL; - + if (GET_BITS(card->resp_cid, 122, 4) < 4) return 0; - + /* * As the ext_csd is so large and mostly unused, we don't store the * raw block in mmc_card. @@ -134,29 +134,29 @@ static int mmc_get_ext_csd(struct rt_mmcsd_card *card, rt_uint8_t **new_ext_csd) LOG_E("alloc memory failed when get ext csd!"); return -RT_ENOMEM; } - + rt_memset(&req, 0, sizeof(struct rt_mmcsd_req)); rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd)); rt_memset(&data, 0, sizeof(struct rt_mmcsd_data)); - + req.cmd = &cmd; req.data = &data; - + cmd.cmd_code = SEND_EXT_CSD; cmd.arg = 0; - + /* NOTE HACK: the RESP_SPI_R1 is always correct here, but we * rely on callers to never use this with "native" calls for reading * CSD or CID. Native versions of those commands use the R2 type, * not R1 plus a data block. */ cmd.flags = RESP_SPI_R1 | RESP_R1 | CMD_ADTC; - + data.blksize = 512; data.blks = 1; data.flags = DATA_DIR_READ; data.buf = ext_csd; - + /* * Some cards require longer data read timeout than indicated in CSD. * Address this by setting the read timeout to a "reasonably high" @@ -165,14 +165,14 @@ static int mmc_get_ext_csd(struct rt_mmcsd_card *card, rt_uint8_t **new_ext_csd) */ data.timeout_ns = 300000000; data.timeout_clks = 0; - + mmcsd_send_request(card->host, &req); - + if (cmd.err) return cmd.err; if (data.err) return data.err; - + *new_ext_csd = ext_csd; return 0; } @@ -192,13 +192,13 @@ static int mmc_parse_ext_csd(struct rt_mmcsd_card *card, rt_uint8_t *ext_csd) card->flags |= CARD_FLAG_HIGHSPEED; card->hs_max_data_rate = 52000000; - + card_capacity = *((rt_uint32_t *)&ext_csd[EXT_CSD_SEC_CNT]); card_capacity *= card->card_blksize; card_capacity >>= 10; /* unit:KB */ card->card_capacity = card_capacity; LOG_I("emmc card capacity %d KB.", card->card_capacity); - + return 0; } @@ -211,41 +211,41 @@ static int mmc_parse_ext_csd(struct rt_mmcsd_card *card, rt_uint8_t *ext_csd) * * Modifies the EXT_CSD register for selected card. */ -static int mmc_switch(struct rt_mmcsd_card *card, rt_uint8_t set, +static int mmc_switch(struct rt_mmcsd_card *card, rt_uint8_t set, rt_uint8_t index, rt_uint8_t value) { int err; struct rt_mmcsd_host *host = card->host; struct rt_mmcsd_cmd cmd = {0}; - + cmd.cmd_code = SWITCH; cmd.arg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | (index << 16) | (value << 8) | set; cmd.flags = RESP_SPI_R1 | RESP_R1 | CMD_AC; - + err = mmcsd_send_cmd(host, &cmd, 3); if (err) return err; - + return 0; } -static int mmc_compare_ext_csds(struct rt_mmcsd_card *card, +static int mmc_compare_ext_csds(struct rt_mmcsd_card *card, rt_uint8_t *ext_csd, rt_uint32_t bus_width) { rt_uint8_t *bw_ext_csd; int err; - + if (bus_width == MMCSD_BUS_WIDTH_1) return 0; - + err = mmc_get_ext_csd(card, &bw_ext_csd); - + if (err || bw_ext_csd == RT_NULL) { err = -RT_ERROR; goto out; } - + /* only compare read only fields */ err = !((ext_csd[EXT_CSD_PARTITION_SUPPORT] == bw_ext_csd[EXT_CSD_PARTITION_SUPPORT]) && (ext_csd[EXT_CSD_ERASED_MEM_CONT] == bw_ext_csd[EXT_CSD_ERASED_MEM_CONT]) && @@ -273,10 +273,10 @@ static int mmc_compare_ext_csds(struct rt_mmcsd_card *card, (ext_csd[EXT_CSD_PWR_CL_DDR_52_195] == bw_ext_csd[EXT_CSD_PWR_CL_DDR_52_195]) && (ext_csd[EXT_CSD_PWR_CL_DDR_52_360] == bw_ext_csd[EXT_CSD_PWR_CL_DDR_52_360]) && (ext_csd[EXT_CSD_PWR_CL_DDR_200_360] == bw_ext_csd[EXT_CSD_PWR_CL_DDR_200_360])); - + if (err) err = -RT_ERROR; - + out: rt_free(bw_ext_csd); return err; @@ -302,10 +302,10 @@ static int mmc_select_bus_width(struct rt_mmcsd_card *card, rt_uint8_t *ext_csd) struct rt_mmcsd_host *host = card->host; unsigned idx, bus_width = 0; int err = 0; - + if (GET_BITS(card->resp_cid, 122, 4) < 4) return 0; - + /* * Unlike SD, MMC cards dont have a configuration register to notify * supported bus width. So bus test command should be run to identify @@ -323,18 +323,18 @@ static int mmc_select_bus_width(struct rt_mmcsd_card *card, rt_uint8_t *ext_csd) * set by drivers. */ if ((!(host->flags & MMCSD_BUSWIDTH_8) && - ext_csd_bits[idx] == EXT_CSD_BUS_WIDTH_8) || + ext_csd_bits[idx] == EXT_CSD_BUS_WIDTH_8) || (!(host->flags & MMCSD_BUSWIDTH_4) && - (ext_csd_bits[idx] == EXT_CSD_BUS_WIDTH_4 || - ext_csd_bits[idx] == EXT_CSD_BUS_WIDTH_8))) - continue; + (ext_csd_bits[idx] == EXT_CSD_BUS_WIDTH_4 || + ext_csd_bits[idx] == EXT_CSD_BUS_WIDTH_8))) + continue; err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH, ext_csd_bits[idx]); if (err) continue; - + bus_width = bus_widths[idx]; mmcsd_set_bus_width(host, bus_width); mmcsd_delay_ms(20); //delay 10ms @@ -358,10 +358,10 @@ static int mmc_select_bus_width(struct rt_mmcsd_card *card, rt_uint8_t *ext_csd) } } } - + return err; } -rt_err_t mmc_send_op_cond(struct rt_mmcsd_host *host, +rt_err_t mmc_send_op_cond(struct rt_mmcsd_host *host, rt_uint32_t ocr, rt_uint32_t *rocr) { struct rt_mmcsd_cmd cmd; @@ -369,20 +369,20 @@ rt_err_t mmc_send_op_cond(struct rt_mmcsd_host *host, rt_err_t err = RT_EOK; rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd)); - + cmd.cmd_code = SEND_OP_COND; cmd.arg = controller_is_spi(host) ? 0 : ocr; cmd.flags = RESP_SPI_R1 | RESP_R3 | CMD_BCR; - + for (i = 100; i; i--) { err = mmcsd_send_cmd(host, &cmd, 3); if (err) break; - + /* if we're just probing, do a single pass */ if (ocr == 0) break; - + /* otherwise wait until reset completes */ if (controller_is_spi(host)) { if (!(cmd.resp[0] & R1_SPI_IDLE)) @@ -391,15 +391,15 @@ rt_err_t mmc_send_op_cond(struct rt_mmcsd_host *host, if (cmd.resp[0] & CARD_BUSY) break; } - + err = -RT_ETIMEOUT; - + mmcsd_delay_ms(10); //delay 10ms } - + if (rocr && !controller_is_spi(host)) *rocr = cmd.resp[0]; - + return err; } @@ -407,17 +407,17 @@ static rt_err_t mmc_set_card_addr(struct rt_mmcsd_host *host, rt_uint32_t rca) { rt_err_t err; struct rt_mmcsd_cmd cmd; - + rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd)); - + cmd.cmd_code = SET_RELATIVE_ADDR; cmd.arg = rca << 16; cmd.flags = RESP_R1 | CMD_AC; - + err = mmcsd_send_cmd(host, &cmd, 3); if (err) return err; - + return 0; } @@ -432,19 +432,19 @@ static rt_int32_t mmcsd_mmc_init_card(struct rt_mmcsd_host *host, struct rt_mmcsd_card *card = RT_NULL; mmcsd_go_idle(host); - + /* The extra bit indicates that we support high capacity */ err = mmc_send_op_cond(host, ocr | (1 << 30), &rocr); if (err) goto err; - - if (controller_is_spi(host)) + + if (controller_is_spi(host)) { err = mmcsd_spi_use_crc(host, 1); if (err) goto err1; } - + if (controller_is_spi(host)) err = mmcsd_get_cid(host, resp); else @@ -453,7 +453,7 @@ static rt_int32_t mmcsd_mmc_init_card(struct rt_mmcsd_host *host, goto err; card = rt_malloc(sizeof(struct rt_mmcsd_card)); - if (!card) + if (!card) { LOG_E("malloc card failed!"); err = -RT_ENOMEM; @@ -469,7 +469,7 @@ static rt_int32_t mmcsd_mmc_init_card(struct rt_mmcsd_host *host, /* * For native busses: get card RCA and quit open drain mode. */ - if (!controller_is_spi(host)) + if (!controller_is_spi(host)) { err = mmc_set_card_addr(host, card->rca); if (err) @@ -486,24 +486,24 @@ static rt_int32_t mmcsd_mmc_init_card(struct rt_mmcsd_host *host, if (err) goto err1; - if (!controller_is_spi(host)) + if (!controller_is_spi(host)) { err = mmcsd_select_card(card); if (err) goto err1; } - + /* * Fetch and process extended CSD. */ - + err = mmc_get_ext_csd(card, &ext_csd); if (err) goto err1; err = mmc_parse_ext_csd(card, ext_csd); if (err) goto err1; - + /* If doing byte addressing, check if required to do sector * addressing. Handle the case of <2GB cards needing sector * addressing. See section 8.1 JEDEC Standard JED84-A441; @@ -511,9 +511,9 @@ static rt_int32_t mmcsd_mmc_init_card(struct rt_mmcsd_host *host, */ if (!(card->flags & CARD_FLAG_SDHC) && (rocr & (1<<30))) card->flags |= CARD_FLAG_SDHC; - + /* set bus speed */ - if (card->flags & CARD_FLAG_HIGHSPEED) + if (card->flags & CARD_FLAG_HIGHSPEED) max_data_rate = card->hs_max_data_rate; else max_data_rate = card->max_data_rate; @@ -522,7 +522,7 @@ static rt_int32_t mmcsd_mmc_init_card(struct rt_mmcsd_host *host, /*switch bus width*/ mmc_select_bus_width(card, ext_csd); - + host->card = card; rt_free(ext_csd); diff --git a/components/drivers/sdio/mmcsd_core.c b/components/drivers/sdio/mmcsd_core.c index 8131a33133..09481d403a 100644 --- a/components/drivers/sdio/mmcsd_core.c +++ b/components/drivers/sdio/mmcsd_core.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -63,7 +63,7 @@ void mmcsd_send_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) req->cmd->err = 0; req->cmd->mrq = req; if (req->data) - { + { req->cmd->data = req->data; req->data->err = 0; req->data->mrq = req; @@ -72,12 +72,12 @@ void mmcsd_send_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) req->data->stop = req->stop; req->stop->err = 0; req->stop->mrq = req; - } + } } host->ops->request(host, req); rt_sem_take(&host->sem_ack, RT_WAITING_FOREVER); - + } while(req->cmd->err && (req->cmd->retries > 0)); @@ -122,7 +122,7 @@ rt_int32_t mmcsd_go_idle(struct rt_mmcsd_host *host) mmcsd_delay_ms(1); - if (!controller_is_spi(host)) + if (!controller_is_spi(host)) { mmcsd_set_chip_select(host, MMCSD_CS_IGNORE); mmcsd_delay_ms(1); @@ -179,7 +179,7 @@ rt_int32_t mmcsd_get_cid(struct rt_mmcsd_host *host, rt_uint32_t *cid) struct rt_mmcsd_data data; rt_uint32_t *buf = RT_NULL; - if (!controller_is_spi(host)) + if (!controller_is_spi(host)) { if (!host->card) return -RT_ERROR; @@ -198,7 +198,7 @@ rt_int32_t mmcsd_get_cid(struct rt_mmcsd_host *host, rt_uint32_t *cid) } buf = (rt_uint32_t *)rt_malloc(16); - if (!buf) + if (!buf) { LOG_E("allocate memory failed!"); @@ -274,7 +274,7 @@ rt_int32_t mmcsd_get_csd(struct rt_mmcsd_card *card, rt_uint32_t *csd) } buf = (rt_uint32_t*)rt_malloc(16); - if (!buf) + if (!buf) { LOG_E("allocate memory failed!"); @@ -336,12 +336,12 @@ static rt_int32_t _mmcsd_select_card(struct rt_mmcsd_host *host, cmd.cmd_code = SELECT_CARD; - if (card) + if (card) { cmd.arg = card->rca << 16; cmd.flags = RESP_R1 | CMD_AC; - } - else + } + else { cmd.arg = 0; cmd.flags = RESP_NONE | CMD_AC; @@ -442,7 +442,7 @@ void mmcsd_set_data_timeout(struct rt_mmcsd_data *data, { rt_uint32_t mult; - if (card->card_type == CARD_TYPE_SDIO) + if (card->card_type == CARD_TYPE_SDIO) { data->timeout_ns = 1000000000; /* SDIO card 1s */ data->timeout_clks = 0; @@ -468,7 +468,7 @@ void mmcsd_set_data_timeout(struct rt_mmcsd_data *data, /* * SD cards also have an upper limit on the timeout. */ - if (card->card_type == CARD_TYPE_SD) + if (card->card_type == CARD_TYPE_SD) { rt_uint32_t timeout_us, limit_us; @@ -488,21 +488,21 @@ void mmcsd_set_data_timeout(struct rt_mmcsd_data *data, /* * SDHC cards always use these fixed values. */ - if (timeout_us > limit_us || card->flags & CARD_FLAG_SDHC) + if (timeout_us > limit_us || card->flags & CARD_FLAG_SDHC) { data->timeout_ns = limit_us * 1000; /* SDHC card fixed 250ms */ data->timeout_clks = 0; } } - if (controller_is_spi(card->host)) + if (controller_is_spi(card->host)) { - if (data->flags & DATA_DIR_WRITE) + if (data->flags & DATA_DIR_WRITE) { if (data->timeout_ns < 1000000000) data->timeout_ns = 1000000000; /* 1s */ - } - else + } + else { if (data->timeout_ns < 100000000) data->timeout_ns = 100000000; /* 100ms */ @@ -522,7 +522,7 @@ rt_uint32_t mmcsd_select_voltage(struct rt_mmcsd_host *host, rt_uint32_t ocr) ocr &= host->valid_ocr; bit = __rt_ffs(ocr); - if (bit) + if (bit) { bit -= 1; @@ -530,8 +530,8 @@ rt_uint32_t mmcsd_select_voltage(struct rt_mmcsd_host *host, rt_uint32_t ocr) host->io_cfg.vdd = bit; mmcsd_set_iocfg(host); - } - else + } + else { LOG_W("host doesn't support card's voltages!"); ocr = 0; @@ -549,7 +549,7 @@ static void mmcsd_power_up(struct rt_mmcsd_host *host) { host->io_cfg.chip_select = MMCSD_CS_HIGH; host->io_cfg.bus_mode = MMCSD_BUSMODE_PUSHPULL; - } + } else { host->io_cfg.chip_select = MMCSD_CS_IGNORE; @@ -580,7 +580,7 @@ static void mmcsd_power_off(struct rt_mmcsd_host *host) { host->io_cfg.clock = 0; host->io_cfg.vdd = 0; - if (!controller_is_spi(host)) + if (!controller_is_spi(host)) { host->io_cfg.bus_mode = MMCSD_BUSMODE_OPENDRAIN; host->io_cfg.chip_select = MMCSD_CS_IGNORE; @@ -619,7 +619,7 @@ void mmcsd_detect(void *param) rt_uint32_t ocr; rt_int32_t err; - while (1) + while (1) { if (rt_mb_recv(&mmcsd_detect_mb, (rt_ubase_t *)&host, RT_WAITING_FOREVER) == RT_EOK) { @@ -644,7 +644,7 @@ void mmcsd_detect(void *param) * detect SD card */ err = mmcsd_send_app_op_cond(host, 0, &ocr); - if (!err) + if (!err) { if (init_sd(host, ocr)) mmcsd_power_off(host); @@ -652,12 +652,12 @@ void mmcsd_detect(void *param) rt_mb_send(&mmcsd_hotpluge_mb, (rt_uint32_t)host); continue; } - + /* * detect mmc card */ err = mmc_send_op_cond(host, 0, &ocr); - if (!err) + if (!err) { if (init_mmc(host, ocr)) mmcsd_power_off(host); @@ -669,21 +669,21 @@ void mmcsd_detect(void *param) } else { - /* card removed */ - mmcsd_host_lock(host); - if (host->card->sdio_function_num != 0) - { - LOG_W("unsupport sdio card plug out!"); - } - else - { - rt_mmcsd_blk_remove(host->card); - rt_free(host->card); - - host->card = RT_NULL; - } - mmcsd_host_unlock(host); - rt_mb_send(&mmcsd_hotpluge_mb, (rt_uint32_t)host); + /* card removed */ + mmcsd_host_lock(host); + if (host->card->sdio_function_num != 0) + { + LOG_W("unsupport sdio card plug out!"); + } + else + { + rt_mmcsd_blk_remove(host->card); + rt_free(host->card); + + host->card = RT_NULL; + } + mmcsd_host_unlock(host); + rt_mb_send(&mmcsd_hotpluge_mb, (rt_uint32_t)host); } } } @@ -694,7 +694,7 @@ struct rt_mmcsd_host *mmcsd_alloc_host(void) struct rt_mmcsd_host *host; host = rt_malloc(sizeof(struct rt_mmcsd_host)); - if (!host) + if (!host) { LOG_E("alloc host failed"); @@ -736,16 +736,16 @@ int rt_mmcsd_core_init(void) &mmcsd_hotpluge_mb_pool[0], sizeof(mmcsd_hotpluge_mb_pool) / sizeof(mmcsd_hotpluge_mb_pool[0]), RT_IPC_FLAG_FIFO); RT_ASSERT(ret == RT_EOK); - ret = rt_thread_init(&mmcsd_detect_thread, "mmcsd_detect", mmcsd_detect, RT_NULL, + ret = rt_thread_init(&mmcsd_detect_thread, "mmcsd_detect", mmcsd_detect, RT_NULL, &mmcsd_stack[0], RT_MMCSD_STACK_SIZE, RT_MMCSD_THREAD_PREORITY, 20); - if (ret == RT_EOK) + if (ret == RT_EOK) { rt_thread_startup(&mmcsd_detect_thread); } rt_sdio_init(); - return 0; + return 0; } INIT_PREV_EXPORT(rt_mmcsd_core_init); diff --git a/components/drivers/sdio/sd.c b/components/drivers/sdio/sd.c index f7e4e46720..d739ee4eaf 100644 --- a/components/drivers/sdio/sd.c +++ b/components/drivers/sdio/sd.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -45,9 +45,9 @@ static const rt_uint8_t tacc_value[] = rt_inline rt_uint32_t GET_BITS(rt_uint32_t *resp, rt_uint32_t start, rt_uint32_t size) -{ +{ const rt_int32_t __size = size; - const rt_uint32_t __mask = (__size < 32 ? 1 << __size : 0) - 1; + const rt_uint32_t __mask = (__size < 32 ? 1 << __size : 0) - 1; const rt_int32_t __off = 3 - ((start) / 32); const rt_int32_t __shft = (start) & 31; rt_uint32_t __res; @@ -97,7 +97,7 @@ static rt_int32_t mmcsd_parse_csd(struct rt_mmcsd_card *card) case 1: card->flags |= CARD_FLAG_SDHC; - /*This field is fixed to 0Eh, which indicates 1 ms. + /*This field is fixed to 0Eh, which indicates 1 ms. The host should not use TAAC, NSAC, and R2W_FACTOR to calculate timeout and should uses fixed timeout values for read and write operations*/ @@ -157,13 +157,13 @@ static rt_int32_t mmcsd_switch(struct rt_mmcsd_card *card) rt_uint8_t *buf; buf = (rt_uint8_t*)rt_malloc(64); - if (!buf) + if (!buf) { LOG_E("alloc memory failed!"); return -RT_ENOMEM; } - + if (card->card_type != CARD_TYPE_SD) goto err; if (card->scr.sd_version < SCR_SPEC_VER_1) @@ -191,7 +191,7 @@ static rt_int32_t mmcsd_switch(struct rt_mmcsd_card *card) mmcsd_send_request(host, &req); - if (cmd.err || data.err) + if (cmd.err || data.err) { goto err1; } @@ -221,12 +221,12 @@ static rt_int32_t mmcsd_switch(struct rt_mmcsd_card *card) mmcsd_send_request(host, &req); - if (cmd.err || data.err) + if (cmd.err || data.err) { goto err1; } - if ((buf[16] & 0xF) != 1) + if ((buf[16] & 0xF) != 1) { LOG_I("switching card to high speed failed!"); goto err; @@ -255,12 +255,12 @@ static rt_err_t mmcsd_app_cmd(struct rt_mmcsd_host *host, cmd.cmd_code = APP_CMD; - if (card) + if (card) { cmd.arg = card->rca << 16; cmd.flags = RESP_R1 | CMD_AC; - } - else + } + else { cmd.arg = 0; cmd.flags = RESP_R1 | CMD_BCR; @@ -285,7 +285,7 @@ rt_err_t mmcsd_send_app_cmd(struct rt_mmcsd_host *host, { struct rt_mmcsd_req req; - rt_uint32_t i; + rt_uint32_t i; rt_err_t err; err = -RT_ERROR; @@ -294,15 +294,15 @@ rt_err_t mmcsd_send_app_cmd(struct rt_mmcsd_host *host, * We have to resend MMC_APP_CMD for each attempt so * we cannot use the retries field in mmc_command. */ - for (i = 0;i <= retry;i++) + for (i = 0;i <= retry;i++) { rt_memset(&req, 0, sizeof(struct rt_mmcsd_req)); err = mmcsd_app_cmd(host, card); - if (err) + if (err) { /* no point in retrying; no APP commands allowed */ - if (controller_is_spi(host)) + if (controller_is_spi(host)) { if (cmd->resp[0] & R1_SPI_ILLEGAL_COMMAND) break; @@ -324,7 +324,7 @@ rt_err_t mmcsd_send_app_cmd(struct rt_mmcsd_host *host, break; /* no point in retrying illegal APP commands */ - if (controller_is_spi(host)) + if (controller_is_spi(host)) { if (cmd->resp[0] & R1_SPI_ILLEGAL_COMMAND) break; @@ -344,7 +344,7 @@ rt_err_t mmcsd_app_set_bus_width(struct rt_mmcsd_card *card, rt_int32_t width) cmd.cmd_code = SD_APP_SET_BUS_WIDTH; cmd.flags = RESP_R1 | CMD_AC; - switch (width) + switch (width) { case MMCSD_BUS_WIDTH_1: cmd.arg = MMCSD_BUS_WIDTH_1; @@ -380,7 +380,7 @@ rt_err_t mmcsd_send_app_op_cond(struct rt_mmcsd_host *host, cmd.arg = ocr; cmd.flags = RESP_SPI_R1 | RESP_R3 | CMD_BCR; - for (i = 100; i; i--) + for (i = 100; i; i--) { err = mmcsd_send_app_cmd(host, RT_NULL, &cmd, 3); if (err) @@ -391,12 +391,12 @@ rt_err_t mmcsd_send_app_op_cond(struct rt_mmcsd_host *host, break; /* otherwise wait until reset completes */ - if (controller_is_spi(host)) + if (controller_is_spi(host)) { if (!(cmd.resp[0] & R1_SPI_IDLE)) break; - } - else + } + else { if (cmd.resp[0] & CARD_BUSY) break; @@ -544,7 +544,7 @@ static rt_int32_t mmcsd_sd_init_card(struct rt_mmcsd_host *host, goto err; card = rt_malloc(sizeof(struct rt_mmcsd_card)); - if (!card) + if (!card) { LOG_E("malloc card failed!"); err = -RT_ENOMEM; @@ -559,7 +559,7 @@ static rt_int32_t mmcsd_sd_init_card(struct rt_mmcsd_host *host, /* * For native busses: get card RCA and quit open drain mode. */ - if (!controller_is_spi(host)) + if (!controller_is_spi(host)) { err = mmcsd_get_card_addr(host, &card->rca); if (err) @@ -576,7 +576,7 @@ static rt_int32_t mmcsd_sd_init_card(struct rt_mmcsd_host *host, if (err) goto err1; - if (!controller_is_spi(host)) + if (!controller_is_spi(host)) { err = mmcsd_select_card(card); if (err) @@ -589,7 +589,7 @@ static rt_int32_t mmcsd_sd_init_card(struct rt_mmcsd_host *host, mmcsd_parse_scr(card); - if (controller_is_spi(host)) + if (controller_is_spi(host)) { err = mmcsd_spi_use_crc(host, 1); if (err) @@ -606,12 +606,12 @@ static rt_int32_t mmcsd_sd_init_card(struct rt_mmcsd_host *host, /* set bus speed */ max_data_rate = (unsigned int)-1; - if (card->flags & CARD_FLAG_HIGHSPEED) + if (card->flags & CARD_FLAG_HIGHSPEED) { if (max_data_rate > card->hs_max_data_rate) max_data_rate = card->hs_max_data_rate; - } - else if (max_data_rate > card->max_data_rate) + } + else if (max_data_rate > card->max_data_rate) { max_data_rate = card->max_data_rate; } @@ -620,7 +620,7 @@ static rt_int32_t mmcsd_sd_init_card(struct rt_mmcsd_host *host, /*switch bus width*/ if ((host->flags & MMCSD_BUSWIDTH_4) && - (card->scr.sd_bus_widths & SD_SCR_BUS_WIDTH_4)) + (card->scr.sd_bus_widths & SD_SCR_BUS_WIDTH_4)) { err = mmcsd_app_set_bus_width(card, MMCSD_BUS_WIDTH_4); if (err) diff --git a/components/drivers/sdio/sdio.c b/components/drivers/sdio/sdio.c index f5d97cdd08..adad68cf66 100644 --- a/components/drivers/sdio/sdio.c +++ b/components/drivers/sdio/sdio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -73,7 +73,7 @@ rt_int32_t sdio_io_send_op_cond(struct rt_mmcsd_host *host, cmd.arg = ocr; cmd.flags = RESP_SPI_R4 | RESP_R4 | CMD_BCR; - for (i = 100; i; i--) + for (i = 100; i; i--) { err = mmcsd_send_cmd(host, &cmd, 0); if (err) @@ -84,7 +84,7 @@ rt_int32_t sdio_io_send_op_cond(struct rt_mmcsd_host *host, break; /* otherwise wait until reset completes */ - if (controller_is_spi(host)) + if (controller_is_spi(host)) { /* * Both R1_SPI_IDLE and MMC_CARD_BUSY indicate @@ -94,8 +94,8 @@ rt_int32_t sdio_io_send_op_cond(struct rt_mmcsd_host *host, */ if (cmd.resp[1] & CARD_BUSY) break; - } - else + } + else { if (cmd.resp[0] & CARD_BUSY) break; @@ -143,7 +143,7 @@ rt_int32_t sdio_io_rw_direct(struct rt_mmcsd_card *card, if (err) return err; - if (!controller_is_spi(card->host)) + if (!controller_is_spi(card->host)) { if (cmd.resp[0] & R5_ERROR) return -RT_EIO; @@ -153,7 +153,7 @@ rt_int32_t sdio_io_rw_direct(struct rt_mmcsd_card *card, return -RT_ERROR; } - if (!rw || raw) + if (!rw || raw) { if (controller_is_spi(card->host)) *pdata = (cmd.resp[0] >> 8) & 0xFF; @@ -218,7 +218,7 @@ rt_int32_t sdio_io_rw_extended(struct rt_mmcsd_card *card, if (data.err) return data.err; - if (!controller_is_spi(card->host)) + if (!controller_is_spi(card->host)) { if (cmd.resp[0] & R5_ERROR) return -RT_EIO; @@ -250,7 +250,7 @@ rt_int32_t sdio_io_rw_extended_block(struct rt_sdio_function *func, rt_int32_t ret; rt_uint32_t left_size; rt_uint32_t max_blks, blks; - + left_size = len; /* Do the bulk of the transfer using block mode (if supported). */ @@ -267,7 +267,7 @@ rt_int32_t sdio_io_rw_extended_block(struct rt_sdio_function *func, blks = max_blks; len = blks * func->cur_blk_size; - ret = sdio_io_rw_extended(func->card, rw, func->num, + ret = sdio_io_rw_extended(func->card, rw, func->num, addr, op_code, buf, blks, func->cur_blk_size); if (ret) return ret; @@ -283,7 +283,7 @@ rt_int32_t sdio_io_rw_extended_block(struct rt_sdio_function *func, { len = MIN(left_size, sdio_max_block_size(func)); - ret = sdio_io_rw_extended(func->card, rw, func->num, + ret = sdio_io_rw_extended(func->card, rw, func->num, addr, op_code, buf, 1, len); if (ret) return ret; @@ -297,7 +297,7 @@ rt_int32_t sdio_io_rw_extended_block(struct rt_sdio_function *func, return 0; } -rt_uint8_t sdio_io_readb(struct rt_sdio_function *func, +rt_uint8_t sdio_io_readb(struct rt_sdio_function *func, rt_uint32_t reg, rt_int32_t *err) { @@ -314,7 +314,7 @@ rt_uint8_t sdio_io_readb(struct rt_sdio_function *func, return data; } -rt_int32_t sdio_io_writeb(struct rt_sdio_function *func, +rt_int32_t sdio_io_writeb(struct rt_sdio_function *func, rt_uint32_t reg, rt_uint8_t data) { @@ -332,7 +332,7 @@ rt_uint16_t sdio_io_readw(struct rt_sdio_function *func, *err = 0; ret = sdio_io_rw_extended_block(func, 0, addr, 1, (rt_uint8_t *)&dmabuf, 2); - if (ret) + if (ret) { if (err) *err = ret; @@ -361,7 +361,7 @@ rt_uint32_t sdio_io_readl(struct rt_sdio_function *func, *err = 0; ret = sdio_io_rw_extended_block(func, 0, addr, 1, (rt_uint8_t *)&dmabuf, 4); - if (ret) + if (ret) { if (err) *err = ret; @@ -379,7 +379,7 @@ rt_int32_t sdio_io_writel(struct rt_sdio_function *func, return sdio_io_rw_extended_block(func, 1, addr, 1, (rt_uint8_t *)&dmabuf, 4); } -rt_int32_t sdio_io_read_multi_fifo_b(struct rt_sdio_function *func, +rt_int32_t sdio_io_read_multi_fifo_b(struct rt_sdio_function *func, rt_uint32_t addr, rt_uint8_t *buf, rt_uint32_t len) @@ -387,7 +387,7 @@ rt_int32_t sdio_io_read_multi_fifo_b(struct rt_sdio_function *func, return sdio_io_rw_extended_block(func, 0, addr, 0, buf, len); } -rt_int32_t sdio_io_write_multi_fifo_b(struct rt_sdio_function *func, +rt_int32_t sdio_io_write_multi_fifo_b(struct rt_sdio_function *func, rt_uint32_t addr, rt_uint8_t *buf, rt_uint32_t len) @@ -395,7 +395,7 @@ rt_int32_t sdio_io_write_multi_fifo_b(struct rt_sdio_function *func, return sdio_io_rw_extended_block(func, 1, addr, 0, buf, len); } -rt_int32_t sdio_io_read_multi_incr_b(struct rt_sdio_function *func, +rt_int32_t sdio_io_read_multi_incr_b(struct rt_sdio_function *func, rt_uint32_t addr, rt_uint8_t *buf, rt_uint32_t len) @@ -403,7 +403,7 @@ rt_int32_t sdio_io_read_multi_incr_b(struct rt_sdio_function *func, return sdio_io_rw_extended_block(func, 0, addr, 1, buf, len); } -rt_int32_t sdio_io_write_multi_incr_b(struct rt_sdio_function *func, +rt_int32_t sdio_io_write_multi_incr_b(struct rt_sdio_function *func, rt_uint32_t addr, rt_uint8_t *buf, rt_uint32_t len) @@ -425,7 +425,7 @@ static rt_int32_t sdio_read_cccr(struct rt_mmcsd_card *card) cccr_version = data & 0x0f; - if (cccr_version > SDIO_CCCR_REV_3_00) + if (cccr_version > SDIO_CCCR_REV_3_00) { LOG_E("unrecognised CCCR structure version %d", cccr_version); @@ -447,7 +447,7 @@ static rt_int32_t sdio_read_cccr(struct rt_mmcsd_card *card) if (data & SDIO_CCCR_CAP_4BLS) card->cccr.bus_width = 1; - if (cccr_version >= SDIO_CCCR_REV_1_10) + if (cccr_version >= SDIO_CCCR_REV_1_10) { data = sdio_io_readb(card->sdio_function[0], SDIO_REG_CCCR_POWER_CTRL, &ret); if (ret) @@ -457,7 +457,7 @@ static rt_int32_t sdio_read_cccr(struct rt_mmcsd_card *card) card->cccr.power_ctrl = 1; } - if (cccr_version >= SDIO_CCCR_REV_1_20) + if (cccr_version >= SDIO_CCCR_REV_1_20) { data = sdio_io_readb(card->sdio_function[0], SDIO_REG_CCCR_SPEED, &ret); if (ret) @@ -528,7 +528,7 @@ static rt_int32_t sdio_read_cis(struct rt_sdio_function *func) for (i = 0; i < 3; i++) { - data = sdio_io_readb(func0, + data = sdio_io_readb(func0, SDIO_REG_FBR_BASE(func->num) + SDIO_REG_FBR_CIS + i, &ret); if (ret) return ret; @@ -557,13 +557,13 @@ static rt_int32_t sdio_read_cis(struct rt_sdio_function *func) return -RT_ENOMEM; curr->data = (rt_uint8_t *)curr + sizeof(struct rt_sdio_function_tuple); - for (i = 0; i < tpl_link; i++) + for (i = 0; i < tpl_link; i++) { curr->data[i] = sdio_io_readb(func0, cisptr + i, &ret); if (ret) break; } - if (ret) + if (ret) { rt_free(curr); break; @@ -611,7 +611,7 @@ static rt_int32_t sdio_read_cis(struct rt_sdio_function *func) LOG_D("CISTPL_VERS_1 too short"); } break; - default: + default: /* this tuple is unknown to the core */ curr->next = RT_NULL; curr->code = tpl_code; @@ -644,7 +644,7 @@ void sdio_free_cis(struct rt_sdio_function *func) tuple = func->tuples; - while (tuple && ((tuple != card->sdio_function[0]->tuples) || (!func->num))) + while (tuple && ((tuple != card->sdio_function[0]->tuples) || (!func->num))) { tmp = tuple; tuple = tuple->next; @@ -660,16 +660,16 @@ static rt_int32_t sdio_read_fbr(struct rt_sdio_function *func) rt_uint8_t data; struct rt_sdio_function *func0 = func->card->sdio_function[0]; - data = sdio_io_readb(func0, + data = sdio_io_readb(func0, SDIO_REG_FBR_BASE(func->num) + SDIO_REG_FBR_STD_FUNC_IF, &ret); if (ret) goto err; data &= 0x0f; - if (data == 0x0f) + if (data == 0x0f) { - data = sdio_io_readb(func0, + data = sdio_io_readb(func0, SDIO_REG_FBR_BASE(func->num) + SDIO_REG_FBR_STD_IF_EXT, &ret); if (ret) goto err; @@ -828,7 +828,7 @@ static rt_int32_t sdio_init_card(struct rt_mmcsd_host *host, rt_uint32_t ocr) if (err) goto err; - if (controller_is_spi(host)) + if (controller_is_spi(host)) { err = mmcsd_spi_use_crc(host, host->spi_use_crc); if (err) @@ -838,7 +838,7 @@ static rt_int32_t sdio_init_card(struct rt_mmcsd_host *host, rt_uint32_t ocr) function_num = (cmd5_resp & 0x70000000) >> 28; card = rt_malloc(sizeof(struct rt_mmcsd_card)); - if (!card) + if (!card) { LOG_E("malloc card failed"); err = -RT_ENOMEM; @@ -862,7 +862,7 @@ static rt_int32_t sdio_init_card(struct rt_mmcsd_host *host, rt_uint32_t ocr) card->sdio_function[0]->card = card; card->sdio_function[0]->num = 0; - if (!controller_is_spi(host)) + if (!controller_is_spi(host)) { err = mmcsd_get_card_addr(host, &card->rca); if (err) @@ -871,7 +871,7 @@ static rt_int32_t sdio_init_card(struct rt_mmcsd_host *host, rt_uint32_t ocr) mmcsd_set_bus_mode(host, MMCSD_BUSMODE_PUSHPULL); } - if (!controller_is_spi(host)) + if (!controller_is_spi(host)) { err = mmcsd_select_card(card); if (err) @@ -890,7 +890,7 @@ static rt_int32_t sdio_init_card(struct rt_mmcsd_host *host, rt_uint32_t ocr) if (err) goto err2; - if (card->flags & CARD_FLAG_HIGHSPEED) + if (card->flags & CARD_FLAG_HIGHSPEED) { mmcsd_set_clock(host, card->host->freq_max > 50000000 ? 50000000 : card->host->freq_max); } @@ -903,7 +903,7 @@ static rt_int32_t sdio_init_card(struct rt_mmcsd_host *host, rt_uint32_t ocr) if (err) goto err2; - for (i = 1; i < function_num + 1; i++) + for (i = 1; i < function_num + 1; i++) { err = sdio_initialize_function(card, i); if (err) @@ -950,7 +950,7 @@ err1: } err: LOG_E("error %d while initialising SDIO card", err); - + return err; } @@ -961,13 +961,13 @@ rt_int32_t init_sdio(struct rt_mmcsd_host *host, rt_uint32_t ocr) RT_ASSERT(host != RT_NULL); - if (ocr & 0x7F) + if (ocr & 0x7F) { LOG_W("Card ocr below the defined voltage rang."); ocr &= ~0x7F; } - if (ocr & VDD_165_195) + if (ocr & VDD_165_195) { LOG_W("Can't support the low voltage SDIO card."); ocr &= ~VDD_165_195; @@ -975,7 +975,7 @@ rt_int32_t init_sdio(struct rt_mmcsd_host *host, rt_uint32_t ocr) current_ocr = mmcsd_select_voltage(host, ocr); - if (!current_ocr) + if (!current_ocr) { err = -RT_ERROR; goto err; @@ -1007,35 +1007,35 @@ static void sdio_irq_thread(void *param) card = host->card; RT_ASSERT(card != RT_NULL); - while (1) + while (1) { if (rt_sem_take(host->sdio_irq_sem, RT_WAITING_FOREVER) == RT_EOK) { mmcsd_host_lock(host); - pending = sdio_io_readb(host->card->sdio_function[0], + pending = sdio_io_readb(host->card->sdio_function[0], SDIO_REG_CCCR_INT_PEND, &ret); - if (ret) + if (ret) { mmcsd_dbg("error %d reading SDIO_REG_CCCR_INT_PEND\n", ret); goto out; } - for (i = 1; i <= 7; i++) + for (i = 1; i <= 7; i++) { - if (pending & (1 << i)) + if (pending & (1 << i)) { struct rt_sdio_function *func = card->sdio_function[i]; - if (!func) + if (!func) { mmcsd_dbg("pending IRQ for " "non-existant function %d\n", func->num); goto out; - } - else if (func->irq_handler) + } + else if (func->irq_handler) { func->irq_handler(func); - } - else + } + else { mmcsd_dbg("pending IRQ with no register handler\n"); goto out; @@ -1063,9 +1063,9 @@ static rt_int32_t sdio_irq_thread_create(struct rt_mmcsd_card *card) host->sdio_irq_sem = rt_sem_create("sdio_irq", 0, RT_IPC_FLAG_FIFO); RT_ASSERT(host->sdio_irq_sem != RT_NULL); - host->sdio_irq_thread = rt_thread_create("sdio_irq", sdio_irq_thread, host, + host->sdio_irq_thread = rt_thread_create("sdio_irq", sdio_irq_thread, host, RT_SDIO_STACK_SIZE, RT_SDIO_THREAD_PRIORITY, 20); - if (host->sdio_irq_thread != RT_NULL) + if (host->sdio_irq_thread != RT_NULL) { rt_thread_startup(host->sdio_irq_thread); } @@ -1081,7 +1081,7 @@ static rt_int32_t sdio_irq_thread_delete(struct rt_mmcsd_card *card) RT_ASSERT(host->sdio_irq_num > 0); host->sdio_irq_num--; - if (!host->sdio_irq_num) + if (!host->sdio_irq_num) { if (host->flags & MMCSD_SUP_SDIO_IRQ) host->ops->enable_sdio_irq(host, 0); @@ -1108,7 +1108,7 @@ rt_int32_t sdio_attach_irq(struct rt_sdio_function *func, mmcsd_dbg("SDIO: enabling IRQ for function %d\n", func->num); - if (func->irq_handler) + if (func->irq_handler) { mmcsd_dbg("SDIO: IRQ for already in use.\n"); @@ -1149,7 +1149,7 @@ rt_int32_t sdio_detach_irq(struct rt_sdio_function *func) mmcsd_dbg("SDIO: disabling IRQ for function %d\n", func->num); - if (func->irq_handler) + if (func->irq_handler) { func->irq_handler = RT_NULL; sdio_irq_thread_delete(func->card); @@ -1206,7 +1206,7 @@ rt_int32_t sdio_enable_func(struct rt_sdio_function *func) timeout = rt_tick_get() + func->enable_timeout_val * RT_TICK_PER_SECOND / 1000; - while (1) + while (1) { reg = sdio_io_readb(func0, SDIO_REG_CCCR_IO_RDY, &ret); if (ret) @@ -1278,17 +1278,17 @@ rt_int32_t sdio_set_block_size(struct rt_sdio_function *func, if (blksize > func->card->host->max_blk_size) return -RT_ERROR; - if (blksize == 0) + if (blksize == 0) { blksize = MIN(func->max_blk_size, func->card->host->max_blk_size); blksize = MIN(blksize, 512u); } - ret = sdio_io_writeb(func0, SDIO_REG_FBR_BASE(func->num) + SDIO_REG_FBR_BLKSIZE, + ret = sdio_io_writeb(func0, SDIO_REG_FBR_BASE(func->num) + SDIO_REG_FBR_BLKSIZE, blksize & 0xff); if (ret) return ret; - ret = sdio_io_writeb(func0, SDIO_REG_FBR_BASE(func->num) + SDIO_REG_FBR_BLKSIZE + 1, + ret = sdio_io_writeb(func0, SDIO_REG_FBR_BASE(func->num) + SDIO_REG_FBR_BLKSIZE + 1, (blksize >> 8) & 0xff); if (ret) return ret; @@ -1301,14 +1301,14 @@ rt_inline rt_int32_t sdio_match_card(struct rt_mmcsd_card *card, const struct rt_sdio_device_id *id) { rt_uint8_t num = 1; - - if ((id->manufacturer != SDIO_ANY_MAN_ID) && + + if ((id->manufacturer != SDIO_ANY_MAN_ID) && (id->manufacturer != card->cis.manufacturer)) return 0; - + while (num <= card->sdio_function_num) { - if ((id->product != SDIO_ANY_PROD_ID) && + if ((id->product != SDIO_ANY_PROD_ID) && (id->product == card->sdio_function[num]->product)) return 1; num++; diff --git a/components/drivers/sensors/sensor.c b/components/drivers/sensors/sensor.c index fbe64c81f2..c7efce62bd 100644 --- a/components/drivers/sensors/sensor.c +++ b/components/drivers/sensors/sensor.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/sensors/sensor.h b/components/drivers/sensors/sensor.h index f9470ecb0d..08c0d2eacd 100644 --- a/components/drivers/sensors/sensor.h +++ b/components/drivers/sensors/sensor.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -153,7 +153,7 @@ struct rt_sensor_device const struct rt_sensor_ops *ops; /* The sensor ops */ struct rt_sensor_module *module; /* The sensor module */ - + rt_err_t (*irq_handle)(rt_sensor_t sensor); /* Called when an interrupt is generated, registered by the driver */ }; diff --git a/components/drivers/sensors/sensor_cmd.c b/components/drivers/sensors/sensor_cmd.c index dd1aa1ef95..ef53be978a 100644 --- a/components/drivers/sensors/sensor_cmd.c +++ b/components/drivers/sensors/sensor_cmd.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -69,7 +69,7 @@ static void sensor_fifo_rx_entry(void *parameter) struct rt_sensor_data *data = RT_NULL; struct rt_sensor_info info; rt_size_t res, i; - + rt_device_control(dev, RT_SENSOR_CTRL_GET_INFO, &info); data = (struct rt_sensor_data *)rt_malloc(sizeof(struct rt_sensor_data) * info.fifo_max); @@ -103,7 +103,7 @@ static void sensor_fifo(int argc, char **argv) return; } sensor = (rt_sensor_t)dev; - + if (rt_device_open(dev, RT_DEVICE_FLAG_FIFO_RX) != RT_EOK) { LOG_E("open device failed!"); diff --git a/components/drivers/serial/serial.c b/components/drivers/serial/serial.c index 5e0af51425..8c3c06f9ac 100644 --- a/components/drivers/serial/serial.c +++ b/components/drivers/serial/serial.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -457,7 +457,7 @@ static void rt_dma_recv_update_put_index(struct rt_serial_device *serial, rt_siz rx_fifo->is_full = RT_TRUE; } } - + if(rx_fifo->is_full == RT_TRUE) { _serial_check_buffer_size(); @@ -612,7 +612,7 @@ static rt_err_t rt_serial_open(struct rt_device *dev, rt_uint16_t oflag) /* initialize the Rx/Tx structure according to open flag */ if (serial->serial_rx == RT_NULL) - { + { if (oflag & RT_DEVICE_FLAG_INT_RX) { struct rt_serial_rx_fifo* rx_fifo; @@ -631,7 +631,7 @@ static rt_err_t rt_serial_open(struct rt_device *dev, rt_uint16_t oflag) /* configure low level device */ serial->ops->control(serial, RT_DEVICE_CTRL_SET_INT, (void *)RT_DEVICE_FLAG_INT_RX); } -#ifdef RT_SERIAL_USING_DMA +#ifdef RT_SERIAL_USING_DMA else if (oflag & RT_DEVICE_FLAG_DMA_RX) { if (serial->config.bufsz == 0) { @@ -672,7 +672,7 @@ static rt_err_t rt_serial_open(struct rt_device *dev, rt_uint16_t oflag) #ifdef RT_SERIAL_USING_DMA else if (oflag & RT_DEVICE_FLAG_DMA_RX) dev->open_flag |= RT_DEVICE_FLAG_DMA_RX; -#endif /* RT_SERIAL_USING_DMA */ +#endif /* RT_SERIAL_USING_DMA */ } if (serial->serial_tx == RT_NULL) @@ -720,7 +720,7 @@ static rt_err_t rt_serial_open(struct rt_device *dev, rt_uint16_t oflag) #ifdef RT_SERIAL_USING_DMA else if (oflag & RT_DEVICE_FLAG_DMA_TX) dev->open_flag |= RT_DEVICE_FLAG_DMA_TX; -#endif /* RT_SERIAL_USING_DMA */ +#endif /* RT_SERIAL_USING_DMA */ } /* set stream flag */ @@ -778,7 +778,7 @@ static rt_err_t rt_serial_close(struct rt_device *dev) serial->ops->control(serial, RT_DEVICE_CTRL_CLR_INT, (void *) RT_DEVICE_FLAG_DMA_RX); } #endif /* RT_SERIAL_USING_DMA */ - + if (dev->open_flag & RT_DEVICE_FLAG_INT_TX) { struct rt_serial_tx_fifo* tx_fifo; @@ -839,7 +839,7 @@ static rt_size_t rt_serial_read(struct rt_device *dev, { return _serial_dma_rx(serial, (rt_uint8_t *)buffer, size); } -#endif /* RT_SERIAL_USING_DMA */ +#endif /* RT_SERIAL_USING_DMA */ return _serial_poll_rx(serial, (rt_uint8_t *)buffer, size); } @@ -860,7 +860,7 @@ static rt_size_t rt_serial_write(struct rt_device *dev, { return _serial_int_tx(serial, (const rt_uint8_t *)buffer, size); } -#ifdef RT_SERIAL_USING_DMA +#ifdef RT_SERIAL_USING_DMA else if (dev->open_flag & RT_DEVICE_FLAG_DMA_TX) { return _serial_dma_tx(serial, (const rt_uint8_t *)buffer, size); @@ -1126,7 +1126,7 @@ static rt_err_t rt_serial_control(struct rt_device *dev, } #ifdef RT_USING_DEVICE_OPS -const static struct rt_device_ops serial_ops = +const static struct rt_device_ops serial_ops = { rt_serial_init, rt_serial_open, diff --git a/components/drivers/spi/enc28j60.c b/components/drivers/spi/enc28j60.c index a8bfe3a159..f99719245b 100644 --- a/components/drivers/spi/enc28j60.c +++ b/components/drivers/spi/enc28j60.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -747,7 +747,7 @@ static struct pbuf *enc28j60_rx(rt_device_t dev) } #ifdef RT_USING_DEVICE_OPS -const static struct rt_device_ops enc28j60_ops = +const static struct rt_device_ops enc28j60_ops = { enc28j60_init, enc28j60_open, diff --git a/components/drivers/spi/enc28j60.h b/components/drivers/spi/enc28j60.h index adff774748..471b71ec2d 100644 --- a/components/drivers/spi/enc28j60.h +++ b/components/drivers/spi/enc28j60.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/spi/qspi_core.c b/components/drivers/spi/qspi_core.c index c9ff6a9637..ca2cba0aba 100644 --- a/components/drivers/spi/qspi_core.c +++ b/components/drivers/spi/qspi_core.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,7 +14,7 @@ rt_err_t rt_qspi_configure(struct rt_qspi_device *device, struct rt_qspi_configu { RT_ASSERT(device != RT_NULL); RT_ASSERT(cfg != RT_NULL); - + struct rt_qspi_device *qspi_device = (struct rt_qspi_device *)device; rt_err_t result = RT_EOK; @@ -35,14 +35,14 @@ rt_err_t rt_qspi_configure(struct rt_qspi_device *device, struct rt_qspi_configu rt_err_t rt_qspi_bus_register(struct rt_spi_bus *bus, const char *name, const struct rt_spi_ops *ops) { rt_err_t result = RT_EOK; - + result = rt_spi_bus_register(bus, name, ops); if(result == RT_EOK) { /* set SPI bus to qspi modes */ bus->mode = RT_SPI_BUS_MODE_QSPI; } - + return result; } @@ -243,7 +243,7 @@ rt_err_t rt_qspi_send(struct rt_qspi_device *device, const void *send_buf, rt_si message.qspi_data_lines = 0; } - + /* set send buf and send size */ message.parent.send_buf = ptr + count; message.parent.recv_buf = RT_NULL; diff --git a/components/drivers/spi/spi_core.c b/components/drivers/spi/spi_core.c index 64b0d2e496..7b6b7a0763 100644 --- a/components/drivers/spi/spi_core.c +++ b/components/drivers/spi/spi_core.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/spi/spi_dev.c b/components/drivers/spi/spi_dev.c index e334e7aeb5..264f5d1856 100644 --- a/components/drivers/spi/spi_dev.c +++ b/components/drivers/spi/spi_dev.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -48,7 +48,7 @@ static rt_err_t _spi_bus_device_control(rt_device_t dev, { case 0: /* set device */ break; - case 1: + case 1: break; } @@ -56,7 +56,7 @@ static rt_err_t _spi_bus_device_control(rt_device_t dev, } #ifdef RT_USING_DEVICE_OPS -const static struct rt_device_ops spi_bus_ops = +const static struct rt_device_ops spi_bus_ops = { RT_NULL, RT_NULL, @@ -129,7 +129,7 @@ static rt_err_t _spidev_device_control(rt_device_t dev, { case 0: /* set device */ break; - case 1: + case 1: break; } @@ -137,7 +137,7 @@ static rt_err_t _spidev_device_control(rt_device_t dev, } #ifdef RT_USING_DEVICE_OPS -const static struct rt_device_ops spi_device_ops = +const static struct rt_device_ops spi_device_ops = { RT_NULL, RT_NULL, diff --git a/components/drivers/spi/spi_flash.h b/components/drivers/spi/spi_flash.h index 30db32474a..d4b0277bf0 100644 --- a/components/drivers/spi/spi_flash.h +++ b/components/drivers/spi/spi_flash.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -25,10 +25,10 @@ typedef struct spi_flash_device *rt_spi_flash_device_t; #ifdef RT_USING_MTD_NOR struct spi_flash_mtd { - struct rt_mtd_nor_device mtd_device; - struct rt_spi_device * rt_spi_device; - struct rt_mutex lock; - void * user_data; + struct rt_mtd_nor_device mtd_device; + struct rt_spi_device * rt_spi_device; + struct rt_mutex lock; + void * user_data; }; #endif diff --git a/components/drivers/spi/spi_flash_sfud.c b/components/drivers/spi/spi_flash_sfud.c index 2333c9ccb3..ba673edf62 100644 --- a/components/drivers/spi/spi_flash_sfud.c +++ b/components/drivers/spi/spi_flash_sfud.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/spi/spi_flash_sfud.h b/components/drivers/spi/spi_flash_sfud.h index 932b7f879c..0d5a751d0c 100644 --- a/components/drivers/spi/spi_flash_sfud.h +++ b/components/drivers/spi/spi_flash_sfud.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/spi/spi_msd.c b/components/drivers/spi/spi_msd.c index 191933e421..875ae3c486 100644 --- a/components/drivers/spi/spi_msd.c +++ b/components/drivers/spi/spi_msd.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -435,7 +435,7 @@ static rt_err_t _write_block(struct rt_spi_device *device, const void *buffer, u } #ifdef RT_USING_DEVICE_OPS -const static struct rt_device_ops msd_ops = +const static struct rt_device_ops msd_ops = { rt_msd_init, rt_msd_open, @@ -445,7 +445,7 @@ const static struct rt_device_ops msd_ops = rt_msd_control }; -const static struct rt_device_ops msd_sdhc_ops = +const static struct rt_device_ops msd_sdhc_ops = { rt_msd_init, rt_msd_open, diff --git a/components/drivers/spi/spi_msd.h b/components/drivers/spi/spi_msd.h index 6370170923..e9febca781 100644 --- a/components/drivers/spi/spi_msd.h +++ b/components/drivers/spi/spi_msd.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -93,12 +93,12 @@ */ typedef enum { - MSD_CARD_TYPE_UNKNOWN = 0, /**< unknown */ - MSD_CARD_TYPE_MMC, /**< MultiMedia Card */ - MSD_CARD_TYPE_SD_V1_X, /**< Ver 1.X Standard Capacity SD Memory Card */ - MSD_CARD_TYPE_SD_V2_X, /**< Ver 2.00 or later Standard Capacity SD Memory Card */ - MSD_CARD_TYPE_SD_SDHC, /**< High Capacity SD Memory Card */ - MSD_CARD_TYPE_SD_SDXC, /**< later Extended Capacity SD Memory Card */ + MSD_CARD_TYPE_UNKNOWN = 0, /**< unknown */ + MSD_CARD_TYPE_MMC, /**< MultiMedia Card */ + MSD_CARD_TYPE_SD_V1_X, /**< Ver 1.X Standard Capacity SD Memory Card */ + MSD_CARD_TYPE_SD_V2_X, /**< Ver 2.00 or later Standard Capacity SD Memory Card */ + MSD_CARD_TYPE_SD_SDHC, /**< High Capacity SD Memory Card */ + MSD_CARD_TYPE_SD_SDXC, /**< later Extended Capacity SD Memory Card */ }msd_card_type; typedef enum diff --git a/components/drivers/spi/spi_wifi_rw009.c b/components/drivers/spi/spi_wifi_rw009.c index 4ddd18ca12..388812d4f3 100644 --- a/components/drivers/spi/spi_wifi_rw009.c +++ b/components/drivers/spi/spi_wifi_rw009.c @@ -1,6 +1,6 @@ /* * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: diff --git a/components/drivers/spi/spi_wifi_rw009.h b/components/drivers/spi/spi_wifi_rw009.h index 049b0a8486..89ed17fb2b 100644 --- a/components/drivers/spi/spi_wifi_rw009.h +++ b/components/drivers/spi/spi_wifi_rw009.h @@ -1,6 +1,6 @@ /* * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: diff --git a/components/drivers/src/completion.c b/components/drivers/src/completion.c index 9e461e49ce..b91ae3d6dc 100644 --- a/components/drivers/src/completion.c +++ b/components/drivers/src/completion.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/src/dataqueue.c b/components/drivers/src/dataqueue.c index 1651417bb9..f32efa1849 100644 --- a/components/drivers/src/dataqueue.c +++ b/components/drivers/src/dataqueue.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -62,7 +62,7 @@ rt_err_t rt_data_queue_push(struct rt_data_queue *queue, rt_ubase_t level; rt_thread_t thread; rt_err_t result; - + RT_ASSERT(queue != RT_NULL); RT_ASSERT(queue->magic == DATAQUEUE_MAGIC); @@ -85,7 +85,7 @@ rt_err_t rt_data_queue_push(struct rt_data_queue *queue, /* reset thread error number */ thread->error = RT_EOK; - + /* suspend thread on the push list */ rt_thread_suspend(thread); rt_list_insert_before(&(queue->suspended_push_list), &(thread->tlist)); @@ -155,13 +155,13 @@ RTM_EXPORT(rt_data_queue_push); rt_err_t rt_data_queue_pop(struct rt_data_queue *queue, const void** data_ptr, - rt_size_t *size, + rt_size_t *size, rt_int32_t timeout) { rt_ubase_t level; rt_thread_t thread; rt_err_t result; - + RT_ASSERT(queue != RT_NULL); RT_ASSERT(queue->magic == DATAQUEUE_MAGIC); RT_ASSERT(data_ptr != RT_NULL); @@ -185,7 +185,7 @@ rt_err_t rt_data_queue_pop(struct rt_data_queue *queue, /* reset thread error number */ thread->error = RT_EOK; - + /* suspend thread on the pop list */ rt_thread_suspend(thread); rt_list_insert_before(&(queue->suspended_pop_list), &(thread->tlist)); @@ -269,11 +269,11 @@ rt_err_t rt_data_queue_peek(struct rt_data_queue *queue, rt_size_t *size) { rt_ubase_t level; - + RT_ASSERT(queue != RT_NULL); RT_ASSERT(queue->magic == DATAQUEUE_MAGIC); - if (queue->is_empty) + if (queue->is_empty) { return -RT_EEMPTY; } @@ -293,7 +293,7 @@ void rt_data_queue_reset(struct rt_data_queue *queue) { rt_ubase_t level; struct rt_thread *thread; - + RT_ASSERT(queue != RT_NULL); RT_ASSERT(queue->magic == DATAQUEUE_MAGIC); @@ -303,9 +303,9 @@ void rt_data_queue_reset(struct rt_data_queue *queue) queue->put_index = 0; queue->is_empty = 1; queue->is_full = 0; - + rt_hw_interrupt_enable(level); - + rt_enter_critical(); /* wakeup all suspend threads */ @@ -375,7 +375,7 @@ rt_err_t rt_data_queue_deinit(struct rt_data_queue *queue) level = rt_hw_interrupt_disable(); queue->magic = 0; rt_hw_interrupt_enable(level); - + rt_free(queue->queue); return RT_EOK; @@ -386,7 +386,7 @@ rt_uint16_t rt_data_queue_len(struct rt_data_queue *queue) { rt_ubase_t level; rt_int16_t len; - + RT_ASSERT(queue != RT_NULL); RT_ASSERT(queue->magic == DATAQUEUE_MAGIC); @@ -405,7 +405,7 @@ rt_uint16_t rt_data_queue_len(struct rt_data_queue *queue) { len = queue->size + queue->put_index - queue->get_index; } - + rt_hw_interrupt_enable(level); return len; diff --git a/components/drivers/src/pipe.c b/components/drivers/src/pipe.c index 2a7e143f6c..3b0b5fc20b 100644 --- a/components/drivers/src/pipe.c +++ b/components/drivers/src/pipe.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -330,7 +330,7 @@ rt_err_t rt_pipe_open (rt_device_t device, rt_uint16_t oflag) ret = -RT_EINVAL; goto __exit; } - + rt_mutex_take(&(pipe->lock), RT_WAITING_FOREVER); if (pipe->fifo == RT_NULL) @@ -428,7 +428,7 @@ rt_err_t rt_pipe_control(rt_device_t dev, int cmd, void *args) } #ifdef RT_USING_DEVICE_OPS -const static struct rt_device_ops pipe_ops = +const static struct rt_device_ops pipe_ops = { RT_NULL, rt_pipe_open, @@ -507,7 +507,7 @@ int rt_pipe_delete(const char *name) rt_device_unregister(device); /* close fifo ringbuffer */ - if (pipe->fifo) + if (pipe->fifo) { rt_ringbuffer_destroy(pipe->fifo); pipe->fifo = RT_NULL; @@ -564,7 +564,7 @@ int pipe(int fildes[2]) int mkfifo(const char *path, mode_t mode) { rt_pipe_t *pipe; - + pipe = rt_pipe_create(path, PIPE_BUFSZ); if (pipe == RT_NULL) { diff --git a/components/drivers/src/ringblk_buf.c b/components/drivers/src/ringblk_buf.c index 7d83149c5e..c9631b9d4a 100644 --- a/components/drivers/src/ringblk_buf.c +++ b/components/drivers/src/ringblk_buf.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/src/ringbuffer.c b/components/drivers/src/ringbuffer.c index 88afd19506..29de20b087 100644 --- a/components/drivers/src/ringbuffer.c +++ b/components/drivers/src/ringbuffer.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -320,8 +320,8 @@ rt_size_t rt_ringbuffer_getchar(struct rt_ringbuffer *rb, rt_uint8_t *ch) } RTM_EXPORT(rt_ringbuffer_getchar); -/** - * get the size of data in rb +/** + * get the size of data in rb */ rt_size_t rt_ringbuffer_data_len(struct rt_ringbuffer *rb) { @@ -341,8 +341,8 @@ rt_size_t rt_ringbuffer_data_len(struct rt_ringbuffer *rb) } RTM_EXPORT(rt_ringbuffer_data_len); -/** - * empty the rb +/** + * empty the rb */ void rt_ringbuffer_reset(struct rt_ringbuffer *rb) { @@ -362,7 +362,7 @@ struct rt_ringbuffer* rt_ringbuffer_create(rt_uint16_t size) struct rt_ringbuffer *rb; rt_uint8_t *pool; - RT_ASSERT(size > 0); + RT_ASSERT(size > 0); size = RT_ALIGN_DOWN(size, RT_ALIGN_SIZE); diff --git a/components/drivers/src/waitqueue.c b/components/drivers/src/waitqueue.c index 02240edbdf..f9a6d6e120 100644 --- a/components/drivers/src/waitqueue.c +++ b/components/drivers/src/waitqueue.c @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2018/06/26 Bernard Fix the wait queue issue when wakeup a soon + * 2018/06/26 Bernard Fix the wait queue issue when wakeup a soon * to blocked thread. */ diff --git a/components/drivers/src/workqueue.c b/components/drivers/src/workqueue.c index 2b5630d8d0..e83db0a337 100644 --- a/components/drivers/src/workqueue.c +++ b/components/drivers/src/workqueue.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/touch/touch.c b/components/drivers/touch/touch.c index e9595e9f8f..abe2c0fe24 100644 --- a/components/drivers/touch/touch.c +++ b/components/drivers/touch/touch.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/touch/touch.h b/components/drivers/touch/touch.h index 73d4d2e488..677e554de0 100644 --- a/components/drivers/touch/touch.h +++ b/components/drivers/touch/touch.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/usb/usbdevice/class/audio_mic.c b/components/drivers/usb/usbdevice/class/audio_mic.c index 23ade2d9b6..760c055d10 100644 --- a/components/drivers/usb/usbdevice/class/audio_mic.c +++ b/components/drivers/usb/usbdevice/class/audio_mic.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/usb/usbdevice/class/audio_speaker.c b/components/drivers/usb/usbdevice/class/audio_speaker.c index e9a3ffaf40..c8bbb9cb5e 100644 --- a/components/drivers/usb/usbdevice/class/audio_speaker.c +++ b/components/drivers/usb/usbdevice/class/audio_speaker.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/usb/usbdevice/class/cdc.h b/components/drivers/usb/usbdevice/class/cdc.h index 4e07f16266..a4616a956b 100644 --- a/components/drivers/usb/usbdevice/class/cdc.h +++ b/components/drivers/usb/usbdevice/class/cdc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -8,7 +8,7 @@ * 2012-10-03 Yi Qiu first version * 2012-12-12 heyuanjie87 add CDC endpoints collection */ - + #ifndef __CDC_H__ #define __CDC_H__ @@ -96,7 +96,7 @@ struct ucdc_header_descriptor rt_uint8_t length; rt_uint8_t type; rt_uint8_t subtype; - rt_uint16_t bcd; + rt_uint16_t bcd; }; typedef struct ucdc_header_descriptor* ucdc_hdr_desc_t; @@ -114,7 +114,7 @@ struct ucdc_call_mgmt_descriptor rt_uint8_t length; rt_uint8_t type; rt_uint8_t subtype; - rt_uint8_t capabilties; + rt_uint8_t capabilties; rt_uint8_t data_interface; }; typedef struct ucdc_call_mgmt_descriptor* ucdc_call_mgmt_desc_t; @@ -136,9 +136,9 @@ struct ucdc_comm_descriptor #endif struct uinterface_descriptor intf_desc; struct ucdc_header_descriptor hdr_desc; - struct ucdc_call_mgmt_descriptor call_mgmt_desc; - struct ucdc_acm_descriptor acm_desc; - struct ucdc_union_descriptor union_desc; + struct ucdc_call_mgmt_descriptor call_mgmt_desc; + struct ucdc_acm_descriptor acm_desc; + struct ucdc_union_descriptor union_desc; struct uendpoint_descriptor ep_desc; }; typedef struct ucdc_comm_descriptor* ucdc_comm_desc_t; @@ -170,7 +170,7 @@ typedef struct ucdc_eth_descriptor* ucdc_eth_desc_t; struct ucdc_data_descriptor { struct uinterface_descriptor intf_desc; - struct uendpoint_descriptor ep_out_desc; + struct uendpoint_descriptor ep_out_desc; struct uendpoint_descriptor ep_in_desc; }; typedef struct ucdc_data_descriptor* ucdc_data_desc_t; diff --git a/components/drivers/usb/usbdevice/class/cdc_vcom.c b/components/drivers/usb/usbdevice/class/cdc_vcom.c index ca9576ed2e..73a6629a66 100644 --- a/components/drivers/usb/usbdevice/class/cdc_vcom.c +++ b/components/drivers/usb/usbdevice/class/cdc_vcom.c @@ -1,12 +1,12 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2012-10-02 Yi Qiu first version - * 2012-12-12 heyuanjie87 change endpoints and function handler + * 2012-12-12 heyuanjie87 change endpoints and function handler * 2013-06-25 heyuanjie87 remove SOF mechinism * 2013-07-20 Yi Qiu do more test * 2016-02-01 Urey Fix some error @@ -142,23 +142,23 @@ const static struct ucdc_comm_descriptor _comm_desc = USB_DESC_LENGTH_INTERFACE, USB_DESC_TYPE_INTERFACE, USB_DYNAMIC, - 0x00, + 0x00, 0x01, USB_CDC_CLASS_COMM, USB_CDC_SUBCLASS_ACM, USB_CDC_PROTOCOL_V25TER, 0x00, }, - /* Header Functional Descriptor */ + /* Header Functional Descriptor */ { - 0x05, + 0x05, USB_CDC_CS_INTERFACE, USB_CDC_SCS_HEADER, 0x0110, }, - /* Call Management Functional Descriptor */ + /* Call Management Functional Descriptor */ { - 0x05, + 0x05, USB_CDC_CS_INTERFACE, USB_CDC_SCS_CALL_MGMT, 0x00, @@ -171,7 +171,7 @@ const static struct ucdc_comm_descriptor _comm_desc = USB_CDC_SCS_ACM, 0x02, }, - /* Union Functional Descriptor */ + /* Union Functional Descriptor */ { 0x05, USB_CDC_CS_INTERFACE, @@ -179,7 +179,7 @@ const static struct ucdc_comm_descriptor _comm_desc = USB_DYNAMIC, USB_DYNAMIC, }, - /* Endpoint Descriptor */ + /* Endpoint Descriptor */ { USB_DESC_LENGTH_ENDPOINT, USB_DESC_TYPE_ENDPOINT, @@ -200,27 +200,27 @@ const static struct ucdc_data_descriptor _data_desc = USB_DESC_TYPE_INTERFACE, USB_DYNAMIC, 0x00, - 0x02, + 0x02, USB_CDC_CLASS_DATA, - 0x00, - 0x00, - 0x00, + 0x00, + 0x00, + 0x00, }, /* endpoint, bulk out */ { - USB_DESC_LENGTH_ENDPOINT, + USB_DESC_LENGTH_ENDPOINT, USB_DESC_TYPE_ENDPOINT, USB_DYNAMIC | USB_DIR_OUT, - USB_EP_ATTR_BULK, + USB_EP_ATTR_BULK, USB_CDC_BUFSIZE, - 0x00, + 0x00, }, /* endpoint, bulk in */ { USB_DESC_LENGTH_ENDPOINT, USB_DESC_TYPE_ENDPOINT, USB_DYNAMIC | USB_DIR_IN, - USB_EP_ATTR_BULK, + USB_EP_ATTR_BULK, USB_CDC_BUFSIZE, 0x00, }, @@ -249,11 +249,11 @@ static void _vcom_reset_state(ufunction_t func) { struct vcom* data; int lvl; - + RT_ASSERT(func != RT_NULL) data = (struct vcom*)func->user_data; - + lvl = rt_hw_interrupt_disable(); data->connected = RT_FALSE; data->in_sending = RT_FALSE; @@ -295,9 +295,9 @@ static rt_err_t _ep_in_handler(ufunction_t func, rt_size_t size) return RT_EOK; } - + rt_completion_done(&data->wait); - + return RT_EOK; } @@ -392,7 +392,7 @@ static rt_err_t _cdc_set_line_coding_callback(udevice_t device, rt_size_t size) RT_DEBUG_LOG(RT_DEBUG_USB, ("_cdc_set_line_coding_callback\n")); dcd_ep0_send_status(device->dcd); - + return RT_EOK; } @@ -434,7 +434,7 @@ static rt_err_t _interface_handler(ufunction_t func, ureq_t setup) RT_ASSERT(setup != RT_NULL); data = (struct vcom*)func->user_data; - + switch(setup->bRequest) { case CDC_SEND_ENCAPSULATED_COMMAND: @@ -484,17 +484,17 @@ static rt_err_t _function_enable(ufunction_t func) RT_DEBUG_LOG(RT_DEBUG_USB, ("cdc function enable\n")); _vcom_reset_state(func); - + data = (struct vcom*)func->user_data; data->ep_out->buffer = rt_malloc(CDC_RX_BUFSIZE); RT_ASSERT(data->ep_out->buffer != RT_NULL); data->ep_out->request.buffer = data->ep_out->buffer; data->ep_out->request.size = EP_MAXPACKET(data->ep_out); - + data->ep_out->request.req_type = UIO_REQUEST_READ_BEST; rt_usbd_io_request(func->device, data->ep_out, &data->ep_out->request); - + return RT_EOK; } @@ -519,7 +519,7 @@ static rt_err_t _function_disable(ufunction_t func) if(data->ep_out->buffer != RT_NULL) { rt_free(data->ep_out->buffer); - data->ep_out->buffer = RT_NULL; + data->ep_out->buffer = RT_NULL; } return RT_EOK; @@ -540,7 +540,7 @@ static struct ufunction_ops ops = * * @return RT_EOK on successful. */ -static rt_err_t _cdc_descriptor_config(ucdc_comm_desc_t comm, +static rt_err_t _cdc_descriptor_config(ucdc_comm_desc_t comm, rt_uint8_t cintf_nr, ucdc_data_desc_t data, rt_uint8_t dintf_nr) { comm->call_mgmt_desc.data_interface = dintf_nr; @@ -580,19 +580,19 @@ ufunction_t rt_usbd_function_cdc_create(udevice_t device) } /* set usb device string description */ rt_usbd_device_set_string(device, _ustring); - + /* create a cdc function */ func = rt_usbd_function_new(device, &dev_desc, &ops); - + /* support HS */ rt_usbd_device_set_qualifier(device, &dev_qualifier); - + /* allocate memory for cdc vcom data */ data = (struct vcom*)rt_malloc(sizeof(struct vcom)); RT_ASSERT(data != RT_NULL); rt_memset(data, 0, sizeof(struct vcom)); func->user_data = (void*)data; - + /* initilize vcom */ rt_usb_vcom_init(func); @@ -642,7 +642,7 @@ ufunction_t rt_usbd_function_cdc_create(udevice_t device) /* add the cdc data interface to cdc function */ rt_usbd_function_add_interface(func, intf_data); - + return func; } @@ -678,7 +678,7 @@ static int _vcom_getc(struct rt_serial_device *serial) rt_uint32_t level; struct ufunction *func; struct vcom *data; - + func = (struct ufunction*)serial->parent.user_data; data = (struct vcom*)func->user_data; @@ -914,7 +914,7 @@ static void rt_usb_vcom_init(struct ufunction *func) rt_err_t result = RT_EOK; struct serial_configure config; struct vcom *data = (struct vcom*)func->user_data; - + /* initialize ring buffer */ rt_ringbuffer_init(&data->rx_ringbuffer, data->rx_rbp, CDC_RX_BUFSIZE); rt_ringbuffer_init(&data->tx_ringbuffer, data->tx_rbp, CDC_TX_BUFSIZE); @@ -948,9 +948,9 @@ static void rt_usb_vcom_init(struct ufunction *func) vcom_thread_stack, VCOM_TASK_STK_SIZE, 16, 20); result = rt_thread_startup(&vcom_thread); - RT_ASSERT(result == RT_EOK); + RT_ASSERT(result == RT_EOK); } -struct udclass vcom_class = +struct udclass vcom_class = { .rt_usbd_function_create = rt_usbd_function_cdc_create }; diff --git a/components/drivers/usb/usbdevice/class/ecm.c b/components/drivers/usb/usbdevice/class/ecm.c index 36557dad74..1550f8e1e2 100644 --- a/components/drivers/usb/usbdevice/class/ecm.c +++ b/components/drivers/usb/usbdevice/class/ecm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -44,9 +44,9 @@ struct rt_ecm_eth ALIGN(4) char rx_buffer[USB_ETH_MTU]; char tx_buffer[USB_ETH_MTU]; - + struct rt_semaphore tx_buffer_free; - + }; typedef struct rt_ecm_eth * rt_ecm_eth_t; @@ -207,7 +207,7 @@ static rt_err_t _cdc_send_notifi(ufunction_t func,ucdc_notification_code_t notif _notifi.bNotificatinCode = notifi; _notifi.wValue = wValue; _notifi.wLength = wLength; - + eps->ep_cmd->request.buffer = (void *)&_notifi; eps->ep_cmd->request.size = 8; eps->ep_cmd->request.req_type = UIO_REQUEST_WRITE; @@ -220,7 +220,7 @@ static rt_err_t _ecm_set_eth_packet_filter(ufunction_t func, ureq_t setup) { rt_ecm_eth_t _ecm_eth = (rt_ecm_eth_t)func->user_data; dcd_ep0_send_status(func->device->dcd); - + /* send link up. */ eth_device_linkchange(&_ecm_eth->parent, RT_TRUE); _cdc_send_notifi(func, UCDC_NOTIFI_NETWORK_CONNECTION, 1, 0); @@ -292,7 +292,7 @@ static rt_err_t _ep_out_handler(ufunction_t func, rt_size_t size) ecm_device->rx_size = ecm_device->rx_offset; ecm_device->rx_offset = 0; eth_device_ready(&ecm_device->parent); - + }else { ecm_device->eps.ep_out->request.buffer = ecm_device->eps.ep_out->buffer; @@ -427,7 +427,7 @@ rt_err_t rt_ecm_eth_tx(rt_device_t dev, struct pbuf* p) rt_sem_release(&ecm_eth_dev->tx_buffer_free); return result; } - + pbuffer = (char *)&ecm_eth_dev->tx_buffer; for (q = p; q != NULL; q = q->next) { @@ -480,7 +480,7 @@ static rt_err_t _function_enable(ufunction_t func) /* reset eth rx tx */ ecm_device->rx_size = 0; ecm_device->rx_offset = 0; - + eps->ep_out->request.buffer = (void *)eps->ep_out->buffer; eps->ep_out->request.size = EP_MAXPACKET(eps->ep_out); eps->ep_out->request.req_type = UIO_REQUEST_READ_BEST; @@ -555,7 +555,7 @@ ufunction_t rt_usbd_function_ecm_create(udevice_t device) ualtsetting_t comm_setting, data_setting; ucdc_data_desc_t data_desc; ucdc_eth_desc_t comm_desc; - + /* parameter check */ RT_ASSERT(device != RT_NULL); @@ -600,7 +600,7 @@ ufunction_t rt_usbd_function_ecm_create(udevice_t device) rt_usbd_set_altsetting(intf_comm, 0); /* add the communication interface to the cdc class */ rt_usbd_function_add_interface(cdc, intf_comm); - + /* create a bulk in and a bulk out endpoint */ data_desc = (ucdc_data_desc_t)data_setting->desc; eps->ep_out = rt_usbd_endpoint_new(&data_desc->ep_out_desc, _ep_out_handler); @@ -648,14 +648,14 @@ ufunction_t rt_usbd_function_ecm_create(udevice_t device) _ecm_eth->parent.eth_tx = rt_ecm_eth_tx; /* register eth device */ eth_device_init(&_ecm_eth->parent, "u0"); - + /* send link up. */ eth_device_linkchange(&_ecm_eth->parent, RT_FALSE); - + return cdc; } -struct udclass ecm_class = +struct udclass ecm_class = { .rt_usbd_function_create = rt_usbd_function_ecm_create }; diff --git a/components/drivers/usb/usbdevice/class/hid.c b/components/drivers/usb/usbdevice/class/hid.c index 52e50296a4..fae45bb0ea 100644 --- a/components/drivers/usb/usbdevice/class/hid.c +++ b/components/drivers/usb/usbdevice/class/hid.c @@ -3,7 +3,7 @@ * COPYRIGHT (C) 2008 - 2018, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 - * + * * Change Logs: * Date Author Notes * 2017-03-13 Urey the first version @@ -621,12 +621,12 @@ static void hid_thread_entry(void* parameter) struct hid_report report; struct hid_s *hiddev; hiddev = (struct hid_s *)parameter; - while(1) - { - if(rt_mq_recv(&hiddev->hid_mq, &report, sizeof(report),RT_WAITING_FOREVER) != RT_EOK ) + while(1) + { + if(rt_mq_recv(&hiddev->hid_mq, &report, sizeof(report),RT_WAITING_FOREVER) != RT_EOK ) continue; - HID_Report_Received(&report); - } + HID_Report_Received(&report); + } } #ifdef RT_USING_DEVICE_OPS @@ -658,7 +658,7 @@ static void rt_usb_hid_init(struct ufunction *func) rt_device_register(&hiddev->parent, "hidd", RT_DEVICE_FLAG_RDWR); rt_mq_init(&hiddev->hid_mq, "hiddmq", hid_mq_pool, sizeof(struct hid_report), sizeof(hid_mq_pool), RT_IPC_FLAG_FIFO); - + rt_thread_init(&hid_thread, "hidd", hid_thread_entry, hiddev, hid_thread_stack, sizeof(hid_thread_stack), RT_USBD_THREAD_PRIO, 20); rt_thread_startup(&hid_thread); @@ -689,7 +689,7 @@ ufunction_t rt_usbd_function_hid_create(udevice_t device) /* create a cdc function */ func = rt_usbd_function_new(device, &_dev_desc, &ops); - + /* For high speed mode supporting */ rt_usbd_device_set_qualifier(device, &dev_qualifier); @@ -730,7 +730,7 @@ ufunction_t rt_usbd_function_hid_create(udevice_t device) rt_usb_hid_init(func); return func; } -struct udclass hid_class = +struct udclass hid_class = { .rt_usbd_function_create = rt_usbd_function_hid_create }; diff --git a/components/drivers/usb/usbdevice/class/hid.h b/components/drivers/usb/usbdevice/class/hid.h index 4d0f314a11..2b6a4ad90a 100644 --- a/components/drivers/usb/usbdevice/class/hid.h +++ b/components/drivers/usb/usbdevice/class/hid.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/usb/usbdevice/class/mstorage.c b/components/drivers/usb/usbdevice/class/mstorage.c index 0cee2c3e16..89be813ad1 100644 --- a/components/drivers/usb/usbdevice/class/mstorage.c +++ b/components/drivers/usb/usbdevice/class/mstorage.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2012-10-01 Yi Qiu first version * 2012-11-25 Heyuanjie87 reduce the memory consumption - * 2012-12-09 Heyuanjie87 change function and endpoint handler + * 2012-12-09 Heyuanjie87 change function and endpoint handler * 2013-07-25 Yi Qiu update for USB CV test */ @@ -20,10 +20,10 @@ enum STAT { STAT_CBW, - STAT_CMD, + STAT_CMD, STAT_CSW, STAT_RECEIVE, - STAT_SEND, + STAT_SEND, }; typedef enum @@ -45,7 +45,7 @@ typedef rt_size_t (*cbw_handler)(ufunction_t func, ustorage_cbw_t cbw); struct scsi_cmd { rt_uint16_t cmd; - cbw_handler handler; + cbw_handler handler; rt_size_t cmd_len; CB_SIZE_TYPE type; rt_size_t data_size; @@ -53,10 +53,10 @@ struct scsi_cmd }; struct mstorage -{ +{ struct ustorage_csw csw_response; uep_t ep_in; - uep_t ep_out; + uep_t ep_out; int status; rt_uint32_t cb_data_size; rt_device_t disk; @@ -64,7 +64,7 @@ struct mstorage rt_int32_t count; rt_int32_t size; struct scsi_cmd* processing; - struct rt_device_blk_geometry geometry; + struct rt_device_blk_geometry geometry; }; ALIGN(4) @@ -179,9 +179,9 @@ static struct scsi_cmd cmd_data[] = {SCSI_REQUEST_SENSE, _request_sense, 6, COUNT, 0, DIR_IN}, {SCSI_INQUIRY_CMD, _inquiry_cmd, 6, COUNT, 0, DIR_IN}, {SCSI_ALLOW_REMOVAL, _allow_removal, 6, FIXED, 0, DIR_NONE}, - {SCSI_MODE_SENSE_6, _mode_sense_6, 6, COUNT, 0, DIR_IN}, - {SCSI_START_STOP, _start_stop, 6, FIXED, 0, DIR_NONE}, - {SCSI_READ_CAPACITIES, _read_capacities, 10, COUNT, 0, DIR_NONE}, + {SCSI_MODE_SENSE_6, _mode_sense_6, 6, COUNT, 0, DIR_IN}, + {SCSI_START_STOP, _start_stop, 6, FIXED, 0, DIR_NONE}, + {SCSI_READ_CAPACITIES, _read_capacities, 10, COUNT, 0, DIR_NONE}, {SCSI_READ_CAPACITY, _read_capacity, 10, FIXED, 8, DIR_IN}, {SCSI_READ_10, _read_10, 10, BLOCK_COUNT, 0, DIR_IN}, {SCSI_WRITE_10, _write_10, 10, BLOCK_COUNT, 0, DIR_OUT}, @@ -196,9 +196,9 @@ static void _send_status(ufunction_t func) RT_DEBUG_LOG(RT_DEBUG_USB, ("_send_status\n")); - data = (struct mstorage*)func->user_data; + data = (struct mstorage*)func->user_data; data->ep_in->request.buffer = (rt_uint8_t*)&data->csw_response; - data->ep_in->request.size = SIZEOF_CSW; + data->ep_in->request.size = SIZEOF_CSW; data->ep_in->request.req_type = UIO_REQUEST_WRITE; rt_usbd_io_request(func->device, data->ep_in, &data->ep_in->request); data->status = STAT_CSW; @@ -209,13 +209,13 @@ static rt_size_t _test_unit_ready(ufunction_t func, ustorage_cbw_t cbw) struct mstorage *data; RT_ASSERT(func != RT_NULL); - RT_ASSERT(func->device != RT_NULL); + RT_ASSERT(func->device != RT_NULL); RT_DEBUG_LOG(RT_DEBUG_USB, ("_test_unit_ready\n")); data = (struct mstorage*)func->user_data; data->csw_response.status = 0; - + return 0; } @@ -224,7 +224,7 @@ static rt_size_t _allow_removal(ufunction_t func, ustorage_cbw_t cbw) struct mstorage *data; RT_ASSERT(func != RT_NULL); - RT_ASSERT(func->device != RT_NULL); + RT_ASSERT(func->device != RT_NULL); RT_DEBUG_LOG(RT_DEBUG_USB, ("_allow_removal\n")); @@ -237,7 +237,7 @@ static rt_size_t _allow_removal(ufunction_t func, ustorage_cbw_t cbw) /** * This function will handle inquiry command request. * - * @param func the usb function object. + * @param func the usb function object. * @param cbw the command block wrapper. * * @return RT_EOK on successful. @@ -249,12 +249,12 @@ static rt_size_t _inquiry_cmd(ufunction_t func, ustorage_cbw_t cbw) rt_uint8_t *buf; RT_ASSERT(func != RT_NULL); - RT_ASSERT(func->device != RT_NULL); + RT_ASSERT(func->device != RT_NULL); RT_ASSERT(cbw != RT_NULL); RT_DEBUG_LOG(RT_DEBUG_USB, ("_inquiry_cmd\n")); - data = (struct mstorage*)func->user_data; + data = (struct mstorage*)func->user_data; buf = data->ep_in->buffer; *(rt_uint32_t*)&buf[0] = 0x0 | (0x80 << 8); @@ -277,7 +277,7 @@ static rt_size_t _inquiry_cmd(ufunction_t func, ustorage_cbw_t cbw) /** * This function will handle sense request. * - * @param func the usb function object. + * @param func the usb function object. * @param cbw the command block wrapper. * * @return RT_EOK on successful. @@ -288,12 +288,12 @@ static rt_size_t _request_sense(ufunction_t func, ustorage_cbw_t cbw) struct request_sense_data *buf; RT_ASSERT(func != RT_NULL); - RT_ASSERT(func->device != RT_NULL); + RT_ASSERT(func->device != RT_NULL); RT_ASSERT(cbw != RT_NULL); RT_DEBUG_LOG(RT_DEBUG_USB, ("_request_sense\n")); - - data = (struct mstorage*)func->user_data; + + data = (struct mstorage*)func->user_data; buf = (struct request_sense_data *)data->ep_in->buffer; buf->ErrorCode = 0x70; @@ -321,7 +321,7 @@ static rt_size_t _request_sense(ufunction_t func, ustorage_cbw_t cbw) * This function will handle mode_sense_6 request. * * @param func the usb function object. - * @param cbw the command block wrapper. + * @param cbw the command block wrapper. * * @return RT_EOK on successful. */ @@ -331,12 +331,12 @@ static rt_size_t _mode_sense_6(ufunction_t func, ustorage_cbw_t cbw) rt_uint8_t *buf; RT_ASSERT(func != RT_NULL); - RT_ASSERT(func->device != RT_NULL); + RT_ASSERT(func->device != RT_NULL); RT_ASSERT(cbw != RT_NULL); RT_DEBUG_LOG(RT_DEBUG_USB, ("_mode_sense_6\n")); - data = (struct mstorage*)func->user_data; + data = (struct mstorage*)func->user_data; buf = data->ep_in->buffer; buf[0] = 3; buf[1] = 0; @@ -356,7 +356,7 @@ static rt_size_t _mode_sense_6(ufunction_t func, ustorage_cbw_t cbw) /** * This function will handle read_capacities request. * - * @param func the usb function object. + * @param func the usb function object. * @param cbw the command block wrapper. * * @return RT_EOK on successful. @@ -368,12 +368,12 @@ static rt_size_t _read_capacities(ufunction_t func, ustorage_cbw_t cbw) rt_uint32_t sector_count, sector_size; RT_ASSERT(func != RT_NULL); - RT_ASSERT(func->device != RT_NULL); + RT_ASSERT(func->device != RT_NULL); RT_ASSERT(cbw != RT_NULL); RT_DEBUG_LOG(RT_DEBUG_USB, ("_read_capacities\n")); - data = (struct mstorage*)func->user_data; + data = (struct mstorage*)func->user_data; buf = data->ep_in->buffer; sector_count = data->geometry.sector_count; sector_size = data->geometry.bytes_per_sector; @@ -401,7 +401,7 @@ static rt_size_t _read_capacities(ufunction_t func, ustorage_cbw_t cbw) /** * This function will handle read_capacity request. * - * @param func the usb function object. + * @param func the usb function object. * @param cbw the command block wapper. * * @return RT_EOK on successful. @@ -414,13 +414,13 @@ static rt_size_t _read_capacity(ufunction_t func, ustorage_cbw_t cbw) rt_uint32_t sector_count, sector_size; RT_ASSERT(func != RT_NULL); - RT_ASSERT(func->device != RT_NULL); + RT_ASSERT(func->device != RT_NULL); RT_ASSERT(cbw != RT_NULL); RT_DEBUG_LOG(RT_DEBUG_USB, ("_read_capacity\n")); - data = (struct mstorage*)func->user_data; - buf = data->ep_in->buffer; + data = (struct mstorage*)func->user_data; + buf = data->ep_in->buffer; sector_count = data->geometry.sector_count - 1; /* Last Logical Block Address */ sector_size = data->geometry.bytes_per_sector; @@ -455,19 +455,19 @@ static rt_size_t _read_10(ufunction_t func, ustorage_cbw_t cbw) { struct mstorage *data; rt_size_t size; - + RT_ASSERT(func != RT_NULL); - RT_ASSERT(func->device != RT_NULL); + RT_ASSERT(func->device != RT_NULL); RT_ASSERT(cbw != RT_NULL); - data = (struct mstorage*)func->user_data; + data = (struct mstorage*)func->user_data; data->block = cbw->cb[2]<<24 | cbw->cb[3]<<16 | cbw->cb[4]<<8 | cbw->cb[5]<<0; data->count = cbw->cb[7]<<8 | cbw->cb[8]<<0; RT_ASSERT(data->count < data->geometry.sector_count); - data->csw_response.data_reside = data->cb_data_size; + data->csw_response.data_reside = data->cb_data_size; size = rt_device_read(data->disk, data->block, data->ep_in->buffer, 1); if(size == 0) { @@ -475,11 +475,11 @@ static rt_size_t _read_10(ufunction_t func, ustorage_cbw_t cbw) } data->ep_in->request.buffer = data->ep_in->buffer; - data->ep_in->request.size = data->geometry.bytes_per_sector; - data->ep_in->request.req_type = UIO_REQUEST_WRITE; + data->ep_in->request.size = data->geometry.bytes_per_sector; + data->ep_in->request.req_type = UIO_REQUEST_WRITE; rt_usbd_io_request(func->device, data->ep_in, &data->ep_in->request); data->status = STAT_SEND; - + return data->geometry.bytes_per_sector; } @@ -499,7 +499,7 @@ static rt_size_t _write_10(ufunction_t func, ustorage_cbw_t cbw) RT_ASSERT(func->device != RT_NULL); RT_ASSERT(cbw != RT_NULL); - data = (struct mstorage*)func->user_data; + data = (struct mstorage*)func->user_data; data->block = cbw->cb[2]<<24 | cbw->cb[3]<<16 | cbw->cb[4]<<8 | cbw->cb[5]<<0; @@ -511,13 +511,13 @@ static rt_size_t _write_10(ufunction_t func, ustorage_cbw_t cbw) data->count, data->block, data->geometry.sector_count)); data->csw_response.data_reside = data->cb_data_size; - + data->ep_out->request.buffer = data->ep_out->buffer; - data->ep_out->request.size = data->geometry.bytes_per_sector; + data->ep_out->request.size = data->geometry.bytes_per_sector; data->ep_out->request.req_type = UIO_REQUEST_READ_FULL; rt_usbd_io_request(func->device, data->ep_out, &data->ep_out->request); data->status = STAT_RECEIVE; - + return data->geometry.bytes_per_sector; } @@ -533,42 +533,42 @@ static rt_size_t _verify_10(ufunction_t func, ustorage_cbw_t cbw) struct mstorage *data; RT_ASSERT(func != RT_NULL); - RT_ASSERT(func->device != RT_NULL); + RT_ASSERT(func->device != RT_NULL); RT_DEBUG_LOG(RT_DEBUG_USB, ("_verify_10\n")); data = (struct mstorage*)func->user_data; data->csw_response.status = 0; - + return 0; } -static rt_size_t _start_stop(ufunction_t func, +static rt_size_t _start_stop(ufunction_t func, ustorage_cbw_t cbw) { struct mstorage *data; RT_ASSERT(func != RT_NULL); - RT_ASSERT(func->device != RT_NULL); + RT_ASSERT(func->device != RT_NULL); RT_DEBUG_LOG(RT_DEBUG_USB, ("_start_stop\n")); data = (struct mstorage*)func->user_data; data->csw_response.status = 0; - + return 0; } static rt_err_t _ep_in_handler(ufunction_t func, rt_size_t size) { struct mstorage *data; - + RT_ASSERT(func != RT_NULL); RT_ASSERT(func->device != RT_NULL); RT_DEBUG_LOG(RT_DEBUG_USB, ("_ep_in_handler\n")); - - data = (struct mstorage*)func->user_data; + + data = (struct mstorage*)func->user_data; switch(data->status) { @@ -576,15 +576,15 @@ static rt_err_t _ep_in_handler(ufunction_t func, rt_size_t size) if(data->ep_in->request.size != SIZEOF_CSW) { rt_kprintf("Size of csw command error\n"); - rt_usbd_ep_set_stall(func->device, data->ep_in); + rt_usbd_ep_set_stall(func->device, data->ep_in); } else { RT_DEBUG_LOG(RT_DEBUG_USB, ("return to cbw status\n")); data->ep_out->request.buffer = data->ep_out->buffer; data->ep_out->request.size = SIZEOF_CBW; - data->ep_out->request.req_type = UIO_REQUEST_READ_FULL; - rt_usbd_io_request(func->device, data->ep_out, &data->ep_out->request); + data->ep_out->request.req_type = UIO_REQUEST_READ_FULL; + rt_usbd_io_request(func->device, data->ep_out, &data->ep_out->request); data->status = STAT_CBW; } break; @@ -597,47 +597,47 @@ static rt_err_t _ep_in_handler(ufunction_t func, rt_size_t size) { data->csw_response.data_reside -= data->ep_in->request.size; if(data->csw_response.data_reside != 0) - { - RT_DEBUG_LOG(RT_DEBUG_USB, ("data_reside %d, request %d\n", + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("data_reside %d, request %d\n", data->csw_response.data_reside, data->ep_in->request.size)); if(data->processing->dir == DIR_OUT) { rt_usbd_ep_set_stall(func->device, data->ep_out); } else - { + { //rt_kprintf("warning:in stall path but not stall\n"); - + /* FIXME: Disable the operation or the disk cannot work. */ - //rt_usbd_ep_set_stall(func->device, data->ep_in); + //rt_usbd_ep_set_stall(func->device, data->ep_in); } data->csw_response.data_reside = 0; } } _send_status(func); break; - case STAT_SEND: + case STAT_SEND: data->csw_response.data_reside -= data->ep_in->request.size; - data->count--; - data->block++; + data->count--; + data->block++; if(data->count > 0 && data->csw_response.data_reside > 0) { if(rt_device_read(data->disk, data->block, data->ep_in->buffer, 1) == 0) { rt_kprintf("disk read error\n"); rt_usbd_ep_set_stall(func->device, data->ep_in); - return -RT_ERROR; + return -RT_ERROR; } data->ep_in->request.buffer = data->ep_in->buffer; - data->ep_in->request.size = data->geometry.bytes_per_sector; - data->ep_in->request.req_type = UIO_REQUEST_WRITE; - rt_usbd_io_request(func->device, data->ep_in, &data->ep_in->request); + data->ep_in->request.size = data->geometry.bytes_per_sector; + data->ep_in->request.req_type = UIO_REQUEST_WRITE; + rt_usbd_io_request(func->device, data->ep_in, &data->ep_in->request); } else { - _send_status(func); - } + _send_status(func); + } break; } @@ -667,7 +667,7 @@ static struct scsi_cmd* _find_cbw_command(rt_uint16_t cmd) { if(cmd_data[i].cmd == cmd) return &cmd_data[i]; - } + } return RT_NULL; } @@ -681,7 +681,7 @@ static void _cb_len_calc(ufunction_t func, struct scsi_cmd* cmd, RT_ASSERT(cmd != RT_NULL); RT_ASSERT(cbw != RT_NULL); - data = (struct mstorage*)func->user_data; + data = (struct mstorage*)func->user_data; if(cmd->cmd_len == 6) { switch(cmd->type) @@ -695,9 +695,9 @@ static void _cb_len_calc(ufunction_t func, struct scsi_cmd* cmd, case FIXED: data->cb_data_size = cmd->data_size; break; - default: + default: break; - } + } } else if(cmd->cmd_len == 10) { @@ -707,32 +707,32 @@ static void _cb_len_calc(ufunction_t func, struct scsi_cmd* cmd, data->cb_data_size = cbw->cb[7]<<8 | cbw->cb[8]; break; case BLOCK_COUNT: - data->cb_data_size = (cbw->cb[7]<<8 | cbw->cb[8]) * + data->cb_data_size = (cbw->cb[7]<<8 | cbw->cb[8]) * data->geometry.bytes_per_sector; break; case FIXED: data->cb_data_size = cmd->data_size; break; - default: + default: break; } } - + //workaround: for stability in full-speed mode else if(cmd->cmd_len == 12) { switch(cmd->type) { case COUNT: - data->cb_data_size = cbw->cb[4]; + data->cb_data_size = cbw->cb[4]; break; - default: + default: break; } } else { - rt_kprintf("cmd_len error %d\n", cmd->cmd_len); + rt_kprintf("cmd_len error %d\n", cmd->cmd_len); } } @@ -745,7 +745,7 @@ static rt_bool_t _cbw_verify(ufunction_t func, struct scsi_cmd* cmd, RT_ASSERT(cbw != RT_NULL); RT_ASSERT(func != RT_NULL); - data = (struct mstorage*)func->user_data; + data = (struct mstorage*)func->user_data; if(cmd->cmd_len != cbw->cb_len) { rt_kprintf("cb_len error\n"); @@ -776,7 +776,7 @@ static rt_bool_t _cbw_verify(ufunction_t func, struct scsi_cmd* cmd, rt_kprintf("xfer_len > data_size\n"); return RT_FALSE; } - + if(cbw->xfer_len < data->cb_data_size) { rt_kprintf("xfer_len < data_size\n"); @@ -784,18 +784,18 @@ static rt_bool_t _cbw_verify(ufunction_t func, struct scsi_cmd* cmd, data->csw_response.status = 1; } - return RT_TRUE; + return RT_TRUE; } static rt_size_t _cbw_handler(ufunction_t func, struct scsi_cmd* cmd, ustorage_cbw_t cbw) -{ +{ struct mstorage *data; RT_ASSERT(func != RT_NULL); RT_ASSERT(cbw != RT_NULL); RT_ASSERT(cmd->handler != RT_NULL); - + data = (struct mstorage*)func->user_data; data->processing = cmd; return cmd->handler(func, cbw); @@ -815,21 +815,21 @@ static rt_err_t _ep_out_handler(ufunction_t func, rt_size_t size) struct scsi_cmd* cmd; rt_size_t len; struct ustorage_cbw* cbw; - + RT_ASSERT(func != RT_NULL); RT_ASSERT(func->device != RT_NULL); RT_DEBUG_LOG(RT_DEBUG_USB, ("_ep_out_handler %d\n", size)); - + data = (struct mstorage*)func->user_data; - cbw = (struct ustorage_cbw*)data->ep_out->buffer; + cbw = (struct ustorage_cbw*)data->ep_out->buffer; if(data->status == STAT_CBW) { /* dump cbw information */ if(cbw->signature != CBW_SIGNATURE || size != SIZEOF_CBW) { goto exit; - } + } data->csw_response.signature = CSW_SIGNATURE; data->csw_response.tag = cbw->tag; @@ -837,33 +837,33 @@ static rt_err_t _ep_out_handler(ufunction_t func, rt_size_t size) data->csw_response.status = 0; RT_DEBUG_LOG(RT_DEBUG_USB, ("ep_out reside %d\n", data->csw_response.data_reside)); - + cmd = _find_cbw_command(cbw->cb[0]); if(cmd == RT_NULL) { rt_kprintf("can't find cbw command\n"); goto exit; - } + } _cb_len_calc(func, cmd, cbw); if(!_cbw_verify(func, cmd, cbw)) { goto exit; } - + len = _cbw_handler(func, cmd, cbw); if(len == 0) { _send_status(func); - } - - return RT_EOK; + } + + return RT_EOK; } else if(data->status == STAT_RECEIVE) { RT_DEBUG_LOG(RT_DEBUG_USB, ("\nwrite size %d block 0x%x oount 0x%x\n", size, data->block, data->size)); - + data->size -= size; data->csw_response.data_reside -= size; @@ -872,10 +872,10 @@ static rt_err_t _ep_out_handler(ufunction_t func, rt_size_t size) if(data->csw_response.data_reside != 0) { data->ep_out->request.buffer = data->ep_out->buffer; - data->ep_out->request.size = data->geometry.bytes_per_sector; - data->ep_out->request.req_type = UIO_REQUEST_READ_FULL; + data->ep_out->request.size = data->geometry.bytes_per_sector; + data->ep_out->request.req_type = UIO_REQUEST_READ_FULL; rt_usbd_io_request(func->device, data->ep_out, &data->ep_out->request); - data->block ++; + data->block ++; } else { @@ -900,7 +900,7 @@ exit: } data->csw_response.status = 1; _send_status(func); - + return -RT_ERROR; } @@ -915,21 +915,21 @@ exit: static rt_err_t _interface_handler(ufunction_t func, ureq_t setup) { rt_uint8_t lun = 0; - + RT_ASSERT(func != RT_NULL); - RT_ASSERT(func->device != RT_NULL); + RT_ASSERT(func->device != RT_NULL); RT_ASSERT(setup != RT_NULL); RT_DEBUG_LOG(RT_DEBUG_USB, ("mstorage_interface_handler\n")); switch(setup->bRequest) { - case USBREQ_GET_MAX_LUN: - + case USBREQ_GET_MAX_LUN: + RT_DEBUG_LOG(RT_DEBUG_USB, ("USBREQ_GET_MAX_LUN\n")); - + if(setup->wValue || setup->wLength != 1) - { + { rt_usbd_ep0_set_stall(func->device); } else @@ -940,14 +940,14 @@ static rt_err_t _interface_handler(ufunction_t func, ureq_t setup) case USBREQ_MASS_STORAGE_RESET: RT_DEBUG_LOG(RT_DEBUG_USB, ("USBREQ_MASS_STORAGE_RESET\n")); - + if(setup->wValue || setup->wLength != 0) { rt_usbd_ep0_set_stall(func->device); } else - { - dcd_ep0_send_status(func->device->dcd); + { + dcd_ep0_send_status(func->device->dcd); } break; default: @@ -984,14 +984,14 @@ static rt_err_t _function_enable(ufunction_t func) rt_kprintf("disk open error\n"); return -RT_ERROR; } - - if(rt_device_control(data->disk, RT_DEVICE_CTRL_BLK_GETGEOME, + + if(rt_device_control(data->disk, RT_DEVICE_CTRL_BLK_GETGEOME, (void*)&data->geometry) != RT_EOK) { rt_kprintf("get disk info error\n"); return -RT_ERROR; } - + data->ep_in->buffer = (rt_uint8_t*)rt_malloc(data->geometry.bytes_per_sector); if(data->ep_in->buffer == RT_NULL) { @@ -1004,14 +1004,14 @@ static rt_err_t _function_enable(ufunction_t func) rt_free(data->ep_in->buffer); rt_kprintf("no memory\n"); return -RT_ENOMEM; - } - + } + /* prepare to read CBW request */ data->ep_out->request.buffer = data->ep_out->buffer; - data->ep_out->request.size = SIZEOF_CBW; - data->ep_out->request.req_type = UIO_REQUEST_READ_FULL; + data->ep_out->request.size = SIZEOF_CBW; + data->ep_out->request.req_type = UIO_REQUEST_READ_FULL; rt_usbd_io_request(func->device, data->ep_out, &data->ep_out->request); - + return RT_EOK; } @@ -1029,11 +1029,11 @@ static rt_err_t _function_disable(ufunction_t func) RT_DEBUG_LOG(RT_DEBUG_USB, ("Mass storage function disabled\n")); - data = (struct mstorage*)func->user_data; + data = (struct mstorage*)func->user_data; if(data->ep_in->buffer != RT_NULL) { rt_free(data->ep_in->buffer); - data->ep_in->buffer = RT_NULL; + data->ep_in->buffer = RT_NULL; } if(data->ep_out->buffer != RT_NULL) @@ -1046,9 +1046,9 @@ static rt_err_t _function_disable(ufunction_t func) rt_device_close(data->disk); data->disk = RT_NULL; } - + data->status = STAT_CBW; - + return RT_EOK; } @@ -1087,11 +1087,11 @@ ufunction_t rt_usbd_function_mstorage_create(udevice_t device) /* set usb device string description */ rt_usbd_device_set_string(device, _ustring); - + /* create a mass storage function */ func = rt_usbd_function_new(device, &dev_desc, &ops); device->dev_qualifier = &dev_qualifier; - + /* allocate memory for mass storage function data */ data = (struct mstorage*)rt_malloc(sizeof(struct mstorage)); rt_memset(data, 0, sizeof(struct mstorage)); @@ -1102,7 +1102,7 @@ ufunction_t rt_usbd_function_mstorage_create(udevice_t device) /* create an alternate setting object */ setting = rt_usbd_altsetting_new(sizeof(struct umass_descriptor)); - + /* config desc in alternate setting */ rt_usbd_altsetting_config_descriptor(setting, &_mass_desc, (rt_off_t)&((umass_desc_t)0)->intf_desc); @@ -1127,7 +1127,7 @@ ufunction_t rt_usbd_function_mstorage_create(udevice_t device) return func; } -struct udclass msc_class = +struct udclass msc_class = { .rt_usbd_function_create = rt_usbd_function_mstorage_create }; diff --git a/components/drivers/usb/usbdevice/class/mstorage.h b/components/drivers/usb/usbdevice/class/mstorage.h index 254038195b..6c81809ef2 100644 --- a/components/drivers/usb/usbdevice/class/mstorage.h +++ b/components/drivers/usb/usbdevice/class/mstorage.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -8,7 +8,7 @@ * 2012-10-01 Yi Qiu first version * 2012-12-12 heyuanjie87 add MASS endpoints collection */ - + #ifndef __MSTORAGE_H__ #define __MSTORAGE_H__ @@ -23,7 +23,7 @@ struct umass_descriptor #endif struct uinterface_descriptor intf_desc; struct uendpoint_descriptor ep_out_desc; - struct uendpoint_descriptor ep_in_desc; + struct uendpoint_descriptor ep_in_desc; }; typedef struct umass_descriptor* umass_desc_t; diff --git a/components/drivers/usb/usbdevice/class/ndis.h b/components/drivers/usb/usbdevice/class/ndis.h index 6d6943366e..b83f3c78ec 100644 --- a/components/drivers/usb/usbdevice/class/ndis.h +++ b/components/drivers/usb/usbdevice/class/ndis.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,14 +7,14 @@ * Date Author Notes */ /* - * ndis.h - * + * ndis.h + * * Modified by Colin O'Flynn * ntddndis.h modified by Benedikt Spranger - * - * Thanks to the cygwin development team, + * + * Thanks to the cygwin development team, * espacially to Casper S. Hornstrup - * + * * THIS SOFTWARE IS NOT COPYRIGHTED * * This source code is offered for use in the public domain. You may @@ -30,7 +30,7 @@ #ifndef __NDIS_H__ #define __NDIS_H__ -#define NDIS_STATUS_MULTICAST_FULL 0xC0010009 +#define NDIS_STATUS_MULTICAST_FULL 0xC0010009 #define NDIS_STATUS_MULTICAST_EXISTS 0xC001000A #define NDIS_STATUS_MULTICAST_NOT_FOUND 0xC001000B @@ -42,21 +42,21 @@ #define OID_PNP_REMOVE_WAKE_UP_PATTERN 0xFD010104 #define OID_PNP_ENABLE_WAKE_UP 0xFD010106 -enum NDIS_DEVICE_POWER_STATE +enum NDIS_DEVICE_POWER_STATE { - NdisDeviceStateUnspecified = 0, - NdisDeviceStateD0, - NdisDeviceStateD1, - NdisDeviceStateD2, - NdisDeviceStateD3, - NdisDeviceStateMaximum + NdisDeviceStateUnspecified = 0, + NdisDeviceStateD0, + NdisDeviceStateD1, + NdisDeviceStateD2, + NdisDeviceStateD3, + NdisDeviceStateMaximum }; struct NDIS_PM_WAKE_UP_CAPABILITIES { - enum NDIS_DEVICE_POWER_STATE MinMagicPacketWakeUp; - enum NDIS_DEVICE_POWER_STATE MinPatternWakeUp; - enum NDIS_DEVICE_POWER_STATE MinLinkChangeWakeUp; + enum NDIS_DEVICE_POWER_STATE MinMagicPacketWakeUp; + enum NDIS_DEVICE_POWER_STATE MinPatternWakeUp; + enum NDIS_DEVICE_POWER_STATE MinLinkChangeWakeUp; }; /* NDIS_PNP_CAPABILITIES.Flags constants */ @@ -194,36 +194,36 @@ struct NDIS_PM_WAKE_UP_CAPABILITIES #define NDIS_MINIPORT_SUPPORTS_CANCEL_SEND_PACKETS 0x00800000 #define NDIS_MINIPORT_64BITS_DMA 0x01000000 -#define NDIS_MEDIUM_802_3 0x00000000 -#define NDIS_MEDIUM_802_5 0x00000001 -#define NDIS_MEDIUM_FDDI 0x00000002 -#define NDIS_MEDIUM_WAN 0x00000003 -#define NDIS_MEDIUM_LOCAL_TALK 0x00000004 -#define NDIS_MEDIUM_DIX 0x00000005 +#define NDIS_MEDIUM_802_3 0x00000000 +#define NDIS_MEDIUM_802_5 0x00000001 +#define NDIS_MEDIUM_FDDI 0x00000002 +#define NDIS_MEDIUM_WAN 0x00000003 +#define NDIS_MEDIUM_LOCAL_TALK 0x00000004 +#define NDIS_MEDIUM_DIX 0x00000005 #define NDIS_MEDIUM_ARCENT_RAW 0x00000006 #define NDIS_MEDIUM_ARCENT_878_2 0x00000007 -#define NDIS_MEDIUM_ATM 0x00000008 +#define NDIS_MEDIUM_ATM 0x00000008 #define NDIS_MEDIUM_WIRELESS_LAN 0x00000009 -#define NDIS_MEDIUM_IRDA 0x0000000A -#define NDIS_MEDIUM_BPC 0x0000000B -#define NDIS_MEDIUM_CO_WAN 0x0000000C -#define NDIS_MEDIUM_1394 0x0000000D - -#define NDIS_PACKET_TYPE_DIRECTED 0x00000001 -#define NDIS_PACKET_TYPE_MULTICAST 0x00000002 -#define NDIS_PACKET_TYPE_ALL_MULTICAST 0x00000004 -#define NDIS_PACKET_TYPE_BROADCAST 0x00000008 -#define NDIS_PACKET_TYPE_SOURCE_ROUTING 0x00000010 -#define NDIS_PACKET_TYPE_PROMISCUOUS 0x00000020 -#define NDIS_PACKET_TYPE_SMT 0x00000040 -#define NDIS_PACKET_TYPE_ALL_LOCAL 0x00000080 -#define NDIS_PACKET_TYPE_GROUP 0x00000100 -#define NDIS_PACKET_TYPE_ALL_FUNCTIONAL 0x00000200 -#define NDIS_PACKET_TYPE_FUNCTIONAL 0x00000400 -#define NDIS_PACKET_TYPE_MAC_FRAME 0x00000800 - -#define NDIS_MEDIA_STATE_CONNECTED 0x00000000 -#define NDIS_MEDIA_STATE_DISCONNECTED 0x00000001 +#define NDIS_MEDIUM_IRDA 0x0000000A +#define NDIS_MEDIUM_BPC 0x0000000B +#define NDIS_MEDIUM_CO_WAN 0x0000000C +#define NDIS_MEDIUM_1394 0x0000000D + +#define NDIS_PACKET_TYPE_DIRECTED 0x00000001 +#define NDIS_PACKET_TYPE_MULTICAST 0x00000002 +#define NDIS_PACKET_TYPE_ALL_MULTICAST 0x00000004 +#define NDIS_PACKET_TYPE_BROADCAST 0x00000008 +#define NDIS_PACKET_TYPE_SOURCE_ROUTING 0x00000010 +#define NDIS_PACKET_TYPE_PROMISCUOUS 0x00000020 +#define NDIS_PACKET_TYPE_SMT 0x00000040 +#define NDIS_PACKET_TYPE_ALL_LOCAL 0x00000080 +#define NDIS_PACKET_TYPE_GROUP 0x00000100 +#define NDIS_PACKET_TYPE_ALL_FUNCTIONAL 0x00000200 +#define NDIS_PACKET_TYPE_FUNCTIONAL 0x00000400 +#define NDIS_PACKET_TYPE_MAC_FRAME 0x00000800 + +#define NDIS_MEDIA_STATE_CONNECTED 0x00000000 +#define NDIS_MEDIA_STATE_DISCONNECTED 0x00000001 #define NDIS_MAC_OPTION_COPY_LOOKAHEAD_DATA 0x00000001 #define NDIS_MAC_OPTION_RECEIVE_SERIALIZED 0x00000002 diff --git a/components/drivers/usb/usbdevice/class/rndis.c b/components/drivers/usb/usbdevice/class/rndis.c index 93e0ba6ae2..391924dba0 100644 --- a/components/drivers/usb/usbdevice/class/rndis.c +++ b/components/drivers/usb/usbdevice/class/rndis.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -215,7 +215,7 @@ const static char* _ustring[] = }; ALIGN(4) -struct usb_os_function_comp_id_descriptor rndis_func_comp_id_desc = +struct usb_os_function_comp_id_descriptor rndis_func_comp_id_desc = { .bFirstInterfaceNumber = USB_DYNAMIC, .reserved1 = 0x01, @@ -347,7 +347,7 @@ static rt_err_t _rndis_init_response(ufunction_t func, rndis_init_msg_t msg) rt_list_insert_before(&((rt_rndis_eth_t)func->user_data)->response_list, &response->list); rt_hw_interrupt_enable(level); } - + return RT_EOK; } @@ -764,7 +764,7 @@ static rt_err_t send_encapsulated_command_done(udevice_t device, rt_size_t size) } //#error here have bug ep 0x82 send failed static rt_err_t _rndis_send_encapsulated_command(ufunction_t func, ureq_t setup) -{ +{ RT_ASSERT(setup->wLength <= sizeof(rndis_message_buffer)); function = func; rt_usbd_ep0_read(func->device,rndis_message_buffer,setup->wLength,send_encapsulated_command_done); @@ -808,7 +808,7 @@ static rt_err_t _rndis_get_encapsulated_response(ufunction_t func, ureq_t setup) data[1] = 0; ((rt_rndis_eth_t)func->user_data)->eps.ep_cmd->request.buffer = ((rt_rndis_eth_t)func->user_data)->eps.ep_cmd->buffer; ((rt_rndis_eth_t)func->user_data)->eps.ep_cmd->request.size = 8; - ((rt_rndis_eth_t)func->user_data)->eps.ep_cmd->request.req_type = UIO_REQUEST_WRITE; + ((rt_rndis_eth_t)func->user_data)->eps.ep_cmd->request.req_type = UIO_REQUEST_WRITE; rt_usbd_io_request(func->device, ((rt_rndis_eth_t)func->user_data)->eps.ep_cmd, &((rt_rndis_eth_t)func->user_data)->eps.ep_cmd->request); } else @@ -983,7 +983,7 @@ static rt_err_t _function_enable(ufunction_t func) ((rt_rndis_eth_t)func->user_data)->need_notify = RT_TRUE; rt_hw_interrupt_enable(level); } - + return RT_EOK; } @@ -1022,7 +1022,7 @@ static rt_err_t _function_disable(ufunction_t func) rt_hw_interrupt_enable(level); } - + /* link down. */ eth_device_linkchange(&((rt_rndis_eth_t)func->user_data)->parent, RT_FALSE); @@ -1323,7 +1323,7 @@ ufunction_t rt_usbd_function_rndis_create(udevice_t device) /* create a cdc class */ cdc = rt_usbd_function_new(device, &_dev_desc, &ops); rt_usbd_device_set_qualifier(device, &dev_qualifier); - _rndis= rt_malloc(sizeof(struct rt_rndis_eth)); + _rndis= rt_malloc(sizeof(struct rt_rndis_eth)); rt_memset(_rndis, 0, sizeof(struct rt_rndis_eth)); cdc->user_data = _rndis; @@ -1357,7 +1357,7 @@ ufunction_t rt_usbd_function_rndis_create(udevice_t device) rt_usbd_set_altsetting(intf_comm, 0); /* add the communication interface to the cdc class */ rt_usbd_function_add_interface(cdc, intf_comm); - + /* create a bulk in and a bulk out endpoint */ data_desc = (ucdc_data_desc_t)data_setting->desc; eps->ep_out = rt_usbd_endpoint_new(&data_desc->ep_out_desc, _ep_out_handler); @@ -1434,7 +1434,7 @@ ufunction_t rt_usbd_function_rndis_create(udevice_t device) return cdc; } -struct udclass rndis_class = +struct udclass rndis_class = { .rt_usbd_function_create = rt_usbd_function_rndis_create }; diff --git a/components/drivers/usb/usbdevice/class/rndis.h b/components/drivers/usb/usbdevice/class/rndis.h index fcdd249984..f25ae4931c 100644 --- a/components/drivers/usb/usbdevice/class/rndis.h +++ b/components/drivers/usb/usbdevice/class/rndis.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,43 +13,43 @@ #include -#define USB_ETH_MTU 1500+14 +#define USB_ETH_MTU 1500+14 #define RNDIS_MESSAGE_BUFFER_SIZE 128 #define RESPONSE_AVAILABLE 0x00000001 /* Remote NDIS version numbers */ -#define RNDIS_MAJOR_VERSION 1 +#define RNDIS_MAJOR_VERSION 1 #define RNDIS_MINOR_VERSION 0 /* common status values */ -#define RNDIS_STATUS_SUCCESS 0X00000000 -#define RNDIS_STATUS_FAILURE 0XC0000001 -#define RNDIS_STATUS_INVALID_DATA 0XC0010015 -#define RNDIS_STATUS_NOT_SUPPORTED 0XC00000BB -#define RNDIS_STATUS_MEDIA_CONNECT 0X4001000B -#define RNDIS_STATUS_MEDIA_DISCONNECT 0X4001000C +#define RNDIS_STATUS_SUCCESS 0X00000000 +#define RNDIS_STATUS_FAILURE 0XC0000001 +#define RNDIS_STATUS_INVALID_DATA 0XC0010015 +#define RNDIS_STATUS_NOT_SUPPORTED 0XC00000BB +#define RNDIS_STATUS_MEDIA_CONNECT 0X4001000B +#define RNDIS_STATUS_MEDIA_DISCONNECT 0X4001000C /* Remote NDIS message types */ -#define REMOTE_NDIS_PACKET_MSG 0x00000001 -#define REMOTE_NDIS_INITIALIZE_MSG 0X00000002 -#define REMOTE_NDIS_HALT_MSG 0X00000003 -#define REMOTE_NDIS_QUERY_MSG 0X00000004 -#define REMOTE_NDIS_SET_MSG 0X00000005 -#define REMOTE_NDIS_RESET_MSG 0X00000006 +#define REMOTE_NDIS_PACKET_MSG 0x00000001 +#define REMOTE_NDIS_INITIALIZE_MSG 0X00000002 +#define REMOTE_NDIS_HALT_MSG 0X00000003 +#define REMOTE_NDIS_QUERY_MSG 0X00000004 +#define REMOTE_NDIS_SET_MSG 0X00000005 +#define REMOTE_NDIS_RESET_MSG 0X00000006 #define REMOTE_NDIS_INDICATE_STATUS_MSG 0X00000007 -#define REMOTE_NDIS_KEEPALIVE_MSG 0X00000008 -#define REMOTE_NDIS_INITIALIZE_CMPLT 0X80000002 -#define REMOTE_NDIS_QUERY_CMPLT 0X80000004 -#define REMOTE_NDIS_SET_CMPLT 0X80000005 -#define REMOTE_NDIS_RESET_CMPLT 0X80000006 -#define REMOTE_NDIS_KEEPALIVE_CMPLT 0X80000008 +#define REMOTE_NDIS_KEEPALIVE_MSG 0X00000008 +#define REMOTE_NDIS_INITIALIZE_CMPLT 0X80000002 +#define REMOTE_NDIS_QUERY_CMPLT 0X80000004 +#define REMOTE_NDIS_SET_CMPLT 0X80000005 +#define REMOTE_NDIS_RESET_CMPLT 0X80000006 +#define REMOTE_NDIS_KEEPALIVE_CMPLT 0X80000008 /* device flags */ -#define RNDIS_DF_CONNECTIONLESS 0x00000001 -#define RNDIS_DF_CONNECTION_ORIENTED 0x00000002 +#define RNDIS_DF_CONNECTIONLESS 0x00000001 +#define RNDIS_DF_CONNECTION_ORIENTED 0x00000002 /* mediums */ -#define RNDIS_MEDIUM_802_3 0x00000000 +#define RNDIS_MEDIUM_802_3 0x00000000 struct ucls_rndis { @@ -64,24 +64,24 @@ struct ucls_rndis /* Remote NDIS generic message type */ struct rndis_gen_msg { - rt_uint32_t MessageType; - rt_uint32_t MessageLength; + rt_uint32_t MessageType; + rt_uint32_t MessageLength; }; typedef struct rndis_gen_msg* rndis_gen_msg_t; struct rndis_packet_msg { - rt_uint32_t MessageType; - rt_uint32_t MessageLength; - rt_uint32_t DataOffset; - rt_uint32_t DataLength; - rt_uint32_t OOBDataOffset; - rt_uint32_t OOBDataLength; - rt_uint32_t NumOOBDataElements; - rt_uint32_t PerPacketInfoOffset; - rt_uint32_t PerPacketInfoLength; - rt_uint32_t VcHandle; - rt_uint32_t Reserved; + rt_uint32_t MessageType; + rt_uint32_t MessageLength; + rt_uint32_t DataOffset; + rt_uint32_t DataLength; + rt_uint32_t OOBDataOffset; + rt_uint32_t OOBDataLength; + rt_uint32_t NumOOBDataElements; + rt_uint32_t PerPacketInfoOffset; + rt_uint32_t PerPacketInfoLength; + rt_uint32_t VcHandle; + rt_uint32_t Reserved; }; typedef struct rndis_packet_msg* rndis_packet_msg_t; @@ -89,132 +89,132 @@ typedef struct rndis_packet_msg* rndis_packet_msg_t; struct rndis_init_msg { rt_uint32_t MessageType; - rt_uint32_t MessageLength; - rt_uint32_t RequestId; - rt_uint32_t MajorVersion; - rt_uint32_t MinorVersion; - rt_uint32_t MaxTransferSize; + rt_uint32_t MessageLength; + rt_uint32_t RequestId; + rt_uint32_t MajorVersion; + rt_uint32_t MinorVersion; + rt_uint32_t MaxTransferSize; }; typedef struct rndis_init_msg* rndis_init_msg_t; /* Response */ struct rndis_init_cmplt { - rt_uint32_t MessageType; - rt_uint32_t MessageLength; - rt_uint32_t RequestId; - rt_uint32_t Status; - rt_uint32_t MajorVersion; - rt_uint32_t MinorVersion; - rt_uint32_t DeviceFlags; - rt_uint32_t Medium; + rt_uint32_t MessageType; + rt_uint32_t MessageLength; + rt_uint32_t RequestId; + rt_uint32_t Status; + rt_uint32_t MajorVersion; + rt_uint32_t MinorVersion; + rt_uint32_t DeviceFlags; + rt_uint32_t Medium; rt_uint32_t MaxPacketsPerTransfer; - rt_uint32_t MaxTransferSize; + rt_uint32_t MaxTransferSize; rt_uint32_t PacketAlignmentFactor; - rt_uint32_t AfListOffset; - rt_uint32_t AfListSize; + rt_uint32_t AfListOffset; + rt_uint32_t AfListSize; }; typedef struct rndis_init_cmplt* rndis_init_cmplt_t; /* Remote NDIS Halt Message */ struct rndis_halt_msg { - rt_uint32_t MessageType; - rt_uint32_t MessageLength; - rt_uint32_t RequestId; + rt_uint32_t MessageType; + rt_uint32_t MessageLength; + rt_uint32_t RequestId; }; /* Remote NDIS Query Message */ struct rndis_query_msg { - rt_uint32_t MessageType; - rt_uint32_t MessageLength; - rt_uint32_t RequestId; - rt_uint32_t Oid; - rt_uint32_t InformationBufferLength; - rt_uint32_t InformationBufferOffset; - rt_uint32_t DeviceVcHandle; + rt_uint32_t MessageType; + rt_uint32_t MessageLength; + rt_uint32_t RequestId; + rt_uint32_t Oid; + rt_uint32_t InformationBufferLength; + rt_uint32_t InformationBufferOffset; + rt_uint32_t DeviceVcHandle; }; typedef struct rndis_query_msg* rndis_query_msg_t; /* Response */ struct rndis_query_cmplt { - rt_uint32_t MessageType; - rt_uint32_t MessageLength; - rt_uint32_t RequestId; - rt_uint32_t Status; - rt_uint32_t InformationBufferLength; - rt_uint32_t InformationBufferOffset; + rt_uint32_t MessageType; + rt_uint32_t MessageLength; + rt_uint32_t RequestId; + rt_uint32_t Status; + rt_uint32_t InformationBufferLength; + rt_uint32_t InformationBufferOffset; }; typedef struct rndis_query_cmplt* rndis_query_cmplt_t; /* Remote NDIS Set Message */ struct rndis_set_msg { - rt_uint32_t MessageType; - rt_uint32_t MessageLength; - rt_uint32_t RequestId; - rt_uint32_t Oid; - rt_uint32_t InformationBufferLength; - rt_uint32_t InformationBufferOffset; - rt_uint32_t DeviceVcHandle; + rt_uint32_t MessageType; + rt_uint32_t MessageLength; + rt_uint32_t RequestId; + rt_uint32_t Oid; + rt_uint32_t InformationBufferLength; + rt_uint32_t InformationBufferOffset; + rt_uint32_t DeviceVcHandle; }; typedef struct rndis_set_msg* rndis_set_msg_t; /* Response */ struct rndis_set_cmplt { - rt_uint32_t MessageType; - rt_uint32_t MessageLength; - rt_uint32_t RequestId; - rt_uint32_t Status; + rt_uint32_t MessageType; + rt_uint32_t MessageLength; + rt_uint32_t RequestId; + rt_uint32_t Status; }; typedef struct rndis_set_cmplt* rndis_set_cmplt_t; /* Remote NDIS Soft Reset Message */ struct rndis_reset_msg { - rt_uint32_t MessageType; - rt_uint32_t MessageLength; - rt_uint32_t Reserved; + rt_uint32_t MessageType; + rt_uint32_t MessageLength; + rt_uint32_t Reserved; }; /* Remote NDIS Soft Reset Response */ struct rndis_reset_cmplt { - rt_uint32_t MessageType; - rt_uint32_t MessageLength; - rt_uint32_t Status; - rt_uint32_t AddressingReset; + rt_uint32_t MessageType; + rt_uint32_t MessageLength; + rt_uint32_t Status; + rt_uint32_t AddressingReset; }; /* Remote NDIS Indicate Status Message */ struct rndis_indicate_status_msg { rt_uint32_t MessageType; - rt_uint32_t MessageLength; - rt_uint32_t Status; - rt_uint32_t StatusBufferLength; - rt_uint32_t StatusBufferOffset; + rt_uint32_t MessageLength; + rt_uint32_t Status; + rt_uint32_t StatusBufferLength; + rt_uint32_t StatusBufferOffset; }; typedef struct rndis_indicate_status_msg* rndis_indicate_status_msg_t; struct rndis_keepalive_msg { - rt_uint32_t MessageType; - rt_uint32_t MessageLength; - rt_uint32_t RequestID; + rt_uint32_t MessageType; + rt_uint32_t MessageLength; + rt_uint32_t RequestID; }; typedef struct rndis_keepalive_msg* rndis_keepalive_msg_t; /* Response: */ struct rndis_keepalive_cmplt { - rt_uint32_t MessageType; - rt_uint32_t MessageLength; - rt_uint32_t RequestId; - rt_uint32_t Status; + rt_uint32_t MessageType; + rt_uint32_t MessageLength; + rt_uint32_t RequestId; + rt_uint32_t Status; }; typedef struct rndis_keepalive_cmplt* rndis_keepalive_cmplt_t; diff --git a/components/drivers/usb/usbdevice/class/winusb.c b/components/drivers/usb/usbdevice/class/winusb.c index 4af6dba3cf..0db3de794a 100644 --- a/components/drivers/usb/usbdevice/class/winusb.c +++ b/components/drivers/usb/usbdevice/class/winusb.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -57,7 +57,7 @@ static struct usb_qualifier_descriptor dev_qualifier = }; ALIGN(4) -struct winusb_descriptor _winusb_desc = +struct winusb_descriptor _winusb_desc = { #ifdef RT_USB_DEVICE_COMPOSITE /* Interface Association Descriptor */ @@ -117,13 +117,13 @@ const static char* _ustring[] = }; ALIGN(4) -struct usb_os_proerty winusb_proerty[] = +struct usb_os_proerty winusb_proerty[] = { USB_OS_PROPERTY_DESC(USB_OS_PROPERTY_TYPE_REG_SZ,"DeviceInterfaceGUID",RT_WINUSB_GUID), }; ALIGN(4) -struct usb_os_function_comp_id_descriptor winusb_func_comp_id_desc = +struct usb_os_function_comp_id_descriptor winusb_func_comp_id_desc = { .bFirstInterfaceNumber = USB_DYNAMIC, .reserved1 = 0x01, @@ -155,7 +155,7 @@ static ufunction_t cmd_func = RT_NULL; static rt_err_t _ep0_cmd_handler(udevice_t device, rt_size_t size) { winusb_device_t winusb_device; - + if(cmd_func != RT_NULL) { winusb_device = (winusb_device_t)cmd_func->user_data; @@ -191,7 +191,7 @@ static rt_err_t _interface_handler(ufunction_t func, ureq_t setup) _ep0_cmd_read(func, setup); break; } - + return RT_EOK; } static rt_err_t _function_enable(ufunction_t func) @@ -291,7 +291,7 @@ static rt_err_t rt_usb_winusb_init(ufunction_t func) winusb_device->parent.user_data = func; - + return rt_device_register(&winusb_device->parent, "winusb", RT_DEVICE_FLAG_RDWR); } @@ -352,7 +352,7 @@ ufunction_t rt_usbd_function_winusb_create(udevice_t device) return func; } -struct udclass winusb_class = +struct udclass winusb_class = { .rt_usbd_function_create = rt_usbd_function_winusb_create }; diff --git a/components/drivers/usb/usbdevice/class/winusb.h b/components/drivers/usb/usbdevice/class/winusb.h index b5f87b4e56..43fec34b6a 100644 --- a/components/drivers/usb/usbdevice/class/winusb.h +++ b/components/drivers/usb/usbdevice/class/winusb.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/usb/usbdevice/core/usbdevice.c b/components/drivers/usb/usbdevice/core/usbdevice.c index 2455bd8017..246b3f5aef 100644 --- a/components/drivers/usb/usbdevice/core/usbdevice.c +++ b/components/drivers/usb/usbdevice/core/usbdevice.c @@ -3,7 +3,7 @@ * COPYRIGHT (C) 2008 - 2018, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 - * + * * Change Logs: * Date Author Notes * 2012-10-02 Yi Qiu first version @@ -62,7 +62,7 @@ static struct usb_qualifier_descriptor dev_qualifier = }; #endif -struct usb_os_comp_id_descriptor usb_comp_id_desc = +struct usb_os_comp_id_descriptor usb_comp_id_desc = { //head section { diff --git a/components/drivers/usb/usbdevice/core/usbdevice_core.c b/components/drivers/usb/usbdevice/core/usbdevice_core.c index ef569d7bf2..fd205ad37f 100644 --- a/components/drivers/usb/usbdevice/core/usbdevice_core.c +++ b/components/drivers/usb/usbdevice/core/usbdevice_core.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -238,7 +238,7 @@ static rt_err_t _get_interface(struct udevice* device, ureq_t setup) rt_uint8_t value; uintf_t intf; ufunction_t func; - + /* parameter check */ RT_ASSERT(device != RT_NULL); RT_ASSERT(setup != RT_NULL); @@ -262,7 +262,7 @@ static rt_err_t _get_interface(struct udevice* device, ureq_t setup) { intf->handler(func, setup); } - + return RT_EOK; } @@ -293,7 +293,7 @@ static rt_err_t _set_interface(struct udevice* device, ureq_t setup) rt_usbd_ep0_set_stall(device); return -RT_ERROR; } - + /* find the specified interface */ intf = rt_usbd_find_interface(device, setup->wIndex & 0xFF, &func); @@ -309,12 +309,12 @@ static rt_err_t _set_interface(struct udevice* device, ureq_t setup) dcd_ep_enable(device->dcd, ep); } dcd_ep0_send_status(device->dcd); - + if (intf->handler) { intf->handler(func, setup); } - + return RT_EOK; } @@ -336,7 +336,7 @@ static rt_err_t _get_config(struct udevice* device, ureq_t setup) RT_ASSERT(device->curr_cfg != RT_NULL); RT_DEBUG_LOG(RT_DEBUG_USB, ("_get_config\n")); - + if (device->state == USB_STATE_CONFIGURED) { /* get current configuration */ @@ -443,7 +443,7 @@ static rt_err_t _set_address(struct udevice* device, ureq_t setup) dcd_ep0_send_status(device->dcd); RT_DEBUG_LOG(RT_DEBUG_USB, ("_set_address\n")); - + device->state = USB_STATE_ADDRESS; return RT_EOK; @@ -479,7 +479,7 @@ static rt_err_t _request_interface(struct udevice* device, ureq_t setup) { ret = -RT_ERROR; } - + return ret; } @@ -564,9 +564,9 @@ static rt_err_t _standard_request(struct udevice* device, ureq_t setup) case USB_REQ_GET_STATUS: { uep_t ep; - + ep = rt_usbd_find_endpoint(device, RT_NULL, setup->wIndex); - value = ep->stalled; + value = ep->stalled; rt_usbd_ep0_write(device, &value, 2); } break; @@ -581,13 +581,13 @@ static rt_err_t _standard_request(struct udevice* device, ureq_t setup) { rt_usbd_clear_feature(device, setup->wValue, setup->wIndex); dcd_ep0_send_status(dcd); - ep->stalled = RT_FALSE; + ep->stalled = RT_FALSE; for (node = ep->request_list.next; node != &ep->request_list; node = node->next) { - req = (uio_request_t)rt_list_entry(node, struct uio_request, list); + req = (uio_request_t)rt_list_entry(node, struct uio_request, list); rt_usbd_io_request(device, ep, req); - RT_DEBUG_LOG(RT_DEBUG_USB, ("fired a request\n")); + RT_DEBUG_LOG(RT_DEBUG_USB, ("fired a request\n")); } rt_list_init(&ep->request_list); @@ -601,10 +601,10 @@ static rt_err_t _standard_request(struct udevice* device, ureq_t setup) if(USB_EP_HALT == setup->wValue) { ep = rt_usbd_find_endpoint(device, RT_NULL, setup->wIndex); - ep->stalled = RT_TRUE; + ep->stalled = RT_TRUE; rt_usbd_set_feature(device, setup->wValue, setup->wIndex); dcd_ep0_send_status(dcd); - } + } } break; case USB_REQ_SYNCH_FRAME: @@ -698,7 +698,7 @@ static rt_err_t _vendor_request(udevice_t device, ureq_t setup) { rt_uint8_t * pusb_comp_id_desc; rt_list_t *p; - usb_comp_id_desc_size = sizeof(struct usb_os_header_comp_id_descriptor) + + usb_comp_id_desc_size = sizeof(struct usb_os_header_comp_id_descriptor) + (sizeof(struct usb_os_function_comp_id_descriptor)-sizeof(rt_list_t))*rt_list_len(&device->os_comp_id_desc->func_desc); usb_comp_id_desc = (rt_uint8_t *)rt_malloc(usb_comp_id_desc_size); @@ -707,7 +707,7 @@ static rt_err_t _vendor_request(udevice_t device, ureq_t setup) pusb_comp_id_desc = usb_comp_id_desc; rt_memcpy((void *)pusb_comp_id_desc,(void *)&device->os_comp_id_desc->head_desc,sizeof(struct usb_os_header_comp_id_descriptor)); pusb_comp_id_desc += sizeof(struct usb_os_header_comp_id_descriptor); - + for (p = device->os_comp_id_desc->func_desc.next; p != &device->os_comp_id_desc->func_desc; p = p->next) { func_comp_id_desc = rt_list_entry(p,struct usb_os_function_comp_id_descriptor,list); @@ -726,7 +726,7 @@ static rt_err_t _vendor_request(udevice_t device, ureq_t setup) } break; } - + break; } return RT_EOK; @@ -784,7 +784,7 @@ static rt_err_t _setup_request(udevice_t device, ureq_t setup) /** * This function will hanle data notify event. * - * @param device the usb device object. + * @param device the usb device object. * @param ep_msg the endpoint message. * * @return RT_EOK. @@ -794,18 +794,18 @@ static rt_err_t _data_notify(udevice_t device, struct ep_msg* ep_msg) uep_t ep; ufunction_t func; rt_size_t size = 0; - + RT_ASSERT(device != RT_NULL); RT_ASSERT(ep_msg != RT_NULL); - + if (device->state != USB_STATE_CONFIGURED) { return -RT_ERROR; } - + ep = rt_usbd_find_endpoint(device, &func, ep_msg->ep_addr); if(ep == RT_NULL) - { + { rt_kprintf("invalid endpoint\n"); return -RT_ERROR; } @@ -817,7 +817,7 @@ static rt_err_t _data_notify(udevice_t device, struct ep_msg* ep_msg) { dcd_ep_write(device->dcd, EP_ADDRESS(ep), ep->request.buffer, EP_MAXPACKET(ep)); ep->request.remain_size -= EP_MAXPACKET(ep); - ep->request.buffer += EP_MAXPACKET(ep); + ep->request.buffer += EP_MAXPACKET(ep); } else if(ep->request.remain_size > 0) { @@ -834,9 +834,9 @@ static rt_err_t _data_notify(udevice_t device, struct ep_msg* ep_msg) size = ep_msg->size; if(ep->request.remain_size == 0) { - return RT_EOK; + return RT_EOK; } - + if(size == 0) { size = dcd_ep_read(device->dcd, EP_ADDRESS(ep), ep->request.buffer); @@ -865,9 +865,9 @@ static rt_err_t _ep0_out_notify(udevice_t device, struct ep_msg* ep_msg) { uep_t ep0; rt_size_t size; - + RT_ASSERT(device != RT_NULL); - RT_ASSERT(ep_msg != RT_NULL); + RT_ASSERT(ep_msg != RT_NULL); RT_ASSERT(device->dcd != RT_NULL); ep0 = &device->dcd->ep0; @@ -875,18 +875,18 @@ static rt_err_t _ep0_out_notify(udevice_t device, struct ep_msg* ep_msg) if(ep0->request.remain_size == 0) { - return RT_EOK; - } + return RT_EOK; + } if(size == 0) { size = dcd_ep_read(device->dcd, EP0_OUT_ADDR, ep0->request.buffer); if(size == 0) { return RT_EOK; - } + } } - ep0->request.remain_size -= size; + ep0->request.remain_size -= size; ep0->request.buffer += size; if(ep0->request.remain_size == 0) { @@ -894,7 +894,7 @@ static rt_err_t _ep0_out_notify(udevice_t device, struct ep_msg* ep_msg) if(ep0->rx_indicate != RT_NULL) { ep0->rx_indicate(device, size); - } + } } else { @@ -959,10 +959,10 @@ static rt_err_t _stop_notify(udevice_t device) static rt_size_t rt_usbd_ep_write(udevice_t device, uep_t ep, void *buffer, rt_size_t size) { rt_uint16_t maxpacket; - - RT_ASSERT(device != RT_NULL); + + RT_ASSERT(device != RT_NULL); RT_ASSERT(device->dcd != RT_NULL); - RT_ASSERT(ep != RT_NULL); + RT_ASSERT(ep != RT_NULL); rt_enter_critical(); maxpacket = EP_MAXPACKET(ep); @@ -970,11 +970,11 @@ static rt_size_t rt_usbd_ep_write(udevice_t device, uep_t ep, void *buffer, rt_s { dcd_ep_write(device->dcd, EP_ADDRESS(ep), ep->request.buffer, maxpacket); ep->request.remain_size -= maxpacket; - ep->request.buffer += maxpacket; + ep->request.buffer += maxpacket; } else { - dcd_ep_write(device->dcd, EP_ADDRESS(ep), ep->request.buffer, + dcd_ep_write(device->dcd, EP_ADDRESS(ep), ep->request.buffer, ep->request.remain_size); ep->request.remain_size = 0; } @@ -984,9 +984,9 @@ static rt_size_t rt_usbd_ep_write(udevice_t device, uep_t ep, void *buffer, rt_s static rt_size_t rt_usbd_ep_read_prepare(udevice_t device, uep_t ep, void *buffer, rt_size_t size) { - RT_ASSERT(device != RT_NULL); + RT_ASSERT(device != RT_NULL); RT_ASSERT(device->dcd != RT_NULL); - RT_ASSERT(ep != RT_NULL); + RT_ASSERT(ep != RT_NULL); RT_ASSERT(buffer != RT_NULL); RT_ASSERT(ep->ep_desc != RT_NULL); @@ -1705,7 +1705,7 @@ rt_err_t rt_usbd_set_config(udevice_t device, rt_uint8_t value) device->curr_cfg = cfg; dcd_set_config(device->dcd, value); - + return RT_TRUE; } @@ -1713,7 +1713,7 @@ rt_err_t rt_usbd_set_config(udevice_t device, rt_uint8_t value) * This function will bRequest an IO transaction. * * @param device the usb device object. - * @param ep the endpoint object. + * @param ep the endpoint object. * @param req IO bRequest. * * @return RT_EOK. @@ -1721,7 +1721,7 @@ rt_err_t rt_usbd_set_config(udevice_t device, rt_uint8_t value) rt_size_t rt_usbd_io_request(udevice_t device, uep_t ep, uio_request_t req) { rt_size_t size = 0; - + RT_ASSERT(device != RT_NULL); RT_ASSERT(req != RT_NULL); @@ -1747,7 +1747,7 @@ rt_size_t rt_usbd_io_request(udevice_t device, uep_t ep, uio_request_t req) { rt_list_insert_before(&ep->request_list, &req->list); RT_DEBUG_LOG(RT_DEBUG_USB, ("suspend a request\n")); - } + } return size; } @@ -1770,10 +1770,10 @@ rt_err_t rt_usbd_set_feature(udevice_t device, rt_uint16_t value, rt_uint16_t in } else if (value == USB_FEATURE_ENDPOINT_HALT) { - RT_DEBUG_LOG(RT_DEBUG_USB, ("set feature stall\n")); + RT_DEBUG_LOG(RT_DEBUG_USB, ("set feature stall\n")); dcd_ep_set_stall(device->dcd, (rt_uint32_t)(index & 0xFF)); } - + return RT_EOK; } @@ -1798,38 +1798,38 @@ rt_err_t rt_usbd_clear_feature(udevice_t device, rt_uint16_t value, rt_uint16_t RT_DEBUG_LOG(RT_DEBUG_USB, ("clear feature stall\n")); dcd_ep_clear_stall(device->dcd, (rt_uint32_t)(index & 0xFF)); } - + return RT_EOK; } rt_err_t rt_usbd_ep0_set_stall(udevice_t device) { RT_ASSERT(device != RT_NULL); - + return dcd_ep_set_stall(device->dcd, 0); } rt_err_t rt_usbd_ep0_clear_stall(udevice_t device) { RT_ASSERT(device != RT_NULL); - + return dcd_ep_clear_stall(device->dcd, 0); } rt_err_t rt_usbd_ep_set_stall(udevice_t device, uep_t ep) { rt_err_t ret; - + RT_ASSERT(device != RT_NULL); RT_ASSERT(ep != RT_NULL); - RT_ASSERT(ep->ep_desc != RT_NULL); + RT_ASSERT(ep->ep_desc != RT_NULL); ret = dcd_ep_set_stall(device->dcd, EP_ADDRESS(ep)); if(ret == RT_EOK) { ep->stalled = RT_TRUE; } - + return ret; } @@ -1846,44 +1846,44 @@ rt_err_t rt_usbd_ep_clear_stall(udevice_t device, uep_t ep) { ep->stalled = RT_FALSE; } - + return ret; } static rt_err_t rt_usbd_ep_assign(udevice_t device, uep_t ep) { int i = 0; - + RT_ASSERT(device != RT_NULL); - RT_ASSERT(device->dcd != RT_NULL); - RT_ASSERT(device->dcd->ep_pool != RT_NULL); + RT_ASSERT(device->dcd != RT_NULL); + RT_ASSERT(device->dcd->ep_pool != RT_NULL); RT_ASSERT(ep != RT_NULL); RT_ASSERT(ep->ep_desc != RT_NULL); while(device->dcd->ep_pool[i].addr != 0xFF) { - if(device->dcd->ep_pool[i].status == ID_UNASSIGNED && + if(device->dcd->ep_pool[i].status == ID_UNASSIGNED && ep->ep_desc->bmAttributes == device->dcd->ep_pool[i].type && (EP_ADDRESS(ep) & 0x80) == device->dcd->ep_pool[i].dir) { EP_ADDRESS(ep) |= device->dcd->ep_pool[i].addr; ep->id = &device->dcd->ep_pool[i]; device->dcd->ep_pool[i].status = ID_ASSIGNED; - RT_DEBUG_LOG(RT_DEBUG_USB, ("assigned %d\n", device->dcd->ep_pool[i].addr)); + RT_DEBUG_LOG(RT_DEBUG_USB, ("assigned %d\n", device->dcd->ep_pool[i].addr)); return RT_EOK; } - + i++; } - + return -RT_ERROR; } rt_err_t rt_usbd_ep_unassign(udevice_t device, uep_t ep) { RT_ASSERT(device != RT_NULL); - RT_ASSERT(device->dcd != RT_NULL); - RT_ASSERT(device->dcd->ep_pool != RT_NULL); + RT_ASSERT(device->dcd != RT_NULL); + RT_ASSERT(device->dcd->ep_pool != RT_NULL); RT_ASSERT(ep != RT_NULL); RT_ASSERT(ep->ep_desc != RT_NULL); @@ -1911,8 +1911,8 @@ rt_err_t rt_usbd_ep0_setup_handler(udcd_t dcd, struct urequest* setup) else { rt_memcpy((void*)&msg.content.setup, (void*)setup, sizeof(struct urequest)); - } - + } + msg.type = USB_MSG_SETUP_NOTIFY; msg.dcd = dcd; rt_usbd_event_signal(&msg); @@ -2011,7 +2011,7 @@ rt_err_t rt_usbd_reset_handler(udcd_t dcd) struct udev_msg msg; RT_ASSERT(dcd != RT_NULL); - + msg.type = USB_MSG_RESET; msg.dcd = dcd; rt_usbd_event_signal(&msg); @@ -2024,7 +2024,7 @@ rt_err_t rt_usbd_connect_handler(udcd_t dcd) struct udev_msg msg; RT_ASSERT(dcd != RT_NULL); - + msg.type = USB_MSG_PLUG_IN; msg.dcd = dcd; rt_usbd_event_signal(&msg); @@ -2037,7 +2037,7 @@ rt_err_t rt_usbd_disconnect_handler(udcd_t dcd) struct udev_msg msg; RT_ASSERT(dcd != RT_NULL); - + msg.type = USB_MSG_PLUG_OUT; msg.dcd = dcd; rt_usbd_event_signal(&msg); @@ -2050,7 +2050,7 @@ rt_err_t rt_usbd_sof_handler(udcd_t dcd) struct udev_msg msg; RT_ASSERT(dcd != RT_NULL); - + msg.type = USB_MSG_SOF; msg.dcd = dcd; rt_usbd_event_signal(&msg); @@ -2063,7 +2063,7 @@ rt_size_t rt_usbd_ep0_write(udevice_t device, void *buffer, rt_size_t size) uep_t ep0; rt_size_t sent_size = 0; - RT_ASSERT(device != RT_NULL); + RT_ASSERT(device != RT_NULL); RT_ASSERT(device->dcd != RT_NULL); RT_ASSERT(buffer != RT_NULL); RT_ASSERT(size > 0); @@ -2085,7 +2085,7 @@ rt_size_t rt_usbd_ep0_write(udevice_t device, void *buffer, rt_size_t size) return dcd_ep_write(device->dcd, EP0_IN_ADDR, ep0->request.buffer, sent_size); } -rt_size_t rt_usbd_ep0_read(udevice_t device, void *buffer, rt_size_t size, +rt_size_t rt_usbd_ep0_read(udevice_t device, void *buffer, rt_size_t size, rt_err_t (*rx_ind)(udevice_t device, rt_size_t size)) { uep_t ep0; @@ -2096,7 +2096,7 @@ rt_size_t rt_usbd_ep0_read(udevice_t device, void *buffer, rt_size_t size, RT_ASSERT(buffer != RT_NULL); ep0 = &device->dcd->ep0; - ep0->request.buffer = (rt_uint8_t *)buffer; + ep0->request.buffer = (rt_uint8_t *)buffer; ep0->request.remain_size = size; ep0->rx_indicate = rx_ind; if(size >= ep0->id->maxpacket) @@ -2143,7 +2143,7 @@ static void rt_usbd_thread_entry(void* parameter) } RT_DEBUG_LOG(RT_DEBUG_USB, ("message type %d\n", msg.type)); - + switch (msg.type) { case USB_MSG_SOF: @@ -2160,7 +2160,7 @@ static void rt_usbd_thread_entry(void* parameter) case USB_MSG_EP0_OUT: _ep0_out_notify(device, &msg.content.ep_msg); break; - case USB_MSG_RESET: + case USB_MSG_RESET: RT_DEBUG_LOG(RT_DEBUG_USB, ("reset %d\n", device->state)); if (device->state == USB_STATE_ADDRESS || device->state == USB_STATE_CONFIGURED) _stop_notify(device); @@ -2170,7 +2170,7 @@ static void rt_usbd_thread_entry(void* parameter) device->state = USB_STATE_ATTACHED; break; case USB_MSG_PLUG_OUT: - device->state = USB_STATE_NOTATTACHED; + device->state = USB_STATE_NOTATTACHED; _stop_notify(device); break; default: diff --git a/components/drivers/usb/usbhost/class/adk.c b/components/drivers/usb/usbhost/class/adk.c index 2425de7bba..492a2f9bb7 100644 --- a/components/drivers/usb/usbhost/class/adk.c +++ b/components/drivers/usb/usbhost/class/adk.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/usb/usbhost/class/adk.h b/components/drivers/usb/usbhost/class/adk.h index c582ad7f17..aebe7de705 100644 --- a/components/drivers/usb/usbhost/class/adk.h +++ b/components/drivers/usb/usbhost/class/adk.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -19,7 +19,7 @@ struct uadkinst upipe_t pipe_out; struct rt_device device; -}; +}; typedef struct uadkinst* uadk_t; #define USB_ACCESSORY_VENDOR_ID 0x18D1 diff --git a/components/drivers/usb/usbhost/class/hid.c b/components/drivers/usb/usbhost/class/hid.c index e16096877f..4038d3b321 100644 --- a/components/drivers/usb/usbhost/class/hid.c +++ b/components/drivers/usb/usbhost/class/hid.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -23,31 +23,31 @@ static rt_list_t _protocal_list; * @param intf the interface instance. * @duration the idle period of requesting data. * @report_id the report id - * + * * @return the error code, RT_EOK on successfully. */ rt_err_t rt_usbh_hid_set_idle(struct uintf* intf, int duration, int report_id) { struct urequest setup; - struct uinstance* device; + struct uinstance* device; int timeout = USB_TIMEOUT_BASIC; - + /* parameter check */ RT_ASSERT(intf != RT_NULL); RT_ASSERT(intf->device != RT_NULL); device = intf->device; - setup.request_type = USB_REQ_TYPE_DIR_OUT | USB_REQ_TYPE_CLASS | + setup.request_type = USB_REQ_TYPE_DIR_OUT | USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE; setup.request = USB_REQ_SET_IDLE; setup.index = 0; setup.length = 0; setup.value = (duration << 8 )| report_id; - if(rt_usb_hcd_control_xfer(device->hcd, device, &setup, RT_NULL, 0, + if(rt_usb_hcd_control_xfer(device->hcd, device, &setup, RT_NULL, 0, timeout) == 0) return RT_EOK; - else return -RT_FALSE; + else return -RT_FALSE; } /** @@ -56,32 +56,32 @@ rt_err_t rt_usbh_hid_set_idle(struct uintf* intf, int duration, int report_id) * @param intf the interface instance. * @buffer the data buffer to save usb report descriptor. * @param nbytes the size of buffer - * + * * @return the error code, RT_EOK on successfully. */ -rt_err_t rt_usbh_hid_get_report(struct uintf* intf, rt_uint8_t type, +rt_err_t rt_usbh_hid_get_report(struct uintf* intf, rt_uint8_t type, rt_uint8_t id, rt_uint8_t *buffer, rt_size_t size) { struct urequest setup; struct uinstance* device; int timeout = USB_TIMEOUT_BASIC; - + /* parameter check */ RT_ASSERT(intf != RT_NULL); RT_ASSERT(intf->device != RT_NULL); device = intf->device; - setup.request_type = USB_REQ_TYPE_DIR_IN | USB_REQ_TYPE_CLASS | + setup.request_type = USB_REQ_TYPE_DIR_IN | USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE; setup.request = USB_REQ_GET_REPORT; setup.index = intf->intf_desc->bInterfaceNumber; setup.length = size; setup.value = (type << 8 ) + id; - if(rt_usb_hcd_control_xfer(device->hcd, device, &setup, buffer, size, + if(rt_usb_hcd_control_xfer(device->hcd, device, &setup, buffer, size, timeout) == size) return RT_EOK; - else return -RT_FALSE; + else return -RT_FALSE; } /** @@ -90,31 +90,31 @@ rt_err_t rt_usbh_hid_get_report(struct uintf* intf, rt_uint8_t type, * @param intf the interface instance. * @buffer the data buffer to save usb report descriptor. * @param nbytes the size of buffer - * + * * @return the error code, RT_EOK on successfully. */ rt_err_t rt_usbh_hid_set_report(struct uintf* intf, rt_uint8_t *buffer, rt_size_t size) { struct urequest setup; - struct uinstance* device; + struct uinstance* device; int timeout = USB_TIMEOUT_BASIC; - + /* parameter check */ RT_ASSERT(intf != RT_NULL); RT_ASSERT(intf->device != RT_NULL); - + device = intf->device; - setup.request_type = USB_REQ_TYPE_DIR_OUT | USB_REQ_TYPE_CLASS | + setup.request_type = USB_REQ_TYPE_DIR_OUT | USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE; setup.request = USB_REQ_SET_REPORT; setup.index = intf->intf_desc->bInterfaceNumber; setup.length = size; setup.value = 0x02 << 8; - if(rt_usb_hcd_control_xfer(device->hcd, device, &setup, buffer, size, + if(rt_usb_hcd_control_xfer(device->hcd, device, &setup, buffer, size, timeout) == size) return RT_EOK; - else return -RT_FALSE; + else return -RT_FALSE; } /** @@ -122,7 +122,7 @@ rt_err_t rt_usbh_hid_set_report(struct uintf* intf, rt_uint8_t *buffer, rt_size_ * * @param intf the interface instance. * @param protocol the protocol id. - * + * * @return the error code, RT_EOK on successfully. */ rt_err_t rt_usbh_hid_set_protocal(struct uintf* intf, int protocol) @@ -130,56 +130,56 @@ rt_err_t rt_usbh_hid_set_protocal(struct uintf* intf, int protocol) struct urequest setup; struct uinstance* device; int timeout = USB_TIMEOUT_BASIC; - + /* parameter check */ RT_ASSERT(intf != RT_NULL); RT_ASSERT(intf->device != RT_NULL); - + device = intf->device; - setup.request_type = USB_REQ_TYPE_DIR_OUT | USB_REQ_TYPE_CLASS | + setup.request_type = USB_REQ_TYPE_DIR_OUT | USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE; setup.request = USB_REQ_SET_PROTOCOL; setup.index = 0; setup.length = 0; setup.value = protocol; - if(rt_usb_hcd_control_xfer(device->hcd, device, &setup, RT_NULL, 0, + if(rt_usb_hcd_control_xfer(device->hcd, device, &setup, RT_NULL, 0, timeout) == 0) return RT_EOK; - else return -RT_FALSE; + else return -RT_FALSE; } /** - * This function will do USB_REQ_GET_DESCRIPTOR request for the device instance + * This function will do USB_REQ_GET_DESCRIPTOR request for the device instance * to set feature of the hub port. * * @param intf the interface instance. * @buffer the data buffer to save usb report descriptor. * @param nbytes the size of buffer - * + * * @return the error code, RT_EOK on successfully. */ -rt_err_t rt_usbh_hid_get_report_descriptor(struct uintf* intf, +rt_err_t rt_usbh_hid_get_report_descriptor(struct uintf* intf, rt_uint8_t *buffer, rt_size_t size) { struct urequest setup; - struct uinstance* device; + struct uinstance* device; int timeout = USB_TIMEOUT_BASIC; - + /* parameter check */ RT_ASSERT(intf != RT_NULL); RT_ASSERT(intf->device != RT_NULL); - + device = intf->device; - setup.request_type = USB_REQ_TYPE_DIR_IN | USB_REQ_TYPE_STANDARD| + setup.request_type = USB_REQ_TYPE_DIR_IN | USB_REQ_TYPE_STANDARD| USB_REQ_TYPE_INTERFACE; setup.request = USB_REQ_GET_DESCRIPTOR; setup.index = 0; setup.length = size; setup.value = USB_DESC_TYPE_REPORT << 8; - if(rt_usb_hcd_control_xfer(device->hcd, device, &setup, buffer, size, + if(rt_usb_hcd_control_xfer(device->hcd, device, &setup, buffer, size, timeout) == size) return RT_EOK; else return -RT_FALSE; } @@ -188,7 +188,7 @@ rt_err_t rt_usbh_hid_get_report_descriptor(struct uintf* intf, * This function will register specified hid protocal to protocal list * * @param protocal the specified protocal. - * + * * @return the error code, RT_EOK on successfully. */ rt_err_t rt_usbh_hid_protocal_register(uprotocal_t protocal) @@ -199,26 +199,26 @@ rt_err_t rt_usbh_hid_protocal_register(uprotocal_t protocal) /* insert class driver into driver list */ rt_list_insert_after(&_protocal_list, &(protocal->list)); - - return RT_EOK; + + return RT_EOK; } /** * This function is the callback function of hid's int endpoint, it is invoked when data comes. * * @param context the context of the callback function. - * + * * @return none. */ static void rt_usbh_hid_callback(void* context) { - upipe_t pipe; + upipe_t pipe; struct uhid* hid; int timeout = USB_TIMEOUT_LONG; /* parameter check */ RT_ASSERT(context != RT_NULL); - + pipe = (upipe_t)context; hid = (struct uhid*)pipe->intf->user_data; @@ -228,7 +228,7 @@ static void rt_usbh_hid_callback(void* context) /* parameter check */ RT_ASSERT(pipe->intf->device->hcd != RT_NULL); - rt_usb_hcd_int_xfer(pipe->intf->device->hcd, pipe, hid->buffer, + rt_usb_hcd_int_xfer(pipe->intf->device->hcd, pipe, hid->buffer, pipe->ep.wMaxPacketSize, timeout); } @@ -236,7 +236,7 @@ static void rt_usbh_hid_callback(void* context) * This function will find specified hid protocal from protocal list * * @param pro_id the protocal id. - * + * * @return the found protocal or RT_NULL if there is no this protocal. */ static uprotocal_t rt_usbh_hid_protocal_find(int pro_id) @@ -246,7 +246,7 @@ static uprotocal_t rt_usbh_hid_protocal_find(int pro_id) /* try to find protocal object */ for (node = _protocal_list.next; node != &_protocal_list; node = node->next) { - uprotocal_t protocal = + uprotocal_t protocal = (uprotocal_t)rt_list_entry(node, struct uprotocal, list); if (protocal->pro_id == pro_id) return protocal; } @@ -260,18 +260,18 @@ static uprotocal_t rt_usbh_hid_protocal_find(int pro_id) * as a hid class device, it will continue the enumulate process. * * @param arg the argument. - * + * * @return the error code, RT_EOK on successfully. */ static rt_err_t rt_usbh_hid_enable(void* arg) { int i = 0, pro_id; - uprotocal_t protocal; + uprotocal_t protocal; struct uhid* hid; struct uintf* intf = (struct uintf*)arg; int timeout = USB_TIMEOUT_BASIC; upipe_t pipe; - + /* parameter check */ if(intf == RT_NULL) { @@ -282,65 +282,65 @@ static rt_err_t rt_usbh_hid_enable(void* arg) pro_id = intf->intf_desc->bInterfaceProtocol; RT_DEBUG_LOG(RT_DEBUG_USB, - ("HID device enable, protocal id %d\n", pro_id)); + ("HID device enable, protocal id %d\n", pro_id)); - protocal = rt_usbh_hid_protocal_find(pro_id); + protocal = rt_usbh_hid_protocal_find(pro_id); if(protocal == RT_NULL) { rt_kprintf("can't find hid protocal %d\n", pro_id); - intf->user_data = RT_NULL; + intf->user_data = RT_NULL; return -RT_ERROR; } - + hid = rt_malloc(sizeof(struct uhid)); RT_ASSERT(hid != RT_NULL); - /* initilize the data structure */ + /* initilize the data structure */ rt_memset(hid, 0, sizeof(struct uhid)); intf->user_data = (void*)hid; hid->protocal = protocal; - + for(i=0; iintf_desc->bNumEndpoints; i++) - { + { rt_err_t ret; uep_desc_t ep_desc; - /* get endpoint descriptor */ + /* get endpoint descriptor */ rt_usbh_get_endpoint_descriptor(intf->intf_desc, i, &ep_desc); if(ep_desc == RT_NULL) { rt_kprintf("rt_usbh_get_endpoint_descriptor error\n"); return -RT_ERROR; } - - if(USB_EP_ATTR(ep_desc->bmAttributes) != USB_EP_ATTR_INT) + + if(USB_EP_ATTR(ep_desc->bmAttributes) != USB_EP_ATTR_INT) continue; - + if(!(ep_desc->bEndpointAddress & USB_DIR_IN)) continue; - ret = rt_usb_hcd_alloc_pipe(intf->device->hcd, &hid->pipe_in, - intf, ep_desc, rt_usbh_hid_callback); + ret = rt_usb_hcd_alloc_pipe(intf->device->hcd, &hid->pipe_in, + intf, ep_desc, rt_usbh_hid_callback); if(ret != RT_EOK) return ret; } /* initialize hid protocal */ - hid->protocal->init((void*)intf); + hid->protocal->init((void*)intf); pipe = hid->pipe_in; /* parameter check */ RT_ASSERT(pipe->intf->device->hcd != RT_NULL); - - rt_usb_hcd_int_xfer(pipe->intf->device->hcd, hid->pipe_in, + + rt_usb_hcd_int_xfer(pipe->intf->device->hcd, hid->pipe_in, hid->buffer, hid->pipe_in->ep.wMaxPacketSize, timeout); return RT_EOK; } /** - * This function will be invoked when usb device plug out is detected and it would clean + * This function will be invoked when usb device plug out is detected and it would clean * and release all hub class related resources. * * @param arg the argument. - * + * * @return the error code, RT_EOK on successfully. */ static rt_err_t rt_usbh_hid_disable(void* arg) @@ -361,10 +361,10 @@ static rt_err_t rt_usbh_hid_disable(void* arg) rt_usb_hcd_free_pipe(intf->device->hcd, hid->pipe_in); } - /* free the hid instance */ + /* free the hid instance */ rt_free(hid); } - + /* free the instance */ rt_free(intf); @@ -374,7 +374,7 @@ static rt_err_t rt_usbh_hid_disable(void* arg) /** * This function will register hid class driver to the usb class driver manager. * and it should be invoked in the usb system initialization. - * + * * @return the error code, RT_EOK on successfully. */ ucd_t rt_usbh_class_driver_hid(void) @@ -382,7 +382,7 @@ ucd_t rt_usbh_class_driver_hid(void) rt_list_init(&_protocal_list); hid_driver.class_code = USB_CLASS_HID; - + hid_driver.enable = rt_usbh_hid_enable; hid_driver.disable = rt_usbh_hid_disable; diff --git a/components/drivers/usb/usbhost/class/hid.h b/components/drivers/usb/usbhost/class/hid.h index 8e446c8cea..10d3c6ee4d 100644 --- a/components/drivers/usb/usbhost/class/hid.h +++ b/components/drivers/usb/usbhost/class/hid.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -18,7 +18,7 @@ struct uhid upipe_t pipe_in; rt_uint8_t buffer[8]; uprotocal_t protocal; -}; +}; typedef struct uhid uhid_t; #define USB_REQ_GET_REPORT 0x01 @@ -28,7 +28,7 @@ typedef struct uhid uhid_t; #define USB_REQ_SET_IDLE 0x0a #define USB_REQ_SET_PROTOCOL 0x0b -#define USB_HID_KEYBOARD 1 +#define USB_HID_KEYBOARD 1 #define USB_HID_MOUSE 2 rt_err_t rt_usbh_hid_set_idle(struct uintf* intf, int duration, int report_id); diff --git a/components/drivers/usb/usbhost/class/mass.c b/components/drivers/usb/usbhost/class/mass.c index 20048873f5..abd89a5efc 100644 --- a/components/drivers/usb/usbhost/class/mass.c +++ b/components/drivers/usb/usbhost/class/mass.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -24,29 +24,29 @@ static struct uclass_driver storage_driver; * * @param intf the interface instance. * @param max_lun the buffer to save max_lun. - * + * * @return the error code, RT_EOK on successfully. */ static rt_err_t _pipe_check(struct uhintf* intf, upipe_t pipe) { - struct uinstance* device; + struct uinstance* device; rt_err_t ret; ustor_t stor; - int size = 0; + int size = 0; struct ustorage_csw csw; if(intf == RT_NULL || pipe == RT_NULL) { rt_kprintf("the interface is not available\n"); return -RT_EIO; - } + } - /* get usb device instance from the interface instance */ - device = intf->device; + /* get usb device instance from the interface instance */ + device = intf->device; - /* get storage instance from the interface instance */ + /* get storage instance from the interface instance */ stor = (ustor_t)intf->user_data; - + /* check pipe status */ if(pipe->status == UPIPE_STATUS_OK) return RT_EOK; @@ -58,11 +58,11 @@ static rt_err_t _pipe_check(struct uhintf* intf, upipe_t pipe) if(pipe->status == UPIPE_STATUS_STALL) { /* clear the pipe stall status */ - ret = rt_usbh_clear_feature(device, pipe->ep.bEndpointAddress, + ret = rt_usbh_clear_feature(device, pipe->ep.bEndpointAddress, USB_FEATURE_ENDPOINT_HALT); if(ret != RT_EOK) return ret; } - + rt_thread_delay(50); @@ -73,14 +73,14 @@ static rt_err_t _pipe_check(struct uhintf* intf, upipe_t pipe) RT_DEBUG_LOG(RT_DEBUG_USB, ("clean storage in pipe stall\n")); /* it should receive csw after clear the stall feature */ - size = rt_usb_hcd_pipe_xfer(stor->pipe_in->inst->hcd, + size = rt_usb_hcd_pipe_xfer(stor->pipe_in->inst->hcd, stor->pipe_in, &csw, SIZEOF_CSW, 100); - if(size != SIZEOF_CSW) + if(size != SIZEOF_CSW) { rt_kprintf("receive the csw after stall failed\n"); return -RT_EIO; } - + return -RT_ERROR; } @@ -89,35 +89,35 @@ static rt_err_t _pipe_check(struct uhintf* intf, upipe_t pipe) * * @param intf the interface instance. * @param max_lun the buffer to save max_lun. - * + * * @return the error code, RT_EOK on successfully. */ -static rt_err_t rt_usb_bulk_only_xfer(struct uhintf* intf, +static rt_err_t rt_usb_bulk_only_xfer(struct uhintf* intf, ustorage_cbw_t cmd, rt_uint8_t* buffer, int timeout) { rt_size_t size; - rt_err_t ret; + rt_err_t ret; upipe_t pipe; struct ustorage_csw csw; ustor_t stor; - RT_ASSERT(cmd != RT_NULL); + RT_ASSERT(cmd != RT_NULL); if(intf == RT_NULL) { rt_kprintf("the interface is not available\n"); return -RT_EIO; } - - /* get storage instance from the interface instance */ + + /* get storage instance from the interface instance */ stor = (ustor_t)intf->user_data; do { /* send the cbw */ - size = rt_usb_hcd_pipe_xfer(stor->pipe_out->inst->hcd, stor->pipe_out, + size = rt_usb_hcd_pipe_xfer(stor->pipe_out->inst->hcd, stor->pipe_out, cmd, SIZEOF_CBW, timeout); - if(size != SIZEOF_CBW) + if(size != SIZEOF_CBW) { rt_kprintf("CBW size error\n"); return -RT_EIO; @@ -126,20 +126,20 @@ static rt_err_t rt_usb_bulk_only_xfer(struct uhintf* intf, { pipe = (cmd->dflags == CBWFLAGS_DIR_IN) ? stor->pipe_in : stor->pipe_out; - size = rt_usb_hcd_pipe_xfer(pipe->inst->hcd, pipe, (void*)buffer, + size = rt_usb_hcd_pipe_xfer(pipe->inst->hcd, pipe, (void*)buffer, cmd->xfer_len, timeout); if(size != cmd->xfer_len) { - rt_kprintf("request size %d, transfer size %d\n", + rt_kprintf("request size %d, transfer size %d\n", cmd->xfer_len, size); break; - } + } } - + /* receive the csw */ - size = rt_usb_hcd_pipe_xfer(stor->pipe_in->inst->hcd, stor->pipe_in, + size = rt_usb_hcd_pipe_xfer(stor->pipe_in->inst->hcd, stor->pipe_in, &csw, SIZEOF_CSW, timeout); - if(size != SIZEOF_CSW) + if(size != SIZEOF_CSW) { rt_kprintf("csw size error\n"); return -RT_EIO; @@ -148,12 +148,12 @@ static rt_err_t rt_usb_bulk_only_xfer(struct uhintf* intf, /* check in pipes status */ ret = _pipe_check(intf, stor->pipe_in); - if(ret != RT_EOK) + if(ret != RT_EOK) { rt_kprintf("in pipe error\n"); return ret; } - + /* check out pipes status */ ret = _pipe_check(intf, stor->pipe_out); if(ret != RT_EOK) @@ -161,20 +161,20 @@ static rt_err_t rt_usb_bulk_only_xfer(struct uhintf* intf, rt_kprintf("out pipe error\n"); return ret; } - + /* check csw status */ if(csw.signature != CSW_SIGNATURE || csw.tag != CBW_TAG_VALUE) { rt_kprintf("csw signature error\n"); return -RT_EIO; } - + if(csw.status != 0) { //rt_kprintf("csw status error:%d\n",csw.status); return -RT_ERROR; } - + return RT_EOK; } @@ -183,12 +183,12 @@ static rt_err_t rt_usb_bulk_only_xfer(struct uhintf* intf, * * @param intf the interface instance. * @param max_lun the buffer to save max_lun. - * + * * @return the error code, RT_EOK on successfully. */ rt_err_t rt_usbh_storage_get_max_lun(struct uhintf* intf, rt_uint8_t* max_lun) { - struct uinstance* device; + struct uinstance* device; struct urequest setup; int timeout = USB_TIMEOUT_BASIC; @@ -196,17 +196,17 @@ rt_err_t rt_usbh_storage_get_max_lun(struct uhintf* intf, rt_uint8_t* max_lun) { rt_kprintf("the interface is not available\n"); return -RT_EIO; - } + } /* parameter check */ RT_ASSERT(intf->device != RT_NULL); RT_DEBUG_LOG(RT_DEBUG_USB, ("rt_usbh_storage_get_max_lun\n")); - /* get usb device instance from the interface instance */ - device = intf->device; + /* get usb device instance from the interface instance */ + device = intf->device; /* construct the request */ - setup.request_type = USB_REQ_TYPE_DIR_IN | USB_REQ_TYPE_CLASS | + setup.request_type = USB_REQ_TYPE_DIR_IN | USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE; setup.bRequest = USBREQ_GET_MAX_LUN; setup.wValue = intf->intf_desc->bInterfaceNumber; @@ -233,13 +233,13 @@ rt_err_t rt_usbh_storage_get_max_lun(struct uhintf* intf, rt_uint8_t* max_lun) * This function will do USBREQ_MASS_STORAGE_RESET request for the usb interface instance. * * @param intf the interface instance. - * + * * @return the error code, RT_EOK on successfully. */ rt_err_t rt_usbh_storage_reset(struct uhintf* intf) { struct urequest setup; - struct uinstance* device; + struct uinstance* device; int timeout = USB_TIMEOUT_BASIC; /* parameter check */ @@ -247,16 +247,16 @@ rt_err_t rt_usbh_storage_reset(struct uhintf* intf) { rt_kprintf("the interface is not available\n"); return -RT_EIO; - } + } RT_ASSERT(intf->device != RT_NULL); RT_DEBUG_LOG(RT_DEBUG_USB, ("rt_usbh_storage_reset\n")); - /* get usb device instance from the interface instance */ - device = intf->device; + /* get usb device instance from the interface instance */ + device = intf->device; /* construct the request */ - setup.request_type = USB_REQ_TYPE_DIR_OUT | USB_REQ_TYPE_CLASS | + setup.request_type = USB_REQ_TYPE_DIR_OUT | USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE; setup.bRequest = USBREQ_MASS_STORAGE_RESET; setup.wIndex = intf->intf_desc->bInterfaceNumber; @@ -279,12 +279,12 @@ rt_err_t rt_usbh_storage_reset(struct uhintf* intf) * * @param intf the interface instance. * @param buffer the data buffer to save read data - * @param sector the start sector address to read. + * @param sector the start sector address to read. * @param sector the sector count to read. - * + * * @return the error code, RT_EOK on successfully. */ -rt_err_t rt_usbh_storage_read10(struct uhintf* intf, rt_uint8_t *buffer, +rt_err_t rt_usbh_storage_read10(struct uhintf* intf, rt_uint8_t *buffer, rt_uint32_t sector, rt_size_t count, int timeout) { struct ustorage_cbw cmd; @@ -294,8 +294,8 @@ rt_err_t rt_usbh_storage_read10(struct uhintf* intf, rt_uint8_t *buffer, { rt_kprintf("interface is not available\n"); return -RT_EIO; - } - + } + RT_ASSERT(intf->device != RT_NULL); RT_DEBUG_LOG(RT_DEBUG_USB, ("rt_usbh_storage_read10\n")); @@ -325,12 +325,12 @@ rt_err_t rt_usbh_storage_read10(struct uhintf* intf, rt_uint8_t *buffer, * * @param intf the interface instance. * @param buffer the data buffer to save write data - * @param sector the start sector address to write. + * @param sector the start sector address to write. * @param sector the sector count to write. - * + * * @return the error code, RT_EOK on successfully. */ -rt_err_t rt_usbh_storage_write10(struct uhintf* intf, rt_uint8_t *buffer, +rt_err_t rt_usbh_storage_write10(struct uhintf* intf, rt_uint8_t *buffer, rt_uint32_t sector, rt_size_t count, int timeout) { struct ustorage_cbw cmd; @@ -340,8 +340,8 @@ rt_err_t rt_usbh_storage_write10(struct uhintf* intf, rt_uint8_t *buffer, { rt_kprintf("the interface is not available\n"); return -RT_EIO; - } - + } + RT_ASSERT(intf->device != RT_NULL); RT_DEBUG_LOG(RT_DEBUG_USB, ("rt_usbh_storage_write10\n")); @@ -371,7 +371,7 @@ rt_err_t rt_usbh_storage_write10(struct uhintf* intf, rt_uint8_t *buffer, * * @param intf the interface instance. * @param buffer the data buffer to save sense data - * + * * @return the error code, RT_EOK on successfully. */ rt_err_t rt_usbh_storage_request_sense(struct uhintf* intf, rt_uint8_t* buffer) @@ -384,12 +384,12 @@ rt_err_t rt_usbh_storage_request_sense(struct uhintf* intf, rt_uint8_t* buffer) { rt_kprintf("the interface is not available\n"); return -RT_EIO; - } - + } + RT_ASSERT(intf->device != RT_NULL); RT_DEBUG_LOG(RT_DEBUG_USB, ("rt_usbh_storage_request_sense\n")); - /* construct the command block wrapper */ + /* construct the command block wrapper */ rt_memset(&cmd, 0, sizeof(struct ustorage_cbw)); cmd.signature = CBW_SIGNATURE; cmd.tag = CBW_TAG_VALUE; @@ -407,7 +407,7 @@ rt_err_t rt_usbh_storage_request_sense(struct uhintf* intf, rt_uint8_t* buffer) * This function will execute SCSI_TEST_UNIT_READY command to get unit ready status. * * @param intf the interface instance. - * + * * @return the error code, RT_EOK on successfully. */ rt_err_t rt_usbh_storage_test_unit_ready(struct uhintf* intf) @@ -420,8 +420,8 @@ rt_err_t rt_usbh_storage_test_unit_ready(struct uhintf* intf) { rt_kprintf("the interface is not available\n"); return -RT_EIO; - } - + } + RT_ASSERT(intf->device != RT_NULL); RT_DEBUG_LOG(RT_DEBUG_USB, ("rt_usbh_storage_test_unit_ready\n")); @@ -434,7 +434,7 @@ rt_err_t rt_usbh_storage_test_unit_ready(struct uhintf* intf) cmd.lun = 0; cmd.cb_len = 12; cmd.cb[0] = SCSI_TEST_UNIT_READY; - + return rt_usb_bulk_only_xfer(intf, &cmd, RT_NULL, timeout); } @@ -443,21 +443,21 @@ rt_err_t rt_usbh_storage_test_unit_ready(struct uhintf* intf) * * @param intf the interface instance. * @param buffer the data buffer to save inquiry data - * + * * @return the error code, RT_EOK on successfully. */ rt_err_t rt_usbh_storage_inquiry(struct uhintf* intf, rt_uint8_t* buffer) { struct ustorage_cbw cmd; int timeout = USB_TIMEOUT_LONG; - + /* parameter check */ if(intf == RT_NULL) { rt_kprintf("the interface is not available\n"); return -RT_EIO; - } - + } + RT_ASSERT(intf->device != RT_NULL); RT_DEBUG_LOG(RT_DEBUG_USB, ("rt_usbh_storage_inquiry\n")); @@ -480,7 +480,7 @@ rt_err_t rt_usbh_storage_inquiry(struct uhintf* intf, rt_uint8_t* buffer) * * @param intf the interface instance. * @param buffer the data buffer to save capacity data - * + * * @return the error code, RT_EOK on successfully. */ rt_err_t rt_usbh_storage_get_capacity(struct uhintf* intf, rt_uint8_t* buffer) @@ -493,7 +493,7 @@ rt_err_t rt_usbh_storage_get_capacity(struct uhintf* intf, rt_uint8_t* buffer) { rt_kprintf("the interface is not available\n"); return -RT_EIO; - } + } RT_ASSERT(intf->device != RT_NULL); RT_DEBUG_LOG(RT_DEBUG_USB, ("rt_usbh_storage_get_capacity\n")); @@ -513,17 +513,17 @@ rt_err_t rt_usbh_storage_get_capacity(struct uhintf* intf, rt_uint8_t* buffer) /** * This function will run mass storage class driver when usb device is detected - * and identified as a mass storage class device, it will continue to do the enumulate + * and identified as a mass storage class device, it will continue to do the enumulate * process. * * @param arg the argument. - * + * * @return the error code, RT_EOK on successfully. */ static rt_err_t rt_usbh_storage_enable(void* arg) { int i = 0; - rt_err_t ret; + rt_err_t ret; ustor_t stor; struct uhintf* intf = (struct uhintf*)arg; @@ -534,25 +534,25 @@ static rt_err_t rt_usbh_storage_enable(void* arg) return -RT_EIO; } - RT_DEBUG_LOG(RT_DEBUG_USB, ("subclass %d, protocal %d\n", + RT_DEBUG_LOG(RT_DEBUG_USB, ("subclass %d, protocal %d\n", intf->intf_desc->bInterfaceSubClass, intf->intf_desc->bInterfaceProtocol)); - + RT_DEBUG_LOG(RT_DEBUG_USB, ("rt_usbh_storage_run\n")); /* only support SCSI subclass and bulk only protocal */ - + stor = rt_malloc(sizeof(struct ustor)); RT_ASSERT(stor != RT_NULL); /* initilize the data structure */ - rt_memset(stor, 0, sizeof(struct ustor)); + rt_memset(stor, 0, sizeof(struct ustor)); intf->user_data = (void*)stor; for(i=0; iintf_desc->bNumEndpoints; i++) - { + { uep_desc_t ep_desc; - + /* get endpoint descriptor from interface descriptor */ rt_usbh_get_endpoint_descriptor(intf->intf_desc, i, &ep_desc); if(ep_desc == RT_NULL) @@ -560,11 +560,11 @@ static rt_err_t rt_usbh_storage_enable(void* arg) rt_kprintf("rt_usb_get_endpoint_descriptor error\n"); return -RT_ERROR; } - - /* the endpoint type of mass storage class should be BULK */ + + /* the endpoint type of mass storage class should be BULK */ if((ep_desc->bmAttributes & USB_EP_ATTR_TYPE_MASK) != USB_EP_ATTR_BULK) continue; - + /* allocate pipes according to the endpoint type */ if(ep_desc->bEndpointAddress & USB_DIR_IN) { @@ -572,7 +572,7 @@ static rt_err_t rt_usbh_storage_enable(void* arg) stor->pipe_in = rt_usb_instance_find_pipe(intf->device,ep_desc->bEndpointAddress); } else - { + { /* alloc an output pipe for the storage instance */ stor->pipe_out = rt_usb_instance_find_pipe(intf->device,ep_desc->bEndpointAddress); } @@ -583,8 +583,8 @@ static rt_err_t rt_usbh_storage_enable(void* arg) { rt_kprintf("pipe error, unsupported device\n"); return -RT_ERROR; - } - + } + /* should implement as callback */ ret = rt_udisk_run(intf); if(ret != RT_EOK) return ret; @@ -593,11 +593,11 @@ static rt_err_t rt_usbh_storage_enable(void* arg) } /** - * This function will be invoked when usb device plug out is detected and it would clean + * This function will be invoked when usb device plug out is detected and it would clean * and release all mass storage class related resources. * * @param arg the argument. - * + * * @return the error code, RT_EOK on successfully. */ static rt_err_t rt_usbh_storage_disable(void* arg) @@ -617,7 +617,7 @@ static rt_err_t rt_usbh_storage_disable(void* arg) rt_udisk_stop(intf); - + /* free storage instance */ if(stor != RT_NULL) rt_free(stor); return RT_EOK; @@ -626,13 +626,13 @@ static rt_err_t rt_usbh_storage_disable(void* arg) /** * This function will register mass storage class driver to the usb class driver manager. * and it should be invoked in the usb system initialization. - * + * * @return the error code, RT_EOK on successfully. */ ucd_t rt_usbh_class_driver_storage(void) { storage_driver.class_code = USB_CLASS_MASS_STORAGE; - + storage_driver.enable = rt_usbh_storage_enable; storage_driver.disable = rt_usbh_storage_disable; diff --git a/components/drivers/usb/usbhost/class/mass.h b/components/drivers/usb/usbhost/class/mass.h index 770e64a03f..2578fb54c7 100644 --- a/components/drivers/usb/usbhost/class/mass.h +++ b/components/drivers/usb/usbhost/class/mass.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -30,17 +30,17 @@ struct ustor upipe_t pipe_in; upipe_t pipe_out; rt_uint32_t capicity[2]; - + struct rt_device dev[MAX_PARTITION_COUNT]; rt_uint8_t dev_cnt; -}; +}; typedef struct ustor* ustor_t; rt_err_t rt_usbh_storage_get_max_lun(struct uhintf* intf, rt_uint8_t* max_lun); rt_err_t rt_usbh_storage_reset(struct uhintf* intf); -rt_err_t rt_usbh_storage_read10(struct uhintf* intf, rt_uint8_t *buffer, +rt_err_t rt_usbh_storage_read10(struct uhintf* intf, rt_uint8_t *buffer, rt_uint32_t sector, rt_size_t count, int timeout); -rt_err_t rt_usbh_storage_write10(struct uhintf* intf, rt_uint8_t *buffer, +rt_err_t rt_usbh_storage_write10(struct uhintf* intf, rt_uint8_t *buffer, rt_uint32_t sector, rt_size_t count, int timeout); rt_err_t rt_usbh_storage_request_sense(struct uhintf* intf, rt_uint8_t* buffer); rt_err_t rt_usbh_storage_test_unit_ready(struct uhintf* intf); diff --git a/components/drivers/usb/usbhost/class/udisk.c b/components/drivers/usb/usbhost/class/udisk.c index 6c8030b29a..8be311e657 100644 --- a/components/drivers/usb/usbhost/class/udisk.c +++ b/components/drivers/usb/usbhost/class/udisk.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/usb/usbhost/class/ukbd.c b/components/drivers/usb/usbhost/class/ukbd.c index 7d608de259..c89d60cd36 100644 --- a/components/drivers/usb/usbhost/class/ukbd.c +++ b/components/drivers/usb/usbhost/class/ukbd.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,13 +14,13 @@ #if defined(RT_USBH_HID) && defined(RT_USBH_HID_KEYBOARD) -static struct uprotocal kbd_protocal; +static struct uprotocal kbd_protocal; static rt_err_t rt_usbh_hid_kbd_callback(void* arg) { int int1, int2; - struct uhid* hid; - + struct uhid* hid; + hid = (struct uhid*)arg; int1 = *(rt_uint32_t*)hid->buffer; @@ -28,9 +28,9 @@ static rt_err_t rt_usbh_hid_kbd_callback(void* arg) if(int1 != 0 || int2 != 0) { - RT_DEBUG_LOG(RT_DEBUG_USB, ("key down 0x%x, 0x%x\n", int1, int2)); + RT_DEBUG_LOG(RT_DEBUG_USB, ("key down 0x%x, 0x%x\n", int1, int2)); } - + return RT_EOK; } @@ -38,20 +38,20 @@ static rt_err_t rt_usbh_hid_kbd_init(void* arg) { struct uintf* intf = (struct uintf*)arg; - RT_ASSERT(intf != RT_NULL); - + RT_ASSERT(intf != RT_NULL); + rt_usbh_hid_set_protocal(intf, 0); rt_usbh_hid_set_idle(intf, 10, 0); - //RT_DEBUG_LOG(RT_DEBUG_USB, ("start usb keyboard\n")); + //RT_DEBUG_LOG(RT_DEBUG_USB, ("start usb keyboard\n")); return RT_EOK; } /** * This function will define the hid keyboard protocal, it will be register to the protocal list. - * + * * @return the keyboard protocal structure. */ uprotocal_t rt_usbh_hid_protocal_kbd(void) diff --git a/components/drivers/usb/usbhost/class/umouse.c b/components/drivers/usb/usbhost/class/umouse.c index e769475a98..94fca210bb 100644 --- a/components/drivers/usb/usbhost/class/umouse.c +++ b/components/drivers/usb/usbhost/class/umouse.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/usb/usbhost/core/driver.c b/components/drivers/usb/usbhost/core/driver.c index 37327108c1..6dad1409a0 100644 --- a/components/drivers/usb/usbhost/core/driver.c +++ b/components/drivers/usb/usbhost/core/driver.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,21 +17,21 @@ static rt_list_t _driver_list; /** * This function will initilize the usb class driver related data structure, * and it should be invoked in the usb system initialization. - * + * * @return the error code, RT_EOK on successfully. */ rt_err_t rt_usbh_class_driver_init(void) { rt_list_init(&_driver_list); - return RT_EOK; + return RT_EOK; } /** * This function will register an usb class driver to the class driver manager. * * @param drv the pointer of the usb class driver. - * + * * @return the error code, RT_EOK on successfully. */ @@ -41,15 +41,15 @@ rt_err_t rt_usbh_class_driver_register(ucd_t drv) /* insert class driver into driver list */ rt_list_insert_after(&_driver_list, &(drv->list)); - - return RT_EOK; + + return RT_EOK; } /** * This function will removes a previously registed usb class driver. * * @param drv the pointer of the usb class driver structure. - * + * * @return the error code, RT_EOK on successfully. */ rt_err_t rt_usbh_class_driver_unregister(ucd_t drv) @@ -67,7 +67,7 @@ rt_err_t rt_usbh_class_driver_unregister(ucd_t drv) * * @param drv the pointer of usb class driver. * @param args the parameter of run function. - * + * * @return the error code, RT_EOK on successfully. */ rt_err_t rt_usbh_class_driver_enable(ucd_t drv, void* args) @@ -85,7 +85,7 @@ rt_err_t rt_usbh_class_driver_enable(ucd_t drv, void* args) * * @param drv the pointer of usb class driver structure. * @param args the argument of the stop function. - * + * * @return the error code, RT_EOK on successfully. */ rt_err_t rt_usbh_class_driver_disable(ucd_t drv, void* args) @@ -102,7 +102,7 @@ rt_err_t rt_usbh_class_driver_disable(ucd_t drv, void* args) /** * This function finds a usb class driver by specified class code and subclass code. * - * @param class_code the usb class driver's class code. + * @param class_code the usb class driver's class code. * @param subclass_code the usb class driver's sub class code. * * @return the registered usb class driver on successful, or RT_NULL on failure. @@ -118,7 +118,7 @@ ucd_t rt_usbh_class_driver_find(int class_code, int subclass_code) /* try to find driver object */ for (node = _driver_list.next; node != &_driver_list; node = node->next) { - ucd_t drv = + ucd_t drv = (ucd_t)rt_list_entry(node, struct uclass_driver, list); if (drv->class_code == class_code) { diff --git a/components/drivers/usb/usbhost/core/hub.c b/components/drivers/usb/usbhost/core/hub.c index eefa571472..b6381ec300 100644 --- a/components/drivers/usb/usbhost/core/hub.c +++ b/components/drivers/usb/usbhost/core/hub.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -77,7 +77,7 @@ static rt_err_t root_hub_ctrl(struct uhcd *hcd, rt_uint16_t port, rt_uint8_t cmd return RT_ERROR; } return RT_EOK; -} +} void rt_usbh_root_hub_connect_handler(struct uhcd *hcd, rt_uint8_t port, rt_bool_t isHS) { struct uhost_msg msg; @@ -106,23 +106,23 @@ void rt_usbh_root_hub_disconnect_handler(struct uhcd *hcd, rt_uint8_t port) } /** - * This function will do USB_REQ_GET_DESCRIPTOR bRequest for the device instance + * This function will do USB_REQ_GET_DESCRIPTOR bRequest for the device instance * to get usb hub descriptor. * * @param intf the interface instance. * @buffer the data buffer to save usb hub descriptor. * @param nbytes the size of buffer - * + * * @return the error code, RT_EOK on successfully. */ rt_err_t rt_usbh_hub_get_descriptor(struct uinstance* device, rt_uint8_t *buffer, rt_size_t nbytes) { struct urequest setup; int timeout = USB_TIMEOUT_BASIC; - + /* parameter check */ RT_ASSERT(device != RT_NULL); - + setup.request_type = USB_REQ_TYPE_DIR_IN | USB_REQ_TYPE_CLASS | USB_REQ_TYPE_DEVICE; setup.bRequest = USB_REQ_GET_DESCRIPTOR; setup.wIndex = 0; @@ -135,24 +135,24 @@ rt_err_t rt_usbh_hub_get_descriptor(struct uinstance* device, rt_uint8_t *buffer { return RT_EOK; } - } - return -RT_FALSE; + } + return -RT_FALSE; } /** - * This function will do USB_REQ_GET_STATUS bRequest for the device instance + * This function will do USB_REQ_GET_STATUS bRequest for the device instance * to get usb hub status. * * @param intf the interface instance. * @buffer the data buffer to save usb hub status. - * + * * @return the error code, RT_EOK on successfully. */ rt_err_t rt_usbh_hub_get_status(struct uinstance* device, rt_uint32_t* buffer) { struct urequest setup; int timeout = USB_TIMEOUT_BASIC; - + /* parameter check */ RT_ASSERT(device != RT_NULL); @@ -168,31 +168,31 @@ rt_err_t rt_usbh_hub_get_status(struct uinstance* device, rt_uint32_t* buffer) return RT_EOK; } } - return -RT_FALSE; + return -RT_FALSE; } /** - * This function will do USB_REQ_GET_STATUS bRequest for the device instance + * This function will do USB_REQ_GET_STATUS bRequest for the device instance * to get hub port status. * * @param intf the interface instance. * @port the hub port to get status. * @buffer the data buffer to save usb hub status. - * + * * @return the error code, RT_EOK on successfully. */ rt_err_t rt_usbh_hub_get_port_status(uhub_t hub, rt_uint16_t port, rt_uint32_t* buffer) { struct urequest setup; int timeout = USB_TIMEOUT_BASIC; - + /* parameter check */ RT_ASSERT(hub != RT_NULL); /* get roothub port status */ if(hub->is_roothub) { - root_hub_ctrl(hub->hcd, port, RH_GET_PORT_STATUS, + root_hub_ctrl(hub->hcd, port, RH_GET_PORT_STATUS, (void*)buffer); return RT_EOK; } @@ -210,36 +210,36 @@ rt_err_t rt_usbh_hub_get_port_status(uhub_t hub, rt_uint16_t port, rt_uint32_t* return RT_EOK; } } - return -RT_FALSE; + return -RT_FALSE; } /** - * This function will do USB_REQ_CLEAR_FEATURE bRequest for the device instance + * This function will do USB_REQ_CLEAR_FEATURE bRequest for the device instance * to clear feature of the hub port. * * @param intf the interface instance. * @port the hub port. * @feature feature to be cleared. - * + * * @return the error code, RT_EOK on successfully. */ rt_err_t rt_usbh_hub_clear_port_feature(uhub_t hub, rt_uint16_t port, rt_uint16_t feature) { struct urequest setup; int timeout = USB_TIMEOUT_BASIC; - + /* parameter check */ RT_ASSERT(hub != RT_NULL); /* clear roothub feature */ if(hub->is_roothub) { - root_hub_ctrl(hub->hcd, port, RH_CLEAR_PORT_FEATURE, + root_hub_ctrl(hub->hcd, port, RH_CLEAR_PORT_FEATURE, (void*)(rt_uint32_t)feature); return RT_EOK; } - setup.request_type = USB_REQ_TYPE_DIR_OUT | USB_REQ_TYPE_CLASS | + setup.request_type = USB_REQ_TYPE_DIR_OUT | USB_REQ_TYPE_CLASS | USB_REQ_TYPE_OTHER; setup.bRequest = USB_REQ_CLEAR_FEATURE; setup.wIndex = port; @@ -250,37 +250,37 @@ rt_err_t rt_usbh_hub_clear_port_feature(uhub_t hub, rt_uint16_t port, rt_uint16_ { return RT_EOK; } - return -RT_FALSE; + return -RT_FALSE; } /** - * This function will do USB_REQ_SET_FEATURE bRequest for the device instance + * This function will do USB_REQ_SET_FEATURE bRequest for the device instance * to set feature of the hub port. * * @param intf the interface instance. * @port the hub port. * @feature feature to be set. - * + * * @return the error code, RT_EOK on successfully. */ -rt_err_t rt_usbh_hub_set_port_feature(uhub_t hub, rt_uint16_t port, +rt_err_t rt_usbh_hub_set_port_feature(uhub_t hub, rt_uint16_t port, rt_uint16_t feature) { struct urequest setup; int timeout = USB_TIMEOUT_BASIC; - + /* parameter check */ RT_ASSERT(hub != RT_NULL); /* clear roothub feature */ if(hub->is_roothub) { - root_hub_ctrl(hub->hcd, port, RH_SET_PORT_FEATURE, + root_hub_ctrl(hub->hcd, port, RH_SET_PORT_FEATURE, (void*)(rt_uint32_t)feature); return RT_EOK; } - setup.request_type = USB_REQ_TYPE_DIR_OUT | USB_REQ_TYPE_CLASS | + setup.request_type = USB_REQ_TYPE_DIR_OUT | USB_REQ_TYPE_CLASS | USB_REQ_TYPE_OTHER; setup.bRequest = USB_REQ_SET_FEATURE; setup.wIndex = port; @@ -291,7 +291,7 @@ rt_err_t rt_usbh_hub_set_port_feature(uhub_t hub, rt_uint16_t port, { return RT_EOK; } - else return -RT_FALSE; + else return -RT_FALSE; } /** @@ -299,17 +299,17 @@ rt_err_t rt_usbh_hub_set_port_feature(uhub_t hub, rt_uint16_t port, * * @param intf the interface instance. * @param port the hub port. - * + * * @return the error code, RT_EOK on successfully. */ rt_err_t rt_usbh_hub_reset_port(uhub_t hub, rt_uint16_t port) { rt_err_t ret; rt_uint32_t pstatus; - + /* parameter check */ RT_ASSERT(hub != RT_NULL); - + rt_thread_delay(50); /* reset hub port */ @@ -321,12 +321,12 @@ rt_err_t rt_usbh_hub_reset_port(uhub_t hub, rt_uint16_t port) ret = rt_usbh_hub_get_port_status(hub, port, &pstatus); if(!(pstatus & PORT_PRS)) break; } - + /* clear port reset feature */ - ret = rt_usbh_hub_clear_port_feature(hub, port, PORT_FEAT_C_RESET); + ret = rt_usbh_hub_clear_port_feature(hub, port, PORT_FEAT_C_RESET); if(ret != RT_EOK) return ret; - rt_thread_delay(50); + rt_thread_delay(50); return RT_EOK; } @@ -336,7 +336,7 @@ rt_err_t rt_usbh_hub_reset_port(uhub_t hub, rt_uint16_t port) * * @param device the usb instance. * @param port the hub port. - * + * * @return the error code, RT_EOK on successfully. */ rt_err_t rt_usbh_hub_port_debounce(uhub_t hub, rt_uint16_t port) @@ -356,15 +356,15 @@ rt_err_t rt_usbh_hub_port_debounce(uhub_t hub, rt_uint16_t port) { ret = rt_usbh_hub_get_port_status(hub, port, &pstatus); if(ret != RT_EOK) return ret; - - if(!(pstatus & PORT_CCS)) + + if(!(pstatus & PORT_CCS)) { connect = RT_FALSE; break; } - + rt_thread_delay(delayticks); - } + } if(connect) return RT_EOK; else return -RT_ERROR; @@ -375,7 +375,7 @@ rt_err_t rt_usbh_hub_port_debounce(uhub_t hub, rt_uint16_t port) * disconnect events. * * @param intf the interface instance. - * + * * @return the error code, RT_EOK on successfully. */ static rt_err_t rt_usbh_hub_port_change(uhub_t hub) @@ -386,7 +386,7 @@ static rt_err_t rt_usbh_hub_port_change(uhub_t hub) /* parameter check */ RT_ASSERT(hub != RT_NULL); - /* get usb device instance */ + /* get usb device instance */ for (i = 0; i < hub->num_ports; i++) { rt_err_t ret; @@ -394,7 +394,7 @@ static rt_err_t rt_usbh_hub_port_change(uhub_t hub) rt_uint32_t pstatus = 0; reconnect = RT_FALSE; - + /* get hub port status */ ret = rt_usbh_hub_get_port_status(hub, i + 1, &pstatus); if(ret != RT_EOK) continue; @@ -402,8 +402,8 @@ static rt_err_t rt_usbh_hub_port_change(uhub_t hub) RT_DEBUG_LOG(RT_DEBUG_USB, ("port %d status 0x%x\n", i + 1, pstatus)); /* check port status change */ - if (pstatus & PORT_CCSC) - { + if (pstatus & PORT_CCSC) + { /* clear port status change feature */ rt_usbh_hub_clear_port_feature(hub, i + 1, PORT_FEAT_C_CONNECTION); reconnect = RT_TRUE; @@ -411,39 +411,39 @@ static rt_err_t rt_usbh_hub_port_change(uhub_t hub) if(pstatus & PORT_PESC) { - rt_usbh_hub_clear_port_feature(hub, i + 1, PORT_FEAT_C_ENABLE); + rt_usbh_hub_clear_port_feature(hub, i + 1, PORT_FEAT_C_ENABLE); reconnect = RT_TRUE; } - + if(reconnect) - { + { if(hub->child[i] != RT_NULL && hub->child[i]->status != DEV_STATUS_IDLE) - { + { rt_usbh_detach_instance(hub->child[i]); /* Child device have been detach. Set hub->child[i] to NULL. */ hub->child[i] = RT_NULL; } - + ret = rt_usbh_hub_port_debounce(hub, i + 1); if(ret != RT_EOK) continue; - + /* allocate an usb instance for new connected device */ device = rt_usbh_alloc_instance(hub->hcd); if(device == RT_NULL) break; - + /* set usb device speed */ device->speed = (pstatus & PORT_LSDA) ? 1 : 0; - device->parent_hub = hub; + device->parent_hub = hub; device->hcd = hub->hcd; device->port = i + 1; hub->child[i] = device; /* reset usb roothub port */ rt_usbh_hub_reset_port(hub, i + 1); - + /* attatch the usb instance to the hcd */ - rt_usbh_attatch_instance(device); + rt_usbh_attatch_instance(device); } } @@ -454,7 +454,7 @@ static rt_err_t rt_usbh_hub_port_change(uhub_t hub) * This function is the callback function of hub's int endpoint, it is invoked when data comes. * * @param context the context of the callback function. - * + * * @return none. */ static void rt_usbh_hub_irq(void* context) @@ -462,9 +462,9 @@ static void rt_usbh_hub_irq(void* context) upipe_t pipe; uhub_t hub; int timeout = USB_TIMEOUT_BASIC; - + RT_ASSERT(context != RT_NULL); - + pipe = (upipe_t)context; hub = (uhub_t)pipe->user_data; @@ -473,14 +473,14 @@ static void rt_usbh_hub_irq(void* context) RT_DEBUG_LOG(RT_DEBUG_USB,("hub irq error\n")); return; } - + rt_usbh_hub_port_change(hub); RT_DEBUG_LOG(RT_DEBUG_USB,("hub int xfer...\n")); /* parameter check */ RT_ASSERT(pipe->inst->hcd != RT_NULL); - + rt_usb_hcd_pipe_xfer(hub->self->hcd, pipe, hub->buffer, pipe->ep.wMaxPacketSize, timeout); } @@ -489,7 +489,7 @@ static void rt_usbh_hub_irq(void* context) * as a hub class device, it will continue to do the enumulate process. * * @param arg the argument. - * + * * @return the error code, RT_EOK on successfully. */ @@ -505,7 +505,7 @@ static rt_err_t rt_usbh_hub_enable(void *arg) int timeout = USB_TIMEOUT_LONG; /* paremeter check */ RT_ASSERT(intf != RT_NULL); - + RT_DEBUG_LOG(RT_DEBUG_USB, ("rt_usbh_hub_run\n")); /* get usb device instance */ @@ -515,7 +515,7 @@ static rt_err_t rt_usbh_hub_enable(void *arg) hub = rt_malloc(sizeof(struct uhub)); RT_ASSERT(hub != RT_NULL); rt_memset(hub, 0, sizeof(struct uhub)); - + /* make interface instance's user data point to hub instance */ intf->user_data = (void*)hub; @@ -524,17 +524,17 @@ static rt_err_t rt_usbh_hub_enable(void *arg) if(ret != RT_EOK) { rt_kprintf("get hub descriptor failed\n"); - return -RT_ERROR; + return -RT_ERROR; } /* get full hub descriptor */ - ret = rt_usbh_hub_get_descriptor(device, (rt_uint8_t*)&hub->hub_desc, + ret = rt_usbh_hub_get_descriptor(device, (rt_uint8_t*)&hub->hub_desc, hub->hub_desc.length); if(ret != RT_EOK) { rt_kprintf("get hub descriptor again failed\n"); - return -RT_ERROR; - } + return -RT_ERROR; + } /* get hub ports number */ /* If hub device supported ports over USB_HUB_PORT_NUM(Ex: 8 port hub). Set hub->num_ports to USB_HUB_PORT_NUM */ @@ -554,7 +554,7 @@ static rt_err_t rt_usbh_hub_enable(void *arg) * 2 * RT_TICK_PER_SECOND / 1000 ); } - if(intf->intf_desc->bNumEndpoints != 1) + if(intf->intf_desc->bNumEndpoints != 1) return -RT_ERROR; /* get endpoint descriptor from interface descriptor */ @@ -565,12 +565,12 @@ static rt_err_t rt_usbh_hub_enable(void *arg) return -RT_ERROR; } - /* the endpoint type of hub class should be interrupt */ + /* the endpoint type of hub class should be interrupt */ if( USB_EP_ATTR(ep_desc->bmAttributes) == USB_EP_ATTR_INT) { /* the endpoint direction of hub class should be in */ if(ep_desc->bEndpointAddress & USB_DIR_IN) - { + { /* allocate a pipe according to the endpoint type */ pipe_in = rt_usb_instance_find_pipe(device,ep_desc->bEndpointAddress); if(pipe_in == RT_NULL) @@ -585,17 +585,17 @@ static rt_err_t rt_usbh_hub_enable(void *arg) /* parameter check */ RT_ASSERT(device->hcd != RT_NULL); pipe_in->user_data = hub; - rt_usb_hcd_pipe_xfer(hub->hcd, pipe_in, hub->buffer, + rt_usb_hcd_pipe_xfer(hub->hcd, pipe_in, hub->buffer, pipe_in->ep.wMaxPacketSize, timeout); return RT_EOK; } /** - * This function will be invoked when usb hub plug out is detected and it would clean + * This function will be invoked when usb hub plug out is detected and it would clean * and release all hub class related resources. * * @param arg the argument. - * + * * @return the error code, RT_EOK on successfully. */ static rt_err_t rt_usbh_hub_disable(void* arg) @@ -615,7 +615,7 @@ static rt_err_t rt_usbh_hub_disable(void* arg) if(hub->child[i] != RT_NULL) rt_usbh_detach_instance(hub->child[i]); } - + if(hub != RT_NULL) rt_free(hub); return RT_EOK; @@ -624,13 +624,13 @@ static rt_err_t rt_usbh_hub_disable(void* arg) /** * This function will register hub class driver to the usb class driver manager. * and it should be invoked in the usb system initialization. - * + * * @return the error code, RT_EOK on successfully. */ ucd_t rt_usbh_class_driver_hub(void) -{ +{ hub_driver.class_code = USB_CLASS_HUB; - + hub_driver.enable = rt_usbh_hub_enable; hub_driver.disable = rt_usbh_hub_disable; @@ -638,27 +638,27 @@ ucd_t rt_usbh_class_driver_hub(void) } /** - * This function is the main entry of usb hub thread, it is in charge of - * processing all messages received from the usb message buffer. + * This function is the main entry of usb hub thread, it is in charge of + * processing all messages received from the usb message buffer. * * @param parameter the parameter of the usb host thread. - * + * * @return none. */ static void rt_usbh_hub_thread_entry(void* parameter) -{ +{ while(1) - { + { struct uhost_msg msg; - + /* receive message */ - if(rt_mq_recv(usb_mq, &msg, sizeof(struct uhost_msg), RT_WAITING_FOREVER) + if(rt_mq_recv(usb_mq, &msg, sizeof(struct uhost_msg), RT_WAITING_FOREVER) != RT_EOK ) continue; //RT_DEBUG_LOG(RT_DEBUG_USB, ("msg type %d\n", msg.type)); - + switch (msg.type) - { + { case USB_MSG_CONNECT_CHANGE: rt_usbh_hub_port_change(msg.content.hub); break; @@ -668,7 +668,7 @@ static void rt_usbh_hub_thread_entry(void* parameter) break; default: break; - } + } } } @@ -676,8 +676,8 @@ static void rt_usbh_hub_thread_entry(void* parameter) * This function will post an message to the usb message queue, * * @param msg the message to be posted - * - * @return the error code, RT_EOK on successfully. + * + * @return the error code, RT_EOK on successfully. */ rt_err_t rt_usbh_event_signal(struct uhost_msg* msg) { @@ -693,7 +693,7 @@ rt_err_t rt_usbh_event_signal(struct uhost_msg* msg) * This function will initialize usb hub thread. * * @return none. - * + * */ void rt_usbh_hub_init(uhcd_t hcd) { @@ -705,9 +705,9 @@ void rt_usbh_hub_init(uhcd_t hcd) root_hub.num_ports = hcd->num_ports; /* create usb message queue */ usb_mq = rt_mq_create("usbh", 32, 16, RT_IPC_FLAG_FIFO); - + /* create usb hub thread */ - thread = rt_thread_create("usbh", rt_usbh_hub_thread_entry, RT_NULL, + thread = rt_thread_create("usbh", rt_usbh_hub_thread_entry, RT_NULL, USB_THREAD_STACK_SIZE, 8, 20); if(thread != RT_NULL) { diff --git a/components/drivers/usb/usbhost/core/usbhost.c b/components/drivers/usb/usbhost/core/usbhost.c index f0294238c4..a76f6d4586 100644 --- a/components/drivers/usb/usbhost/core/usbhost.c +++ b/components/drivers/usb/usbhost/core/usbhost.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -19,13 +19,13 @@ /** * This function will initialize the usb host stack, all the usb class driver and * host controller driver are also be initialized here. - * + * * @return none. */ rt_err_t rt_usb_host_init(void) { ucd_t drv; - rt_device_t uhc; + rt_device_t uhc; uhc = rt_device_find(USB_HOST_CONTROLLER_NAME); if(uhc == RT_NULL) diff --git a/components/drivers/usb/usbhost/core/usbhost_core.c b/components/drivers/usb/usbhost/core/usbhost_core.c index d72dca82f2..71fe3b8b3f 100644 --- a/components/drivers/usb/usbhost/core/usbhost_core.c +++ b/components/drivers/usb/usbhost/core/usbhost_core.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -27,28 +27,28 @@ uinst_t rt_usbh_alloc_instance(uhcd_t uhcd) /* lock scheduler */ rt_enter_critical(); - + for(i=0; idev_desc; - + /* alloc address 0 ep0 pipe*/ ep0_out_desc.wMaxPacketSize = 8; ep0_in_desc.wMaxPacketSize = 8; @@ -106,7 +106,7 @@ rt_err_t rt_usbh_attatch_instance(uinst_t device) rt_usb_hcd_alloc_pipe(device->hcd, &device->pipe_ep0_in, device, &ep0_in_desc); RT_DEBUG_LOG(RT_DEBUG_USB, ("start enumnation\n")); - + /* get device descriptor head */ ret = rt_usbh_get_descriptor(device, USB_DESC_TYPE_DEVICE, (void*)dev_desc, 8); if(ret != RT_EOK) @@ -114,7 +114,7 @@ rt_err_t rt_usbh_attatch_instance(uinst_t device) rt_kprintf("get device descriptor head failed\n"); return ret; } - + /* reset bus */ rt_usbh_hub_reset_port(device->parent_hub, device->port); rt_thread_delay(2); @@ -127,20 +127,20 @@ rt_err_t rt_usbh_attatch_instance(uinst_t device) return ret; } /* free address 0 ep0 pipe*/ - + rt_usb_hcd_free_pipe(device->hcd,device->pipe_ep0_out); rt_usb_hcd_free_pipe(device->hcd,device->pipe_ep0_in); - + /* set device max packet size */ ep0_out_desc.wMaxPacketSize = device->dev_desc.bMaxPacketSize0; ep0_in_desc.wMaxPacketSize = device->dev_desc.bMaxPacketSize0; - + /* alloc true address ep0 pipe*/ rt_usb_hcd_alloc_pipe(device->hcd, &device->pipe_ep0_out, device, &ep0_out_desc); rt_usb_hcd_alloc_pipe(device->hcd, &device->pipe_ep0_in, device, &ep0_in_desc); RT_DEBUG_LOG(RT_DEBUG_USB, ("get device descriptor length %d\n", dev_desc->bLength)); - + /* get full device descriptor again */ ret = rt_usbh_get_descriptor(device, USB_DESC_TYPE_DEVICE, (void*)dev_desc, dev_desc->bLength); if(ret != RT_EOK) @@ -169,7 +169,7 @@ rt_err_t rt_usbh_attatch_instance(uinst_t device) rt_memset(device->cfg_desc, 0, cfg_desc.wTotalLength); /* get full configuration descriptor */ - ret = rt_usbh_get_descriptor(device, USB_DESC_TYPE_CONFIGURATION, + ret = rt_usbh_get_descriptor(device, USB_DESC_TYPE_CONFIGURATION, device->cfg_desc, cfg_desc.wTotalLength); if(ret != RT_EOK) { @@ -179,12 +179,12 @@ rt_err_t rt_usbh_attatch_instance(uinst_t device) /* set configuration */ ret = rt_usbh_set_configure(device, 1); - if(ret != RT_EOK) + if(ret != RT_EOK) { return ret; } for(i=0; icfg_desc->bNumInterfaces; i++) - { + { /* get interface descriptor through configuration descriptor */ ret = rt_usbh_get_interface_descriptor(device->cfg_desc, i, &intf_desc); if(ret != RT_EOK) @@ -193,7 +193,7 @@ rt_err_t rt_usbh_attatch_instance(uinst_t device) return -RT_ERROR; } - RT_DEBUG_LOG(RT_DEBUG_USB, ("interface class 0x%x, subclass 0x%x\n", + RT_DEBUG_LOG(RT_DEBUG_USB, ("interface class 0x%x, subclass 0x%x\n", intf_desc->bInterfaceClass, intf_desc->bInterfaceSubClass)); /* alloc pipe*/ @@ -216,9 +216,9 @@ rt_err_t rt_usbh_attatch_instance(uinst_t device) } } /* find driver by class code found in interface descriptor */ - drv = rt_usbh_class_driver_find(intf_desc->bInterfaceClass, + drv = rt_usbh_class_driver_find(intf_desc->bInterfaceClass, intf_desc->bInterfaceSubClass); - + if(drv != RT_NULL) { /* allocate memory for interface device */ @@ -245,7 +245,7 @@ rt_err_t rt_usbh_attatch_instance(uinst_t device) continue; } } - + return RT_EOK; } @@ -254,19 +254,19 @@ rt_err_t rt_usbh_attatch_instance(uinst_t device) * and release all resource. * * @param device the usb device instance. - * + * * @return the error code, RT_EOK on successfully. */ rt_err_t rt_usbh_detach_instance(uinst_t device) { int i = 0; rt_list_t * l; - if(device == RT_NULL) + if(device == RT_NULL) { rt_kprintf("no usb instance to detach\n"); return -RT_ERROR; } - + /* free configration descriptor */ if (device->cfg_desc) { for (i = 0; i < device->cfg_desc->bNumInterfaces; i++) @@ -282,10 +282,10 @@ rt_err_t rt_usbh_detach_instance(uinst_t device) } rt_free(device->cfg_desc); } - + rt_usb_hcd_free_pipe(device->hcd,device->pipe_ep0_out); rt_usb_hcd_free_pipe(device->hcd,device->pipe_ep0_in); - + while(device->pipe.next!= &device->pipe) { l = device->pipe.next; @@ -293,29 +293,29 @@ rt_err_t rt_usbh_detach_instance(uinst_t device) rt_usb_hcd_free_pipe(device->hcd,rt_list_entry(l,struct upipe,list)); } rt_memset(device, 0, sizeof(struct uinstance)); - + return RT_EOK; } /** * This function will do USB_REQ_GET_DESCRIPTO' bRequest for the usb device instance, * - * @param device the usb device instance. + * @param device the usb device instance. * @param type the type of descriptor bRequest. * @param buffer the data buffer to save requested data * @param nbytes the size of buffer - * + * * @return the error code, RT_EOK on successfully. */ -rt_err_t rt_usbh_get_descriptor(uinst_t device, rt_uint8_t type, void* buffer, +rt_err_t rt_usbh_get_descriptor(uinst_t device, rt_uint8_t type, void* buffer, int nbytes) { struct urequest setup; int timeout = USB_TIMEOUT_BASIC; - + RT_ASSERT(device != RT_NULL); - setup.request_type = USB_REQ_TYPE_DIR_IN | USB_REQ_TYPE_STANDARD | + setup.request_type = USB_REQ_TYPE_DIR_IN | USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_DEVICE; setup.bRequest = USB_REQ_GET_DESCRIPTOR; setup.wIndex = 0; @@ -339,19 +339,19 @@ rt_err_t rt_usbh_get_descriptor(uinst_t device, rt_uint8_t type, void* buffer, * This function will set an address to the usb device. * * @param device the usb device instance. - * + * * @return the error code, RT_EOK on successfully. */ rt_err_t rt_usbh_set_address(uinst_t device) { struct urequest setup; int timeout = USB_TIMEOUT_BASIC; - + RT_ASSERT(device != RT_NULL); RT_DEBUG_LOG(RT_DEBUG_USB, ("rt_usb_set_address\n")); - setup.request_type = USB_REQ_TYPE_DIR_OUT | USB_REQ_TYPE_STANDARD | + setup.request_type = USB_REQ_TYPE_DIR_OUT | USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_DEVICE; setup.bRequest = USB_REQ_SET_ADDRESS; setup.wIndex = 0; @@ -375,7 +375,7 @@ rt_err_t rt_usbh_set_address(uinst_t device) * * @param device the usb device instance. * @param config the configuration number. - * + * * @return the error code, RT_EOK on successfully. */ rt_err_t rt_usbh_set_configure(uinst_t device, int config) @@ -386,7 +386,7 @@ rt_err_t rt_usbh_set_configure(uinst_t device, int config) /* check parameter */ RT_ASSERT(device != RT_NULL); - setup.request_type = USB_REQ_TYPE_DIR_OUT | USB_REQ_TYPE_STANDARD | + setup.request_type = USB_REQ_TYPE_DIR_OUT | USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_DEVICE; setup.bRequest = USB_REQ_SET_CONFIGURATION; setup.wIndex = 0; @@ -401,7 +401,7 @@ rt_err_t rt_usbh_set_configure(uinst_t device, int config) { return RT_ERROR; } - return RT_EOK; + return RT_EOK; } /** @@ -409,7 +409,7 @@ rt_err_t rt_usbh_set_configure(uinst_t device, int config) * * @param device the usb device instance. * @param intf the interface number. - * + * * @return the error code, RT_EOK on successfully. */ rt_err_t rt_usbh_set_interface(uinst_t device, int intf) @@ -420,7 +420,7 @@ rt_err_t rt_usbh_set_interface(uinst_t device, int intf) /* check parameter */ RT_ASSERT(device != RT_NULL); - setup.request_type = USB_REQ_TYPE_DIR_OUT | USB_REQ_TYPE_STANDARD | + setup.request_type = USB_REQ_TYPE_DIR_OUT | USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_INTERFACE; setup.bRequest = USB_REQ_SET_INTERFACE; setup.wIndex = 0; @@ -431,8 +431,8 @@ rt_err_t rt_usbh_set_interface(uinst_t device, int intf) { return RT_ERROR; } - - return RT_EOK; + + return RT_EOK; } /** @@ -440,7 +440,7 @@ rt_err_t rt_usbh_set_interface(uinst_t device, int intf) * * @param device the usb device instance. * @param endpoint the endpoint number of the usb device. - * + * * @return the error code, RT_EOK on successfully. */ rt_err_t rt_usbh_clear_feature(uinst_t device, int endpoint, int feature) @@ -451,7 +451,7 @@ rt_err_t rt_usbh_clear_feature(uinst_t device, int endpoint, int feature) /* check parameter */ RT_ASSERT(device != RT_NULL); - setup.request_type = USB_REQ_TYPE_DIR_OUT | USB_REQ_TYPE_STANDARD | + setup.request_type = USB_REQ_TYPE_DIR_OUT | USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_ENDPOINT; setup.bRequest = USB_REQ_CLEAR_FEATURE; setup.wIndex = endpoint; @@ -462,8 +462,8 @@ rt_err_t rt_usbh_clear_feature(uinst_t device, int endpoint, int feature) { return RT_ERROR; } - - return RT_EOK; + + return RT_EOK; } /** @@ -472,10 +472,10 @@ rt_err_t rt_usbh_clear_feature(uinst_t device, int endpoint, int feature) * @param cfg_desc the point of configuration descriptor structure. * @param num the number of interface descriptor. * @intf_desc the point of interface descriptor point. - * + * * @return the error code, RT_EOK on successfully. */ -rt_err_t rt_usbh_get_interface_descriptor(ucfg_desc_t cfg_desc, int num, +rt_err_t rt_usbh_get_interface_descriptor(ucfg_desc_t cfg_desc, int num, uintf_desc_t* intf_desc) { rt_uint32_t ptr, depth = 0; @@ -487,9 +487,9 @@ rt_err_t rt_usbh_get_interface_descriptor(ucfg_desc_t cfg_desc, int num, ptr = (rt_uint32_t)cfg_desc + cfg_desc->bLength; while(ptr < (rt_uint32_t)cfg_desc + cfg_desc->wTotalLength) { - if(depth++ > 0x20) + if(depth++ > 0x20) { - *intf_desc = RT_NULL; + *intf_desc = RT_NULL; return -RT_EIO; } desc = (udesc_t)ptr; @@ -500,10 +500,10 @@ rt_err_t rt_usbh_get_interface_descriptor(ucfg_desc_t cfg_desc, int num, *intf_desc = (uintf_desc_t)desc; RT_DEBUG_LOG(RT_DEBUG_USB, - ("rt_usb_get_interface_descriptor: %d\n", num)); + ("rt_usb_get_interface_descriptor: %d\n", num)); return RT_EOK; } - } + } ptr = (rt_uint32_t)desc + desc->bLength; } @@ -517,14 +517,14 @@ rt_err_t rt_usbh_get_interface_descriptor(ucfg_desc_t cfg_desc, int num, * @param intf_desc the point of interface descriptor structure. * @param num the number of endpoint descriptor. * @param ep_desc the point of endpoint descriptor point. - * + * * @return the error code, RT_EOK on successfully. */ -rt_err_t rt_usbh_get_endpoint_descriptor(uintf_desc_t intf_desc, int num, +rt_err_t rt_usbh_get_endpoint_descriptor(uintf_desc_t intf_desc, int num, uep_desc_t* ep_desc) { int count = 0, depth = 0; - rt_uint32_t ptr; + rt_uint32_t ptr; udesc_t desc; /* check parameter */ @@ -535,15 +535,15 @@ rt_err_t rt_usbh_get_endpoint_descriptor(uintf_desc_t intf_desc, int num, ptr = (rt_uint32_t)intf_desc + intf_desc->bLength; while(count < intf_desc->bNumEndpoints) { - if(depth++ > 0x20) + if(depth++ > 0x20) { - *ep_desc = RT_NULL; + *ep_desc = RT_NULL; return -RT_EIO; } - desc = (udesc_t)ptr; + desc = (udesc_t)ptr; if(desc->type == USB_DESC_TYPE_ENDPOINT) { - if(num == count) + if(num == count) { *ep_desc = (uep_desc_t)desc; diff --git a/components/drivers/watchdog/watchdog.c b/components/drivers/watchdog/watchdog.c index 09a6bf4fad..38dff5864a 100644 --- a/components/drivers/watchdog/watchdog.c +++ b/components/drivers/watchdog/watchdog.c @@ -1,6 +1,6 @@ /* * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: @@ -65,7 +65,7 @@ static rt_err_t rt_watchdog_control(struct rt_device *dev, } #ifdef RT_USING_DEVICE_OPS -const static struct rt_device_ops wdt_ops = +const static struct rt_device_ops wdt_ops = { rt_watchdog_init, rt_watchdog_open, diff --git a/components/drivers/wlan/wlan_cfg.c b/components/drivers/wlan/wlan_cfg.c index 7fa9ecb2da..0befe6e7da 100644 --- a/components/drivers/wlan/wlan_cfg.c +++ b/components/drivers/wlan/wlan_cfg.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/wlan/wlan_cfg.h b/components/drivers/wlan/wlan_cfg.h index 3fae3f3e98..4d0e73729d 100644 --- a/components/drivers/wlan/wlan_cfg.h +++ b/components/drivers/wlan/wlan_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/wlan/wlan_cmd.c b/components/drivers/wlan/wlan_cmd.c index fead6a8bf2..fde9065428 100644 --- a/components/drivers/wlan/wlan_cmd.c +++ b/components/drivers/wlan/wlan_cmd.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/wlan/wlan_dev.c b/components/drivers/wlan/wlan_dev.c index 347e6a57d4..68df0b3bfc 100644 --- a/components/drivers/wlan/wlan_dev.c +++ b/components/drivers/wlan/wlan_dev.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/wlan/wlan_dev.h b/components/drivers/wlan/wlan_dev.h index 43d6506d6f..41e0fa47d5 100644 --- a/components/drivers/wlan/wlan_dev.h +++ b/components/drivers/wlan/wlan_dev.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -583,7 +583,7 @@ rt_err_t rt_wlan_dev_report_data(struct rt_wlan_device *device, void *buff, int /* * wlan device register interface */ -rt_err_t rt_wlan_dev_register(struct rt_wlan_device *wlan, const char *name, +rt_err_t rt_wlan_dev_register(struct rt_wlan_device *wlan, const char *name, const struct rt_wlan_dev_ops *ops, rt_uint32_t flag, void *user_data); #ifdef __cplusplus diff --git a/components/drivers/wlan/wlan_lwip.c b/components/drivers/wlan/wlan_lwip.c index 3c4e4dd598..30205ac332 100644 --- a/components/drivers/wlan/wlan_lwip.c +++ b/components/drivers/wlan/wlan_lwip.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/wlan/wlan_mgnt.c b/components/drivers/wlan/wlan_mgnt.c index fefe700acc..6abac5691c 100644 --- a/components/drivers/wlan/wlan_mgnt.c +++ b/components/drivers/wlan/wlan_mgnt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/wlan/wlan_mgnt.h b/components/drivers/wlan/wlan_mgnt.h index df0827bb7b..38d5c31da2 100644 --- a/components/drivers/wlan/wlan_mgnt.h +++ b/components/drivers/wlan/wlan_mgnt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/wlan/wlan_prot.c b/components/drivers/wlan/wlan_prot.c index b1a1b5de99..5c32a3fbda 100644 --- a/components/drivers/wlan/wlan_prot.c +++ b/components/drivers/wlan/wlan_prot.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/wlan/wlan_prot.h b/components/drivers/wlan/wlan_prot.h index 2df979270f..5f8930f452 100644 --- a/components/drivers/wlan/wlan_prot.h +++ b/components/drivers/wlan/wlan_prot.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/wlan/wlan_workqueue.c b/components/drivers/wlan/wlan_workqueue.c index 4cd98346d2..76b95e66b0 100644 --- a/components/drivers/wlan/wlan_workqueue.c +++ b/components/drivers/wlan/wlan_workqueue.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/drivers/wlan/wlan_workqueue.h b/components/drivers/wlan/wlan_workqueue.h index 49bc4a5f9f..7a68a27e03 100644 --- a/components/drivers/wlan/wlan_workqueue.h +++ b/components/drivers/wlan/wlan_workqueue.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/finsh/cmd.c b/components/finsh/cmd.c index ebef0eac1c..27f2d71fd7 100644 --- a/components/finsh/cmd.c +++ b/components/finsh/cmd.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/finsh/finsh.h b/components/finsh/finsh.h index eb38682c4f..e99963e74d 100644 --- a/components/finsh/finsh.h +++ b/components/finsh/finsh.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/finsh/finsh_api.h b/components/finsh/finsh_api.h index c601415d82..f3efb432e1 100644 --- a/components/finsh/finsh_api.h +++ b/components/finsh/finsh_api.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/finsh/finsh_compiler.c b/components/finsh/finsh_compiler.c index 1b1f67cb76..306c54aec9 100644 --- a/components/finsh/finsh_compiler.c +++ b/components/finsh/finsh_compiler.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/finsh/finsh_error.c b/components/finsh/finsh_error.c index bdd0108f98..a5cf2eb514 100644 --- a/components/finsh/finsh_error.c +++ b/components/finsh/finsh_error.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/finsh/finsh_error.h b/components/finsh/finsh_error.h index 614e02a350..8dfafd013c 100644 --- a/components/finsh/finsh_error.h +++ b/components/finsh/finsh_error.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/finsh/finsh_heap.c b/components/finsh/finsh_heap.c index 0d185db474..9f64d108dd 100644 --- a/components/finsh/finsh_heap.c +++ b/components/finsh/finsh_heap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/finsh/finsh_heap.h b/components/finsh/finsh_heap.h index 9c04e5c22f..f320c2771a 100644 --- a/components/finsh/finsh_heap.h +++ b/components/finsh/finsh_heap.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/finsh/finsh_init.c b/components/finsh/finsh_init.c index 72f5aa5e9a..76302a0516 100644 --- a/components/finsh/finsh_init.c +++ b/components/finsh/finsh_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/finsh/finsh_node.c b/components/finsh/finsh_node.c index 0de82c189d..82a4c03f1e 100644 --- a/components/finsh/finsh_node.c +++ b/components/finsh/finsh_node.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/finsh/finsh_node.h b/components/finsh/finsh_node.h index c7ce099636..ff4333df13 100644 --- a/components/finsh/finsh_node.h +++ b/components/finsh/finsh_node.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/finsh/finsh_ops.c b/components/finsh/finsh_ops.c index 2eafb50c69..ec8b8cb58a 100644 --- a/components/finsh/finsh_ops.c +++ b/components/finsh/finsh_ops.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/finsh/finsh_ops.h b/components/finsh/finsh_ops.h index 95a8b001fb..0cc945f078 100644 --- a/components/finsh/finsh_ops.h +++ b/components/finsh/finsh_ops.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -25,90 +25,90 @@ * OP [op1] */ -#define FINSH_OP_NOOP 0x00 +#define FINSH_OP_NOOP 0x00 /* add @ r1 = r2 + r3 */ -#define FINSH_OP_ADD_BYTE 0x01 -#define FINSH_OP_ADD_WORD 0x02 -#define FINSH_OP_ADD_DWORD 0x03 +#define FINSH_OP_ADD_BYTE 0x01 +#define FINSH_OP_ADD_WORD 0x02 +#define FINSH_OP_ADD_DWORD 0x03 /* sub @ r1 = r2 - r3 */ -#define FINSH_OP_SUB_BYTE 0x04 -#define FINSH_OP_SUB_WORD 0x05 -#define FINSH_OP_SUB_DWORD 0x06 +#define FINSH_OP_SUB_BYTE 0x04 +#define FINSH_OP_SUB_WORD 0x05 +#define FINSH_OP_SUB_DWORD 0x06 /* div @ r1 = r2 / r3 */ -#define FINSH_OP_DIV_BYTE 0x07 -#define FINSH_OP_DIV_WORD 0x08 -#define FINSH_OP_DIV_DWORD 0x09 +#define FINSH_OP_DIV_BYTE 0x07 +#define FINSH_OP_DIV_WORD 0x08 +#define FINSH_OP_DIV_DWORD 0x09 /* mod @ r1 = r2 % r3 */ -#define FINSH_OP_MOD_BYTE 0x0A -#define FINSH_OP_MOD_WORD 0x0B -#define FINSH_OP_MOD_DWORD 0x0C +#define FINSH_OP_MOD_BYTE 0x0A +#define FINSH_OP_MOD_WORD 0x0B +#define FINSH_OP_MOD_DWORD 0x0C /* mul @ r1 = r2 * r3 */ -#define FINSH_OP_MUL_BYTE 0x0D -#define FINSH_OP_MUL_WORD 0x0E -#define FINSH_OP_MUL_DWORD 0x0F +#define FINSH_OP_MUL_BYTE 0x0D +#define FINSH_OP_MUL_WORD 0x0E +#define FINSH_OP_MUL_DWORD 0x0F /* and @ r1 = r2 & r3 */ -#define FINSH_OP_AND_BYTE 0x10 -#define FINSH_OP_AND_WORD 0x11 -#define FINSH_OP_AND_DWORD 0x12 +#define FINSH_OP_AND_BYTE 0x10 +#define FINSH_OP_AND_WORD 0x11 +#define FINSH_OP_AND_DWORD 0x12 /* or @ r1 = r2 | r3 */ -#define FINSH_OP_OR_BYTE 0x13 -#define FINSH_OP_OR_WORD 0x14 -#define FINSH_OP_OR_DWORD 0x15 +#define FINSH_OP_OR_BYTE 0x13 +#define FINSH_OP_OR_WORD 0x14 +#define FINSH_OP_OR_DWORD 0x15 /* xor @ r1 = r2 ^ r3 */ -#define FINSH_OP_XOR_BYTE 0x16 -#define FINSH_OP_XOR_WORD 0x17 -#define FINSH_OP_XOR_DWORD 0x18 +#define FINSH_OP_XOR_BYTE 0x16 +#define FINSH_OP_XOR_WORD 0x17 +#define FINSH_OP_XOR_DWORD 0x18 /* bw @ r1 = ~r2 */ -#define FINSH_OP_BITWISE_BYTE 0x19 -#define FINSH_OP_BITWISE_WORD 0x1A -#define FINSH_OP_BITWISE_DWORD 0x1B +#define FINSH_OP_BITWISE_BYTE 0x19 +#define FINSH_OP_BITWISE_WORD 0x1A +#define FINSH_OP_BITWISE_DWORD 0x1B /* shl @ r1 = r2 << r3 */ -#define FINSH_OP_SHL_BYTE 0x1C -#define FINSH_OP_SHL_WORD 0x1D -#define FINSH_OP_SHL_DWORD 0x1E +#define FINSH_OP_SHL_BYTE 0x1C +#define FINSH_OP_SHL_WORD 0x1D +#define FINSH_OP_SHL_DWORD 0x1E /* shr @ r1 = r2 >> r3 */ -#define FINSH_OP_SHR_BYTE 0x1F -#define FINSH_OP_SHR_WORD 0x20 -#define FINSH_OP_SHR_DWORD 0x21 +#define FINSH_OP_SHR_BYTE 0x1F +#define FINSH_OP_SHR_WORD 0x20 +#define FINSH_OP_SHR_DWORD 0x21 /* ld @ r1 = [r2] */ -#define FINSH_OP_LD_BYTE 0x22 -#define FINSH_OP_LD_WORD 0x23 -#define FINSH_OP_LD_DWORD 0x24 +#define FINSH_OP_LD_BYTE 0x22 +#define FINSH_OP_LD_WORD 0x23 +#define FINSH_OP_LD_DWORD 0x24 -#define FINSH_OP_LD_VALUE_BYTE 0x25 -#define FINSH_OP_LD_VALUE_WORD 0x26 -#define FINSH_OP_LD_VALUE_DWORD 0x27 +#define FINSH_OP_LD_VALUE_BYTE 0x25 +#define FINSH_OP_LD_VALUE_WORD 0x26 +#define FINSH_OP_LD_VALUE_DWORD 0x27 /* st @ [r2] = r1 */ -#define FINSH_OP_ST_BYTE 0x28 -#define FINSH_OP_ST_WORD 0x29 -#define FINSH_OP_ST_DWORD 0x2A +#define FINSH_OP_ST_BYTE 0x28 +#define FINSH_OP_ST_WORD 0x29 +#define FINSH_OP_ST_DWORD 0x2A /* pop */ -#define FINSH_OP_POP 0x2B +#define FINSH_OP_POP 0x2B /* call r1 @ [r1](stack) */ -#define FINSH_OP_SYSCALL 0x2C +#define FINSH_OP_SYSCALL 0x2C /* load value from stack */ -#define FINSH_OP_LD_VALUE_BYTE_STACK 0x2D -#define FINSH_OP_LD_VALUE_WORD_STACK 0x2E -#define FINSH_OP_LD_VALUE_DWORD_STACK 0x2F +#define FINSH_OP_LD_VALUE_BYTE_STACK 0x2D +#define FINSH_OP_LD_VALUE_WORD_STACK 0x2E +#define FINSH_OP_LD_VALUE_DWORD_STACK 0x2F /* halt */ -#define FINSH_OP_HALT 0xFF +#define FINSH_OP_HALT 0xFF typedef void (*op_func)(); extern const op_func op_table[]; diff --git a/components/finsh/finsh_parser.c b/components/finsh/finsh_parser.c index 0e7617003c..4b8b4af7e4 100644 --- a/components/finsh/finsh_parser.c +++ b/components/finsh/finsh_parser.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/finsh/finsh_parser.h b/components/finsh/finsh_parser.h index 8e149a7e00..2d0148093a 100644 --- a/components/finsh/finsh_parser.h +++ b/components/finsh/finsh_parser.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/finsh/finsh_token.c b/components/finsh/finsh_token.c index 5fb593d816..dfd613da5b 100644 --- a/components/finsh/finsh_token.c +++ b/components/finsh/finsh_token.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/finsh/finsh_token.h b/components/finsh/finsh_token.h index 0ce98c0f14..9845357b8e 100644 --- a/components/finsh/finsh_token.h +++ b/components/finsh/finsh_token.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/finsh/finsh_var.c b/components/finsh/finsh_var.c index 6a27bf1fab..2e3df30c6d 100644 --- a/components/finsh/finsh_var.c +++ b/components/finsh/finsh_var.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/finsh/finsh_var.h b/components/finsh/finsh_var.h index 8d7ee6a201..796f979441 100644 --- a/components/finsh/finsh_var.h +++ b/components/finsh/finsh_var.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/finsh/finsh_vm.c b/components/finsh/finsh_vm.c index 7c56407084..e56cedbdfb 100644 --- a/components/finsh/finsh_vm.c +++ b/components/finsh/finsh_vm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/finsh/finsh_vm.h b/components/finsh/finsh_vm.h index fc515418e4..15d5da1ef8 100644 --- a/components/finsh/finsh_vm.h +++ b/components/finsh/finsh_vm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/finsh/msh.c b/components/finsh/msh.c index 79f1e3c87f..73a5197dcd 100644 --- a/components/finsh/msh.c +++ b/components/finsh/msh.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/finsh/msh.h b/components/finsh/msh.h index b7153107ea..17c7a39ef1 100644 --- a/components/finsh/msh.h +++ b/components/finsh/msh.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/finsh/msh_file.c b/components/finsh/msh_file.c index 10025965f0..b431d944c3 100644 --- a/components/finsh/msh_file.c +++ b/components/finsh/msh_file.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -101,7 +101,7 @@ int msh_exec_script(const char *cmd_line, int size) int length; line_buf = (char *) rt_malloc(RT_CONSOLEBUF_SIZE); - if (line_buf == RT_NULL) + if (line_buf == RT_NULL) { close(fd); return -RT_ENOMEM; diff --git a/components/finsh/shell.c b/components/finsh/shell.c index 61f0b9562e..0d41625184 100644 --- a/components/finsh/shell.c +++ b/components/finsh/shell.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -844,7 +844,7 @@ int finsh_system_init(void) finsh_system_var_init(&__vsymtab_start, &__vsymtab_end); #elif defined(_MSC_VER) unsigned int *ptr_begin, *ptr_end; - + if(shell) { rt_kprintf("finsh shell already init.\n"); diff --git a/components/finsh/shell.h b/components/finsh/shell.h index bf954fb5a6..e6b1921c60 100644 --- a/components/finsh/shell.h +++ b/components/finsh/shell.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/finsh/symbol.c b/components/finsh/symbol.c index 78df9fac5c..c6623e2d82 100644 --- a/components/finsh/symbol.c +++ b/components/finsh/symbol.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2010-03-22 Bernard first version */ - + #include #if defined(RT_USING_FINSH) && !defined(FINSH_USING_SYMTAB) diff --git a/components/libc/aio/posix_aio.c b/components/libc/aio/posix_aio.c index 3eb7634495..66f15e4c57 100644 --- a/components/libc/aio/posix_aio.c +++ b/components/libc/aio/posix_aio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,25 +22,25 @@ struct rt_workqueue* aio_queue = NULL; /** - * The aio_cancel() function shall attempt to cancel one or more asynchronous I/O - * requests currently outstanding against file descriptor fildes. The aiocbp - * argument points to the asynchronous I/O control block for a particular request - * to be canceled. If aiocbp is NULL, then all outstanding cancelable asynchronous + * The aio_cancel() function shall attempt to cancel one or more asynchronous I/O + * requests currently outstanding against file descriptor fildes. The aiocbp + * argument points to the asynchronous I/O control block for a particular request + * to be canceled. If aiocbp is NULL, then all outstanding cancelable asynchronous * I/O requests against fildes shall be canceled. - * - * Normal asynchronous notification shall occur for asynchronous I/O operations - * that are successfully canceled. If there are requests that cannot be canceled, - * then the normal asynchronous completion process shall take place for those + * + * Normal asynchronous notification shall occur for asynchronous I/O operations + * that are successfully canceled. If there are requests that cannot be canceled, + * then the normal asynchronous completion process shall take place for those * requests when they are completed. - * - * For requested operations that are successfully canceled, the associated error - * status shall be set to [ECANCELED] and the return status shall be -1. For - * requested operations that are not successfully canceled, the aiocbp shall not + * + * For requested operations that are successfully canceled, the associated error + * status shall be set to [ECANCELED] and the return status shall be -1. For + * requested operations that are not successfully canceled, the aiocbp shall not * be modified by aio_cancel(). - * - * If aiocbp is not NULL, then if fildes does not have the same value as the file + * + * If aiocbp is not NULL, then if fildes does not have the same value as the file * descriptor with which the asynchronous operation was initiated, unspecified results occur. - * + * * Which operations are cancelable is implementation-defined. */ int aio_cancel(int fd, struct aiocb *cb) @@ -61,9 +61,9 @@ int aio_cancel(int fd, struct aiocb *cb) } /** - * The aio_error() function shall return the error status associated with the - * aiocb structure referenced by the aiocbp argument. The error status for an - * asynchronous I/O operation is the errno value that would be set by the corresponding + * The aio_error() function shall return the error status associated with the + * aiocb structure referenced by the aiocbp argument. The error status for an + * asynchronous I/O operation is the errno value that would be set by the corresponding * read(), write(), */ int aio_error (const struct aiocb *cb) @@ -77,44 +77,44 @@ int aio_error (const struct aiocb *cb) } /** - * The aio_fsync() function shall asynchronously perform a file synchronization - * operation, as specified by the op argument, for I/O operations associated with - * the file indicated by the file descriptor aio_fildes member of the aiocb - * structure referenced by the aiocbp argument and queued at the time of the - * call to aio_fsync(). The function call shall return when the synchronization - * request has been initiated or queued to the file or device (even when the data + * The aio_fsync() function shall asynchronously perform a file synchronization + * operation, as specified by the op argument, for I/O operations associated with + * the file indicated by the file descriptor aio_fildes member of the aiocb + * structure referenced by the aiocbp argument and queued at the time of the + * call to aio_fsync(). The function call shall return when the synchronization + * request has been initiated or queued to the file or device (even when the data * cannot be synchronized immediately). - * - * option: If op is O_DSYNC, all currently queued I/O operations shall be completed - * as if by a call to fdatasync(); that is, as defined for synchronized I/O data + * + * option: If op is O_DSYNC, all currently queued I/O operations shall be completed + * as if by a call to fdatasync(); that is, as defined for synchronized I/O data * integrity completion. - * - * option: If op is O_SYNC, all currently queued I/O operations shall be completed - * as if by a call to fsync(); that is, as defined for synchronized I/O file integrity - * completion. If the aio_fsync() function fails, or if the operation queued by - * aio_fsync() fails, then outstanding I/O operations are not guaranteed to have + * + * option: If op is O_SYNC, all currently queued I/O operations shall be completed + * as if by a call to fsync(); that is, as defined for synchronized I/O file integrity + * completion. If the aio_fsync() function fails, or if the operation queued by + * aio_fsync() fails, then outstanding I/O operations are not guaranteed to have * been completed. - * - * If aio_fsync() succeeds, then it is only the I/O that was queued at the time - * of the call to aio_fsync() that is guaranteed to be forced to the relevant + * + * If aio_fsync() succeeds, then it is only the I/O that was queued at the time + * of the call to aio_fsync() that is guaranteed to be forced to the relevant * completion state. The completion of subsequent I/O on the file descriptor is * not guaranteed to be completed in a synchronized fashion. - * - * The aiocbp argument refers to an asynchronous I/O control block. The aiocbp - * value may be used as an argument to aio_error() and aio_return() in order to - * determine the error status and return status, respectively, of the asynchronous - * operation while it is proceeding. When the request is queued, the error status - * for the operation is [EINPROGRESS]. When all data has been successfully transferred, - * the error status shall be reset to reflect the success or failure of the operation. - * If the operation does not complete successfully, the error status for the - * operation shall be set to indicate the error. The aio_sigevent member determines - * the asynchronous notification to occur as specified in Signal Generation and - * Delivery when all operations have achieved synchronized I/O completion. All - * other members of the structure referenced by aiocbp are ignored. If the control - * block referenced by aiocbp becomes an illegal address prior to asynchronous + * + * The aiocbp argument refers to an asynchronous I/O control block. The aiocbp + * value may be used as an argument to aio_error() and aio_return() in order to + * determine the error status and return status, respectively, of the asynchronous + * operation while it is proceeding. When the request is queued, the error status + * for the operation is [EINPROGRESS]. When all data has been successfully transferred, + * the error status shall be reset to reflect the success or failure of the operation. + * If the operation does not complete successfully, the error status for the + * operation shall be set to indicate the error. The aio_sigevent member determines + * the asynchronous notification to occur as specified in Signal Generation and + * Delivery when all operations have achieved synchronized I/O completion. All + * other members of the structure referenced by aiocbp are ignored. If the control + * block referenced by aiocbp becomes an illegal address prior to asynchronous * I/O completion, then the behavior is undefined. - * - * If the aio_fsync() function fails or aiocbp indicates an error condition, + * + * If the aio_fsync() function fails or aiocbp indicates an error condition, * data is not guaranteed to have been successfully transferred. */ static void aio_fync_work(struct rt_work* work, void* work_data) @@ -169,7 +169,7 @@ static void aio_read_work(struct rt_work* work, void* work_data) level = rt_hw_interrupt_disable(); if (len <= 0) cb->aio_result = errno; - else + else cb->aio_result = len; rt_hw_interrupt_enable(level); @@ -177,51 +177,51 @@ static void aio_read_work(struct rt_work* work, void* work_data) } /** - * The aio_read() function shall read aiocbp->aio_nbytes from the file associated - * with aiocbp->aio_fildes into the buffer pointed to by aiocbp->aio_buf. The - * function call shall return when the read request has been initiated or queued + * The aio_read() function shall read aiocbp->aio_nbytes from the file associated + * with aiocbp->aio_fildes into the buffer pointed to by aiocbp->aio_buf. The + * function call shall return when the read request has been initiated or queued * to the file or device (even when the data cannot be delivered immediately). - * - * If prioritized I/O is supported for this file, then the asynchronous operation - * shall be submitted at a priority equal to a base scheduling priority minus - * aiocbp->aio_reqprio. If Thread Execution Scheduling is not supported, then + * + * If prioritized I/O is supported for this file, then the asynchronous operation + * shall be submitted at a priority equal to a base scheduling priority minus + * aiocbp->aio_reqprio. If Thread Execution Scheduling is not supported, then * the base scheduling priority is that of the calling process; - * - * otherwise, the base scheduling priority is that of the calling thread. - * - * The aiocbp value may be used as an argument to aio_error() and aio_return() - * in order to determine the error status and return status, respectively, of - * the asynchronous operation while it is proceeding. If an error condition is - * encountered during queuing, the function call shall return without having - * initiated or queued the request. The requested operation takes place at the - * absolute position in the file as given by aio_offset, as if lseek() were called - * immediately prior to the operation with an offset equal to aio_offset and a - * whence equal to SEEK_SET. After a successful call to enqueue an asynchronous + * + * otherwise, the base scheduling priority is that of the calling thread. + * + * The aiocbp value may be used as an argument to aio_error() and aio_return() + * in order to determine the error status and return status, respectively, of + * the asynchronous operation while it is proceeding. If an error condition is + * encountered during queuing, the function call shall return without having + * initiated or queued the request. The requested operation takes place at the + * absolute position in the file as given by aio_offset, as if lseek() were called + * immediately prior to the operation with an offset equal to aio_offset and a + * whence equal to SEEK_SET. After a successful call to enqueue an asynchronous * I/O operation, the value of the file offset for the file is unspecified. * - * The aio_sigevent member specifies the notification which occurs when the + * The aio_sigevent member specifies the notification which occurs when the * request is completed. * * The aiocbp->aio_lio_opcode field shall be ignored by aio_read(). - * - * The aiocbp argument points to an aiocb structure. If the buffer pointed to by - * aiocbp->aio_buf or the control block pointed to by aiocbp becomes an illegal + * + * The aiocbp argument points to an aiocb structure. If the buffer pointed to by + * aiocbp->aio_buf or the control block pointed to by aiocbp becomes an illegal * address prior to asynchronous I/O completion, then the behavior is undefined. - * - * Simultaneous asynchronous operations using the same aiocbp produce undefined + * + * Simultaneous asynchronous operations using the same aiocbp produce undefined * results. - * + * * If synchronized I/O is enabled on the file associated with aiocbp->aio_fildes, - * the behavior of this function shall be according to the definitions of synchronized - * I/O data integrity completion and synchronized I/O file integrity completion. - * - * For any system action that changes the process memory space while an asynchronous - * I/O is outstanding to the address range being changed, the result of that action + * the behavior of this function shall be according to the definitions of synchronized + * I/O data integrity completion and synchronized I/O file integrity completion. + * + * For any system action that changes the process memory space while an asynchronous + * I/O is outstanding to the address range being changed, the result of that action * is undefined. - * - * For regular files, no data transfer shall occur past the offset maximum + * + * For regular files, no data transfer shall occur past the offset maximum * established in the open file description associated with aiocbp->aio_fildes. - * + * */ int aio_read(struct aiocb *cb) { @@ -242,16 +242,16 @@ int aio_read(struct aiocb *cb) } /** - * The aio_return() function shall return the return status associated with the - * aiocb structure referenced by the aiocbp argument. The return status for an - * asynchronous I/O operation is the value that would be returned by the corresponding - * read(), write(), or fsync() function call. If the error status for the operation - * is equal to [EINPROGRESS], then the return status for the operation is undefined. - * The aio_return() function may be called exactly once to retrieve the return - * status of a given asynchronous operation; thereafter, if the same aiocb structure - * is used in a call to aio_return() or aio_error(), an error may be returned. - * When the aiocb structure referred to by aiocbp is used to submit another asynchronous - * operation, then aio_return() may be successfully used to retrieve the return + * The aio_return() function shall return the return status associated with the + * aiocb structure referenced by the aiocbp argument. The return status for an + * asynchronous I/O operation is the value that would be returned by the corresponding + * read(), write(), or fsync() function call. If the error status for the operation + * is equal to [EINPROGRESS], then the return status for the operation is undefined. + * The aio_return() function may be called exactly once to retrieve the return + * status of a given asynchronous operation; thereafter, if the same aiocb structure + * is used in a call to aio_return() or aio_error(), an error may be returned. + * When the aiocb structure referred to by aiocbp is used to submit another asynchronous + * operation, then aio_return() may be successfully used to retrieve the return * status of that operation. */ ssize_t aio_return(struct aiocb *cb) @@ -268,23 +268,23 @@ ssize_t aio_return(struct aiocb *cb) } /** - * The aio_suspend() function shall suspend the calling thread until at least - * one of the asynchronous I/O operations referenced by the list argument has - * completed, until a signal interrupts the function, or, if timeout is not NULL, - * until the time interval specified by timeout has passed. If any of the aiocb - * structures in the list correspond to completed asynchronous I/O operations - * (that is, the error status for the operation is not equal to [EINPROGRESS]) - * at the time of the call, the function shall return without suspending the - * calling thread. The list argument is an array of pointers to asynchronous I/O - * control blocks. The nent argument indicates the number of elements in the - * array. Each aiocb structure pointed to has been used in initiating an asynchronous - * I/O request via aio_read(), aio_write(), or lio_listio(). This array may - * contain null pointers, which are ignored. If this array contains pointers - * that refer to aiocb structures that have not been used in submitting asynchronous + * The aio_suspend() function shall suspend the calling thread until at least + * one of the asynchronous I/O operations referenced by the list argument has + * completed, until a signal interrupts the function, or, if timeout is not NULL, + * until the time interval specified by timeout has passed. If any of the aiocb + * structures in the list correspond to completed asynchronous I/O operations + * (that is, the error status for the operation is not equal to [EINPROGRESS]) + * at the time of the call, the function shall return without suspending the + * calling thread. The list argument is an array of pointers to asynchronous I/O + * control blocks. The nent argument indicates the number of elements in the + * array. Each aiocb structure pointed to has been used in initiating an asynchronous + * I/O request via aio_read(), aio_write(), or lio_listio(). This array may + * contain null pointers, which are ignored. If this array contains pointers + * that refer to aiocb structures that have not been used in submitting asynchronous * I/O, the effect is undefined. - * - * If the time interval indicated in the timespec structure pointed to by timeout - * passes before any of the I/O operations referenced by list are completed, then + * + * If the time interval indicated in the timespec structure pointed to by timeout + * passes before any of the I/O operations referenced by list are completed, then * aio_suspend() shall return with an error. */ int aio_suspend(const struct aiocb *const list[], int nent, @@ -315,7 +315,7 @@ static void aio_write_work(struct rt_work* work, void* work_data) level = rt_hw_interrupt_disable(); if (len <= 0) cb->aio_result = errno; - else + else cb->aio_result = len; rt_hw_interrupt_enable(level); @@ -323,42 +323,42 @@ static void aio_write_work(struct rt_work* work, void* work_data) } /** - * The aio_write() function shall write aiocbp->aio_nbytes to the file associated - * with aiocbp->aio_fildes from the buffer pointed to by aiocbp->aio_buf. The - * function shall return when the write request has been initiated or, at a minimum, + * The aio_write() function shall write aiocbp->aio_nbytes to the file associated + * with aiocbp->aio_fildes from the buffer pointed to by aiocbp->aio_buf. The + * function shall return when the write request has been initiated or, at a minimum, * queued to the file or device. - * - * The aiocbp argument may be used as an argument to aio_error() and aio_return() - * in order to determine the error status and return status, respectively, of the + * + * The aiocbp argument may be used as an argument to aio_error() and aio_return() + * in order to determine the error status and return status, respectively, of the * asynchronous operation while it is proceeding. - * - * The aiocbp argument points to an aiocb structure. If the buffer pointed to by - * aiocbp->aio_buf or the control block pointed to by aiocbp becomes an illegal + * + * The aiocbp argument points to an aiocb structure. If the buffer pointed to by + * aiocbp->aio_buf or the control block pointed to by aiocbp becomes an illegal * address prior to asynchronous I/O completion, then the behavior is undefined. - * - * If O_APPEND is not set for the file descriptor aio_fildes, then the requested - * operation shall take place at the absolute position in the file as given by - * aio_offset, as if lseek() were called immediately prior to the operation with - * an offset equal to aio_offset and a whence equal to SEEK_SET. If O_APPEND is - * set for the file descriptor, or if aio_fildes is associated with a device that - * is incapable of seeking, write operations append to the file in the same order - * as the calls were made, except under circumstances described in Asynchronous - * I/O. After a successful call to enqueue an asynchronous I/O operation, the value + * + * If O_APPEND is not set for the file descriptor aio_fildes, then the requested + * operation shall take place at the absolute position in the file as given by + * aio_offset, as if lseek() were called immediately prior to the operation with + * an offset equal to aio_offset and a whence equal to SEEK_SET. If O_APPEND is + * set for the file descriptor, or if aio_fildes is associated with a device that + * is incapable of seeking, write operations append to the file in the same order + * as the calls were made, except under circumstances described in Asynchronous + * I/O. After a successful call to enqueue an asynchronous I/O operation, the value * of the file offset for the file is unspecified. - * - * The aio_sigevent member specifies the notification which occurs when the request + * + * The aio_sigevent member specifies the notification which occurs when the request * is completed. - * + * * The aiocbp->aio_lio_opcode field shall be ignored by aio_write(). - * - * Simultaneous asynchronous operations using the same aiocbp produce undefined + * + * Simultaneous asynchronous operations using the same aiocbp produce undefined * results. - * - * If synchronized I/O is enabled on the file associated with aiocbp->aio_fildes, - * the behavior of this function shall be according to the definitions of synchronized + * + * If synchronized I/O is enabled on the file associated with aiocbp->aio_fildes, + * the behavior of this function shall be according to the definitions of synchronized * I/O data integrity completion, and synchronized I/O file integrity completion. - * - * For regular files, no data transfer shall occur past the offset maximum established + * + * For regular files, no data transfer shall occur past the offset maximum established * in the open file description associated with aiocbp->aio_fildes. */ int aio_write(struct aiocb *cb) @@ -385,69 +385,69 @@ int aio_write(struct aiocb *cb) } /** - * The lio_listio() function shall initiate a list of I/O requests with a single + * The lio_listio() function shall initiate a list of I/O requests with a single * function call. - * - * The mode argument takes one of the values LIO_WAIT or LIO_NOWAIT declared in - * and determines whether the function returns when the I/O operations - * have been completed, or as soon as the operations have been queued. If the - * mode argument is LIO_WAIT, the function shall wait until all I/O is complete + * + * The mode argument takes one of the values LIO_WAIT or LIO_NOWAIT declared in + * and determines whether the function returns when the I/O operations + * have been completed, or as soon as the operations have been queued. If the + * mode argument is LIO_WAIT, the function shall wait until all I/O is complete * and the sig argument shall be ignored. - * - * If the mode argument is LIO_NOWAIT, the function shall return immediately, and - * asynchronous notification shall occur, according to the sig argument, when all - * the I/O operations complete. If sig is NULL, then no asynchronous notification - * shall occur. If sig is not NULL, asynchronous notification occurs as specified + * + * If the mode argument is LIO_NOWAIT, the function shall return immediately, and + * asynchronous notification shall occur, according to the sig argument, when all + * the I/O operations complete. If sig is NULL, then no asynchronous notification + * shall occur. If sig is not NULL, asynchronous notification occurs as specified * in Signal Generation and Delivery when all the requests in list have completed. - * + * * The I/O requests enumerated by list are submitted in an unspecified order. - * - * The list argument is an array of pointers to aiocb structures. The array contains + * + * The list argument is an array of pointers to aiocb structures. The array contains * nent elements. The array may contain NULL elements, which shall be ignored. - * - * If the buffer pointed to by list or the aiocb structures pointed to by the - * elements of the array list become illegal addresses before all asynchronous I/O - * completed and, if necessary, the notification is sent, then the behavior is - * undefined. If the buffers pointed to by the aio_buf member of the aiocb structure - * pointed to by the elements of the array list become illegal addresses prior to - * the asynchronous I/O associated with that aiocb structure being completed, the + * + * If the buffer pointed to by list or the aiocb structures pointed to by the + * elements of the array list become illegal addresses before all asynchronous I/O + * completed and, if necessary, the notification is sent, then the behavior is + * undefined. If the buffers pointed to by the aio_buf member of the aiocb structure + * pointed to by the elements of the array list become illegal addresses prior to + * the asynchronous I/O associated with that aiocb structure being completed, the * behavior is undefined. - * - * The aio_lio_opcode field of each aiocb structure specifies the operation to be - * performed. The supported operations are LIO_READ, LIO_WRITE, and LIO_NOP; these - * symbols are defined in . The LIO_NOP operation causes the list entry to - * be ignored. If the aio_lio_opcode element is equal to LIO_READ, then an I/O operation - * is submitted as if by a call to aio_read() with the aiocbp equal to the address - * of the aiocb structure. If the aio_lio_opcode element is equal to LIO_WRITE, then - * an I/O operation is submitted as if by a call to aio_write() with the aiocbp equal + * + * The aio_lio_opcode field of each aiocb structure specifies the operation to be + * performed. The supported operations are LIO_READ, LIO_WRITE, and LIO_NOP; these + * symbols are defined in . The LIO_NOP operation causes the list entry to + * be ignored. If the aio_lio_opcode element is equal to LIO_READ, then an I/O operation + * is submitted as if by a call to aio_read() with the aiocbp equal to the address + * of the aiocb structure. If the aio_lio_opcode element is equal to LIO_WRITE, then + * an I/O operation is submitted as if by a call to aio_write() with the aiocbp equal * to the address of the aiocb structure. - * - * The aio_fildes member specifies the file descriptor on which the operation is to + * + * The aio_fildes member specifies the file descriptor on which the operation is to * be performed. - * - * The aio_buf member specifies the address of the buffer to or from which the data + * + * The aio_buf member specifies the address of the buffer to or from which the data * is transferred. - * + * * The aio_nbytes member specifies the number of bytes of data to be transferred. - * - * The members of the aiocb structure further describe the I/O operation to be - * performed, in a manner identical to that of the corresponding aiocb structure + * + * The members of the aiocb structure further describe the I/O operation to be + * performed, in a manner identical to that of the corresponding aiocb structure * when used by the aio_read() and aio_write() functions. - * - * The nent argument specifies how many elements are members of the list; that is, + * + * The nent argument specifies how many elements are members of the list; that is, * the length of the array. - * - * The behavior of this function is altered according to the definitions of synchronized - * I/O data integrity completion and synchronized I/O file integrity completion if + * + * The behavior of this function is altered according to the definitions of synchronized + * I/O data integrity completion and synchronized I/O file integrity completion if * synchronized I/O is enabled on the file associated with aio_fildes. - * - * For regular files, no data transfer shall occur past the offset maximum established + * + * For regular files, no data transfer shall occur past the offset maximum established * in the open file description associated with aiocbp->aio_fildes. - * - * If sig->sigev_notify is SIGEV_THREAD and sig->sigev_notify_attributes is a - * non-null pointer and the block pointed to by this pointer becomes an illegal - * address prior to all asynchronous I/O being completed, then the behavior is - * undefined. + * + * If sig->sigev_notify is SIGEV_THREAD and sig->sigev_notify_attributes is a + * non-null pointer and the block pointed to by this pointer becomes an illegal + * address prior to all asynchronous I/O being completed, then the behavior is + * undefined. */ int lio_listio(int mode, struct aiocb * const list[], int nent, struct sigevent *sig) diff --git a/components/libc/aio/posix_aio.h b/components/libc/aio/posix_aio.h index f20ed48cb3..de11738515 100644 --- a/components/libc/aio/posix_aio.h +++ b/components/libc/aio/posix_aio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/armlibc/dirent.h b/components/libc/compilers/armlibc/dirent.h index d3bc58cbc5..2c0521d2e3 100644 --- a/components/libc/compilers/armlibc/dirent.h +++ b/components/libc/compilers/armlibc/dirent.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -18,32 +18,32 @@ */ /* File types */ -#define FT_REGULAR 0 /* regular file */ -#define FT_SOCKET 1 /* socket file */ -#define FT_DIRECTORY 2 /* directory */ -#define FT_USER 3 /* user defined */ +#define FT_REGULAR 0 /* regular file */ +#define FT_SOCKET 1 /* socket file */ +#define FT_DIRECTORY 2 /* directory */ +#define FT_USER 3 /* user defined */ #ifdef __cplusplus extern "C" { #endif #ifndef HAVE_DIR_STRUCTURE -typedef struct +typedef struct { - int fd; /* directory file */ - char buf[512]; - int num; - int cur; + int fd; /* directory file */ + char buf[512]; + int num; + int cur; } DIR; #endif #ifndef HAVE_DIRENT_STRUCTURE struct dirent { - rt_uint8_t d_type; /* The type of the file */ - rt_uint8_t d_namlen; /* The length of the not including the terminating null file name */ - rt_uint16_t d_reclen; /* length of this record */ - char d_name[256]; /* The null-terminated file name */ + rt_uint8_t d_type; /* The type of the file */ + rt_uint8_t d_namlen; /* The length of the not including the terminating null file name */ + rt_uint16_t d_reclen; /* length of this record */ + char d_name[256]; /* The null-terminated file name */ }; #endif diff --git a/components/libc/compilers/armlibc/fcntl.h b/components/libc/compilers/armlibc/fcntl.h index 3e650a8471..f247b926e9 100644 --- a/components/libc/compilers/armlibc/fcntl.h +++ b/components/libc/compilers/armlibc/fcntl.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/armlibc/libc.c b/components/libc/compilers/armlibc/libc.c index fee390d4b4..971ddb8d49 100644 --- a/components/libc/compilers/armlibc/libc.c +++ b/components/libc/compilers/armlibc/libc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/armlibc/libc.h b/components/libc/compilers/armlibc/libc.h index b9b1b6212d..aecf8cdc50 100644 --- a/components/libc/compilers/armlibc/libc.h +++ b/components/libc/compilers/armlibc/libc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/armlibc/libc_syms.c b/components/libc/compilers/armlibc/libc_syms.c index 0e1c42d899..d03197a5db 100644 --- a/components/libc/compilers/armlibc/libc_syms.c +++ b/components/libc/compilers/armlibc/libc_syms.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/armlibc/mem_std.c b/components/libc/compilers/armlibc/mem_std.c index e160104a25..c350aa68fa 100644 --- a/components/libc/compilers/armlibc/mem_std.c +++ b/components/libc/compilers/armlibc/mem_std.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/armlibc/stdio.c b/components/libc/compilers/armlibc/stdio.c index 5262a4dd92..c786c78aa5 100644 --- a/components/libc/compilers/armlibc/stdio.c +++ b/components/libc/compilers/armlibc/stdio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/armlibc/stubs.c b/components/libc/compilers/armlibc/stubs.c index b4cc13799e..5d9331ba17 100644 --- a/components/libc/compilers/armlibc/stubs.c +++ b/components/libc/compilers/armlibc/stubs.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -9,7 +9,7 @@ * 2013-11-24 aozima fixed _sys_read()/_sys_write() issues. * 2014-08-03 bernard If using msh, use system() implementation * in msh. - * 2020-08-05 Meco Man fixed _sys_flen() compiling-warning when + * 2020-08-05 Meco Man fixed _sys_flen() compiling-warning when * RT_USING_DFS is not defined */ @@ -310,7 +310,7 @@ int system(const char *string) #ifdef __MICROLIB #include -int fputc(int c, FILE *f) +int fputc(int c, FILE *f) { char ch[2] = {0}; @@ -319,7 +319,7 @@ int fputc(int c, FILE *f) return 1; } -int fgetc(FILE *f) +int fgetc(FILE *f) { #ifdef RT_USING_POSIX char ch; diff --git a/components/libc/compilers/armlibc/sys/errno.h b/components/libc/compilers/armlibc/sys/errno.h index 9c4307ebfb..74cc986f7c 100644 --- a/components/libc/compilers/armlibc/sys/errno.h +++ b/components/libc/compilers/armlibc/sys/errno.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/armlibc/sys/ioctl.h b/components/libc/compilers/armlibc/sys/ioctl.h index 033a57014a..df17b19a61 100644 --- a/components/libc/compilers/armlibc/sys/ioctl.h +++ b/components/libc/compilers/armlibc/sys/ioctl.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/armlibc/sys/mman.h b/components/libc/compilers/armlibc/sys/mman.h index 8c61b32b7c..6a260ccd70 100644 --- a/components/libc/compilers/armlibc/sys/mman.h +++ b/components/libc/compilers/armlibc/sys/mman.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/armlibc/sys/stat.h b/components/libc/compilers/armlibc/sys/stat.h index ce95230e88..c4b42083c4 100644 --- a/components/libc/compilers/armlibc/sys/stat.h +++ b/components/libc/compilers/armlibc/sys/stat.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/armlibc/sys/types.h b/components/libc/compilers/armlibc/sys/types.h index 78fee1bb99..d87a13a27e 100644 --- a/components/libc/compilers/armlibc/sys/types.h +++ b/components/libc/compilers/armlibc/sys/types.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/armlibc/sys/unistd.h b/components/libc/compilers/armlibc/sys/unistd.h index 1763282812..2f188735de 100644 --- a/components/libc/compilers/armlibc/sys/unistd.h +++ b/components/libc/compilers/armlibc/sys/unistd.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/armlibc/unistd.h b/components/libc/compilers/armlibc/unistd.h index 70187722d8..9b96d45adb 100644 --- a/components/libc/compilers/armlibc/unistd.h +++ b/components/libc/compilers/armlibc/unistd.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/common/sys/time.h b/components/libc/compilers/common/sys/time.h index 79cfbbfaf2..92552c294b 100644 --- a/components/libc/compilers/common/sys/time.h +++ b/components/libc/compilers/common/sys/time.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/common/termios.h b/components/libc/compilers/common/termios.h index 414d0c0cb3..2960d52c58 100644 --- a/components/libc/compilers/common/termios.h +++ b/components/libc/compilers/common/termios.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/common/time.c b/components/libc/compilers/common/time.c index 50a800b259..6c184fbf43 100644 --- a/components/libc/compilers/common/time.c +++ b/components/libc/compilers/common/time.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -246,9 +246,9 @@ int gettimeofday(struct timeval *tp, void *ignore) #if defined (__IAR_SYSTEMS_ICC__) && (__VER__) >= 6020000 #pragma module_name = "?time" #if _DLIB_TIME_USES_64 -time_t __time64(time_t *t) +time_t __time64(time_t *t) #else -time_t __time32(time_t *t) +time_t __time32(time_t *t) #endif #else time_t time(time_t *t) diff --git a/components/libc/compilers/common/unistd.c b/components/libc/compilers/common/unistd.c index df970b2b59..cdc065d05a 100644 --- a/components/libc/compilers/common/unistd.c +++ b/components/libc/compilers/common/unistd.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/dlib/dirent.h b/components/libc/compilers/dlib/dirent.h index 4c897cc550..2c0521d2e3 100644 --- a/components/libc/compilers/dlib/dirent.h +++ b/components/libc/compilers/dlib/dirent.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/dlib/environ.c b/components/libc/compilers/dlib/environ.c index ac19758838..84b04fda55 100644 --- a/components/libc/compilers/dlib/environ.c +++ b/components/libc/compilers/dlib/environ.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/dlib/fcntl.h b/components/libc/compilers/dlib/fcntl.h index ce95230e88..c4b42083c4 100644 --- a/components/libc/compilers/dlib/fcntl.h +++ b/components/libc/compilers/dlib/fcntl.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/dlib/libc.c b/components/libc/compilers/dlib/libc.c index 8b42411a6b..d0dca7c5f6 100644 --- a/components/libc/compilers/dlib/libc.c +++ b/components/libc/compilers/dlib/libc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/dlib/libc.h b/components/libc/compilers/dlib/libc.h index 5b46bee0c8..fc3cafca78 100644 --- a/components/libc/compilers/dlib/libc.h +++ b/components/libc/compilers/dlib/libc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/dlib/rmtx.c b/components/libc/compilers/dlib/rmtx.c index 69405c8f6a..66c3f9377d 100644 --- a/components/libc/compilers/dlib/rmtx.c +++ b/components/libc/compilers/dlib/rmtx.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,7 +22,7 @@ void _Mtxinit(_Rmtx *m) rt_mutex_t mutex; RT_ASSERT(m != RT_NULL); - + mutex = (rt_mutex_t)m; rt_mutex_init(mutex, "iarMtx", RT_IPC_FLAG_FIFO); } diff --git a/components/libc/compilers/dlib/stdio.c b/components/libc/compilers/dlib/stdio.c index b35ade7a38..c11157d759 100644 --- a/components/libc/compilers/dlib/stdio.c +++ b/components/libc/compilers/dlib/stdio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/dlib/sys/errno.h b/components/libc/compilers/dlib/sys/errno.h index 1ad4c8acc0..54a1d33cd0 100644 --- a/components/libc/compilers/dlib/sys/errno.h +++ b/components/libc/compilers/dlib/sys/errno.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/dlib/sys/mman.h b/components/libc/compilers/dlib/sys/mman.h index 8c61b32b7c..6a260ccd70 100644 --- a/components/libc/compilers/dlib/sys/mman.h +++ b/components/libc/compilers/dlib/sys/mman.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/dlib/sys/signal.h b/components/libc/compilers/dlib/sys/signal.h index 22adb1228b..a30235f2b2 100644 --- a/components/libc/compilers/dlib/sys/signal.h +++ b/components/libc/compilers/dlib/sys/signal.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/dlib/sys/stat.h b/components/libc/compilers/dlib/sys/stat.h index ce95230e88..c4b42083c4 100644 --- a/components/libc/compilers/dlib/sys/stat.h +++ b/components/libc/compilers/dlib/sys/stat.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/dlib/sys/types.h b/components/libc/compilers/dlib/sys/types.h index 7dbeddcaa9..e13a0f6d08 100644 --- a/components/libc/compilers/dlib/sys/types.h +++ b/components/libc/compilers/dlib/sys/types.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/dlib/sys/unistd.h b/components/libc/compilers/dlib/sys/unistd.h index 29f68f24f8..a4dac0cf66 100644 --- a/components/libc/compilers/dlib/sys/unistd.h +++ b/components/libc/compilers/dlib/sys/unistd.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,22 +17,22 @@ #include #else -#define _FREAD 0x0001 /* read enabled */ -#define _FWRITE 0x0002 /* write enabled */ -#define _FAPPEND 0x0008 /* append (writes guaranteed at the end) */ -#define _FMARK 0x0010 /* internal; mark during gc() */ -#define _FDEFER 0x0020 /* internal; defer for next gc pass */ -#define _FASYNC 0x0040 /* signal pgrp when data ready */ -#define _FSHLOCK 0x0080 /* BSD flock() shared lock present */ -#define _FEXLOCK 0x0100 /* BSD flock() exclusive lock present */ -#define _FCREAT 0x0200 /* open with file create */ -#define _FTRUNC 0x0400 /* open with truncation */ -#define _FEXCL 0x0800 /* error on open if file exists */ -#define _FNBIO 0x1000 /* non blocking I/O (sys5 style) */ -#define _FSYNC 0x2000 /* do all writes synchronously */ -#define _FNONBLOCK 0x4000 /* non blocking I/O (POSIX style) */ -#define _FNDELAY _FNONBLOCK /* non blocking I/O (4.2 style) */ -#define _FNOCTTY 0x8000 /* don't assign a ctty on this open */ +#define _FREAD 0x0001 /* read enabled */ +#define _FWRITE 0x0002 /* write enabled */ +#define _FAPPEND 0x0008 /* append (writes guaranteed at the end) */ +#define _FMARK 0x0010 /* internal; mark during gc() */ +#define _FDEFER 0x0020 /* internal; defer for next gc pass */ +#define _FASYNC 0x0040 /* signal pgrp when data ready */ +#define _FSHLOCK 0x0080 /* BSD flock() shared lock present */ +#define _FEXLOCK 0x0100 /* BSD flock() exclusive lock present */ +#define _FCREAT 0x0200 /* open with file create */ +#define _FTRUNC 0x0400 /* open with truncation */ +#define _FEXCL 0x0800 /* error on open if file exists */ +#define _FNBIO 0x1000 /* non blocking I/O (sys5 style) */ +#define _FSYNC 0x2000 /* do all writes synchronously */ +#define _FNONBLOCK 0x4000 /* non blocking I/O (POSIX style) */ +#define _FNDELAY _FNONBLOCK /* non blocking I/O (4.2 style) */ +#define _FNOCTTY 0x8000 /* don't assign a ctty on this open */ #endif diff --git a/components/libc/compilers/dlib/syscall_close.c b/components/libc/compilers/dlib/syscall_close.c index f46162deb7..7ed1cc2f2d 100644 --- a/components/libc/compilers/dlib/syscall_close.c +++ b/components/libc/compilers/dlib/syscall_close.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/dlib/syscall_lseek.c b/components/libc/compilers/dlib/syscall_lseek.c index b79cc410b7..47a069bf0a 100644 --- a/components/libc/compilers/dlib/syscall_lseek.c +++ b/components/libc/compilers/dlib/syscall_lseek.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/dlib/syscall_mem.c b/components/libc/compilers/dlib/syscall_mem.c index 236ef1c12d..9c6de64455 100644 --- a/components/libc/compilers/dlib/syscall_mem.c +++ b/components/libc/compilers/dlib/syscall_mem.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/dlib/syscall_open.c b/components/libc/compilers/dlib/syscall_open.c index 96e02dc32a..37bfcecb47 100644 --- a/components/libc/compilers/dlib/syscall_open.c +++ b/components/libc/compilers/dlib/syscall_open.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/dlib/syscall_read.c b/components/libc/compilers/dlib/syscall_read.c index e248211486..afb661bd93 100644 --- a/components/libc/compilers/dlib/syscall_read.c +++ b/components/libc/compilers/dlib/syscall_read.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/dlib/syscall_remove.c b/components/libc/compilers/dlib/syscall_remove.c index e7f0268b1b..629127bf74 100644 --- a/components/libc/compilers/dlib/syscall_remove.c +++ b/components/libc/compilers/dlib/syscall_remove.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/dlib/syscall_write.c b/components/libc/compilers/dlib/syscall_write.c index 85c0da22c3..de464530b8 100644 --- a/components/libc/compilers/dlib/syscall_write.c +++ b/components/libc/compilers/dlib/syscall_write.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/dlib/syscalls.h b/components/libc/compilers/dlib/syscalls.h index 993962e8db..3a89f16e01 100644 --- a/components/libc/compilers/dlib/syscalls.h +++ b/components/libc/compilers/dlib/syscalls.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/dlib/unistd.h b/components/libc/compilers/dlib/unistd.h index a07d8409c2..72b9d538ec 100644 --- a/components/libc/compilers/dlib/unistd.h +++ b/components/libc/compilers/dlib/unistd.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/minilibc/ctype.c b/components/libc/compilers/minilibc/ctype.c index b94ff2dae8..4278d8e419 100644 --- a/components/libc/compilers/minilibc/ctype.c +++ b/components/libc/compilers/minilibc/ctype.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,34 +16,34 @@ int isprint (int ch) { - ch&=0x7f; - return (ch>=32 && ch<127); + ch&=0x7f; + return (ch>=32 && ch<127); } int isalpha(int ch) { - return (unsigned int)((ch | 0x20) - 'a') < 26u; + return (unsigned int)((ch | 0x20) - 'a') < 26u; } int isdigit (int ch) { - return (unsigned int)(ch - '0') < 10u; + return (unsigned int)(ch - '0') < 10u; } int isspace(int ch) { - switch(ch) - { - case ' ': - case '\n': - case '\f': - case '\r': - case '\t': - case '\v': - return 1; - default: - return 0; - } + switch(ch) + { + case ' ': + case '\n': + case '\f': + case '\r': + case '\t': + case '\v': + return 1; + default: + return 0; + } } #endif diff --git a/components/libc/compilers/minilibc/ctype.h b/components/libc/compilers/minilibc/ctype.h index 5f41376ed8..9d394dd125 100644 --- a/components/libc/compilers/minilibc/ctype.h +++ b/components/libc/compilers/minilibc/ctype.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/minilibc/errno.h b/components/libc/compilers/minilibc/errno.h index a7ee380594..b1cbe5452b 100644 --- a/components/libc/compilers/minilibc/errno.h +++ b/components/libc/compilers/minilibc/errno.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -11,6 +11,6 @@ #include "libc/libc_errno.h" /* Others defined in libc/libc_errno.h */ -#define ENSRNOTFOUND 163 /* Domain name not found */ +#define ENSRNOTFOUND 163 /* Domain name not found */ #endif diff --git a/components/libc/compilers/minilibc/inttypes.h b/components/libc/compilers/minilibc/inttypes.h index 8bab743655..595e83a085 100644 --- a/components/libc/compilers/minilibc/inttypes.h +++ b/components/libc/compilers/minilibc/inttypes.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/minilibc/math.c b/components/libc/compilers/minilibc/math.c index cd5770178e..375e94344f 100644 --- a/components/libc/compilers/minilibc/math.c +++ b/components/libc/compilers/minilibc/math.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/minilibc/math.h b/components/libc/compilers/minilibc/math.h index 49b80d8219..327f470920 100644 --- a/components/libc/compilers/minilibc/math.h +++ b/components/libc/compilers/minilibc/math.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/minilibc/qsort.c b/components/libc/compilers/minilibc/qsort.c index 2b97ce763c..5f11e3a4fd 100644 --- a/components/libc/compilers/minilibc/qsort.c +++ b/components/libc/compilers/minilibc/qsort.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -24,7 +24,7 @@ static void exch(char* base,size_t size,size_t a,size_t b) { /* Blame him for the scary variable names */ /* http://www.cs.princeton.edu/~rs/talks/QuicksortIsOptimal.pdf */ static void quicksort(char* base,size_t size,ssize_t l,ssize_t r, - int (*compar)(const void*,const void*)) { + int (*compar)(const void*,const void*)) { ssize_t i=l-1, j=r, p=l-1, q=r, k; char* v=base+r*size; if (r<=l) return; diff --git a/components/libc/compilers/minilibc/rand.c b/components/libc/compilers/minilibc/rand.c index 88603dc808..8bbf42a32b 100644 --- a/components/libc/compilers/minilibc/rand.c +++ b/components/libc/compilers/minilibc/rand.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,10 +13,10 @@ static unsigned int _seed=1; /* Knuth's TAOCP section 3.6 */ -#define M ((1U<<31) -1) -#define A 48271 -#define Q 44488 // M/A -#define R 3399 // M%A; R < Q !!! +#define M ((1U<<31) -1) +#define A 48271 +#define Q 44488 // M/A +#define R 3399 // M%A; R < Q !!! int rand_r(unsigned int* seed) { int32_t X; @@ -24,7 +24,7 @@ int rand_r(unsigned int* seed) X = *seed; X = A*(X%Q) - R * (int32_t) (X/Q); if (X < 0) - X += M; + X += M; *seed = X; return X; @@ -35,8 +35,8 @@ int rand(void) { } void srand(unsigned int i) -{ - _seed=i; +{ + _seed=i; } int random(void) __attribute__((alias("rand"))); diff --git a/components/libc/compilers/minilibc/signal.h b/components/libc/compilers/minilibc/signal.h index f52f1e1009..e350d166b7 100644 --- a/components/libc/compilers/minilibc/signal.h +++ b/components/libc/compilers/minilibc/signal.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/minilibc/stddef.h b/components/libc/compilers/minilibc/stddef.h index 7353a157cb..496c4b8ecf 100644 --- a/components/libc/compilers/minilibc/stddef.h +++ b/components/libc/compilers/minilibc/stddef.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/minilibc/stdint.h b/components/libc/compilers/minilibc/stdint.h index bd5fdc83f5..b2fb999c74 100644 --- a/components/libc/compilers/minilibc/stdint.h +++ b/components/libc/compilers/minilibc/stdint.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -223,7 +223,7 @@ typedef __UINTMAX_TYPE__ uintmax_t; #define WINT_MIN __WINT_MIN__ #endif /* (!defined __cplusplus || __cplusplus >= 201103L - || defined __STDC_LIMIT_MACROS) */ + || defined __STDC_LIMIT_MACROS) */ #if (!defined __cplusplus || __cplusplus >= 201103L \ || defined __STDC_CONSTANT_MACROS) @@ -250,7 +250,7 @@ typedef __UINTMAX_TYPE__ uintmax_t; #define UINTMAX_C(c) __UINTMAX_C(c) #endif /* (!defined __cplusplus || __cplusplus >= 201103L - || defined __STDC_CONSTANT_MACROS) */ + || defined __STDC_CONSTANT_MACROS) */ #ifndef __INT_MAX__ #define __INT_MAX__ 2147483647 @@ -259,8 +259,8 @@ typedef __UINTMAX_TYPE__ uintmax_t; #define INT_MAX (__INT_MAX__) #define UINT_MAX (INT_MAX * 2U + 1U) -#define LONG_MAX ((long)(~0UL>>1)) -#define LONG_MIN (-LONG_MAX - 1) -#define ULONG_MAX (~0UL) +#define LONG_MAX ((long)(~0UL>>1)) +#define LONG_MIN (-LONG_MAX - 1) +#define ULONG_MAX (~0UL) #endif diff --git a/components/libc/compilers/minilibc/stdio.h b/components/libc/compilers/minilibc/stdio.h index 678682cf5e..7c29ef011f 100644 --- a/components/libc/compilers/minilibc/stdio.h +++ b/components/libc/compilers/minilibc/stdio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -10,16 +10,16 @@ #define __STDIO_H__ #define BUFSIZ 128 -#define EOF (-1) +#define EOF (-1) #ifndef SEEK_SET -#define SEEK_SET 0 /* set file offset to offset */ +#define SEEK_SET 0 /* set file offset to offset */ #endif #ifndef SEEK_CUR -#define SEEK_CUR 1 /* set file offset to current plus offset */ +#define SEEK_CUR 1 /* set file offset to current plus offset */ #endif #ifndef SEEK_END -#define SEEK_END 2 /* set file offset to EOF plus offset */ +#define SEEK_END 2 /* set file offset to EOF plus offset */ #endif #endif diff --git a/components/libc/compilers/minilibc/stdlib.c b/components/libc/compilers/minilibc/stdlib.c index 8154ec5b8b..2bbad75fea 100644 --- a/components/libc/compilers/minilibc/stdlib.c +++ b/components/libc/compilers/minilibc/stdlib.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,60 +15,60 @@ int atoi(const char* s) { - long int v=0; - int sign=1; - while ( *s == ' ' || (unsigned int)(*s - 9) < 5u) s++; - switch (*s) - { - case '-': - sign=-1; - case '+': - ++s; - } - while ((unsigned int) (*s - '0') < 10u) - { - v=v*10+*s-'0'; - ++s; - } - return sign==-1?-v:v; + long int v=0; + int sign=1; + while ( *s == ' ' || (unsigned int)(*s - 9) < 5u) s++; + switch (*s) + { + case '-': + sign=-1; + case '+': + ++s; + } + while ((unsigned int) (*s - '0') < 10u) + { + v=v*10+*s-'0'; + ++s; + } + return sign==-1?-v:v; } -long int atol(const char* s) +long int atol(const char* s) { - long int v=0; - int sign=0; - while ( *s == ' ' || (unsigned int)(*s - 9) < 5u) ++s; - switch (*s) - { - case '-': sign=-1; - case '+': ++s; - } - while ((unsigned int) (*s - '0') < 10u) - { - v=v*10+*s-'0'; ++s; - } - return sign?-v:v; + long int v=0; + int sign=0; + while ( *s == ' ' || (unsigned int)(*s - 9) < 5u) ++s; + switch (*s) + { + case '-': sign=-1; + case '+': ++s; + } + while ((unsigned int) (*s - '0') < 10u) + { + v=v*10+*s-'0'; ++s; + } + return sign?-v:v; } #ifdef RT_USING_HEAP void *malloc(size_t size) { - return rt_malloc(size); + return rt_malloc(size); } void free(void *ptr) { - rt_free(ptr); + rt_free(ptr); } void *realloc(void *ptr, size_t size) { - return rt_realloc(ptr, size); + return rt_realloc(ptr, size); } void *calloc(size_t nelem, size_t elsize) { - return rt_calloc(nelem, elsize); + return rt_calloc(nelem, elsize); } #endif diff --git a/components/libc/compilers/minilibc/stdlib.h b/components/libc/compilers/minilibc/stdlib.h index d57d95b64d..96d3354099 100644 --- a/components/libc/compilers/minilibc/stdlib.h +++ b/components/libc/compilers/minilibc/stdlib.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/minilibc/string.c b/components/libc/compilers/minilibc/string.c index 1ab7c0509f..4eb9cc3a42 100644 --- a/components/libc/compilers/minilibc/string.c +++ b/components/libc/compilers/minilibc/string.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -21,44 +21,44 @@ /* there is no strcpy and strcmp implementation in RT-Thread */ char *strcpy(char *dest, const char *src) { - return (char *)rt_strncpy(dest, src, rt_strlen(src) + 1); + return (char *)rt_strncpy(dest, src, rt_strlen(src) + 1); } char *strncpy(char *dest, const char *src, size_t siz) { - return (char *)rt_strncpy(dest, src, siz); + return (char *)rt_strncpy(dest, src, siz); } size_t strlcpy(char *dst, const char *src, size_t siz) { - register char *d = dst; - register const char *s = src; - register size_t n = siz; - - /* Copy as many bytes as will fit */ - if (n != 0 && --n != 0) - { - do - { - if ((*d++ = *s++) == 0) break; - } while (--n != 0); - } - - /* Not enough room in dst, add NUL and traverse rest of src */ - if (n == 0) - { - if (siz != 0) *d = '\0'; /* NUL-terminate dst */ - while (*s++) ; - } - - return(s - src - 1); /* count does not include NUL */ + register char *d = dst; + register const char *s = src; + register size_t n = siz; + + /* Copy as many bytes as will fit */ + if (n != 0 && --n != 0) + { + do + { + if ((*d++ = *s++) == 0) break; + } while (--n != 0); + } + + /* Not enough room in dst, add NUL and traverse rest of src */ + if (n == 0) + { + if (siz != 0) *d = '\0'; /* NUL-terminate dst */ + while (*s++) ; + } + + return(s - src - 1); /* count does not include NUL */ } int strcmp (const char *s1, const char *s2) { - while (*s1 && *s1 == *s2) - s1++, s2++; - return (*s1 - *s2); + while (*s1 && *s1 == *s2) + s1++, s2++; + return (*s1 - *s2); } /** @@ -69,87 +69,87 @@ int strcmp (const char *s1, const char *s2) */ int strncmp(const char *cs,const char *ct, size_t count) { - register signed char __res = 0; + register signed char __res = 0; - while (count) { - if ((__res = *cs - *ct++) != 0 || !*cs++) - break; - count--; - } + while (count) { + if ((__res = *cs - *ct++) != 0 || !*cs++) + break; + count--; + } - return __res; + return __res; } char *strcat(char * dest, const char * src) { - char *tmp = dest; + char *tmp = dest; - while (*dest) - dest++; - while ((*dest++ = *src++) != '\0') - ; + while (*dest) + dest++; + while ((*dest++ = *src++) != '\0') + ; - return tmp; + return tmp; } char *strncat(char *dest, const char *src, size_t count) { - char *tmp = dest; - - if (count) { - while (*dest) - dest++; - while ((*dest++ = *src++)) { - if (--count == 0) { - *dest = '\0'; - break; - } - } - } - - return tmp; + char *tmp = dest; + + if (count) { + while (*dest) + dest++; + while ((*dest++ = *src++)) { + if (--count == 0) { + *dest = '\0'; + break; + } + } + } + + return tmp; } -char *strrchr(const char *t, int c) +char *strrchr(const char *t, int c) { - register char ch; - register const char *l=0; - - ch = c; - for (;;) - { - if (*t == ch) l=t; - if (!*t) return (char*)l; - ++t; - } - - return (char*)l; + register char ch; + register const char *l=0; + + ch = c; + for (;;) + { + if (*t == ch) l=t; + if (!*t) return (char*)l; + ++t; + } + + return (char*)l; } int strncasecmp ( const char* s1, const char* s2, size_t len ) { - register unsigned int x2; - register unsigned int x1; - register const char* end = s1 + len; + register unsigned int x2; + register unsigned int x1; + register const char* end = s1 + len; - while (1) - { - if ((s1 >= end) ) - return 0; + while (1) + { + if ((s1 >= end) ) + return 0; - x2 = *s2 - 'A'; if ((x2 < 26u)) x2 += 32; - x1 = *s1 - 'A'; if ((x1 < 26u)) x1 += 32; - s1++; s2++; + x2 = *s2 - 'A'; if ((x2 < 26u)) x2 += 32; + x1 = *s1 - 'A'; if ((x1 < 26u)) x1 += 32; + s1++; s2++; - if (x2 != x1) - break; + if (x2 != x1) + break; - if (x1 == (unsigned int)-'A') - break; - } + if (x1 == (unsigned int)-'A') + break; + } - return x1 - x2; + return x1 - x2; } /* private function */ @@ -157,50 +157,50 @@ int strncasecmp ( const char* s1, const char* s2, size_t len ) rt_inline int divide(int *n, int base) { - rt_int32_t res; - - /* optimized for processor which does not support divide instructions. */ - if (base == 10) - { - res = ((int)*n) % 10U; - *n = ((int)*n) / 10U; - } - else - { - res = ((int)*n) % 16U; - *n = ((int)*n) / 16U; - } - - return res; + rt_int32_t res; + + /* optimized for processor which does not support divide instructions. */ + if (base == 10) + { + res = ((int)*n) % 10U; + *n = ((int)*n) / 10U; + } + else + { + res = ((int)*n) % 16U; + *n = ((int)*n) / 16U; + } + + return res; } rt_inline int skip_atoi(const char **s) { - register int i=0; - while (isdigit(**s)) i = i*10 + *((*s)++) - '0'; + register int i=0; + while (isdigit(**s)) i = i*10 + *((*s)++) - '0'; - return i; + return i; } unsigned char _ctype[] = { -_C,_C,_C,_C,_C,_C,_C,_C, /* 0-7 */ -_C,_C|_S,_C|_S,_C|_S,_C|_S,_C|_S,_C,_C, /* 8-15 */ -_C,_C,_C,_C,_C,_C,_C,_C, /* 16-23 */ -_C,_C,_C,_C,_C,_C,_C,_C, /* 24-31 */ -_S|_SP,_P,_P,_P,_P,_P,_P,_P, /* 32-39 */ -_P,_P,_P,_P,_P,_P,_P,_P, /* 40-47 */ -_D,_D,_D,_D,_D,_D,_D,_D, /* 48-55 */ -_D,_D,_P,_P,_P,_P,_P,_P, /* 56-63 */ -_P,_U|_X,_U|_X,_U|_X,_U|_X,_U|_X,_U|_X,_U, /* 64-71 */ -_U,_U,_U,_U,_U,_U,_U,_U, /* 72-79 */ -_U,_U,_U,_U,_U,_U,_U,_U, /* 80-87 */ -_U,_U,_U,_P,_P,_P,_P,_P, /* 88-95 */ -_P,_L|_X,_L|_X,_L|_X,_L|_X,_L|_X,_L|_X,_L, /* 96-103 */ -_L,_L,_L,_L,_L,_L,_L,_L, /* 104-111 */ -_L,_L,_L,_L,_L,_L,_L,_L, /* 112-119 */ -_L,_L,_L,_P,_P,_P,_P,_C, /* 120-127 */ -0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 128-143 */ -0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 144-159 */ +_C,_C,_C,_C,_C,_C,_C,_C, /* 0-7 */ +_C,_C|_S,_C|_S,_C|_S,_C|_S,_C|_S,_C,_C, /* 8-15 */ +_C,_C,_C,_C,_C,_C,_C,_C, /* 16-23 */ +_C,_C,_C,_C,_C,_C,_C,_C, /* 24-31 */ +_S|_SP,_P,_P,_P,_P,_P,_P,_P, /* 32-39 */ +_P,_P,_P,_P,_P,_P,_P,_P, /* 40-47 */ +_D,_D,_D,_D,_D,_D,_D,_D, /* 48-55 */ +_D,_D,_P,_P,_P,_P,_P,_P, /* 56-63 */ +_P,_U|_X,_U|_X,_U|_X,_U|_X,_U|_X,_U|_X,_U, /* 64-71 */ +_U,_U,_U,_U,_U,_U,_U,_U, /* 72-79 */ +_U,_U,_U,_U,_U,_U,_U,_U, /* 80-87 */ +_U,_U,_U,_P,_P,_P,_P,_P, /* 88-95 */ +_P,_L|_X,_L|_X,_L|_X,_L|_X,_L|_X,_L|_X,_L, /* 96-103 */ +_L,_L,_L,_L,_L,_L,_L,_L, /* 104-111 */ +_L,_L,_L,_L,_L,_L,_L,_L, /* 112-119 */ +_L,_L,_L,_P,_P,_P,_P,_C, /* 120-127 */ +0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 128-143 */ +0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 144-159 */ _S|_SP,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P, /* 160-175 */ _P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P, /* 176-191 */ _U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U, /* 192-207 */ @@ -210,42 +210,42 @@ _L,_L,_L,_L,_L,_L,_L,_P,_L,_L,_L,_L,_L,_L,_L,_L}; /* 240-255 */ #define __ismask(x) (_ctype[(int)(unsigned char)(x)]) -#define isalnum(c) ((__ismask(c)&(_U|_L|_D)) != 0) -#define isalpha(c) ((__ismask(c)&(_U|_L)) != 0) -#define iscntrl(c) ((__ismask(c)&(_C)) != 0) -#define isgraph(c) ((__ismask(c)&(_P|_U|_L|_D)) != 0) -#define islower(c) ((__ismask(c)&(_L)) != 0) -#define isprint(c) ((__ismask(c)&(_P|_U|_L|_D|_SP)) != 0) -#define ispunct(c) ((__ismask(c)&(_P)) != 0) -#define isspace(c) ((__ismask(c)&(_S)) != 0) -#define isupper(c) ((__ismask(c)&(_U)) != 0) -#define isxdigit(c) ((__ismask(c)&(_D|_X)) != 0) +#define isalnum(c) ((__ismask(c)&(_U|_L|_D)) != 0) +#define isalpha(c) ((__ismask(c)&(_U|_L)) != 0) +#define iscntrl(c) ((__ismask(c)&(_C)) != 0) +#define isgraph(c) ((__ismask(c)&(_P|_U|_L|_D)) != 0) +#define islower(c) ((__ismask(c)&(_L)) != 0) +#define isprint(c) ((__ismask(c)&(_P|_U|_L|_D|_SP)) != 0) +#define ispunct(c) ((__ismask(c)&(_P)) != 0) +#define isspace(c) ((__ismask(c)&(_S)) != 0) +#define isupper(c) ((__ismask(c)&(_U)) != 0) +#define isxdigit(c) ((__ismask(c)&(_D|_X)) != 0) #define isascii(c) (((unsigned char)(c))<=0x7f) #define toascii(c) (((unsigned char)(c))&0x7f) static inline unsigned char __tolower(unsigned char c) { - if (isupper(c)) - c -= 'A'-'a'; - return c; + if (isupper(c)) + c -= 'A'-'a'; + return c; } static inline unsigned char __toupper(unsigned char c) { - if (islower(c)) - c -= 'a'-'A'; - return c; + if (islower(c)) + c -= 'a'-'A'; + return c; } -int tolower(int c) +int tolower(int c) { - return __tolower(c); + return __tolower(c); } int toupper(int c) { - return __toupper(c); + return __toupper(c); } /** @@ -256,30 +256,30 @@ int toupper(int c) */ unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base) { - unsigned long result = 0,value; - - if (!base) { - base = 10; - if (*cp == '0') { - base = 8; - cp++; - if ((toupper(*cp) == 'X') && isxdigit(cp[1])) { - cp++; - base = 16; - } - } - } else if (base == 16) { - if (cp[0] == '0' && toupper(cp[1]) == 'X') - cp += 2; - } - while (isxdigit(*cp) && - (value = isdigit(*cp) ? *cp-'0' : toupper(*cp)-'A'+10) < base) { - result = result*base + value; - cp++; - } - if (endp) - *endp = (char *)cp; - return result; + unsigned long result = 0,value; + + if (!base) { + base = 10; + if (*cp == '0') { + base = 8; + cp++; + if ((toupper(*cp) == 'X') && isxdigit(cp[1])) { + cp++; + base = 16; + } + } + } else if (base == 16) { + if (cp[0] == '0' && toupper(cp[1]) == 'X') + cp += 2; + } + while (isxdigit(*cp) && + (value = isdigit(*cp) ? *cp-'0' : toupper(*cp)-'A'+10) < base) { + result = result*base + value; + cp++; + } + if (endp) + *endp = (char *)cp; + return result; } /** @@ -290,9 +290,9 @@ unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base) */ long simple_strtol(const char *cp,char **endp,unsigned int base) { - if(*cp=='-') - return -simple_strtoul(cp+1,endp,base); - return simple_strtoul(cp,endp,base); + if(*cp=='-') + return -simple_strtoul(cp+1,endp,base); + return simple_strtoul(cp,endp,base); } /** @@ -303,30 +303,30 @@ long simple_strtol(const char *cp,char **endp,unsigned int base) */ unsigned long long simple_strtoull(const char *cp,char **endp,unsigned int base) { - unsigned long long result = 0, value; - - if (*cp == '0') { - cp++; - if ((toupper(*cp) == 'X') && isxdigit (cp[1])) { - base = 16; - cp++; - } - if (!base) { - base = 8; - } - } - if (!base) { - base = 10; - } - while (isxdigit (*cp) && (value = isdigit (*cp) - ? *cp - '0' - : (islower (*cp) ? toupper (*cp) : *cp) - 'A' + 10) < base) { - result = result * base + value; - cp++; - } - if (endp) - *endp = (char *) cp; - return result; + unsigned long long result = 0, value; + + if (*cp == '0') { + cp++; + if ((toupper(*cp) == 'X') && isxdigit (cp[1])) { + base = 16; + cp++; + } + if (!base) { + base = 8; + } + } + if (!base) { + base = 10; + } + while (isxdigit (*cp) && (value = isdigit (*cp) + ? *cp - '0' + : (islower (*cp) ? toupper (*cp) : *cp) - 'A' + 10) < base) { + result = result * base + value; + cp++; + } + if (endp) + *endp = (char *) cp; + return result; } /** @@ -337,284 +337,284 @@ unsigned long long simple_strtoull(const char *cp,char **endp,unsigned int base) */ long long simple_strtoll(const char *cp,char **endp,unsigned int base) { - if(*cp=='-') - return -simple_strtoull(cp+1,endp,base); - return simple_strtoull(cp,endp,base); + if(*cp=='-') + return -simple_strtoull(cp+1,endp,base); + return simple_strtoull(cp,endp,base); } /** * vsscanf - Unformat a buffer into a list of arguments - * @buf: input buffer - * @fmt: format of buffer - * @args: arguments + * @buf: input buffer + * @fmt: format of buffer + * @args: arguments */ int vsscanf(const char * buf, const char * fmt, va_list args) { - const char *str = buf; - char *next; - int num = 0; - int qualifier; - int base; - int field_width = -1; - int is_sign = 0; - - while(*fmt && *str) { - /* skip any white space in format */ - /* white space in format matchs any amount of - * white space, including none, in the input. - */ - if (isspace(*fmt)) { - while (isspace(*fmt)) - ++fmt; - while (isspace(*str)) - ++str; - } - - /* anything that is not a conversion must match exactly */ - if (*fmt != '%' && *fmt) { - if (*fmt++ != *str++) - break; - continue; - } - - if (!*fmt) - break; - ++fmt; - - /* skip this conversion. - * advance both strings to next white space - */ - if (*fmt == '*') { - while (!isspace(*fmt) && *fmt) - fmt++; - while (!isspace(*str) && *str) - str++; - continue; - } - - /* get field width */ - if (isdigit(*fmt)) - field_width = skip_atoi(&fmt); - - /* get conversion qualifier */ - qualifier = -1; - if (*fmt == 'h' || *fmt == 'l' || *fmt == 'L' || *fmt == 'Z') { - qualifier = *fmt; - fmt++; - } - base = 10; - is_sign = 0; - - if (!*fmt || !*str) - break; - - switch(*fmt++) { - case 'c': - { - char *s = (char *) va_arg(args,char*); - if (field_width == -1) - field_width = 1; - do { - *s++ = *str++; - } while(field_width-- > 0 && *str); - num++; - } - continue; - case 's': - { - char *s = (char *) va_arg(args, char *); - if(field_width == -1) - field_width = INT_MAX; - /* first, skip leading white space in buffer */ - while (isspace(*str)) - str++; - - /* now copy until next white space */ - while (*str && !isspace(*str) && field_width--) { - *s++ = *str++; - } - *s = '\0'; - num++; - } - continue; - case 'n': - /* return number of characters read so far */ - { - int *i = (int *)va_arg(args,int*); - *i = str - buf; - } - continue; - case 'o': - base = 8; - break; - case 'x': - case 'X': - base = 16; - break; - case 'd': - case 'i': - is_sign = 1; - case 'u': - break; - case '%': - /* looking for '%' in str */ - if (*str++ != '%') - return num; - continue; - default: - /* invalid format; stop here */ - return num; - } - - /* have some sort of integer conversion. - * first, skip white space in buffer. - */ - while (isspace(*str)) - str++; - - if (!*str || !isdigit(*str)) - break; - - switch(qualifier) { - case 'h': - if (is_sign) { - short *s = (short *) va_arg(args,short *); - *s = (short) simple_strtol(str,&next,base); - } else { - unsigned short *s = (unsigned short *) va_arg(args, unsigned short *); - *s = (unsigned short) simple_strtoul(str, &next, base); - } - break; - case 'l': - if (is_sign) { - long *l = (long *) va_arg(args,long *); - *l = simple_strtol(str,&next,base); - } else { - unsigned long *l = (unsigned long*) va_arg(args,unsigned long*); - *l = simple_strtoul(str,&next,base); - } - break; - case 'L': - if (is_sign) { - long long *l = (long long*) va_arg(args,long long *); - *l = simple_strtoll(str,&next,base); - } else { - unsigned long long *l = (unsigned long long*) va_arg(args,unsigned long long*); - *l = simple_strtoull(str,&next,base); - } - break; - case 'Z': - { - unsigned long *s = (unsigned long*) va_arg(args,unsigned long*); - *s = (unsigned long) simple_strtoul(str,&next,base); - } - break; - default: - if (is_sign) { - int *i = (int *) va_arg(args, int*); - *i = (int) simple_strtol(str,&next,base); - } else { - unsigned int *i = (unsigned int*) va_arg(args, unsigned int*); - *i = (unsigned int) simple_strtoul(str,&next,base); - } - break; - } - num++; - - if (!next) - break; - str = next; - } - return num; + const char *str = buf; + char *next; + int num = 0; + int qualifier; + int base; + int field_width = -1; + int is_sign = 0; + + while(*fmt && *str) { + /* skip any white space in format */ + /* white space in format matchs any amount of + * white space, including none, in the input. + */ + if (isspace(*fmt)) { + while (isspace(*fmt)) + ++fmt; + while (isspace(*str)) + ++str; + } + + /* anything that is not a conversion must match exactly */ + if (*fmt != '%' && *fmt) { + if (*fmt++ != *str++) + break; + continue; + } + + if (!*fmt) + break; + ++fmt; + + /* skip this conversion. + * advance both strings to next white space + */ + if (*fmt == '*') { + while (!isspace(*fmt) && *fmt) + fmt++; + while (!isspace(*str) && *str) + str++; + continue; + } + + /* get field width */ + if (isdigit(*fmt)) + field_width = skip_atoi(&fmt); + + /* get conversion qualifier */ + qualifier = -1; + if (*fmt == 'h' || *fmt == 'l' || *fmt == 'L' || *fmt == 'Z') { + qualifier = *fmt; + fmt++; + } + base = 10; + is_sign = 0; + + if (!*fmt || !*str) + break; + + switch(*fmt++) { + case 'c': + { + char *s = (char *) va_arg(args,char*); + if (field_width == -1) + field_width = 1; + do { + *s++ = *str++; + } while(field_width-- > 0 && *str); + num++; + } + continue; + case 's': + { + char *s = (char *) va_arg(args, char *); + if(field_width == -1) + field_width = INT_MAX; + /* first, skip leading white space in buffer */ + while (isspace(*str)) + str++; + + /* now copy until next white space */ + while (*str && !isspace(*str) && field_width--) { + *s++ = *str++; + } + *s = '\0'; + num++; + } + continue; + case 'n': + /* return number of characters read so far */ + { + int *i = (int *)va_arg(args,int*); + *i = str - buf; + } + continue; + case 'o': + base = 8; + break; + case 'x': + case 'X': + base = 16; + break; + case 'd': + case 'i': + is_sign = 1; + case 'u': + break; + case '%': + /* looking for '%' in str */ + if (*str++ != '%') + return num; + continue; + default: + /* invalid format; stop here */ + return num; + } + + /* have some sort of integer conversion. + * first, skip white space in buffer. + */ + while (isspace(*str)) + str++; + + if (!*str || !isdigit(*str)) + break; + + switch(qualifier) { + case 'h': + if (is_sign) { + short *s = (short *) va_arg(args,short *); + *s = (short) simple_strtol(str,&next,base); + } else { + unsigned short *s = (unsigned short *) va_arg(args, unsigned short *); + *s = (unsigned short) simple_strtoul(str, &next, base); + } + break; + case 'l': + if (is_sign) { + long *l = (long *) va_arg(args,long *); + *l = simple_strtol(str,&next,base); + } else { + unsigned long *l = (unsigned long*) va_arg(args,unsigned long*); + *l = simple_strtoul(str,&next,base); + } + break; + case 'L': + if (is_sign) { + long long *l = (long long*) va_arg(args,long long *); + *l = simple_strtoll(str,&next,base); + } else { + unsigned long long *l = (unsigned long long*) va_arg(args,unsigned long long*); + *l = simple_strtoull(str,&next,base); + } + break; + case 'Z': + { + unsigned long *s = (unsigned long*) va_arg(args,unsigned long*); + *s = (unsigned long) simple_strtoul(str,&next,base); + } + break; + default: + if (is_sign) { + int *i = (int *) va_arg(args, int*); + *i = (int) simple_strtol(str,&next,base); + } else { + unsigned int *i = (unsigned int*) va_arg(args, unsigned int*); + *i = (unsigned int) simple_strtoul(str,&next,base); + } + break; + } + num++; + + if (!next) + break; + str = next; + } + return num; } /** * sscanf - Unformat a buffer into a list of arguments - * @buf: input buffer - * @fmt: formatting of buffer - * @...: resulting arguments + * @buf: input buffer + * @fmt: formatting of buffer + * @...: resulting arguments */ int sscanf(const char * buf, const char * fmt, ...) { - va_list args; - int i; - - va_start(args,fmt); - i = vsscanf(buf,fmt,args); - va_end(args); - - return i; + va_list args; + int i; + + va_start(args,fmt); + i = vsscanf(buf,fmt,args); + va_end(args); + + return i; } size_t strspn(const char *s, const char *accept) { - size_t l=0; - int a=1,i, al=strlen(accept); - - while((a)&&(*s)) - { - for(a=i=0;(!a)&&(i terminate it */ - } - *ptrptr=s; - return tmp; + char*tmp=0; + + if (s==0) s=*ptrptr; + s += strspn(s,delim); /* overread leading delimiter */ + if (*s) + { + tmp=s; + s+=strcspn(s,delim); + + if (*s) *s++=0; /* not the end ? => terminate it */ + } + *ptrptr=s; + return tmp; } char *strtok(char *s, const char *delim) { - static char *strtok_pos; - return strtok_r(s,delim,&strtok_pos); + static char *strtok_pos; + return strtok_r(s,delim,&strtok_pos); } char *strchr(const char *s1, int i) { - const unsigned char *s = (const unsigned char *)s1; - unsigned char c = (unsigned int)i; + const unsigned char *s = (const unsigned char *)s1; + unsigned char c = (unsigned int)i; - while (*s && *s != c) - { - s++; - } + while (*s && *s != c) + { + s++; + } - if (*s != c) - { - s = NULL; - } + if (*s != c) + { + s = NULL; + } - return (char *) s; + return (char *) s; } long strtol(const char *str, char **endptr, int base) diff --git a/components/libc/compilers/minilibc/string.h b/components/libc/compilers/minilibc/string.h index 45524c7764..6ccbc79fe9 100644 --- a/components/libc/compilers/minilibc/string.h +++ b/components/libc/compilers/minilibc/string.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,22 +16,22 @@ /* replace for standard string library */ #if !defined (RT_USING_NEWLIB) && defined (RT_USING_MINILIBC) -#define ZEROPAD (1 << 0) /* pad with zero */ -#define SIGN (1 << 1) /* unsigned/signed long */ -#define PLUS (1 << 2) /* show plus */ -#define SPACE (1 << 3) /* space if plus */ -#define LEFT (1 << 4) /* left justified */ -#define SPECIAL (1 << 5) /* 0x */ -#define LARGE (1 << 6) /* use 'ABCDEF' instead of 'abcdef' */ +#define ZEROPAD (1 << 0) /* pad with zero */ +#define SIGN (1 << 1) /* unsigned/signed long */ +#define PLUS (1 << 2) /* show plus */ +#define SPACE (1 << 3) /* space if plus */ +#define LEFT (1 << 4) /* left justified */ +#define SPECIAL (1 << 5) /* 0x */ +#define LARGE (1 << 6) /* use 'ABCDEF' instead of 'abcdef' */ -#define _U 0x01 /* upper */ -#define _L 0x02 /* lower */ -#define _D 0x04 /* digit */ -#define _C 0x08 /* cntrl */ -#define _P 0x10 /* punct */ -#define _S 0x20 /* white space (space/lf/tab) */ -#define _X 0x40 /* hex digit */ -#define _SP 0x80 /* hard space (0x20) */ +#define _U 0x01 /* upper */ +#define _L 0x02 /* lower */ +#define _D 0x04 /* digit */ +#define _C 0x08 /* cntrl */ +#define _P 0x10 /* punct */ +#define _S 0x20 /* white space (space/lf/tab) */ +#define _X 0x40 /* hex digit */ +#define _SP 0x80 /* hard space (0x20) */ void* memset(void *s, int c, size_t n); void* memcpy(void *dest, const void *src, size_t n); diff --git a/components/libc/compilers/minilibc/sys/mman.h b/components/libc/compilers/minilibc/sys/mman.h index 8c61b32b7c..6a260ccd70 100644 --- a/components/libc/compilers/minilibc/sys/mman.h +++ b/components/libc/compilers/minilibc/sys/mman.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/minilibc/sys/stat.h b/components/libc/compilers/minilibc/sys/stat.h index 65db477a4a..8867b84a1b 100644 --- a/components/libc/compilers/minilibc/sys/stat.h +++ b/components/libc/compilers/minilibc/sys/stat.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,31 +14,31 @@ #ifdef RT_USING_DFS #include #else -#define _FREAD 0x0001 /* read enabled */ -#define _FWRITE 0x0002 /* write enabled */ -#define _FAPPEND 0x0008 /* append (writes guaranteed at the end) */ -#define _FMARK 0x0010 /* internal; mark during gc() */ -#define _FDEFER 0x0020 /* internal; defer for next gc pass */ -#define _FASYNC 0x0040 /* signal pgrp when data ready */ -#define _FSHLOCK 0x0080 /* BSD flock() shared lock present */ -#define _FEXLOCK 0x0100 /* BSD flock() exclusive lock present */ -#define _FCREAT 0x0200 /* open with file create */ -#define _FTRUNC 0x0400 /* open with truncation */ -#define _FEXCL 0x0800 /* error on open if file exists */ -#define _FNBIO 0x1000 /* non blocking I/O (sys5 style) */ -#define _FSYNC 0x2000 /* do all writes synchronously */ -#define _FNONBLOCK 0x4000 /* non blocking I/O (POSIX style) */ -#define _FNDELAY _FNONBLOCK /* non blocking I/O (4.2 style) */ -#define _FNOCTTY 0x8000 /* don't assign a ctty on this open */ +#define _FREAD 0x0001 /* read enabled */ +#define _FWRITE 0x0002 /* write enabled */ +#define _FAPPEND 0x0008 /* append (writes guaranteed at the end) */ +#define _FMARK 0x0010 /* internal; mark during gc() */ +#define _FDEFER 0x0020 /* internal; defer for next gc pass */ +#define _FASYNC 0x0040 /* signal pgrp when data ready */ +#define _FSHLOCK 0x0080 /* BSD flock() shared lock present */ +#define _FEXLOCK 0x0100 /* BSD flock() exclusive lock present */ +#define _FCREAT 0x0200 /* open with file create */ +#define _FTRUNC 0x0400 /* open with truncation */ +#define _FEXCL 0x0800 /* error on open if file exists */ +#define _FNBIO 0x1000 /* non blocking I/O (sys5 style) */ +#define _FSYNC 0x2000 /* do all writes synchronously */ +#define _FNONBLOCK 0x4000 /* non blocking I/O (POSIX style) */ +#define _FNDELAY _FNONBLOCK /* non blocking I/O (4.2 style) */ +#define _FNOCTTY 0x8000 /* don't assign a ctty on this open */ -#define O_RDONLY 0 /* +1 == FREAD */ -#define O_WRONLY 1 /* +1 == FWRITE */ -#define O_RDWR 2 /* +1 == FREAD|FWRITE */ -#define O_APPEND _FAPPEND -#define O_CREAT _FCREAT -#define O_TRUNC _FTRUNC -#define O_EXCL _FEXCL -#define O_SYNC _FSYNC +#define O_RDONLY 0 /* +1 == FREAD */ +#define O_WRONLY 1 /* +1 == FWRITE */ +#define O_RDWR 2 /* +1 == FREAD|FWRITE */ +#define O_APPEND _FAPPEND +#define O_CREAT _FCREAT +#define O_TRUNC _FTRUNC +#define O_EXCL _FEXCL +#define O_SYNC _FSYNC #endif #endif diff --git a/components/libc/compilers/minilibc/sys/time.h b/components/libc/compilers/minilibc/sys/time.h index 22a93f5c9d..aa9e6d704e 100644 --- a/components/libc/compilers/minilibc/sys/time.h +++ b/components/libc/compilers/minilibc/sys/time.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,36 +17,36 @@ typedef long time_t; * and used in other calls. */ struct timeval { - long tv_sec; /* seconds */ - long tv_usec; /* and microseconds */ + long tv_sec; /* seconds */ + long tv_usec; /* and microseconds */ }; /* * Structure defined by POSIX.1b to be like a timeval. */ struct timespec { - time_t tv_sec; /* seconds */ - long tv_nsec; /* and nanoseconds */ + time_t tv_sec; /* seconds */ + long tv_nsec; /* and nanoseconds */ }; struct timezone { - int tz_minuteswest; /* minutes west of Greenwich */ - int tz_dsttime; /* type of dst correction */ + int tz_minuteswest; /* minutes west of Greenwich */ + int tz_dsttime; /* type of dst correction */ }; struct tm { - int tm_sec; /* Seconds. [0-60] (1 leap second) */ - int tm_min; /* Minutes. [0-59] */ - int tm_hour; /* Hours. [0-23] */ - int tm_mday; /* Day. [1-31] */ - int tm_mon; /* Month. [0-11] */ - int tm_year; /* Year - 1900. */ - int tm_wday; /* Day of week. [0-6] */ - int tm_yday; /* Days in year.[0-365] */ - int tm_isdst; /* DST. [-1/0/1]*/ - - long int tm_gmtoff; /* Seconds east of UTC. */ - const char *tm_zone; /* Timezone abbreviation. */ + int tm_sec; /* Seconds. [0-60] (1 leap second) */ + int tm_min; /* Minutes. [0-59] */ + int tm_hour; /* Hours. [0-23] */ + int tm_mday; /* Day. [1-31] */ + int tm_mon; /* Month. [0-11] */ + int tm_year; /* Year - 1900. */ + int tm_wday; /* Day of week. [0-6] */ + int tm_yday; /* Days in year.[0-365] */ + int tm_isdst; /* DST. [-1/0/1]*/ + + long int tm_gmtoff; /* Seconds east of UTC. */ + const char *tm_zone; /* Timezone abbreviation. */ }; int gettimeofday(struct timeval *tp, void *ignore); diff --git a/components/libc/compilers/minilibc/sys/types.h b/components/libc/compilers/minilibc/sys/types.h index 746235273c..5bed922a0a 100644 --- a/components/libc/compilers/minilibc/sys/types.h +++ b/components/libc/compilers/minilibc/sys/types.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -38,7 +38,7 @@ typedef int caddr_t; typedef unsigned int wint_t; typedef unsigned long useconds_t; -typedef unsigned long clock_t; /* clock() */ +typedef unsigned long clock_t; /* clock() */ #ifndef NULL #define NULL (0) diff --git a/components/libc/compilers/minilibc/time.c b/components/libc/compilers/minilibc/time.c index 25e8f0e310..3ac76c883f 100644 --- a/components/libc/compilers/minilibc/time.c +++ b/components/libc/compilers/minilibc/time.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/minilibc/time.h b/components/libc/compilers/minilibc/time.h index 09fc7d2e67..fba310fbe4 100644 --- a/components/libc/compilers/minilibc/time.h +++ b/components/libc/compilers/minilibc/time.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/newlib/libc.c b/components/libc/compilers/newlib/libc.c index 2234c36f98..9834a9a015 100644 --- a/components/libc/compilers/newlib/libc.c +++ b/components/libc/compilers/newlib/libc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -19,7 +19,7 @@ #include #endif -int _EXFUN(putenv,(char *__string)); +int _EXFUN(putenv,(char *__string)); int libc_system_init(void) { diff --git a/components/libc/compilers/newlib/libc.h b/components/libc/compilers/newlib/libc.h index fdf2ab4f60..bf294ac116 100644 --- a/components/libc/compilers/newlib/libc.h +++ b/components/libc/compilers/newlib/libc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,7 +16,7 @@ #include #ifndef _EXFUN -#define _EXFUN(name, proto) name proto +#define _EXFUN(name, proto) name proto #endif #define MILLISECOND_PER_SECOND 1000UL diff --git a/components/libc/compilers/newlib/libc_syms.c b/components/libc/compilers/newlib/libc_syms.c index b150c10fd6..f0882afcfc 100644 --- a/components/libc/compilers/newlib/libc_syms.c +++ b/components/libc/compilers/newlib/libc_syms.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/newlib/stdio.c b/components/libc/compilers/newlib/stdio.c index 233a447396..ce5bdb75cb 100644 --- a/components/libc/compilers/newlib/stdio.c +++ b/components/libc/compilers/newlib/stdio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,7 +15,7 @@ #define STDIO_DEVICE_NAME_MAX 32 -int _EXFUN(fileno, (FILE *)); +int _EXFUN(fileno, (FILE *)); static FILE* std_console = NULL; @@ -48,7 +48,7 @@ int libc_stdio_set_console(const char* device_name, int mode) { _GLOBAL_REENT->_stdin = std_console; } - else + else { _GLOBAL_REENT->_stdin = NULL; } diff --git a/components/libc/compilers/newlib/sys/dirent.h b/components/libc/compilers/newlib/sys/dirent.h index db8c0655a1..bfba586093 100644 --- a/components/libc/compilers/newlib/sys/dirent.h +++ b/components/libc/compilers/newlib/sys/dirent.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,36 +17,36 @@ */ /* File types */ -#define FT_REGULAR 0 /* regular file */ -#define FT_SOCKET 1 /* socket file */ -#define FT_DIRECTORY 2 /* directory */ -#define FT_USER 3 /* user defined */ +#define FT_REGULAR 0 /* regular file */ +#define FT_SOCKET 1 /* socket file */ +#define FT_DIRECTORY 2 /* directory */ +#define FT_USER 3 /* user defined */ -#define DT_UNKNOWN 0x00 -#define DT_REG 0x01 -#define DT_DIR 0x02 +#define DT_UNKNOWN 0x00 +#define DT_REG 0x01 +#define DT_DIR 0x02 #ifdef __cplusplus extern "C" { #endif #ifndef HAVE_DIR_STRUCTURE -typedef struct +typedef struct { - int fd; /* directory file */ - char buf[512]; - int num; - int cur; + int fd; /* directory file */ + char buf[512]; + int num; + int cur; } DIR; #endif #ifndef HAVE_DIRENT_STRUCTURE struct dirent { - rt_uint8_t d_type; /* The type of the file */ - rt_uint8_t d_namlen; /* The length of the not including the terminating null file name */ - rt_uint16_t d_reclen; /* length of this record */ - char d_name[256]; /* The null-terminated file name */ + rt_uint8_t d_type; /* The type of the file */ + rt_uint8_t d_namlen; /* The length of the not including the terminating null file name */ + rt_uint16_t d_reclen; /* length of this record */ + char d_name[256]; /* The null-terminated file name */ }; #endif diff --git a/components/libc/compilers/newlib/sys/mman.h b/components/libc/compilers/newlib/sys/mman.h index 8c61b32b7c..6a260ccd70 100644 --- a/components/libc/compilers/newlib/sys/mman.h +++ b/components/libc/compilers/newlib/sys/mman.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/newlib/sys/statfs.h b/components/libc/compilers/newlib/sys/statfs.h index 3c923a21f9..0996af9a18 100644 --- a/components/libc/compilers/newlib/sys/statfs.h +++ b/components/libc/compilers/newlib/sys/statfs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,9 +13,9 @@ struct statfs { - rt_size_t f_bsize; /* block size */ - rt_size_t f_blocks; /* total data blocks in file system */ - rt_size_t f_bfree; /* free blocks in file system */ + rt_size_t f_bsize; /* block size */ + rt_size_t f_blocks; /* total data blocks in file system */ + rt_size_t f_bfree; /* free blocks in file system */ }; #endif diff --git a/components/libc/compilers/newlib/sys/termios.h b/components/libc/compilers/newlib/sys/termios.h index ce95230e88..c4b42083c4 100644 --- a/components/libc/compilers/newlib/sys/termios.h +++ b/components/libc/compilers/newlib/sys/termios.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/compilers/newlib/syscalls.c b/components/libc/compilers/newlib/syscalls.c index 228fa0d140..754059fe2f 100644 --- a/components/libc/compilers/newlib/syscalls.c +++ b/components/libc/compilers/newlib/syscalls.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/libdl/arch/arm.c b/components/libc/libdl/arch/arm.c index a53c04f0bc..6a884bdb54 100644 --- a/components/libc/libdl/arch/arm.c +++ b/components/libc/libdl/arch/arm.c @@ -1,8 +1,8 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 - * + * * Change Logs: * Date Author Notes * 2018/08/29 Bernard first version diff --git a/components/libc/libdl/arch/x86.c b/components/libc/libdl/arch/x86.c index 16f2322fb4..e7ad714a03 100644 --- a/components/libc/libdl/arch/x86.c +++ b/components/libc/libdl/arch/x86.c @@ -1,8 +1,8 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 - * + * * Change Logs: * Date Author Notes * 2018/09/15 parai first version @@ -13,9 +13,9 @@ #ifdef __i386__ -#define R_X86_64_GLOB_DAT 6 /* Create GOT entry */ -#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */ -#define R_X86_64_RELATIVE 8 /* Adjust by program base */ +#define R_X86_64_GLOB_DAT 6 /* Create GOT entry */ +#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */ +#define R_X86_64_RELATIVE 8 /* Adjust by program base */ int dlmodule_relocate(struct rt_dlmodule *module, Elf32_Rel *rel, Elf32_Addr sym_val) { Elf32_Addr *where, tmp; diff --git a/components/libc/libdl/dlclose.c b/components/libc/libdl/dlclose.c index 1202e13f2c..876a1576c8 100644 --- a/components/libc/libdl/dlclose.c +++ b/components/libc/libdl/dlclose.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/libdl/dlelf.c b/components/libc/libdl/dlelf.c index 1265ffcb07..3a4e62ad9b 100644 --- a/components/libc/libdl/dlelf.c +++ b/components/libc/libdl/dlelf.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -172,7 +172,7 @@ rt_err_t dlmodule_load_shared_object(struct rt_dlmodule* module, void *module_pt rel ++; } - if (unsolved) + if (unsolved) return -RT_ERROR; } @@ -301,7 +301,7 @@ rt_err_t dlmodule_load_relocated_object(struct rt_dlmodule* module, void *module (rt_uint8_t *)elf_module + shdr[index].sh_offset, shdr[index].sh_size); rodata_addr = (rt_uint32_t)ptr; - LOG_D("load rodata 0x%x, size %d, rodata 0x%x", ptr, + LOG_D("load rodata 0x%x, size %d, rodata 0x%x", ptr, shdr[index].sh_size, *(rt_uint32_t *)data_addr); ptr += shdr[index].sh_size; } @@ -313,7 +313,7 @@ rt_err_t dlmodule_load_relocated_object(struct rt_dlmodule* module, void *module (rt_uint8_t *)elf_module + shdr[index].sh_offset, shdr[index].sh_size); data_addr = (rt_uint32_t)ptr; - LOG_D("load data 0x%x, size %d, data 0x%x", ptr, + LOG_D("load data 0x%x, size %d, data 0x%x", ptr, shdr[index].sh_size, *(rt_uint32_t *)data_addr); ptr += shdr[index].sh_size; } @@ -362,7 +362,7 @@ rt_err_t dlmodule_load_relocated_object(struct rt_dlmodule* module, void *module if (sym->st_shndx != STN_UNDEF) { Elf32_Addr addr = 0; - + if ((ELF_ST_TYPE(sym->st_info) == STT_SECTION) || (ELF_ST_TYPE(sym->st_info) == STT_OBJECT)) { diff --git a/components/libc/libdl/dlelf.h b/components/libc/libdl/dlelf.h index 014ebe85c8..ad9e2cdade 100644 --- a/components/libc/libdl/dlelf.h +++ b/components/libc/libdl/dlelf.h @@ -1,8 +1,8 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 - * + * * Change Logs: * Date Author Notes * 2018/08/29 Bernard first version diff --git a/components/libc/libdl/dlerror.c b/components/libc/libdl/dlerror.c index ad9b630e4c..de948eb16b 100644 --- a/components/libc/libdl/dlerror.c +++ b/components/libc/libdl/dlerror.c @@ -1,8 +1,8 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 - * + * * Change Logs: * Date Author Notes * 2010-11-17 yi.qiu first version @@ -13,6 +13,6 @@ const char *dlerror(void) { - return "TODO"; + return "TODO"; } RTM_EXPORT(dlerror) diff --git a/components/libc/libdl/dlfcn.h b/components/libc/libdl/dlfcn.h index 55273a41eb..f5c9063f2f 100644 --- a/components/libc/libdl/dlfcn.h +++ b/components/libc/libdl/dlfcn.h @@ -1,8 +1,8 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 - * + * * Change Logs: * Date Author Notes * 2010-11-17 yi.qiu first version diff --git a/components/libc/libdl/dlmodule.c b/components/libc/libdl/dlmodule.c index 21e070a106..5387bc4c0f 100644 --- a/components/libc/libdl/dlmodule.c +++ b/components/libc/libdl/dlmodule.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -547,7 +547,7 @@ struct rt_dlmodule* dlmodule_exec(const char* pgname, const char* cmd, int cmd_s if (module->priority > RT_THREAD_PRIORITY_MAX) module->priority = RT_THREAD_PRIORITY_MAX - 1; if (module->stack_size < 2048 || module->stack_size > (1024 * 32)) module->stack_size = 2048; - tid = rt_thread_create(module->parent.name, _dlmodule_thread_entry, (void*)module, + tid = rt_thread_create(module->parent.name, _dlmodule_thread_entry, (void*)module, module->stack_size, module->priority, 10); if (tid) { @@ -580,7 +580,7 @@ void dlmodule_exit(int ret_code) rt_enter_critical(); /* module is not running */ - if (module->stat != RT_DLMODULE_STAT_RUNNING) + if (module->stat != RT_DLMODULE_STAT_RUNNING) { /* restore scheduling */ rt_exit_critical(); diff --git a/components/libc/libdl/dlmodule.h b/components/libc/libdl/dlmodule.h index 4a4ead3303..688c0d4dfa 100644 --- a/components/libc/libdl/dlmodule.h +++ b/components/libc/libdl/dlmodule.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/libdl/dlopen.c b/components/libc/libdl/dlopen.c index a8202ec607..bcb57d78f0 100644 --- a/components/libc/libdl/dlopen.c +++ b/components/libc/libdl/dlopen.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -43,12 +43,12 @@ void* dlopen(const char *filename, int flags) /* find in module list */ module = dlmodule_find(fullpath); - if(module != RT_NULL) + if(module != RT_NULL) { rt_exit_critical(); module->nref++; } - else + else { rt_exit_critical(); module = dlmodule_load(fullpath); diff --git a/components/libc/libdl/dlsym.c b/components/libc/libdl/dlsym.c index ed0f183d83..f7c1c901fd 100644 --- a/components/libc/libdl/dlsym.c +++ b/components/libc/libdl/dlsym.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,7 +17,7 @@ void* dlsym(void *handle, const char* symbol) { int i; struct rt_dlmodule *module; - + RT_ASSERT(handle != RT_NULL); module = (struct rt_dlmodule *)handle; diff --git a/components/libc/mmap/posix_mmap.c b/components/libc/mmap/posix_mmap.c index a16ace8306..e68b82e640 100644 --- a/components/libc/mmap/posix_mmap.c +++ b/components/libc/mmap/posix_mmap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/pthreads/mqueue.c b/components/libc/pthreads/mqueue.c index 003b49b9a0..1af0ab2919 100644 --- a/components/libc/pthreads/mqueue.c +++ b/components/libc/pthreads/mqueue.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/pthreads/mqueue.h b/components/libc/pthreads/mqueue.h index 5cadde3ae8..5152bfad29 100644 --- a/components/libc/pthreads/mqueue.h +++ b/components/libc/pthreads/mqueue.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/pthreads/posix_types.h b/components/libc/pthreads/posix_types.h index ca20464bb5..f2d806cc9a 100644 --- a/components/libc/pthreads/posix_types.h +++ b/components/libc/pthreads/posix_types.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2013-12-23 Bernard Add the checking for ESHUTDOWN + * 2013-12-23 Bernard Add the checking for ESHUTDOWN */ #ifndef __POSIX_TYPES_H__ diff --git a/components/libc/pthreads/pthread.c b/components/libc/pthreads/pthread.c index 5d3bc0796a..eabc929728 100644 --- a/components/libc/pthreads/pthread.c +++ b/components/libc/pthreads/pthread.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -200,7 +200,7 @@ int pthread_create(pthread_t *pid, /* allocate posix thread data */ pth_id = _pthread_data_create(); - if (pth_id == PTHREAD_NUM_MAX) + if (pth_id == PTHREAD_NUM_MAX) { ret = ENOMEM; goto __exit; diff --git a/components/libc/pthreads/pthread.h b/components/libc/pthreads/pthread.h index 7bb72b726c..8639c1604b 100644 --- a/components/libc/pthreads/pthread.h +++ b/components/libc/pthreads/pthread.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -161,7 +161,7 @@ int pthread_attr_getguardsize(pthread_attr_t const *attr, size_t *guard_size); int pthread_attr_setscope(pthread_attr_t *attr, int scope); int pthread_attr_getscope(pthread_attr_t const *attr); int pthread_system_init(void); -int pthread_create (pthread_t *tid, const pthread_attr_t *attr, +int pthread_create (pthread_t *tid, const pthread_attr_t *attr, void *(*start) (void *), void *arg); int pthread_detach (pthread_t thread); diff --git a/components/libc/pthreads/pthread_attr.c b/components/libc/pthreads/pthread_attr.c index 2294599bf3..4aedf5a90d 100644 --- a/components/libc/pthreads/pthread_attr.c +++ b/components/libc/pthreads/pthread_attr.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,7 +16,7 @@ #define DEFAULT_STACK_SIZE 2048 #define DEFAULT_PRIORITY (RT_THREAD_PRIORITY_MAX/2 + RT_THREAD_PRIORITY_MAX/4) -const pthread_attr_t pthread_default_attr = +const pthread_attr_t pthread_default_attr = { 0, /* stack base */ DEFAULT_STACK_SIZE, /* stack size */ diff --git a/components/libc/pthreads/pthread_barrier.c b/components/libc/pthreads/pthread_barrier.c index d76fe7f13f..1a5b7fa3f9 100644 --- a/components/libc/pthreads/pthread_barrier.c +++ b/components/libc/pthreads/pthread_barrier.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/pthreads/pthread_cond.c b/components/libc/pthreads/pthread_cond.c index 38dc697469..59c271bf6e 100644 --- a/components/libc/pthreads/pthread_cond.c +++ b/components/libc/pthreads/pthread_cond.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -84,10 +84,10 @@ int pthread_cond_init(pthread_cond_t *cond, const pthread_condattr_t *attr) rt_snprintf(cond_name, sizeof(cond_name), "cond%02d", cond_num++); - if (attr == RT_NULL) /* use default value */ - cond->attr = PTHREAD_PROCESS_PRIVATE; - else - cond->attr = *attr; + if (attr == RT_NULL) /* use default value */ + cond->attr = PTHREAD_PROCESS_PRIVATE; + else + cond->attr = *attr; result = rt_sem_init(&cond->sem, cond_name, 0, RT_IPC_FLAG_FIFO); if (result != RT_EOK) diff --git a/components/libc/pthreads/pthread_internal.h b/components/libc/pthreads/pthread_internal.h index a6706ca091..24f24c8ce0 100644 --- a/components/libc/pthreads/pthread_internal.h +++ b/components/libc/pthreads/pthread_internal.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/pthreads/pthread_mutex.c b/components/libc/pthreads/pthread_mutex.c index 8f96531782..a681380b11 100644 --- a/components/libc/pthreads/pthread_mutex.c +++ b/components/libc/pthreads/pthread_mutex.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -211,7 +211,7 @@ int pthread_mutex_unlock(pthread_mutex_t *mutex) result = rt_mutex_release(&(mutex->lock)); if (result == RT_EOK) return 0; - + return EINVAL; } RTM_EXPORT(pthread_mutex_unlock); diff --git a/components/libc/pthreads/pthread_rwlock.c b/components/libc/pthreads/pthread_rwlock.c index 64a0e221b4..1c2fe19f5f 100644 --- a/components/libc/pthreads/pthread_rwlock.c +++ b/components/libc/pthreads/pthread_rwlock.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -60,7 +60,7 @@ int pthread_rwlock_init(pthread_rwlock_t *rwlock, pthread_mutex_init(&(rwlock->rw_mutex), NULL); pthread_cond_init(&(rwlock->rw_condreaders), NULL); pthread_cond_init(&(rwlock->rw_condwriters), NULL); - + rwlock->rw_nwaitwriters = 0; rwlock->rw_nwaitreaders = 0; rwlock->rw_refcount = 0; @@ -117,7 +117,7 @@ int pthread_rwlock_destroy (pthread_rwlock_t *rwlock) pthread_mutex_unlock(&rwlock->rw_mutex); if (result == 0) pthread_mutex_destroy(&rwlock->rw_mutex); - + return result; } RTM_EXPORT(pthread_rwlock_destroy); @@ -234,7 +234,7 @@ int pthread_rwlock_timedwrlock(pthread_rwlock_t *rwlock, result = pthread_cond_timedwait(&rwlock->rw_condwriters, &rwlock->rw_mutex, abstime); /* rw_mutex should have been taken again when returned from waiting */ rwlock->rw_nwaitwriters--; - + if (result != 0) break; } @@ -324,7 +324,7 @@ int pthread_rwlock_wrlock(pthread_rwlock_t *rwlock) result = pthread_cond_wait(&rwlock->rw_condwriters, &rwlock->rw_mutex); /* rw_mutex should have been taken again when returned from waiting */ rwlock->rw_nwaitwriters--; - + if (result != 0) break; } diff --git a/components/libc/pthreads/pthread_spin.c b/components/libc/pthreads/pthread_spin.c index b31f4f6393..3f3dc1593c 100644 --- a/components/libc/pthreads/pthread_spin.c +++ b/components/libc/pthreads/pthread_spin.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/pthreads/pthread_tls.c b/components/libc/pthreads/pthread_tls.c index 4b97d796d9..d48df7f2dd 100644 --- a/components/libc/pthreads/pthread_tls.c +++ b/components/libc/pthreads/pthread_tls.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/pthreads/sched.c b/components/libc/pthreads/sched.c index a1bf50985e..5f2a53c01f 100644 --- a/components/libc/pthreads/sched.c +++ b/components/libc/pthreads/sched.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/pthreads/sched.h b/components/libc/pthreads/sched.h index dbaf66edc2..07e2c0c6a8 100644 --- a/components/libc/pthreads/sched.h +++ b/components/libc/pthreads/sched.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/pthreads/semaphore.c b/components/libc/pthreads/semaphore.c index 2ed93e99b6..398cdf1f49 100644 --- a/components/libc/pthreads/semaphore.c +++ b/components/libc/pthreads/semaphore.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/pthreads/semaphore.h b/components/libc/pthreads/semaphore.h index d135ae9261..872226e385 100644 --- a/components/libc/pthreads/semaphore.h +++ b/components/libc/pthreads/semaphore.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/signal/posix_signal.c b/components/libc/signal/posix_signal.c index c0dd90e637..b06fe12685 100644 --- a/components/libc/signal/posix_signal.c +++ b/components/libc/signal/posix_signal.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/signal/posix_signal.h b/components/libc/signal/posix_signal.h index 896d6b6da4..fa8ad38fa6 100644 --- a/components/libc/signal/posix_signal.h +++ b/components/libc/signal/posix_signal.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/termios/posix_termios.c b/components/libc/termios/posix_termios.c index 9c736c3184..01ba010c86 100644 --- a/components/libc/termios/posix_termios.c +++ b/components/libc/termios/posix_termios.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/termios/posix_termios.h b/components/libc/termios/posix_termios.h index c61191b7dc..5bd1999b0a 100644 --- a/components/libc/termios/posix_termios.h +++ b/components/libc/termios/posix_termios.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/time/clock_time.c b/components/libc/time/clock_time.c index 83b3b916ca..f74e11724f 100644 --- a/components/libc/time/clock_time.c +++ b/components/libc/time/clock_time.c @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2012-12-08 Bernard fix the issue of _timevalue.tv_usec initialization, + * 2012-12-08 Bernard fix the issue of _timevalue.tv_usec initialization, * which found by Rob */ diff --git a/components/libc/time/clock_time.h b/components/libc/time/clock_time.h index 7feb0390a4..aef3ed2138 100644 --- a/components/libc/time/clock_time.h +++ b/components/libc/time/clock_time.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/libc/time/posix_sleep.c b/components/libc/time/posix_sleep.c index f21b0a7994..af05b1b9a1 100644 --- a/components/libc/time/posix_sleep.c +++ b/components/libc/time/posix_sleep.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/net/at/at_socket/at_socket.c b/components/net/at/at_socket/at_socket.c index ce8559f129..6d4c040856 100644 --- a/components/net/at/at_socket/at_socket.c +++ b/components/net/at/at_socket/at_socket.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -70,8 +70,8 @@ struct at_socket *at_get_socket(int socket) return at_sock; } } - } - + } + rt_hw_interrupt_enable(level); return RT_NULL; @@ -289,7 +289,7 @@ static int alloc_empty_socket(rt_slist_t *l) rt_slist_for_each(node, &_socket_list) { at_sock = rt_slist_entry(node, struct at_socket, list); - if(at_sock->socket != idx) + if(at_sock->socket != idx) break; idx++; pre_node = node; @@ -337,7 +337,7 @@ static struct at_socket *alloc_socket_by_device(struct at_device *device, enum a { goto __err; } - + sock = &(device->sockets[idx]); /* the socket descriptor is the number of sockte lists */ sock->socket = alloc_empty_socket(&(sock->list)); @@ -508,7 +508,7 @@ int at_closesocket(int socket) /* deal with TCP server actively disconnect */ rt_thread_delay(rt_tick_from_millisecond(100)); - + sock = at_get_socket(socket); if (sock == RT_NULL) { @@ -529,7 +529,7 @@ int at_closesocket(int socket) } } - free_socket(sock); + free_socket(sock); return 0; } @@ -603,7 +603,7 @@ int at_bind(int socket, const struct sockaddr *name, socklen_t namelen) /* input ip address is different from device ip address */ if (ip_addr_cmp(&input_ipaddr, &local_ipaddr) == 0) - { + { struct at_socket *new_sock = RT_NULL; struct at_device *new_device = RT_NULL; enum at_socket_type type = sock->type; @@ -613,7 +613,7 @@ int at_bind(int socket, const struct sockaddr *name, socklen_t namelen) { return -1; } - + extern struct at_device *at_device_get_by_ipaddr(ip_addr_t *ip_addr); new_device = at_device_get_by_ipaddr(&input_ipaddr); if (new_device == RT_NULL) @@ -649,7 +649,7 @@ static void at_recv_notice_cb(struct at_socket *sock, at_socket_evt_t event, con { RT_ASSERT(buff); RT_ASSERT(event == AT_SOCKET_EVT_RECV); - + /* check the socket object status */ if (sock->magic != AT_SOCKET_MAGIC) { @@ -675,7 +675,7 @@ static void at_closed_notice_cb(struct at_socket *sock, at_socket_evt_t event, c { return; } - + at_do_event_changes(sock, AT_EVENT_RECV, RT_TRUE); at_do_event_changes(sock, AT_EVENT_ERROR, RT_TRUE); @@ -731,7 +731,7 @@ __exit: { at_do_event_changes(sock, AT_EVENT_SEND, RT_TRUE); } - + return result; } @@ -780,7 +780,7 @@ int at_recvfrom(int socket, void *mem, size_t len, int flags, struct sockaddr *f goto __exit; } rt_mutex_release(sock->recv_lock); - + /* socket passively closed, receive function return 0 */ if (sock->state == AT_SOCKET_CLOSED) { @@ -821,7 +821,7 @@ int at_recvfrom(int socket, void *mem, size_t len, int flags, struct sockaddr *f goto __exit; } else - { + { /* get receive buffer to receiver ring buffer */ rt_mutex_take(sock->recv_lock, RT_WAITING_FOREVER); @@ -945,7 +945,7 @@ __exit: { if (sock != RT_NULL) { - at_do_event_changes(sock, AT_EVENT_ERROR, RT_TRUE); + at_do_event_changes(sock, AT_EVENT_ERROR, RT_TRUE); } } else @@ -1138,13 +1138,13 @@ struct hostent *at_gethostbyname(const char *name) #if NETDEV_IPV4 && NETDEV_IPV6 addr.u_addr.ip4.addr = ipstr_to_u32(ipstr); - addr.type = IPADDR_TYPE_V4; + addr.type = IPADDR_TYPE_V4; #elif NETDEV_IPV4 addr.addr = ipstr_to_u32(ipstr); #elif NETDEV_IPV6 #error "not support IPV6." #endif /* NETDEV_IPV4 && NETDEV_IPV6 */ - + /* fill hostent structure */ s_hostent_addr = addr; s_phostent_addr[0] = &s_hostent_addr; @@ -1243,8 +1243,8 @@ int at_getaddrinfo(const char *nodename, const char *servname, { strncpy(ip_str, nodename, strlen(nodename)); } - - #if NETDEV_IPV4 && NETDEV_IPV6 + + #if NETDEV_IPV4 && NETDEV_IPV6 addr.type = IPADDR_TYPE_V4; if ((addr.u_addr.ip4.addr = ipstr_to_u32(ip_str)) == 0) { @@ -1254,7 +1254,7 @@ int at_getaddrinfo(const char *nodename, const char *servname, addr.addr = ipstr_to_u32(ip_str); #elif NETDEV_IPV6 #error "not support IPV6." - #endif /* NETDEV_IPV4 && NETDEV_IPV6 */ + #endif /* NETDEV_IPV4 && NETDEV_IPV6 */ } } else diff --git a/components/net/at/at_socket/at_socket.h b/components/net/at/at_socket/at_socket.h index 3317579f05..caac6d2d5d 100644 --- a/components/net/at/at_socket/at_socket.h +++ b/components/net/at/at_socket/at_socket.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/net/at/include/at.h b/components/net/at/include/at.h index 2d0e270f6a..7d9de6b353 100644 --- a/components/net/at/include/at.h +++ b/components/net/at/include/at.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/net/at/include/at_log.h b/components/net/at/include/at_log.h index 9e133561f7..acb5b34ecc 100644 --- a/components/net/at/include/at_log.h +++ b/components/net/at/include/at_log.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/net/at/src/at_base_cmd.c b/components/net/at/src/at_base_cmd.c index b182477f9b..00720c87b2 100644 --- a/components/net/at/src/at_base_cmd.c +++ b/components/net/at/src/at_base_cmd.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/net/at/src/at_cli.c b/components/net/at/src/at_cli.c index e39a913357..25fbb708f4 100644 --- a/components/net/at/src/at_cli.c +++ b/components/net/at/src/at_cli.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -27,7 +27,7 @@ static rt_err_t (*odev_rx_ind)(rt_device_t dev, rt_size_t size) = RT_NULL; #ifdef AT_USING_CLIENT static struct rt_semaphore client_rx_notice; static struct rt_ringbuffer *client_rx_fifo = RT_NULL; -#endif +#endif static char console_getchar(void) { diff --git a/components/net/at/src/at_client.c b/components/net/at/src/at_client.c index b9d0ee89cb..d636460c2d 100644 --- a/components/net/at/src/at_client.c +++ b/components/net/at/src/at_client.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -579,7 +579,7 @@ int at_obj_set_urc_table(at_client_t client, const struct at_urc *urc_table, rt_ client->urc_table[client->urc_table_size].urc = urc_table; client->urc_table[client->urc_table_size].urc_size = table_sz; client->urc_table_size++; - + rt_free(old_urc_table); } diff --git a/components/net/at/src/at_server.c b/components/net/at/src/at_server.c index 81d00951f5..bfbbbae2d3 100644 --- a/components/net/at/src/at_server.c +++ b/components/net/at/src/at_server.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/net/at/src/at_utils.c b/components/net/at/src/at_utils.c index 7d26425f56..8d8887fe5e 100644 --- a/components/net/at/src/at_utils.c +++ b/components/net/at/src/at_utils.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/net/lwip-1.4.1/src/arch/sys_arch.c b/components/net/lwip-1.4.1/src/arch/sys_arch.c index d9a11a7e59..b411563f3e 100644 --- a/components/net/lwip-1.4.1/src/arch/sys_arch.c +++ b/components/net/lwip-1.4.1/src/arch/sys_arch.c @@ -1,5 +1,5 @@ /* - * COPYRIGHT (C) 2006-2018, RT-Thread Development Team + * COPYRIGHT (C) 2006-2021, RT-Thread Development Team * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, @@ -195,9 +195,9 @@ int lwip_system_init(void) netifapi_netif_set_addr(netif_default, &ipaddr, &netmask, &gw); } #endif - rt_kprintf("lwIP-%d.%d.%d initialized!\n", LWIP_VERSION_MAJOR, LWIP_VERSION_MINOR, LWIP_VERSION_REVISION); + rt_kprintf("lwIP-%d.%d.%d initialized!\n", LWIP_VERSION_MAJOR, LWIP_VERSION_MINOR, LWIP_VERSION_REVISION); - return 0; + return 0; } INIT_PREV_EXPORT(lwip_system_init); @@ -618,7 +618,7 @@ u32_t sys_jiffies(void) u32_t sys_now(void) { - return rt_tick_get() * (1000 / RT_TICK_PER_SECOND); + return rt_tick_get() * (1000 / RT_TICK_PER_SECOND); } #ifdef RT_LWIP_PPP diff --git a/components/net/lwip-1.4.1/src/netif/ethernetif.c b/components/net/lwip-1.4.1/src/netif/ethernetif.c index 4a8ff12521..052ee1bb01 100644 --- a/components/net/lwip-1.4.1/src/netif/ethernetif.c +++ b/components/net/lwip-1.4.1/src/netif/ethernetif.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * COPYRIGHT (C) 2006-2010, RT-Thread Development Team + * COPYRIGHT (C) 2006-2021, RT-Thread Development Team * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, @@ -59,9 +59,9 @@ #define netifapi_netif_set_link_down(n) netifapi_netif_common(n, netif_set_link_down, NULL) #ifndef RT_LWIP_ETHTHREAD_PRIORITY -#define RT_ETHERNETIF_THREAD_PREORITY 0x90 +#define RT_ETHERNETIF_THREAD_PREORITY 0x90 #else -#define RT_ETHERNETIF_THREAD_PREORITY RT_LWIP_ETHTHREAD_PRIORITY +#define RT_ETHERNETIF_THREAD_PREORITY RT_LWIP_ETHTHREAD_PRIORITY #endif #ifndef LWIP_NO_TX_THREAD @@ -70,8 +70,8 @@ */ struct eth_tx_msg { - struct netif *netif; - struct pbuf *buf; + struct netif *netif; + struct pbuf *buf; }; static struct rt_mailbox eth_tx_thread_mb; @@ -156,16 +156,16 @@ static int lwip_netdev_set_dns_server(struct netdev *netif, uint8_t dns_num, ip_ static int lwip_netdev_set_dhcp(struct netdev *netif, rt_bool_t is_enabled) { netdev_low_level_set_dhcp_status(netif, is_enabled); - + if(RT_TRUE == is_enabled) { dhcp_start((struct netif *)netif->user_data); } else { - dhcp_stop((struct netif *)netif->user_data); + dhcp_stop((struct netif *)netif->user_data); } - + return ERR_OK; } #endif /* RT_LWIP_DHCP */ @@ -368,7 +368,7 @@ static err_t ethernetif_linkoutput(struct netif *netif, struct pbuf *p) struct eth_tx_msg msg; struct eth_device* enetif; - RT_ASSERT(netif != RT_NULL); + RT_ASSERT(netif != RT_NULL); enetif = (struct eth_device*)netif->state; /* send a message to eth tx thread */ @@ -382,13 +382,13 @@ static err_t ethernetif_linkoutput(struct netif *netif, struct pbuf *p) #else struct eth_device* enetif; - RT_ASSERT(netif != RT_NULL); + RT_ASSERT(netif != RT_NULL); enetif = (struct eth_device*)netif->state; - if (enetif->eth_tx(&(enetif->parent), p) != RT_EOK) - { - return ERR_IF; - } + if (enetif->eth_tx(&(enetif->parent), p) != RT_EOK) + { + return ERR_IF; + } #endif return ERR_OK; } @@ -474,16 +474,16 @@ rt_err_t eth_device_init_with_flag(struct eth_device *dev, const char *name, rt_ netif->name[1] = name[1]; /* set hw address to 6 */ - netif->hwaddr_len = 6; + netif->hwaddr_len = 6; /* maximum transfer unit */ - netif->mtu = ETHERNET_MTU; + netif->mtu = ETHERNET_MTU; /* get hardware MAC address */ rt_device_control(&(dev->parent), NIOCTL_GADDR, netif->hwaddr); /* set output */ - netif->output = etharp_output; - netif->linkoutput = ethernetif_linkoutput; + netif->output = etharp_output; + netif->linkoutput = ethernetif_linkoutput; /* if tcp thread has been started up, we add this netif to the system */ if (rt_thread_find("tcpip") != RT_NULL) @@ -565,12 +565,12 @@ rt_err_t eth_device_linkchange(struct eth_device* dev, rt_bool_t up) /* NOTE: please not use it in interrupt when no RxThread exist */ rt_err_t eth_device_linkchange(struct eth_device* dev, rt_bool_t up) { - if (up == RT_TRUE) - netifapi_netif_set_link_up(dev->netif); - else - netifapi_netif_set_link_down(dev->netif); + if (up == RT_TRUE) + netifapi_netif_set_link_up(dev->netif); + else + netifapi_netif_set_link_down(dev->netif); - return RT_EOK; + return RT_EOK; } #endif @@ -638,8 +638,8 @@ static void eth_rx_thread_entry(void* parameter) /* receive all of buffer */ while (1) { - if(device->eth_rx == RT_NULL) break; - + if(device->eth_rx == RT_NULL) break; + p = device->eth_rx(&(device->parent)); if (p != RT_NULL) { diff --git a/components/net/lwip-2.0.2/src/arch/sys_arch.c b/components/net/lwip-2.0.2/src/arch/sys_arch.c index 7a814f403e..b0d4709c93 100644 --- a/components/net/lwip-2.0.2/src/arch/sys_arch.c +++ b/components/net/lwip-2.0.2/src/arch/sys_arch.c @@ -1,5 +1,5 @@ /* - * COPYRIGHT (C) 2006-2018, RT-Thread Development Team + * COPYRIGHT (C) 2006-2021, RT-Thread Development Team * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, diff --git a/components/net/lwip-2.0.2/src/netif/ethernetif.c b/components/net/lwip-2.0.2/src/netif/ethernetif.c index 12c931fbb4..b49125c194 100644 --- a/components/net/lwip-2.0.2/src/netif/ethernetif.c +++ b/components/net/lwip-2.0.2/src/netif/ethernetif.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * COPYRIGHT (C) 2006-2018, RT-Thread Development Team + * COPYRIGHT (C) 2006-2021, RT-Thread Development Team * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, @@ -172,7 +172,7 @@ static int lwip_netdev_set_dhcp(struct netdev *netif, rt_bool_t is_enabled) } else { - dhcp_stop((struct netif *)netif->user_data); + dhcp_stop((struct netif *)netif->user_data); } return ERR_OK; } @@ -183,7 +183,7 @@ static int lwip_netdev_set_dhcp(struct netdev *netif, rt_bool_t is_enabled) extern int lwip_ping_recv(int s, int *ttl); extern err_t lwip_ping_send(int s, ip_addr_t *addr, int size); -int lwip_netdev_ping(struct netdev *netif, const char *host, size_t data_len, +int lwip_netdev_ping(struct netdev *netif, const char *host, size_t data_len, uint32_t timeout, struct netdev_ping_resp *ping_resp) { int s, ttl, recv_len, result = 0; @@ -198,7 +198,7 @@ int lwip_netdev_ping(struct netdev *netif, const char *host, size_t data_len, struct addrinfo hint, *res = RT_NULL; struct sockaddr_in *h = RT_NULL; struct in_addr ina; - + RT_ASSERT(netif); RT_ASSERT(host); RT_ASSERT(ping_resp); @@ -217,7 +217,7 @@ int lwip_netdev_ping(struct netdev *netif, const char *host, size_t data_len, return -RT_ERROR; } rt_memcpy(&(ping_resp->ip_addr), &target_addr, sizeof(ip_addr_t)); - + /* new a socket */ if ((s = lwip_socket(AF_INET, SOCK_RAW, IP_PROTO_ICMP)) < 0) { @@ -285,7 +285,7 @@ const struct netdev_ops lwip_netdev_ops = lwip_netdev_set_addr_info, #ifdef RT_LWIP_DNS lwip_netdev_set_dns_server, -#else +#else NULL, #endif /* RT_LWIP_DNS */ @@ -333,8 +333,8 @@ static int netdev_add(struct netif *lwip_netif) rt_strncpy(name, lwip_netif->name, LWIP_NETIF_NAME_LEN); result = netdev_register(netdev, name, (void *)lwip_netif); - - /* Update netdev info after registered */ + + /* Update netdev info after registered */ netdev->flags = lwip_netif->flags; netdev->mtu = lwip_netif->mtu; netdev->ops = &lwip_netdev_ops; @@ -343,7 +343,7 @@ static int netdev_add(struct netif *lwip_netif) netdev->ip_addr = lwip_netif->ip_addr; netdev->gw = lwip_netif->gw; netdev->netmask = lwip_netif->netmask; - + #ifdef RT_LWIP_DHCP netdev_low_level_set_dhcp_status(netdev, RT_TRUE); #endif @@ -422,7 +422,7 @@ static err_t eth_netif_device_init(struct netif *netif) /* network interface device register */ netdev_add(netif); #endif /* RT_USING_NETDEV */ - + ethif = (struct eth_device*)netif->state; if (ethif != RT_NULL) { @@ -541,7 +541,7 @@ rt_err_t eth_device_init_with_flag(struct eth_device *dev, const char *name, rt_ ipaddr.addr = inet_addr(RT_LWIP_IPADDR); gw.addr = inet_addr(RT_LWIP_GWADDR); netmask.addr = inet_addr(RT_LWIP_MSKADDR); -#else +#else IP4_ADDR(&ipaddr, 0, 0, 0, 0); IP4_ADDR(&gw, 0, 0, 0, 0); IP4_ADDR(&netmask, 0, 0, 0, 0); @@ -693,7 +693,7 @@ static void eth_rx_thread_entry(void* parameter) while (1) { if(device->eth_rx == RT_NULL) break; - + p = device->eth_rx(&(device->parent)); if (p != RT_NULL) { @@ -716,9 +716,9 @@ static void eth_rx_thread_entry(void* parameter) } #endif -/* this function does not need, - * use eth_system_device_init_private() - * call by lwip_system_init(). +/* this function does not need, + * use eth_system_device_init_private() + * call by lwip_system_init(). */ int eth_system_device_init(void) { @@ -861,27 +861,27 @@ void list_if(void) rt_kprintf("gw address: %s\n", ipaddr_ntoa(&(netif->gw))); rt_kprintf("net mask : %s\n", ipaddr_ntoa(&(netif->netmask))); #if LWIP_IPV6 - { - ip6_addr_t *addr; - int addr_state; - int i; - - addr = (ip6_addr_t *)&netif->ip6_addr[0]; - addr_state = netif->ip6_addr_state[0]; - - rt_kprintf("\nipv6 link-local: %s state:%02X %s\n", ip6addr_ntoa(addr), - addr_state, ip6_addr_isvalid(addr_state)?"VALID":"INVALID"); - - for(i=1; iip6_addr[i]; - addr_state = netif->ip6_addr_state[i]; - - rt_kprintf("ipv6[%d] address: %s state:%02X %s\n", i, ip6addr_ntoa(addr), - addr_state, ip6_addr_isvalid(addr_state)?"VALID":"INVALID"); - } - - } + { + ip6_addr_t *addr; + int addr_state; + int i; + + addr = (ip6_addr_t *)&netif->ip6_addr[0]; + addr_state = netif->ip6_addr_state[0]; + + rt_kprintf("\nipv6 link-local: %s state:%02X %s\n", ip6addr_ntoa(addr), + addr_state, ip6_addr_isvalid(addr_state)?"VALID":"INVALID"); + + for(i=1; iip6_addr[i]; + addr_state = netif->ip6_addr_state[i]; + + rt_kprintf("ipv6[%d] address: %s state:%02X %s\n", i, ip6addr_ntoa(addr), + addr_state, ip6_addr_isvalid(addr_state)?"VALID":"INVALID"); + } + + } rt_kprintf("\r\n"); #endif /* LWIP_IPV6 */ netif = netif->next; diff --git a/components/net/lwip-2.1.2/src/arch/sys_arch.c b/components/net/lwip-2.1.2/src/arch/sys_arch.c index a0eeed1073..c97609a4ea 100644 --- a/components/net/lwip-2.1.2/src/arch/sys_arch.c +++ b/components/net/lwip-2.1.2/src/arch/sys_arch.c @@ -1,5 +1,5 @@ /* - * COPYRIGHT (C) 2006-2018, RT-Thread Development Team + * COPYRIGHT (C) 2006-2021, RT-Thread Development Team * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, diff --git a/components/net/lwip-2.1.2/src/netif/ethernetif.c b/components/net/lwip-2.1.2/src/netif/ethernetif.c index 52bd0fb7b6..829978c139 100644 --- a/components/net/lwip-2.1.2/src/netif/ethernetif.c +++ b/components/net/lwip-2.1.2/src/netif/ethernetif.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * COPYRIGHT (C) 2006-2018, RT-Thread Development Team + * COPYRIGHT (C) 2006-2021, RT-Thread Development Team * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, @@ -163,16 +163,16 @@ static int lwip_netdev_set_dns_server(struct netdev *netif, uint8_t dns_num, ip_ static int lwip_netdev_set_dhcp(struct netdev *netif, rt_bool_t is_enabled) { netdev_low_level_set_dhcp_status(netif, is_enabled); - + if(RT_TRUE == is_enabled) { dhcp_start((struct netif *)netif->user_data); } else { - dhcp_stop((struct netif *)netif->user_data); + dhcp_stop((struct netif *)netif->user_data); } - + return ERR_OK; } #endif /* RT_LWIP_DHCP */ @@ -182,7 +182,7 @@ static int lwip_netdev_set_dhcp(struct netdev *netif, rt_bool_t is_enabled) extern int lwip_ping_recv(int s, int *ttl); extern err_t lwip_ping_send(int s, ip_addr_t *addr, int size); -int lwip_netdev_ping(struct netdev *netif, const char *host, size_t data_len, +int lwip_netdev_ping(struct netdev *netif, const char *host, size_t data_len, uint32_t timeout, struct netdev_ping_resp *ping_resp) { int s, ttl, recv_len, result = 0; @@ -197,7 +197,7 @@ int lwip_netdev_ping(struct netdev *netif, const char *host, size_t data_len, struct addrinfo hint, *res = RT_NULL; struct sockaddr_in *h = RT_NULL; struct in_addr ina; - + RT_ASSERT(netif); RT_ASSERT(host); RT_ASSERT(ping_resp); @@ -216,7 +216,7 @@ int lwip_netdev_ping(struct netdev *netif, const char *host, size_t data_len, return -RT_ERROR; } rt_memcpy(&(ping_resp->ip_addr), &target_addr, sizeof(ip_addr_t)); - + /* new a socket */ if ((s = lwip_socket(AF_INET, SOCK_RAW, IP_PROTO_ICMP)) < 0) { @@ -284,7 +284,7 @@ const struct netdev_ops lwip_netdev_ops = lwip_netdev_set_addr_info, #ifdef RT_LWIP_DNS lwip_netdev_set_dns_server, -#else +#else NULL, #endif /* RT_LWIP_DNS */ @@ -323,7 +323,7 @@ static int netdev_add(struct netif *lwip_netif) { return -ERR_IF; } - + #ifdef SAL_USING_LWIP extern int sal_lwip_netdev_set_pf_info(struct netdev *netdev); /* set the lwIP network interface device protocol family information */ @@ -332,7 +332,7 @@ static int netdev_add(struct netif *lwip_netif) rt_strncpy(name, lwip_netif->name, LWIP_NETIF_NAME_LEN); result = netdev_register(netdev, name, (void *)lwip_netif); - + /* Update netdev info after registered */ netdev->flags = lwip_netif->flags; netdev->mtu = lwip_netif->mtu; @@ -375,7 +375,7 @@ static int netdev_flags_sync(struct netif *lwip_netif) { return -ERR_IF; } - + netdev->mtu = lwip_netif->mtu; netdev->flags |= lwip_netif->flags; @@ -438,7 +438,7 @@ static err_t eth_netif_device_init(struct netif *netif) /* copy device flags to netif flags */ netif->flags = (ethif->flags & 0xff); netif->mtu = ETHERNET_MTU; - + /* set output */ netif->output = etharp_output; @@ -530,7 +530,7 @@ rt_err_t eth_device_init_with_flag(struct eth_device *dev, const char *name, rt_ /* set linkoutput */ netif->linkoutput = ethernetif_linkoutput; - + /* get hardware MAC address */ rt_device_control(&(dev->parent), NIOCTL_GADDR, netif->hwaddr); @@ -550,7 +550,7 @@ rt_err_t eth_device_init_with_flag(struct eth_device *dev, const char *name, rt_ ipaddr.addr = inet_addr(RT_LWIP_IPADDR); gw.addr = inet_addr(RT_LWIP_GWADDR); netmask.addr = inet_addr(RT_LWIP_MSKADDR); -#else +#else IP4_ADDR(&ipaddr, 0, 0, 0, 0); IP4_ADDR(&gw, 0, 0, 0, 0); IP4_ADDR(&netmask, 0, 0, 0, 0); @@ -702,7 +702,7 @@ static void eth_rx_thread_entry(void* parameter) while (1) { if(device->eth_rx == RT_NULL) break; - + p = device->eth_rx(&(device->parent)); if (p != RT_NULL) { @@ -725,9 +725,9 @@ static void eth_rx_thread_entry(void* parameter) } #endif -/* this function does not need, - * use eth_system_device_init_private() - * call by lwip_system_init(). +/* this function does not need, + * use eth_system_device_init_private() + * call by lwip_system_init(). */ int eth_system_device_init(void) { @@ -870,27 +870,27 @@ void list_if(void) rt_kprintf("gw address: %s\n", ipaddr_ntoa(&(netif->gw))); rt_kprintf("net mask : %s\n", ipaddr_ntoa(&(netif->netmask))); #if LWIP_IPV6 - { - ip6_addr_t *addr; - int addr_state; - int i; - - addr = (ip6_addr_t *)&netif->ip6_addr[0]; - addr_state = netif->ip6_addr_state[0]; - - rt_kprintf("\nipv6 link-local: %s state:%02X %s\n", ip6addr_ntoa(addr), - addr_state, ip6_addr_isvalid(addr_state)?"VALID":"INVALID"); - - for(i=1; iip6_addr[i]; - addr_state = netif->ip6_addr_state[i]; - - rt_kprintf("ipv6[%d] address: %s state:%02X %s\n", i, ip6addr_ntoa(addr), - addr_state, ip6_addr_isvalid(addr_state)?"VALID":"INVALID"); - } - - } + { + ip6_addr_t *addr; + int addr_state; + int i; + + addr = (ip6_addr_t *)&netif->ip6_addr[0]; + addr_state = netif->ip6_addr_state[0]; + + rt_kprintf("\nipv6 link-local: %s state:%02X %s\n", ip6addr_ntoa(addr), + addr_state, ip6_addr_isvalid(addr_state)?"VALID":"INVALID"); + + for(i=1; iip6_addr[i]; + addr_state = netif->ip6_addr_state[i]; + + rt_kprintf("ipv6[%d] address: %s state:%02X %s\n", i, ip6addr_ntoa(addr), + addr_state, ip6_addr_isvalid(addr_state)?"VALID":"INVALID"); + } + + } rt_kprintf("\r\n"); #endif /* LWIP_IPV6 */ netif = netif->next; diff --git a/components/net/lwip_dhcpd/dhcp_server.c b/components/net/lwip_dhcpd/dhcp_server.c index 93b4ad16f0..0ebbe89ca4 100644 --- a/components/net/lwip_dhcpd/dhcp_server.c +++ b/components/net/lwip_dhcpd/dhcp_server.c @@ -2,7 +2,7 @@ * File : dhcp_server.c * A simple DHCP server implementation * - * COPYRIGHT (C) 2011-2018, Shanghai Real-Thread Technology Co., Ltd + * COPYRIGHT (C) 2011-2021, Shanghai Real-Thread Technology Co., Ltd * http://www.rt-thread.com * All rights reserved. * diff --git a/components/net/lwip_dhcpd/dhcp_server.h b/components/net/lwip_dhcpd/dhcp_server.h index ea68d6b8ec..3533cb6087 100644 --- a/components/net/lwip_dhcpd/dhcp_server.h +++ b/components/net/lwip_dhcpd/dhcp_server.h @@ -2,7 +2,7 @@ * File : dhcp_server.h * A simple DHCP server implementation * - * COPYRIGHT (C) 2011-2018, Shanghai Real-Thread Technology Co., Ltd + * COPYRIGHT (C) 2011-2021, Shanghai Real-Thread Technology Co., Ltd * http://www.rt-thread.com * All rights reserved. * diff --git a/components/net/lwip_dhcpd/dhcp_server_raw.c b/components/net/lwip_dhcpd/dhcp_server_raw.c index 6c786301be..06a7affc97 100644 --- a/components/net/lwip_dhcpd/dhcp_server_raw.c +++ b/components/net/lwip_dhcpd/dhcp_server_raw.c @@ -1,7 +1,7 @@ /* * File : dhcp_server_raw.c * A simple DHCP server implementation - * COPYRIGHT (C) 2011-2018, Shanghai Real-Thread Technology Co., Ltd + * COPYRIGHT (C) 2011-2021, Shanghai Real-Thread Technology Co., Ltd * http://www.rt-thread.com * All rights reserved. * @@ -26,7 +26,7 @@ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY * OF SUCH DAMAGE. - * + * * Change Logs: * Date Author Notes * 2014-04-01 Ren.Haibo the first version diff --git a/components/net/netdev/include/arpa/inet.h b/components/net/netdev/include/arpa/inet.h index 085e15dcbc..9072dffb79 100644 --- a/components/net/netdev/include/arpa/inet.h +++ b/components/net/netdev/include/arpa/inet.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/net/netdev/include/netdev.h b/components/net/netdev/include/netdev.h index e11a8929b0..16da0e502c 100644 --- a/components/net/netdev/include/netdev.h +++ b/components/net/netdev/include/netdev.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -79,8 +79,8 @@ struct netdev_ops; /* network interface device object */ struct netdev { - rt_slist_t list; - + rt_slist_t list; + char name[RT_NAME_MAX]; /* network interface device name */ ip_addr_t ip_addr; /* IP address */ ip_addr_t netmask; /* subnet mask */ @@ -91,11 +91,11 @@ struct netdev ip_addr_t dns_servers[NETDEV_DNS_SERVERS_NUM]; /* DNS server */ uint8_t hwaddr_len; /* hardware address length */ uint8_t hwaddr[NETDEV_HWADDR_MAX_LEN]; /* hardware address */ - + uint16_t flags; /* network interface device status flag */ uint16_t mtu; /* maximum transfer unit (in bytes) */ const struct netdev_ops *ops; /* network interface device operations */ - + netdev_callback_fn status_callback; /* network interface device flags change callback */ netdev_callback_fn addr_callback; /* network interface device address information change callback */ diff --git a/components/net/netdev/include/netdev_ipaddr.h b/components/net/netdev/include/netdev_ipaddr.h index 65970ec5b7..08ea50ed9d 100644 --- a/components/net/netdev/include/netdev_ipaddr.h +++ b/components/net/netdev/include/netdev_ipaddr.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -23,30 +23,30 @@ extern "C" { * On subnets, the decomposition of addresses to host and net parts * is done according to subnet mask, not the masks here. */ -#define IN_CLASSA(i) (((long)(i) & 0x80000000) == 0) -#define IN_CLASSA_NET 0xff000000 -#define IN_CLASSA_NSHIFT 24 -#define IN_CLASSA_HOST 0x00ffffff -#define IN_CLASSA_MAX 128 +#define IN_CLASSA(i) (((long)(i) & 0x80000000) == 0) +#define IN_CLASSA_NET 0xff000000 +#define IN_CLASSA_NSHIFT 24 +#define IN_CLASSA_HOST 0x00ffffff +#define IN_CLASSA_MAX 128 -#define IN_CLASSB(i) (((long)(i) & 0xc0000000) == 0x80000000) -#define IN_CLASSB_NET 0xffff0000 -#define IN_CLASSB_NSHIFT 16 -#define IN_CLASSB_HOST 0x0000ffff -#define IN_CLASSB_MAX 65536 +#define IN_CLASSB(i) (((long)(i) & 0xc0000000) == 0x80000000) +#define IN_CLASSB_NET 0xffff0000 +#define IN_CLASSB_NSHIFT 16 +#define IN_CLASSB_HOST 0x0000ffff +#define IN_CLASSB_MAX 65536 -#define IN_CLASSC(i) (((long)(i) & 0xe0000000) == 0xc0000000) -#define IN_CLASSC_NET 0xffffff00 -#define IN_CLASSC_NSHIFT 8 -#define IN_CLASSC_HOST 0x000000ff +#define IN_CLASSC(i) (((long)(i) & 0xe0000000) == 0xc0000000) +#define IN_CLASSC_NET 0xffffff00 +#define IN_CLASSC_NSHIFT 8 +#define IN_CLASSC_HOST 0x000000ff -#define IN_CLASSD(i) (((long)(i) & 0xf0000000) == 0xe0000000) -#define IN_MULTICAST(i) IN_CLASSD(i) +#define IN_CLASSD(i) (((long)(i) & 0xf0000000) == 0xe0000000) +#define IN_MULTICAST(i) IN_CLASSD(i) -#define IN_EXPERIMENTAL(i) (((long)(i) & 0xe0000000) == 0xe0000000) -#define IN_BADCLASS(i) (((long)(i) & 0xf0000000) == 0xf0000000) +#define IN_EXPERIMENTAL(i) (((long)(i) & 0xe0000000) == 0xe0000000) +#define IN_BADCLASS(i) (((long)(i) & 0xf0000000) == 0xf0000000) -#define IN_LOOPBACKNET 127 /* official! */ +#define IN_LOOPBACKNET 127 /* official! */ /* IP address types for use in ip_addr_t.type member */ enum netdev_ip_addr_type { @@ -307,7 +307,7 @@ const char *netdev_inet_ntop(int af, const void *src, char *dst, int32_t size); int netdev_inet_pton(int af, const char *src, void *dst); #define inet_ntop(af, src, dst, size) netdev_inet_ntop(af, src, dst, size) -#define inet_pton(af, src, dst) netdev_inet_pton(af, src, dst) +#define inet_pton(af, src, dst) netdev_inet_pton(af, src, dst) #ifdef __cplusplus } diff --git a/components/net/netdev/src/netdev.c b/components/net/netdev/src/netdev.c index 326464866b..ce418757f7 100644 --- a/components/net/netdev/src/netdev.c +++ b/components/net/netdev/src/netdev.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/net/netdev/src/netdev_ipaddr.c b/components/net/netdev/src/netdev_ipaddr.c index a70a90bb75..9abb41bd14 100644 --- a/components/net/netdev/src/netdev_ipaddr.c +++ b/components/net/netdev/src/netdev_ipaddr.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/net/sal_socket/dfs_net/dfs_net.c b/components/net/sal_socket/dfs_net/dfs_net.c index f1a3d777a1..67b652c320 100644 --- a/components/net/sal_socket/dfs_net/dfs_net.c +++ b/components/net/sal_socket/dfs_net/dfs_net.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -21,7 +21,7 @@ int dfs_net_getsocket(int fd) { int socket; - struct dfs_fd *_dfs_fd; + struct dfs_fd *_dfs_fd; _dfs_fd = fd_get(fd); if (_dfs_fd == NULL) return -1; @@ -68,7 +68,7 @@ static int dfs_net_poll(struct dfs_fd *file, struct rt_pollreq *req) return sal_poll(file, req); } -const struct dfs_file_ops _net_fops = +const struct dfs_file_ops _net_fops = { NULL, /* open */ dfs_net_close, diff --git a/components/net/sal_socket/impl/af_inet.h b/components/net/sal_socket/impl/af_inet.h index caffbe1400..421d15bfae 100644 --- a/components/net/sal_socket/impl/af_inet.h +++ b/components/net/sal_socket/impl/af_inet.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/net/sal_socket/impl/af_inet_at.c b/components/net/sal_socket/impl/af_inet_at.c index 135e4183c4..c85dfe9f06 100644 --- a/components/net/sal_socket/impl/af_inet_at.c +++ b/components/net/sal_socket/impl/af_inet_at.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -85,7 +85,7 @@ static const struct sal_socket_ops at_socket_ops = #endif /* SAL_USING_POSIX */ }; -static const struct sal_netdb_ops at_netdb_ops = +static const struct sal_netdb_ops at_netdb_ops = { at_gethostbyname, NULL, diff --git a/components/net/sal_socket/impl/af_inet_lwip.c b/components/net/sal_socket/impl/af_inet_lwip.c index 56df735ab9..2e19275b5d 100644 --- a/components/net/sal_socket/impl/af_inet_lwip.c +++ b/components/net/sal_socket/impl/af_inet_lwip.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -229,7 +229,7 @@ int inet_ioctlsocket(int socket, long cmd, void *arg) { case F_GETFL: case F_SETFL: - return lwip_fcntl(socket, cmd, (int) arg); + return lwip_fcntl(socket, cmd, (int) arg); default: return lwip_ioctl(socket, cmd, arg); @@ -320,7 +320,7 @@ static const struct sal_proto_family lwip_inet_family = AF_INET6, #else AF_INET, -#endif +#endif &lwip_socket_ops, &lwip_netdb_ops, }; @@ -329,7 +329,7 @@ static const struct sal_proto_family lwip_inet_family = int sal_lwip_netdev_set_pf_info(struct netdev *netdev) { RT_ASSERT(netdev); - + netdev->sal_user_data = (void *) &lwip_inet_family; return 0; } diff --git a/components/net/sal_socket/impl/proto_mbedtls.c b/components/net/sal_socket/impl/proto_mbedtls.c index 3472bbeaf5..79fbdcc5d4 100644 --- a/components/net/sal_socket/impl/proto_mbedtls.c +++ b/components/net/sal_socket/impl/proto_mbedtls.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -59,7 +59,7 @@ static void *mebdtls_socket(int socket) { tls_free(session); session = RT_NULL; - + return RT_NULL; } @@ -68,7 +68,7 @@ static void *mebdtls_socket(int socket) { mbedtls_client_close(session); return RT_NULL; - } + } session->server_fd.fd = socket; return (void *)session; @@ -89,7 +89,7 @@ int mbedtls_net_send_cb(void *ctx, const unsigned char *buf, size_t len) { return -1; } - + pf = (struct sal_proto_family *)sock->netdev->sal_user_data; /* Register scoket sendto option to TLS send data callback */ @@ -128,7 +128,7 @@ int mbedtls_net_recv_cb( void *ctx, unsigned char *buf, size_t len) } pf = (struct sal_proto_family *)sock->netdev->sal_user_data; - + /* Register scoket recvfrom option to TLS recv data callback */ ret = pf->skt_ops->recvfrom((int) sock->user_data, (void *)buf, len, 0, RT_NULL, RT_NULL); if (ret < 0) @@ -183,7 +183,7 @@ static int mbedtls_connect(void *sock) mbedtls_x509_crt_verify_info((char *)session->buffer, session->buffer_len, " ! ", ret); goto __exit; } - + return ret; __exit: @@ -199,27 +199,27 @@ static int mbedtls_closesocket(void *sock) { struct sal_socket *ssock; int socket; - + if (sock == RT_NULL) { return 0; } - + socket = ((MbedTLSSession *) sock)->server_fd.fd; ssock = sal_get_socket(socket); if (ssock == RT_NULL) { return -1; } - + /* Close TLS client session, and clean user-data in SAL socket */ mbedtls_client_close((MbedTLSSession *) sock); ssock->user_data_tls = RT_NULL; - + return 0; } -static const struct sal_proto_tls_ops mbedtls_proto_ops= +static const struct sal_proto_tls_ops mbedtls_proto_ops= { RT_NULL, mebdtls_socket, diff --git a/components/net/sal_socket/include/dfs_net/dfs_net.h b/components/net/sal_socket/include/dfs_net/dfs_net.h index ad28b8ec2a..82b7526603 100644 --- a/components/net/sal_socket/include/dfs_net/dfs_net.h +++ b/components/net/sal_socket/include/dfs_net/dfs_net.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/net/sal_socket/include/dfs_net/sys_select/sys/select.h b/components/net/sal_socket/include/dfs_net/sys_select/sys/select.h index 8899daee96..f174bc6504 100644 --- a/components/net/sal_socket/include/dfs_net/sys_select/sys/select.h +++ b/components/net/sal_socket/include/dfs_net/sys_select/sys/select.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/net/sal_socket/include/sal.h b/components/net/sal_socket/include/sal.h index 6ffaa90356..dd250e37b6 100644 --- a/components/net/sal_socket/include/sal.h +++ b/components/net/sal_socket/include/sal.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/net/sal_socket/include/sal_netdb.h b/components/net/sal_socket/include/sal_netdb.h index d5ce9b1d7e..50064ce343 100644 --- a/components/net/sal_socket/include/sal_netdb.h +++ b/components/net/sal_socket/include/sal_netdb.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/net/sal_socket/include/sal_socket.h b/components/net/sal_socket/include/sal_socket.h index b620bbe23c..497be47e41 100644 --- a/components/net/sal_socket/include/sal_socket.h +++ b/components/net/sal_socket/include/sal_socket.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -171,7 +171,7 @@ struct sockaddr_in #endif /* NETDEV_IPV4 */ #if NETDEV_IPV6 -struct sockaddr_in6 +struct sockaddr_in6 { uint8_t sin6_len; /* length of this structure */ sa_family_t sin6_family; /* AF_INET6 */ diff --git a/components/net/sal_socket/include/sal_tls.h b/components/net/sal_socket/include/sal_tls.h index 7681b313bd..f211a3c1f8 100644 --- a/components/net/sal_socket/include/sal_tls.h +++ b/components/net/sal_socket/include/sal_tls.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/net/sal_socket/include/socket/netdb.h b/components/net/sal_socket/include/socket/netdb.h index 17f83efe00..4783405022 100644 --- a/components/net/sal_socket/include/socket/netdb.h +++ b/components/net/sal_socket/include/socket/netdb.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/net/sal_socket/include/socket/netinet/in.h b/components/net/sal_socket/include/socket/netinet/in.h index 57c417d7b6..37240547b4 100644 --- a/components/net/sal_socket/include/socket/netinet/in.h +++ b/components/net/sal_socket/include/socket/netinet/in.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/net/sal_socket/include/socket/netinet/tcp.h b/components/net/sal_socket/include/socket/netinet/tcp.h index 2ac4d6f40d..a3b530186a 100644 --- a/components/net/sal_socket/include/socket/netinet/tcp.h +++ b/components/net/sal_socket/include/socket/netinet/tcp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/net/sal_socket/include/socket/netinet/udp.h b/components/net/sal_socket/include/socket/netinet/udp.h index 485d7d142c..21f50d55e5 100644 --- a/components/net/sal_socket/include/socket/netinet/udp.h +++ b/components/net/sal_socket/include/socket/netinet/udp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/net/sal_socket/include/socket/sys_socket/sys/socket.h b/components/net/sal_socket/include/socket/sys_socket/sys/socket.h index 04470aa84a..a86240e2ff 100644 --- a/components/net/sal_socket/include/socket/sys_socket/sys/socket.h +++ b/components/net/sal_socket/include/socket/sys_socket/sys/socket.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/net/sal_socket/socket/net_netdb.c b/components/net/sal_socket/socket/net_netdb.c index bc76a48965..03b995c68d 100644 --- a/components/net/sal_socket/socket/net_netdb.c +++ b/components/net/sal_socket/socket/net_netdb.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/net/sal_socket/socket/net_sockets.c b/components/net/sal_socket/socket/net_sockets.c index a53b2f1f9c..3637635d50 100644 --- a/components/net/sal_socket/socket/net_sockets.c +++ b/components/net/sal_socket/socket/net_sockets.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -95,7 +95,7 @@ int shutdown(int s, int how) rt_set_errno(-EBADF); return -1; } - + if (sal_shutdown(socket, how) == 0) { error = 0; @@ -105,7 +105,7 @@ int shutdown(int s, int how) rt_set_errno(-ENOTSOCK); error = -1; } - + fd_put(d); return error; diff --git a/components/net/sal_socket/src/sal_socket.c b/components/net/sal_socket/src/sal_socket.c index edd5cd9a72..2781088711 100644 --- a/components/net/sal_socket/src/sal_socket.c +++ b/components/net/sal_socket/src/sal_socket.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/net/uip/rt-thread/uip_ethernetif.c b/components/net/uip/rt-thread/uip_ethernetif.c index fa4e52461e..593fdba2b5 100644 --- a/components/net/uip/rt-thread/uip_ethernetif.c +++ b/components/net/uip/rt-thread/uip_ethernetif.c @@ -14,9 +14,9 @@ /* * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, @@ -25,21 +25,21 @@ * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. + * derived from this software without specific prior written permission. * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY * OF SUCH DAMAGE. * * This file is part of the lwIP TCP/IP stack. - * + * * Author: Adam Dunkels * */ @@ -62,19 +62,19 @@ extern u16_t uip_len, uip_slen; static struct rt_mailbox eth_rx_thread_mb; static struct rt_thread eth_rx_thread; #ifndef RT_LWIP_ETHTHREAD_PRIORITY -#define RT_ETHERNETIF_THREAD_PREORITY 0x90 +#define RT_ETHERNETIF_THREAD_PREORITY 0x90 static char eth_rx_thread_mb_pool[48 * 4]; static char eth_rx_thread_stack[1024]; #else -#define RT_ETHERNETIF_THREAD_PREORITY RT_LWIP_ETHTHREAD_PRIORITY +#define RT_ETHERNETIF_THREAD_PREORITY RT_LWIP_ETHTHREAD_PRIORITY static char eth_rx_thread_mb_pool[RT_LWIP_ETHTHREAD_MBOX_SIZE * 4]; static char eth_rx_thread_stack[RT_LWIP_ETHTHREAD_STACKSIZE]; #endif struct eth_tx_msg { - struct netif *netif; - struct pbuf *buf; + struct netif *netif; + struct pbuf *buf; }; static struct rt_mailbox eth_tx_thread_mb; static struct rt_thread eth_tx_thread; @@ -89,225 +89,225 @@ static char eth_tx_thread_stack[RT_LWIP_ETHTHREAD_STACKSIZE]; /* the interface provided to uIP */ err_t eth_init(struct netif *netif) { - return 0; + return 0; } extern err_t ethernetif_linkoutput(struct netif *netif, struct pbuf *p); err_t eth_input(struct pbuf *p,struct netif *inp) { - struct eth_hdr *ethhdr; + struct eth_hdr *ethhdr; - if(p != RT_NULL) - { + if(p != RT_NULL) + { #ifdef LINK_STATS - //LINK_STATS_INC(link.recv); -#endif LINK_STATS - - ethhdr = p->payload; - - switch(uip_htons(ethhdr->type)) - { - case ETHTYPE_IP: //ETHTYPE_IP - etharp_ip_input(inp, p); - pbuf_header(p, -((rt_int16_t)sizeof(struct eth_hdr))); - if (tcpip_input(p, inp) != ERR_OK) - { - // discard packet - pbuf_free(p); - } - break; - - case ETHTYPE_ARP: - etharp_arp_input(inp, (struct eth_addr *)inp->hwaddr, p); - break; - - default: - pbuf_free(p); - p = RT_NULL; - break; - } - } + //LINK_STATS_INC(link.recv); +#endif LINK_STATS + + ethhdr = p->payload; + + switch(uip_htons(ethhdr->type)) + { + case ETHTYPE_IP: //ETHTYPE_IP + etharp_ip_input(inp, p); + pbuf_header(p, -((rt_int16_t)sizeof(struct eth_hdr))); + if (tcpip_input(p, inp) != ERR_OK) + { + // discard packet + pbuf_free(p); + } + break; + + case ETHTYPE_ARP: + etharp_arp_input(inp, (struct eth_addr *)inp->hwaddr, p); + break; + + default: + pbuf_free(p); + p = RT_NULL; + break; + } + } return ERR_OK; } err_t ethernetif_output(struct netif *netif, struct pbuf *p, struct ip_addr *ipaddr) { - return etharp_output(netif, p, ipaddr); + return etharp_output(netif, p, ipaddr); } err_t ethernetif_linkoutput(struct netif *netif, struct pbuf *p) { - struct eth_tx_msg msg; - struct eth_device* enetif; + struct eth_tx_msg msg; + struct eth_device* enetif; - enetif = (struct eth_device*)netif->state; + enetif = (struct eth_device*)netif->state; - /* send a message to eth tx thread */ - msg.netif = netif; - msg.buf = p; - if (rt_mb_send(ð_tx_thread_mb, (rt_uint32_t) &msg) == RT_EOK) - { - /* waiting for ack */ - rt_sem_take(&(enetif->tx_ack), RT_WAITING_FOREVER); - } + /* send a message to eth tx thread */ + msg.netif = netif; + msg.buf = p; + if (rt_mb_send(ð_tx_thread_mb, (rt_uint32_t) &msg) == RT_EOK) + { + /* waiting for ack */ + rt_sem_take(&(enetif->tx_ack), RT_WAITING_FOREVER); + } - return ERR_OK; + return ERR_OK; } /* ethernetif APIs */ rt_err_t eth_device_init(struct eth_device* dev, const char* name) { - struct netif* netif; + struct netif* netif; uip_ipaddr_t ipaddr; - netif = (struct netif*) rt_malloc (sizeof(struct netif)); - if (netif == RT_NULL) - { - rt_kprintf("malloc netif failed\n"); - return -RT_ERROR; - } - rt_memset(netif, 0, sizeof(struct netif)); - - /* set netif */ - dev->netif = netif; - /* register to rt-thread device manager */ - rt_device_register(&(dev->parent), name, RT_DEVICE_FLAG_RDWR); - dev->parent.type = RT_Device_Class_NetIf; - rt_sem_init(&(dev->tx_ack), name, 0, RT_IPC_FLAG_FIFO); - - /* set name */ - netif->name[0] = name[0]; - netif->name[1] = name[1]; - - /* set hw address to 6 */ - netif->hwaddr_len = 6; - /* maximum transfer unit */ - netif->mtu = ETHERNET_MTU; - /* broadcast capability */ - netif->flags = NETIF_FLAG_BROADCAST; - + netif = (struct netif*) rt_malloc (sizeof(struct netif)); + if (netif == RT_NULL) + { + rt_kprintf("malloc netif failed\n"); + return -RT_ERROR; + } + rt_memset(netif, 0, sizeof(struct netif)); + + /* set netif */ + dev->netif = netif; + /* register to rt-thread device manager */ + rt_device_register(&(dev->parent), name, RT_DEVICE_FLAG_RDWR); + dev->parent.type = RT_Device_Class_NetIf; + rt_sem_init(&(dev->tx_ack), name, 0, RT_IPC_FLAG_FIFO); + + /* set name */ + netif->name[0] = name[0]; + netif->name[1] = name[1]; + + /* set hw address to 6 */ + netif->hwaddr_len = 6; + /* maximum transfer unit */ + netif->mtu = ETHERNET_MTU; + /* broadcast capability */ + netif->flags = NETIF_FLAG_BROADCAST; + #if LWIP_IGMP - /* igmp support */ - netif->flags |= NETIF_FLAG_IGMP; + /* igmp support */ + netif->flags |= NETIF_FLAG_IGMP; #endif - /* get hardware address */ - rt_device_control(&(dev->parent), NIOCTL_GADDR, netif->hwaddr); - - /* set output */ - netif->output = ethernetif_output; - netif->linkoutput = ethernetif_linkoutput; - - /* add netif to lwip */ - - if (netif_add(netif, IP_ADDR_ANY, IP_ADDR_BROADCAST, IP_ADDR_ANY, dev, - eth_init, eth_input) == RT_NULL) - { - /* failed, unregister device and free netif */ - rt_device_unregister(&(dev->parent)); - rt_free(netif); - return -RT_ERROR; - } - - netif_set_default(netif); - return RT_EOK; + /* get hardware address */ + rt_device_control(&(dev->parent), NIOCTL_GADDR, netif->hwaddr); + + /* set output */ + netif->output = ethernetif_output; + netif->linkoutput = ethernetif_linkoutput; + + /* add netif to lwip */ + + if (netif_add(netif, IP_ADDR_ANY, IP_ADDR_BROADCAST, IP_ADDR_ANY, dev, + eth_init, eth_input) == RT_NULL) + { + /* failed, unregister device and free netif */ + rt_device_unregister(&(dev->parent)); + rt_free(netif); + return -RT_ERROR; + } + + netif_set_default(netif); + return RT_EOK; } /* ethernet buffer */ void eth_tx_thread_entry(void* parameter) { - struct eth_tx_msg* msg; - - while (1) - { - if (rt_mb_recv(ð_tx_thread_mb, (rt_uint32_t*)&msg, RT_WAITING_FOREVER) == RT_EOK) - { - struct eth_device* enetif; - - RT_ASSERT(msg->netif != RT_NULL); - RT_ASSERT(msg->buf != RT_NULL); - - enetif = (struct eth_device*)msg->netif->state; - if (enetif != RT_NULL) - { - /* call driver's interface */ - if (enetif->eth_tx(&(enetif->parent), msg->buf) != RT_EOK) - { - rt_kprintf("transmit eth packet failed\n"); - } - } - - /* send ack */ - rt_sem_release(&(enetif->tx_ack)); - } - } + struct eth_tx_msg* msg; + + while (1) + { + if (rt_mb_recv(ð_tx_thread_mb, (rt_uint32_t*)&msg, RT_WAITING_FOREVER) == RT_EOK) + { + struct eth_device* enetif; + + RT_ASSERT(msg->netif != RT_NULL); + RT_ASSERT(msg->buf != RT_NULL); + + enetif = (struct eth_device*)msg->netif->state; + if (enetif != RT_NULL) + { + /* call driver's interface */ + if (enetif->eth_tx(&(enetif->parent), msg->buf) != RT_EOK) + { + rt_kprintf("transmit eth packet failed\n"); + } + } + + /* send ack */ + rt_sem_release(&(enetif->tx_ack)); + } + } } /* ethernet buffer */ void eth_rx_thread_entry(void* parameter) { - struct eth_device* device; - - while (1) - { - if (rt_mb_recv(ð_rx_thread_mb, (rt_uint32_t*)&device, RT_WAITING_FOREVER) == RT_EOK) - { - struct pbuf *p; - - /* receive all of buffer */ - while (1) - { - p = device->eth_rx(&(device->parent)); - if (p != RT_NULL) - { - /* notify to upper layer */ - eth_input(p, device->netif); - } - else break; - } - } - } + struct eth_device* device; + + while (1) + { + if (rt_mb_recv(ð_rx_thread_mb, (rt_uint32_t*)&device, RT_WAITING_FOREVER) == RT_EOK) + { + struct pbuf *p; + + /* receive all of buffer */ + while (1) + { + p = device->eth_rx(&(device->parent)); + if (p != RT_NULL) + { + /* notify to upper layer */ + eth_input(p, device->netif); + } + else break; + } + } + } } rt_err_t eth_device_ready(struct eth_device* dev) { - /* post message to ethernet thread */ - return rt_mb_send(ð_rx_thread_mb, (rt_uint32_t)dev); + /* post message to ethernet thread */ + return rt_mb_send(ð_rx_thread_mb, (rt_uint32_t)dev); } rt_err_t eth_system_device_init() { - rt_err_t result = RT_EOK; - - /* init rx thread */ - /* init mailbox and create ethernet thread */ - result = rt_mb_init(ð_rx_thread_mb, "erxmb", - ð_rx_thread_mb_pool[0], sizeof(eth_rx_thread_mb_pool)/4, - RT_IPC_FLAG_FIFO); - RT_ASSERT(result == RT_EOK); - - result = rt_thread_init(ð_rx_thread, "erx", eth_rx_thread_entry, RT_NULL, - ð_rx_thread_stack[0], sizeof(eth_rx_thread_stack), - RT_ETHERNETIF_THREAD_PREORITY, 16); - RT_ASSERT(result == RT_EOK); - - result = rt_thread_startup(ð_rx_thread); - RT_ASSERT(result == RT_EOK); - - /* init tx thread */ - /* init mailbox and create ethernet thread */ - - result = rt_mb_init(ð_tx_thread_mb, "etxmb", - ð_tx_thread_mb_pool[0], sizeof(eth_tx_thread_mb_pool)/4, - RT_IPC_FLAG_FIFO); - RT_ASSERT(result == RT_EOK); - - result = rt_thread_init(ð_tx_thread, "etx", eth_tx_thread_entry, RT_NULL, - ð_tx_thread_stack[0], sizeof(eth_tx_thread_stack), - RT_ETHERNETIF_THREAD_PREORITY, 16); - RT_ASSERT(result == RT_EOK); - - result = rt_thread_startup(ð_tx_thread); - RT_ASSERT(result == RT_EOK); - - return result; + rt_err_t result = RT_EOK; + + /* init rx thread */ + /* init mailbox and create ethernet thread */ + result = rt_mb_init(ð_rx_thread_mb, "erxmb", + ð_rx_thread_mb_pool[0], sizeof(eth_rx_thread_mb_pool)/4, + RT_IPC_FLAG_FIFO); + RT_ASSERT(result == RT_EOK); + + result = rt_thread_init(ð_rx_thread, "erx", eth_rx_thread_entry, RT_NULL, + ð_rx_thread_stack[0], sizeof(eth_rx_thread_stack), + RT_ETHERNETIF_THREAD_PREORITY, 16); + RT_ASSERT(result == RT_EOK); + + result = rt_thread_startup(ð_rx_thread); + RT_ASSERT(result == RT_EOK); + + /* init tx thread */ + /* init mailbox and create ethernet thread */ + + result = rt_mb_init(ð_tx_thread_mb, "etxmb", + ð_tx_thread_mb_pool[0], sizeof(eth_tx_thread_mb_pool)/4, + RT_IPC_FLAG_FIFO); + RT_ASSERT(result == RT_EOK); + + result = rt_thread_init(ð_tx_thread, "etx", eth_tx_thread_entry, RT_NULL, + ð_tx_thread_stack[0], sizeof(eth_tx_thread_stack), + RT_ETHERNETIF_THREAD_PREORITY, 16); + RT_ASSERT(result == RT_EOK); + + result = rt_thread_startup(ð_tx_thread); + RT_ASSERT(result == RT_EOK); + + return result; } diff --git a/components/utilities/ulog/backend/console_be.c b/components/utilities/ulog/backend/console_be.c index 95dd547426..b84cd95d09 100644 --- a/components/utilities/ulog/backend/console_be.c +++ b/components/utilities/ulog/backend/console_be.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/utilities/ulog/syslog/syslog.c b/components/utilities/ulog/syslog/syslog.c index 4c290bed52..a081db6eb6 100644 --- a/components/utilities/ulog/syslog/syslog.c +++ b/components/utilities/ulog/syslog/syslog.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/utilities/ulog/syslog/syslog.h b/components/utilities/ulog/syslog/syslog.h index 43eec7125f..8e4d5ba15f 100644 --- a/components/utilities/ulog/syslog/syslog.h +++ b/components/utilities/ulog/syslog/syslog.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/utilities/ulog/ulog.c b/components/utilities/ulog/ulog.c index 7610089298..757fa5276c 100644 --- a/components/utilities/ulog/ulog.c +++ b/components/utilities/ulog/ulog.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/utilities/ulog/ulog.h b/components/utilities/ulog/ulog.h index c78d72eda5..1fab86f389 100644 --- a/components/utilities/ulog/ulog.h +++ b/components/utilities/ulog/ulog.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/utilities/ulog/ulog_def.h b/components/utilities/ulog/ulog_def.h index de5e82fcc5..d1b276de7d 100644 --- a/components/utilities/ulog/ulog_def.h +++ b/components/utilities/ulog/ulog_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -102,8 +102,8 @@ extern "C" { #define ulog_hex(TAG, width, buf, size) ulog_hexdump(TAG, width, buf, size) #else #define ulog_hex(TAG, width, buf, size) -#endif /* (LOG_LVL >= LOG_LVL_DBG) && (ULOG_OUTPUT_LVL >= LOG_LVL_DBG) */ - +#endif /* (LOG_LVL >= LOG_LVL_DBG) && (ULOG_OUTPUT_LVL >= LOG_LVL_DBG) */ + /* assert for developer. */ #ifdef ULOG_ASSERT_ENABLE #define ULOG_ASSERT(EXPR) \ @@ -142,7 +142,7 @@ extern "C" { #define log_d LOG_D #define log_v LOG_D #define log_raw LOG_RAW -#define log_hex LOG_HEX +#define log_hex LOG_HEX #define ELOG_LVL_ASSERT LOG_LVL_ASSERT #define ELOG_LVL_ERROR LOG_LVL_ERROR #define ELOG_LVL_WARN LOG_LVL_WARNING diff --git a/components/utilities/utest/utest.c b/components/utilities/utest/utest.c index 6500ae2fbe..325823de8a 100644 --- a/components/utilities/utest/utest.c +++ b/components/utilities/utest/utest.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/utilities/utest/utest.h b/components/utilities/utest/utest.h index 8d83fa3184..6822c1a137 100644 --- a/components/utilities/utest/utest.h +++ b/components/utilities/utest/utest.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,13 +22,13 @@ extern "C" { /** * utest_error - * + * * @brief Test result. - * + * * @member UTEST_PASSED Test success. * @member UTEST_FAILED Test failed. * @member UTEST_PASSED Test skipped. - * + * */ enum utest_error { @@ -40,13 +40,13 @@ typedef enum utest_error utest_err_e; /** * utest - * + * * @brief utest data structure. - * + * * @member error Error number from enum `utest_error`. * @member passed_num Total number of tests passed. * @member failed_num Total number of tests failed. - * + * */ struct utest { @@ -58,16 +58,16 @@ typedef struct utest *utest_t; /** * utest_tc_export - * + * * @brief utest testcase data structure. * Will export the data to `UtestTcTab` section in flash. - * + * * @member name Testcase name. * @member run_timeout Testcase maximum test time (Time unit: seconds). * @member init Necessary initialization before executing the test case function. * @member tc Total number of tests failed. * @member cleanup Total number of tests failed. - * + * */ struct utest_tc_export { const char *name; @@ -80,61 +80,61 @@ typedef struct utest_tc_export *utest_tc_export_t; /** * test_unit_func - * + * * @brief Unit test handler function pointer. - * + * */ typedef void (*test_unit_func)(void); /** * utest_unit_run - * + * * @brief Unit test function executor. * No need for the user to call this function directly - * + * * @param func Unit test function. * @param unit_func_name Unit test function name. - * + * * @return void - * + * */ void utest_unit_run(test_unit_func func, const char *unit_func_name); /** * utest_handle_get - * + * * @brief Get the utest data structure handle. * No need for the user to call this function directly - * + * * @param void - * + * * @return utest_t type. (struct utest *) - * + * */ utest_t utest_handle_get(void); /** * UTEST_NAME_MAX_LEN - * + * * @brief Testcase name maximum length. - * + * */ #define UTEST_NAME_MAX_LEN (128u) /** * UTEST_TC_EXPORT - * + * * @brief Export testcase function to `UtestTcTab` section in flash. * Used in application layer. - * + * * @param testcase The testcase function. * @param name The testcase name. * @param init The initialization function of the test case. * @param cleanup The cleanup function of the test case. * @param timeout Testcase maximum test time (Time unit: seconds). - * + * * @return None - * + * */ #define UTEST_TC_EXPORT(testcase, name, init, cleanup, timeout) \ RT_USED static const struct utest_tc_export _utest_testcase \ @@ -149,14 +149,14 @@ utest_t utest_handle_get(void); /** * UTEST_UNIT_RUN - * + * * @brief Unit test function executor. * Used in `testcase` function in application. - * + * * @param test_unit_func Unit test function - * + * * @return None - * + * */ #define UTEST_UNIT_RUN(test_unit_func) \ utest_unit_run(test_unit_func, #test_unit_func); \ diff --git a/components/utilities/utest/utest_assert.h b/components/utilities/utest/utest_assert.h index d83279272e..2e2007e773 100644 --- a/components/utilities/utest/utest_assert.h +++ b/components/utilities/utest/utest_assert.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -30,10 +30,10 @@ void utest_assert_buf(const char *a, const char *b, rt_size_t sz, rt_bool_t equa /** * uassert_x macros - * + * * @brief Get the utest data structure handle. * No need for the user to call this function directly. - * + * * @macro uassert_true if @value is true, not assert, means passing. * @macro uassert_false if @value is false, not assert, means passing. * @macro uassert_null if @value is null, not assert, means passing. @@ -46,7 +46,7 @@ void utest_assert_buf(const char *a, const char *b, rt_size_t sz, rt_bool_t equa * @macro uassert_buf_not_equal if @a not equal to @b, not assert, means passing. buf type test. * @macro uassert_in_range if @value is in range of min and max, not assert, means passing. * @macro uassert_not_in_range if @value is not in range of min and max, not assert, means passing. - * + * */ #define uassert_true(value) __utest_assert(value, "(" #value ") is false") #define uassert_false(value) __utest_assert(!(value), "(" #value ") is true") @@ -62,7 +62,7 @@ void utest_assert_buf(const char *a, const char *b, rt_size_t sz, rt_bool_t equa #define uassert_buf_equal(a, b, sz) utest_assert_buf((const char*)(a), (const char*)(b), (sz), RT_TRUE, __FILE__, __LINE__, __func__, "buf not equal") #define uassert_buf_not_equal(a, b, sz) utest_assert_buf((const char*)(a), (const char*)(b), (sz), RT_FALSE, __FILE__, __LINE__, __func__, "buf equal") -#define uassert_in_range(value, min, max) __utest_assert(((value >= min) && (value <= max)), "(" #value ") not in range("#min","#max")") +#define uassert_in_range(value, min, max) __utest_assert(((value >= min) && (value <= max)), "(" #value ") not in range("#min","#max")") #define uassert_not_in_range(value, min, max) __utest_assert(!((value >= min) && (value <= max)), "(" #value ") in range("#min","#max")") #ifdef __cplusplus diff --git a/components/utilities/utest/utest_log.h b/components/utilities/utest/utest_log.h index 0403268351..6aa54386a8 100644 --- a/components/utilities/utest/utest_log.h +++ b/components/utilities/utest/utest_log.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/utilities/ymodem/ymodem.c b/components/utilities/ymodem/ymodem.c index 07055db615..8e4b04258f 100644 --- a/components/utilities/ymodem/ymodem.c +++ b/components/utilities/ymodem/ymodem.c @@ -13,7 +13,7 @@ #include #include "ymodem.h" -#ifdef YMODEM_USING_CRC_TABLE +#ifdef YMODEM_USING_CRC_TABLE static const rt_uint16_t ccitt_table[256] = { 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50A5, 0x60C6, 0x70E7, diff --git a/components/vbus/prio_queue.c b/components/vbus/prio_queue.c index bca3cdcd9a..f7f5bb05ac 100644 --- a/components/vbus/prio_queue.c +++ b/components/vbus/prio_queue.c @@ -1,6 +1,6 @@ /* * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: diff --git a/components/vbus/prio_queue.h b/components/vbus/prio_queue.h index 7358ffdb23..3e214212f7 100644 --- a/components/vbus/prio_queue.h +++ b/components/vbus/prio_queue.h @@ -1,6 +1,6 @@ /* * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: diff --git a/components/vbus/share_hdr/vbus_api.h b/components/vbus/share_hdr/vbus_api.h index db6cb7b72c..a643822a9c 100644 --- a/components/vbus/share_hdr/vbus_api.h +++ b/components/vbus/share_hdr/vbus_api.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/components/vbus/vbus.c b/components/vbus/vbus.c index 8add15d9db..e24a0eed0e 100644 --- a/components/vbus/vbus.c +++ b/components/vbus/vbus.c @@ -1,6 +1,6 @@ /* * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: @@ -899,8 +899,8 @@ int rt_vbus_request_chn(struct rt_vbus_request *req, int timeout) { int i, chnr, err; - size_t plen = rt_strlen(req->name) + 2; - unsigned char *pbuf; + size_t plen = rt_strlen(req->name) + 2; + unsigned char *pbuf; rt_ubase_t lvl; lvl = rt_hw_interrupt_disable(); @@ -930,8 +930,8 @@ int rt_vbus_request_chn(struct rt_vbus_request *req, goto _waitforcmp; } - pbuf = rt_malloc(plen); - if (!pbuf) + pbuf = rt_malloc(plen); + if (!pbuf) { rt_hw_interrupt_enable(lvl); return -RT_ENOMEM; @@ -944,7 +944,7 @@ int rt_vbus_request_chn(struct rt_vbus_request *req, rt_memcpy(pbuf+1, req->name, plen-1); vbus_verbose("%s --> remote\n", dump_cmd_pkt(pbuf, plen)); - err = _chn0_post(pbuf, plen, RT_WAITING_FOREVER); + err = _chn0_post(pbuf, plen, RT_WAITING_FOREVER); rt_free(pbuf); _waitforcmp: diff --git a/components/vbus/vbus.h b/components/vbus/vbus.h index ea271d8e79..9434daf9ed 100644 --- a/components/vbus/vbus.h +++ b/components/vbus/vbus.h @@ -1,6 +1,6 @@ /* * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: @@ -51,14 +51,14 @@ struct rt_vbus_data { }; struct rt_vbus_wm_cfg { - unsigned int low, high; + unsigned int low, high; }; struct rt_vbus_request { - unsigned char prio; - const char *name; - int is_server; - struct rt_vbus_wm_cfg recv_wm, post_wm; + unsigned char prio; + const char *name; + int is_server; + struct rt_vbus_wm_cfg recv_wm, post_wm; }; /** Request a channel. diff --git a/components/vbus/vbus_chnx.c b/components/vbus/vbus_chnx.c index d064d6f1f2..8529989f63 100644 --- a/components/vbus/vbus_chnx.c +++ b/components/vbus/vbus_chnx.c @@ -1,6 +1,6 @@ /* * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: diff --git a/components/vbus/watermark_queue.c b/components/vbus/watermark_queue.c index e56790d286..7a39b11359 100644 --- a/components/vbus/watermark_queue.c +++ b/components/vbus/watermark_queue.c @@ -1,6 +1,6 @@ /* * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: diff --git a/components/vbus/watermark_queue.h b/components/vbus/watermark_queue.h index 0ecc52d8ff..50bbc69577 100644 --- a/components/vbus/watermark_queue.h +++ b/components/vbus/watermark_queue.h @@ -1,6 +1,6 @@ /* * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: diff --git a/components/vmm/vmm.c b/components/vmm/vmm.c index 7d6f9875db..f91858b83e 100644 --- a/components/vmm/vmm.c +++ b/components/vmm/vmm.c @@ -1,9 +1,9 @@ /* * VMM startup file. * - * COPYRIGHT (C) 2013-2014, Real-Thread Information Technology Ltd + * COPYRIGHT (C) 2013-2021, Real-Thread Information Technology Ltd * All rights reserved - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: diff --git a/components/vmm/vmm.h b/components/vmm/vmm.h index 17bba8439b..93788a9b1e 100644 --- a/components/vmm/vmm.h +++ b/components/vmm/vmm.h @@ -1,9 +1,9 @@ /* * VMM startup file. * - * COPYRIGHT (C) 2013-2014, Real-Thread Information Technology Ltd + * COPYRIGHT (C) 2013-2021, Real-Thread Information Technology Ltd * All rights reserved - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: diff --git a/components/vmm/vmm_context.c b/components/vmm/vmm_context.c index 91641a483a..e59f53200c 100644 --- a/components/vmm/vmm_context.c +++ b/components/vmm/vmm_context.c @@ -1,7 +1,7 @@ /* - * COPYRIGHT (C) 2013-2014, Real-Thread Information Technology Ltd + * COPYRIGHT (C) 2013-2021, Real-Thread Information Technology Ltd * All rights reserved - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: diff --git a/components/vmm/vmm_context.h b/components/vmm/vmm_context.h index 019b681459..42bc9df164 100644 --- a/components/vmm/vmm_context.h +++ b/components/vmm/vmm_context.h @@ -1,7 +1,7 @@ /* - * COPYRIGHT (C) 2013-2014, Real-Thread Information Technology Ltd + * COPYRIGHT (C) 2013-2021, Real-Thread Information Technology Ltd * All rights reserved - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: diff --git a/components/vmm/vmm_iomap.c b/components/vmm/vmm_iomap.c index 55bd1ac36e..526090abaa 100644 --- a/components/vmm/vmm_iomap.c +++ b/components/vmm/vmm_iomap.c @@ -1,9 +1,9 @@ /* * VMM IO map table * - * COPYRIGHT (C) 2013-2014, Real-Thread Information Technology Ltd + * COPYRIGHT (C) 2013-2021, Real-Thread Information Technology Ltd * All rights reserved - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: diff --git a/components/vmm/vmm_vector.c b/components/vmm/vmm_vector.c index d7909607ce..580a88f419 100644 --- a/components/vmm/vmm_vector.c +++ b/components/vmm/vmm_vector.c @@ -1,9 +1,9 @@ /* * VMM vector handle - * - * COPYRIGHT (C) 2013-2014, Real-Thread Information Technology Ltd + * + * COPYRIGHT (C) 2013-2021, Real-Thread Information Technology Ltd * All rights reserved - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: @@ -23,9 +23,9 @@ void vmm_guest_isr(int irqno, void* parameter) void vmm_vector_init(void) { - rt_hw_interrupt_install(RT_VMM_VIRQ_TRIGGER, vmm_guest_isr, RT_NULL, "virq"); - rt_hw_interrupt_umask(RT_VMM_VIRQ_TRIGGER); + rt_hw_interrupt_install(RT_VMM_VIRQ_TRIGGER, vmm_guest_isr, RT_NULL, "virq"); + rt_hw_interrupt_umask(RT_VMM_VIRQ_TRIGGER); - return; + return; } diff --git a/documentation/doxygen/kernel.h b/documentation/doxygen/kernel.h index b54144780b..0702f3556c 100644 --- a/documentation/doxygen/kernel.h +++ b/documentation/doxygen/kernel.h @@ -32,10 +32,10 @@ * round-robin scheduling is used for this case. * - The time of scheduler to choose the next highest ready thread is determinant. * - There are four status in thread management - * -# Initialization - * -# Running/Ready - * -# Blocked - * -# Closed + * -# Initialization + * -# Running/Ready + * -# Blocked + * -# Closed * - The number of threads in the system is unlimited, only related with RAM. */ diff --git a/documentation/doxygen/systeminit.h b/documentation/doxygen/systeminit.h index d62aca59bb..2167e2d6f0 100644 --- a/documentation/doxygen/systeminit.h +++ b/documentation/doxygen/systeminit.h @@ -7,7 +7,7 @@ * * @brief System initialization procedure. * - * When RT-Thread operating system starts up, the basic operating system facility + * When RT-Thread operating system starts up, the basic operating system facility * initialization routines must be invoked. * * The suggested initialization sequence is: diff --git a/examples/file/listdir.c b/examples/file/listdir.c index cf91bc77d4..eee3f04f6e 100644 --- a/examples/file/listdir.c +++ b/examples/file/listdir.c @@ -17,37 +17,37 @@ static char fullpath[256]; void list_dir(const char* path) { - DIR *dir; + DIR *dir; - dir = opendir(path); - if (dir != RT_NULL) - { - struct dirent* dirent; - struct stat s; + dir = opendir(path); + if (dir != RT_NULL) + { + struct dirent* dirent; + struct stat s; - do - { - dirent = readdir(dir); - if (dirent == RT_NULL) break; - rt_memset(&s, 0, sizeof(struct stat)); + do + { + dirent = readdir(dir); + if (dirent == RT_NULL) break; + rt_memset(&s, 0, sizeof(struct stat)); - /* build full path for each file */ - rt_sprintf(fullpath, "%s/%s", path, dirent->d_name); + /* build full path for each file */ + rt_sprintf(fullpath, "%s/%s", path, dirent->d_name); - stat(fullpath, &s); - if ( s.st_mode & DFS_S_IFDIR ) - { - rt_kprintf("%s\t\t\n", dirent->d_name); - } - else - { - rt_kprintf("%s\t\t%lu\n", dirent->d_name, s.st_size); - } - } while (dirent != RT_NULL); + stat(fullpath, &s); + if ( s.st_mode & DFS_S_IFDIR ) + { + rt_kprintf("%s\t\t\n", dirent->d_name); + } + else + { + rt_kprintf("%s\t\t%lu\n", dirent->d_name, s.st_size); + } + } while (dirent != RT_NULL); - closedir(dir); - } - else rt_kprintf("open %s directory failed\n", path); + closedir(dir); + } + else rt_kprintf("open %s directory failed\n", path); } #ifdef RT_USING_FINSH diff --git a/examples/file/readspeed.c b/examples/file/readspeed.c index 52f15b627b..aeeb43f865 100644 --- a/examples/file/readspeed.c +++ b/examples/file/readspeed.c @@ -50,9 +50,9 @@ void readspeed(const char* filename, int block_size) } tick = rt_tick_get() - tick; - /* close file and release memory */ + /* close file and release memory */ close(fd); - rt_free(buff_ptr); + rt_free(buff_ptr); /* calculate read speed */ rt_kprintf("File read speed: %d byte/s\n", total_length /tick * RT_TICK_PER_SECOND); diff --git a/examples/file/writespeed.c b/examples/file/writespeed.c index ab6946888f..ff96b81b49 100644 --- a/examples/file/writespeed.c +++ b/examples/file/writespeed.c @@ -36,31 +36,31 @@ void writespeed(const char* filename, int total_length, int block_size) return; } - /* prepare write data */ - for (index = 0; index < block_size; index++) - { - buff_ptr[index] = index; - } - index = 0; + /* prepare write data */ + for (index = 0; index < block_size; index++) + { + buff_ptr[index] = index; + } + index = 0; - /* get the beginning tick */ + /* get the beginning tick */ tick = rt_tick_get(); - while (index < total_length / block_size) - { - length = write(fd, buff_ptr, block_size); - if (length != block_size) - { - rt_kprintf("write failed\n"); - break; - } + while (index < total_length / block_size) + { + length = write(fd, buff_ptr, block_size); + if (length != block_size) + { + rt_kprintf("write failed\n"); + break; + } - index ++; - } + index ++; + } tick = rt_tick_get() - tick; - /* close file and release memory */ + /* close file and release memory */ close(fd); - rt_free(buff_ptr); + rt_free(buff_ptr); /* calculate write speed */ rt_kprintf("File write speed: %d byte/s\n", total_length / tick * RT_TICK_PER_SECOND); diff --git a/examples/kernel/tc_comm.h b/examples/kernel/tc_comm.h index aee1fec2d2..c72c91ad53 100644 --- a/examples/kernel/tc_comm.h +++ b/examples/kernel/tc_comm.h @@ -1,7 +1,7 @@ #ifndef __TC_COMM_H__ #define __TC_COMM_H__ -/* +/* * RT-Thread TestCase * */ diff --git a/examples/pm/timer_app.c b/examples/pm/timer_app.c index b7ff675b39..5797693149 100644 --- a/examples/pm/timer_app.c +++ b/examples/pm/timer_app.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/examples/pm/wakeup_app.c b/examples/pm/wakeup_app.c index 0d4c42a997..d287bf74ec 100644 --- a/examples/pm/wakeup_app.c +++ b/examples/pm/wakeup_app.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/examples/test/net_test.c b/examples/test/net_test.c index 53bd2836fa..b37543eafc 100644 --- a/examples/test/net_test.c +++ b/examples/test/net_test.c @@ -7,108 +7,108 @@ #include #include -/* +/* * UDP echo server */ #define UDP_ECHO_PORT 7 rt_thread_t udpecho_tid = RT_NULL; void udpecho_entry(void *parameter) { - struct netconn *conn; - struct netbuf *buf; - struct ip_addr *addr; - unsigned short port; + struct netconn *conn; + struct netbuf *buf; + struct ip_addr *addr; + unsigned short port; - conn = netconn_new(NETCONN_UDP); - netconn_bind(conn, IP_ADDR_ANY, 7); + conn = netconn_new(NETCONN_UDP); + netconn_bind(conn, IP_ADDR_ANY, 7); - while(1) - { + while(1) + { /* received data to buffer */ -#if LWIP_VERSION_MINOR==3U - buf = netconn_recv(conn); +#if LWIP_VERSION_MINOR==3U + buf = netconn_recv(conn); #else - netconn_recv(conn, &buf); + netconn_recv(conn, &buf); #endif - - addr = netbuf_fromaddr(buf); - port = netbuf_fromport(buf); - /* send the data to buffer */ - netconn_connect(conn, addr, port); + addr = netbuf_fromaddr(buf); + port = netbuf_fromport(buf); + + /* send the data to buffer */ + netconn_connect(conn, addr, port); - /* reset address, and send to client */ -#if LWIP_VERSION_MINOR==3U - buf->addr = RT_NULL; + /* reset address, and send to client */ +#if LWIP_VERSION_MINOR==3U + buf->addr = RT_NULL; #else - buf->addr = *IP_ADDR_ANY; + buf->addr = *IP_ADDR_ANY; #endif - - netconn_send(conn, buf); - - /* release buffer */ - netbuf_delete(buf); - } + + netconn_send(conn, buf); + + /* release buffer */ + netbuf_delete(buf); + } } /* * UDP socket echo server */ -#define UDP_SOCKET_ECHO_PORT 700 -#define UDP_SOCKET_BUFFER_SIZE 4096 +#define UDP_SOCKET_ECHO_PORT 700 +#define UDP_SOCKET_BUFFER_SIZE 4096 rt_thread_t udpecho_socket_tid = RT_NULL; void udpecho_socket_entry(void *parameter) { - int sock; - int bytes_read; - char *recv_data; - rt_uint32_t addr_len; - struct sockaddr_in server_addr, client_addr; - - /* allocate the data buffer */ - recv_data = rt_malloc(UDP_SOCKET_BUFFER_SIZE); - if (recv_data == RT_NULL) - { - /* no memory yet */ - rt_kprintf("no memory\n"); - goto _exit; - } - /* create a UDP socket */ - if ((sock = socket(AF_INET, SOCK_DGRAM, 0)) == -1) - { - rt_kprintf("create socket error\n"); - goto _exit; - } - - /* initialize server address */ - server_addr.sin_family = AF_INET; - server_addr.sin_port = htons(UDP_SOCKET_ECHO_PORT); - server_addr.sin_addr.s_addr = INADDR_ANY; - rt_memset(&(server_addr.sin_zero),0, sizeof(server_addr.sin_zero)); - - /* bind socket to server address */ - if (bind(sock,(struct sockaddr *)&server_addr, - sizeof(struct sockaddr)) == -1) - { - /* bind failed */ - rt_kprintf("bind error\n"); - goto _exit; - } - - addr_len = sizeof(struct sockaddr); - while (1) - { - /* try to receive from UDP socket */ - bytes_read = recvfrom(sock, recv_data, UDP_SOCKET_BUFFER_SIZE, 0, - (struct sockaddr *)&client_addr, &addr_len); - - /* send back */ - sendto(sock, recv_data, bytes_read, 0, - (struct sockaddr *)&client_addr, addr_len); - } + int sock; + int bytes_read; + char *recv_data; + rt_uint32_t addr_len; + struct sockaddr_in server_addr, client_addr; + + /* allocate the data buffer */ + recv_data = rt_malloc(UDP_SOCKET_BUFFER_SIZE); + if (recv_data == RT_NULL) + { + /* no memory yet */ + rt_kprintf("no memory\n"); + goto _exit; + } + /* create a UDP socket */ + if ((sock = socket(AF_INET, SOCK_DGRAM, 0)) == -1) + { + rt_kprintf("create socket error\n"); + goto _exit; + } + + /* initialize server address */ + server_addr.sin_family = AF_INET; + server_addr.sin_port = htons(UDP_SOCKET_ECHO_PORT); + server_addr.sin_addr.s_addr = INADDR_ANY; + rt_memset(&(server_addr.sin_zero),0, sizeof(server_addr.sin_zero)); + + /* bind socket to server address */ + if (bind(sock,(struct sockaddr *)&server_addr, + sizeof(struct sockaddr)) == -1) + { + /* bind failed */ + rt_kprintf("bind error\n"); + goto _exit; + } + + addr_len = sizeof(struct sockaddr); + while (1) + { + /* try to receive from UDP socket */ + bytes_read = recvfrom(sock, recv_data, UDP_SOCKET_BUFFER_SIZE, 0, + (struct sockaddr *)&client_addr, &addr_len); + + /* send back */ + sendto(sock, recv_data, bytes_read, 0, + (struct sockaddr *)&client_addr, addr_len); + } _exit: - rt_free(recv_data); - return; + rt_free(recv_data); + return; } /* @@ -118,59 +118,59 @@ _exit: rt_thread_t tcpecho_tid = RT_NULL; void tcpecho_entry(void *parameter) { - struct netconn *conn, *newconn; - err_t err; + struct netconn *conn, *newconn; + err_t err; - /* Create a new connection identifier. */ - conn = netconn_new(NETCONN_TCP); + /* Create a new connection identifier. */ + conn = netconn_new(NETCONN_TCP); - /* Bind connection to well known port number 7. */ - netconn_bind(conn, NULL, TCP_ECHO_PORT); + /* Bind connection to well known port number 7. */ + netconn_bind(conn, NULL, TCP_ECHO_PORT); - /* Tell connection to go into listening mode. */ - netconn_listen(conn); + /* Tell connection to go into listening mode. */ + netconn_listen(conn); - while(1) - { - /* Grab new connection. */ -#if LWIP_VERSION_MINOR==3U - newconn = netconn_accept(conn); - if(newconn != NULL) + while(1) + { + /* Grab new connection. */ +#if LWIP_VERSION_MINOR==3U + newconn = netconn_accept(conn); + if(newconn != NULL) #else - err = netconn_accept(conn, &newconn); - if(err == ERR_OK) + err = netconn_accept(conn, &newconn); + if(err == ERR_OK) #endif - /* Process the new connection. */ - { - struct netbuf *buf; - void *data; - u16_t len; + /* Process the new connection. */ + { + struct netbuf *buf; + void *data; + u16_t len; #if LWIP_VERSION_MINOR==3U - while((buf = netconn_recv(newconn)) != NULL) + while((buf = netconn_recv(newconn)) != NULL) #else - while((err = netconn_recv(newconn, &buf)) == ERR_OK) + while((err = netconn_recv(newconn, &buf)) == ERR_OK) #endif - { - do - { - netbuf_data(buf, &data, &len); - err = netconn_write(newconn, data, len, NETCONN_COPY); - if(err != ERR_OK){} - } - while(netbuf_next(buf) >= 0); - netbuf_delete(buf); - } - /* Close connection and discard connection identifier. */ - netconn_delete(newconn); - } - } + { + do + { + netbuf_data(buf, &data, &len); + err = netconn_write(newconn, data, len, NETCONN_COPY); + if(err != ERR_OK){} + } + while(netbuf_next(buf) >= 0); + netbuf_delete(buf); + } + /* Close connection and discard connection identifier. */ + netconn_delete(newconn); + } + } } /* * TCP socket echo server */ -#define TCP_SOCKET_ECHO_PORT 700 -#define TCP_SOCKET_BUFFER_SIZE 4096 +#define TCP_SOCKET_ECHO_PORT 700 +#define TCP_SOCKET_BUFFER_SIZE 4096 rt_thread_t tcpecho_socket_tid = RT_NULL; void tcpecho_socket_entry(void *parameter) { @@ -179,79 +179,79 @@ void tcpecho_socket_entry(void *parameter) int sock = -1, connected, bytes_received; struct sockaddr_in server_addr, client_addr; - recv_data = rt_malloc(TCP_SOCKET_BUFFER_SIZE); - if (recv_data == RT_NULL) - { - rt_kprintf("no memory\n"); - goto _exit; - } - - /* create a TCP socket */ - if ((sock = socket(AF_INET, SOCK_STREAM, 0)) == -1) - { - rt_kprintf("create socket error\n"); - goto _exit; - } - - /* initialize server address */ - server_addr.sin_family = AF_INET; - server_addr.sin_port = htons(TCP_SOCKET_ECHO_PORT); - server_addr.sin_addr.s_addr = INADDR_ANY; - rt_memset(&(server_addr.sin_zero),8, sizeof(server_addr.sin_zero)); - - /* bind to server address */ - if (bind(sock, (struct sockaddr *)&server_addr, sizeof(struct sockaddr)) == -1) - { - rt_kprintf("bind address failed\n"); - goto _exit; + recv_data = rt_malloc(TCP_SOCKET_BUFFER_SIZE); + if (recv_data == RT_NULL) + { + rt_kprintf("no memory\n"); + goto _exit; + } + + /* create a TCP socket */ + if ((sock = socket(AF_INET, SOCK_STREAM, 0)) == -1) + { + rt_kprintf("create socket error\n"); + goto _exit; + } + + /* initialize server address */ + server_addr.sin_family = AF_INET; + server_addr.sin_port = htons(TCP_SOCKET_ECHO_PORT); + server_addr.sin_addr.s_addr = INADDR_ANY; + rt_memset(&(server_addr.sin_zero),8, sizeof(server_addr.sin_zero)); + + /* bind to server address */ + if (bind(sock, (struct sockaddr *)&server_addr, sizeof(struct sockaddr)) == -1) + { + rt_kprintf("bind address failed\n"); + goto _exit; } - /* listen */ - if (listen(sock, 5) == -1) - { - rt_kprintf("listen error\n"); - goto _exit; - } - - sin_size = sizeof(struct sockaddr_in); - while(1) - { - /* accept client connected */ - connected = accept(sock, (struct sockaddr *)&client_addr, &sin_size); - if (connected > 0) - { - int timeout; - - /* set timeout option */ - timeout = 5000; /* 5second */ - setsockopt(connected, SOL_SOCKET, SO_RCVTIMEO, &timeout, sizeof(timeout)); - - /* handle this client */ - while (1) - { - /* receive data from this connection */ - bytes_received = recv(connected,recv_data, TCP_SOCKET_BUFFER_SIZE, 0); - if (bytes_received <= 0) - { - rt_kprintf("close client connection, errno: %d\n", - rt_get_errno()); - /* connection closed. */ - lwip_close(connected); - break; - } - - /* send data to client */ - send(connected, recv_data, bytes_received, 0); - } - } + /* listen */ + if (listen(sock, 5) == -1) + { + rt_kprintf("listen error\n"); + goto _exit; + } + + sin_size = sizeof(struct sockaddr_in); + while(1) + { + /* accept client connected */ + connected = accept(sock, (struct sockaddr *)&client_addr, &sin_size); + if (connected > 0) + { + int timeout; + + /* set timeout option */ + timeout = 5000; /* 5second */ + setsockopt(connected, SOL_SOCKET, SO_RCVTIMEO, &timeout, sizeof(timeout)); + + /* handle this client */ + while (1) + { + /* receive data from this connection */ + bytes_received = recv(connected,recv_data, TCP_SOCKET_BUFFER_SIZE, 0); + if (bytes_received <= 0) + { + rt_kprintf("close client connection, errno: %d\n", + rt_get_errno()); + /* connection closed. */ + lwip_close(connected); + break; + } + + /* send data to client */ + send(connected, recv_data, bytes_received, 0); + } + } } _exit: - /* close socket */ - if (sock != -1) lwip_close(sock); - rt_free(recv_data); + /* close socket */ + if (sock != -1) lwip_close(sock); + rt_free(recv_data); - return ; + return ; } /* @@ -261,40 +261,40 @@ _exit: /* network test utilities entry */ void net_test(void) { - /* start UDP echo server */ - if (udpecho_tid == RT_NULL) - { - udpecho_tid = rt_thread_create("uecho", - udpecho_entry, RT_NULL, - 512, RT_THREAD_PRIORITY_MAX/2, 5); - if (udpecho_tid != RT_NULL) - rt_thread_startup(udpecho_tid); - } - if (udpecho_socket_tid == RT_NULL) - { - udpecho_socket_tid = rt_thread_create("uecho_s", - udpecho_socket_entry, RT_NULL, - 512, RT_THREAD_PRIORITY_MAX/2 + 1, 5); - if (udpecho_socket_tid != RT_NULL) - rt_thread_startup(udpecho_socket_tid); - } - - if (tcpecho_tid == RT_NULL) - { - tcpecho_tid = rt_thread_create("techo", - tcpecho_entry, RT_NULL, - 512, RT_THREAD_PRIORITY_MAX/2 + 2, 5); - if (tcpecho_tid != RT_NULL) - rt_thread_startup(tcpecho_tid); - } - if (tcpecho_socket_tid == RT_NULL) - { - tcpecho_socket_tid = rt_thread_create("techo_s", - tcpecho_socket_entry, RT_NULL, - 512, RT_THREAD_PRIORITY_MAX/2 + 3, 5); - if (tcpecho_socket_tid != RT_NULL) - rt_thread_startup(tcpecho_socket_tid); - } + /* start UDP echo server */ + if (udpecho_tid == RT_NULL) + { + udpecho_tid = rt_thread_create("uecho", + udpecho_entry, RT_NULL, + 512, RT_THREAD_PRIORITY_MAX/2, 5); + if (udpecho_tid != RT_NULL) + rt_thread_startup(udpecho_tid); + } + if (udpecho_socket_tid == RT_NULL) + { + udpecho_socket_tid = rt_thread_create("uecho_s", + udpecho_socket_entry, RT_NULL, + 512, RT_THREAD_PRIORITY_MAX/2 + 1, 5); + if (udpecho_socket_tid != RT_NULL) + rt_thread_startup(udpecho_socket_tid); + } + + if (tcpecho_tid == RT_NULL) + { + tcpecho_tid = rt_thread_create("techo", + tcpecho_entry, RT_NULL, + 512, RT_THREAD_PRIORITY_MAX/2 + 2, 5); + if (tcpecho_tid != RT_NULL) + rt_thread_startup(tcpecho_tid); + } + if (tcpecho_socket_tid == RT_NULL) + { + tcpecho_socket_tid = rt_thread_create("techo_s", + tcpecho_socket_entry, RT_NULL, + 512, RT_THREAD_PRIORITY_MAX/2 + 3, 5); + if (tcpecho_socket_tid != RT_NULL) + rt_thread_startup(tcpecho_socket_tid); + } } FINSH_FUNCTION_EXPORT(net_test, network test); diff --git a/examples/test/rtc_test.c b/examples/test/rtc_test.c index 992eb08d3d..48129ca36c 100644 --- a/examples/test/rtc_test.c +++ b/examples/test/rtc_test.c @@ -21,48 +21,48 @@ * Date Author Notes * 2018-01-15 Liu2guang the first version. */ -#include -#include +#include +#include int rtc_test(void) -{ +{ uint8_t i; time_t now; - rt_err_t ret = RT_EOK; - + rt_err_t ret = RT_EOK; + rt_kprintf("[RTC Test]RTC Test Start...\n"); rt_thread_delay(RT_TICK_PER_SECOND); - rt_kprintf("[RTC Test]Set RTC 2017-04-01 12:30:46\n\n"); + rt_kprintf("[RTC Test]Set RTC 2017-04-01 12:30:46\n\n"); rt_thread_delay(RT_TICK_PER_SECOND); - - ret = set_date(2017, 4, 1); + + ret = set_date(2017, 4, 1); if(ret != RT_EOK) { - rt_kprintf("[RTC Test]Set RTC Date failed\n"); + rt_kprintf("[RTC Test]Set RTC Date failed\n"); return RT_ERROR; } - + rt_thread_delay(RT_TICK_PER_SECOND); - - ret = set_time(12, 30, 46); + + ret = set_time(12, 30, 46); if(ret != RT_EOK) { - rt_kprintf("[RTC Test]Set RTC Time failed\n"); + rt_kprintf("[RTC Test]Set RTC Time failed\n"); return RT_ERROR; } - + rt_thread_delay(RT_TICK_PER_SECOND); - + for(i = 0; i < 10; i++) { - rt_kprintf("[RTC Test]Read RTC Date and Time: "); + rt_kprintf("[RTC Test]Read RTC Date and Time: "); now = time(RT_NULL); rt_kprintf("%s", ctime(&now)); - + rt_thread_delay(RT_TICK_PER_SECOND); } - + rt_kprintf("\n"); return RT_EOK; @@ -70,5 +70,5 @@ int rtc_test(void) #ifdef RT_USING_FINSH #include FINSH_FUNCTION_EXPORT(rtc_test, rtc drive test. e.g: rtc_test()); -MSH_CMD_EXPORT(rtc_test, rtc drive test. e.g: rtc_test()); +MSH_CMD_EXPORT(rtc_test, rtc drive test. e.g: rtc_test()); #endif diff --git a/examples/ulog/ulog_example.c b/examples/ulog/ulog_example.c index 88572f5152..f7ee068799 100644 --- a/examples/ulog/ulog_example.c +++ b/examples/ulog/ulog_example.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/include/libc/libc_dirent.h b/include/libc/libc_dirent.h index c3a19878ec..052ba54a63 100644 --- a/include/libc/libc_dirent.h +++ b/include/libc/libc_dirent.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/include/libc/libc_errno.h b/include/libc/libc_errno.h index 9143c841f2..30d6092e33 100644 --- a/include/libc/libc_errno.h +++ b/include/libc/libc_errno.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -161,7 +161,7 @@ defined in armcc/errno.h #define EPROTONOSUPPORT (ERROR_BASE_NO + 93) #define ESOCKTNOSUPPORT (ERROR_BASE_NO + 94) #define EOPNOTSUPP (ERROR_BASE_NO + 95) -#define ENOTSUP EOPNOTSUPP +#define ENOTSUP EOPNOTSUPP #define EPFNOSUPPORT (ERROR_BASE_NO + 96) #define EAFNOSUPPORT (ERROR_BASE_NO + 97) #define EADDRINUSE (ERROR_BASE_NO + 98) diff --git a/include/libc/libc_fcntl.h b/include/libc/libc_fcntl.h index 94705ba1b4..0969a90588 100644 --- a/include/libc/libc_fcntl.h +++ b/include/libc/libc_fcntl.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 */ @@ -42,7 +42,7 @@ #ifdef _O_BINARY #define O_BINARY _O_BINARY #else -#define O_BINARY 0 +#define O_BINARY 0 #endif #endif diff --git a/include/libc/libc_fdset.h b/include/libc/libc_fdset.h index 33a888883c..88be6446cb 100644 --- a/include/libc/libc_fdset.h +++ b/include/libc/libc_fdset.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/include/libc/libc_ioctl.h b/include/libc/libc_ioctl.h index ef5a5257a8..8f706a46cc 100644 --- a/include/libc/libc_ioctl.h +++ b/include/libc/libc_ioctl.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 */ @@ -32,99 +32,99 @@ * in send queue. */ #endif -#define TCGETS 0x5401 -#define TCSETS 0x5402 -#define TCSETSW 0x5403 -#define TCSETSF 0x5404 -#define TCGETA 0x5405 -#define TCSETA 0x5406 -#define TCSETAW 0x5407 -#define TCSETAF 0x5408 -#define TCSBRK 0x5409 -#define TCXONC 0x540A -#define TCFLSH 0x540B -#define TIOCEXCL 0x540C -#define TIOCNXCL 0x540D -#define TIOCSCTTY 0x540E -#define TIOCGPGRP 0x540F -#define TIOCSPGRP 0x5410 -#define TIOCOUTQ 0x5411 -#define TIOCSTI 0x5412 -#define TIOCGWINSZ 0x5413 -#define TIOCSWINSZ 0x5414 -#define TIOCMGET 0x5415 -#define TIOCMBIS 0x5416 -#define TIOCMBIC 0x5417 -#define TIOCMSET 0x5418 -#define TIOCGSOFTCAR 0x5419 -#define TIOCSSOFTCAR 0x541A -// #define FIONREAD 0x541B -#define TIOCINQ FIONREAD -#define TIOCLINUX 0x541C -#define TIOCCONS 0x541D -#define TIOCGSERIAL 0x541E -#define TIOCSSERIAL 0x541F -#define TIOCPKT 0x5420 -// #define FIONBIO 0x5421 -#define TIOCNOTTY 0x5422 -#define TIOCSETD 0x5423 -#define TIOCGETD 0x5424 -#define TCSBRKP 0x5425 -#define TIOCSBRK 0x5427 -#define TIOCCBRK 0x5428 -#define TIOCGSID 0x5429 -#define TIOCGRS485 0x542E -#define TIOCSRS485 0x542F -#define TIOCGPTN 0x80045430 -#define TIOCSPTLCK 0x40045431 -#define TIOCGDEV 0x80045432 -#define TCGETX 0x5432 -#define TCSETX 0x5433 -#define TCSETXF 0x5434 -#define TCSETXW 0x5435 -#define TIOCSIG 0x40045436 -#define TIOCVHANGUP 0x5437 -#define TIOCGPKT 0x80045438 -#define TIOCGPTLCK 0x80045439 -#define TIOCGEXCL 0x80045440 - -#define FIONCLEX 0x5450 -#define FIOCLEX 0x5451 +#define TCGETS 0x5401 +#define TCSETS 0x5402 +#define TCSETSW 0x5403 +#define TCSETSF 0x5404 +#define TCGETA 0x5405 +#define TCSETA 0x5406 +#define TCSETAW 0x5407 +#define TCSETAF 0x5408 +#define TCSBRK 0x5409 +#define TCXONC 0x540A +#define TCFLSH 0x540B +#define TIOCEXCL 0x540C +#define TIOCNXCL 0x540D +#define TIOCSCTTY 0x540E +#define TIOCGPGRP 0x540F +#define TIOCSPGRP 0x5410 +#define TIOCOUTQ 0x5411 +#define TIOCSTI 0x5412 +#define TIOCGWINSZ 0x5413 +#define TIOCSWINSZ 0x5414 +#define TIOCMGET 0x5415 +#define TIOCMBIS 0x5416 +#define TIOCMBIC 0x5417 +#define TIOCMSET 0x5418 +#define TIOCGSOFTCAR 0x5419 +#define TIOCSSOFTCAR 0x541A +// #define FIONREAD 0x541B +#define TIOCINQ FIONREAD +#define TIOCLINUX 0x541C +#define TIOCCONS 0x541D +#define TIOCGSERIAL 0x541E +#define TIOCSSERIAL 0x541F +#define TIOCPKT 0x5420 +// #define FIONBIO 0x5421 +#define TIOCNOTTY 0x5422 +#define TIOCSETD 0x5423 +#define TIOCGETD 0x5424 +#define TCSBRKP 0x5425 +#define TIOCSBRK 0x5427 +#define TIOCCBRK 0x5428 +#define TIOCGSID 0x5429 +#define TIOCGRS485 0x542E +#define TIOCSRS485 0x542F +#define TIOCGPTN 0x80045430 +#define TIOCSPTLCK 0x40045431 +#define TIOCGDEV 0x80045432 +#define TCGETX 0x5432 +#define TCSETX 0x5433 +#define TCSETXF 0x5434 +#define TCSETXW 0x5435 +#define TIOCSIG 0x40045436 +#define TIOCVHANGUP 0x5437 +#define TIOCGPKT 0x80045438 +#define TIOCGPTLCK 0x80045439 +#define TIOCGEXCL 0x80045440 + +#define FIONCLEX 0x5450 +#define FIOCLEX 0x5451 #ifndef _WIN32 -#define FIOASYNC 0x5452 +#define FIOASYNC 0x5452 #endif -#define TIOCSERCONFIG 0x5453 -#define TIOCSERGWILD 0x5454 -#define TIOCSERSWILD 0x5455 -#define TIOCGLCKTRMIOS 0x5456 -#define TIOCSLCKTRMIOS 0x5457 -#define TIOCSERGSTRUCT 0x5458 +#define TIOCSERCONFIG 0x5453 +#define TIOCSERGWILD 0x5454 +#define TIOCSERSWILD 0x5455 +#define TIOCGLCKTRMIOS 0x5456 +#define TIOCSLCKTRMIOS 0x5457 +#define TIOCSERGSTRUCT 0x5458 #define TIOCSERGETLSR 0x5459 #define TIOCSERGETMULTI 0x545A #define TIOCSERSETMULTI 0x545B -#define TIOCMIWAIT 0x545C -#define TIOCGICOUNT 0x545D -#define FIOQSIZE 0x5460 +#define TIOCMIWAIT 0x545C +#define TIOCGICOUNT 0x545D +#define FIOQSIZE 0x5460 -#define TIOCPKT_DATA 0 -#define TIOCPKT_FLUSHREAD 1 -#define TIOCPKT_FLUSHWRITE 2 -#define TIOCPKT_STOP 4 -#define TIOCPKT_START 8 -#define TIOCPKT_NOSTOP 16 -#define TIOCPKT_DOSTOP 32 -#define TIOCPKT_IOCTL 64 +#define TIOCPKT_DATA 0 +#define TIOCPKT_FLUSHREAD 1 +#define TIOCPKT_FLUSHWRITE 2 +#define TIOCPKT_STOP 4 +#define TIOCPKT_START 8 +#define TIOCPKT_NOSTOP 16 +#define TIOCPKT_DOSTOP 32 +#define TIOCPKT_IOCTL 64 #define TIOCSER_TEMT 0x01 struct winsize { - unsigned short ws_row; - unsigned short ws_col; - unsigned short ws_xpixel; - unsigned short ws_ypixel; + unsigned short ws_row; + unsigned short ws_col; + unsigned short ws_xpixel; + unsigned short ws_ypixel; }; #define TIOCM_LE 0x001 @@ -227,8 +227,8 @@ struct winsize { #define SIOCADDDLCI 0x8980 #define SIOCDELDLCI 0x8981 -#define SIOCDEVPRIVATE 0x89F0 -#define SIOCPROTOPRIVATE 0x89E0 +#define SIOCDEVPRIVATE 0x89F0 +#define SIOCPROTOPRIVATE 0x89E0 #endif diff --git a/include/libc/libc_signal.h b/include/libc/libc_signal.h index 539685de3e..8a4cc0d738 100644 --- a/include/libc/libc_signal.h +++ b/include/libc/libc_signal.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -57,11 +57,11 @@ typedef struct siginfo siginfo_t; #define SI_USER 0x01 /* Signal sent by kill(). */ #define SI_QUEUE 0x02 /* Signal sent by sigqueue(). */ -#define SI_TIMER 0x03 /* Signal generated by expiration of a +#define SI_TIMER 0x03 /* Signal generated by expiration of a timer set by timer_settime(). */ -#define SI_ASYNCIO 0x04 /* Signal generated by completion of an +#define SI_ASYNCIO 0x04 /* Signal generated by completion of an asynchronous I/O request. */ -#define SI_MESGQ 0x05 /* Signal generated by arrival of a +#define SI_MESGQ 0x05 /* Signal generated by arrival of a message on an empty message queue. */ #if !defined(RT_USING_NEWLIB) diff --git a/include/libc/libc_stat.h b/include/libc/libc_stat.h index 6497cfe12c..98450cd0d0 100644 --- a/include/libc/libc_stat.h +++ b/include/libc/libc_stat.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/include/rtdbg.h b/include/rtdbg.h index be5a57f312..c0a4e68222 100644 --- a/include/rtdbg.h +++ b/include/rtdbg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/include/rtdebug.h b/include/rtdebug.h index b66cd6fc69..8d4e55ac93 100644 --- a/include/rtdebug.h +++ b/include/rtdebug.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/include/rtdef.h b/include/rtdef.h index a27854cb39..193b027009 100644 --- a/include/rtdef.h +++ b/include/rtdef.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/include/rthw.h b/include/rthw.h index 21ac3da6c8..7ec9623470 100644 --- a/include/rthw.h +++ b/include/rthw.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -117,7 +117,7 @@ void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context)); */ void rt_hw_us_delay(rt_uint32_t us); -#define RT_DEFINE_SPINLOCK(x) +#define RT_DEFINE_SPINLOCK(x) #define RT_DECLARE_SPINLOCK(x) rt_ubase_t x #define rt_hw_spin_lock(lock) *(lock) = rt_hw_interrupt_disable() diff --git a/include/rtlibc.h b/include/rtlibc.h index b3a548beb1..4780d628b1 100644 --- a/include/rtlibc.h +++ b/include/rtlibc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/include/rtm.h b/include/rtm.h index 7e07a2239c..fd675fcf6f 100644 --- a/include/rtm.h +++ b/include/rtm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/include/rtservice.h b/include/rtservice.h index 81d6c71f17..d0bad85de1 100644 --- a/include/rtservice.h +++ b/include/rtservice.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -128,21 +128,21 @@ rt_inline unsigned int rt_list_len(const rt_list_t *l) /** * rt_list_for_each - iterate over a list - * @pos: the rt_list_t * to use as a loop cursor. - * @head: the head for your list. + * @pos: the rt_list_t * to use as a loop cursor. + * @head: the head for your list. */ #define rt_list_for_each(pos, head) \ for (pos = (head)->next; pos != (head); pos = pos->next) /** * rt_list_for_each_safe - iterate over a list safe against removal of list entry - * @pos: the rt_list_t * to use as a loop cursor. - * @n: another rt_list_t * to use as temporary storage - * @head: the head for your list. + * @pos: the rt_list_t * to use as a loop cursor. + * @n: another rt_list_t * to use as temporary storage + * @head: the head for your list. */ #define rt_list_for_each_safe(pos, n, head) \ - for (pos = (head)->next, n = pos->next; pos != (head); \ - pos = n, n = pos->next) + for (pos = (head)->next, n = pos->next; pos != (head); \ + pos = n, n = pos->next) /** * rt_list_for_each_entry - iterate over list of given type diff --git a/include/rtthread.h b/include/rtthread.h index 419f02695b..9d4282aa5b 100644 --- a/include/rtthread.h +++ b/include/rtthread.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/AT91SAM7S/AT91SAM7S.h b/libcpu/arm/AT91SAM7S/AT91SAM7S.h index 130f9074d1..91b57053da 100644 --- a/libcpu/arm/AT91SAM7S/AT91SAM7S.h +++ b/libcpu/arm/AT91SAM7S/AT91SAM7S.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,276 +15,276 @@ extern "C" { #endif -#define AT91_REG *(volatile unsigned int *) /* Hardware register definition */ +#define AT91_REG *(volatile unsigned int *) /* Hardware register definition */ /* ========== Register definition for TC0 peripheral ========== */ -#define AT91C_TC0_SR (AT91_REG(0xFFFA0020)) /* TC0 Status Register */ -#define AT91C_TC0_RC (AT91_REG(0xFFFA001C)) /* TC0 Register C */ -#define AT91C_TC0_RB (AT91_REG(0xFFFA0018)) /* TC0 Register B */ -#define AT91C_TC0_CCR (AT91_REG(0xFFFA0000)) /* TC0 Channel Control Register */ -#define AT91C_TC0_CMR (AT91_REG(0xFFFA0004)) /* TC0 Channel Mode Register (Capture Mode / Waveform Mode) */ -#define AT91C_TC0_IER (AT91_REG(0xFFFA0024)) /* TC0 Interrupt Enable Register */ -#define AT91C_TC0_RA (AT91_REG(0xFFFA0014)) /* TC0 Register A */ -#define AT91C_TC0_IDR (AT91_REG(0xFFFA0028)) /* TC0 Interrupt Disable Register */ -#define AT91C_TC0_CV (AT91_REG(0xFFFA0010)) /* TC0 Counter Value */ -#define AT91C_TC0_IMR (AT91_REG(0xFFFA002C)) /* TC0 Interrupt Mask Register */ +#define AT91C_TC0_SR (AT91_REG(0xFFFA0020)) /* TC0 Status Register */ +#define AT91C_TC0_RC (AT91_REG(0xFFFA001C)) /* TC0 Register C */ +#define AT91C_TC0_RB (AT91_REG(0xFFFA0018)) /* TC0 Register B */ +#define AT91C_TC0_CCR (AT91_REG(0xFFFA0000)) /* TC0 Channel Control Register */ +#define AT91C_TC0_CMR (AT91_REG(0xFFFA0004)) /* TC0 Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC0_IER (AT91_REG(0xFFFA0024)) /* TC0 Interrupt Enable Register */ +#define AT91C_TC0_RA (AT91_REG(0xFFFA0014)) /* TC0 Register A */ +#define AT91C_TC0_IDR (AT91_REG(0xFFFA0028)) /* TC0 Interrupt Disable Register */ +#define AT91C_TC0_CV (AT91_REG(0xFFFA0010)) /* TC0 Counter Value */ +#define AT91C_TC0_IMR (AT91_REG(0xFFFA002C)) /* TC0 Interrupt Mask Register */ /* ========== Register definition for TC1 peripheral ========== */ -#define AT91C_TC1_RB (AT91_REG(0xFFFA0058)) /* TC1 Register B */ -#define AT91C_TC1_CCR (AT91_REG(0xFFFA0040)) /* TC1 Channel Control Register */ -#define AT91C_TC1_IER (AT91_REG(0xFFFA0064)) /* TC1 Interrupt Enable Register */ -#define AT91C_TC1_IDR (AT91_REG(0xFFFA0068)) /* TC1 Interrupt Disable Register */ -#define AT91C_TC1_SR (AT91_REG(0xFFFA0060)) /* TC1 Status Register */ -#define AT91C_TC1_CMR (AT91_REG(0xFFFA0044)) /* TC1 Channel Mode Register (Capture Mode / Waveform Mode) */ -#define AT91C_TC1_RA (AT91_REG(0xFFFA0054)) /* TC1 Register A */ -#define AT91C_TC1_RC (AT91_REG(0xFFFA005C)) /* TC1 Register C */ -#define AT91C_TC1_IMR (AT91_REG(0xFFFA006C)) /* TC1 Interrupt Mask Register */ -#define AT91C_TC1_CV (AT91_REG(0xFFFA0050)) /* TC1 Counter Value */ +#define AT91C_TC1_RB (AT91_REG(0xFFFA0058)) /* TC1 Register B */ +#define AT91C_TC1_CCR (AT91_REG(0xFFFA0040)) /* TC1 Channel Control Register */ +#define AT91C_TC1_IER (AT91_REG(0xFFFA0064)) /* TC1 Interrupt Enable Register */ +#define AT91C_TC1_IDR (AT91_REG(0xFFFA0068)) /* TC1 Interrupt Disable Register */ +#define AT91C_TC1_SR (AT91_REG(0xFFFA0060)) /* TC1 Status Register */ +#define AT91C_TC1_CMR (AT91_REG(0xFFFA0044)) /* TC1 Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC1_RA (AT91_REG(0xFFFA0054)) /* TC1 Register A */ +#define AT91C_TC1_RC (AT91_REG(0xFFFA005C)) /* TC1 Register C */ +#define AT91C_TC1_IMR (AT91_REG(0xFFFA006C)) /* TC1 Interrupt Mask Register */ +#define AT91C_TC1_CV (AT91_REG(0xFFFA0050)) /* TC1 Counter Value */ /* ========== Register definition for TC2 peripheral ========== */ -#define AT91C_TC2_CMR (AT91_REG(0xFFFA0084)) /* TC2 Channel Mode Register (Capture Mode / Waveform Mode) */ -#define AT91C_TC2_CCR (AT91_REG(0xFFFA0080)) /* TC2 Channel Control Register */ -#define AT91C_TC2_CV (AT91_REG(0xFFFA0090)) /* TC2 Counter Value */ -#define AT91C_TC2_RA (AT91_REG(0xFFFA0094)) /* TC2 Register A */ -#define AT91C_TC2_RB (AT91_REG(0xFFFA0098)) /* TC2 Register B */ -#define AT91C_TC2_IDR (AT91_REG(0xFFFA00A8)) /* TC2 Interrupt Disable Register */ -#define AT91C_TC2_IMR (AT91_REG(0xFFFA00AC)) /* TC2 Interrupt Mask Register */ -#define AT91C_TC2_RC (AT91_REG(0xFFFA009C)) /* TC2 Register C */ -#define AT91C_TC2_IER (AT91_REG(0xFFFA00A4)) /* TC2 Interrupt Enable Register */ -#define AT91C_TC2_SR (AT91_REG(0xFFFA00A0)) /* TC2 Status Register */ +#define AT91C_TC2_CMR (AT91_REG(0xFFFA0084)) /* TC2 Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC2_CCR (AT91_REG(0xFFFA0080)) /* TC2 Channel Control Register */ +#define AT91C_TC2_CV (AT91_REG(0xFFFA0090)) /* TC2 Counter Value */ +#define AT91C_TC2_RA (AT91_REG(0xFFFA0094)) /* TC2 Register A */ +#define AT91C_TC2_RB (AT91_REG(0xFFFA0098)) /* TC2 Register B */ +#define AT91C_TC2_IDR (AT91_REG(0xFFFA00A8)) /* TC2 Interrupt Disable Register */ +#define AT91C_TC2_IMR (AT91_REG(0xFFFA00AC)) /* TC2 Interrupt Mask Register */ +#define AT91C_TC2_RC (AT91_REG(0xFFFA009C)) /* TC2 Register C */ +#define AT91C_TC2_IER (AT91_REG(0xFFFA00A4)) /* TC2 Interrupt Enable Register */ +#define AT91C_TC2_SR (AT91_REG(0xFFFA00A0)) /* TC2 Status Register */ /* ========== Register definition for PITC peripheral ========== */ -#define AT91C_PITC_PIVR (AT91_REG(0xFFFFFD38)) /* PITC Period Interval Value Register */ -#define AT91C_PITC_PISR (AT91_REG(0xFFFFFD34)) /* PITC Period Interval Status Register */ -#define AT91C_PITC_PIIR (AT91_REG(0xFFFFFD3C)) /* PITC Period Interval Image Register */ -#define AT91C_PITC_PIMR (AT91_REG(0xFFFFFD30)) /* PITC Period Interval Mode Register */ +#define AT91C_PITC_PIVR (AT91_REG(0xFFFFFD38)) /* PITC Period Interval Value Register */ +#define AT91C_PITC_PISR (AT91_REG(0xFFFFFD34)) /* PITC Period Interval Status Register */ +#define AT91C_PITC_PIIR (AT91_REG(0xFFFFFD3C)) /* PITC Period Interval Image Register */ +#define AT91C_PITC_PIMR (AT91_REG(0xFFFFFD30)) /* PITC Period Interval Mode Register */ /* ========== Register definition for UDP peripheral ========== */ -#define AT91C_UDP_NUM (AT91_REG(0xFFFB0000)) /* UDP Frame Number Register */ -#define AT91C_UDP_STAT (AT91_REG(0xFFFB0004)) /* UDP Global State Register */ -#define AT91C_UDP_FADDR (AT91_REG(0xFFFB0008)) /* UDP Function Address Register */ -#define AT91C_UDP_IER (AT91_REG(0xFFFB0010)) /* UDP Interrupt Enable Register */ -#define AT91C_UDP_IDR (AT91_REG(0xFFFB0014)) /* UDP Interrupt Disable Register */ -#define AT91C_UDP_IMR (AT91_REG(0xFFFB0018)) /* UDP Interrupt Mask Register */ -#define AT91C_UDP_ISR (AT91_REG(0xFFFB001C)) /* UDP Interrupt Status Register */ -#define AT91C_UDP_ICR (AT91_REG(0xFFFB0020)) /* UDP Interrupt Clear Register */ -#define AT91C_UDP_RSTEP (AT91_REG(0xFFFB0028)) /* UDP Reset Endpoint Register */ -#define AT91C_UDP_CSR0 (AT91_REG(0xFFFB0030)) /* UDP Endpoint Control and Status Register */ -#define AT91C_UDP_CSR(n) (*(&AT91C_UDP_CSR0 + n)) -#define AT91C_UDP_FDR0 (AT91_REG(0xFFFB0050)) /* UDP Endpoint FIFO Data Register */ -#define AT91C_UDP_FDR(n) (*(&AT91C_UDP_FDR0 + n)) -#define AT91C_UDP_TXVC (AT91_REG(0xFFFB0074)) /* UDP Transceiver Control Register */ +#define AT91C_UDP_NUM (AT91_REG(0xFFFB0000)) /* UDP Frame Number Register */ +#define AT91C_UDP_STAT (AT91_REG(0xFFFB0004)) /* UDP Global State Register */ +#define AT91C_UDP_FADDR (AT91_REG(0xFFFB0008)) /* UDP Function Address Register */ +#define AT91C_UDP_IER (AT91_REG(0xFFFB0010)) /* UDP Interrupt Enable Register */ +#define AT91C_UDP_IDR (AT91_REG(0xFFFB0014)) /* UDP Interrupt Disable Register */ +#define AT91C_UDP_IMR (AT91_REG(0xFFFB0018)) /* UDP Interrupt Mask Register */ +#define AT91C_UDP_ISR (AT91_REG(0xFFFB001C)) /* UDP Interrupt Status Register */ +#define AT91C_UDP_ICR (AT91_REG(0xFFFB0020)) /* UDP Interrupt Clear Register */ +#define AT91C_UDP_RSTEP (AT91_REG(0xFFFB0028)) /* UDP Reset Endpoint Register */ +#define AT91C_UDP_CSR0 (AT91_REG(0xFFFB0030)) /* UDP Endpoint Control and Status Register */ +#define AT91C_UDP_CSR(n) (*(&AT91C_UDP_CSR0 + n)) +#define AT91C_UDP_FDR0 (AT91_REG(0xFFFB0050)) /* UDP Endpoint FIFO Data Register */ +#define AT91C_UDP_FDR(n) (*(&AT91C_UDP_FDR0 + n)) +#define AT91C_UDP_TXVC (AT91_REG(0xFFFB0074)) /* UDP Transceiver Control Register */ /* ========== Register definition for US0 peripheral ========== */ -#define AT91C_US0_CR (AT91_REG(0xFFFC0000)) /* US0 Control Register */ -#define AT91C_US0_MR (AT91_REG(0xFFFC0004)) /* US0 Mode Register */ -#define AT91C_US0_IER (AT91_REG(0xFFFC0008)) /* US0 Interrupt Enable Register */ -#define AT91C_US0_IDR (AT91_REG(0xFFFC000C)) /* US0 Interrupt Disable Register */ -#define AT91C_US0_IMR (AT91_REG(0xFFFC0010)) /* US0 Interrupt Mask Register */ -#define AT91C_US0_CSR (AT91_REG(0xFFFC0014)) /* US0 Channel Status Register */ -#define AT91C_US0_RHR (AT91_REG(0xFFFC0018)) /* US0 Receiver Holding Register */ -#define AT91C_US0_THR (AT91_REG(0xFFFC001C)) /* US0 Transmitter Holding Register */ -#define AT91C_US0_BRGR (AT91_REG(0xFFFC0020)) /* US0 Baud Rate Generator Register */ -#define AT91C_US0_RTOR (AT91_REG(0xFFFC0024)) /* US0 Receiver Time-out Register */ -#define AT91C_US0_TTGR (AT91_REG(0xFFFC0028)) /* US0 Transmitter Time-guard Register */ -#define AT91C_US0_NER (AT91_REG(0xFFFC0044)) /* US0 Nb Errors Register */ -#define AT91C_US0_FIDI (AT91_REG(0xFFFC0040)) /* US0 FI_DI_Ratio Register */ -#define AT91C_US0_IF (AT91_REG(0xFFFC004C)) /* US0 IRDA_FILTER Register */ +#define AT91C_US0_CR (AT91_REG(0xFFFC0000)) /* US0 Control Register */ +#define AT91C_US0_MR (AT91_REG(0xFFFC0004)) /* US0 Mode Register */ +#define AT91C_US0_IER (AT91_REG(0xFFFC0008)) /* US0 Interrupt Enable Register */ +#define AT91C_US0_IDR (AT91_REG(0xFFFC000C)) /* US0 Interrupt Disable Register */ +#define AT91C_US0_IMR (AT91_REG(0xFFFC0010)) /* US0 Interrupt Mask Register */ +#define AT91C_US0_CSR (AT91_REG(0xFFFC0014)) /* US0 Channel Status Register */ +#define AT91C_US0_RHR (AT91_REG(0xFFFC0018)) /* US0 Receiver Holding Register */ +#define AT91C_US0_THR (AT91_REG(0xFFFC001C)) /* US0 Transmitter Holding Register */ +#define AT91C_US0_BRGR (AT91_REG(0xFFFC0020)) /* US0 Baud Rate Generator Register */ +#define AT91C_US0_RTOR (AT91_REG(0xFFFC0024)) /* US0 Receiver Time-out Register */ +#define AT91C_US0_TTGR (AT91_REG(0xFFFC0028)) /* US0 Transmitter Time-guard Register */ +#define AT91C_US0_NER (AT91_REG(0xFFFC0044)) /* US0 Nb Errors Register */ +#define AT91C_US0_FIDI (AT91_REG(0xFFFC0040)) /* US0 FI_DI_Ratio Register */ +#define AT91C_US0_IF (AT91_REG(0xFFFC004C)) /* US0 IRDA_FILTER Register */ /* ========== Register definition for AIC peripheral ========== */ -#define AT91C_AIC_SMR0 (AT91_REG(0xFFFFF000)) /* AIC Source Mode Register */ -#define AT91C_AIC_SMR(n) (*(&AT91C_AIC_SMR0 + n)) -#define AT91C_AIC_SVR0 (AT91_REG(0xFFFFF080)) /* AIC Source Vector Register */ -#define AT91C_AIC_SVR(n) (*(&AT91C_AIC_SVR0 + n)) -#define AT91C_AIC_IVR (AT91_REG(0xFFFFF100)) /* AIC Interrupt Vector Register */ -#define AT91C_AIC_FVR (AT91_REG(0xFFFFF104)) /* AIC FIQ Vector Register */ -#define AT91C_AIC_ISR (AT91_REG(0xFFFFF108)) /* AIC Interrupt Status Register */ -#define AT91C_AIC_IPR (AT91_REG(0xFFFFF10C)) /* AIC Interrupt Pending Register */ -#define AT91C_AIC_IMR (AT91_REG(0xFFFFF110)) /* AIC Interrupt Mask Register */ -#define AT91C_AIC_CISR (AT91_REG(0xFFFFF114)) /* AIC Core Interrupt Status Register */ -#define AT91C_AIC_IECR (AT91_REG(0xFFFFF120)) /* AIC Interrupt Enable Command Register */ -#define AT91C_AIC_IDCR (AT91_REG(0xFFFFF124)) /* AIC Interrupt Disable Command Register */ -#define AT91C_AIC_ICCR (AT91_REG(0xFFFFF128)) /* AIC Interrupt Clear Command Register */ -#define AT91C_AIC_ISCR (AT91_REG(0xFFFFF12C)) /* AIC Interrupt Set Command Register */ -#define AT91C_AIC_EOICR (AT91_REG(0xFFFFF130)) /* AIC End of Interrupt Command Register */ -#define AT91C_AIC_SPU (AT91_REG(0xFFFFF134)) /* AIC Spurious Vector Register */ -#define AT91C_AIC_DCR (AT91_REG(0xFFFFF138)) /* AIC Debug Control Register (Protect) */ -#define AT91C_AIC_FFER (AT91_REG(0xFFFFF140)) /* AIC Fast Forcing Enable Register */ -#define AT91C_AIC_FFDR (AT91_REG(0xFFFFF144)) /* AIC Fast Forcing Disable Register */ -#define AT91C_AIC_FFSR (AT91_REG(0xFFFFF148)) /* AIC Fast Forcing Status Register */ +#define AT91C_AIC_SMR0 (AT91_REG(0xFFFFF000)) /* AIC Source Mode Register */ +#define AT91C_AIC_SMR(n) (*(&AT91C_AIC_SMR0 + n)) +#define AT91C_AIC_SVR0 (AT91_REG(0xFFFFF080)) /* AIC Source Vector Register */ +#define AT91C_AIC_SVR(n) (*(&AT91C_AIC_SVR0 + n)) +#define AT91C_AIC_IVR (AT91_REG(0xFFFFF100)) /* AIC Interrupt Vector Register */ +#define AT91C_AIC_FVR (AT91_REG(0xFFFFF104)) /* AIC FIQ Vector Register */ +#define AT91C_AIC_ISR (AT91_REG(0xFFFFF108)) /* AIC Interrupt Status Register */ +#define AT91C_AIC_IPR (AT91_REG(0xFFFFF10C)) /* AIC Interrupt Pending Register */ +#define AT91C_AIC_IMR (AT91_REG(0xFFFFF110)) /* AIC Interrupt Mask Register */ +#define AT91C_AIC_CISR (AT91_REG(0xFFFFF114)) /* AIC Core Interrupt Status Register */ +#define AT91C_AIC_IECR (AT91_REG(0xFFFFF120)) /* AIC Interrupt Enable Command Register */ +#define AT91C_AIC_IDCR (AT91_REG(0xFFFFF124)) /* AIC Interrupt Disable Command Register */ +#define AT91C_AIC_ICCR (AT91_REG(0xFFFFF128)) /* AIC Interrupt Clear Command Register */ +#define AT91C_AIC_ISCR (AT91_REG(0xFFFFF12C)) /* AIC Interrupt Set Command Register */ +#define AT91C_AIC_EOICR (AT91_REG(0xFFFFF130)) /* AIC End of Interrupt Command Register */ +#define AT91C_AIC_SPU (AT91_REG(0xFFFFF134)) /* AIC Spurious Vector Register */ +#define AT91C_AIC_DCR (AT91_REG(0xFFFFF138)) /* AIC Debug Control Register (Protect) */ +#define AT91C_AIC_FFER (AT91_REG(0xFFFFF140)) /* AIC Fast Forcing Enable Register */ +#define AT91C_AIC_FFDR (AT91_REG(0xFFFFF144)) /* AIC Fast Forcing Disable Register */ +#define AT91C_AIC_FFSR (AT91_REG(0xFFFFF148)) /* AIC Fast Forcing Status Register */ /* ========== Register definition for DBGU peripheral ========== */ -#define AT91C_DBGU_EXID (AT91_REG(0xFFFFF244)) /* DBGU Chip ID Extension Register */ -#define AT91C_DBGU_BRGR (AT91_REG(0xFFFFF220)) /* DBGU Baud Rate Generator Register */ -#define AT91C_DBGU_IDR (AT91_REG(0xFFFFF20C)) /* DBGU Interrupt Disable Register */ -#define AT91C_DBGU_CSR (AT91_REG(0xFFFFF214)) /* DBGU Channel Status Register */ -#define AT91C_DBGU_CIDR (AT91_REG(0xFFFFF240)) /* DBGU Chip ID Register */ -#define AT91C_DBGU_MR (AT91_REG(0xFFFFF204)) /* DBGU Mode Register */ -#define AT91C_DBGU_IMR (AT91_REG(0xFFFFF210)) /* DBGU Interrupt Mask Register */ -#define AT91C_DBGU_CR (AT91_REG(0xFFFFF200)) /* DBGU Control Register */ -#define AT91C_DBGU_FNTR (AT91_REG(0xFFFFF248)) /* DBGU Force NTRST Register */ -#define AT91C_DBGU_THR (AT91_REG(0xFFFFF21C)) /* DBGU Transmitter Holding Register */ -#define AT91C_DBGU_RHR (AT91_REG(0xFFFFF218)) /* DBGU Receiver Holding Register */ -#define AT91C_DBGU_IER (AT91_REG(0xFFFFF208)) /* DBGU Interrupt Enable Register */ +#define AT91C_DBGU_EXID (AT91_REG(0xFFFFF244)) /* DBGU Chip ID Extension Register */ +#define AT91C_DBGU_BRGR (AT91_REG(0xFFFFF220)) /* DBGU Baud Rate Generator Register */ +#define AT91C_DBGU_IDR (AT91_REG(0xFFFFF20C)) /* DBGU Interrupt Disable Register */ +#define AT91C_DBGU_CSR (AT91_REG(0xFFFFF214)) /* DBGU Channel Status Register */ +#define AT91C_DBGU_CIDR (AT91_REG(0xFFFFF240)) /* DBGU Chip ID Register */ +#define AT91C_DBGU_MR (AT91_REG(0xFFFFF204)) /* DBGU Mode Register */ +#define AT91C_DBGU_IMR (AT91_REG(0xFFFFF210)) /* DBGU Interrupt Mask Register */ +#define AT91C_DBGU_CR (AT91_REG(0xFFFFF200)) /* DBGU Control Register */ +#define AT91C_DBGU_FNTR (AT91_REG(0xFFFFF248)) /* DBGU Force NTRST Register */ +#define AT91C_DBGU_THR (AT91_REG(0xFFFFF21C)) /* DBGU Transmitter Holding Register */ +#define AT91C_DBGU_RHR (AT91_REG(0xFFFFF218)) /* DBGU Receiver Holding Register */ +#define AT91C_DBGU_IER (AT91_REG(0xFFFFF208)) /* DBGU Interrupt Enable Register */ /* ========== Register definition for PIO peripheral ========== */ -#define AT91C_PIO_ODR (AT91_REG(0xFFFFF414)) /* PIOA Output Disable Registerr */ -#define AT91C_PIO_SODR (AT91_REG(0xFFFFF430)) /* PIOA Set Output Data Register */ -#define AT91C_PIO_ISR (AT91_REG(0xFFFFF44C)) /* PIOA Interrupt Status Register */ -#define AT91C_PIO_ABSR (AT91_REG(0xFFFFF478)) /* PIOA AB Select Status Register */ -#define AT91C_PIO_IER (AT91_REG(0xFFFFF440)) /* PIOA Interrupt Enable Register */ -#define AT91C_PIO_PPUDR (AT91_REG(0xFFFFF460)) /* PIOA Pull-up Disable Register */ -#define AT91C_PIO_IMR (AT91_REG(0xFFFFF448)) /* PIOA Interrupt Mask Register */ -#define AT91C_PIO_PER (AT91_REG(0xFFFFF400)) /* PIOA PIO Enable Register */ -#define AT91C_PIO_IFDR (AT91_REG(0xFFFFF424)) /* PIOA Input Filter Disable Register */ -#define AT91C_PIO_OWDR (AT91_REG(0xFFFFF4A4)) /* PIOA Output Write Disable Register */ -#define AT91C_PIO_MDSR (AT91_REG(0xFFFFF458)) /* PIOA Multi-driver Status Register */ -#define AT91C_PIO_IDR (AT91_REG(0xFFFFF444)) /* PIOA Interrupt Disable Register */ -#define AT91C_PIO_ODSR (AT91_REG(0xFFFFF438)) /* PIOA Output Data Status Register */ -#define AT91C_PIO_PPUSR (AT91_REG(0xFFFFF468)) /* PIOA Pull-up Status Register */ -#define AT91C_PIO_OWSR (AT91_REG(0xFFFFF4A8)) /* PIOA Output Write Status Register */ -#define AT91C_PIO_BSR (AT91_REG(0xFFFFF474)) /* PIOA Select B Register */ -#define AT91C_PIO_OWER (AT91_REG(0xFFFFF4A0)) /* PIOA Output Write Enable Register */ -#define AT91C_PIO_IFER (AT91_REG(0xFFFFF420)) /* PIOA Input Filter Enable Register */ -#define AT91C_PIO_PDSR (AT91_REG(0xFFFFF43C)) /* PIOA Pin Data Status Register */ -#define AT91C_PIO_PPUER (AT91_REG(0xFFFFF464)) /* PIOA Pull-up Enable Register */ -#define AT91C_PIO_OSR (AT91_REG(0xFFFFF418)) /* PIOA Output Status Register */ -#define AT91C_PIO_ASR (AT91_REG(0xFFFFF470)) /* PIOA Select A Register */ -#define AT91C_PIO_MDDR (AT91_REG(0xFFFFF454)) /* PIOA Multi-driver Disable Register */ -#define AT91C_PIO_CODR (AT91_REG(0xFFFFF434)) /* PIOA Clear Output Data Register */ -#define AT91C_PIO_MDER (AT91_REG(0xFFFFF450)) /* PIOA Multi-driver Enable Register */ -#define AT91C_PIO_PDR (AT91_REG(0xFFFFF404)) /* PIOA PIO Disable Register */ -#define AT91C_PIO_IFSR (AT91_REG(0xFFFFF428)) /* PIOA Input Filter Status Register */ -#define AT91C_PIO_OER (AT91_REG(0xFFFFF410)) /* PIOA Output Enable Register */ -#define AT91C_PIO_PSR (AT91_REG(0xFFFFF408)) /* PIOA PIO Status Register */ +#define AT91C_PIO_ODR (AT91_REG(0xFFFFF414)) /* PIOA Output Disable Registerr */ +#define AT91C_PIO_SODR (AT91_REG(0xFFFFF430)) /* PIOA Set Output Data Register */ +#define AT91C_PIO_ISR (AT91_REG(0xFFFFF44C)) /* PIOA Interrupt Status Register */ +#define AT91C_PIO_ABSR (AT91_REG(0xFFFFF478)) /* PIOA AB Select Status Register */ +#define AT91C_PIO_IER (AT91_REG(0xFFFFF440)) /* PIOA Interrupt Enable Register */ +#define AT91C_PIO_PPUDR (AT91_REG(0xFFFFF460)) /* PIOA Pull-up Disable Register */ +#define AT91C_PIO_IMR (AT91_REG(0xFFFFF448)) /* PIOA Interrupt Mask Register */ +#define AT91C_PIO_PER (AT91_REG(0xFFFFF400)) /* PIOA PIO Enable Register */ +#define AT91C_PIO_IFDR (AT91_REG(0xFFFFF424)) /* PIOA Input Filter Disable Register */ +#define AT91C_PIO_OWDR (AT91_REG(0xFFFFF4A4)) /* PIOA Output Write Disable Register */ +#define AT91C_PIO_MDSR (AT91_REG(0xFFFFF458)) /* PIOA Multi-driver Status Register */ +#define AT91C_PIO_IDR (AT91_REG(0xFFFFF444)) /* PIOA Interrupt Disable Register */ +#define AT91C_PIO_ODSR (AT91_REG(0xFFFFF438)) /* PIOA Output Data Status Register */ +#define AT91C_PIO_PPUSR (AT91_REG(0xFFFFF468)) /* PIOA Pull-up Status Register */ +#define AT91C_PIO_OWSR (AT91_REG(0xFFFFF4A8)) /* PIOA Output Write Status Register */ +#define AT91C_PIO_BSR (AT91_REG(0xFFFFF474)) /* PIOA Select B Register */ +#define AT91C_PIO_OWER (AT91_REG(0xFFFFF4A0)) /* PIOA Output Write Enable Register */ +#define AT91C_PIO_IFER (AT91_REG(0xFFFFF420)) /* PIOA Input Filter Enable Register */ +#define AT91C_PIO_PDSR (AT91_REG(0xFFFFF43C)) /* PIOA Pin Data Status Register */ +#define AT91C_PIO_PPUER (AT91_REG(0xFFFFF464)) /* PIOA Pull-up Enable Register */ +#define AT91C_PIO_OSR (AT91_REG(0xFFFFF418)) /* PIOA Output Status Register */ +#define AT91C_PIO_ASR (AT91_REG(0xFFFFF470)) /* PIOA Select A Register */ +#define AT91C_PIO_MDDR (AT91_REG(0xFFFFF454)) /* PIOA Multi-driver Disable Register */ +#define AT91C_PIO_CODR (AT91_REG(0xFFFFF434)) /* PIOA Clear Output Data Register */ +#define AT91C_PIO_MDER (AT91_REG(0xFFFFF450)) /* PIOA Multi-driver Enable Register */ +#define AT91C_PIO_PDR (AT91_REG(0xFFFFF404)) /* PIOA PIO Disable Register */ +#define AT91C_PIO_IFSR (AT91_REG(0xFFFFF428)) /* PIOA Input Filter Status Register */ +#define AT91C_PIO_OER (AT91_REG(0xFFFFF410)) /* PIOA Output Enable Register */ +#define AT91C_PIO_PSR (AT91_REG(0xFFFFF408)) /* PIOA PIO Status Register */ // ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_IMR (AT91_REG(0xFFFFF448)) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_IER (AT91_REG(0xFFFFF440)) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_OWDR (AT91_REG(0xFFFFF4A4)) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_ISR (AT91_REG(0xFFFFF44C)) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_PPUDR (AT91_REG(0xFFFFF460)) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_MDSR (AT91_REG(0xFFFFF458)) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_MDER (AT91_REG(0xFFFFF450)) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PER (AT91_REG(0xFFFFF400)) // (PIOA) PIO Enable Register -#define AT91C_PIOA_PSR (AT91_REG(0xFFFFF408)) // (PIOA) PIO Status Register -#define AT91C_PIOA_OER (AT91_REG(0xFFFFF410)) // (PIOA) Output Enable Register -#define AT91C_PIOA_BSR (AT91_REG(0xFFFFF474)) // (PIOA) Select B Register -#define AT91C_PIOA_PPUER (AT91_REG(0xFFFFF464)) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_MDDR (AT91_REG(0xFFFFF454)) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_PDR (AT91_REG(0xFFFFF404)) // (PIOA) PIO Disable Register -#define AT91C_PIOA_ODR (AT91_REG(0xFFFFF414)) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_IFDR (AT91_REG(0xFFFFF424)) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_ABSR (AT91_REG(0xFFFFF478)) // (PIOA) AB Select Status Register -#define AT91C_PIOA_ASR (AT91_REG(0xFFFFF470)) // (PIOA) Select A Register -#define AT91C_PIOA_PPUSR (AT91_REG(0xFFFFF468)) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_ODSR (AT91_REG(0xFFFFF438)) // (PIOA) Output Data Status Register -#define AT91C_PIOA_SODR (AT91_REG(0xFFFFF430)) // (PIOA) Set Output Data Register -#define AT91C_PIOA_IFSR (AT91_REG(0xFFFFF428)) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_IFER (AT91_REG(0xFFFFF420)) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_OSR (AT91_REG(0xFFFFF418)) // (PIOA) Output Status Register -#define AT91C_PIOA_IDR (AT91_REG(0xFFFFF444)) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_PDSR (AT91_REG(0xFFFFF43C)) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_CODR (AT91_REG(0xFFFFF434)) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_OWSR (AT91_REG(0xFFFFF4A8)) // (PIOA) Output Write Status Register -#define AT91C_PIOA_OWER (AT91_REG(0xFFFFF4A0)) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IMR (AT91_REG(0xFFFFF448)) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_IER (AT91_REG(0xFFFFF440)) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_OWDR (AT91_REG(0xFFFFF4A4)) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_ISR (AT91_REG(0xFFFFF44C)) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_PPUDR (AT91_REG(0xFFFFF460)) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_MDSR (AT91_REG(0xFFFFF458)) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_MDER (AT91_REG(0xFFFFF450)) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PER (AT91_REG(0xFFFFF400)) // (PIOA) PIO Enable Register +#define AT91C_PIOA_PSR (AT91_REG(0xFFFFF408)) // (PIOA) PIO Status Register +#define AT91C_PIOA_OER (AT91_REG(0xFFFFF410)) // (PIOA) Output Enable Register +#define AT91C_PIOA_BSR (AT91_REG(0xFFFFF474)) // (PIOA) Select B Register +#define AT91C_PIOA_PPUER (AT91_REG(0xFFFFF464)) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_MDDR (AT91_REG(0xFFFFF454)) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_PDR (AT91_REG(0xFFFFF404)) // (PIOA) PIO Disable Register +#define AT91C_PIOA_ODR (AT91_REG(0xFFFFF414)) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_IFDR (AT91_REG(0xFFFFF424)) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_ABSR (AT91_REG(0xFFFFF478)) // (PIOA) AB Select Status Register +#define AT91C_PIOA_ASR (AT91_REG(0xFFFFF470)) // (PIOA) Select A Register +#define AT91C_PIOA_PPUSR (AT91_REG(0xFFFFF468)) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_ODSR (AT91_REG(0xFFFFF438)) // (PIOA) Output Data Status Register +#define AT91C_PIOA_SODR (AT91_REG(0xFFFFF430)) // (PIOA) Set Output Data Register +#define AT91C_PIOA_IFSR (AT91_REG(0xFFFFF428)) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_IFER (AT91_REG(0xFFFFF420)) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_OSR (AT91_REG(0xFFFFF418)) // (PIOA) Output Status Register +#define AT91C_PIOA_IDR (AT91_REG(0xFFFFF444)) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_PDSR (AT91_REG(0xFFFFF43C)) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_CODR (AT91_REG(0xFFFFF434)) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_OWSR (AT91_REG(0xFFFFF4A8)) // (PIOA) Output Write Status Register +#define AT91C_PIOA_OWER (AT91_REG(0xFFFFF4A0)) // (PIOA) Output Write Enable Register // ========== Register definition for PIOB peripheral ========== -#define AT91C_PIOB_OWSR (AT91_REG(0xFFFFF6A8)) // (PIOB) Output Write Status Register -#define AT91C_PIOB_PPUSR (AT91_REG(0xFFFFF668)) // (PIOB) Pull-up Status Register -#define AT91C_PIOB_PPUDR (AT91_REG(0xFFFFF660)) // (PIOB) Pull-up Disable Register -#define AT91C_PIOB_MDSR (AT91_REG(0xFFFFF658)) // (PIOB) Multi-driver Status Register -#define AT91C_PIOB_MDER (AT91_REG(0xFFFFF650)) // (PIOB) Multi-driver Enable Register -#define AT91C_PIOB_IMR (AT91_REG(0xFFFFF648)) // (PIOB) Interrupt Mask Register -#define AT91C_PIOB_OSR (AT91_REG(0xFFFFF618)) // (PIOB) Output Status Register -#define AT91C_PIOB_OER (AT91_REG(0xFFFFF610)) // (PIOB) Output Enable Register -#define AT91C_PIOB_PSR (AT91_REG(0xFFFFF608)) // (PIOB) PIO Status Register -#define AT91C_PIOB_PER (AT91_REG(0xFFFFF600)) // (PIOB) PIO Enable Register -#define AT91C_PIOB_BSR (AT91_REG(0xFFFFF674)) // (PIOB) Select B Register -#define AT91C_PIOB_PPUER (AT91_REG(0xFFFFF664)) // (PIOB) Pull-up Enable Register -#define AT91C_PIOB_IFDR (AT91_REG(0xFFFFF624)) // (PIOB) Input Filter Disable Register -#define AT91C_PIOB_ODR (AT91_REG(0xFFFFF614)) // (PIOB) Output Disable Registerr -#define AT91C_PIOB_ABSR (AT91_REG(0xFFFFF678)) // (PIOB) AB Select Status Register -#define AT91C_PIOB_ASR (AT91_REG(0xFFFFF670)) // (PIOB) Select A Register -#define AT91C_PIOB_IFER (AT91_REG(0xFFFFF620)) // (PIOB) Input Filter Enable Register -#define AT91C_PIOB_IFSR (AT91_REG(0xFFFFF628)) // (PIOB) Input Filter Status Register -#define AT91C_PIOB_SODR (AT91_REG(0xFFFFF630)) // (PIOB) Set Output Data Register -#define AT91C_PIOB_ODSR (AT91_REG(0xFFFFF638)) // (PIOB) Output Data Status Register -#define AT91C_PIOB_CODR (AT91_REG(0xFFFFF634)) // (PIOB) Clear Output Data Register -#define AT91C_PIOB_PDSR (AT91_REG(0xFFFFF63C)) // (PIOB) Pin Data Status Register -#define AT91C_PIOB_OWER (AT91_REG(0xFFFFF6A0)) // (PIOB) Output Write Enable Register -#define AT91C_PIOB_IER (AT91_REG(0xFFFFF640)) // (PIOB) Interrupt Enable Register -#define AT91C_PIOB_OWDR (AT91_REG(0xFFFFF6A4)) // (PIOB) Output Write Disable Register -#define AT91C_PIOB_MDDR (AT91_REG(0xFFFFF654)) // (PIOB) Multi-driver Disable Register -#define AT91C_PIOB_ISR (AT91_REG(0xFFFFF64C)) // (PIOB) Interrupt Status Register -#define AT91C_PIOB_IDR (AT91_REG(0xFFFFF644)) // (PIOB) Interrupt Disable Register -#define AT91C_PIOB_PDR (AT91_REG(0xFFFFF604)) // (PIOB) PIO Disable Register +#define AT91C_PIOB_OWSR (AT91_REG(0xFFFFF6A8)) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PPUSR (AT91_REG(0xFFFFF668)) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_PPUDR (AT91_REG(0xFFFFF660)) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_MDSR (AT91_REG(0xFFFFF658)) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_MDER (AT91_REG(0xFFFFF650)) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_IMR (AT91_REG(0xFFFFF648)) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_OSR (AT91_REG(0xFFFFF618)) // (PIOB) Output Status Register +#define AT91C_PIOB_OER (AT91_REG(0xFFFFF610)) // (PIOB) Output Enable Register +#define AT91C_PIOB_PSR (AT91_REG(0xFFFFF608)) // (PIOB) PIO Status Register +#define AT91C_PIOB_PER (AT91_REG(0xFFFFF600)) // (PIOB) PIO Enable Register +#define AT91C_PIOB_BSR (AT91_REG(0xFFFFF674)) // (PIOB) Select B Register +#define AT91C_PIOB_PPUER (AT91_REG(0xFFFFF664)) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_IFDR (AT91_REG(0xFFFFF624)) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_ODR (AT91_REG(0xFFFFF614)) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_ABSR (AT91_REG(0xFFFFF678)) // (PIOB) AB Select Status Register +#define AT91C_PIOB_ASR (AT91_REG(0xFFFFF670)) // (PIOB) Select A Register +#define AT91C_PIOB_IFER (AT91_REG(0xFFFFF620)) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_IFSR (AT91_REG(0xFFFFF628)) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_SODR (AT91_REG(0xFFFFF630)) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ODSR (AT91_REG(0xFFFFF638)) // (PIOB) Output Data Status Register +#define AT91C_PIOB_CODR (AT91_REG(0xFFFFF634)) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_PDSR (AT91_REG(0xFFFFF63C)) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_OWER (AT91_REG(0xFFFFF6A0)) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_IER (AT91_REG(0xFFFFF640)) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_OWDR (AT91_REG(0xFFFFF6A4)) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDDR (AT91_REG(0xFFFFF654)) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_ISR (AT91_REG(0xFFFFF64C)) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_IDR (AT91_REG(0xFFFFF644)) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_PDR (AT91_REG(0xFFFFF604)) // (PIOB) PIO Disable Register /* ========== Register definition for PMC peripheral ========== */ -#define AT91C_PMC_SCER (AT91_REG(0xFFFFFC00)) /* PMC System Clock Enable Register */ -#define AT91C_PMC_SCDR (AT91_REG(0xFFFFFC04)) /* PMC System Clock Disable Register */ -#define AT91C_PMC_SCSR (AT91_REG(0xFFFFFC08)) /* PMC System Clock Status Register */ -#define AT91C_PMC_PCER (AT91_REG(0xFFFFFC10)) /* PMC Peripheral Clock Enable Register */ -#define AT91C_PMC_PCDR (AT91_REG(0xFFFFFC14)) /* PMC Peripheral Clock Disable Register */ -#define AT91C_PMC_PCSR (AT91_REG(0xFFFFFC18)) /* PMC Peripheral Clock Status Register */ -#define AT91C_PMC_MOR (AT91_REG(0xFFFFFC20)) /* PMC Main Oscillator Register */ -#define AT91C_PMC_MCFR (AT91_REG(0xFFFFFC24)) /* PMC Main Clock Frequency Register */ -#define AT91C_PMC_PLLR (AT91_REG(0xFFFFFC2C)) /* PMC PLL Register */ -#define AT91C_PMC_MCKR (AT91_REG(0xFFFFFC30)) /* PMC Master Clock Register */ -#define AT91C_PMC_PCKR (AT91_REG(0xFFFFFC40)) /* PMC Programmable Clock Register */ -#define AT91C_PMC_IER (AT91_REG(0xFFFFFC60)) /* PMC Interrupt Enable Register */ -#define AT91C_PMC_IDR (AT91_REG(0xFFFFFC64)) /* PMC Interrupt Disable Register */ -#define AT91C_PMC_SR (AT91_REG(0xFFFFFC68)) /* PMC Status Register */ -#define AT91C_PMC_IMR (AT91_REG(0xFFFFFC6C)) /* PMC Interrupt Mask Register */ +#define AT91C_PMC_SCER (AT91_REG(0xFFFFFC00)) /* PMC System Clock Enable Register */ +#define AT91C_PMC_SCDR (AT91_REG(0xFFFFFC04)) /* PMC System Clock Disable Register */ +#define AT91C_PMC_SCSR (AT91_REG(0xFFFFFC08)) /* PMC System Clock Status Register */ +#define AT91C_PMC_PCER (AT91_REG(0xFFFFFC10)) /* PMC Peripheral Clock Enable Register */ +#define AT91C_PMC_PCDR (AT91_REG(0xFFFFFC14)) /* PMC Peripheral Clock Disable Register */ +#define AT91C_PMC_PCSR (AT91_REG(0xFFFFFC18)) /* PMC Peripheral Clock Status Register */ +#define AT91C_PMC_MOR (AT91_REG(0xFFFFFC20)) /* PMC Main Oscillator Register */ +#define AT91C_PMC_MCFR (AT91_REG(0xFFFFFC24)) /* PMC Main Clock Frequency Register */ +#define AT91C_PMC_PLLR (AT91_REG(0xFFFFFC2C)) /* PMC PLL Register */ +#define AT91C_PMC_MCKR (AT91_REG(0xFFFFFC30)) /* PMC Master Clock Register */ +#define AT91C_PMC_PCKR (AT91_REG(0xFFFFFC40)) /* PMC Programmable Clock Register */ +#define AT91C_PMC_IER (AT91_REG(0xFFFFFC60)) /* PMC Interrupt Enable Register */ +#define AT91C_PMC_IDR (AT91_REG(0xFFFFFC64)) /* PMC Interrupt Disable Register */ +#define AT91C_PMC_SR (AT91_REG(0xFFFFFC68)) /* PMC Status Register */ +#define AT91C_PMC_IMR (AT91_REG(0xFFFFFC6C)) /* PMC Interrupt Mask Register */ /******************************************************************************/ /* PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 */ /******************************************************************************/ -#define AT91C_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91C_ID_SYS 1 /* System Peripheral */ -#define AT91C_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91C_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91C_ID_ADC 4 /* Analog-to-Digital Converter */ -#define AT91C_ID_SPI 5 /* Serial Peripheral Interface */ -#define AT91C_ID_US0 6 /* USART 0 */ -#define AT91C_ID_US1 7 /* USART 1 */ -#define AT91C_ID_SSC 8 /* Serial Synchronous Controller */ -#define AT91C_ID_TWI 9 /* Two-Wire Interface */ -#define AT91C_ID_PWMC 10 /* PWM Controller */ -#define AT91C_ID_UDP 11 /* USB Device Port */ -#define AT91C_ID_TC0 12 /* Timer Counter 0 */ -#define AT91C_ID_TC1 13 /* Timer Counter 1 */ -#define AT91C_ID_TC2 14 /* Timer Counter 2 */ -#define AT91C_ID_15 15 /* Reserved */ -#define AT91C_ID_16 16 /* Reserved */ -#define AT91C_ID_17 17 /* Reserved */ -#define AT91C_ID_18 18 /* Reserved */ -#define AT91C_ID_19 19 /* Reserved */ -#define AT91C_ID_20 20 /* Reserved */ -#define AT91C_ID_21 21 /* Reserved */ -#define AT91C_ID_22 22 /* Reserved */ -#define AT91C_ID_23 23 /* Reserved */ -#define AT91C_ID_24 24 /* Reserved */ -#define AT91C_ID_25 25 /* Reserved */ -#define AT91C_ID_26 26 /* Reserved */ -#define AT91C_ID_27 27 /* Reserved */ -#define AT91C_ID_28 28 /* Reserved */ -#define AT91C_ID_29 29 /* Reserved */ -#define AT91C_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91C_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ -#define AT91C_ALL_INT 0xC0007FF7 /* ALL VALID INTERRUPTS */ +#define AT91C_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define AT91C_ID_SYS 1 /* System Peripheral */ +#define AT91C_ID_PIOA 2 /* Parallel IO Controller A */ +#define AT91C_ID_PIOB 3 /* Parallel IO Controller B */ +#define AT91C_ID_ADC 4 /* Analog-to-Digital Converter */ +#define AT91C_ID_SPI 5 /* Serial Peripheral Interface */ +#define AT91C_ID_US0 6 /* USART 0 */ +#define AT91C_ID_US1 7 /* USART 1 */ +#define AT91C_ID_SSC 8 /* Serial Synchronous Controller */ +#define AT91C_ID_TWI 9 /* Two-Wire Interface */ +#define AT91C_ID_PWMC 10 /* PWM Controller */ +#define AT91C_ID_UDP 11 /* USB Device Port */ +#define AT91C_ID_TC0 12 /* Timer Counter 0 */ +#define AT91C_ID_TC1 13 /* Timer Counter 1 */ +#define AT91C_ID_TC2 14 /* Timer Counter 2 */ +#define AT91C_ID_15 15 /* Reserved */ +#define AT91C_ID_16 16 /* Reserved */ +#define AT91C_ID_17 17 /* Reserved */ +#define AT91C_ID_18 18 /* Reserved */ +#define AT91C_ID_19 19 /* Reserved */ +#define AT91C_ID_20 20 /* Reserved */ +#define AT91C_ID_21 21 /* Reserved */ +#define AT91C_ID_22 22 /* Reserved */ +#define AT91C_ID_23 23 /* Reserved */ +#define AT91C_ID_24 24 /* Reserved */ +#define AT91C_ID_25 25 /* Reserved */ +#define AT91C_ID_26 26 /* Reserved */ +#define AT91C_ID_27 27 /* Reserved */ +#define AT91C_ID_28 28 /* Reserved */ +#define AT91C_ID_29 29 /* Reserved */ +#define AT91C_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ +#define AT91C_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ +#define AT91C_ALL_INT 0xC0007FF7 /* ALL VALID INTERRUPTS */ /*****************************/ /* CPU Mode */ /*****************************/ -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define ABORTMODE 0x17 -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define ABORTMODE 0x17 +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 #ifdef __cplusplus } diff --git a/libcpu/arm/AT91SAM7S/cpu.c b/libcpu/arm/AT91SAM7S/cpu.c index 8d28063eb1..8a6943dca1 100644 --- a/libcpu/arm/AT91SAM7S/cpu.c +++ b/libcpu/arm/AT91SAM7S/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -30,9 +30,9 @@ void rt_hw_cpu_reset() */ void rt_hw_cpu_shutdown() { - rt_kprintf("shutdown...\n"); + rt_kprintf("shutdown...\n"); - while (1); + while (1); } /*@}*/ diff --git a/libcpu/arm/AT91SAM7S/interrupt.c b/libcpu/arm/AT91SAM7S/interrupt.c index db9d31fe28..e4aa8643f1 100644 --- a/libcpu/arm/AT91SAM7S/interrupt.c +++ b/libcpu/arm/AT91SAM7S/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -11,7 +11,7 @@ #include #include "AT91SAM7S.h" -#define MAX_HANDLERS 32 +#define MAX_HANDLERS 32 extern rt_uint32_t rt_interrupt_nest; @@ -25,7 +25,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag; void rt_hw_interrupt_handler(int vector) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } /** @@ -33,18 +33,18 @@ void rt_hw_interrupt_handler(int vector) */ void rt_hw_interrupt_init() { - rt_base_t index; + rt_base_t index; - for (index = 0; index < MAX_HANDLERS; index ++) - { - AT91C_AIC_SVR(index) = (rt_uint32_t)rt_hw_interrupt_handler; - } + for (index = 0; index < MAX_HANDLERS; index ++) + { + AT91C_AIC_SVR(index) = (rt_uint32_t)rt_hw_interrupt_handler; + } - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; } /** @@ -53,11 +53,11 @@ void rt_hw_interrupt_init() */ void rt_hw_interrupt_mask(int vector) { - /* disable interrupt */ - AT91C_AIC_IDCR = 1 << vector; + /* disable interrupt */ + AT91C_AIC_IDCR = 1 << vector; - /* clear interrupt */ - AT91C_AIC_ICCR = 1 << vector; + /* clear interrupt */ + AT91C_AIC_ICCR = 1 << vector; } /** @@ -66,7 +66,7 @@ void rt_hw_interrupt_mask(int vector) */ void rt_hw_interrupt_umask(int vector) { - AT91C_AIC_IECR = 1 << vector; + AT91C_AIC_IECR = 1 << vector; } /** @@ -77,11 +77,11 @@ void rt_hw_interrupt_umask(int vector) */ void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler) { - if(vector >= 0 && vector < MAX_HANDLERS) - { - if (*old_handler != RT_NULL) *old_handler = (rt_isr_handler_t)AT91C_AIC_SVR(vector); - if (new_handler != RT_NULL) AT91C_AIC_SVR(vector) = (rt_uint32_t)new_handler; - } + if(vector >= 0 && vector < MAX_HANDLERS) + { + if (*old_handler != RT_NULL) *old_handler = (rt_isr_handler_t)AT91C_AIC_SVR(vector); + if (new_handler != RT_NULL) AT91C_AIC_SVR(vector) = (rt_uint32_t)new_handler; + } } /*@}*/ diff --git a/libcpu/arm/AT91SAM7S/serial.c b/libcpu/arm/AT91SAM7S/serial.c index adbe8609d6..583443f4cb 100644 --- a/libcpu/arm/AT91SAM7S/serial.c +++ b/libcpu/arm/AT91SAM7S/serial.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,46 +22,46 @@ typedef volatile rt_uint32_t REG32; struct rt_at91serial_hw { - REG32 US_CR; // Control Register - REG32 US_MR; // Mode Register - REG32 US_IER; // Interrupt Enable Register - REG32 US_IDR; // Interrupt Disable Register - REG32 US_IMR; // Interrupt Mask Register - REG32 US_CSR; // Channel Status Register - REG32 US_RHR; // Receiver Holding Register - REG32 US_THR; // Transmitter Holding Register - REG32 US_BRGR; // Baud Rate Generator Register - REG32 US_RTOR; // Receiver Time-out Register - REG32 US_TTGR; // Transmitter Time-guard Register - REG32 Reserved0[5]; // - REG32 US_FIDI; // FI_DI_Ratio Register - REG32 US_NER; // Nb Errors Register - REG32 Reserved1[1]; // - REG32 US_IF; // IRDA_FILTER Register - REG32 Reserved2[44]; // - REG32 US_RPR; // Receive Pointer Register - REG32 US_RCR; // Receive Counter Register - REG32 US_TPR; // Transmit Pointer Register - REG32 US_TCR; // Transmit Counter Register - REG32 US_RNPR; // Receive Next Pointer Register - REG32 US_RNCR; // Receive Next Counter Register - REG32 US_TNPR; // Transmit Next Pointer Register - REG32 US_TNCR; // Transmit Next Counter Register - REG32 US_PTCR; // PDC Transfer Control Register - REG32 US_PTSR; // PDC Transfer Status Register + REG32 US_CR; // Control Register + REG32 US_MR; // Mode Register + REG32 US_IER; // Interrupt Enable Register + REG32 US_IDR; // Interrupt Disable Register + REG32 US_IMR; // Interrupt Mask Register + REG32 US_CSR; // Channel Status Register + REG32 US_RHR; // Receiver Holding Register + REG32 US_THR; // Transmitter Holding Register + REG32 US_BRGR; // Baud Rate Generator Register + REG32 US_RTOR; // Receiver Time-out Register + REG32 US_TTGR; // Transmitter Time-guard Register + REG32 Reserved0[5]; // + REG32 US_FIDI; // FI_DI_Ratio Register + REG32 US_NER; // Nb Errors Register + REG32 Reserved1[1]; // + REG32 US_IF; // IRDA_FILTER Register + REG32 Reserved2[44]; // + REG32 US_RPR; // Receive Pointer Register + REG32 US_RCR; // Receive Counter Register + REG32 US_TPR; // Transmit Pointer Register + REG32 US_TCR; // Transmit Counter Register + REG32 US_RNPR; // Receive Next Pointer Register + REG32 US_RNCR; // Receive Next Counter Register + REG32 US_TNPR; // Transmit Next Pointer Register + REG32 US_TNCR; // Transmit Next Counter Register + REG32 US_PTCR; // PDC Transfer Control Register + REG32 US_PTSR; // PDC Transfer Status Register }; struct rt_at91serial { - struct rt_device parent; + struct rt_device parent; - struct rt_at91serial_hw* hw_base; - rt_uint16_t peripheral_id; - rt_uint32_t baudrate; + struct rt_at91serial_hw* hw_base; + rt_uint16_t peripheral_id; + rt_uint32_t baudrate; - /* reception field */ - rt_uint16_t save_index, read_index; - rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; + /* reception field */ + rt_uint16_t save_index, read_index; + rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; }; #ifdef RT_USING_UART1 struct rt_at91serial serial1; @@ -72,312 +72,312 @@ struct rt_at91serial serial2; static void rt_hw_serial_isr(int irqno) { - rt_base_t level; - struct rt_device* device; - struct rt_at91serial* serial = RT_NULL; + rt_base_t level; + struct rt_device* device; + struct rt_at91serial* serial = RT_NULL; - if (irqno == AT91C_ID_US0) - { + if (irqno == AT91C_ID_US0) + { #ifdef RT_USING_UART1 - /* serial 1 */ - serial = &serial1; + /* serial 1 */ + serial = &serial1; #endif - } - else if (irqno == AT91C_ID_US1) - { + } + else if (irqno == AT91C_ID_US1) + { #ifdef RT_USING_UART2 - /* serial 2 */ - serial = &serial2; + /* serial 2 */ + serial = &serial2; #endif - } - RT_ASSERT(serial != RT_NULL); + } + RT_ASSERT(serial != RT_NULL); - /* get generic device object */ - device = (rt_device_t)serial; + /* get generic device object */ + device = (rt_device_t)serial; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - /* get received character */ - serial->rx_buffer[serial->save_index] = serial->hw_base->US_RHR; + /* get received character */ + serial->rx_buffer[serial->save_index] = serial->hw_base->US_RHR; - /* move to next position */ - serial->save_index ++; - if (serial->save_index >= RT_UART_RX_BUFFER_SIZE) - serial->save_index = 0; + /* move to next position */ + serial->save_index ++; + if (serial->save_index >= RT_UART_RX_BUFFER_SIZE) + serial->save_index = 0; - /* if the next position is read index, discard this 'read char' */ - if (serial->save_index == serial->read_index) - { - serial->read_index ++; - if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) - serial->read_index = 0; - } + /* if the next position is read index, discard this 'read char' */ + if (serial->save_index == serial->read_index) + { + serial->read_index ++; + if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) + serial->read_index = 0; + } - /* enable interrupt */ - rt_hw_interrupt_enable(level); + /* enable interrupt */ + rt_hw_interrupt_enable(level); - /* indicate to upper layer application */ - if (device->rx_indicate != RT_NULL) - device->rx_indicate(device, 1); + /* indicate to upper layer application */ + if (device->rx_indicate != RT_NULL) + device->rx_indicate(device, 1); - /* ack interrupt */ - AT91C_AIC_EOICR = 1; + /* ack interrupt */ + AT91C_AIC_EOICR = 1; } static rt_err_t rt_serial_init (rt_device_t dev) { - rt_uint32_t bd; - struct rt_at91serial* serial = (struct rt_at91serial*) dev; - - RT_ASSERT(serial != RT_NULL); - /* must be US0 or US1 */ - RT_ASSERT(((serial->peripheral_id == AT91C_ID_US0) || - (serial->peripheral_id == AT91C_ID_US1))); - - /* Enable Clock for USART */ - AT91C_PMC_PCER = 1 << serial->peripheral_id; - - /* Enable RxD0 and TxDO Pin */ - if (serial->peripheral_id == AT91C_ID_US0) - { - /* set pinmux */ - AT91C_PIO_PDR = (1 << 5) | (1 << 6); - } - else if (serial->peripheral_id == AT91C_ID_US1) - { - /* set pinmux */ - AT91C_PIO_PDR = (1 << 21) | (1 << 22); - } - - serial->hw_base->US_CR = AT91C_US_RSTRX | /* Reset Receiver */ - AT91C_US_RSTTX | /* Reset Transmitter */ - AT91C_US_RXDIS | /* Receiver Disable */ - AT91C_US_TXDIS; /* Transmitter Disable */ - - serial->hw_base->US_MR = AT91C_US_USMODE_NORMAL | /* Normal Mode */ - AT91C_US_CLKS_CLOCK | /* Clock = MCK */ - AT91C_US_CHRL_8_BITS | /* 8-bit Data */ - AT91C_US_PAR_NONE | /* No Parity */ - AT91C_US_NBSTOP_1_BIT; /* 1 Stop Bit */ - - /* set baud rate divisor */ - bd = ((MCK*10)/(serial->baudrate * 16)); - if ((bd % 10) >= 5) bd = (bd / 10) + 1; - else bd /= 10; - - serial->hw_base->US_BRGR = bd; - serial->hw_base->US_CR = AT91C_US_RXEN | /* Receiver Enable */ - AT91C_US_TXEN; /* Transmitter Enable */ - - /* reset rx index */ - serial->save_index = 0; - serial->read_index = 0; - - /* reset rx buffer */ - rt_memset(serial->rx_buffer, 0, RT_UART_RX_BUFFER_SIZE); - - return RT_EOK; + rt_uint32_t bd; + struct rt_at91serial* serial = (struct rt_at91serial*) dev; + + RT_ASSERT(serial != RT_NULL); + /* must be US0 or US1 */ + RT_ASSERT(((serial->peripheral_id == AT91C_ID_US0) || + (serial->peripheral_id == AT91C_ID_US1))); + + /* Enable Clock for USART */ + AT91C_PMC_PCER = 1 << serial->peripheral_id; + + /* Enable RxD0 and TxDO Pin */ + if (serial->peripheral_id == AT91C_ID_US0) + { + /* set pinmux */ + AT91C_PIO_PDR = (1 << 5) | (1 << 6); + } + else if (serial->peripheral_id == AT91C_ID_US1) + { + /* set pinmux */ + AT91C_PIO_PDR = (1 << 21) | (1 << 22); + } + + serial->hw_base->US_CR = AT91C_US_RSTRX | /* Reset Receiver */ + AT91C_US_RSTTX | /* Reset Transmitter */ + AT91C_US_RXDIS | /* Receiver Disable */ + AT91C_US_TXDIS; /* Transmitter Disable */ + + serial->hw_base->US_MR = AT91C_US_USMODE_NORMAL | /* Normal Mode */ + AT91C_US_CLKS_CLOCK | /* Clock = MCK */ + AT91C_US_CHRL_8_BITS | /* 8-bit Data */ + AT91C_US_PAR_NONE | /* No Parity */ + AT91C_US_NBSTOP_1_BIT; /* 1 Stop Bit */ + + /* set baud rate divisor */ + bd = ((MCK*10)/(serial->baudrate * 16)); + if ((bd % 10) >= 5) bd = (bd / 10) + 1; + else bd /= 10; + + serial->hw_base->US_BRGR = bd; + serial->hw_base->US_CR = AT91C_US_RXEN | /* Receiver Enable */ + AT91C_US_TXEN; /* Transmitter Enable */ + + /* reset rx index */ + serial->save_index = 0; + serial->read_index = 0; + + /* reset rx buffer */ + rt_memset(serial->rx_buffer, 0, RT_UART_RX_BUFFER_SIZE); + + return RT_EOK; } static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) { - struct rt_at91serial *serial = (struct rt_at91serial*)dev; - RT_ASSERT(serial != RT_NULL); - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* enable UART rx interrupt */ - serial->hw_base->US_IER = 1 << 0; /* RxReady interrupt */ - serial->hw_base->US_IMR |= 1 << 0; /* umask RxReady interrupt */ - - /* install UART handler */ - rt_hw_interrupt_install(serial->peripheral_id, rt_hw_serial_isr, RT_NULL); - AT91C_AIC_SMR(serial->peripheral_id) = 5 | (0x01 << 5); - rt_hw_interrupt_umask(serial->peripheral_id); - } - - return RT_EOK; + struct rt_at91serial *serial = (struct rt_at91serial*)dev; + RT_ASSERT(serial != RT_NULL); + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* enable UART rx interrupt */ + serial->hw_base->US_IER = 1 << 0; /* RxReady interrupt */ + serial->hw_base->US_IMR |= 1 << 0; /* umask RxReady interrupt */ + + /* install UART handler */ + rt_hw_interrupt_install(serial->peripheral_id, rt_hw_serial_isr, RT_NULL); + AT91C_AIC_SMR(serial->peripheral_id) = 5 | (0x01 << 5); + rt_hw_interrupt_umask(serial->peripheral_id); + } + + return RT_EOK; } static rt_err_t rt_serial_close(rt_device_t dev) { - struct rt_at91serial *serial = (struct rt_at91serial*)dev; - RT_ASSERT(serial != RT_NULL); + struct rt_at91serial *serial = (struct rt_at91serial*)dev; + RT_ASSERT(serial != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* disable interrupt */ - serial->hw_base->US_IDR = 1 << 0; /* RxReady interrupt */ - serial->hw_base->US_IMR &= ~(1 << 0); /* mask RxReady interrupt */ - } + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* disable interrupt */ + serial->hw_base->US_IDR = 1 << 0; /* RxReady interrupt */ + serial->hw_base->US_IMR &= ~(1 << 0); /* mask RxReady interrupt */ + } - return RT_EOK; + return RT_EOK; } static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - struct rt_at91serial *serial = (struct rt_at91serial*)dev; - RT_ASSERT(serial != RT_NULL); - - /* point to buffer */ - ptr = (rt_uint8_t*) buffer; - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - while (size) - { - /* interrupt receive */ - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - if (serial->read_index != serial->save_index) - { - *ptr = serial->rx_buffer[serial->read_index]; - - serial->read_index ++; - if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) - serial->read_index = 0; - } - else - { - /* no data in rx buffer */ - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - break; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - - ptr ++; size --; - } - - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; - } - else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) - { - /* not support right now */ - RT_ASSERT(0); - } - else - { - /* poll mode */ - while (size) - { - /* Wait for Full Rx Buffer */ - while (!(serial->hw_base->US_CSR & AT91C_US_RXRDY)); - - /* Read Character */ - *ptr = serial->hw_base->US_RHR; - ptr ++; - size --; - } - - return (rt_size_t)ptr - (rt_size_t)buffer; - } - - return 0; + rt_uint8_t* ptr; + struct rt_at91serial *serial = (struct rt_at91serial*)dev; + RT_ASSERT(serial != RT_NULL); + + /* point to buffer */ + ptr = (rt_uint8_t*) buffer; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + while (size) + { + /* interrupt receive */ + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + if (serial->read_index != serial->save_index) + { + *ptr = serial->rx_buffer[serial->read_index]; + + serial->read_index ++; + if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) + serial->read_index = 0; + } + else + { + /* no data in rx buffer */ + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + ptr ++; size --; + } + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) + { + /* not support right now */ + RT_ASSERT(0); + } + else + { + /* poll mode */ + while (size) + { + /* Wait for Full Rx Buffer */ + while (!(serial->hw_base->US_CSR & AT91C_US_RXRDY)); + + /* Read Character */ + *ptr = serial->hw_base->US_RHR; + ptr ++; + size --; + } + + return (rt_size_t)ptr - (rt_size_t)buffer; + } + + return 0; } static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - struct rt_at91serial *serial = (struct rt_at91serial*)dev; - RT_ASSERT(serial != RT_NULL); - - ptr = (rt_uint8_t*) buffer; - if (dev->open_flag & RT_DEVICE_OFLAG_WRONLY) - { - if (dev->flag & RT_DEVICE_FLAG_STREAM) - { - /* it's a stream mode device */ - while (size) - { - /* stream mode */ - if (*ptr == '\n') - { - while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); - serial->hw_base->US_THR = '\r'; - } - - /* Wait for Empty Tx Buffer */ - while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); - - /* Transmit Character */ - serial->hw_base->US_THR = *ptr; - ptr ++; size --; - } - } - else - { - while (size) - { - /* Wait for Empty Tx Buffer */ - while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); - - /* Transmit Character */ - serial->hw_base->US_THR = *ptr; - ptr ++; size --; - } - } - } - - return (rt_size_t)ptr - (rt_size_t)buffer; + rt_uint8_t* ptr; + struct rt_at91serial *serial = (struct rt_at91serial*)dev; + RT_ASSERT(serial != RT_NULL); + + ptr = (rt_uint8_t*) buffer; + if (dev->open_flag & RT_DEVICE_OFLAG_WRONLY) + { + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* it's a stream mode device */ + while (size) + { + /* stream mode */ + if (*ptr == '\n') + { + while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); + serial->hw_base->US_THR = '\r'; + } + + /* Wait for Empty Tx Buffer */ + while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); + + /* Transmit Character */ + serial->hw_base->US_THR = *ptr; + ptr ++; size --; + } + } + else + { + while (size) + { + /* Wait for Empty Tx Buffer */ + while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); + + /* Transmit Character */ + serial->hw_base->US_THR = *ptr; + ptr ++; size --; + } + } + } + + return (rt_size_t)ptr - (rt_size_t)buffer; } static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) { - return RT_EOK; + return RT_EOK; } rt_err_t rt_hw_serial_init() { - rt_device_t device; + rt_device_t device; #ifdef RT_USING_UART1 - device = (rt_device_t) &serial1; - - /* init serial device private data */ - serial1.hw_base = (struct rt_at91serial_hw*)AT91C_BASE_US0; - serial1.peripheral_id = AT91C_ID_US0; - serial1.baudrate = 115200; - - /* set device virtual interface */ - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; - - /* register uart1 on device subsystem */ - rt_device_register(device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); + device = (rt_device_t) &serial1; + + /* init serial device private data */ + serial1.hw_base = (struct rt_at91serial_hw*)AT91C_BASE_US0; + serial1.peripheral_id = AT91C_ID_US0; + serial1.baudrate = 115200; + + /* set device virtual interface */ + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; + + /* register uart1 on device subsystem */ + rt_device_register(device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); #endif #ifdef RT_USING_UART2 - device = (rt_device_t) &serial2; - - serial2.hw_base = (struct rt_at91serial_hw*)AT91C_BASE_US1; - serial2.peripheral_id = AT91C_ID_US1; - serial2.baudrate = 115200; - - /* set device virtual interface */ - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; - - /* register uart2 on device subsystem */ - rt_device_register(device, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); + device = (rt_device_t) &serial2; + + serial2.hw_base = (struct rt_at91serial_hw*)AT91C_BASE_US1; + serial2.peripheral_id = AT91C_ID_US1; + serial2.baudrate = 115200; + + /* set device virtual interface */ + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; + + /* register uart2 on device subsystem */ + rt_device_register(device, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); #endif - return RT_EOK; + return RT_EOK; } /*@}*/ diff --git a/libcpu/arm/AT91SAM7S/serial.h b/libcpu/arm/AT91SAM7S/serial.h index 0937e92f6c..7766053a7f 100644 --- a/libcpu/arm/AT91SAM7S/serial.h +++ b/libcpu/arm/AT91SAM7S/serial.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,48 +17,48 @@ #define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address #endif -#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* US RXRDY Interrupt */ -#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* US TXRDY Interrupt */ -#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* US Reset Receiver */ -#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) /* US Reset Transmitter */ -#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) /* US Receiver Enable */ -#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) /* US Receiver Disable */ -#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) /* US Transmitter Enable */ -#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) /* US Transmitter Disable */ -#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) /* US Reset Status Bits */ +#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* US RXRDY Interrupt */ +#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* US TXRDY Interrupt */ +#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* US Reset Receiver */ +#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) /* US Reset Transmitter */ +#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) /* US Receiver Enable */ +#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) /* US Receiver Disable */ +#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) /* US Transmitter Enable */ +#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) /* US Transmitter Disable */ +#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) /* US Reset Status Bits */ -#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) /* USAR) Normal */ -#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) /* USAR) RS485 */ -#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) /* USAR) Hardware Handshaking */ -#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) /* USAR) Modem */ -#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) /* USAR) ISO7816 protocol: T = 0 */ -#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) /* USAR) ISO7816 protocol: T = 1 */ -#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) /* USAR) IrDA */ -#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) /* USAR) Software Handshaking */ +#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) /* USAR) Normal */ +#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) /* USAR) RS485 */ +#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) /* USAR) Hardware Handshaking */ +#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) /* USAR) Modem */ +#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) /* USAR) ISO7816 protocol: T = 0 */ +#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) /* USAR) ISO7816 protocol: T = 1 */ +#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) /* USAR) IrDA */ +#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) /* USAR) Software Handshaking */ -#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) /* USAR) Clock */ -#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) /* USAR) fdiv1 */ -#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) /* USAR) slow_clock (ARM) */ -#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) /* USAR) External (SCK) */ +#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) /* USAR) Clock */ +#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) /* USAR) fdiv1 */ +#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) /* USAR) slow_clock (ARM) */ +#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) /* USAR) External (SCK) */ -#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) /* USAR) Character Length: 5 bits */ -#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) /* USAR) Character Length: 6 bits */ -#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) /* USAR) Character Length: 7 bits */ -#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) /* USAR) Character Length: 8 bits */ +#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) /* USAR) Character Length: 5 bits */ +#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) /* USAR) Character Length: 6 bits */ +#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) /* USAR) Character Length: 7 bits */ +#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) /* USAR) Character Length: 8 bits */ -#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) /* DBGU Even Parity */ -#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) /* DBGU Odd Parity */ -#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) /* DBGU Parity forced to 0 (Space) */ -#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) /* DBGU Parity forced to 1 (Mark) */ -#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* DBGU No Parity */ -#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) /* DBGU Multi-drop mode */ +#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) /* DBGU Even Parity */ +#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) /* DBGU Odd Parity */ +#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) /* DBGU Parity forced to 0 (Space) */ +#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) /* DBGU Parity forced to 1 (Mark) */ +#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* DBGU No Parity */ +#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) /* DBGU Multi-drop mode */ -#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* USART 1 stop bit */ -#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) /* USART Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */ -#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) /* USART 2 stop bits */ +#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* USART 1 stop bit */ +#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) /* USART Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */ +#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) /* USART 2 stop bits */ -#define MCK 48054857 -#define BR 115200 /* Baud Rate */ -#define BRD (MCK/16/BR) /* Baud Rate Divisor */ +#define MCK 48054857 +#define BR 115200 /* Baud Rate */ +#define BRD (MCK/16/BR) /* Baud Rate Divisor */ #endif diff --git a/libcpu/arm/AT91SAM7S/stack.c b/libcpu/arm/AT91SAM7S/stack.c index 6f8bd13bf9..23fce8e6e2 100644 --- a/libcpu/arm/AT91SAM7S/stack.c +++ b/libcpu/arm/AT91SAM7S/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/AT91SAM7S/trap.c b/libcpu/arm/AT91SAM7S/trap.c index 208e568950..aa9df7c74b 100644 --- a/libcpu/arm/AT91SAM7S/trap.c +++ b/libcpu/arm/AT91SAM7S/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,12 +20,12 @@ void rt_hw_trap_irq() { - rt_isr_handler_t hander = (rt_isr_handler_t)AT91C_AIC_IVR; + rt_isr_handler_t hander = (rt_isr_handler_t)AT91C_AIC_IVR; - hander(AT91C_AIC_ISR); + hander(AT91C_AIC_ISR); - /* end of interrupt */ - AT91C_AIC_EOICR = 0; + /* end of interrupt */ + AT91C_AIC_EOICR = 0; } void rt_hw_trap_fiq() diff --git a/libcpu/arm/AT91SAM7X/cpu.c b/libcpu/arm/AT91SAM7X/cpu.c index 484c19d10a..7c950dab78 100644 --- a/libcpu/arm/AT91SAM7X/cpu.c +++ b/libcpu/arm/AT91SAM7X/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -30,9 +30,9 @@ void rt_hw_cpu_reset() */ void rt_hw_cpu_shutdown() { - rt_kprintf("shutdown...\n"); + rt_kprintf("shutdown...\n"); - while (1); + while (1); } /*@}*/ diff --git a/libcpu/arm/AT91SAM7X/interrupt.c b/libcpu/arm/AT91SAM7X/interrupt.c index 0c37f63ada..3a28f507ca 100644 --- a/libcpu/arm/AT91SAM7X/interrupt.c +++ b/libcpu/arm/AT91SAM7X/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,10 +13,10 @@ #include #include "AT91SAM7X256.h" -#define MAX_HANDLERS 32 +#define MAX_HANDLERS 32 /* exception and interrupt handler table */ -struct rt_irq_desc irq_desc[MAX_HANDLERS]; +struct rt_irq_desc irq_desc[MAX_HANDLERS]; extern rt_uint32_t rt_interrupt_nest; @@ -30,7 +30,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag; static void rt_hw_interrupt_handler(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } /** @@ -38,7 +38,7 @@ static void rt_hw_interrupt_handler(int vector, void *param) */ void rt_hw_interrupt_init(void) { - rt_base_t index; + rt_base_t index; /* init exceptions table */ for(index=0; index < MAX_HANDLERS; index++) @@ -47,16 +47,16 @@ void rt_hw_interrupt_init(void) irq_desc[index].param = RT_NULL; } - for (index = 0; index < MAX_HANDLERS; index ++) - { - AT91C_BASE_AIC->AIC_SVR[index] = (rt_uint32_t)rt_hw_interrupt_handler; - } + for (index = 0; index < MAX_HANDLERS; index ++) + { + AT91C_BASE_AIC->AIC_SVR[index] = (rt_uint32_t)rt_hw_interrupt_handler; + } - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; } /** @@ -65,11 +65,11 @@ void rt_hw_interrupt_init(void) */ void rt_hw_interrupt_mask(int vector) { - /* disable interrupt */ - AT91C_BASE_AIC->AIC_IDCR = 1 << vector; + /* disable interrupt */ + AT91C_BASE_AIC->AIC_IDCR = 1 << vector; - /* clear interrupt */ - AT91C_BASE_AIC->AIC_ICCR = 1 << vector; + /* clear interrupt */ + AT91C_BASE_AIC->AIC_ICCR = 1 << vector; } /** @@ -78,7 +78,7 @@ void rt_hw_interrupt_mask(int vector) */ void rt_hw_interrupt_umask(int vector) { - AT91C_BASE_AIC->AIC_IECR = 1 << vector; + AT91C_BASE_AIC->AIC_IECR = 1 << vector; } /** @@ -90,21 +90,21 @@ void rt_hw_interrupt_umask(int vector) * * @return the old handler */ -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name) { - rt_isr_handler_t old_handler = RT_NULL; - if(vector >= 0 && vector < MAX_HANDLERS) - { - old_handler = irq_desc[vector].handler; - if (handler != RT_NULL) - { - irq_desc[vector].handler = (rt_isr_handler_t)handler; - irq_desc[vector].param = param; - } - } - - return old_handler; + rt_isr_handler_t old_handler = RT_NULL; + if(vector >= 0 && vector < MAX_HANDLERS) + { + old_handler = irq_desc[vector].handler; + if (handler != RT_NULL) + { + irq_desc[vector].handler = (rt_isr_handler_t)handler; + irq_desc[vector].param = param; + } + } + + return old_handler; } /*@}*/ diff --git a/libcpu/arm/AT91SAM7X/stack.c b/libcpu/arm/AT91SAM7X/stack.c index ef60b1a760..caa4826014 100644 --- a/libcpu/arm/AT91SAM7X/stack.c +++ b/libcpu/arm/AT91SAM7X/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/AT91SAM7X/trap.c b/libcpu/arm/AT91SAM7X/trap.c index 1c1c351ff8..3c012dd85e 100644 --- a/libcpu/arm/AT91SAM7X/trap.c +++ b/libcpu/arm/AT91SAM7X/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,17 +20,17 @@ void rt_hw_trap_irq(void) { - int irqno; - extern struct rt_irq_desc irq_desc[]; + int irqno; + extern struct rt_irq_desc irq_desc[]; - /* get interrupt number */ - irqno = AT91C_BASE_AIC->AIC_ISR; + /* get interrupt number */ + irqno = AT91C_BASE_AIC->AIC_ISR; - /* invoke isr with parameters */ - irq_desc[irqno].handler(irqno, irq_desc[irqno].param); + /* invoke isr with parameters */ + irq_desc[irqno].handler(irqno, irq_desc[irqno].param); - /* end of interrupt */ - AT91C_BASE_AIC->AIC_EOICR = 0; + /* end of interrupt */ + AT91C_BASE_AIC->AIC_EOICR = 0; } void rt_hw_trap_fiq(void) @@ -41,9 +41,9 @@ void rt_hw_trap_fiq(void) extern struct rt_thread* rt_current_thread; void rt_hw_trap_abort(void) { - rt_kprintf("Abort occured!!! Thread [%s] suspended.\n",rt_current_thread->name); - rt_thread_suspend(rt_current_thread); - rt_schedule(); + rt_kprintf("Abort occured!!! Thread [%s] suspended.\n",rt_current_thread->name); + rt_thread_suspend(rt_current_thread); + rt_schedule(); } /*@}*/ diff --git a/libcpu/arm/am335x/am33xx.h b/libcpu/arm/am335x/am33xx.h index 99a65ac915..3112a8ac15 100644 --- a/libcpu/arm/am335x/am33xx.h +++ b/libcpu/arm/am335x/am33xx.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -9,8 +9,8 @@ #ifndef __AM33XX_H__ #define __AM33XX_H__ -#define REG32(x) (*((volatile unsigned int *)(x))) -#define REG16(x) (*((volatile unsigned short *)(x))) +#define REG32(x) (*((volatile unsigned int *)(x))) +#define REG16(x) (*((volatile unsigned short *)(x))) /** Cache Line size in ARM Cortex-A8. */ #define AM33XX_CACHELINE_SIZE (64) @@ -198,22 +198,22 @@ #define CM_DPLL_CLKSEL_TIMER2_CLK(base) REG32(CM_DPLL(base) + 0x8) /* timer registers */ -#define DMTIMER_TIDR(base) REG32(base + 0x0) -#define DMTIMER_TIOCP_CFG(base) REG32(base + 0x10) -#define DMTIMER_IRQ_EOI(base) REG32(base + 0x20) -#define DMTIMER_IRQSTATUS_RAW(base) REG32(base + 0x24) -#define DMTIMER_IRQSTATUS(base) REG32(base + 0x28) -#define DMTIMER_IRQENABLE_SET(base) REG32(base + 0x2C) -#define DMTIMER_IRQENABLE_CLR(base) REG32(base + 0x30) -#define DMTIMER_IRQWAKEEN(base) REG32(base + 0x34) -#define DMTIMER_TCLR(base) REG32(base + 0x38) -#define DMTIMER_TCRR(base) REG32(base + 0x3C) -#define DMTIMER_TLDR(base) REG32(base + 0x40) -#define DMTIMER_TTGR(base) REG32(base + 0x44) -#define DMTIMER_TWPS(base) REG32(base + 0x48) -#define DMTIMER_TMAR(base) REG32(base + 0x4C) -#define DMTIMER_TCAR(base, n) REG32(base + 0x50 + (((n) - 1) * 8)) -#define DMTIMER_TSICR(base) REG32(base + 0x54) +#define DMTIMER_TIDR(base) REG32(base + 0x0) +#define DMTIMER_TIOCP_CFG(base) REG32(base + 0x10) +#define DMTIMER_IRQ_EOI(base) REG32(base + 0x20) +#define DMTIMER_IRQSTATUS_RAW(base) REG32(base + 0x24) +#define DMTIMER_IRQSTATUS(base) REG32(base + 0x28) +#define DMTIMER_IRQENABLE_SET(base) REG32(base + 0x2C) +#define DMTIMER_IRQENABLE_CLR(base) REG32(base + 0x30) +#define DMTIMER_IRQWAKEEN(base) REG32(base + 0x34) +#define DMTIMER_TCLR(base) REG32(base + 0x38) +#define DMTIMER_TCRR(base) REG32(base + 0x3C) +#define DMTIMER_TLDR(base) REG32(base + 0x40) +#define DMTIMER_TTGR(base) REG32(base + 0x44) +#define DMTIMER_TWPS(base) REG32(base + 0x48) +#define DMTIMER_TMAR(base) REG32(base + 0x4C) +#define DMTIMER_TCAR(base, n) REG32(base + 0x50 + (((n) - 1) * 8)) +#define DMTIMER_TSICR(base) REG32(base + 0x54) #define EMU_INT 0 #define COMMTX_INT 1 @@ -317,33 +317,33 @@ struct rt_hw_register { - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; - unsigned long ORIG_r0; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; + unsigned long ORIG_r0; }; -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define ABORTMODE 0x17 -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define ABORTMODE 0x17 +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 #endif diff --git a/libcpu/arm/am335x/cpu.c b/libcpu/arm/am335x/cpu.c index cae865fe50..284e2ea260 100644 --- a/libcpu/arm/am335x/cpu.c +++ b/libcpu/arm/am335x/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,74 +17,74 @@ */ /*@{*/ -#define ICACHE_MASK (rt_uint32_t)(1 << 12) -#define DCACHE_MASK (rt_uint32_t)(1 << 2) +#define ICACHE_MASK (rt_uint32_t)(1 << 12) +#define DCACHE_MASK (rt_uint32_t)(1 << 2) #if defined(__CC_ARM) rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - __asm - { - mrc p15, 0, i, c1, c0, 0 - } + __asm + { + mrc p15, 0, i, c1, c0, 0 + } - return i; + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } rt_inline void cache_disable(rt_uint32_t bit) { - rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } #elif defined(__GNUC__) rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - return i; + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "orr r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "orr r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } rt_inline void cache_disable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "bic r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "bic r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } #endif @@ -96,7 +96,7 @@ rt_inline void cache_disable(rt_uint32_t bit) */ void rt_hw_cpu_icache_enable() { - cache_enable(ICACHE_MASK); + cache_enable(ICACHE_MASK); } /** @@ -105,7 +105,7 @@ void rt_hw_cpu_icache_enable() */ void rt_hw_cpu_icache_disable() { - cache_disable(ICACHE_MASK); + cache_disable(ICACHE_MASK); } /** @@ -114,7 +114,7 @@ void rt_hw_cpu_icache_disable() */ rt_base_t rt_hw_cpu_icache_status() { - return (cp15_rd() & ICACHE_MASK); + return (cp15_rd() & ICACHE_MASK); } /** @@ -123,7 +123,7 @@ rt_base_t rt_hw_cpu_icache_status() */ void rt_hw_cpu_dcache_enable() { - cache_enable(DCACHE_MASK); + cache_enable(DCACHE_MASK); } /** @@ -132,7 +132,7 @@ void rt_hw_cpu_dcache_enable() */ void rt_hw_cpu_dcache_disable() { - cache_disable(DCACHE_MASK); + cache_disable(DCACHE_MASK); } /** @@ -141,7 +141,7 @@ void rt_hw_cpu_dcache_disable() */ rt_base_t rt_hw_cpu_dcache_status() { - return (cp15_rd() & DCACHE_MASK); + return (cp15_rd() & DCACHE_MASK); } #endif @@ -151,14 +151,14 @@ rt_base_t rt_hw_cpu_dcache_status() */ void rt_hw_cpu_shutdown() { - rt_uint32_t level; - rt_kprintf("shutdown...\n"); - - level = rt_hw_interrupt_disable(); - while (level) - { - RT_ASSERT(0); - } + rt_uint32_t level; + rt_kprintf("shutdown...\n"); + + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } } /*@}*/ diff --git a/libcpu/arm/am335x/interrupt.c b/libcpu/arm/am335x/interrupt.c index 3acd868496..c4c5e8d7eb 100644 --- a/libcpu/arm/am335x/interrupt.c +++ b/libcpu/arm/am335x/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,7 +17,7 @@ #define AINTC_BASE AM33XX_AINTC_REGS -#define MAX_HANDLERS 128 +#define MAX_HANDLERS 128 extern volatile rt_uint8_t rt_interrupt_nest; @@ -59,13 +59,13 @@ extern int system_vectors; static void rt_hw_vector_init(void) { unsigned int *dest = (unsigned int *)AM335X_VECTOR_BASE; - + #ifdef __ICCARM__ unsigned int *src = (unsigned int *)&__vector; #else unsigned int *src = (unsigned int *)&system_vectors; #endif - + rt_memcpy(dest, src, 16 * 4); rt_cpu_vector_set_base(AM335X_VECTOR_BASE); } diff --git a/libcpu/arm/am335x/interrupt.h b/libcpu/arm/am335x/interrupt.h index 7461f94da0..90f392f407 100644 --- a/libcpu/arm/am335x/interrupt.h +++ b/libcpu/arm/am335x/interrupt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,28 +14,28 @@ #define INT_IRQ 0x00 #define INT_FIQ 0x01 -#define INTC_REVISION(hw_base) REG32((hw_base) + 0x0) -#define INTC_SYSCONFIG(hw_base) REG32((hw_base) + 0x10) -#define INTC_SYSSTATUS(hw_base) REG32((hw_base) + 0x14) -#define INTC_SIR_IRQ(hw_base) REG32((hw_base) + 0x40) -#define INTC_SIR_FIQ(hw_base) REG32((hw_base) + 0x44) -#define INTC_CONTROL(hw_base) REG32((hw_base) + 0x48) -#define INTC_PROTECTION(hw_base) REG32((hw_base) + 0x4c) -#define INTC_IDLE(hw_base) REG32((hw_base) + 0x50) -#define INTC_IRQ_PRIORITY(hw_base) REG32((hw_base) + 0x60) -#define INTC_FIQ_PRIORITY(hw_base) REG32((hw_base) + 0x64) -#define INTC_THRESHOLD(hw_base) REG32((hw_base) + 0x68) -#define INTC_SICR(hw_base) REG32((hw_base) + 0x6c) -#define INTC_SCR(hw_base, n) REG32((hw_base) + 0x70 + ((n) * 0x04)) -#define INTC_ITR(hw_base, n) REG32((hw_base) + 0x80 + ((n) * 0x20)) -#define INTC_MIR(hw_base, n) REG32((hw_base) + 0x84 + ((n) * 0x20)) -#define INTC_MIR_CLEAR(hw_base, n) REG32((hw_base) + 0x88 + ((n) * 0x20)) -#define INTC_MIR_SET(hw_base, n) REG32((hw_base) + 0x8c + ((n) * 0x20)) -#define INTC_ISR_SET(hw_base, n) REG32((hw_base) + 0x90 + ((n) * 0x20)) -#define INTC_ISR_CLEAR(hw_base, n) REG32((hw_base) + 0x94 + ((n) * 0x20)) +#define INTC_REVISION(hw_base) REG32((hw_base) + 0x0) +#define INTC_SYSCONFIG(hw_base) REG32((hw_base) + 0x10) +#define INTC_SYSSTATUS(hw_base) REG32((hw_base) + 0x14) +#define INTC_SIR_IRQ(hw_base) REG32((hw_base) + 0x40) +#define INTC_SIR_FIQ(hw_base) REG32((hw_base) + 0x44) +#define INTC_CONTROL(hw_base) REG32((hw_base) + 0x48) +#define INTC_PROTECTION(hw_base) REG32((hw_base) + 0x4c) +#define INTC_IDLE(hw_base) REG32((hw_base) + 0x50) +#define INTC_IRQ_PRIORITY(hw_base) REG32((hw_base) + 0x60) +#define INTC_FIQ_PRIORITY(hw_base) REG32((hw_base) + 0x64) +#define INTC_THRESHOLD(hw_base) REG32((hw_base) + 0x68) +#define INTC_SICR(hw_base) REG32((hw_base) + 0x6c) +#define INTC_SCR(hw_base, n) REG32((hw_base) + 0x70 + ((n) * 0x04)) +#define INTC_ITR(hw_base, n) REG32((hw_base) + 0x80 + ((n) * 0x20)) +#define INTC_MIR(hw_base, n) REG32((hw_base) + 0x84 + ((n) * 0x20)) +#define INTC_MIR_CLEAR(hw_base, n) REG32((hw_base) + 0x88 + ((n) * 0x20)) +#define INTC_MIR_SET(hw_base, n) REG32((hw_base) + 0x8c + ((n) * 0x20)) +#define INTC_ISR_SET(hw_base, n) REG32((hw_base) + 0x90 + ((n) * 0x20)) +#define INTC_ISR_CLEAR(hw_base, n) REG32((hw_base) + 0x94 + ((n) * 0x20)) #define INTC_PENDING_IRQ(hw_base, n) REG32((hw_base) + 0x98 + ((n) * 0x20)) #define INTC_PENDING_FIQ(hw_base, n) REG32((hw_base) + 0x9c + ((n) * 0x20)) -#define INTC_ILR(hw_base, n) REG32((hw_base) + 0x100 + ((n) * 0x04)) +#define INTC_ILR(hw_base, n) REG32((hw_base) + 0x100 + ((n) * 0x04)) void rt_hw_interrupt_control(int vector, int priority, int route); int rt_hw_interrupt_get_active(int fiq_irq); diff --git a/libcpu/arm/am335x/mmu.c b/libcpu/arm/am335x/mmu.c index babe825298..fbd886d0e6 100644 --- a/libcpu/arm/am335x/mmu.c +++ b/libcpu/arm/am335x/mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,122 +22,122 @@ extern void rt_cpu_tlb_set(register rt_uint32_t i); void mmu_disable_dcache() { - rt_cpu_dcache_disable(); + rt_cpu_dcache_disable(); } void mmu_enable_dcache() { - rt_hw_cpu_dcache_enable(); + rt_hw_cpu_dcache_enable(); } void mmu_disable_icache() { - rt_cpu_icache_disable(); + rt_cpu_icache_disable(); } void mmu_enable_icache() { - rt_hw_cpu_icache_enable(); + rt_hw_cpu_icache_enable(); } void mmu_disable() { - rt_cpu_mmu_disable(); + rt_cpu_mmu_disable(); } void mmu_enable() { - rt_cpu_mmu_enable(); + rt_cpu_mmu_enable(); } void mmu_setttbase(register rt_uint32_t i) { - register rt_uint32_t value; + register rt_uint32_t value; /* Invalidates all TLBs.Domain access is selected as * client by configuring domain access register, * in that case access controlled by permission value * set by page table entry */ - value = 0; - asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value)); + value = 0; + asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value)); - value = 0x55555555; - asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value)); - - rt_cpu_tlb_set(i); + value = 0x55555555; + asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value)); + + rt_cpu_tlb_set(i); } void mmu_set_domain(register rt_uint32_t i) { - asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); + asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); } void mmu_enable_alignfault() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 1); + i |= (1 << 1); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_alignfault() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 1); + i &= ~(1 << 1); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_clean_invalidated_cache_index(int index) { - asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); + asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); } void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~0x1f; + ptr = buffer & ~0x1f; - while (ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr)); - ptr += 32; - } + while (ptr < buffer + size) + { + asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr)); + ptr += 32; + } } void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~0x1f; + ptr = buffer & ~0x1f; - while (ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr)); - ptr += 32; - } + while (ptr < buffer + size) + { + asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr)); + ptr += 32; + } } void mmu_invalidate_tlb() { - asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); } void mmu_invalidate_icache() { - asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); } /* level1 page table */ @@ -150,8 +150,8 @@ void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd, rt_uint32_t paddrS nSec=(vaddrEnd>>20)-(vaddrStart>>20); for(i=0;i<=nSec;i++) { - *pTT = attr |(((paddrStart>>20)+i)<<20); - pTT++; + *pTT = attr |(((paddrStart>>20)+i)<<20); + pTT++; } } @@ -161,21 +161,21 @@ RT_WEAK void mmu_setmtts(void) mmu_setmtt(0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB); /* None cached for 4G memory */ mmu_setmtt(0x80200000, 0x80800000 - 1, 0x80200000, RW_CB); /* 126M cached DDR memory */ mmu_setmtt(0x80000000, 0x80200000 - 1, 0x80000000, RW_NCNB); /* 2M none-cached DDR memory */ - mmu_setmtt(0x402F0000, 0x40300000 - 1, 0x402F0000, RW_CB); /* 63K OnChip memory */ + mmu_setmtt(0x402F0000, 0x40300000 - 1, 0x402F0000, RW_CB); /* 63K OnChip memory */ } void rt_hw_mmu_init(void) { - /* disable I/D cache */ - mmu_disable_dcache(); - mmu_disable_icache(); - mmu_disable(); - mmu_invalidate_tlb(); + /* disable I/D cache */ + mmu_disable_dcache(); + mmu_disable_icache(); + mmu_disable(); + mmu_invalidate_tlb(); mmu_setmtts(); - /* set MMU table address */ - mmu_setttbase((rt_uint32_t)_page_table); + /* set MMU table address */ + mmu_setttbase((rt_uint32_t)_page_table); /* enables MMU */ mmu_enable(); diff --git a/libcpu/arm/am335x/mmu.h b/libcpu/arm/am335x/mmu.h index 73635d3a0e..706d669844 100644 --- a/libcpu/arm/am335x/mmu.h +++ b/libcpu/arm/am335x/mmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,27 +13,27 @@ #include -#define DESC_SEC (0x2) -#define CB (3<<2) //cache_on, write_back -#define CNB (2<<2) //cache_on, write_through -#define NCB (1<<2) //cache_off,WR_BUF on -#define NCNB (0<<2) //cache_off,WR_BUF off -#define AP_RW (3<<10) //supervisor=RW, user=RW -#define AP_RO (2<<10) //supervisor=RW, user=RO - -#define DOMAIN_FAULT (0x0) -#define DOMAIN_CHK (0x1) -#define DOMAIN_NOTCHK (0x3) -#define DOMAIN0 (0x0<<5) -#define DOMAIN1 (0x1<<5) - -#define DOMAIN0_ATTR (DOMAIN_CHK<<0) -#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) - -#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */ -#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */ -#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ -#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ +#define DESC_SEC (0x2) +#define CB (3<<2) //cache_on, write_back +#define CNB (2<<2) //cache_on, write_through +#define NCB (1<<2) //cache_off,WR_BUF on +#define NCNB (0<<2) //cache_off,WR_BUF off +#define AP_RW (3<<10) //supervisor=RW, user=RW +#define AP_RO (2<<10) //supervisor=RW, user=RO + +#define DOMAIN_FAULT (0x0) +#define DOMAIN_CHK (0x1) +#define DOMAIN_NOTCHK (0x3) +#define DOMAIN0 (0x0<<5) +#define DOMAIN1 (0x1<<5) + +#define DOMAIN0_ATTR (DOMAIN_CHK<<0) +#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) + +#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */ +#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */ +#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ +#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ void rt_hw_mmu_init(void); diff --git a/libcpu/arm/am335x/stack.c b/libcpu/arm/am335x/stack.c index 1dad930818..db3cb37e73 100644 --- a/libcpu/arm/am335x/stack.c +++ b/libcpu/arm/am335x/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/am335x/trap.c b/libcpu/arm/am335x/trap.c index b77543da64..7c73ce93d3 100644 --- a/libcpu/arm/am335x/trap.c +++ b/libcpu/arm/am335x/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -36,13 +36,13 @@ extern long list_thread(void); void rt_hw_show_register (struct rt_hw_register *regs) { - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); } /** @@ -62,15 +62,15 @@ void rt_hw_trap_udef(struct rt_hw_register *regs) return; #endif - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("undefined instruction\n"); - rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name); + rt_kprintf("undefined instruction\n"); + rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -84,10 +84,10 @@ void rt_hw_trap_udef(struct rt_hw_register *regs) */ void rt_hw_trap_swi(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("software interrupt\n"); - rt_hw_cpu_shutdown(); + rt_kprintf("software interrupt\n"); + rt_hw_cpu_shutdown(); } /** @@ -100,15 +100,15 @@ void rt_hw_trap_swi(struct rt_hw_register *regs) */ void rt_hw_trap_pabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("prefetch abort\n"); - rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name); + rt_kprintf("prefetch abort\n"); + rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -124,29 +124,29 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs) #ifdef RT_USING_GDB if (gdb_mem_fault_handler) { - regs->pc = (unsigned long)gdb_mem_fault_handler; + regs->pc = (unsigned long)gdb_mem_fault_handler; return; } #endif - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("data abort\n"); - rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name); + rt_kprintf("data abort\n"); + rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } void rt_hw_trap_irq() { void *param; - unsigned long ir; + unsigned long ir; rt_isr_handler_t isr_func; extern struct rt_irq_desc isr_table[]; - ir = rt_hw_interrupt_get_active(INT_IRQ); + ir = rt_hw_interrupt_get_active(INT_IRQ); if (ir == 127) { /* new IRQ generation */ @@ -169,18 +169,18 @@ void rt_hw_trap_irq() if (isr_func != RT_NULL) isr_func(ir, param); - /* new IRQ generation */ + /* new IRQ generation */ rt_hw_interrupt_ack(INT_IRQ); } void rt_hw_trap_fiq() { void *param; - unsigned long ir; + unsigned long ir; rt_isr_handler_t isr_func; extern struct rt_irq_desc isr_table[]; - ir = rt_hw_interrupt_get_active(INT_FIQ); + ir = rt_hw_interrupt_get_active(INT_FIQ); /* get interrupt service routine */ isr_func = isr_table[ir].handler; @@ -189,7 +189,7 @@ void rt_hw_trap_fiq() /* turn to interrupt service routine */ isr_func(ir, param); - /* new FIQ generation */ + /* new FIQ generation */ rt_hw_interrupt_ack(INT_FIQ); } diff --git a/libcpu/arm/arm926/cpuport.c b/libcpu/arm/arm926/cpuport.c index 035e97d543..603c80f2dd 100644 --- a/libcpu/arm/arm926/cpuport.c +++ b/libcpu/arm/arm926/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/arm926/machine.c b/libcpu/arm/arm926/machine.c index aa26d10ec6..19baa4d9fe 100644 --- a/libcpu/arm/arm926/machine.c +++ b/libcpu/arm/arm926/machine.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/arm926/mmu.c b/libcpu/arm/arm926/mmu.c index 19d70b9b0b..50ada17f22 100644 --- a/libcpu/arm/arm926/mmu.c +++ b/libcpu/arm/arm926/mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/arm926/mmu.h b/libcpu/arm/arm926/mmu.h index 36fdbeacd8..ecd39d4edf 100644 --- a/libcpu/arm/arm926/mmu.h +++ b/libcpu/arm/arm926/mmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/arm926/stack.c b/libcpu/arm/arm926/stack.c index f90bfa8c22..caf16c41bc 100644 --- a/libcpu/arm/arm926/stack.c +++ b/libcpu/arm/arm926/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/arm926/trap.c b/libcpu/arm/arm926/trap.c index 9e7ba48037..c364b2addd 100644 --- a/libcpu/arm/arm926/trap.c +++ b/libcpu/arm/arm926/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/armv6/armv6.h b/libcpu/arm/armv6/armv6.h index 659ce90721..522c35845f 100644 --- a/libcpu/arm/armv6/armv6.h +++ b/libcpu/arm/armv6/armv6.h @@ -1,12 +1,12 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes */ - + #ifndef __ARMV6_H__ #define __ARMV6_H__ @@ -26,7 +26,7 @@ #ifndef __ASSEMBLY__ struct rt_hw_register { - rt_uint32_t cpsr; + rt_uint32_t cpsr; rt_uint32_t r0; rt_uint32_t r1; rt_uint32_t r2; @@ -46,24 +46,24 @@ struct rt_hw_register }; #if(0) struct rt_hw_register{ - rt_uint32_t r0; - rt_uint32_t r1; - rt_uint32_t r2; - rt_uint32_t r3; - rt_uint32_t r4; - rt_uint32_t r5; - rt_uint32_t r6; - rt_uint32_t r7; - rt_uint32_t r8; - rt_uint32_t r9; - rt_uint32_t r10; - rt_uint32_t fp; - rt_uint32_t ip; - rt_uint32_t sp; - rt_uint32_t lr; - rt_uint32_t pc; - rt_uint32_t cpsr; - rt_uint32_t ORIG_r0; + rt_uint32_t r0; + rt_uint32_t r1; + rt_uint32_t r2; + rt_uint32_t r3; + rt_uint32_t r4; + rt_uint32_t r5; + rt_uint32_t r6; + rt_uint32_t r7; + rt_uint32_t r8; + rt_uint32_t r9; + rt_uint32_t r10; + rt_uint32_t fp; + rt_uint32_t ip; + rt_uint32_t sp; + rt_uint32_t lr; + rt_uint32_t pc; + rt_uint32_t cpsr; + rt_uint32_t ORIG_r0; }; #endif #endif diff --git a/libcpu/arm/armv6/cpuport.c b/libcpu/arm/armv6/cpuport.c index c8e9201722..eda87225d5 100644 --- a/libcpu/arm/armv6/cpuport.c +++ b/libcpu/arm/armv6/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -11,8 +11,8 @@ #include #include -#define ICACHE_MASK (rt_uint32_t)(1 << 12) -#define DCACHE_MASK (rt_uint32_t)(1 << 2) +#define ICACHE_MASK (rt_uint32_t)(1 << 12) +#define DCACHE_MASK (rt_uint32_t)(1 << 2) extern void machine_reset(void); extern void machine_shutdown(void); @@ -20,32 +20,32 @@ extern void machine_shutdown(void); #ifdef __GNUC__ rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - return i; + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "orr r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "orr r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } rt_inline void cache_disable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "bic r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "bic r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } @@ -54,38 +54,38 @@ rt_inline void cache_disable(rt_uint32_t bit) #ifdef __CC_ARM rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - __asm - { - mrc p15, 0, i, c1, c0, 0 - } + __asm + { + mrc p15, 0, i, c1, c0, 0 + } - return i; + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } rt_inline void cache_disable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } #endif @@ -95,7 +95,7 @@ rt_inline void cache_disable(rt_uint32_t bit) */ void rt_hw_cpu_icache_enable() { - cache_enable(ICACHE_MASK); + cache_enable(ICACHE_MASK); } /** @@ -104,7 +104,7 @@ void rt_hw_cpu_icache_enable() */ void rt_hw_cpu_icache_disable() { - cache_disable(ICACHE_MASK); + cache_disable(ICACHE_MASK); } /** @@ -113,7 +113,7 @@ void rt_hw_cpu_icache_disable() */ rt_base_t rt_hw_cpu_icache_status() { - return (cp15_rd() & ICACHE_MASK); + return (cp15_rd() & ICACHE_MASK); } /** @@ -122,7 +122,7 @@ rt_base_t rt_hw_cpu_icache_status() */ void rt_hw_cpu_dcache_enable() { - cache_enable(DCACHE_MASK); + cache_enable(DCACHE_MASK); } /** @@ -131,7 +131,7 @@ void rt_hw_cpu_dcache_enable() */ void rt_hw_cpu_dcache_disable() { - cache_disable(DCACHE_MASK); + cache_disable(DCACHE_MASK); } /** @@ -140,7 +140,7 @@ void rt_hw_cpu_dcache_disable() */ rt_base_t rt_hw_cpu_dcache_status() { - return (cp15_rd() & DCACHE_MASK); + return (cp15_rd() & DCACHE_MASK); } /** @@ -149,13 +149,13 @@ rt_base_t rt_hw_cpu_dcache_status() */ void rt_hw_cpu_reset() { - - rt_kprintf("Restarting system...\n"); - machine_reset(); - while(1); /* loop forever and wait for reset to happen */ + rt_kprintf("Restarting system...\n"); + machine_reset(); - /* NEVER REACHED */ + while(1); /* loop forever and wait for reset to happen */ + + /* NEVER REACHED */ } /** @@ -164,67 +164,67 @@ void rt_hw_cpu_reset() */ void rt_hw_cpu_shutdown() { - rt_uint32_t level; - rt_kprintf("shutdown...\n"); + rt_uint32_t level; + rt_kprintf("shutdown...\n"); - level = rt_hw_interrupt_disable(); - machine_shutdown(); - while (level) - { - RT_ASSERT(0); - } + level = rt_hw_interrupt_disable(); + machine_shutdown(); + while (level) + { + RT_ASSERT(0); + } } #ifdef RT_USING_CPU_FFS /** - * This function finds the first bit set (beginning with the least significant bit) + * This function finds the first bit set (beginning with the least significant bit) * in value and return the index of that bit. * - * Bits are numbered starting at 1 (the least significant bit). A return value of + * Bits are numbered starting at 1 (the least significant bit). A return value of * zero from any of these functions means that the argument was zero. - * - * @return return the index of the first bit set. If value is 0, then this function + * + * @return return the index of the first bit set. If value is 0, then this function * shall return 0. */ #if defined(__CC_ARM) int __rt_ffs(int value) { - register rt_uint32_t x; + register rt_uint32_t x; + + if (value == 0) + return value; - if (value == 0) - return value; - - __asm - { - rsb x, value, #0 - and x, x, value - clz x, x - rsb x, x, #32 - } + __asm + { + rsb x, value, #0 + and x, x, value + clz x, x + rsb x, x, #32 + } - return x; + return x; } #elif defined(__IAR_SYSTEMS_ICC__) int __rt_ffs(int value) { - if (value == 0) - return value; + if (value == 0) + return value; - __ASM("RSB r4, r0, #0"); - __ASM("AND r4, r4, r0"); - __ASM("CLZ r4, r4"); - __ASM("RSB r0, r4, #32"); + __ASM("RSB r4, r0, #0"); + __ASM("AND r4, r4, r0"); + __ASM("CLZ r4, r4"); + __ASM("RSB r0, r4, #32"); } #elif defined(__GNUC__) int __rt_ffs(int value) { - if (value == 0) - return value; + if (value == 0) + return value; - value &= (-value); - asm ("clz %0, %1": "=r"(value) :"r"(value)); + value &= (-value); + asm ("clz %0, %1": "=r"(value) :"r"(value)); - return (32 - value); + return (32 - value); } #endif diff --git a/libcpu/arm/armv6/mmu.c b/libcpu/arm/armv6/mmu.c index ae3cf73559..deb2f8365f 100644 --- a/libcpu/arm/armv6/mmu.c +++ b/libcpu/arm/armv6/mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,411 +12,411 @@ #ifdef __CC_ARM void mmu_setttbase(rt_uint32_t i) { - register rt_uint32_t value; + register rt_uint32_t value; - /* Invalidates all TLBs.Domain access is selected as - * client by configuring domain access register, - * in that case access controlled by permission value - * set by page table entry - */ - value = 0; - __asm volatile - { - mcr p15, 0, value, c8, c7, 0 - } + /* Invalidates all TLBs.Domain access is selected as + * client by configuring domain access register, + * in that case access controlled by permission value + * set by page table entry + */ + value = 0; + __asm volatile + { + mcr p15, 0, value, c8, c7, 0 + } - value = 0x55555555; - __asm volatile - { - mcr p15, 0, value, c3, c0, 0 - mcr p15, 0, i, c2, c0, 0 - } + value = 0x55555555; + __asm volatile + { + mcr p15, 0, value, c3, c0, 0 + mcr p15, 0, i, c2, c0, 0 + } } void mmu_set_domain(rt_uint32_t i) { - __asm volatile - { - mcr p15,0, i, c3, c0, 0 - } + __asm volatile + { + mcr p15,0, i, c3, c0, 0 + } } void mmu_enable() { - register rt_uint32_t value; + register rt_uint32_t value; - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x01 - mcr p15, 0, value, c1, c0, 0 - } + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x01 + mcr p15, 0, value, c1, c0, 0 + } } void mmu_disable() { - register rt_uint32_t value; + register rt_uint32_t value; - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x01 - mcr p15, 0, value, c1, c0, 0 - } + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x01 + mcr p15, 0, value, c1, c0, 0 + } } void mmu_enable_icache() { - register rt_uint32_t value; + register rt_uint32_t value; - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x1000 - mcr p15, 0, value, c1, c0, 0 - } + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x1000 + mcr p15, 0, value, c1, c0, 0 + } } void mmu_enable_dcache() { - register rt_uint32_t value; + register rt_uint32_t value; - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x04 - mcr p15, 0, value, c1, c0, 0 - } + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x04 + mcr p15, 0, value, c1, c0, 0 + } } void mmu_disable_icache() { - register rt_uint32_t value; + register rt_uint32_t value; - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x1000 - mcr p15, 0, value, c1, c0, 0 - } + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x1000 + mcr p15, 0, value, c1, c0, 0 + } } void mmu_disable_dcache() { - register rt_uint32_t value; + register rt_uint32_t value; - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x04 - mcr p15, 0, value, c1, c0, 0 - } + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x04 + mcr p15, 0, value, c1, c0, 0 + } } void mmu_enable_alignfault() { - register rt_uint32_t value; + register rt_uint32_t value; - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x02 - mcr p15, 0, value, c1, c0, 0 - } + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x02 + mcr p15, 0, value, c1, c0, 0 + } } void mmu_disable_alignfault() { - register rt_uint32_t value; + register rt_uint32_t value; - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x02 - mcr p15, 0, value, c1, c0, 0 - } + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x02 + mcr p15, 0, value, c1, c0, 0 + } } void mmu_clean_invalidated_cache_index(int index) { - __asm volatile - { - mcr p15, 0, index, c7, c14, 2 - } + __asm volatile + { + mcr p15, 0, index, c7, c14, 2 + } } void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while(ptr < buffer + size) - { - __asm volatile - { - MCR p15, 0, ptr, c7, c14, 1 - } - ptr += CACHE_LINE_SIZE; - } + while(ptr < buffer + size) + { + __asm volatile + { + MCR p15, 0, ptr, c7, c14, 1 + } + ptr += CACHE_LINE_SIZE; + } } void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - __asm volatile - { - MCR p15, 0, ptr, c7, c10, 1 - } - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + __asm volatile + { + MCR p15, 0, ptr, c7, c10, 1 + } + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - __asm volatile - { - MCR p15, 0, ptr, c7, c6, 1 - } - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + __asm volatile + { + MCR p15, 0, ptr, c7, c6, 1 + } + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_tlb() { - register rt_uint32_t value; + register rt_uint32_t value; - value = 0; - __asm volatile - { - mcr p15, 0, value, c8, c7, 0 - } + value = 0; + __asm volatile + { + mcr p15, 0, value, c8, c7, 0 + } } void mmu_invalidate_icache() { - register rt_uint32_t value; + register rt_uint32_t value; - value = 0; + value = 0; - __asm volatile - { - mcr p15, 0, value, c7, c5, 0 - } + __asm volatile + { + mcr p15, 0, value, c7, c5, 0 + } } void mmu_invalidate_dcache_all() { - register rt_uint32_t value; + register rt_uint32_t value; - value = 0; + value = 0; - __asm volatile - { - mcr p15, 0, value, c7, c6, 0 - } + __asm volatile + { + mcr p15, 0, value, c7, c6, 0 + } } #elif defined(__GNUC__) void mmu_setttbase(register rt_uint32_t i) { - register rt_uint32_t value; + register rt_uint32_t value; - /* Invalidates all TLBs.Domain access is selected as - * client by configuring domain access register, - * in that case access controlled by permission value - * set by page table entry - */ - value = 0; - asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value)); + /* Invalidates all TLBs.Domain access is selected as + * client by configuring domain access register, + * in that case access controlled by permission value + * set by page table entry + */ + value = 0; + asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value)); - value = 0x55555555; - asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value)); - asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i)); + value = 0x55555555; + asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value)); + asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i)); } void mmu_set_domain(register rt_uint32_t i) { - asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); + asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); } void mmu_enable() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= 0x1; - /* Enables the extended page tables to be configured for - the hardware page translation mechanism, Subpage AP bits disabled */ - i |= (1 << 23); /* support for ARMv6 MMU features */ - i |= (1 << 13); /* High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C */ + i |= 0x1; + /* Enables the extended page tables to be configured for + the hardware page translation mechanism, Subpage AP bits disabled */ + i |= (1 << 23); /* support for ARMv6 MMU features */ + i |= (1 << 13); /* High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C */ - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~0x1; + i &= ~0x1; - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_icache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 12); + i |= (1 << 12); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_dcache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 2); + i |= (1 << 2); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_icache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 12); + i &= ~(1 << 12); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_dcache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 2); + i &= ~(1 << 2); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_alignfault() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 1); + i |= (1 << 1); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_alignfault() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 1); + i &= ~(1 << 1); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_clean_invalidated_cache_index(int index) { - asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); + asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); } void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while(ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr)); - ptr += CACHE_LINE_SIZE; - } + while(ptr < buffer + size) + { + asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr)); + ptr += CACHE_LINE_SIZE; + } } void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr)); - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr)); + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr)); - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr)); + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_tlb() { - asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); } void mmu_invalidate_icache() { - asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); } void mmu_invalidate_dcache_all() { - asm volatile ("mcr p15, 0, %0, c7, c6, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c7, c6, 0": :"r" (0)); } #endif @@ -426,123 +426,123 @@ static volatile unsigned int _pgd_table[4*1024] ALIGN(16*1024); * level2 page table * RT_MMU_PTE_SIZE must be 1024*n */ -#define RT_MMU_PTE_SIZE 4096 +#define RT_MMU_PTE_SIZE 4096 static volatile unsigned int _pte_table[RT_MMU_PTE_SIZE] ALIGN(1*1024); void mmu_create_pgd(struct mem_desc *mdesc) { - volatile rt_uint32_t *pTT; - volatile int i, nSec; - pTT = (rt_uint32_t *)_pgd_table + (mdesc->vaddr_start >> 20); - nSec = (mdesc->vaddr_end >> 20) - (mdesc->vaddr_start >> 20); - for(i = 0; i <= nSec; i++) - { - *pTT = mdesc->sect_attr | (((mdesc->paddr_start >> 20) + i) << 20); - pTT++; - } + volatile rt_uint32_t *pTT; + volatile int i, nSec; + pTT = (rt_uint32_t *)_pgd_table + (mdesc->vaddr_start >> 20); + nSec = (mdesc->vaddr_end >> 20) - (mdesc->vaddr_start >> 20); + for(i = 0; i <= nSec; i++) + { + *pTT = mdesc->sect_attr | (((mdesc->paddr_start >> 20) + i) << 20); + pTT++; + } } void mmu_create_pte(struct mem_desc *mdesc) { - volatile rt_uint32_t *pTT; - volatile rt_uint32_t *p_pteentry; - int i; - rt_uint32_t vaddr; - rt_uint32_t total_page = 0; - rt_uint32_t pte_offset = 0; - rt_uint32_t sect_attr = 0; - - total_page = (mdesc->vaddr_end >> 12) - (mdesc->vaddr_start >> 12) + 1; - pte_offset = mdesc->sect_attr & 0xfffffc00; - sect_attr = mdesc->sect_attr & 0x3ff; - vaddr = mdesc->vaddr_start; - - for(i = 0; i < total_page; i++) - { - pTT = (rt_uint32_t *)_pgd_table + (vaddr >> 20); - if (*pTT == 0) /* Level 1 page table item not used, now update pgd item */ - { - *pTT = pte_offset | sect_attr; - p_pteentry = (rt_uint32_t *)pte_offset + - ((vaddr & 0x000ff000) >> 12); - pte_offset += 1024; - } - else /* using old Level 1 page table item */ - { - p_pteentry = (rt_uint32_t *)(*pTT & 0xfffffc00) + - ((vaddr & 0x000ff000) >> 12); - } - - - *p_pteentry = mdesc->page_attr | (((mdesc->paddr_start >> 12) + i) << 12); - vaddr += 0x1000; - } + volatile rt_uint32_t *pTT; + volatile rt_uint32_t *p_pteentry; + int i; + rt_uint32_t vaddr; + rt_uint32_t total_page = 0; + rt_uint32_t pte_offset = 0; + rt_uint32_t sect_attr = 0; + + total_page = (mdesc->vaddr_end >> 12) - (mdesc->vaddr_start >> 12) + 1; + pte_offset = mdesc->sect_attr & 0xfffffc00; + sect_attr = mdesc->sect_attr & 0x3ff; + vaddr = mdesc->vaddr_start; + + for(i = 0; i < total_page; i++) + { + pTT = (rt_uint32_t *)_pgd_table + (vaddr >> 20); + if (*pTT == 0) /* Level 1 page table item not used, now update pgd item */ + { + *pTT = pte_offset | sect_attr; + p_pteentry = (rt_uint32_t *)pte_offset + + ((vaddr & 0x000ff000) >> 12); + pte_offset += 1024; + } + else /* using old Level 1 page table item */ + { + p_pteentry = (rt_uint32_t *)(*pTT & 0xfffffc00) + + ((vaddr & 0x000ff000) >> 12); + } + + + *p_pteentry = mdesc->page_attr | (((mdesc->paddr_start >> 12) + i) << 12); + vaddr += 0x1000; + } } static void build_pte_mem_desc(struct mem_desc *mdesc, rt_uint32_t size) { - rt_uint32_t pte_offset = 0; - rt_uint32_t nsec = 0; - /* set page table */ - for (; size > 0; size--) - { - if (mdesc->mapped_mode == PAGE_MAPPED) - { - nsec = (RT_ALIGN(mdesc->vaddr_end, 0x100000) - RT_ALIGN_DOWN(mdesc->vaddr_start, 0x100000)) >> 20; - mdesc->sect_attr |= (((rt_uint32_t)_pte_table)& 0xfffffc00) + pte_offset; - pte_offset += nsec << 10; - } - if (pte_offset >= RT_MMU_PTE_SIZE) - { - rt_kprintf("PTE table size too little\n"); - RT_ASSERT(0); - } + rt_uint32_t pte_offset = 0; + rt_uint32_t nsec = 0; + /* set page table */ + for (; size > 0; size--) + { + if (mdesc->mapped_mode == PAGE_MAPPED) + { + nsec = (RT_ALIGN(mdesc->vaddr_end, 0x100000) - RT_ALIGN_DOWN(mdesc->vaddr_start, 0x100000)) >> 20; + mdesc->sect_attr |= (((rt_uint32_t)_pte_table)& 0xfffffc00) + pte_offset; + pte_offset += nsec << 10; + } + if (pte_offset >= RT_MMU_PTE_SIZE) + { + rt_kprintf("PTE table size too little\n"); + RT_ASSERT(0); + } - mdesc++; - } + mdesc++; + } } void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size) { - /* disable I/D cache */ - mmu_disable_dcache(); - mmu_disable_icache(); - mmu_disable(); - mmu_invalidate_tlb(); - - /* clear pgd and pte table */ - rt_memset((void *)_pgd_table, 0, 16*1024); - rt_memset((void *)_pte_table, 0, RT_MMU_PTE_SIZE); - build_pte_mem_desc(mdesc, size); - /* set page table */ - for (; size > 0; size--) - { - if (mdesc->mapped_mode == SECT_MAPPED) - { - mmu_create_pgd(mdesc); - } - else - { - mmu_create_pte(mdesc); - } - - mdesc++; - } - - /* set MMU table address */ - mmu_setttbase((rt_uint32_t)_pgd_table); - - /* enables MMU */ - mmu_enable(); - - /* enable Instruction Cache */ - mmu_enable_icache(); - - /* enable Data Cache */ - mmu_enable_dcache(); - - mmu_invalidate_icache(); - mmu_invalidate_dcache_all(); + /* disable I/D cache */ + mmu_disable_dcache(); + mmu_disable_icache(); + mmu_disable(); + mmu_invalidate_tlb(); + + /* clear pgd and pte table */ + rt_memset((void *)_pgd_table, 0, 16*1024); + rt_memset((void *)_pte_table, 0, RT_MMU_PTE_SIZE); + build_pte_mem_desc(mdesc, size); + /* set page table */ + for (; size > 0; size--) + { + if (mdesc->mapped_mode == SECT_MAPPED) + { + mmu_create_pgd(mdesc); + } + else + { + mmu_create_pte(mdesc); + } + + mdesc++; + } + + /* set MMU table address */ + mmu_setttbase((rt_uint32_t)_pgd_table); + + /* enables MMU */ + mmu_enable(); + + /* enable Instruction Cache */ + mmu_enable_icache(); + + /* enable Data Cache */ + mmu_enable_dcache(); + + mmu_invalidate_icache(); + mmu_invalidate_dcache_all(); } diff --git a/libcpu/arm/armv6/mmu.h b/libcpu/arm/armv6/mmu.h index 4df61ac21d..18355378bd 100644 --- a/libcpu/arm/armv6/mmu.h +++ b/libcpu/arm/armv6/mmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,7 +12,7 @@ #include -#define CACHE_LINE_SIZE 32 +#define CACHE_LINE_SIZE 32 /* * Hardware page table definitions. @@ -30,7 +30,7 @@ /* * - section */ -#define PGD_SECT_BUFFERABLE (1 << 2) +#define PGD_SECT_BUFFERABLE (1 << 2) #define PGD_SECT_CACHEABLE (1 << 3) #define PGD_SECT_XN (1 << 4) /* ARMv6 */ #define PGD_SECT_AP0 (1 << 10) @@ -155,35 +155,35 @@ #define PAGE_RONX_FAULT (PAGE_AP_RO|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read Only without cache and write buffer */ -#define DESC_SEC (0x2|(1<<4)) -#define CB (3<<2) //cache_on, write_back -#define CNB (2<<2) //cache_on, write_through -#define NCB (1<<2) //cache_off,WR_BUF on -#define NCNB (0<<2) //cache_off,WR_BUF off -#define AP_RW (3<<10) //supervisor=RW, user=RW -#define AP_RO (2<<10) //supervisor=RW, user=RO +#define DESC_SEC (0x2|(1<<4)) +#define CB (3<<2) //cache_on, write_back +#define CNB (2<<2) //cache_on, write_through +#define NCB (1<<2) //cache_off,WR_BUF on +#define NCNB (0<<2) //cache_off,WR_BUF off +#define AP_RW (3<<10) //supervisor=RW, user=RW +#define AP_RO (2<<10) //supervisor=RW, user=RO -#define DOMAIN_FAULT (0x0) -#define DOMAIN_CHK (0x1) -#define DOMAIN_NOTCHK (0x3) -#define DOMAIN0 (0x0<<5) -#define DOMAIN1 (0x1<<5) +#define DOMAIN_FAULT (0x0) +#define DOMAIN_CHK (0x1) +#define DOMAIN_NOTCHK (0x3) +#define DOMAIN0 (0x0<<5) +#define DOMAIN1 (0x1<<5) -#define DOMAIN0_ATTR (DOMAIN_CHK<<0) -#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) +#define DOMAIN0_ATTR (DOMAIN_CHK<<0) +#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) -#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */ -#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */ -#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ -#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ +#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */ +#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */ +#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ +#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ struct mem_desc { - rt_uint32_t vaddr_start; - rt_uint32_t vaddr_end; - rt_uint32_t paddr_start; - rt_uint32_t sect_attr; /* when page mapped */ - rt_uint32_t page_attr; /* only sector mapped valid */ - rt_uint32_t mapped_mode; + rt_uint32_t vaddr_start; + rt_uint32_t vaddr_end; + rt_uint32_t paddr_start; + rt_uint32_t sect_attr; /* when page mapped */ + rt_uint32_t page_attr; /* only sector mapped valid */ + rt_uint32_t mapped_mode; #define SECT_MAPPED 0 #define PAGE_MAPPED 1 }; diff --git a/libcpu/arm/armv6/stack.c b/libcpu/arm/armv6/stack.c index 52de999fc2..33a8d96d48 100644 --- a/libcpu/arm/armv6/stack.c +++ b/libcpu/arm/armv6/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/armv6/vfp.c b/libcpu/arm/armv6/vfp.c index 9aa8d34fcc..fc07f5a309 100644 --- a/libcpu/arm/armv6/vfp.c +++ b/libcpu/arm/armv6/vfp.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/armv6/vfp.h b/libcpu/arm/armv6/vfp.h index c347dbe0a6..fd084f3aef 100644 --- a/libcpu/arm/armv6/vfp.h +++ b/libcpu/arm/armv6/vfp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -87,7 +87,7 @@ }) #define vmsr(vfp, var) \ - asm("vmsr "#vfp", %0" \ + asm("vmsr "#vfp", %0" \ : : "r" (var) : "cc") diff --git a/libcpu/arm/common/backtrace.c b/libcpu/arm/common/backtrace.c index 4fc87b20d1..388a409d88 100644 --- a/libcpu/arm/common/backtrace.c +++ b/libcpu/arm/common/backtrace.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/common/div0.c b/libcpu/arm/common/div0.c index 0cb3e09b54..113778b43f 100644 --- a/libcpu/arm/common/div0.c +++ b/libcpu/arm/common/div0.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -8,5 +8,5 @@ */ void __div0 (void) { - while (1) ; + while (1) ; } diff --git a/libcpu/arm/common/showmem.c b/libcpu/arm/common/showmem.c index b770e4ce17..1a94ff1d9f 100644 --- a/libcpu/arm/common/showmem.c +++ b/libcpu/arm/common/showmem.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,27 +12,27 @@ void rt_hw_show_memory(rt_uint32_t addr, rt_uint32_t size) { - int i = 0, j =0; + int i = 0, j =0; - RT_ASSERT(addr); + RT_ASSERT(addr); - addr = addr & ~0xF; - size = 4*((size + 3)/4); + addr = addr & ~0xF; + size = 4*((size + 3)/4); - while(i < size) - { - rt_kprintf("0x%08x: ", addr ); + while(i < size) + { + rt_kprintf("0x%08x: ", addr ); - for(j=0; j<4; j++) - { - rt_kprintf("0x%08x ", *(rt_uint32_t *)addr); + for(j=0; j<4; j++) + { + rt_kprintf("0x%08x ", *(rt_uint32_t *)addr); - addr += 4; - i++; - } + addr += 4; + i++; + } - rt_kprintf("\n"); - } + rt_kprintf("\n"); + } - return; + return; } diff --git a/libcpu/arm/cortex-a/armv7.h b/libcpu/arm/cortex-a/armv7.h index d22f72fa68..f284bb5255 100644 --- a/libcpu/arm/cortex-a/armv7.h +++ b/libcpu/arm/cortex-a/armv7.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,43 +12,43 @@ /* the exception stack without VFP registers */ struct rt_hw_exp_stack { - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; }; struct rt_hw_stack { - unsigned long cpsr; - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long lr; - unsigned long pc; + unsigned long cpsr; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long lr; + unsigned long pc; }; #define USERMODE 0x10 diff --git a/libcpu/arm/cortex-a/cache.c b/libcpu/arm/cortex-a/cache.c index 30af86baa1..0a7e702dbb 100644 --- a/libcpu/arm/cortex-a/cache.c +++ b/libcpu/arm/cortex-a/cache.c @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2019-03-29 quanzhao the first version + * 2019-03-29 quanzhao the first version */ #include #include diff --git a/libcpu/arm/cortex-a/cp15.h b/libcpu/arm/cortex-a/cp15.h index 97c5b93ad2..687199e573 100644 --- a/libcpu/arm/cortex-a/cp15.h +++ b/libcpu/arm/cortex-a/cp15.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/cpu.c b/libcpu/arm/cortex-a/cpu.c index 7c6bf58a4b..f834291040 100644 --- a/libcpu/arm/cortex-a/cpu.c +++ b/libcpu/arm/cortex-a/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/gic.c b/libcpu/arm/cortex-a/gic.c index 2e94b88277..faad418b2d 100644 --- a/libcpu/arm/cortex-a/gic.c +++ b/libcpu/arm/cortex-a/gic.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/gic.h b/libcpu/arm/cortex-a/gic.h index a16d0467fb..e48f9f854d 100644 --- a/libcpu/arm/cortex-a/gic.h +++ b/libcpu/arm/cortex-a/gic.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/interrupt.c b/libcpu/arm/cortex-a/interrupt.c index b7a70719a9..0d440d1d0e 100644 --- a/libcpu/arm/cortex-a/interrupt.c +++ b/libcpu/arm/cortex-a/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/interrupt.h b/libcpu/arm/cortex-a/interrupt.h index 442187edee..a8a9afb95c 100644 --- a/libcpu/arm/cortex-a/interrupt.h +++ b/libcpu/arm/cortex-a/interrupt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/mmu.c b/libcpu/arm/cortex-a/mmu.c index 1260f41fe5..243fe19a0a 100644 --- a/libcpu/arm/cortex-a/mmu.c +++ b/libcpu/arm/cortex-a/mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/mmu.h b/libcpu/arm/cortex-a/mmu.h index fbce6df935..5cc60a774d 100644 --- a/libcpu/arm/cortex-a/mmu.h +++ b/libcpu/arm/cortex-a/mmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/pmu.c b/libcpu/arm/cortex-a/pmu.c index 8ffc1dede6..2b9165cc8b 100644 --- a/libcpu/arm/cortex-a/pmu.c +++ b/libcpu/arm/cortex-a/pmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/pmu.h b/libcpu/arm/cortex-a/pmu.h index fb8390133d..64a74b5d39 100644 --- a/libcpu/arm/cortex-a/pmu.h +++ b/libcpu/arm/cortex-a/pmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/stack.c b/libcpu/arm/cortex-a/stack.c index 07d795ab5b..e68b324867 100644 --- a/libcpu/arm/cortex-a/stack.c +++ b/libcpu/arm/cortex-a/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/trap.c b/libcpu/arm/cortex-a/trap.c index dc232a46ee..a213e776c7 100644 --- a/libcpu/arm/cortex-a/trap.c +++ b/libcpu/arm/cortex-a/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-m0/cpuport.c b/libcpu/arm/cortex-m0/cpuport.c index 19aec42230..49e15bf339 100644 --- a/libcpu/arm/cortex-m0/cpuport.c +++ b/libcpu/arm/cortex-m0/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-m3/cpuport.c b/libcpu/arm/cortex-m3/cpuport.c index d58782e2c5..ab0a2c3529 100644 --- a/libcpu/arm/cortex-m3/cpuport.c +++ b/libcpu/arm/cortex-m3/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-m4/cpuport.c b/libcpu/arm/cortex-m4/cpuport.c index dc8a9aab59..3c6a9aed74 100644 --- a/libcpu/arm/cortex-m4/cpuport.c +++ b/libcpu/arm/cortex-m4/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -454,7 +454,7 @@ RT_WEAK void rt_hw_cpu_reset(void) * @return return the index of the first bit set. If value is 0, then this function * shall return 0. */ -#if defined(__CC_ARM) +#if defined(__CC_ARM) __asm int __rt_ffs(int value) { CMP r0, #0x00 diff --git a/libcpu/arm/cortex-m7/cpuport.c b/libcpu/arm/cortex-m7/cpuport.c index e701a52307..3c6a9aed74 100644 --- a/libcpu/arm/cortex-m7/cpuport.c +++ b/libcpu/arm/cortex-m7/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-r4/armv7.h b/libcpu/arm/cortex-r4/armv7.h index 3adcb92c5d..d29b41a213 100644 --- a/libcpu/arm/cortex-r4/armv7.h +++ b/libcpu/arm/cortex-r4/armv7.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,23 +16,23 @@ /* the exception stack without VFP registers */ struct rt_hw_exp_stack { - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; }; #define USERMODE 0x10 diff --git a/libcpu/arm/cortex-r4/cpu.c b/libcpu/arm/cortex-r4/cpu.c index d2e8130e7c..a018bc6959 100644 --- a/libcpu/arm/cortex-r4/cpu.c +++ b/libcpu/arm/cortex-r4/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -30,22 +30,22 @@ void rt_hw_cpu_reset() */ void rt_hw_cpu_shutdown() { - rt_kprintf("shutdown...\n"); + rt_kprintf("shutdown...\n"); - while (1); + while (1); } #ifdef __TI_COMPILER_VERSION__ #ifdef RT_USING_CPU_FFS int __rt_ffs(int value) { - if (value == 0) - return value; + if (value == 0) + return value; - __asm(" rsb r1, r0, #0"); - __asm(" and r1, r1, r0"); - __asm(" clz r1, r1"); - __asm(" rsb r0, r1, #32"); + __asm(" rsb r1, r0, #0"); + __asm(" and r1, r1, r0"); + __asm(" clz r1, r1"); + __asm(" rsb r0, r1, #32"); } #endif diff --git a/libcpu/arm/cortex-r4/interrupt.c b/libcpu/arm/cortex-r4/interrupt.c index 30e14f5a2d..14a9023921 100644 --- a/libcpu/arm/cortex-r4/interrupt.c +++ b/libcpu/arm/cortex-r4/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,7 +17,7 @@ #include "armv7.h" -#define MAX_HANDLERS 96 +#define MAX_HANDLERS 96 /* exception and interrupt handler table */ struct rt_irq_desc irq_desc[MAX_HANDLERS]; @@ -36,16 +36,16 @@ rt_uint32_t rt_thread_switch_interrupt_flag; static void rt_hw_int_not_handle(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } #define vimRAM (0xFFF82000U) void rt_hw_interrupt_init(void) { - register int i; + register int i; - rt_uint32_t *vect_addr; + rt_uint32_t *vect_addr; /* the initialization is done in sys_startup.c */ @@ -55,15 +55,15 @@ void rt_hw_interrupt_init(void) { irq_desc[i].handler = rt_hw_int_not_handle; - vect_addr = (rt_uint32_t *)(vimRAM + i*4); - *vect_addr = (rt_uint32_t)&irq_desc[i]; + vect_addr = (rt_uint32_t *)(vimRAM + i*4); + *vect_addr = (rt_uint32_t)&irq_desc[i]; } - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; } void rt_hw_interrupt_mask(int vector) @@ -86,21 +86,21 @@ void rt_hw_interrupt_umask(int vector) * @return the old handler */ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) + void *param, const char *name) { - rt_isr_handler_t old_handler = RT_NULL; - - if(vector >= 0 && vector < MAX_HANDLERS) - { - old_handler = irq_desc[vector].handler; - if (handler != RT_NULL) - { - irq_desc[vector].handler = handler; - irq_desc[vector].param = param; - } - } - - return old_handler; + rt_isr_handler_t old_handler = RT_NULL; + + if(vector >= 0 && vector < MAX_HANDLERS) + { + old_handler = irq_desc[vector].handler; + if (handler != RT_NULL) + { + irq_desc[vector].handler = handler; + irq_desc[vector].param = param; + } + } + + return old_handler; } /*@}*/ diff --git a/libcpu/arm/cortex-r4/stack.c b/libcpu/arm/cortex-r4/stack.c index 612cde3bfb..539b47d3d2 100644 --- a/libcpu/arm/cortex-r4/stack.c +++ b/libcpu/arm/cortex-r4/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-r4/trap.c b/libcpu/arm/cortex-r4/trap.c index d50ad06538..e6c62390c1 100644 --- a/libcpu/arm/cortex-r4/trap.c +++ b/libcpu/arm/cortex-r4/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -28,13 +28,13 @@ */ void rt_hw_show_register (struct rt_hw_exp_stack *regs) { - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); } /** @@ -49,8 +49,8 @@ void rt_hw_trap_udef(struct rt_hw_exp_stack *regs) { rt_kprintf("undefined instruction\n"); rt_hw_show_register(regs); - if (rt_thread_self() != RT_NULL) - rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); + if (rt_thread_self() != RT_NULL) + rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); rt_hw_cpu_shutdown(); } @@ -68,7 +68,7 @@ void rt_hw_trap_svc(struct rt_hw_exp_stack *regs) rt_kprintf("software interrupt\n"); rt_hw_show_register(regs); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif rt_hw_cpu_shutdown(); } @@ -86,7 +86,7 @@ void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs) rt_kprintf("prefetch abort\n"); rt_hw_show_register(regs); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif rt_hw_cpu_shutdown(); } @@ -104,7 +104,7 @@ void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs) rt_kprintf("Data Abort "); rt_hw_show_register(regs); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif rt_hw_cpu_shutdown(); } @@ -121,7 +121,7 @@ void rt_hw_trap_resv(struct rt_hw_exp_stack *regs) rt_kprintf("Reserved trap\n"); rt_hw_show_register(regs); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif rt_hw_cpu_shutdown(); } @@ -129,15 +129,15 @@ void rt_hw_trap_resv(struct rt_hw_exp_stack *regs) extern rt_isr_handler_t isr_table[]; void rt_hw_trap_irq(void) { - int irqno; - struct rt_irq_desc* irq; - extern struct rt_irq_desc irq_desc[]; + int irqno; + struct rt_irq_desc* irq; + extern struct rt_irq_desc irq_desc[]; - irq = (struct rt_irq_desc*) vimREG->IRQVECREG; - irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc); + irq = (struct rt_irq_desc*) vimREG->IRQVECREG; + irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc); - /* invoke isr */ - irq->handler(irqno, irq->param); + /* invoke isr */ + irq->handler(irqno, irq->param); } void rt_hw_trap_fiq(void) diff --git a/libcpu/arm/dm36x/cpuport.c b/libcpu/arm/dm36x/cpuport.c index f6e8a20056..fc80248528 100644 --- a/libcpu/arm/dm36x/cpuport.c +++ b/libcpu/arm/dm36x/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -11,8 +11,8 @@ #include #include -#define ICACHE_MASK (rt_uint32_t)(1 << 12) -#define DCACHE_MASK (rt_uint32_t)(1 << 2) +#define ICACHE_MASK (rt_uint32_t)(1 << 12) +#define DCACHE_MASK (rt_uint32_t)(1 << 2) extern void machine_reset(void); extern void machine_shutdown(void); @@ -20,70 +20,70 @@ extern void machine_shutdown(void); #ifdef __GNUC__ rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - return i; + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "orr r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "orr r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } rt_inline void cache_disable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "bic r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "bic r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } #endif #ifdef __CC_ARM rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - __asm - { - mrc p15, 0, i, c1, c0, 0 - } + __asm + { + mrc p15, 0, i, c1, c0, 0 + } - return i; + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } rt_inline void cache_disable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } #endif @@ -93,7 +93,7 @@ rt_inline void cache_disable(rt_uint32_t bit) */ void rt_hw_cpu_icache_enable() { - cache_enable(ICACHE_MASK); + cache_enable(ICACHE_MASK); } /** @@ -102,7 +102,7 @@ void rt_hw_cpu_icache_enable() */ void rt_hw_cpu_icache_disable() { - cache_disable(ICACHE_MASK); + cache_disable(ICACHE_MASK); } /** @@ -111,7 +111,7 @@ void rt_hw_cpu_icache_disable() */ rt_base_t rt_hw_cpu_icache_status() { - return (cp15_rd() & ICACHE_MASK); + return (cp15_rd() & ICACHE_MASK); } /** @@ -120,7 +120,7 @@ rt_base_t rt_hw_cpu_icache_status() */ void rt_hw_cpu_dcache_enable() { - cache_enable(DCACHE_MASK); + cache_enable(DCACHE_MASK); } /** @@ -129,7 +129,7 @@ void rt_hw_cpu_dcache_enable() */ void rt_hw_cpu_dcache_disable() { - cache_disable(DCACHE_MASK); + cache_disable(DCACHE_MASK); } /** @@ -138,7 +138,7 @@ void rt_hw_cpu_dcache_disable() */ rt_base_t rt_hw_cpu_dcache_status() { - return (cp15_rd() & DCACHE_MASK); + return (cp15_rd() & DCACHE_MASK); } /** @@ -147,13 +147,13 @@ rt_base_t rt_hw_cpu_dcache_status() */ void rt_hw_cpu_reset() { - - rt_kprintf("Restarting system...\n"); - machine_reset(); - while(1); /* loop forever and wait for reset to happen */ + rt_kprintf("Restarting system...\n"); + machine_reset(); - /* NEVER REACHED */ + while(1); /* loop forever and wait for reset to happen */ + + /* NEVER REACHED */ } /** @@ -162,67 +162,67 @@ void rt_hw_cpu_reset() */ void rt_hw_cpu_shutdown() { - rt_uint32_t level; - rt_kprintf("shutdown...\n"); + rt_uint32_t level; + rt_kprintf("shutdown...\n"); - level = rt_hw_interrupt_disable(); - machine_shutdown(); - while (level) - { - RT_ASSERT(0); - } + level = rt_hw_interrupt_disable(); + machine_shutdown(); + while (level) + { + RT_ASSERT(0); + } } #ifdef RT_USING_CPU_FFS /** - * This function finds the first bit set (beginning with the least significant bit) + * This function finds the first bit set (beginning with the least significant bit) * in value and return the index of that bit. * - * Bits are numbered starting at 1 (the least significant bit). A return value of + * Bits are numbered starting at 1 (the least significant bit). A return value of * zero from any of these functions means that the argument was zero. - * - * @return return the index of the first bit set. If value is 0, then this function + * + * @return return the index of the first bit set. If value is 0, then this function * shall return 0. */ #if defined(__CC_ARM) int __rt_ffs(int value) { - register rt_uint32_t x; + register rt_uint32_t x; + + if (value == 0) + return value; - if (value == 0) - return value; - - __asm - { - rsb x, value, #0 - and x, x, value - clz x, x - rsb x, x, #32 - } + __asm + { + rsb x, value, #0 + and x, x, value + clz x, x + rsb x, x, #32 + } - return x; + return x; } #elif defined(__IAR_SYSTEMS_ICC__) int __rt_ffs(int value) { - if (value == 0) - return value; + if (value == 0) + return value; - __ASM("RSB r4, r0, #0"); - __ASM("AND r4, r4, r0"); - __ASM("CLZ r4, r4"); - __ASM("RSB r0, r4, #32"); + __ASM("RSB r4, r0, #0"); + __ASM("AND r4, r4, r0"); + __ASM("CLZ r4, r4"); + __ASM("RSB r0, r4, #32"); } #elif defined(__GNUC__) int __rt_ffs(int value) { - if (value == 0) - return value; + if (value == 0) + return value; - value &= (-value); - asm ("clz %0, %1": "=r"(value) :"r"(value)); + value &= (-value); + asm ("clz %0, %1": "=r"(value) :"r"(value)); - return (32 - value); + return (32 - value); } #endif diff --git a/libcpu/arm/dm36x/mmu.c b/libcpu/arm/dm36x/mmu.c index abb2c1cd9e..bec2e6a71c 100644 --- a/libcpu/arm/dm36x/mmu.c +++ b/libcpu/arm/dm36x/mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,22 +12,22 @@ #ifdef __CC_ARM void mmu_setttbase(rt_uint32_t i) { - register rt_uint32_t value; + register rt_uint32_t value; /* Invalidates all TLBs.Domain access is selected as * client by configuring domain access register, * in that case access controlled by permission value * set by page table entry */ - value = 0; + value = 0; __asm volatile { mcr p15, 0, value, c8, c7, 0 - } + } - value = 0x55555555; - __asm volatile - { + value = 0x55555555; + __asm volatile + { mcr p15, 0, value, c3, c0, 0 mcr p15, 0, i, c2, c0, 0 } @@ -153,44 +153,44 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) while(ptr < buffer + size) { - __asm volatile - { - MCR p15, 0, ptr, c7, c14, 1 - } + __asm volatile + { + MCR p15, 0, ptr, c7, c14, 1 + } ptr += CACHE_LINE_SIZE; } } void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - __asm volatile - { - MCR p15, 0, ptr, c7, c10, 1 - } - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + __asm volatile + { + MCR p15, 0, ptr, c7, c10, 1 + } + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - __asm volatile - { - MCR p15, 0, ptr, c7, c6, 1 - } - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + __asm volatile + { + MCR p15, 0, ptr, c7, c6, 1 + } + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_tlb() @@ -231,137 +231,137 @@ void mmu_invalidate_dcache_all() #elif defined(__GNUC__) void mmu_setttbase(register rt_uint32_t i) { - register rt_uint32_t value; + register rt_uint32_t value; /* Invalidates all TLBs.Domain access is selected as * client by configuring domain access register, * in that case access controlled by permission value * set by page table entry */ - value = 0; - asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value)); + value = 0; + asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value)); - value = 0x55555555; - asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value)); - asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i)); + value = 0x55555555; + asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value)); + asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i)); } void mmu_set_domain(register rt_uint32_t i) { - asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); + asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); } void mmu_enable() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= 0x1; - i |= (1 << 13); /* High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C */ - /* S R bit=1 0 for system protection */ - i |= (1 << 8); - i &= ~(1 << 9); + i |= 0x1; + i |= (1 << 13); /* High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C */ + /* S R bit=1 0 for system protection */ + i |= (1 << 8); + i &= ~(1 << 9); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~0x1; + i &= ~0x1; - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_icache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 12); + i |= (1 << 12); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_dcache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 2); + i |= (1 << 2); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_icache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 12); + i &= ~(1 << 12); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_dcache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 2); + i &= ~(1 << 2); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_alignfault() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 1); + i |= (1 << 1); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_alignfault() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 1); + i &= ~(1 << 1); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_clean_invalidated_cache_index(int index) { - asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); + asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); } void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) @@ -372,7 +372,7 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) while(ptr < buffer + size) { - asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr)); + asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr)); ptr += CACHE_LINE_SIZE; } } @@ -380,38 +380,38 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr)); - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr)); + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr)); - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr)); + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_tlb() { - asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); } void mmu_invalidate_icache() { - asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); } void mmu_invalidate_dcache_all() @@ -462,13 +462,13 @@ void mmu_create_pte(struct mem_desc *mdesc) if (*pTT == 0) /* Level 1 page table item not used, now update pgd item */ { *pTT = pte_offset | sect_attr; - p_pteentry = (rt_uint32_t *)pte_offset + + p_pteentry = (rt_uint32_t *)pte_offset + ((vaddr & 0x000ff000) >> 12); pte_offset += 1024; } else /* using old Level 1 page table item */ { - p_pteentry = (rt_uint32_t *)(*pTT & 0xfffffc00) + + p_pteentry = (rt_uint32_t *)(*pTT & 0xfffffc00) + ((vaddr & 0x000ff000) >> 12); } @@ -503,13 +503,13 @@ static void build_pte_mem_desc(struct mem_desc *mdesc, rt_uint32_t size) void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size) { - /* disable I/D cache */ - mmu_disable_dcache(); - mmu_disable_icache(); - mmu_disable(); - mmu_invalidate_tlb(); + /* disable I/D cache */ + mmu_disable_dcache(); + mmu_disable_icache(); + mmu_disable(); + mmu_invalidate_tlb(); - /* clear pgd and pte table */ + /* clear pgd and pte table */ rt_memset((void *)_pgd_table, 0, 16*1024); rt_memset((void *)_pte_table, 0, RT_MMU_PTE_SIZE); build_pte_mem_desc(mdesc, size); diff --git a/libcpu/arm/dm36x/mmu.h b/libcpu/arm/dm36x/mmu.h index 3410b881ac..60a4e3c6e9 100644 --- a/libcpu/arm/dm36x/mmu.h +++ b/libcpu/arm/dm36x/mmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,7 +12,7 @@ #include -#define CACHE_LINE_SIZE 32 +#define CACHE_LINE_SIZE 32 /* * Hardware page table definitions. @@ -30,7 +30,7 @@ /* * - section */ -#define PGD_SECT_BUFFERABLE (1 << 2) +#define PGD_SECT_BUFFERABLE (1 << 2) #define PGD_SECT_CACHEABLE (1 << 3) #define PGD_SECT_XN (1 << 4) /* ARMv6 */ #define PGD_SECT_AP0 (1 << 10) @@ -133,14 +133,14 @@ #define PAGE_RO_FAULT (PAGE_AP_RO|PTE_TYPE_SMALL) /* Read Only without cache and write buffer */ struct mem_desc { - rt_uint32_t vaddr_start; - rt_uint32_t vaddr_end; - rt_uint32_t paddr_start; - rt_uint32_t sect_attr; /* when page mapped */ - rt_uint32_t page_attr; /* only sector mapped valid */ - rt_uint32_t mapped_mode; - #define SECT_MAPPED 0 - #define PAGE_MAPPED 1 + rt_uint32_t vaddr_start; + rt_uint32_t vaddr_end; + rt_uint32_t paddr_start; + rt_uint32_t sect_attr; /* when page mapped */ + rt_uint32_t page_attr; /* only sector mapped valid */ + rt_uint32_t mapped_mode; + #define SECT_MAPPED 0 + #define PAGE_MAPPED 1 }; diff --git a/libcpu/arm/dm36x/stack.c b/libcpu/arm/dm36x/stack.c index 9d7385b9c8..e725d060c1 100644 --- a/libcpu/arm/dm36x/stack.c +++ b/libcpu/arm/dm36x/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/lpc214x/cpuport.c b/libcpu/arm/lpc214x/cpuport.c index 2543a5e0a9..723699c3c8 100644 --- a/libcpu/arm/lpc214x/cpuport.c +++ b/libcpu/arm/lpc214x/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,13 +13,13 @@ #include #include "lpc214x.h" -#define MAX_HANDLERS 32 -#define SVCMODE 0x13 +#define MAX_HANDLERS 32 +#define SVCMODE 0x13 extern rt_uint32_t rt_interrupt_nest; /* exception and interrupt handler table */ -struct rt_irq_desc irq_desc[MAX_HANDLERS]; +struct rt_irq_desc irq_desc[MAX_HANDLERS]; /** * @addtogroup LPC214x @@ -37,35 +37,35 @@ struct rt_irq_desc irq_desc[MAX_HANDLERS]; * @return stack address */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) + rt_uint8_t *stack_addr, void *texit) { - unsigned long *stk; - - stk = (unsigned long *)stack_addr; - *(stk) = (unsigned long)tentry; /* entry point */ - *(--stk) = (unsigned long)texit; /* lr */ - *(--stk) = 0; /* r12 */ - *(--stk) = 0; /* r11 */ - *(--stk) = 0; /* r10 */ - *(--stk) = 0; /* r9 */ - *(--stk) = 0; /* r8 */ - *(--stk) = 0; /* r7 */ - *(--stk) = 0; /* r6 */ - *(--stk) = 0; /* r5 */ - *(--stk) = 0; /* r4 */ - *(--stk) = 0; /* r3 */ - *(--stk) = 0; /* r2 */ - *(--stk) = 0; /* r1 */ - *(--stk) = (unsigned long)parameter; /* r0 : argument */ - - /* cpsr */ - if ((rt_uint32_t)tentry & 0x01) - *(--stk) = SVCMODE | 0x20; /* thumb mode */ - else - *(--stk) = SVCMODE; /* arm mode */ - - /* return task's current stack address */ - return (rt_uint8_t *)stk; + unsigned long *stk; + + stk = (unsigned long *)stack_addr; + *(stk) = (unsigned long)tentry; /* entry point */ + *(--stk) = (unsigned long)texit; /* lr */ + *(--stk) = 0; /* r12 */ + *(--stk) = 0; /* r11 */ + *(--stk) = 0; /* r10 */ + *(--stk) = 0; /* r9 */ + *(--stk) = 0; /* r8 */ + *(--stk) = 0; /* r7 */ + *(--stk) = 0; /* r6 */ + *(--stk) = 0; /* r5 */ + *(--stk) = 0; /* r4 */ + *(--stk) = 0; /* r3 */ + *(--stk) = 0; /* r2 */ + *(--stk) = 0; /* r1 */ + *(--stk) = (unsigned long)parameter; /* r0 : argument */ + + /* cpsr */ + if ((rt_uint32_t)tentry & 0x01) + *(--stk) = SVCMODE | 0x20; /* thumb mode */ + else + *(--stk) = SVCMODE; /* arm mode */ + + /* return task's current stack address */ + return (rt_uint8_t *)stk; } /* exception and interrupt handler table */ @@ -74,7 +74,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag; void rt_hw_interrupt_handler(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } /** @@ -82,32 +82,32 @@ void rt_hw_interrupt_handler(int vector, void *param) */ void rt_hw_interrupt_init(void) { - rt_base_t index; - rt_uint32_t *vect_addr, *vect_ctl; + rt_base_t index; + rt_uint32_t *vect_addr, *vect_ctl; - /* initialize VIC*/ - VICIntEnClr = 0xffffffff; - VICVectAddr = 0; - /* set all to IRQ */ - VICIntSelect = 0; + /* initialize VIC*/ + VICIntEnClr = 0xffffffff; + VICVectAddr = 0; + /* set all to IRQ */ + VICIntSelect = 0; rt_memset(irq_desc, 0x00, sizeof(irq_desc)); - for (index = 0; index < MAX_HANDLERS; index ++) - { + for (index = 0; index < MAX_HANDLERS; index ++) + { irq_desc[index].handler = rt_hw_interrupt_handler; - vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + (index << 2)); - vect_ctl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + (index << 2)); + vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + (index << 2)); + vect_ctl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + (index << 2)); - *vect_addr = (rt_uint32_t)&irq_desc[index]; - *vect_ctl = 0xF; - } + *vect_addr = (rt_uint32_t)&irq_desc[index]; + *vect_ctl = 0xF; + } - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; } /** @@ -116,7 +116,7 @@ void rt_hw_interrupt_init(void) */ void rt_hw_interrupt_mask(int vector) { - VICIntEnClr = (1 << vector); + VICIntEnClr = (1 << vector); } /** @@ -125,7 +125,7 @@ void rt_hw_interrupt_mask(int vector) */ void rt_hw_interrupt_umask(int vector) { - VICIntEnable = (1 << vector); + VICIntEnable = (1 << vector); } /** @@ -143,17 +143,17 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, if(vector >= 0 && vector < MAX_HANDLERS) { - rt_uint32_t* vect_ctl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + (vector << 2)); + rt_uint32_t* vect_ctl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + (vector << 2)); /* assign IRQ slot and enable this slot */ *vect_ctl = 0x20 | (vector & 0x1F); old_handler = irq_desc[vector].handler; - if (handler != RT_NULL) - { - irq_desc[vector].handler = handler; - irq_desc[vector].param = param; - } + if (handler != RT_NULL) + { + irq_desc[vector].handler = handler; + irq_desc[vector].param = param; + } } return old_handler; @@ -173,22 +173,22 @@ void rt_hw_cpu_reset(void) */ void rt_hw_cpu_shutdown() { - rt_kprintf("shutdown...\n"); + rt_kprintf("shutdown...\n"); - while (1); + while (1); } void rt_hw_trap_irq(void) { int irqno; - struct rt_irq_desc* irq; + struct rt_irq_desc* irq; extern struct rt_irq_desc irq_desc[]; - irq = (struct rt_irq_desc*) VICVectAddr; - irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc); + irq = (struct rt_irq_desc*) VICVectAddr; + irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc); - /* invoke isr */ - irq->handler(irqno, irq->param); + /* invoke isr */ + irq->handler(irqno, irq->param); /* acknowledge Interrupt */ // VICVectAddr = 0; diff --git a/libcpu/arm/lpc24xx/LPC24xx.h b/libcpu/arm/lpc24xx/LPC24xx.h index 5cb9730854..827310ca67 100644 --- a/libcpu/arm/lpc24xx/LPC24xx.h +++ b/libcpu/arm/lpc24xx/LPC24xx.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,20 +14,20 @@ #ifdef __cplusplus extern "C" { #endif - -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define ABORTMODE 0x17 -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 - -#define MCLK (72000000) - + +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define ABORTMODE 0x17 +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 + +#define MCLK (72000000) + /* Vectored Interrupt Controller (VIC) */ -#define VIC_BASE_ADDR 0xFFFFF000 +#define VIC_BASE_ADDR 0xFFFFF000 #define VICIRQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x000)) #define VICFIQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x004)) #define VICRawIntr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x008)) @@ -111,7 +111,7 @@ these registers are known as "VICVectPriority(x)". */ /* Pin Connect Block */ -#define PINSEL_BASE_ADDR 0xE002C000 +#define PINSEL_BASE_ADDR 0xE002C000 #define PINSEL0 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x00)) #define PINSEL1 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x04)) #define PINSEL2 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x08)) @@ -137,7 +137,7 @@ these registers are known as "VICVectPriority(x)". */ #define PINMODE9 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x64)) /* General Purpose Input/Output (GPIO) */ -#define GPIO_BASE_ADDR 0xE0028000 +#define GPIO_BASE_ADDR 0xE0028000 #define IOPIN0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x00)) #define IOSET0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x04)) #define IODIR0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x08)) @@ -148,13 +148,13 @@ these registers are known as "VICVectPriority(x)". */ #define IOCLR1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x1C)) /* GPIO Interrupt Registers */ -#define IO0_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x90)) +#define IO0_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x90)) #define IO0_INT_EN_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x94)) #define IO0_INT_STAT_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x84)) #define IO0_INT_STAT_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x88)) #define IO0_INT_CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x8C)) -#define IO2_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB0)) +#define IO2_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB0)) #define IO2_INT_EN_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB4)) #define IO2_INT_STAT_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA4)) #define IO2_INT_STAT_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA8)) @@ -162,227 +162,227 @@ these registers are known as "VICVectPriority(x)". */ #define IO_INT_STAT (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x80)) -#define PARTCFG_BASE_ADDR 0x3FFF8000 -#define PARTCFG (*(volatile unsigned long *)(PARTCFG_BASE_ADDR + 0x00)) +#define PARTCFG_BASE_ADDR 0x3FFF8000 +#define PARTCFG (*(volatile unsigned long *)(PARTCFG_BASE_ADDR + 0x00)) /* Fast I/O setup */ -#define FIO_BASE_ADDR 0x3FFFC000 -#define FIO0DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x00)) +#define FIO_BASE_ADDR 0x3FFFC000 +#define FIO0DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x00)) #define FIO0MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x10)) #define FIO0PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x14)) #define FIO0SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x18)) #define FIO0CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x1C)) -#define FIO1DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x20)) +#define FIO1DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x20)) #define FIO1MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x30)) #define FIO1PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x34)) #define FIO1SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x38)) #define FIO1CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x3C)) -#define FIO2DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x40)) +#define FIO2DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x40)) #define FIO2MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x50)) #define FIO2PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x54)) #define FIO2SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x58)) #define FIO2CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x5C)) -#define FIO3DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x60)) +#define FIO3DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x60)) #define FIO3MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x70)) #define FIO3PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x74)) #define FIO3SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x78)) #define FIO3CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x7C)) -#define FIO4DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x80)) +#define FIO4DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x80)) #define FIO4MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x90)) #define FIO4PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x94)) #define FIO4SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x98)) #define FIO4CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x9C)) /* FIOs can be accessed through WORD, HALF-WORD or BYTE. */ -#define FIO0DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x00)) -#define FIO1DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x20)) -#define FIO2DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x40)) -#define FIO3DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x60)) -#define FIO4DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x80)) - -#define FIO0DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x01)) -#define FIO1DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) -#define FIO2DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x41)) -#define FIO3DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x61)) -#define FIO4DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x81)) - -#define FIO0DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x02)) -#define FIO1DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x22)) -#define FIO2DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x42)) -#define FIO3DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x62)) -#define FIO4DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x82)) - -#define FIO0DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x03)) -#define FIO1DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x23)) -#define FIO2DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x43)) -#define FIO3DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x63)) -#define FIO4DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x83)) - -#define FIO0DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x00)) -#define FIO1DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x20)) -#define FIO2DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x40)) -#define FIO3DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x60)) -#define FIO4DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x80)) - -#define FIO0DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x02)) -#define FIO1DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x22)) -#define FIO2DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x42)) -#define FIO3DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x62)) -#define FIO4DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x82)) - -#define FIO0MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x10)) -#define FIO1MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x30)) -#define FIO2MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x50)) -#define FIO3MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x70)) -#define FIO4MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x90)) - -#define FIO0MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x11)) -#define FIO1MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) -#define FIO2MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x51)) -#define FIO3MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x71)) -#define FIO4MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x91)) - -#define FIO0MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x12)) -#define FIO1MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x32)) -#define FIO2MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x52)) -#define FIO3MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x72)) -#define FIO4MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x92)) - -#define FIO0MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x13)) -#define FIO1MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x33)) -#define FIO2MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x53)) -#define FIO3MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x73)) -#define FIO4MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x93)) - -#define FIO0MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x10)) -#define FIO1MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x30)) -#define FIO2MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x50)) -#define FIO3MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x70)) -#define FIO4MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x90)) - -#define FIO0MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x12)) -#define FIO1MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x32)) -#define FIO2MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x52)) -#define FIO3MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x72)) -#define FIO4MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x92)) - -#define FIO0PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x14)) -#define FIO1PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x34)) -#define FIO2PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x54)) -#define FIO3PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x74)) -#define FIO4PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x94)) - -#define FIO0PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x15)) -#define FIO1PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x35)) -#define FIO2PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x55)) -#define FIO3PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x75)) -#define FIO4PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x95)) - -#define FIO0PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x16)) -#define FIO1PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x36)) -#define FIO2PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x56)) -#define FIO3PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x76)) -#define FIO4PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x96)) - -#define FIO0PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x17)) -#define FIO1PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x37)) -#define FIO2PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x57)) -#define FIO3PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x77)) -#define FIO4PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x97)) - -#define FIO0PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x14)) -#define FIO1PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x34)) -#define FIO2PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x54)) -#define FIO3PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x74)) -#define FIO4PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x94)) - -#define FIO0PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x16)) -#define FIO1PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x36)) -#define FIO2PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x56)) -#define FIO3PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x76)) -#define FIO4PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x96)) - -#define FIO0SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x18)) -#define FIO1SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x38)) -#define FIO2SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x58)) -#define FIO3SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x78)) -#define FIO4SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x98)) - -#define FIO0SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x19)) -#define FIO1SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x29)) -#define FIO2SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x59)) -#define FIO3SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x79)) -#define FIO4SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x99)) - -#define FIO0SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1A)) -#define FIO1SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3A)) -#define FIO2SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5A)) -#define FIO3SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7A)) -#define FIO4SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9A)) - -#define FIO0SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1B)) -#define FIO1SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3B)) -#define FIO2SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5B)) -#define FIO3SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7B)) -#define FIO4SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9B)) - -#define FIO0SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x18)) -#define FIO1SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x38)) -#define FIO2SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x58)) -#define FIO3SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x78)) -#define FIO4SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x98)) - -#define FIO0SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1A)) -#define FIO1SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3A)) -#define FIO2SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5A)) -#define FIO3SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7A)) -#define FIO4SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9A)) - -#define FIO0CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1C)) -#define FIO1CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3C)) -#define FIO2CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5C)) -#define FIO3CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7C)) -#define FIO4CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9C)) - -#define FIO0CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1D)) -#define FIO1CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x2D)) -#define FIO2CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5D)) -#define FIO3CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7D)) -#define FIO4CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9D)) - -#define FIO0CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1E)) -#define FIO1CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3E)) -#define FIO2CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5E)) -#define FIO3CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7E)) -#define FIO4CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9E)) - -#define FIO0CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1F)) -#define FIO1CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3F)) -#define FIO2CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5F)) -#define FIO3CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7F)) -#define FIO4CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9F)) - -#define FIO0CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1C)) -#define FIO1CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3C)) -#define FIO2CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5C)) -#define FIO3CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7C)) -#define FIO4CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9C)) - -#define FIO0CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1E)) -#define FIO1CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3E)) -#define FIO2CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5E)) -#define FIO3CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7E)) -#define FIO4CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9E)) +#define FIO0DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x00)) +#define FIO1DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x20)) +#define FIO2DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x40)) +#define FIO3DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x60)) +#define FIO4DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x80)) + +#define FIO0DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x01)) +#define FIO1DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) +#define FIO2DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x41)) +#define FIO3DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x61)) +#define FIO4DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x81)) + +#define FIO0DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x02)) +#define FIO1DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x22)) +#define FIO2DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x42)) +#define FIO3DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x62)) +#define FIO4DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x82)) + +#define FIO0DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x03)) +#define FIO1DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x23)) +#define FIO2DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x43)) +#define FIO3DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x63)) +#define FIO4DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x83)) + +#define FIO0DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x00)) +#define FIO1DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x20)) +#define FIO2DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x40)) +#define FIO3DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x60)) +#define FIO4DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x80)) + +#define FIO0DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x02)) +#define FIO1DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x22)) +#define FIO2DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x42)) +#define FIO3DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x62)) +#define FIO4DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x82)) + +#define FIO0MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x10)) +#define FIO1MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x30)) +#define FIO2MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x50)) +#define FIO3MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x70)) +#define FIO4MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x90)) + +#define FIO0MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x11)) +#define FIO1MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) +#define FIO2MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x51)) +#define FIO3MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x71)) +#define FIO4MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x91)) + +#define FIO0MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x12)) +#define FIO1MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x32)) +#define FIO2MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x52)) +#define FIO3MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x72)) +#define FIO4MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x92)) + +#define FIO0MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x13)) +#define FIO1MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x33)) +#define FIO2MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x53)) +#define FIO3MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x73)) +#define FIO4MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x93)) + +#define FIO0MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x10)) +#define FIO1MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x30)) +#define FIO2MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x50)) +#define FIO3MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x70)) +#define FIO4MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x90)) + +#define FIO0MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x12)) +#define FIO1MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x32)) +#define FIO2MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x52)) +#define FIO3MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x72)) +#define FIO4MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x92)) + +#define FIO0PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x14)) +#define FIO1PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x34)) +#define FIO2PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x54)) +#define FIO3PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x74)) +#define FIO4PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x94)) + +#define FIO0PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x15)) +#define FIO1PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x35)) +#define FIO2PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x55)) +#define FIO3PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x75)) +#define FIO4PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x95)) + +#define FIO0PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x16)) +#define FIO1PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x36)) +#define FIO2PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x56)) +#define FIO3PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x76)) +#define FIO4PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x96)) + +#define FIO0PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x17)) +#define FIO1PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x37)) +#define FIO2PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x57)) +#define FIO3PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x77)) +#define FIO4PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x97)) + +#define FIO0PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x14)) +#define FIO1PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x34)) +#define FIO2PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x54)) +#define FIO3PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x74)) +#define FIO4PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x94)) + +#define FIO0PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x16)) +#define FIO1PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x36)) +#define FIO2PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x56)) +#define FIO3PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x76)) +#define FIO4PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x96)) + +#define FIO0SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x18)) +#define FIO1SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x38)) +#define FIO2SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x58)) +#define FIO3SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x78)) +#define FIO4SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x98)) + +#define FIO0SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x19)) +#define FIO1SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x29)) +#define FIO2SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x59)) +#define FIO3SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x79)) +#define FIO4SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x99)) + +#define FIO0SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1A)) +#define FIO1SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3A)) +#define FIO2SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5A)) +#define FIO3SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7A)) +#define FIO4SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9A)) + +#define FIO0SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1B)) +#define FIO1SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3B)) +#define FIO2SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5B)) +#define FIO3SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7B)) +#define FIO4SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9B)) + +#define FIO0SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x18)) +#define FIO1SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x38)) +#define FIO2SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x58)) +#define FIO3SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x78)) +#define FIO4SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x98)) + +#define FIO0SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1A)) +#define FIO1SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3A)) +#define FIO2SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5A)) +#define FIO3SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7A)) +#define FIO4SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9A)) + +#define FIO0CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1C)) +#define FIO1CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3C)) +#define FIO2CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5C)) +#define FIO3CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7C)) +#define FIO4CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9C)) + +#define FIO0CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1D)) +#define FIO1CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x2D)) +#define FIO2CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5D)) +#define FIO3CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7D)) +#define FIO4CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9D)) + +#define FIO0CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1E)) +#define FIO1CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3E)) +#define FIO2CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5E)) +#define FIO3CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7E)) +#define FIO4CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9E)) + +#define FIO0CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1F)) +#define FIO1CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3F)) +#define FIO2CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5F)) +#define FIO3CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7F)) +#define FIO4CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9F)) + +#define FIO0CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1C)) +#define FIO1CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3C)) +#define FIO2CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5C)) +#define FIO3CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7C)) +#define FIO4CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9C)) + +#define FIO0CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1E)) +#define FIO1CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3E)) +#define FIO2CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5E)) +#define FIO3CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7E)) +#define FIO4CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9E)) /* System Control Block(SCB) modules include Memory Accelerator Module, -Phase Locked Loop, VPB divider, Power Control, External Interrupt, +Phase Locked Loop, VPB divider, Power Control, External Interrupt, Reset, and Code Security/Debugging */ -#define SCB_BASE_ADDR 0xE01FC000 +#define SCB_BASE_ADDR 0xE01FC000 /* Memory Accelerator Module (MAM) */ #define MAMCR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x000)) @@ -405,7 +405,7 @@ Reset, and Code Security/Debugging */ #define CLKSRCSEL (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x10C)) #define PCLKSEL0 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A8)) #define PCLKSEL1 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1AC)) - + /* External Interrupts */ #define EXTINT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x140)) #define INTWAKE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x144)) @@ -423,22 +423,22 @@ Reset, and Code Security/Debugging */ #define AHBCFG2 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x18C)) /* System Controls and Status */ -#define SCS (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0)) +#define SCS (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0)) -/* MPMC(EMC) registers, note: all the external memory controller(EMC) registers +/* MPMC(EMC) registers, note: all the external memory controller(EMC) registers are for LPC24xx only. */ -#define STATIC_MEM0_BASE 0x80000000 -#define STATIC_MEM1_BASE 0x81000000 -#define STATIC_MEM2_BASE 0x82000000 -#define STATIC_MEM3_BASE 0x83000000 +#define STATIC_MEM0_BASE 0x80000000 +#define STATIC_MEM1_BASE 0x81000000 +#define STATIC_MEM2_BASE 0x82000000 +#define STATIC_MEM3_BASE 0x83000000 -#define DYNAMIC_MEM0_BASE 0xA0000000 -#define DYNAMIC_MEM1_BASE 0xB0000000 -#define DYNAMIC_MEM2_BASE 0xC0000000 -#define DYNAMIC_MEM3_BASE 0xD0000000 +#define DYNAMIC_MEM0_BASE 0xA0000000 +#define DYNAMIC_MEM1_BASE 0xB0000000 +#define DYNAMIC_MEM2_BASE 0xC0000000 +#define DYNAMIC_MEM3_BASE 0xD0000000 /* External Memory Controller (EMC) */ -#define EMC_BASE_ADDR 0xFFE08000 +#define EMC_BASE_ADDR 0xFFE08000 #define EMC_CTRL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x000)) #define EMC_STAT (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x004)) #define EMC_CONFIG (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x008)) @@ -503,9 +503,9 @@ are for LPC24xx only. */ #define EMC_STA_EXT_WAIT (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x880)) - + /* Timer 0 */ -#define TMR0_BASE_ADDR 0xE0004000 +#define TMR0_BASE_ADDR 0xE0004000 #define T0IR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x00)) #define T0TCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x04)) #define T0TC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x08)) @@ -525,7 +525,7 @@ are for LPC24xx only. */ #define T0CTCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x70)) /* Timer 1 */ -#define TMR1_BASE_ADDR 0xE0008000 +#define TMR1_BASE_ADDR 0xE0008000 #define T1IR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x00)) #define T1TCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x04)) #define T1TC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x08)) @@ -545,7 +545,7 @@ are for LPC24xx only. */ #define T1CTCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x70)) /* Timer 2 */ -#define TMR2_BASE_ADDR 0xE0070000 +#define TMR2_BASE_ADDR 0xE0070000 #define T2IR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x00)) #define T2TCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x04)) #define T2TC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x08)) @@ -565,7 +565,7 @@ are for LPC24xx only. */ #define T2CTCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x70)) /* Timer 3 */ -#define TMR3_BASE_ADDR 0xE0074000 +#define TMR3_BASE_ADDR 0xE0074000 #define T3IR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x00)) #define T3TCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x04)) #define T3TC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x08)) @@ -586,7 +586,7 @@ are for LPC24xx only. */ /* Pulse Width Modulator (PWM) */ -#define PWM0_BASE_ADDR 0xE0014000 +#define PWM0_BASE_ADDR 0xE0014000 #define PWM0IR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x00)) #define PWM0TCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x04)) #define PWM0TC (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x08)) @@ -610,7 +610,7 @@ are for LPC24xx only. */ #define PWM0LER (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x50)) #define PWM0CTCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x70)) -#define PWM1_BASE_ADDR 0xE0018000 +#define PWM1_BASE_ADDR 0xE0018000 #define PWM1IR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x00)) #define PWM1TCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x04)) #define PWM1TC (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x08)) @@ -636,7 +636,7 @@ are for LPC24xx only. */ /* Universal Asynchronous Receiver Transmitter 0 (UART0) */ -#define UART0_BASE_ADDR 0xE000C000 +#define UART0_BASE_ADDR 0xE000C000 #define U0RBR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) #define U0THR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) #define U0DLL (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) @@ -653,7 +653,7 @@ are for LPC24xx only. */ #define U0TER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x30)) /* Universal Asynchronous Receiver Transmitter 1 (UART1) */ -#define UART1_BASE_ADDR 0xE0010000 +#define UART1_BASE_ADDR 0xE0010000 #define U1RBR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) #define U1THR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) #define U1DLL (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) @@ -671,7 +671,7 @@ are for LPC24xx only. */ #define U1TER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x30)) /* Universal Asynchronous Receiver Transmitter 2 (UART2) */ -#define UART2_BASE_ADDR 0xE0078000 +#define UART2_BASE_ADDR 0xE0078000 #define U2RBR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) #define U2THR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) #define U2DLL (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) @@ -688,7 +688,7 @@ are for LPC24xx only. */ #define U2TER (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x30)) /* Universal Asynchronous Receiver Transmitter 3 (UART3) */ -#define UART3_BASE_ADDR 0xE007C000 +#define UART3_BASE_ADDR 0xE007C000 #define U3RBR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) #define U3THR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) #define U3DLL (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) @@ -705,7 +705,7 @@ are for LPC24xx only. */ #define U3TER (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x30)) /* I2C Interface 0 */ -#define I2C0_BASE_ADDR 0xE001C000 +#define I2C0_BASE_ADDR 0xE001C000 #define I20CONSET (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x00)) #define I20STAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x04)) #define I20DAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x08)) @@ -715,7 +715,7 @@ are for LPC24xx only. */ #define I20CONCLR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x18)) /* I2C Interface 1 */ -#define I2C1_BASE_ADDR 0xE005C000 +#define I2C1_BASE_ADDR 0xE005C000 #define I21CONSET (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x00)) #define I21STAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x04)) #define I21DAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x08)) @@ -725,7 +725,7 @@ are for LPC24xx only. */ #define I21CONCLR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x18)) /* I2C Interface 2 */ -#define I2C2_BASE_ADDR 0xE0080000 +#define I2C2_BASE_ADDR 0xE0080000 #define I22CONSET (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x00)) #define I22STAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x04)) #define I22DAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x08)) @@ -735,7 +735,7 @@ are for LPC24xx only. */ #define I22CONCLR (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x18)) /* SPI0 (Serial Peripheral Interface 0) */ -#define SPI0_BASE_ADDR 0xE0020000 +#define SPI0_BASE_ADDR 0xE0020000 #define S0SPCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x00)) #define S0SPSR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x04)) #define S0SPDR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x08)) @@ -743,7 +743,7 @@ are for LPC24xx only. */ #define S0SPINT (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x1C)) /* SSP0 Controller */ -#define SSP0_BASE_ADDR 0xE0068000 +#define SSP0_BASE_ADDR 0xE0068000 #define SSP0CR0 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x00)) #define SSP0CR1 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x04)) #define SSP0DR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x08)) @@ -756,7 +756,7 @@ are for LPC24xx only. */ #define SSP0DMACR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x24)) /* SSP1 Controller */ -#define SSP1_BASE_ADDR 0xE0030000 +#define SSP1_BASE_ADDR 0xE0030000 #define SSP1CR0 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x00)) #define SSP1CR1 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x04)) #define SSP1DR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x08)) @@ -770,7 +770,7 @@ are for LPC24xx only. */ /* Real Time Clock */ -#define RTC_BASE_ADDR 0xE0024000 +#define RTC_BASE_ADDR 0xE0024000 #define RTC_ILR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x00)) #define RTC_CTC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x04)) #define RTC_CCR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x08)) @@ -801,7 +801,7 @@ are for LPC24xx only. */ /* A/D Converter 0 (AD0) */ -#define AD0_BASE_ADDR 0xE0034000 +#define AD0_BASE_ADDR 0xE0034000 #define AD0CR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x00)) #define AD0GDR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x04)) #define AD0INTEN (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x0C)) @@ -817,12 +817,12 @@ are for LPC24xx only. */ /* D/A Converter */ -#define DAC_BASE_ADDR 0xE006C000 +#define DAC_BASE_ADDR 0xE006C000 #define DACR (*(volatile unsigned long *)(DAC_BASE_ADDR + 0x00)) /* Watchdog */ -#define WDG_BASE_ADDR 0xE0000000 +#define WDG_BASE_ADDR 0xE0000000 #define WDMOD (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x00)) #define WDTC (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x04)) #define WDFEED (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x08)) @@ -830,78 +830,78 @@ are for LPC24xx only. */ #define WDCLKSEL (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x10)) /* CAN CONTROLLERS AND ACCEPTANCE FILTER */ -#define CAN_ACCEPT_BASE_ADDR 0xE003C000 -#define CAN_AFMR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x00)) -#define CAN_SFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x04)) -#define CAN_SFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x08)) -#define CAN_EFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x0C)) -#define CAN_EFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x10)) -#define CAN_EOT (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x14)) -#define CAN_LUT_ERR_ADR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x18)) -#define CAN_LUT_ERR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x1C)) - -#define CAN_CENTRAL_BASE_ADDR 0xE0040000 -#define CAN_TX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x00)) -#define CAN_RX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x04)) -#define CAN_MSR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x08)) - -#define CAN1_BASE_ADDR 0xE0044000 -#define CAN1MOD (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x00)) -#define CAN1CMR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x04)) -#define CAN1GSR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x08)) -#define CAN1ICR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x0C)) -#define CAN1IER (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x10)) -#define CAN1BTR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x14)) -#define CAN1EWL (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x18)) -#define CAN1SR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x1C)) -#define CAN1RFS (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x20)) -#define CAN1RID (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x24)) -#define CAN1RDA (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x28)) -#define CAN1RDB (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x2C)) - -#define CAN1TFI1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x30)) -#define CAN1TID1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x34)) -#define CAN1TDA1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x38)) -#define CAN1TDB1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x3C)) -#define CAN1TFI2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x40)) -#define CAN1TID2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x44)) -#define CAN1TDA2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x48)) -#define CAN1TDB2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x4C)) -#define CAN1TFI3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x50)) -#define CAN1TID3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x54)) -#define CAN1TDA3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x58)) -#define CAN1TDB3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x5C)) - -#define CAN2_BASE_ADDR 0xE0048000 -#define CAN2MOD (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x00)) -#define CAN2CMR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x04)) -#define CAN2GSR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x08)) -#define CAN2ICR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x0C)) -#define CAN2IER (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x10)) -#define CAN2BTR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x14)) -#define CAN2EWL (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x18)) -#define CAN2SR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x1C)) -#define CAN2RFS (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x20)) -#define CAN2RID (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x24)) -#define CAN2RDA (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x28)) -#define CAN2RDB (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x2C)) - -#define CAN2TFI1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x30)) -#define CAN2TID1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x34)) -#define CAN2TDA1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x38)) -#define CAN2TDB1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x3C)) -#define CAN2TFI2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x40)) -#define CAN2TID2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x44)) -#define CAN2TDA2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x48)) -#define CAN2TDB2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x4C)) -#define CAN2TFI3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x50)) -#define CAN2TID3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x54)) -#define CAN2TDA3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x58)) -#define CAN2TDB3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x5C)) +#define CAN_ACCEPT_BASE_ADDR 0xE003C000 +#define CAN_AFMR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x00)) +#define CAN_SFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x04)) +#define CAN_SFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x08)) +#define CAN_EFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x0C)) +#define CAN_EFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x10)) +#define CAN_EOT (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x14)) +#define CAN_LUT_ERR_ADR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x18)) +#define CAN_LUT_ERR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x1C)) + +#define CAN_CENTRAL_BASE_ADDR 0xE0040000 +#define CAN_TX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x00)) +#define CAN_RX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x04)) +#define CAN_MSR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x08)) + +#define CAN1_BASE_ADDR 0xE0044000 +#define CAN1MOD (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x00)) +#define CAN1CMR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x04)) +#define CAN1GSR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x08)) +#define CAN1ICR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x0C)) +#define CAN1IER (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x10)) +#define CAN1BTR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x14)) +#define CAN1EWL (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x18)) +#define CAN1SR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x1C)) +#define CAN1RFS (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x20)) +#define CAN1RID (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x24)) +#define CAN1RDA (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x28)) +#define CAN1RDB (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x2C)) + +#define CAN1TFI1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x30)) +#define CAN1TID1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x34)) +#define CAN1TDA1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x38)) +#define CAN1TDB1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x3C)) +#define CAN1TFI2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x40)) +#define CAN1TID2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x44)) +#define CAN1TDA2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x48)) +#define CAN1TDB2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x4C)) +#define CAN1TFI3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x50)) +#define CAN1TID3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x54)) +#define CAN1TDA3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x58)) +#define CAN1TDB3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x5C)) + +#define CAN2_BASE_ADDR 0xE0048000 +#define CAN2MOD (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x00)) +#define CAN2CMR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x04)) +#define CAN2GSR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x08)) +#define CAN2ICR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x0C)) +#define CAN2IER (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x10)) +#define CAN2BTR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x14)) +#define CAN2EWL (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x18)) +#define CAN2SR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x1C)) +#define CAN2RFS (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x20)) +#define CAN2RID (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x24)) +#define CAN2RDA (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x28)) +#define CAN2RDB (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x2C)) + +#define CAN2TFI1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x30)) +#define CAN2TID1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x34)) +#define CAN2TDA1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x38)) +#define CAN2TDB1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x3C)) +#define CAN2TFI2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x40)) +#define CAN2TID2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x44)) +#define CAN2TDA2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x48)) +#define CAN2TDB2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x4C)) +#define CAN2TFI3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x50)) +#define CAN2TID3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x54)) +#define CAN2TDA3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x58)) +#define CAN2TDB3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x5C)) /* MultiMedia Card Interface(MCI) Controller */ -#define MCI_BASE_ADDR 0xE008C000 +#define MCI_BASE_ADDR 0xE008C000 #define MCI_POWER (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x00)) #define MCI_CLOCK (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x04)) #define MCI_ARGUMENT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x08)) @@ -924,7 +924,7 @@ are for LPC24xx only. */ /* I2S Interface Controller (I2S) */ -#define I2S_BASE_ADDR 0xE0088000 +#define I2S_BASE_ADDR 0xE0088000 #define I2S_DAO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x00)) #define I2S_DAI (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x04)) #define I2S_TX_FIFO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x08)) @@ -938,7 +938,7 @@ are for LPC24xx only. */ /* General-purpose DMA Controller */ -#define DMA_BASE_ADDR 0xFFE04000 +#define DMA_BASE_ADDR 0xFFE04000 #define GPDMA_INT_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x000)) #define GPDMA_INT_TCSTAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x004)) #define GPDMA_INT_TCCLR (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x008)) @@ -970,8 +970,8 @@ are for LPC24xx only. */ /* USB Controller */ -#define USB_INT_BASE_ADDR 0xE01FC1C0 -#define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */ +#define USB_INT_BASE_ADDR 0xE01FC1C0 +#define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */ #define USB_INT_STAT (*(volatile unsigned long *)(USB_INT_BASE_ADDR + 0x00)) @@ -1027,7 +1027,7 @@ are for LPC24xx only. */ /* USB Host and OTG registers are for LPC24xx only */ /* USB Host Controller */ -#define USBHC_BASE_ADDR 0xFFE0C000 +#define USBHC_BASE_ADDR 0xFFE0C000 #define HC_REVISION (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x00)) #define HC_CONTROL (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x04)) #define HC_CMD_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x08)) @@ -1053,16 +1053,16 @@ are for LPC24xx only. */ #define HC_RH_PORT_STAT2 (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x58)) /* USB OTG Controller */ -#define USBOTG_BASE_ADDR 0xFFE0C100 +#define USBOTG_BASE_ADDR 0xFFE0C100 #define OTG_INT_STAT (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x00)) #define OTG_INT_EN (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x04)) #define OTG_INT_SET (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x08)) #define OTG_INT_CLR (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x0C)) -/* On LPC23xx, the name is USBPortSel, on LPC24xx, the name is OTG_STAT_CTRL */ +/* On LPC23xx, the name is USBPortSel, on LPC24xx, the name is OTG_STAT_CTRL */ #define OTG_STAT_CTRL (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10)) #define OTG_TIMER (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x14)) -#define USBOTG_I2C_BASE_ADDR 0xFFE0C300 +#define USBOTG_I2C_BASE_ADDR 0xFFE0C300 #define OTG_I2C_RX (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00)) #define OTG_I2C_TX (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00)) #define OTG_I2C_STS (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x04)) @@ -1070,20 +1070,20 @@ are for LPC24xx only. */ #define OTG_I2C_CLKHI (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x0C)) #define OTG_I2C_CLKLO (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x10)) -/* On LPC23xx, the names are USBClkCtrl and USBClkSt; on LPC24xx, the names are +/* On LPC23xx, the names are USBClkCtrl and USBClkSt; on LPC24xx, the names are OTG_CLK_CTRL and OTG_CLK_STAT respectively. */ -#define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0 +#define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0 #define OTG_CLK_CTRL (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04)) #define OTG_CLK_STAT (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08)) /* Note: below three register name convention is for LPC23xx USB device only, match -with the spec. update in USB Device Section. */ +with the spec. update in USB Device Section. */ #define USBPortSel (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10)) #define USBClkCtrl (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04)) #define USBClkSt (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08)) /* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */ -#define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */ +#define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */ #define MAC_MAC1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */ #define MAC_MAC2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */ #define MAC_IPGT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */ @@ -1139,7 +1139,7 @@ with the spec. update in USB Device Section. */ #define MAC_MODULEID (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */ /* LCD Controller registers */ -#define LCD_BASE_ADDR 0xFFE10000 /* AHB Peripheral # 4 */ +#define LCD_BASE_ADDR 0xFFE10000 /* AHB Peripheral # 4 */ #define LCD_CFG (*(volatile unsigned long *)(0xE01FC1B8)) #define LCD_TIMH (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x000)) #define LCD_TIMV (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x004)) @@ -1169,24 +1169,24 @@ with the spec. update in USB Device Section. */ struct rt_hw_register { - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; - unsigned long ORIG_r0; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; + unsigned long ORIG_r0; }; #ifdef __cplusplus diff --git a/libcpu/arm/lpc24xx/cpu.c b/libcpu/arm/lpc24xx/cpu.c index f3a61e16a3..071535180e 100644 --- a/libcpu/arm/lpc24xx/cpu.c +++ b/libcpu/arm/lpc24xx/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -30,9 +30,9 @@ void rt_hw_cpu_reset() */ void rt_hw_cpu_shutdown() { - rt_kprintf("shutdown...\n"); + rt_kprintf("shutdown...\n"); - while (1); + while (1); } /*@}*/ diff --git a/libcpu/arm/lpc24xx/interrupt.c b/libcpu/arm/lpc24xx/interrupt.c index a855de1e11..87bb86b879 100644 --- a/libcpu/arm/lpc24xx/interrupt.c +++ b/libcpu/arm/lpc24xx/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,10 +13,10 @@ #include #include "LPC24xx.h" -#define MAX_HANDLERS 32 +#define MAX_HANDLERS 32 /* exception and interrupt handler table */ -struct rt_irq_desc irq_desc[MAX_HANDLERS]; +struct rt_irq_desc irq_desc[MAX_HANDLERS]; extern rt_uint32_t rt_interrupt_nest; @@ -30,19 +30,19 @@ rt_uint32_t rt_thread_switch_interrupt_flag; /*@{*/ void rt_hw_interrupt_handler(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } void rt_hw_interrupt_init(void) { - register int i; + register int i; - rt_uint32_t *vect_addr, *vect_cntl; - - /* initialize VIC*/ - VICIntEnClr = 0xffffffff; - VICVectAddr = 0; - VICIntSelect = 0; + rt_uint32_t *vect_addr, *vect_cntl; + + /* initialize VIC*/ + VICIntEnClr = 0xffffffff; + VICVectAddr = 0; + VICIntSelect = 0; /* init exceptions table */ rt_memset(irq_desc, 0x00, sizeof(irq_desc)); @@ -50,27 +50,27 @@ void rt_hw_interrupt_init(void) { irq_desc[i].handler = rt_hw_interrupt_handler; - vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + i*4); - vect_cntl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + i*4); - *vect_addr = (rt_uint32_t)&irq_desc[i]; - *vect_cntl = 0xF; + vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + i*4); + vect_cntl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + i*4); + *vect_addr = (rt_uint32_t)&irq_desc[i]; + *vect_cntl = 0xF; } - - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; } void rt_hw_interrupt_mask(int vector) { - VICIntEnClr = (1 << vector); + VICIntEnClr = (1 << vector); } void rt_hw_interrupt_umask(int vector) { - VICIntEnable = (1 << vector); + VICIntEnable = (1 << vector); } /** @@ -82,22 +82,22 @@ void rt_hw_interrupt_umask(int vector) * * @return the old handler */ -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name) { - rt_isr_handler_t old_handler = RT_NULL; - - if(vector >= 0 && vector < MAX_HANDLERS) - { - old_handler = irq_desc[vector].handler; - if (handler != RT_NULL) - { - irq_desc[vector].handler = handler; - irq_desc[vector].param = param; - } - } - - return old_handler; + rt_isr_handler_t old_handler = RT_NULL; + + if(vector >= 0 && vector < MAX_HANDLERS) + { + old_handler = irq_desc[vector].handler; + if (handler != RT_NULL) + { + irq_desc[vector].handler = handler; + irq_desc[vector].param = param; + } + } + + return old_handler; } /*@}*/ diff --git a/libcpu/arm/lpc24xx/stack.c b/libcpu/arm/lpc24xx/stack.c index 0378a5f658..a7bce755b3 100644 --- a/libcpu/arm/lpc24xx/stack.c +++ b/libcpu/arm/lpc24xx/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/lpc24xx/trap.c b/libcpu/arm/lpc24xx/trap.c index d296bfdbfe..7ad7328a93 100644 --- a/libcpu/arm/lpc24xx/trap.c +++ b/libcpu/arm/lpc24xx/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -27,13 +27,13 @@ */ void rt_hw_show_register (struct rt_hw_register *regs) { - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); } /** @@ -48,8 +48,8 @@ void rt_hw_trap_udef(struct rt_hw_register *regs) { rt_kprintf("undefined instruction\n"); rt_hw_show_register(regs); - if (rt_thread_self() != RT_NULL) - rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); + if (rt_thread_self() != RT_NULL) + rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); rt_hw_cpu_shutdown(); } @@ -66,8 +66,8 @@ void rt_hw_trap_swi(struct rt_hw_register *regs) { rt_kprintf("software interrupt\n"); rt_hw_show_register(regs); - if (rt_thread_self() != RT_NULL) - rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); + if (rt_thread_self() != RT_NULL) + rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); rt_hw_cpu_shutdown(); } @@ -83,8 +83,8 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs) { rt_kprintf("prefetch abort\n"); rt_hw_show_register(regs); - if (rt_thread_self() != RT_NULL) - rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); + if (rt_thread_self() != RT_NULL) + rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); rt_hw_cpu_shutdown(); } @@ -97,11 +97,11 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs) * @note never invoke this function in application */ void rt_hw_trap_dabt(struct rt_hw_register *regs) -{ +{ rt_kprintf("Data Abort "); rt_hw_show_register(regs); - if (rt_thread_self() != RT_NULL) - rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); + if (rt_thread_self() != RT_NULL) + rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); rt_hw_cpu_shutdown(); } @@ -116,27 +116,27 @@ void rt_hw_trap_resv(struct rt_hw_register *regs) { rt_kprintf("not used\n"); rt_hw_show_register(regs); - if (rt_thread_self() != RT_NULL) - rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); + if (rt_thread_self() != RT_NULL) + rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); rt_hw_cpu_shutdown(); } extern rt_isr_handler_t isr_table[]; void rt_hw_trap_irq(void) { - int irqno; - struct rt_irq_desc* irq; - extern struct rt_irq_desc irq_desc[]; + int irqno; + struct rt_irq_desc* irq; + extern struct rt_irq_desc irq_desc[]; - irq = (struct rt_irq_desc*) VICVectAddr; - irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc); + irq = (struct rt_irq_desc*) VICVectAddr; + irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc); - /* invoke isr */ - irq->handler(irqno, irq->param); + /* invoke isr */ + irq->handler(irqno, irq->param); } void rt_hw_trap_fiq(void) -{ +{ rt_kprintf("fast interrupt request\n"); } diff --git a/libcpu/arm/realview-a8-vmm/armv7.h b/libcpu/arm/realview-a8-vmm/armv7.h index d22f72fa68..f284bb5255 100644 --- a/libcpu/arm/realview-a8-vmm/armv7.h +++ b/libcpu/arm/realview-a8-vmm/armv7.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,43 +12,43 @@ /* the exception stack without VFP registers */ struct rt_hw_exp_stack { - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; }; struct rt_hw_stack { - unsigned long cpsr; - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long lr; - unsigned long pc; + unsigned long cpsr; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long lr; + unsigned long pc; }; #define USERMODE 0x10 diff --git a/libcpu/arm/realview-a8-vmm/cp15.h b/libcpu/arm/realview-a8-vmm/cp15.h index 486f38200d..b18331af92 100644 --- a/libcpu/arm/realview-a8-vmm/cp15.h +++ b/libcpu/arm/realview-a8-vmm/cp15.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/realview-a8-vmm/cpu.c b/libcpu/arm/realview-a8-vmm/cpu.c index 2d78715011..5f82671c1b 100644 --- a/libcpu/arm/realview-a8-vmm/cpu.c +++ b/libcpu/arm/realview-a8-vmm/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,14 +20,14 @@ /** shutdown CPU */ void rt_hw_cpu_shutdown() { - rt_uint32_t level; - rt_kprintf("shutdown...\n"); + rt_uint32_t level; + rt_kprintf("shutdown...\n"); - level = rt_hw_interrupt_disable(); - while (level) - { - RT_ASSERT(0); - } + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } } /*@}*/ diff --git a/libcpu/arm/realview-a8-vmm/gic.c b/libcpu/arm/realview-a8-vmm/gic.c index 82f87b7e8f..962317821a 100644 --- a/libcpu/arm/realview-a8-vmm/gic.c +++ b/libcpu/arm/realview-a8-vmm/gic.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/realview-a8-vmm/gic.h b/libcpu/arm/realview-a8-vmm/gic.h index 8fcdf05f6f..7c781ad4d9 100644 --- a/libcpu/arm/realview-a8-vmm/gic.h +++ b/libcpu/arm/realview-a8-vmm/gic.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/realview-a8-vmm/interrupt.c b/libcpu/arm/realview-a8-vmm/interrupt.c index 5ef0bdc460..d57588644e 100644 --- a/libcpu/arm/realview-a8-vmm/interrupt.c +++ b/libcpu/arm/realview-a8-vmm/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/realview-a8-vmm/interrupt.h b/libcpu/arm/realview-a8-vmm/interrupt.h index 7461f94da0..90f392f407 100644 --- a/libcpu/arm/realview-a8-vmm/interrupt.h +++ b/libcpu/arm/realview-a8-vmm/interrupt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,28 +14,28 @@ #define INT_IRQ 0x00 #define INT_FIQ 0x01 -#define INTC_REVISION(hw_base) REG32((hw_base) + 0x0) -#define INTC_SYSCONFIG(hw_base) REG32((hw_base) + 0x10) -#define INTC_SYSSTATUS(hw_base) REG32((hw_base) + 0x14) -#define INTC_SIR_IRQ(hw_base) REG32((hw_base) + 0x40) -#define INTC_SIR_FIQ(hw_base) REG32((hw_base) + 0x44) -#define INTC_CONTROL(hw_base) REG32((hw_base) + 0x48) -#define INTC_PROTECTION(hw_base) REG32((hw_base) + 0x4c) -#define INTC_IDLE(hw_base) REG32((hw_base) + 0x50) -#define INTC_IRQ_PRIORITY(hw_base) REG32((hw_base) + 0x60) -#define INTC_FIQ_PRIORITY(hw_base) REG32((hw_base) + 0x64) -#define INTC_THRESHOLD(hw_base) REG32((hw_base) + 0x68) -#define INTC_SICR(hw_base) REG32((hw_base) + 0x6c) -#define INTC_SCR(hw_base, n) REG32((hw_base) + 0x70 + ((n) * 0x04)) -#define INTC_ITR(hw_base, n) REG32((hw_base) + 0x80 + ((n) * 0x20)) -#define INTC_MIR(hw_base, n) REG32((hw_base) + 0x84 + ((n) * 0x20)) -#define INTC_MIR_CLEAR(hw_base, n) REG32((hw_base) + 0x88 + ((n) * 0x20)) -#define INTC_MIR_SET(hw_base, n) REG32((hw_base) + 0x8c + ((n) * 0x20)) -#define INTC_ISR_SET(hw_base, n) REG32((hw_base) + 0x90 + ((n) * 0x20)) -#define INTC_ISR_CLEAR(hw_base, n) REG32((hw_base) + 0x94 + ((n) * 0x20)) +#define INTC_REVISION(hw_base) REG32((hw_base) + 0x0) +#define INTC_SYSCONFIG(hw_base) REG32((hw_base) + 0x10) +#define INTC_SYSSTATUS(hw_base) REG32((hw_base) + 0x14) +#define INTC_SIR_IRQ(hw_base) REG32((hw_base) + 0x40) +#define INTC_SIR_FIQ(hw_base) REG32((hw_base) + 0x44) +#define INTC_CONTROL(hw_base) REG32((hw_base) + 0x48) +#define INTC_PROTECTION(hw_base) REG32((hw_base) + 0x4c) +#define INTC_IDLE(hw_base) REG32((hw_base) + 0x50) +#define INTC_IRQ_PRIORITY(hw_base) REG32((hw_base) + 0x60) +#define INTC_FIQ_PRIORITY(hw_base) REG32((hw_base) + 0x64) +#define INTC_THRESHOLD(hw_base) REG32((hw_base) + 0x68) +#define INTC_SICR(hw_base) REG32((hw_base) + 0x6c) +#define INTC_SCR(hw_base, n) REG32((hw_base) + 0x70 + ((n) * 0x04)) +#define INTC_ITR(hw_base, n) REG32((hw_base) + 0x80 + ((n) * 0x20)) +#define INTC_MIR(hw_base, n) REG32((hw_base) + 0x84 + ((n) * 0x20)) +#define INTC_MIR_CLEAR(hw_base, n) REG32((hw_base) + 0x88 + ((n) * 0x20)) +#define INTC_MIR_SET(hw_base, n) REG32((hw_base) + 0x8c + ((n) * 0x20)) +#define INTC_ISR_SET(hw_base, n) REG32((hw_base) + 0x90 + ((n) * 0x20)) +#define INTC_ISR_CLEAR(hw_base, n) REG32((hw_base) + 0x94 + ((n) * 0x20)) #define INTC_PENDING_IRQ(hw_base, n) REG32((hw_base) + 0x98 + ((n) * 0x20)) #define INTC_PENDING_FIQ(hw_base, n) REG32((hw_base) + 0x9c + ((n) * 0x20)) -#define INTC_ILR(hw_base, n) REG32((hw_base) + 0x100 + ((n) * 0x04)) +#define INTC_ILR(hw_base, n) REG32((hw_base) + 0x100 + ((n) * 0x04)) void rt_hw_interrupt_control(int vector, int priority, int route); int rt_hw_interrupt_get_active(int fiq_irq); diff --git a/libcpu/arm/realview-a8-vmm/mmu.c b/libcpu/arm/realview-a8-vmm/mmu.c index 58acdd8145..f4d6068099 100644 --- a/libcpu/arm/realview-a8-vmm/mmu.c +++ b/libcpu/arm/realview-a8-vmm/mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/realview-a8-vmm/pmu.c b/libcpu/arm/realview-a8-vmm/pmu.c index 8ffc1dede6..2b9165cc8b 100644 --- a/libcpu/arm/realview-a8-vmm/pmu.c +++ b/libcpu/arm/realview-a8-vmm/pmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/realview-a8-vmm/pmu.h b/libcpu/arm/realview-a8-vmm/pmu.h index fb8390133d..64a74b5d39 100644 --- a/libcpu/arm/realview-a8-vmm/pmu.h +++ b/libcpu/arm/realview-a8-vmm/pmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/realview-a8-vmm/stack.c b/libcpu/arm/realview-a8-vmm/stack.c index 619a16c446..8cf73ac05c 100644 --- a/libcpu/arm/realview-a8-vmm/stack.c +++ b/libcpu/arm/realview-a8-vmm/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/realview-a8-vmm/trap.c b/libcpu/arm/realview-a8-vmm/trap.c index 4a522f5126..c6ca45aee7 100644 --- a/libcpu/arm/realview-a8-vmm/trap.c +++ b/libcpu/arm/realview-a8-vmm/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -131,7 +131,7 @@ void rt_hw_trap_resv(struct rt_hw_exp_stack *regs) rt_hw_cpu_shutdown(); } -#define GIC_ACK_INTID_MASK 0x000003ff +#define GIC_ACK_INTID_MASK 0x000003ff void rt_hw_trap_irq(void) { diff --git a/libcpu/arm/s3c24x0/cpu.c b/libcpu/arm/s3c24x0/cpu.c index 4d3bf3c1ab..ac4037c7b8 100644 --- a/libcpu/arm/s3c24x0/cpu.c +++ b/libcpu/arm/s3c24x0/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,76 +17,76 @@ */ /*@{*/ -#define ICACHE_MASK (rt_uint32_t)(1 << 12) -#define DCACHE_MASK (rt_uint32_t)(1 << 2) +#define ICACHE_MASK (rt_uint32_t)(1 << 12) +#define DCACHE_MASK (rt_uint32_t)(1 << 2) #ifdef __GNUC__ rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - return i; + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "orr r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "orr r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } rt_inline void cache_disable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "bic r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "bic r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } #endif #ifdef __CC_ARM rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - __asm - { - mrc p15, 0, i, c1, c0, 0 - } + __asm + { + mrc p15, 0, i, c1, c0, 0 + } - return i; + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } rt_inline void cache_disable(rt_uint32_t bit) { - rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } #endif @@ -96,7 +96,7 @@ rt_inline void cache_disable(rt_uint32_t bit) */ void rt_hw_cpu_icache_enable() { - cache_enable(ICACHE_MASK); + cache_enable(ICACHE_MASK); } /** @@ -105,7 +105,7 @@ void rt_hw_cpu_icache_enable() */ void rt_hw_cpu_icache_disable() { - cache_disable(ICACHE_MASK); + cache_disable(ICACHE_MASK); } /** @@ -114,7 +114,7 @@ void rt_hw_cpu_icache_disable() */ rt_base_t rt_hw_cpu_icache_status() { - return (cp15_rd() & ICACHE_MASK); + return (cp15_rd() & ICACHE_MASK); } /** @@ -123,7 +123,7 @@ rt_base_t rt_hw_cpu_icache_status() */ void rt_hw_cpu_dcache_enable() { - cache_enable(DCACHE_MASK); + cache_enable(DCACHE_MASK); } /** @@ -132,7 +132,7 @@ void rt_hw_cpu_dcache_enable() */ void rt_hw_cpu_dcache_disable() { - cache_disable(DCACHE_MASK); + cache_disable(DCACHE_MASK); } /** @@ -141,7 +141,7 @@ void rt_hw_cpu_dcache_disable() */ rt_base_t rt_hw_cpu_dcache_status() { - return (cp15_rd() & DCACHE_MASK); + return (cp15_rd() & DCACHE_MASK); } /** @@ -150,21 +150,21 @@ rt_base_t rt_hw_cpu_dcache_status() */ void rt_hw_cpu_reset() { - /* Disable all interrupt except the WDT */ - INTMSK = (~((rt_uint32_t)1 << INTWDT)); + /* Disable all interrupt except the WDT */ + INTMSK = (~((rt_uint32_t)1 << INTWDT)); - /* Disable watchdog */ - WTCON = 0x0000; + /* Disable watchdog */ + WTCON = 0x0000; - /* Initialize watchdog timer count register */ - WTCNT = 0x0001; + /* Initialize watchdog timer count register */ + WTCNT = 0x0001; - /* Enable watchdog timer; assert reset at timer timeout */ - WTCON = 0x0021; + /* Enable watchdog timer; assert reset at timer timeout */ + WTCON = 0x0021; - while(1); /* loop forever and wait for reset to happen */ + while(1); /* loop forever and wait for reset to happen */ - /* NEVER REACHED */ + /* NEVER REACHED */ } /** @@ -173,14 +173,14 @@ void rt_hw_cpu_reset() */ void rt_hw_cpu_shutdown() { - rt_uint32_t level; - rt_kprintf("shutdown...\n"); - - level = rt_hw_interrupt_disable(); - while (level) - { - RT_ASSERT(0); - } + rt_uint32_t level; + rt_kprintf("shutdown...\n"); + + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } } /*@}*/ diff --git a/libcpu/arm/s3c24x0/interrupt.c b/libcpu/arm/s3c24x0/interrupt.c index 8c7aebeb25..c985fc7c86 100644 --- a/libcpu/arm/s3c24x0/interrupt.c +++ b/libcpu/arm/s3c24x0/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,7 +13,7 @@ #include #include "s3c24x0.h" -#define MAX_HANDLERS 32 +#define MAX_HANDLERS 32 extern rt_uint32_t rt_interrupt_nest; @@ -29,7 +29,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag; static void rt_hw_interrupt_handle(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } /** @@ -77,7 +77,7 @@ void rt_hw_interrupt_init(void) */ void rt_hw_interrupt_mask(int vector) { - INTMSK |= 1 << vector; + INTMSK |= 1 << vector; } /** @@ -86,15 +86,15 @@ void rt_hw_interrupt_mask(int vector) */ void rt_hw_interrupt_umask(int vector) { - if (vector == INTNOTUSED6) - { - rt_kprintf("Interrupt vec %d is not used!\n", vector); - // while(1); - } - else if (vector == INTGLOBAL) - INTMSK = 0x0; - else - INTMSK &= ~(1 << vector); + if (vector == INTNOTUSED6) + { + rt_kprintf("Interrupt vec %d is not used!\n", vector); + // while(1); + } + else if (vector == INTGLOBAL) + INTMSK = 0x0; + else + INTMSK &= ~(1 << vector); } /** @@ -115,9 +115,9 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, if (handler != RT_NULL) { #ifdef RT_USING_INTERRUPT_INFO - rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); + rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); #endif /* RT_USING_INTERRUPT_INFO */ - isr_table[vector].handler = handler; + isr_table[vector].handler = handler; isr_table[vector].param = param; } } diff --git a/libcpu/arm/s3c24x0/mmu.c b/libcpu/arm/s3c24x0/mmu.c index dc993ec9a3..4e5ef8d3c6 100644 --- a/libcpu/arm/s3c24x0/mmu.c +++ b/libcpu/arm/s3c24x0/mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,158 +12,158 @@ #include #include "s3c24x0.h" -#define _MMUTT_STARTADDRESS 0x33FF0000 +#define _MMUTT_STARTADDRESS 0x33FF0000 -#define DESC_SEC (0x2|(1<<4)) -#define CB (3<<2) //cache_on, write_back -#define CNB (2<<2) //cache_on, write_through -#define NCB (1<<2) //cache_off,WR_BUF on -#define NCNB (0<<2) //cache_off,WR_BUF off -#define AP_RW (3<<10) //supervisor=RW, user=RW -#define AP_RO (2<<10) //supervisor=RW, user=RO +#define DESC_SEC (0x2|(1<<4)) +#define CB (3<<2) //cache_on, write_back +#define CNB (2<<2) //cache_on, write_through +#define NCB (1<<2) //cache_off,WR_BUF on +#define NCNB (0<<2) //cache_off,WR_BUF off +#define AP_RW (3<<10) //supervisor=RW, user=RW +#define AP_RO (2<<10) //supervisor=RW, user=RO -#define DOMAIN_FAULT (0x0) -#define DOMAIN_CHK (0x1) -#define DOMAIN_NOTCHK (0x3) -#define DOMAIN0 (0x0<<5) -#define DOMAIN1 (0x1<<5) +#define DOMAIN_FAULT (0x0) +#define DOMAIN_CHK (0x1) +#define DOMAIN_NOTCHK (0x3) +#define DOMAIN0 (0x0<<5) +#define DOMAIN1 (0x1<<5) -#define DOMAIN0_ATTR (DOMAIN_CHK<<0) -#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) +#define DOMAIN0_ATTR (DOMAIN_CHK<<0) +#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) -#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) -#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) -#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) -#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) +#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) +#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) +#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) +#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) #ifdef __GNUC__ void mmu_setttbase(register rt_uint32_t i) { - asm volatile ("mcr p15, 0, %0, c2, c0, 0": :"r" (i)); + asm volatile ("mcr p15, 0, %0, c2, c0, 0": :"r" (i)); } void mmu_set_domain(register rt_uint32_t i) { - asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); + asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); } void mmu_enable() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= 0x1; + i |= 0x1; - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~0x1; + i &= ~0x1; - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_icache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 12); + i |= (1 << 12); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_dcache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 2); + i |= (1 << 2); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_icache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 12); + i &= ~(1 << 12); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_dcache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 2); + i &= ~(1 << 2); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_alignfault() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 1); + i |= (1 << 1); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_alignfault() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 1); + i &= ~(1 << 1); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_clean_invalidated_cache_index(int index) { - asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); + asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); } void mmu_invalidate_tlb() { - asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); } void mmu_invalidate_icache() { - asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); } #endif @@ -320,71 +320,71 @@ void mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr) nSec=(vaddrEnd>>20)-(vaddrStart>>20); for(i=0;i<=nSec;i++) { - *pTT = attr |(((paddrStart>>20)+i)<<20); - pTT++; + *pTT = attr |(((paddrStart>>20)+i)<<20); + pTT++; } } void rt_hw_mmu_init(void) { - int i,j; - //========================== IMPORTANT NOTE ========================= - //The current stack and code area can't be re-mapped in this routine. - //If you want memory map mapped freely, your own sophiscated mmu - //initialization code is needed. - //=================================================================== - - mmu_disable_dcache(); - mmu_disable_icache(); - - //If write-back is used,the DCache should be cleared. - for(i=0;i<64;i++) - for(j=0;j<8;j++) - mmu_clean_invalidated_cache_index((i<<26)|(j<<5)); - - mmu_invalidate_icache(); - - //To complete mmu_Init() fast, Icache may be turned on here. - mmu_enable_icache(); - - mmu_disable(); - mmu_invalidate_tlb(); - - //mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr); - mmu_setmtt(0x00000000,0x07f00000,0x00000000,RW_CNB); //bank0 - mmu_setmtt(0x00000000,0x03f00000,(int)0x30000000,RW_CB); //bank0 - mmu_setmtt(0x04000000,0x07f00000,0,RW_NCNB); //bank0 - mmu_setmtt(0x08000000,0x0ff00000,0x08000000,RW_CNB); //bank1 - mmu_setmtt(0x10000000,0x17f00000,0x10000000,RW_NCNB); //bank2 - mmu_setmtt(0x18000000,0x1ff00000,0x18000000,RW_NCNB); //bank3 - //mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_CB); //bank4 - mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_NCNB); //bank4 for DM9000 - mmu_setmtt(0x28000000,0x2ff00000,0x28000000,RW_NCNB); //bank5 - //30f00000->30100000, 31000000->30200000 - mmu_setmtt(0x30000000,0x30100000,0x30000000,RW_CB); //bank6-1 - mmu_setmtt(0x30200000,0x33e00000,0x30200000,RW_CB); //bank6-2 - - mmu_setmtt(0x33f00000,0x34000000,0x33f00000,RW_NCNB); //bank6-3 - mmu_setmtt(0x38000000,0x3ff00000,0x38000000,RW_NCNB); //bank7 - - mmu_setmtt(0x40000000,0x47f00000,0x40000000,RW_NCNB); //SFR - mmu_setmtt(0x48000000,0x5af00000,0x48000000,RW_NCNB); //SFR - mmu_setmtt(0x5b000000,0x5b000000,0x5b000000,RW_NCNB); //SFR - mmu_setmtt(0x5b100000,0xfff00000,0x5b100000,RW_FAULT);//not used - mmu_setmtt(0x60000000,0x67f00000,0x60000000,RW_NCNB); //SFR - - mmu_setttbase(_MMUTT_STARTADDRESS); - - /* DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked) */ - mmu_set_domain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR); - - mmu_enable_alignfault(); - - mmu_enable(); - - /* ICache enable */ - mmu_enable_icache(); - /* DCache should be turned on after mmu is turned on. */ - mmu_enable_dcache(); + int i,j; + //========================== IMPORTANT NOTE ========================= + //The current stack and code area can't be re-mapped in this routine. + //If you want memory map mapped freely, your own sophiscated mmu + //initialization code is needed. + //=================================================================== + + mmu_disable_dcache(); + mmu_disable_icache(); + + //If write-back is used,the DCache should be cleared. + for(i=0;i<64;i++) + for(j=0;j<8;j++) + mmu_clean_invalidated_cache_index((i<<26)|(j<<5)); + + mmu_invalidate_icache(); + + //To complete mmu_Init() fast, Icache may be turned on here. + mmu_enable_icache(); + + mmu_disable(); + mmu_invalidate_tlb(); + + //mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr); + mmu_setmtt(0x00000000,0x07f00000,0x00000000,RW_CNB); //bank0 + mmu_setmtt(0x00000000,0x03f00000,(int)0x30000000,RW_CB); //bank0 + mmu_setmtt(0x04000000,0x07f00000,0,RW_NCNB); //bank0 + mmu_setmtt(0x08000000,0x0ff00000,0x08000000,RW_CNB); //bank1 + mmu_setmtt(0x10000000,0x17f00000,0x10000000,RW_NCNB); //bank2 + mmu_setmtt(0x18000000,0x1ff00000,0x18000000,RW_NCNB); //bank3 + //mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_CB); //bank4 + mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_NCNB); //bank4 for DM9000 + mmu_setmtt(0x28000000,0x2ff00000,0x28000000,RW_NCNB); //bank5 + //30f00000->30100000, 31000000->30200000 + mmu_setmtt(0x30000000,0x30100000,0x30000000,RW_CB); //bank6-1 + mmu_setmtt(0x30200000,0x33e00000,0x30200000,RW_CB); //bank6-2 + + mmu_setmtt(0x33f00000,0x34000000,0x33f00000,RW_NCNB); //bank6-3 + mmu_setmtt(0x38000000,0x3ff00000,0x38000000,RW_NCNB); //bank7 + + mmu_setmtt(0x40000000,0x47f00000,0x40000000,RW_NCNB); //SFR + mmu_setmtt(0x48000000,0x5af00000,0x48000000,RW_NCNB); //SFR + mmu_setmtt(0x5b000000,0x5b000000,0x5b000000,RW_NCNB); //SFR + mmu_setmtt(0x5b100000,0xfff00000,0x5b100000,RW_FAULT);//not used + mmu_setmtt(0x60000000,0x67f00000,0x60000000,RW_NCNB); //SFR + + mmu_setttbase(_MMUTT_STARTADDRESS); + + /* DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked) */ + mmu_set_domain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR); + + mmu_enable_alignfault(); + + mmu_enable(); + + /* ICache enable */ + mmu_enable_icache(); + /* DCache should be turned on after mmu is turned on. */ + mmu_enable_dcache(); } diff --git a/libcpu/arm/s3c24x0/rtc.c b/libcpu/arm/s3c24x0/rtc.c index d0c80bce6b..653bb09f77 100644 --- a/libcpu/arm/s3c24x0/rtc.c +++ b/libcpu/arm/s3c24x0/rtc.c @@ -1,14 +1,14 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2009-04-26 yi.qiu first version - * 2010-03-18 Gary Lee add functions such as GregorianDay - * and rtc_time_to_tm - * 2009-03-20 yi.qiu clean up + * 2009-04-26 yi.qiu first version + * 2010-03-18 Gary Lee add functions such as GregorianDay + * and rtc_time_to_tm + * 2009-03-20 yi.qiu clean up */ #include @@ -17,50 +17,50 @@ // #define RTC_DEBUG -#define RTC_ENABLE RTCCON |= 0x01; /*RTC read and write enable */ -#define RTC_DISABLE RTCCON &= ~0x01; /* RTC read and write disable */ -#define BCD2BIN(n) (((((n) >> 4) & 0x0F) * 10) + ((n) & 0x0F)) -#define BIN2BCD(n) ((((n) / 10) << 4) | ((n) % 10)) +#define RTC_ENABLE RTCCON |= 0x01; /*RTC read and write enable */ +#define RTC_DISABLE RTCCON &= ~0x01; /* RTC read and write disable */ +#define BCD2BIN(n) (((((n) >> 4) & 0x0F) * 10) + ((n) & 0x0F)) +#define BIN2BCD(n) ((((n) / 10) << 4) | ((n) % 10)) /** * This function get rtc time */ void rt_hw_rtc_get(struct tm *ti) { - rt_uint8_t sec, min, hour, mday, wday, mon, year; - - /* enable access to RTC registers */ - RTCCON |= RTC_ENABLE; - - /* read RTC registers */ - do - { - sec = BCDSEC; - min = BCDMIN; - hour = BCDHOUR; - mday = BCDDATE; - wday = BCDDAY; - mon = BCDMON; - year = BCDYEAR; + rt_uint8_t sec, min, hour, mday, wday, mon, year; + + /* enable access to RTC registers */ + RTCCON |= RTC_ENABLE; + + /* read RTC registers */ + do + { + sec = BCDSEC; + min = BCDMIN; + hour = BCDHOUR; + mday = BCDDATE; + wday = BCDDAY; + mon = BCDMON; + year = BCDYEAR; } while (sec != BCDSEC); #ifdef RTC_DEBUG - rt_kprintf("sec:%x min:%x hour:%x mday:%x wday:%x mon:%x year:%x\n", - sec, min, hour, mday, wday, mon, year); + rt_kprintf("sec:%x min:%x hour:%x mday:%x wday:%x mon:%x year:%x\n", + sec, min, hour, mday, wday, mon, year); #endif - /* disable access to RTC registers */ - RTC_DISABLE - - ti->tm_sec = BCD2BIN(sec & 0x7F); - ti->tm_min = BCD2BIN(min & 0x7F); - ti->tm_hour = BCD2BIN(hour & 0x3F); - ti->tm_mday = BCD2BIN(mday & 0x3F); - ti->tm_mon = BCD2BIN(mon & 0x1F); - ti->tm_year = BCD2BIN(year); - ti->tm_wday = BCD2BIN(wday & 0x07); - ti->tm_yday = 0; - ti->tm_isdst = 0; + /* disable access to RTC registers */ + RTC_DISABLE + + ti->tm_sec = BCD2BIN(sec & 0x7F); + ti->tm_min = BCD2BIN(min & 0x7F); + ti->tm_hour = BCD2BIN(hour & 0x3F); + ti->tm_mday = BCD2BIN(mday & 0x3F); + ti->tm_mon = BCD2BIN(mon & 0x1F); + ti->tm_year = BCD2BIN(year); + ti->tm_wday = BCD2BIN(wday & 0x07); + ti->tm_yday = 0; + ti->tm_isdst = 0; } /** @@ -68,32 +68,32 @@ void rt_hw_rtc_get(struct tm *ti) */ void rt_hw_rtc_set(struct tm *ti) { - rt_uint8_t sec, min, hour, mday, wday, mon, year; - - year = BIN2BCD(ti->tm_year); - mon = BIN2BCD(ti->tm_mon); - wday = BIN2BCD(ti->tm_wday); - mday = BIN2BCD(ti->tm_mday); - hour = BIN2BCD(ti->tm_hour); - min = BIN2BCD(ti->tm_min); - sec = BIN2BCD(ti->tm_sec); - - /* enable access to RTC registers */ - RTC_ENABLE - - do{ - /* write RTC registers */ - BCDSEC = sec; - BCDMIN = min; - BCDHOUR = hour; - BCDDATE = mday; - BCDDAY = wday; - BCDMON = mon; - BCDYEAR = year; - }while (sec != BCDSEC); - - /* disable access to RTC registers */ - RTC_DISABLE + rt_uint8_t sec, min, hour, mday, wday, mon, year; + + year = BIN2BCD(ti->tm_year); + mon = BIN2BCD(ti->tm_mon); + wday = BIN2BCD(ti->tm_wday); + mday = BIN2BCD(ti->tm_mday); + hour = BIN2BCD(ti->tm_hour); + min = BIN2BCD(ti->tm_min); + sec = BIN2BCD(ti->tm_sec); + + /* enable access to RTC registers */ + RTC_ENABLE + + do{ + /* write RTC registers */ + BCDSEC = sec; + BCDMIN = min; + BCDHOUR = hour; + BCDDATE = mday; + BCDDAY = wday; + BCDMON = mon; + BCDYEAR = year; + }while (sec != BCDSEC); + + /* disable access to RTC registers */ + RTC_DISABLE } /** @@ -101,85 +101,85 @@ void rt_hw_rtc_set(struct tm *ti) */ void rt_hw_rtc_reset (void) { - RTCCON = (RTCCON & ~0x06) | 0x08; - RTCCON &= ~(0x08|0x01); + RTCCON = (RTCCON & ~0x06) | 0x08; + RTCCON &= ~(0x08|0x01); } static struct rt_device rtc; static rt_err_t rtc_open(rt_device_t dev, rt_uint16_t oflag) { - RTC_ENABLE - return RT_EOK; + RTC_ENABLE + return RT_EOK; } static rt_err_t rtc_close(rt_device_t dev) { - RTC_DISABLE - return RT_EOK; + RTC_DISABLE + return RT_EOK; } static rt_size_t rtc_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - return RT_EOK; + return RT_EOK; } static rt_err_t rtc_control(rt_device_t dev, int cmd, void *args) { - struct tm tm, *tm_ptr; + struct tm tm, *tm_ptr; time_t *time; - RT_ASSERT(dev != RT_NULL); - - time = (time_t *)args; - switch (cmd) - { - case RT_DEVICE_CTRL_RTC_GET_TIME: - /* read device */ - rt_hw_rtc_get(&tm); - *((rt_time_t *)args) = mktime(&tm); - break; - - case RT_DEVICE_CTRL_RTC_SET_TIME: - tm_ptr = localtime(time); - /* write device */ - rt_hw_rtc_set(tm_ptr); - break; - } - - return RT_EOK; + RT_ASSERT(dev != RT_NULL); + + time = (time_t *)args; + switch (cmd) + { + case RT_DEVICE_CTRL_RTC_GET_TIME: + /* read device */ + rt_hw_rtc_get(&tm); + *((rt_time_t *)args) = mktime(&tm); + break; + + case RT_DEVICE_CTRL_RTC_SET_TIME: + tm_ptr = localtime(time); + /* write device */ + rt_hw_rtc_set(tm_ptr); + break; + } + + return RT_EOK; } void rt_hw_rtc_init(void) { - rtc.type = RT_Device_Class_RTC; - - /* register rtc device */ - rtc.init = RT_NULL; - rtc.open = rtc_open; - rtc.close = rtc_close; - rtc.read = rtc_read; - rtc.write = RT_NULL; - rtc.control = rtc_control; - - /* no private */ - rtc.user_data = RT_NULL; - - rt_device_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR); + rtc.type = RT_Device_Class_RTC; + + /* register rtc device */ + rtc.init = RT_NULL; + rtc.open = rtc_open; + rtc.close = rtc_close; + rtc.read = rtc_read; + rtc.write = RT_NULL; + rtc.control = rtc_control; + + /* no private */ + rtc.user_data = RT_NULL; + + rt_device_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR); } #ifdef RT_USING_FINSH #include void list_date() { - time_t time; - rt_device_t device; + time_t time; + rt_device_t device; - device = rt_device_find("rtc"); - if (device != RT_NULL) - { - rt_device_control(device, RT_DEVICE_CTRL_RTC_GET_TIME, &time); + device = rt_device_find("rtc"); + if (device != RT_NULL) + { + rt_device_control(device, RT_DEVICE_CTRL_RTC_GET_TIME, &time); - rt_kprintf("%d, %s\n", time, ctime(&time)); - } + rt_kprintf("%d, %s\n", time, ctime(&time)); + } } FINSH_FUNCTION_EXPORT(list_date, list date); #endif diff --git a/libcpu/arm/s3c24x0/rtc.h b/libcpu/arm/s3c24x0/rtc.h index aafa714b0e..78219325a5 100644 --- a/libcpu/arm/s3c24x0/rtc.h +++ b/libcpu/arm/s3c24x0/rtc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/s3c24x0/s3c24x0.h b/libcpu/arm/s3c24x0/s3c24x0.h index 03749c5227..75e1eb0119 100644 --- a/libcpu/arm/s3c24x0/s3c24x0.h +++ b/libcpu/arm/s3c24x0/s3c24x0.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,7 +22,7 @@ extern "C" { */ /*@{*/ -// Memory control +// Memory control #define BWSCON (*(volatile unsigned *)0x48000000) //Bus width & wait status #define BANKCON0 (*(volatile unsigned *)0x48000004) //Boot ROM control #define BANKCON1 (*(volatile unsigned *)0x48000008) //BANK1 control @@ -101,7 +101,7 @@ extern "C" { #define CLKCON (*(volatile unsigned *)0x4c00000c) //Clock generator control #define CLKSLOW (*(volatile unsigned *)0x4c000010) //Slow clock control #define CLKDIVN (*(volatile unsigned *)0x4c000014) //Clock divider control -#define CAMDIVN (*(volatile unsigned *)0x4c000018) //USB, CAM Clock divider control +#define CAMDIVN (*(volatile unsigned *)0x4c000018) //USB, CAM Clock divider control // LCD CONTROLLER @@ -114,7 +114,7 @@ extern "C" { #define LCDSADDR2 (*(volatile unsigned *)0x4d000018) //STN/TFT Frame buffer start address 2 #define LCDSADDR3 (*(volatile unsigned *)0x4d00001c) //STN/TFT Virtual screen address set #define REDLUT (*(volatile unsigned *)0x4d000020) //STN Red lookup table -#define GREENLUT (*(volatile unsigned *)0x4d000024) //STN Green lookup table +#define GREENLUT (*(volatile unsigned *)0x4d000024) //STN Green lookup table #define BLUELUT (*(volatile unsigned *)0x4d000028) //STN Blue lookup table #define DITHMODE (*(volatile unsigned *)0x4d00004c) //STN Dithering mode #define TPAL (*(volatile unsigned *)0x4d000050) //TFT Temporary palette @@ -223,10 +223,10 @@ extern "C" { #define TCNTO4 (*(volatile unsigned *)0x51000040) //Timer count observation 4 // Added for 2440 -#define FLTOUT (*(volatile unsigned *)0x560000c0) // Filter output(Read only) -#define DSC0 (*(volatile unsigned *)0x560000c4) // Strength control register 0 -#define DSC1 (*(volatile unsigned *)0x560000c8) // Strength control register 1 -#define MSLCON (*(volatile unsigned *)0x560000cc) // Memory sleep control register +#define FLTOUT (*(volatile unsigned *)0x560000c0) // Filter output(Read only) +#define DSC0 (*(volatile unsigned *)0x560000c4) // Strength control register 0 +#define DSC1 (*(volatile unsigned *)0x560000c8) // Strength control register 1 +#define MSLCON (*(volatile unsigned *)0x560000cc) // Memory sleep control register // USB DEVICE @@ -388,9 +388,9 @@ extern "C" { #define GPHDAT (*(volatile unsigned *)0x56000074) //Port H data #define GPHUP (*(volatile unsigned *)0x56000078) //Pull-up control H -#define GPJCON (*(volatile unsigned *)0x560000d0) //Port J control -#define GPJDAT (*(volatile unsigned *)0x560000d4) //Port J data -#define GPJUP (*(volatile unsigned *)0x560000d8) //Pull-up control J +#define GPJCON (*(volatile unsigned *)0x560000d0) //Port J control +#define GPJDAT (*(volatile unsigned *)0x560000d4) //Port J data +#define GPJUP (*(volatile unsigned *)0x560000d8) //Pull-up control J #define MISCCR (*(volatile unsigned *)0x56000080) //Miscellaneous control #define DCLKCON (*(volatile unsigned *)0x56000084) //DCLK0/1 control @@ -495,7 +495,7 @@ extern "C" { #ifdef __BIG_ENDIAN /* edited for 2440A */ #define SDIDAT (*(volatile unsigned *)0x5a00004c) #else // Little Endian -#define SDIDAT (*(volatile unsigned *)0x5a000040) +#define SDIDAT (*(volatile unsigned *)0x5a000040) #endif //SD Interface // PENDING BIT @@ -562,40 +562,40 @@ extern "C" { #define ClearPending(bit) {SRCPND = bit;INTPND = bit;INTPND;} //Wait until INTPND is changed for the case that the ISR is very short. -#define INTGLOBAL 32 +#define INTGLOBAL 32 /*****************************/ /* CPU Mode */ /*****************************/ -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define ABORTMODE 0x17 -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define ABORTMODE 0x17 +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 struct rt_hw_register { - rt_uint32_t r0; - rt_uint32_t r1; - rt_uint32_t r2; - rt_uint32_t r3; - rt_uint32_t r4; - rt_uint32_t r5; - rt_uint32_t r6; - rt_uint32_t r7; - rt_uint32_t r8; - rt_uint32_t r9; - rt_uint32_t r10; - rt_uint32_t fp; - rt_uint32_t ip; - rt_uint32_t sp; - rt_uint32_t lr; - rt_uint32_t pc; - rt_uint32_t cpsr; - rt_uint32_t ORIG_r0; + rt_uint32_t r0; + rt_uint32_t r1; + rt_uint32_t r2; + rt_uint32_t r3; + rt_uint32_t r4; + rt_uint32_t r5; + rt_uint32_t r6; + rt_uint32_t r7; + rt_uint32_t r8; + rt_uint32_t r9; + rt_uint32_t r10; + rt_uint32_t fp; + rt_uint32_t ip; + rt_uint32_t sp; + rt_uint32_t lr; + rt_uint32_t pc; + rt_uint32_t cpsr; + rt_uint32_t ORIG_r0; }; #ifdef __cplusplus diff --git a/libcpu/arm/s3c24x0/stack.c b/libcpu/arm/s3c24x0/stack.c index 82607c3590..99938e2317 100644 --- a/libcpu/arm/s3c24x0/stack.c +++ b/libcpu/arm/s3c24x0/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/s3c24x0/system_clock.c b/libcpu/arm/s3c24x0/system_clock.c index 833b193cce..235c5e5e5c 100644 --- a/libcpu/arm/s3c24x0/system_clock.c +++ b/libcpu/arm/s3c24x0/system_clock.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -11,21 +11,21 @@ #include #include "s3c24x0.h" -#define CONFIG_SYS_CLK_FREQ 12000000 // Fin = 12.00MHz +#define CONFIG_SYS_CLK_FREQ 12000000 // Fin = 12.00MHz #if CONFIG_SYS_CLK_FREQ == 12000000 - /* MPLL=2*12*100/6=400MHz */ - #define MPL_MIDV 92 /* m=MPL_MDIV+8=100 */ - #define MPL_PDIV 4 /* p=MPL_PDIV+2=6 */ - #define MPL_SDIV 0 /* s=MPL_SDIV=0 */ - /* UPLL=12*64/8=96MHz */ - #define UPL_MDIV 56 /* m=UPL_MDIV+8=64 */ - #define UPL_PDIV 2 /* p=UPL_PDIV+2=4 */ - #define UPL_SDIV 1 /* s=UPL_SDIV=1 */ - /* System clock divider FCLK:HCLK:PCLK=1:4:8 */ - #define DIVN_UPLL 0x1 /* UCLK = UPLL clock / 2 */ - #define HDIVN 0x2 /* HCLK = FCLK / 4 */ - #define PDIVN 0x1 /* PCLK = HCLK / 2 */ + /* MPLL=2*12*100/6=400MHz */ + #define MPL_MIDV 92 /* m=MPL_MDIV+8=100 */ + #define MPL_PDIV 4 /* p=MPL_PDIV+2=6 */ + #define MPL_SDIV 0 /* s=MPL_SDIV=0 */ + /* UPLL=12*64/8=96MHz */ + #define UPL_MDIV 56 /* m=UPL_MDIV+8=64 */ + #define UPL_PDIV 2 /* p=UPL_PDIV+2=4 */ + #define UPL_SDIV 1 /* s=UPL_SDIV=1 */ + /* System clock divider FCLK:HCLK:PCLK=1:4:8 */ + #define DIVN_UPLL 0x1 /* UCLK = UPLL clock / 2 */ + #define HDIVN 0x2 /* HCLK = FCLK / 4 */ + #define PDIVN 0x1 /* PCLK = HCLK / 2 */ #endif rt_uint32_t PCLK; @@ -35,60 +35,60 @@ rt_uint32_t UCLK; void rt_hw_get_clock(void) { - rt_uint32_t val; - rt_uint8_t m, p, s; + rt_uint32_t val; + rt_uint8_t m, p, s; - val = MPLLCON; - m = (val>>12)&0xff; - p = (val>>4)&0x3f; - s = val&3; + val = MPLLCON; + m = (val>>12)&0xff; + p = (val>>4)&0x3f; + s = val&3; - FCLK = ((m+8)*(CONFIG_SYS_CLK_FREQ/100)*2)/((p+2)*(1<>1)&3; - p = val&1; + val = CLKDIVN; + m = (val>>1)&3; + p = val&1; - switch (m) { - case 0: - HCLK = FCLK; - break; - case 1: - HCLK = FCLK>>1; - break; - case 2: - if(s&2) - HCLK = FCLK>>3; - else - HCLK = FCLK>>2; - break; - case 3: - if(s&1) - HCLK = FCLK/6; - else - HCLK = FCLK/3; - break; + switch (m) { + case 0: + HCLK = FCLK; + break; + case 1: + HCLK = FCLK>>1; + break; + case 2: + if(s&2) + HCLK = FCLK>>3; + else + HCLK = FCLK>>2; + break; + case 3: + if(s&1) + HCLK = FCLK/6; + else + HCLK = FCLK/3; + break; } - if(p) - PCLK = HCLK>>1; - else - PCLK = HCLK; + if(p) + PCLK = HCLK>>1; + else + PCLK = HCLK; } void rt_hw_set_mpll_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv) { - MPLLCON = sdiv | (pdiv<<4) | (mdiv<<12); + MPLLCON = sdiv | (pdiv<<4) | (mdiv<<12); } void rt_hw_set_upll_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv) { - UPLLCON = (mdiv<<12) | (pdiv<<4) | sdiv; + UPLLCON = (mdiv<<12) | (pdiv<<4) | sdiv; } void rt_hw_set_divider(rt_uint8_t hdivn, rt_uint8_t pdivn) { - CLKDIVN = (hdivn<<1) | pdivn; + CLKDIVN = (hdivn<<1) | pdivn; } /** @@ -96,9 +96,9 @@ void rt_hw_set_divider(rt_uint8_t hdivn, rt_uint8_t pdivn) */ void rt_hw_clock_init(void) { - LOCKTIME = 0xFFFFFFFF; - rt_hw_set_mpll_clock(MPL_SDIV, MPL_PDIV, MPL_MIDV); - rt_hw_set_upll_clock(UPL_SDIV, UPL_PDIV, UPL_MDIV); - rt_hw_set_divider(HDIVN, PDIVN); + LOCKTIME = 0xFFFFFFFF; + rt_hw_set_mpll_clock(MPL_SDIV, MPL_PDIV, MPL_MIDV); + rt_hw_set_upll_clock(UPL_SDIV, UPL_PDIV, UPL_MDIV); + rt_hw_set_divider(HDIVN, PDIVN); } diff --git a/libcpu/arm/s3c24x0/trap.c b/libcpu/arm/s3c24x0/trap.c index f2f389c6b0..f0e8a7097a 100644 --- a/libcpu/arm/s3c24x0/trap.c +++ b/libcpu/arm/s3c24x0/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -34,13 +34,13 @@ extern long list_thread(void); void rt_hw_show_register (struct rt_hw_register *regs) { - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); } /** @@ -53,15 +53,15 @@ void rt_hw_show_register (struct rt_hw_register *regs) */ void rt_hw_trap_udef(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("undefined instruction\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_kprintf("undefined instruction\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -75,10 +75,10 @@ void rt_hw_trap_udef(struct rt_hw_register *regs) */ void rt_hw_trap_swi(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("software interrupt\n"); - rt_hw_cpu_shutdown(); + rt_kprintf("software interrupt\n"); + rt_hw_cpu_shutdown(); } /** @@ -91,15 +91,15 @@ void rt_hw_trap_swi(struct rt_hw_register *regs) */ void rt_hw_trap_pabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("prefetch abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_kprintf("prefetch abort\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -112,15 +112,15 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs) */ void rt_hw_trap_dabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("data abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_kprintf("data abort\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -132,9 +132,9 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs) */ void rt_hw_trap_resv(struct rt_hw_register *regs) { - rt_kprintf("not used\n"); - rt_hw_show_register(regs); - rt_hw_cpu_shutdown(); + rt_kprintf("not used\n"); + rt_hw_show_register(regs); + rt_hw_cpu_shutdown(); } extern struct rt_irq_desc isr_table[]; @@ -161,13 +161,13 @@ void rt_hw_trap_irq(void) ClearPending(1 << irq); #ifdef RT_USING_INTERRUPT_INFO - isr_table[irq].counter++; + isr_table[irq].counter++; #endif /* RT_USING_INTERRUPT_INFO */ } void rt_hw_trap_fiq(void) { - rt_kprintf("fast interrupt request\n"); + rt_kprintf("fast interrupt request\n"); } /*@}*/ diff --git a/libcpu/arm/s3c44b0/cpu.c b/libcpu/arm/s3c44b0/cpu.c index 03ebefba18..c9af445307 100644 --- a/libcpu/arm/s3c44b0/cpu.c +++ b/libcpu/arm/s3c44b0/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,29 +22,29 @@ */ void rt_hw_cpu_icache_enable() { - rt_base_t reg; - - volatile int i; - /* flush cycle */ - for(i = 0x10002000; i < 0x10004800; i+=16) - { - *((int *)i)=0x0; - } - - /* - * Init cache - * Non-cacheable area (everything outside RAM) - * 0x0000:0000 - 0x0C00:0000 - */ - NCACHBE0 = 0xC0000000; - NCACHBE1 = 0x00000000; - - /* - Enable chache - */ - reg = SYSCFG; - reg |= 0x00000006; /* 8kB */ - SYSCFG = reg; + rt_base_t reg; + + volatile int i; + /* flush cycle */ + for(i = 0x10002000; i < 0x10004800; i+=16) + { + *((int *)i)=0x0; + } + + /* + * Init cache + * Non-cacheable area (everything outside RAM) + * 0x0000:0000 - 0x0C00:0000 + */ + NCACHBE0 = 0xC0000000; + NCACHBE1 = 0x00000000; + + /* + Enable chache + */ + reg = SYSCFG; + reg |= 0x00000006; /* 8kB */ + SYSCFG = reg; } /** @@ -53,11 +53,11 @@ void rt_hw_cpu_icache_enable() */ void rt_hw_cpu_icache_disable() { - rt_base_t reg; + rt_base_t reg; - reg = SYSCFG; - reg &= ~0x00000006; /* 8kB */ - SYSCFG = reg; + reg = SYSCFG; + reg &= ~0x00000006; /* 8kB */ + SYSCFG = reg; } /** @@ -66,7 +66,7 @@ void rt_hw_cpu_icache_disable() */ rt_base_t rt_hw_cpu_icache_status() { - return 0; + return 0; } /** @@ -75,7 +75,7 @@ rt_base_t rt_hw_cpu_icache_status() */ void rt_hw_cpu_dcache_enable() { - rt_hw_cpu_icache_enable(); + rt_hw_cpu_icache_enable(); } /** @@ -84,7 +84,7 @@ void rt_hw_cpu_dcache_enable() */ void rt_hw_cpu_dcache_disable() { - rt_hw_cpu_icache_disable(); + rt_hw_cpu_icache_disable(); } /** @@ -93,7 +93,7 @@ void rt_hw_cpu_dcache_disable() */ rt_base_t rt_hw_cpu_dcache_status() { - return rt_hw_cpu_icache_status(); + return rt_hw_cpu_icache_status(); } /** @@ -110,9 +110,9 @@ void rt_hw_cpu_reset() */ void rt_hw_cpu_shutdown() { - rt_kprintf("shutdown...\n"); + rt_kprintf("shutdown...\n"); - while (1); + while (1); } /*@}*/ diff --git a/libcpu/arm/s3c44b0/interrupt.c b/libcpu/arm/s3c44b0/interrupt.c index 6b3eed4a39..5464011dd2 100644 --- a/libcpu/arm/s3c44b0/interrupt.c +++ b/libcpu/arm/s3c44b0/interrupt.c @@ -1,19 +1,19 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2006-09-06 XuXinming first version - * 2006-09-15 Bernard add interrupt bank 0..3 for more effective + * 2006-09-15 Bernard add interrupt bank 0..3 for more effective * in irq trap */ #include #include "s3c44b0.h" -#define MAX_HANDLERS 26 +#define MAX_HANDLERS 26 extern rt_uint32_t rt_interrupt_nest; @@ -34,7 +34,7 @@ unsigned char interrupt_bank3[256]; void rt_hw_interrupt_handle(int vector) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } /** @@ -42,70 +42,70 @@ void rt_hw_interrupt_handle(int vector) */ void rt_hw_interrupt_init() { - register int i; - - /* all interrupt disabled include global bit */ - INTMSK = 0x07ffffff; - - /* clear pending register */ - I_ISPC = 0x03ffffff; - - /* non-vector mode IRQ enable */ - INTCON = 0x5; - - /* all IRQ mode */ - INTMOD = 0x0; - - /* init exceptions table */ - for(i=0; ir0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); } /** @@ -52,10 +52,10 @@ void rt_hw_show_register (struct rt_hw_register *regs) */ void rt_hw_trap_udef(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("undefined instruction\n"); - rt_hw_cpu_shutdown(); + rt_kprintf("undefined instruction\n"); + rt_hw_cpu_shutdown(); } /** @@ -84,10 +84,10 @@ void rt_hw_trap_swi(struct rt_hw_register *regs) */ void rt_hw_trap_pabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("prefetch abort\n"); - rt_hw_cpu_shutdown(); + rt_kprintf("prefetch abort\n"); + rt_hw_cpu_shutdown(); } /** @@ -100,10 +100,10 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs) */ void rt_hw_trap_dabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("data abort\n"); - rt_hw_cpu_shutdown(); + rt_kprintf("data abort\n"); + rt_hw_cpu_shutdown(); } /** @@ -123,50 +123,50 @@ void rt_hw_trap_resv(struct rt_hw_register *regs) extern rt_isr_handler_t isr_table[]; void rt_hw_trap_irq() { - register unsigned long ispr, intstat; - register rt_isr_handler_t isr_func; + register unsigned long ispr, intstat; + register rt_isr_handler_t isr_func; #ifdef BSP_INT_DEBUG - rt_kprintf("irq coming, "); + rt_kprintf("irq coming, "); #endif - intstat = I_ISPR & 0x7ffffff; + intstat = I_ISPR & 0x7ffffff; #ifdef BSP_INT_DEBUG - rt_kprintf("I_ISPR: %d\n", intstat); + rt_kprintf("I_ISPR: %d\n", intstat); #endif - ispr = intstat; - - /* to find interrupt */ - if ( intstat & 0xff ) /* lowest 8bits */ - { - intstat = interrupt_bank0[intstat & 0xff]; - isr_func = (rt_isr_handler_t)isr_table[ intstat ]; - } - else if ( intstat & 0xff00 ) /* low 8bits */ - { - intstat = interrupt_bank1[(intstat & 0xff00) >> 8]; - isr_func = (rt_isr_handler_t)isr_table[ intstat ]; - } - else if ( intstat & 0xff0000 ) /* high 8bits */ - { - intstat = interrupt_bank2[(intstat & 0xff0000) >> 16]; - isr_func = (rt_isr_handler_t)isr_table[ intstat ]; - } - else if ( intstat & 0xff000000 ) /* highest 8bits */ - { - intstat = interrupt_bank3[(intstat & 0xff000000) >> 24]; - isr_func = (rt_isr_handler_t)isr_table[ intstat ]; - } - else return; + ispr = intstat; + + /* to find interrupt */ + if ( intstat & 0xff ) /* lowest 8bits */ + { + intstat = interrupt_bank0[intstat & 0xff]; + isr_func = (rt_isr_handler_t)isr_table[ intstat ]; + } + else if ( intstat & 0xff00 ) /* low 8bits */ + { + intstat = interrupt_bank1[(intstat & 0xff00) >> 8]; + isr_func = (rt_isr_handler_t)isr_table[ intstat ]; + } + else if ( intstat & 0xff0000 ) /* high 8bits */ + { + intstat = interrupt_bank2[(intstat & 0xff0000) >> 16]; + isr_func = (rt_isr_handler_t)isr_table[ intstat ]; + } + else if ( intstat & 0xff000000 ) /* highest 8bits */ + { + intstat = interrupt_bank3[(intstat & 0xff000000) >> 24]; + isr_func = (rt_isr_handler_t)isr_table[ intstat ]; + } + else return; #ifdef BSP_INT_DEBUG - rt_kprintf("irq: %d happen\n", intstat); + rt_kprintf("irq: %d happen\n", intstat); #endif - /* turn to interrupt service routine */ - isr_func(intstat); + /* turn to interrupt service routine */ + isr_func(intstat); - I_ISPC = ispr; /* clear interrupt */ + I_ISPC = ispr; /* clear interrupt */ } void rt_hw_trap_fiq() diff --git a/libcpu/arm/sep4020/clk.c b/libcpu/arm/sep4020/clk.c index da69e25b6d..031d310fcf 100644 --- a/libcpu/arm/sep4020/clk.c +++ b/libcpu/arm/sep4020/clk.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -11,46 +11,46 @@ #include #include "sep4020.h" -#define CLK_IN 4000000 /* Fin = 4.00MHz */ -#define SYSCLK 72000000 /* system clock we want */ - -#define CLK_ESRAM 0 -#define CLK_LCDC 1 -#define CLK_PWM 2 -#define CLK_DMAC 3 -#define CLK_EMI 4 -#define CLK_MMCSD 5 -#define CLK_SSI 7 -#define CLK_UART0 8 -#define CLK_UART1 9 -#define CLK_UART2 10 -#define CLK_UART3 11 -#define CLK_USB 12 -#define CLK_MAC 13 -#define CLK_SMC 14 -#define CLK_I2C 15 -#define CLK_GPT 16 +#define CLK_IN 4000000 /* Fin = 4.00MHz */ +#define SYSCLK 72000000 /* system clock we want */ + +#define CLK_ESRAM 0 +#define CLK_LCDC 1 +#define CLK_PWM 2 +#define CLK_DMAC 3 +#define CLK_EMI 4 +#define CLK_MMCSD 5 +#define CLK_SSI 7 +#define CLK_UART0 8 +#define CLK_UART1 9 +#define CLK_UART2 10 +#define CLK_UART3 11 +#define CLK_USB 12 +#define CLK_MAC 13 +#define CLK_SMC 14 +#define CLK_I2C 15 +#define CLK_GPT 16 static void rt_hw_set_system_clock(void) { - rt_uint8_t pv; - - /* pv value*/ - pv = SYSCLK/2/CLK_IN; - /* go to normal mode*/ - *(RP)PMU_PMDR = 0x01; - /* set the clock */ - *(RP)PMU_PMCR = 0x4000 | pv; - /* trige configurate*/ - *(RP)PMU_PMCR = 0xc000 | pv; + rt_uint8_t pv; + + /* pv value*/ + pv = SYSCLK/2/CLK_IN; + /* go to normal mode*/ + *(RP)PMU_PMDR = 0x01; + /* set the clock */ + *(RP)PMU_PMCR = 0x4000 | pv; + /* trige configurate*/ + *(RP)PMU_PMCR = 0xc000 | pv; } static void rt_hw_set_usb_clock(void) { - /* set the clock */ - *(RP)PMU_PUCR = 0x000c; - /* trige configurate*/ - *(RP)PMU_PMCR = 0x800c; + /* set the clock */ + *(RP)PMU_PUCR = 0x000c; + /* trige configurate*/ + *(RP)PMU_PMCR = 0x800c; } @@ -59,10 +59,10 @@ static void rt_hw_set_usb_clock(void) */ void rt_hw_clock_init(void) { - /* set system clock */ - rt_hw_set_system_clock(); - /* set usb clock */ - rt_hw_set_usb_clock(); + /* set system clock */ + rt_hw_set_system_clock(); + /* set usb clock */ + rt_hw_set_usb_clock(); } /** @@ -70,22 +70,22 @@ void rt_hw_clock_init(void) */ rt_uint32_t rt_hw_get_clock(void) { - rt_uint32_t val; - rt_uint8_t pv, pd, npd; - - /* get PMCR value */ - val =*(RP) PMU_PMCR; - /* get NPD */ - npd = (val >> 14) & 0x01; - /* get PD */ - pd = (val >> 10) & 0x0f; - /* get PV */ - pv = val & 0x7f; - /* caculate the system clock */ - if(npd) - val = 2 * CLK_IN * pv; - else - val = CLK_IN * pv / (pd + 1); + rt_uint32_t val; + rt_uint8_t pv, pd, npd; + + /* get PMCR value */ + val =*(RP) PMU_PMCR; + /* get NPD */ + npd = (val >> 14) & 0x01; + /* get PD */ + pd = (val >> 10) & 0x0f; + /* get PV */ + pv = val & 0x7f; + /* caculate the system clock */ + if(npd) + val = 2 * CLK_IN * pv; + else + val = CLK_IN * pv / (pd + 1); return(val); } diff --git a/libcpu/arm/sep4020/cpu.c b/libcpu/arm/sep4020/cpu.c index ee4eab626b..2d443309b0 100644 --- a/libcpu/arm/sep4020/cpu.c +++ b/libcpu/arm/sep4020/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -21,76 +21,76 @@ extern rt_uint32_t rt_hw_interrupt_disable(void); */ /*@{*/ -#define ICACHE_MASK (rt_uint32_t)(1 << 12) -#define DCACHE_MASK (rt_uint32_t)(1 << 2) +#define ICACHE_MASK (rt_uint32_t)(1 << 12) +#define DCACHE_MASK (rt_uint32_t)(1 << 2) #ifdef __GNUC__ rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - return i; + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "orr r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "orr r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } rt_inline void cache_disable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "bic r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "bic r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } #endif #ifdef __CC_ARM rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - __asm - { - mrc p15, 0, i, c1, c0, 0 - } + __asm + { + mrc p15, 0, i, c1, c0, 0 + } - return i; + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } rt_inline void cache_disable(rt_uint32_t bit) { - rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } #endif @@ -100,7 +100,7 @@ rt_inline void cache_disable(rt_uint32_t bit) */ void rt_hw_cpu_icache_enable() { - cache_enable(ICACHE_MASK); + cache_enable(ICACHE_MASK); } /** @@ -109,7 +109,7 @@ void rt_hw_cpu_icache_enable() */ void rt_hw_cpu_icache_disable() { - cache_disable(ICACHE_MASK); + cache_disable(ICACHE_MASK); } /** @@ -118,7 +118,7 @@ void rt_hw_cpu_icache_disable() */ rt_base_t rt_hw_cpu_icache_status() { - return (cp15_rd() & ICACHE_MASK); + return (cp15_rd() & ICACHE_MASK); } /** @@ -127,7 +127,7 @@ rt_base_t rt_hw_cpu_icache_status() */ void rt_hw_cpu_dcache_enable() { - cache_enable(DCACHE_MASK); + cache_enable(DCACHE_MASK); } /** @@ -136,7 +136,7 @@ void rt_hw_cpu_dcache_enable() */ void rt_hw_cpu_dcache_disable() { - cache_disable(DCACHE_MASK); + cache_disable(DCACHE_MASK); } /** @@ -145,7 +145,7 @@ void rt_hw_cpu_dcache_disable() */ rt_base_t rt_hw_cpu_dcache_status() { - return (cp15_rd() & DCACHE_MASK); + return (cp15_rd() & DCACHE_MASK); } /** @@ -155,18 +155,18 @@ rt_base_t rt_hw_cpu_dcache_status() void rt_hw_cpu_reset() { - /* enable watchdog */ - *(RP)(RTC_CTR) = 0x02; + /* enable watchdog */ + *(RP)(RTC_CTR) = 0x02; - /*Enable watchdog reset*/ - *(RP)(RTC_INT_EN) = 0x20; + /*Enable watchdog reset*/ + *(RP)(RTC_INT_EN) = 0x20; - /* Initialize watchdog timer count register */ - *(RP)(RTC_WD_CNT) = 0x0001; + /* Initialize watchdog timer count register */ + *(RP)(RTC_WD_CNT) = 0x0001; - while(1); /* loop forever and wait for reset to happen */ + while(1); /* loop forever and wait for reset to happen */ - /* NEVER REACHED */ + /* NEVER REACHED */ } /** @@ -175,12 +175,12 @@ void rt_hw_cpu_reset() */ void rt_hw_cpu_shutdown() { - rt_uint32_t UNUSED level; - rt_kprintf("shutdown...\n"); + rt_uint32_t UNUSED level; + rt_kprintf("shutdown...\n"); - level = rt_hw_interrupt_disable(); + level = rt_hw_interrupt_disable(); - RT_ASSERT(RT_NULL); + RT_ASSERT(RT_NULL); } /*@}*/ diff --git a/libcpu/arm/sep4020/interrupt.c b/libcpu/arm/sep4020/interrupt.c index ebc9c9625b..24907c139f 100644 --- a/libcpu/arm/sep4020/interrupt.c +++ b/libcpu/arm/sep4020/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,7 +13,7 @@ #include #include -#define MAX_HANDLERS 32 +#define MAX_HANDLERS 32 extern rt_uint32_t rt_interrupt_nest; @@ -29,7 +29,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag; static void rt_hw_interrupt_handle(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } /** @@ -45,7 +45,7 @@ void rt_hw_interrupt_init(void) *(RP)(INTC_IMR) = 0xFFFFFFFF; /*enable all the irq*/ - *(RP)(INTC_IER) = 0XFFFFFFFF; + *(RP)(INTC_IER) = 0XFFFFFFFF; /*Dont use any forced irq*/ *(RP)(INTC_IFR) = 0x0; @@ -82,7 +82,7 @@ void rt_hw_interrupt_init(void) */ void rt_hw_interrupt_mask(int vector) { - *(RP)(INTC_IMR) |= 1 << vector; + *(RP)(INTC_IMR) |= 1 << vector; } /** @@ -91,12 +91,12 @@ void rt_hw_interrupt_mask(int vector) */ void rt_hw_interrupt_umask(int vector) { - if(vector == 16) - { - rt_kprintf("Interrupt vec %d is not used!\n", vector); - } - else - *(RP)(INTC_IMR) &= ~(1 << vector); + if(vector == 16) + { + rt_kprintf("Interrupt vec %d is not used!\n", vector); + } + else + *(RP)(INTC_IMR) &= ~(1 << vector); } @@ -118,7 +118,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, if (handler != RT_NULL) { #ifdef RT_USING_INTERRUPT_INFO - rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); + rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); #endif /* RT_USING_INTERRUPT_INFO */ isr_table[vector].handler = handler; isr_table[vector].param = param; diff --git a/libcpu/arm/sep4020/sep4020.h b/libcpu/arm/sep4020/sep4020.h index 4ae09d0275..bb8effbff0 100644 --- a/libcpu/arm/sep4020/sep4020.h +++ b/libcpu/arm/sep4020/sep4020.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,13 +13,13 @@ /*Core definations*/ #define SVCMODE -#define Mode_USR 0x10 -#define Mode_FIQ 0x11 -#define Mode_IRQ 0x12 -#define Mode_SVC 0x13 -#define Mode_ABT 0x17 -#define Mode_UND 0x1B -#define Mode_SYS 0x1F +#define Mode_USR 0x10 +#define Mode_FIQ 0x11 +#define Mode_IRQ 0x12 +#define Mode_SVC 0x13 +#define Mode_ABT 0x17 +#define Mode_UND 0x1B +#define Mode_SYS 0x1F @@ -106,7 +106,7 @@ #define RTC_INT_STS (RTC_BASE+0X014) /* 中断状态寄存器 */ #define RTC_SAMP (RTC_BASE+0X018) /* 采样周期寄存器 */ #define RTC_WD_CNT (RTC_BASE+0X01C) /* Watch-Dog计数值寄存器 */ -#define RTC_WD_SEV (RTC_BASE+0X020) /* Watch-Dog服务寄存器 */ +#define RTC_WD_SEV (RTC_BASE+0X020) /* Watch-Dog服务寄存器 */ #define RTC_CONFIG_CHECK (RTC_BASE+0X024) /* 配置时间确认寄存器 (在配置时间之前先写0xaaaaaaaa) */ #define RTC_KEY0 (RTC_BASE+0X02C) /* 密钥寄存器 */ @@ -325,18 +325,18 @@ * SD模块 * 基址: 0x1000B000 */ - -#define SDC_CLOCK_CONTROL (SD_BASE+0x00) /* SDIO时钟控制寄存器 */ -#define SDC_SOFTWARE_RESET (SD_BASE+0X04) /* SDIO软件复位寄存器 */ -#define SDC_ARGUMENT (SD_BASE+0X08) /* SDIO命令参数寄存器 */ -#define SDC_COMMAND (SD_BASE+0X0C) /* SDIO命令控制寄存器 */ + +#define SDC_CLOCK_CONTROL (SD_BASE+0x00) /* SDIO时钟控制寄存器 */ +#define SDC_SOFTWARE_RESET (SD_BASE+0X04) /* SDIO软件复位寄存器 */ +#define SDC_ARGUMENT (SD_BASE+0X08) /* SDIO命令参数寄存器 */ +#define SDC_COMMAND (SD_BASE+0X0C) /* SDIO命令控制寄存器 */ #define SDC_BLOCK_SIZE (SD_BASE+0X10) /* SDIO数据块长度寄存器 */ -#define SDC_BLOCK_COUNT (SD_BASE+0X14) /* SDIO数据块数目寄存器 */ -#define SDC_TRANSFER_MODE (SD_BASE+0X18) /* SDIO传输模式选择寄存器 */ -#define SDC_RESPONSE0 (SD_BASE+0X1c) /* SDIO响应寄存器0 */ -#define SDC_RESPONSE1 (SD_BASE+0X20) /* SDIO响应寄存器1 */ -#define SDC_RESPONSE2 (SD_BASE+0X24) /* SDIO响应寄存器2 */ -#define SDC_RESPONSE3 (SD_BASE+0X28) /* SDIO响应寄存器3 */ +#define SDC_BLOCK_COUNT (SD_BASE+0X14) /* SDIO数据块数目寄存器 */ +#define SDC_TRANSFER_MODE (SD_BASE+0X18) /* SDIO传输模式选择寄存器 */ +#define SDC_RESPONSE0 (SD_BASE+0X1c) /* SDIO响应寄存器0 */ +#define SDC_RESPONSE1 (SD_BASE+0X20) /* SDIO响应寄存器1 */ +#define SDC_RESPONSE2 (SD_BASE+0X24) /* SDIO响应寄存器2 */ +#define SDC_RESPONSE3 (SD_BASE+0X28) /* SDIO响应寄存器3 */ #define SDC_READ_TIMEOUT_CONTROL (SD_BASE+0X2c) /* SDIO读超时控制寄存器 */ #define SDC_INTERRUPT_STATUS (SD_BASE+0X30) /* SDIO中断状态寄存器 */ #define SDC_INTERRUPT_STATUS_MASK (SD_BASE+0X34) /* SDIO中断状态屏蔽寄存器 */ @@ -650,15 +650,15 @@ #define MAC_HASH0 (MAC_BASE+0X048) /* MAC HASH寄存器 */ #define MAC_HASH1 (MAC_BASE+0X04C) /* MAC HASH寄存器 */ #define MAC_TXPAUSE (MAC_BASE+0X050) /* MAC控制帧寄存器 */ -#define MAC_TX_BD (MAC_BASE+0X400) -#define MAC_RX_BD (MAC_BASE+0X600) +#define MAC_TX_BD (MAC_BASE+0X400) +#define MAC_RX_BD (MAC_BASE+0X600) /* ************************************** * Error Codes: * IF SUCCESS RETURN 0, ELSE RETURN OTHER ERROR CODE, - * parameter error return (-33)/E_PAR, + * parameter error return (-33)/E_PAR, * hardware error reture (-99)/E_HA ************************************** */ @@ -680,7 +680,7 @@ #define E_QOVR (-73) /* Queuing or nesting overflow */ #define E_DLT (-81) /* Object being waited for was deleted */ #define E_TMOUT (-85) /* Polling failure or timeout exceeded */ -#define E_RLWAI (-86) /* WAIT state was forcibly released */ +#define E_RLWAI (-86) /* WAIT state was forcibly released */ #define E_HA (-99) /* HARD WARE ERROR */ @@ -692,7 +692,7 @@ */ #define CLK_SGPT (1 << 16) -#define CLK_SI2S (1 << 15) +#define CLK_SI2S (1 << 15) #define CLK_SSMC (1 << 14) #define CLK_SMAC (1 << 13) #define CLK_SUSB (1 << 12) @@ -713,8 +713,8 @@ /*Interrupt Sources*/ -#define INTSRC_RTC 31 -#define INTSRC_DMAC 30 +#define INTSRC_RTC 31 +#define INTSRC_DMAC 30 #define INTSRC_EMI 29 #define INTSRC_MAC 28 #define INTSRC_TIMER1 27 @@ -732,17 +732,17 @@ #define INTSRC_USB 15 #define INTSRC_SMC0 14 #define INTSRC_SMC1 13 -#define INTSRC_SDIO 12 -#define INTSRC_EXINT10 11 -#define INTSRC_EXINT9 10 -#define INTSRC_EXINT8 9 -#define INTSRC_EXINT7 8 -#define INTSRC_EXINT6 7 -#define INTSRC_EXINT5 6 -#define INTSRC_EXINT4 5 -#define INTSRC_EXINT3 4 -#define INTSRC_EXINT2 3 -#define INTSRC_EXINT1 2 +#define INTSRC_SDIO 12 +#define INTSRC_EXINT10 11 +#define INTSRC_EXINT9 10 +#define INTSRC_EXINT8 9 +#define INTSRC_EXINT7 8 +#define INTSRC_EXINT6 7 +#define INTSRC_EXINT5 6 +#define INTSRC_EXINT4 5 +#define INTSRC_EXINT3 4 +#define INTSRC_EXINT2 3 +#define INTSRC_EXINT1 2 #define INTSRC_EXINT0 1 #define INTSRC_NULL 0 @@ -752,7 +752,7 @@ #define set_int_force(intnum) *(RP)INTC_IFR = (1 << intnum) //置1后，软件强制该位对应的中断源发出中断信号 #define enable_irq(intnum) *(RP)INTC_IER |= (1 << intnum) //置1后，允许中断源的IRQ 中断信号 #define disable_irq( intnum) *(RP)INTC_IER &= ~(1<< intnum) //置0后，不允许中断源的IRQ 中断信号 -#define mask_irq(intnum) *(RP)INTC_IMR |= (1 << intnum) //置1后，屏蔽对应的IRQ 中断信号 +#define mask_irq(intnum) *(RP)INTC_IMR |= (1 << intnum) //置1后，屏蔽对应的IRQ 中断信号 #define unmask_irq(intnum) *(RP)INTC_IMR &= ~(1 << intnum) //置0后，通过对应的IRQ 中断信号 #define mask_all_irq() *(RP)INTC_IMR = 0xFFFFFFFF //屏蔽对应的IRQ 中断信号 #define unmask_all_irq() *(RP)INTC_IMR = 0x00000000 //通过对应的IRQ 中断信号 @@ -765,7 +765,7 @@ * 所有程序中用到的Typedef ************************************** */ - + typedef char S8; /* signed 8-bit integer */ typedef short S16; /* signed 16-bit integer */ typedef long S32; /* signed 32-bit integer */ @@ -782,8 +782,8 @@ typedef void (*FP)(); /* program start address */ #ifndef _BOOL_TYPE_ #define _BOOL_TYPE_ -typedef int BOOL; /* Boolean value. TRUE (1) or FALSE (0). */ -#endif +typedef int BOOL; /* Boolean value. TRUE (1) or FALSE (0). */ +#endif typedef int ER; /* Error code. A signed integer. */ @@ -802,71 +802,71 @@ typedef int ER; /* Error code. A signed integer. */ /*Macros for debug*/ #define EOUT(fmt,...) \ - do \ - { \ - rt_kprintf("EOUT:(%s:%i) ",__FILE__,__LINE__); \ - rt_kprintf(fmt,##__VA_ARGS__); \ - }while(0) + do \ + { \ + rt_kprintf("EOUT:(%s:%i) ",__FILE__,__LINE__); \ + rt_kprintf(fmt,##__VA_ARGS__); \ + }while(0) #define RT_DEBUG #ifdef RT_DEBUG - #define DBOUT(fmt,...) \ - do \ - { \ - rt_kprintf("DBOUT:(%s:%i) ",__FILE__,__LINE__); \ - rt_kprintf(fmt,##__VA_ARGS__); \ - }while(0) + #define DBOUT(fmt,...) \ + do \ + { \ + rt_kprintf("DBOUT:(%s:%i) ",__FILE__,__LINE__); \ + rt_kprintf(fmt,##__VA_ARGS__); \ + }while(0) #else - #define DBOUT(fmt,...) \ - do{}while(0) + #define DBOUT(fmt,...) \ + do{}while(0) #endif -#ifdef RT_DEBUG - #define ASSERT(arg) \ - if((arg) == 0) \ - { \ - while(1) \ - { \ - rt_kprintf("have a assert failure\n"); \ - } \ - } +#ifdef RT_DEBUG + #define ASSERT(arg) \ + if((arg) == 0) \ + { \ + while(1) \ + { \ + rt_kprintf("have a assert failure\n"); \ + } \ + } #else - #define ASSERT(arg) \ - do \ - { \ - }while(0) + #define ASSERT(arg) \ + do \ + { \ + }while(0) #endif #define write_reg(reg,value) \ - do \ - { \ - *(RP)(reg) = value; \ - }while(0) + do \ + { \ + *(RP)(reg) = value; \ + }while(0) #define read_reg(reg) (*(RP)reg) struct rt_hw_register { - rt_uint32_t r0; - rt_uint32_t r1; - rt_uint32_t r2; - rt_uint32_t r3; - rt_uint32_t r4; - rt_uint32_t r5; - rt_uint32_t r6; - rt_uint32_t r7; - rt_uint32_t r8; - rt_uint32_t r9; - rt_uint32_t r10; - rt_uint32_t fp; - rt_uint32_t ip; - rt_uint32_t sp; - rt_uint32_t lr; - rt_uint32_t pc; - rt_uint32_t cpsr; - rt_uint32_t ORIG_r0; + rt_uint32_t r0; + rt_uint32_t r1; + rt_uint32_t r2; + rt_uint32_t r3; + rt_uint32_t r4; + rt_uint32_t r5; + rt_uint32_t r6; + rt_uint32_t r7; + rt_uint32_t r8; + rt_uint32_t r9; + rt_uint32_t r10; + rt_uint32_t fp; + rt_uint32_t ip; + rt_uint32_t sp; + rt_uint32_t lr; + rt_uint32_t pc; + rt_uint32_t cpsr; + rt_uint32_t ORIG_r0; }; diff --git a/libcpu/arm/sep4020/serial.c b/libcpu/arm/sep4020/serial.c index 713959238a..9bf1546c08 100644 --- a/libcpu/arm/sep4020/serial.c +++ b/libcpu/arm/sep4020/serial.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2006-03-13 Bernard first version * 2009-04-20 yi.qiu modified according bernard's stm32 version - * 2010-10-6 wangmeng added sep4020 surpport + * 2010-10-6 wangmeng added sep4020 surpport */ #include #include @@ -24,204 +24,204 @@ */ static rt_err_t rt_serial_init (rt_device_t dev) { - struct serial_device* uart = (struct serial_device*) dev->user_data; - - if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) - { - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_memset(uart->int_rx->rx_buffer, 0, - sizeof(uart->int_rx->rx_buffer)); - uart->int_rx->read_index = uart->int_rx->save_index = 0; - } - - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - rt_memset(uart->int_tx->tx_buffer, 0, - sizeof(uart->int_tx->tx_buffer)); - uart->int_tx->write_index = uart->int_tx->save_index = 0; - } - - dev->flag |= RT_DEVICE_FLAG_ACTIVATED; - } - - return RT_EOK; + struct serial_device* uart = (struct serial_device*) dev->user_data; + + if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) + { + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_memset(uart->int_rx->rx_buffer, 0, + sizeof(uart->int_rx->rx_buffer)); + uart->int_rx->read_index = uart->int_rx->save_index = 0; + } + + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + rt_memset(uart->int_tx->tx_buffer, 0, + sizeof(uart->int_tx->tx_buffer)); + uart->int_tx->write_index = uart->int_tx->save_index = 0; + } + + dev->flag |= RT_DEVICE_FLAG_ACTIVATED; + } + + return RT_EOK; } /* save a char to serial buffer */ static void rt_serial_savechar(struct serial_device* uart, char ch) { - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch; - uart->int_rx->save_index ++; - if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->save_index = 0; - - /* if the next position is read index, discard this 'read char' */ - if (uart->int_rx->save_index == uart->int_rx->read_index) - { - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch; + uart->int_rx->save_index ++; + if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->save_index = 0; + + /* if the next position is read index, discard this 'read char' */ + if (uart->int_rx->save_index == uart->int_rx->read_index) + { + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); } static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) { - RT_ASSERT(dev != RT_NULL); - return RT_EOK; + RT_ASSERT(dev != RT_NULL); + return RT_EOK; } static rt_err_t rt_serial_close(rt_device_t dev) { - RT_ASSERT(dev != RT_NULL); - return RT_EOK; + RT_ASSERT(dev != RT_NULL); + return RT_EOK; } static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - rt_err_t err_code; - struct serial_device* uart; - - ptr = buffer; - err_code = RT_EOK; - uart = (struct serial_device*)dev->user_data; - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_base_t level; - - /* interrupt mode Rx */ - while (size) - { - if (uart->int_rx->read_index != uart->int_rx->save_index) - { - *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; - size --; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } - else - { - /* set error code */ - err_code = -RT_EEMPTY; - break; - } - } - } - else - { - /* polling mode */ - while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) - { - while (uart->uart_device->lsr & USTAT_RCV_READY) - { - *ptr = uart->uart_device->dlbl_fifo.txfifo & 0xff; - ptr ++; - } - } - } - - /* set error code */ - rt_set_errno(err_code); - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + rt_uint8_t* ptr; + rt_err_t err_code; + struct serial_device* uart; + + ptr = buffer; + err_code = RT_EOK; + uart = (struct serial_device*)dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_base_t level; + + /* interrupt mode Rx */ + while (size) + { + if (uart->int_rx->read_index != uart->int_rx->save_index) + { + *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; + size --; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + else + { + /* set error code */ + err_code = -RT_EEMPTY; + break; + } + } + } + else + { + /* polling mode */ + while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) + { + while (uart->uart_device->lsr & USTAT_RCV_READY) + { + *ptr = uart->uart_device->dlbl_fifo.txfifo & 0xff; + ptr ++; + } + } + } + + /* set error code */ + rt_set_errno(err_code); + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; } static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) -{ - rt_uint8_t* ptr; - rt_err_t err_code; - struct serial_device* uart; - - err_code = RT_EOK; - ptr = (rt_uint8_t*)buffer; - uart = (struct serial_device*)dev->user_data; - - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - /* interrupt mode Tx */ - while (uart->int_tx->save_index != uart->int_tx->write_index) - { - /* save on tx buffer */ - uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++; - - -- size; - - /* move to next position */ - uart->int_tx->save_index ++; - - /* wrap save index */ - if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE) - uart->int_tx->save_index = 0; - } - - /* set error code */ - if (size > 0) - err_code = -RT_EFULL; - } - else - { - /* polling mode */ - while (size) - { - /* - * to be polite with serial console add a line feed - * to the carriage return character - */ - if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM)) - { - while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); - uart->uart_device->dlbl_fifo.txfifo = '\r'; - } - - while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); - uart->uart_device->dlbl_fifo.txfifo = (*ptr & 0x1FF); - - ++ptr; --size; - } - } - - /* set error code */ - rt_set_errno(err_code); - - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; +{ + rt_uint8_t* ptr; + rt_err_t err_code; + struct serial_device* uart; + + err_code = RT_EOK; + ptr = (rt_uint8_t*)buffer; + uart = (struct serial_device*)dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* interrupt mode Tx */ + while (uart->int_tx->save_index != uart->int_tx->write_index) + { + /* save on tx buffer */ + uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++; + + -- size; + + /* move to next position */ + uart->int_tx->save_index ++; + + /* wrap save index */ + if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE) + uart->int_tx->save_index = 0; + } + + /* set error code */ + if (size > 0) + err_code = -RT_EFULL; + } + else + { + /* polling mode */ + while (size) + { + /* + * to be polite with serial console add a line feed + * to the carriage return character + */ + if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM)) + { + while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); + uart->uart_device->dlbl_fifo.txfifo = '\r'; + } + + while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); + uart->uart_device->dlbl_fifo.txfifo = (*ptr & 0x1FF); + + ++ptr; --size; + } + } + + /* set error code */ + rt_set_errno(err_code); + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; } static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) { - RT_ASSERT(dev != RT_NULL); - - switch (cmd) - { - case RT_DEVICE_CTRL_SUSPEND: - /* suspend device */ - dev->flag |= RT_DEVICE_FLAG_SUSPENDED; - break; - - case RT_DEVICE_CTRL_RESUME: - /* resume device */ - dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; - break; - } - - return RT_EOK; + RT_ASSERT(dev != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_SUSPEND: + /* suspend device */ + dev->flag |= RT_DEVICE_FLAG_SUSPENDED; + break; + + case RT_DEVICE_CTRL_RESUME: + /* resume device */ + dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; + break; + } + + return RT_EOK; } /* @@ -229,49 +229,49 @@ static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) */ rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial) { - RT_ASSERT(device != RT_NULL); - - device->type = RT_Device_Class_Char; - device->rx_indicate = RT_NULL; - device->tx_complete = RT_NULL; - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; - device->user_data = serial; - - /* register a character device */ - return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); + RT_ASSERT(device != RT_NULL); + + device->type = RT_Device_Class_Char; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; + device->user_data = serial; + + /* register a character device */ + return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); } - + /* ISR for serial interrupt */ void rt_hw_serial_isr(rt_device_t device) { - struct serial_device* uart = (struct serial_device*) device->user_data; - - /* interrupt mode receive */ - RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); - - /* save on rx buffer */ - while (uart->uart_device->lsr & USTAT_RCV_READY) - { - rt_serial_savechar(uart, uart->uart_device->dlbl_fifo.rxfifo & 0xff); - } - - /* invoke callback */ - if (device->rx_indicate != RT_NULL) - { - rt_size_t rx_length; - - /* get rx length */ - rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? - UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : - uart->int_rx->save_index - uart->int_rx->read_index; - - device->rx_indicate(device, rx_length); - } + struct serial_device* uart = (struct serial_device*) device->user_data; + + /* interrupt mode receive */ + RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); + + /* save on rx buffer */ + while (uart->uart_device->lsr & USTAT_RCV_READY) + { + rt_serial_savechar(uart, uart->uart_device->dlbl_fifo.rxfifo & 0xff); + } + + /* invoke callback */ + if (device->rx_indicate != RT_NULL) + { + rt_size_t rx_length; + + /* get rx length */ + rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? + UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : + uart->int_rx->save_index - uart->int_rx->read_index; + + device->rx_indicate(device, rx_length); + } } /*@}*/ diff --git a/libcpu/arm/sep4020/serial.h b/libcpu/arm/sep4020/serial.h index 69e7df248c..26ec0f6cec 100644 --- a/libcpu/arm/sep4020/serial.h +++ b/libcpu/arm/sep4020/serial.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2006-03-13 Bernard first version * 2009-04-20 yi.qiu modified according bernard's stm32 version - * 2010-10-6 wangmeng added sep4020 surpport + * 2010-10-6 wangmeng added sep4020 surpport */ #ifndef __SERIAL_H__ @@ -15,67 +15,67 @@ #include -#define USTAT_RCV_READY 0x01 /* receive data ready */ -#define USTAT_TXB_EMPTY 0x40 /* tx buffer empty */ -#define BPS 115200 /* serial baudrate */ +#define USTAT_RCV_READY 0x01 /* receive data ready */ +#define USTAT_TXB_EMPTY 0x40 /* tx buffer empty */ +#define BPS 115200 /* serial baudrate */ -#define UART_RX_BUFFER_SIZE 64 -#define UART_TX_BUFFER_SIZE 64 +#define UART_RX_BUFFER_SIZE 64 +#define UART_TX_BUFFER_SIZE 64 /*For sep4020's uart have several secondary function*/ /*we use union to decribe it*/ union dlbl_fifo { - rt_uint32_t dlbl; - rt_uint32_t rxfifo; - rt_uint32_t txfifo; + rt_uint32_t dlbl; + rt_uint32_t rxfifo; + rt_uint32_t txfifo; }; union dlbh_ier { - rt_uint32_t dlbh; - rt_uint32_t ier; + rt_uint32_t dlbh; + rt_uint32_t ier; }; union iir_fcr { - rt_uint32_t iir; - rt_uint32_t fcr; + rt_uint32_t iir; + rt_uint32_t fcr; }; struct serial_int_rx { - rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; - rt_uint32_t read_index, save_index; + rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; + rt_uint32_t read_index, save_index; }; struct serial_int_tx { - rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; - rt_uint32_t write_index, save_index; + rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; + rt_uint32_t write_index, save_index; }; typedef struct uartport { - union dlbl_fifo dlbl_fifo; - union dlbh_ier dlbh_ier; - union iir_fcr iir_fcr; - rt_uint32_t lcr; - rt_uint32_t mcr; - rt_uint32_t lsr; - rt_uint32_t msr; + union dlbl_fifo dlbl_fifo; + union dlbh_ier dlbh_ier; + union iir_fcr iir_fcr; + rt_uint32_t lcr; + rt_uint32_t mcr; + rt_uint32_t lsr; + rt_uint32_t msr; }uartport; struct serial_device { - uartport* uart_device; - - /* rx structure */ - struct serial_int_rx* int_rx; + uartport* uart_device; - /* tx structure */ - struct serial_int_tx* int_tx; + /* rx structure */ + struct serial_int_rx* int_rx; + + /* tx structure */ + struct serial_int_tx* int_tx; }; rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial); diff --git a/libcpu/arm/sep4020/stack.c b/libcpu/arm/sep4020/stack.c index b2205c76d2..3a7b5fd87c 100644 --- a/libcpu/arm/sep4020/stack.c +++ b/libcpu/arm/sep4020/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/sep4020/trap.c b/libcpu/arm/sep4020/trap.c index c551b2246c..441a55bd6d 100644 --- a/libcpu/arm/sep4020/trap.c +++ b/libcpu/arm/sep4020/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -31,13 +31,13 @@ extern struct rt_thread *rt_current_thread; void rt_hw_show_register (struct rt_hw_register *regs) { - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); } /** @@ -50,13 +50,13 @@ void rt_hw_show_register (struct rt_hw_register *regs) */ void rt_hw_trap_udef(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("undefined instruction\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); - rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); + rt_kprintf("undefined instruction\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -70,10 +70,10 @@ void rt_hw_trap_udef(struct rt_hw_register *regs) */ void rt_hw_trap_swi(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("software interrupt\n"); - rt_hw_cpu_shutdown(); + rt_kprintf("software interrupt\n"); + rt_hw_cpu_shutdown(); } /** @@ -86,13 +86,13 @@ void rt_hw_trap_swi(struct rt_hw_register *regs) */ void rt_hw_trap_pabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("prefetch abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); - rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); + rt_kprintf("prefetch abort\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -105,13 +105,13 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs) */ void rt_hw_trap_dabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("data abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); - rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); + rt_kprintf("data abort\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -123,9 +123,9 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs) */ void rt_hw_trap_resv(struct rt_hw_register *regs) { - rt_kprintf("not used\n"); - rt_hw_show_register(regs); - rt_hw_cpu_shutdown(); + rt_kprintf("not used\n"); + rt_hw_show_register(regs); + rt_hw_cpu_shutdown(); } extern struct rt_irq_desc isr_table[]; @@ -155,13 +155,13 @@ void rt_hw_trap_irq(void) isr_func(irq, param); #ifdef RT_USING_INTERRUPT_INFO - isr_table[irq].counter++; + isr_table[irq].counter++; #endif /* RT_USING_INTERRUPT_INFO */ } void rt_hw_trap_fiq(void) { - rt_kprintf("fast interrupt request\n"); + rt_kprintf("fast interrupt request\n"); } /*@}*/ diff --git a/libcpu/avr32/uc3/cpu.c b/libcpu/avr32/uc3/cpu.c index b77e78dc5b..190ce93257 100644 --- a/libcpu/avr32/uc3/cpu.c +++ b/libcpu/avr32/uc3/cpu.c @@ -25,7 +25,7 @@ */ void rt_hw_cpu_reset() { - /*NOTREACHED*/ + /*NOTREACHED*/ } /** @@ -34,9 +34,9 @@ void rt_hw_cpu_reset() */ void rt_hw_cpu_shutdown() { - rt_kprintf("shutdown...\n"); + rt_kprintf("shutdown...\n"); - RT_ASSERT(0); + RT_ASSERT(0); } /*@}*/ diff --git a/libcpu/avr32/uc3/serial.c b/libcpu/avr32/uc3/serial.c index 14ef865448..66fb6ca8b9 100644 --- a/libcpu/avr32/uc3/serial.c +++ b/libcpu/avr32/uc3/serial.c @@ -24,8 +24,8 @@ struct rt_device _rt_usart_device; struct avr32_serial_int_rx _rt_usart_rx; struct avr32_serial_device uart = { - .uart_device = (avr32_usart_t *) &AVR32_USART1, - .int_rx = &_rt_usart_rx + .uart_device = (avr32_usart_t *) &AVR32_USART1, + .int_rx = &_rt_usart_rx }; /** @@ -36,163 +36,163 @@ struct avr32_serial_device uart = /* RT-Thread Device Interface */ static rt_err_t rt_serial_init (rt_device_t dev) { - struct avr32_serial_device* uart = (struct avr32_serial_device*) dev->user_data; + struct avr32_serial_device* uart = (struct avr32_serial_device*) dev->user_data; - if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) - { - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_memset(uart->int_rx->rx_buffer, 0, sizeof(uart->int_rx->rx_buffer)); - uart->int_rx->read_index = 0; - uart->int_rx->save_index = 0; - } + if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) + { + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_memset(uart->int_rx->rx_buffer, 0, sizeof(uart->int_rx->rx_buffer)); + uart->int_rx->read_index = 0; + uart->int_rx->save_index = 0; + } - dev->flag |= RT_DEVICE_FLAG_ACTIVATED; - } + dev->flag |= RT_DEVICE_FLAG_ACTIVATED; + } - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) { - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_close(rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - rt_err_t err_code; - struct avr32_serial_device* uart; - - ptr = buffer; - err_code = RT_EOK; - uart = (struct avr32_serial_device*)dev->user_data; - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* interrupt mode Rx */ - while (size) - { - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - if (uart->int_rx->read_index != uart->int_rx->save_index) - { - /* read a character */ - *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; - size--; - - /* move to next position */ - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; - } - else - { - /* set error code */ - err_code = -RT_EEMPTY; - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - break; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } - } - else - { - /* polling mode */ - while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) - { - while (usart_test_hit(uart->uart_device)) - { - *ptr = uart->uart_device->rhr & 0xff; - ptr ++; - } - } - } - - /* set error code */ - rt_set_errno(err_code); - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + rt_uint8_t* ptr; + rt_err_t err_code; + struct avr32_serial_device* uart; + + ptr = buffer; + err_code = RT_EOK; + uart = (struct avr32_serial_device*)dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* interrupt mode Rx */ + while (size) + { + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + if (uart->int_rx->read_index != uart->int_rx->save_index) + { + /* read a character */ + *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; + size--; + + /* move to next position */ + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + } + else + { + /* set error code */ + err_code = -RT_EEMPTY; + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + } + else + { + /* polling mode */ + while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) + { + while (usart_test_hit(uart->uart_device)) + { + *ptr = uart->uart_device->rhr & 0xff; + ptr ++; + } + } + } + + /* set error code */ + rt_set_errno(err_code); + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; } static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - rt_err_t err_code; - struct avr32_serial_device* uart; - - err_code = RT_EOK; - ptr = (rt_uint8_t*)buffer; - uart = (struct avr32_serial_device*)dev->user_data; - - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - /* interrupt mode Tx, does not support */ - RT_ASSERT(0); - } - else - { - /* polling mode */ - if (dev->flag & RT_DEVICE_FLAG_STREAM) - { - /* stream mode */ - while (size) - { - usart_putchar(uart->uart_device, (int) *ptr); - - ++ptr; --size; - } - } - else - { - /* write data directly */ - while (size) - { - usart_bw_write_char(uart->uart_device, (int) *ptr); - - ++ptr; --size; - } - } - } - - /* set error code */ - rt_set_errno(err_code); - - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + rt_uint8_t* ptr; + rt_err_t err_code; + struct avr32_serial_device* uart; + + err_code = RT_EOK; + ptr = (rt_uint8_t*)buffer; + uart = (struct avr32_serial_device*)dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* interrupt mode Tx, does not support */ + RT_ASSERT(0); + } + else + { + /* polling mode */ + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* stream mode */ + while (size) + { + usart_putchar(uart->uart_device, (int) *ptr); + + ++ptr; --size; + } + } + else + { + /* write data directly */ + while (size) + { + usart_bw_write_char(uart->uart_device, (int) *ptr); + + ++ptr; --size; + } + } + } + + /* set error code */ + rt_set_errno(err_code); + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; } static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) { - struct avr32_serial_device* uart; + struct avr32_serial_device* uart; - RT_ASSERT(dev != RT_NULL); + RT_ASSERT(dev != RT_NULL); - uart = (struct avr32_serial_device*)dev->user_data; - switch (cmd) - { - case RT_DEVICE_CTRL_SUSPEND: - /* suspend device */ - dev->flag |= RT_DEVICE_FLAG_SUSPENDED; - break; + uart = (struct avr32_serial_device*)dev->user_data; + switch (cmd) + { + case RT_DEVICE_CTRL_SUSPEND: + /* suspend device */ + dev->flag |= RT_DEVICE_FLAG_SUSPENDED; + break; - case RT_DEVICE_CTRL_RESUME: - /* resume device */ - dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; - break; - } + case RT_DEVICE_CTRL_RESUME: + /* resume device */ + dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; + break; + } - return RT_EOK; + return RT_EOK; } /* @@ -201,77 +201,77 @@ static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) */ rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct avr32_serial_device *serial) { - RT_ASSERT(device != RT_NULL); - - if ((flag & RT_DEVICE_FLAG_DMA_RX) || - (flag & RT_DEVICE_FLAG_INT_TX)) - { - RT_ASSERT(0); - } - - device->type = RT_Device_Class_Char; - device->rx_indicate = RT_NULL; - device->tx_complete = RT_NULL; - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; - device->user_data = serial; - - /* register a character device */ - return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); + RT_ASSERT(device != RT_NULL); + + if ((flag & RT_DEVICE_FLAG_DMA_RX) || + (flag & RT_DEVICE_FLAG_INT_TX)) + { + RT_ASSERT(0); + } + + device->type = RT_Device_Class_Char; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; + device->user_data = serial; + + /* register a character device */ + return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); } /* ISR for serial interrupt */ void rt_hw_serial_isr(void) { - struct avr32_serial_device* uart = (struct avr32_serial_device*) _rt_usart_device.user_data; - rt_base_t level; - - if (usart_test_hit(uart->uart_device)) - { - /* interrupt mode receive */ - RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - /* save character */ - uart->int_rx->rx_buffer[uart->int_rx->save_index] = uart->uart_device->rhr & 0xff; - uart->int_rx->save_index ++; - if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->save_index = 0; - - /* if the next position is read index, discard this 'read char' */ - if (uart->int_rx->save_index == uart->int_rx->read_index) - { - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - - /* invoke callback */ - if (_rt_usart_device.rx_indicate != RT_NULL) - { - rt_size_t rx_length; - - /* get rx length */ - rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? - UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : - uart->int_rx->save_index - uart->int_rx->read_index; - - _rt_usart_device.rx_indicate(&_rt_usart_device, rx_length); - } - } - else - { - usart_reset_status(uart->uart_device); - } + struct avr32_serial_device* uart = (struct avr32_serial_device*) _rt_usart_device.user_data; + rt_base_t level; + + if (usart_test_hit(uart->uart_device)) + { + /* interrupt mode receive */ + RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + /* save character */ + uart->int_rx->rx_buffer[uart->int_rx->save_index] = uart->uart_device->rhr & 0xff; + uart->int_rx->save_index ++; + if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->save_index = 0; + + /* if the next position is read index, discard this 'read char' */ + if (uart->int_rx->save_index == uart->int_rx->read_index) + { + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + /* invoke callback */ + if (_rt_usart_device.rx_indicate != RT_NULL) + { + rt_size_t rx_length; + + /* get rx length */ + rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? + UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : + uart->int_rx->save_index - uart->int_rx->read_index; + + _rt_usart_device.rx_indicate(&_rt_usart_device, rx_length); + } + } + else + { + usart_reset_status(uart->uart_device); + } } /*@}*/ diff --git a/libcpu/avr32/uc3/serial.h b/libcpu/avr32/uc3/serial.h index a17338701b..fef65a12be 100644 --- a/libcpu/avr32/uc3/serial.h +++ b/libcpu/avr32/uc3/serial.h @@ -21,29 +21,29 @@ #include "compiler.h" #include "usart.h" -#define UART_RX_BUFFER_SIZE 64 -#define UART_TX_DMA_NODE_SIZE 4 +#define UART_RX_BUFFER_SIZE 64 +#define UART_TX_DMA_NODE_SIZE 4 /* data node for Tx Mode */ struct avr32_serial_data_node { - rt_uint8_t *data_ptr; - rt_size_t data_size; - struct avr32_serial_data_node *next, *prev; + rt_uint8_t *data_ptr; + rt_size_t data_size; + struct avr32_serial_data_node *next, *prev; }; struct avr32_serial_int_rx { - rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; - rt_uint32_t read_index, save_index; + rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; + rt_uint32_t read_index, save_index; }; struct avr32_serial_device { - avr32_usart_t *uart_device; + avr32_usart_t *uart_device; - /* rx structure */ - struct avr32_serial_int_rx* int_rx; + /* rx structure */ + struct avr32_serial_int_rx* int_rx; }; rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct avr32_serial_device *serial); diff --git a/libcpu/avr32/uc3/stack.c b/libcpu/avr32/uc3/stack.c index dd43b5edbc..dee1161c12 100644 --- a/libcpu/avr32/uc3/stack.c +++ b/libcpu/avr32/uc3/stack.c @@ -30,28 +30,28 @@ */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) { - unsigned long *stk; + unsigned long *stk; - stk = (unsigned long *)stack_addr; - *(stk) = 0; /* r8 */ - *(--stk) = 0; /* r9 */ - *(--stk) = 0; /* r10 */ - *(--stk) = 0; /* r11 */ - *(--stk) = 0; /* r12 */ - *(--stk) = (unsigned long)texit; /* lr */ - *(--stk) = (unsigned long)tentry; /* entry point, pc */ - *(--stk) = 0x00600000; /* sr */ - *(--stk) = 0; /* r0 */ - *(--stk) = 0; /* r1 */ - *(--stk) = 0; /* r2 */ - *(--stk) = 0; /* r3 */ - *(--stk) = 0; /* r4 */ - *(--stk) = 0; /* r5 */ - *(--stk) = 0; /* r6 */ - *(--stk) = 0; /* r7 */ + stk = (unsigned long *)stack_addr; + *(stk) = 0; /* r8 */ + *(--stk) = 0; /* r9 */ + *(--stk) = 0; /* r10 */ + *(--stk) = 0; /* r11 */ + *(--stk) = 0; /* r12 */ + *(--stk) = (unsigned long)texit; /* lr */ + *(--stk) = (unsigned long)tentry; /* entry point, pc */ + *(--stk) = 0x00600000; /* sr */ + *(--stk) = 0; /* r0 */ + *(--stk) = 0; /* r1 */ + *(--stk) = 0; /* r2 */ + *(--stk) = 0; /* r3 */ + *(--stk) = 0; /* r4 */ + *(--stk) = 0; /* r5 */ + *(--stk) = 0; /* r6 */ + *(--stk) = 0; /* r7 */ - /* return task's current stack address */ - return (rt_uint8_t *)stk; + /* return task's current stack address */ + return (rt_uint8_t *)stk; } /*@}*/ diff --git a/libcpu/blackfin/bf53x/cpuport.c b/libcpu/blackfin/bf53x/cpuport.c index 91cfaeb403..2d69ccc99a 100644 --- a/libcpu/blackfin/bf53x/cpuport.c +++ b/libcpu/blackfin/bf53x/cpuport.c @@ -8,8 +8,8 @@ * http://www.rt-thread.org/license/LICENSE * * Change Logs: - * Date Author Notes - * 2012-02-13 mojingxian first version + * Date Author Notes + * 2012-02-13 mojingxian first version */ #include @@ -23,10 +23,10 @@ rt_uint32_t rt_thread_switch_interrupt_flag; * initializes stack of thread */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) + rt_uint8_t *stack_addr, void *texit) { unsigned char i; - unsigned long *stk; + unsigned long *stk; stk = (unsigned long *)stack_addr; /* Load stack pointer */ diff --git a/libcpu/blackfin/bf53x/serial.c b/libcpu/blackfin/bf53x/serial.c index b8a4c52570..4a6484a647 100644 --- a/libcpu/blackfin/bf53x/serial.c +++ b/libcpu/blackfin/bf53x/serial.c @@ -29,206 +29,206 @@ */ static rt_err_t rt_serial_init (rt_device_t dev) { - struct serial_device* uart = (struct serial_device*) dev->user_data; - - if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) - { - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_memset(uart->int_rx->rx_buffer, 0, - sizeof(uart->int_rx->rx_buffer)); - uart->int_rx->read_index = uart->int_rx->save_index = 0; - } - - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - rt_memset(uart->int_tx->tx_buffer, 0, - sizeof(uart->int_tx->tx_buffer)); - uart->int_tx->write_index = uart->int_tx->save_index = 0; - } - - dev->flag |= RT_DEVICE_FLAG_ACTIVATED; - } - - return RT_EOK; + struct serial_device* uart = (struct serial_device*) dev->user_data; + + if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) + { + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_memset(uart->int_rx->rx_buffer, 0, + sizeof(uart->int_rx->rx_buffer)); + uart->int_rx->read_index = uart->int_rx->save_index = 0; + } + + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + rt_memset(uart->int_tx->tx_buffer, 0, + sizeof(uart->int_tx->tx_buffer)); + uart->int_tx->write_index = uart->int_tx->save_index = 0; + } + + dev->flag |= RT_DEVICE_FLAG_ACTIVATED; + } + + return RT_EOK; } /* save a char to serial buffer */ static void rt_serial_savechar(struct serial_device* uart, char ch) { - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch; - uart->int_rx->save_index ++; - if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->save_index = 0; - - /* if the next position is read index, discard this 'read char' */ - if (uart->int_rx->save_index == uart->int_rx->read_index) - { - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch; + uart->int_rx->save_index ++; + if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->save_index = 0; + + /* if the next position is read index, discard this 'read char' */ + if (uart->int_rx->save_index == uart->int_rx->read_index) + { + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); } static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) -{ - RT_ASSERT(dev != RT_NULL); - - return RT_EOK; +{ + RT_ASSERT(dev != RT_NULL); + + return RT_EOK; } static rt_err_t rt_serial_close(rt_device_t dev) -{ - RT_ASSERT(dev != RT_NULL); +{ + RT_ASSERT(dev != RT_NULL); - return RT_EOK; + return RT_EOK; } static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - rt_err_t err_code; - struct serial_device* uart; - - ptr = buffer; - err_code = RT_EOK; - uart = (struct serial_device*)dev->user_data; - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_base_t level; - - /* interrupt mode Rx */ - while (size) - { - if (uart->int_rx->read_index != uart->int_rx->save_index) - { - *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; - size --; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } - else - { - /* set error code */ - err_code = -RT_EEMPTY; - break; - } - } - } - else - { - /* polling mode */ - while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) - { - //while (uart->uart_device->ustat & USTAT_RCV_READY) - { - *ptr = uart->uart_device->rbr_thr & 0xff; - ptr ++; - } - } - } - - /* set error code */ - rt_set_errno(err_code); - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + rt_uint8_t* ptr; + rt_err_t err_code; + struct serial_device* uart; + + ptr = buffer; + err_code = RT_EOK; + uart = (struct serial_device*)dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_base_t level; + + /* interrupt mode Rx */ + while (size) + { + if (uart->int_rx->read_index != uart->int_rx->save_index) + { + *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; + size --; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + else + { + /* set error code */ + err_code = -RT_EEMPTY; + break; + } + } + } + else + { + /* polling mode */ + while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) + { + //while (uart->uart_device->ustat & USTAT_RCV_READY) + { + *ptr = uart->uart_device->rbr_thr & 0xff; + ptr ++; + } + } + } + + /* set error code */ + rt_set_errno(err_code); + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; } static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - rt_err_t err_code; - struct serial_device* uart; - - err_code = RT_EOK; - ptr = (rt_uint8_t*)buffer; - uart = (struct serial_device*)dev->user_data; - - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - /* interrupt mode Tx */ - while (uart->int_tx->save_index != uart->int_tx->write_index) - { - /* save on tx buffer */ - uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++; - - -- size; - - /* move to next position */ - uart->int_tx->save_index ++; - - /* wrap save index */ - if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE) - uart->int_tx->save_index = 0; - } - - /* set error code */ - if (size > 0) - err_code = -RT_EFULL; - } - else - { - /* polling mode */ - while (size) - { - /* - * to be polite with serial console add a line feed - * to the carriage return character - */ - if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM)) - { - while (!(uart->uart_device->lsr & 0x20)); - uart->uart_device->rbr_thr = '\r'; - } - - while (!(uart->uart_device->lsr & 0x20)); - uart->uart_device->rbr_thr = (*ptr & 0xFF); - - ++ptr; --size; - } - } - - /* set error code */ - rt_set_errno(err_code); - - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + rt_uint8_t* ptr; + rt_err_t err_code; + struct serial_device* uart; + + err_code = RT_EOK; + ptr = (rt_uint8_t*)buffer; + uart = (struct serial_device*)dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* interrupt mode Tx */ + while (uart->int_tx->save_index != uart->int_tx->write_index) + { + /* save on tx buffer */ + uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++; + + -- size; + + /* move to next position */ + uart->int_tx->save_index ++; + + /* wrap save index */ + if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE) + uart->int_tx->save_index = 0; + } + + /* set error code */ + if (size > 0) + err_code = -RT_EFULL; + } + else + { + /* polling mode */ + while (size) + { + /* + * to be polite with serial console add a line feed + * to the carriage return character + */ + if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM)) + { + while (!(uart->uart_device->lsr & 0x20)); + uart->uart_device->rbr_thr = '\r'; + } + + while (!(uart->uart_device->lsr & 0x20)); + uart->uart_device->rbr_thr = (*ptr & 0xFF); + + ++ptr; --size; + } + } + + /* set error code */ + rt_set_errno(err_code); + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; } static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) { - RT_ASSERT(dev != RT_NULL); - - switch (cmd) - { - case RT_DEVICE_CTRL_SUSPEND: - /* suspend device */ - dev->flag |= RT_DEVICE_FLAG_SUSPENDED; - break; - - case RT_DEVICE_CTRL_RESUME: - /* resume device */ - dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; - break; - } - - return RT_EOK; + RT_ASSERT(dev != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_SUSPEND: + /* suspend device */ + dev->flag |= RT_DEVICE_FLAG_SUSPENDED; + break; + + case RT_DEVICE_CTRL_RESUME: + /* resume device */ + dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; + break; + } + + return RT_EOK; } /* @@ -236,49 +236,49 @@ static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) */ rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial) { - RT_ASSERT(device != RT_NULL); - - device->type = RT_Device_Class_Char; - device->rx_indicate = RT_NULL; - device->tx_complete = RT_NULL; - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; - device->user_data = serial; - - /* register a character device */ - return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); + RT_ASSERT(device != RT_NULL); + + device->type = RT_Device_Class_Char; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; + device->user_data = serial; + + /* register a character device */ + return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); } - + /* ISR for serial interrupt */ void rt_hw_serial_isr(rt_device_t device) { - struct serial_device* uart = (struct serial_device*) device->user_data; - - /* interrupt mode receive */ - RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); - - /* save on rx buffer */ - //while (uart->uart_device->ustat & USTAT_RCV_READY) - { - rt_serial_savechar(uart, uart->uart_device->rbr_thr & 0xff); - } - - /* invoke callback */ - if (device->rx_indicate != RT_NULL) - { - rt_size_t rx_length; - - /* get rx length */ - rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? - UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : - uart->int_rx->save_index - uart->int_rx->read_index; - - device->rx_indicate(device, rx_length); - } + struct serial_device* uart = (struct serial_device*) device->user_data; + + /* interrupt mode receive */ + RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); + + /* save on rx buffer */ + //while (uart->uart_device->ustat & USTAT_RCV_READY) + { + rt_serial_savechar(uart, uart->uart_device->rbr_thr & 0xff); + } + + /* invoke callback */ + if (device->rx_indicate != RT_NULL) + { + rt_size_t rx_length; + + /* get rx length */ + rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? + UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : + uart->int_rx->save_index - uart->int_rx->read_index; + + device->rx_indicate(device, rx_length); + } } /*@}*/ diff --git a/libcpu/ia32/__udivsi3.c b/libcpu/ia32/__udivsi3.c index ec7c59d1cb..506dc2ddd5 100644 --- a/libcpu/ia32/__udivsi3.c +++ b/libcpu/ia32/__udivsi3.c @@ -16,31 +16,31 @@ uint32_t __udivsi3(uint32_t num, uint32_t den) { - uint32_t quot = 0, qbit = 1; + uint32_t quot = 0, qbit = 1; - if (den == 0) - { - asm volatile ("int $0"); - return 0; /* If trap returns... */ - } + if (den == 0) + { + asm volatile ("int $0"); + return 0; /* If trap returns... */ + } - /* Left-justify denominator and count shift */ - while ((int32_t) den >= 0) - { - den <<= 1; - qbit <<= 1; - } + /* Left-justify denominator and count shift */ + while ((int32_t) den >= 0) + { + den <<= 1; + qbit <<= 1; + } - while (qbit) - { - if (den <= num) - { - num -= den; - quot += qbit; - } - den >>= 1; - qbit >>= 1; - } + while (qbit) + { + if (den <= num) + { + num -= den; + quot += qbit; + } + den >>= 1; + qbit >>= 1; + } - return quot; + return quot; } diff --git a/libcpu/ia32/__umodsi3.c b/libcpu/ia32/__umodsi3.c index 226a2c0800..101db9debd 100644 --- a/libcpu/ia32/__umodsi3.c +++ b/libcpu/ia32/__umodsi3.c @@ -16,31 +16,31 @@ uint32_t __umodsi3(uint32_t num, uint32_t den) { - register uint32_t quot = 0, qbit = 1; + register uint32_t quot = 0, qbit = 1; - if (den == 0) - { - asm volatile ("int $0"); - return 0; /* if trap returns... */ - } + if (den == 0) + { + asm volatile ("int $0"); + return 0; /* if trap returns... */ + } - /* left-justify denominator and count shift */ - while ((int32_t) den >= 0) - { - den <<= 1; - qbit <<= 1; - } + /* left-justify denominator and count shift */ + while ((int32_t) den >= 0) + { + den <<= 1; + qbit <<= 1; + } - while (qbit) - { - if (den <= num) - { - num -= den; - quot += qbit; - } - den >>= 1; - qbit >>= 1; - } + while (qbit) + { + if (den <= num) + { + num -= den; + quot += qbit; + } + den >>= 1; + qbit >>= 1; + } - return num; + return num; } diff --git a/libcpu/ia32/backtrace.c b/libcpu/ia32/backtrace.c index b8f094d90f..ee90ae71ca 100644 --- a/libcpu/ia32/backtrace.c +++ b/libcpu/ia32/backtrace.c @@ -16,5 +16,5 @@ void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry) { - /* no implementation */ + /* no implementation */ } diff --git a/libcpu/ia32/interrupt.c b/libcpu/ia32/interrupt.c index 82a5aa3791..f14a9a3ca1 100644 --- a/libcpu/ia32/interrupt.c +++ b/libcpu/ia32/interrupt.c @@ -7,7 +7,7 @@ * Date Author Notes * 2015/9/15 Bernard Update to new interrupt framework. */ - + #include #include @@ -36,45 +36,45 @@ void rt_hw_interrupt_handle(int vector, void* param); */ void rt_hw_pic_init() { - outb(IO_PIC1, 0x11); - outb(IO_PIC1+1, IRQ_OFFSET); - outb(IO_PIC1+1, 1<> 8)); - } - - /* init interrupt nest, and context */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + outb(IO_PIC1, 0x11); + outb(IO_PIC1+1, IRQ_OFFSET); + outb(IO_PIC1+1, 1<> 8)); + } + + /* init interrupt nest, and context */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; } void rt_hw_interrupt_handle(int vector, void* param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } void rt_hw_isr(int vector) { - if (vector < MAX_HANDLERS) - { - irq_desc[vector].handler(vector, irq_desc[vector].param); - } + if (vector < MAX_HANDLERS) + { + irq_desc[vector].handler(vector, irq_desc[vector].param); + } } /** @@ -83,10 +83,10 @@ void rt_hw_isr(int vector) */ void rt_hw_interrupt_init(void) { - int idx; - - rt_hw_idt_init(); - rt_hw_pic_init(); + int idx; + + rt_hw_idt_init(); + rt_hw_pic_init(); /* init exceptions table */ for(idx=0; idx < MAX_HANDLERS; idx++) @@ -102,16 +102,16 @@ void rt_hw_interrupt_init(void) void rt_hw_interrupt_umask(int vector) { - irq_mask_8259A = irq_mask_8259A&~(1<> 8)); + irq_mask_8259A = irq_mask_8259A&~(1<> 8)); } void rt_hw_interrupt_mask(int vector) { - irq_mask_8259A = irq_mask_8259A | (1<> 8)); + irq_mask_8259A = irq_mask_8259A | (1<> 8)); } rt_isr_handler_t rt_hw_interrupt_install(int vector, @@ -140,15 +140,15 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_base_t rt_hw_interrupt_disable(void) { - rt_base_t level; + rt_base_t level; - __asm__ __volatile__("pushfl ; popl %0 ; cli":"=g" (level): :"memory"); - return level; + __asm__ __volatile__("pushfl ; popl %0 ; cli":"=g" (level): :"memory"); + return level; } void rt_hw_interrupt_enable(rt_base_t level) { - __asm__ __volatile__("pushl %0 ; popfl": :"g" (level):"memory", "cc"); + __asm__ __volatile__("pushl %0 ; popfl": :"g" (level):"memory", "cc"); } /*@}*/ diff --git a/libcpu/ia32/showmem.c b/libcpu/ia32/showmem.c index 38f037f83d..5374a3ad48 100644 --- a/libcpu/ia32/showmem.c +++ b/libcpu/ia32/showmem.c @@ -16,27 +16,27 @@ void rt_hw_show_memory(rt_uint32_t addr, rt_uint32_t size) { - int i = 0, j =0; + int i = 0, j =0; - RT_ASSERT(addr); + RT_ASSERT(addr); - addr = addr & ~0xF; - size = 4*((size + 3)/4); + addr = addr & ~0xF; + size = 4*((size + 3)/4); - while(i < size) - { - rt_kprintf("0x%08x: ", addr ); + while(i < size) + { + rt_kprintf("0x%08x: ", addr ); - for(j=0; j<4; j++) - { - rt_kprintf("0x%08x ", *(rt_uint32_t *)addr); + for(j=0; j<4; j++) + { + rt_kprintf("0x%08x ", *(rt_uint32_t *)addr); - addr += 4; - i++; - } + addr += 4; + i++; + } - rt_kprintf("\n"); - } + rt_kprintf("\n"); + } - return; + return; } diff --git a/libcpu/ia32/stack.c b/libcpu/ia32/stack.c index 9d656a73d6..a533b94076 100644 --- a/libcpu/ia32/stack.c +++ b/libcpu/ia32/stack.c @@ -10,7 +10,7 @@ * Change Logs: * Date Author Notes */ - + #include #include @@ -24,36 +24,36 @@ * This function will initialize thread stack * * @param tentry the entry of thread - * @param parameter the parameter of entry + * @param parameter the parameter of entry * @param stack_addr the beginning stack address * @param texit the function will be called when thread exit * * @return stack address */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) + rt_uint8_t *stack_addr, void *texit) { - unsigned long *stk; + unsigned long *stk; - stk = (unsigned long *)stack_addr; - *(--stk) = (unsigned long)parameter; - *(--stk) = (unsigned long)texit; - *(--stk) = 0x200; /*flags*/ - *(--stk) = 0x08; /*cs*/ - *(--stk) = (unsigned long)tentry; /*eip*/ - *(--stk) = 0; /*irqno*/ - *(--stk) = 0x10; /*ds*/ - *(--stk) = 0x10; /*es*/ - *(--stk) = 0; /*eax*/ - *(--stk) = 0; /*ecx*/ - *(--stk) = 0; /*edx*/ - *(--stk) = 0; /*ebx*/ - *(--stk) = 0; /*esp*/ - *(--stk) = 0; /*ebp*/ - *(--stk) = 0; /*esi*/ - *(--stk) = 0; /*edi*/ + stk = (unsigned long *)stack_addr; + *(--stk) = (unsigned long)parameter; + *(--stk) = (unsigned long)texit; + *(--stk) = 0x200; /*flags*/ + *(--stk) = 0x08; /*cs*/ + *(--stk) = (unsigned long)tentry; /*eip*/ + *(--stk) = 0; /*irqno*/ + *(--stk) = 0x10; /*ds*/ + *(--stk) = 0x10; /*es*/ + *(--stk) = 0; /*eax*/ + *(--stk) = 0; /*ecx*/ + *(--stk) = 0; /*edx*/ + *(--stk) = 0; /*ebx*/ + *(--stk) = 0; /*esp*/ + *(--stk) = 0; /*ebp*/ + *(--stk) = 0; /*esi*/ + *(--stk) = 0; /*edi*/ - /* return task's current stack address */ - return (rt_uint8_t *)stk; + /* return task's current stack address */ + return (rt_uint8_t *)stk; } /*@}*/ diff --git a/libcpu/ia32/trap.c b/libcpu/ia32/trap.c index 5e9a51d6d2..b3484cfd58 100644 --- a/libcpu/ia32/trap.c +++ b/libcpu/ia32/trap.c @@ -22,7 +22,7 @@ struct Gatedesc idt[256] = { {0}, }; struct Pseudodesc idt_pd = { - 0, sizeof(idt) - 1, (unsigned long) idt, + 0, sizeof(idt) - 1, (unsigned long) idt, }; /* exception and interrupt handler table */ @@ -40,36 +40,36 @@ extern rt_isr_handler_t hdinterrupt_func[]; * */ void rt_hw_idt_init(void) -{ - extern void Xdefault; - int i, j, func; +{ + extern void Xdefault; + int i, j, func; + + // install a default handler + for (i = 0; i < sizeof(idt)/sizeof(idt[0]); i++) + SETGATE(idt[i], 0, GD_KT, &Xdefault, 0); + + /*install trap handler*/ + for(i = 0; i < 16; i++) + { + func = (int)trap_func[i]; + SETGATE(idt[i], 0, GD_KT, func, 0); + } - // install a default handler - for (i = 0; i < sizeof(idt)/sizeof(idt[0]); i++) - SETGATE(idt[i], 0, GD_KT, &Xdefault, 0); + func = (int)trap_func[3]; + SETGATE(idt[3], 0, GD_KT, func, 3); - /*install trap handler*/ - for(i = 0; i < 16; i++) - { - func = (int)trap_func[i]; - SETGATE(idt[i], 0, GD_KT, func, 0); - } + i = 0; - func = (int)trap_func[3]; - SETGATE(idt[3], 0, GD_KT, func, 3); + /*install exteral interrupt handler*/ + for(j = IRQ_OFFSET; j < IRQ_OFFSET + MAX_HANDLERS; j++) + { + func = (int)hdinterrupt_func[i]; + SETGATE(idt[j], 0, GD_KT, func, 0); + i++; + } - i = 0; - - /*install exteral interrupt handler*/ - for(j = IRQ_OFFSET; j < IRQ_OFFSET + MAX_HANDLERS; j++) - { - func = (int)hdinterrupt_func[i]; - SETGATE(idt[j], 0, GD_KT, func, 0); - i++; - } - - // Load the IDT - asm volatile("lidt idt_pd + 2"); + // Load the IDT + asm volatile("lidt idt_pd + 2"); } /** @@ -80,24 +80,24 @@ void rt_hw_idt_init(void) */ void rt_hw_trap_irq(int trapno) { - switch(trapno) - { - case T_DIVIDE: - rt_kprintf("Divide error interrupt\n"); - RT_ASSERT(0); - case T_PGFLT: - rt_kprintf("Page fault interrupt\n"); - RT_ASSERT(0); - case T_GPFLT: - rt_kprintf("General protection interrupt\n"); - RT_ASSERT(0); - case T_DEFAULT: - rt_hw_interrupt_handle(T_DEFAULT); - return; - } + switch(trapno) + { + case T_DIVIDE: + rt_kprintf("Divide error interrupt\n"); + RT_ASSERT(0); + case T_PGFLT: + rt_kprintf("Page fault interrupt\n"); + RT_ASSERT(0); + case T_GPFLT: + rt_kprintf("General protection interrupt\n"); + RT_ASSERT(0); + case T_DEFAULT: + rt_hw_interrupt_handle(T_DEFAULT); + return; + } - /*kernel bug if run here*/ - RT_ASSERT(0); + /*kernel bug if run here*/ + RT_ASSERT(0); } /*@}*/ diff --git a/libcpu/m16c/m16c62p/cpuport.c b/libcpu/m16c/m16c62p/cpuport.c index c66f73b727..8f9a50d89a 100644 --- a/libcpu/m16c/m16c62p/cpuport.c +++ b/libcpu/m16c/m16c62p/cpuport.c @@ -113,4 +113,4 @@ void rt_hw_interrupt_enable(rt_base_t level) temp = level & 0xffff; asm("LDC %0, FLG": :"r" (temp)); } -#endif \ No newline at end of file +#endif diff --git a/libcpu/mips/common/exception.h b/libcpu/mips/common/exception.h index 2cb03d20e7..77fdb4a659 100644 --- a/libcpu/mips/common/exception.h +++ b/libcpu/mips/common/exception.h @@ -18,9 +18,9 @@ /* * important register numbers */ -#define REG_EPC 37 -#define REG_FP 72 -#define REG_SP 29 +#define REG_EPC 37 +#define REG_FP 72 +#define REG_SP 29 /* * Stack layout for the GDB exception handler @@ -28,117 +28,117 @@ * * The first PTRSIZE*6 bytes are argument save space for C subroutines. */ -#define NUMREGS 90 +#define NUMREGS 90 -#define GDB_FR_REG0 (PTRSIZE*6) /* 0 */ -#define GDB_FR_REG1 ((GDB_FR_REG0) + LONGSIZE) /* 1 */ -#define GDB_FR_REG2 ((GDB_FR_REG1) + LONGSIZE) /* 2 */ -#define GDB_FR_REG3 ((GDB_FR_REG2) + LONGSIZE) /* 3 */ -#define GDB_FR_REG4 ((GDB_FR_REG3) + LONGSIZE) /* 4 */ -#define GDB_FR_REG5 ((GDB_FR_REG4) + LONGSIZE) /* 5 */ -#define GDB_FR_REG6 ((GDB_FR_REG5) + LONGSIZE) /* 6 */ -#define GDB_FR_REG7 ((GDB_FR_REG6) + LONGSIZE) /* 7 */ -#define GDB_FR_REG8 ((GDB_FR_REG7) + LONGSIZE) /* 8 */ -#define GDB_FR_REG9 ((GDB_FR_REG8) + LONGSIZE) /* 9 */ -#define GDB_FR_REG10 ((GDB_FR_REG9) + LONGSIZE) /* 10 */ -#define GDB_FR_REG11 ((GDB_FR_REG10) + LONGSIZE) /* 11 */ -#define GDB_FR_REG12 ((GDB_FR_REG11) + LONGSIZE) /* 12 */ -#define GDB_FR_REG13 ((GDB_FR_REG12) + LONGSIZE) /* 13 */ -#define GDB_FR_REG14 ((GDB_FR_REG13) + LONGSIZE) /* 14 */ -#define GDB_FR_REG15 ((GDB_FR_REG14) + LONGSIZE) /* 15 */ -#define GDB_FR_REG16 ((GDB_FR_REG15) + LONGSIZE) /* 16 */ -#define GDB_FR_REG17 ((GDB_FR_REG16) + LONGSIZE) /* 17 */ -#define GDB_FR_REG18 ((GDB_FR_REG17) + LONGSIZE) /* 18 */ -#define GDB_FR_REG19 ((GDB_FR_REG18) + LONGSIZE) /* 19 */ -#define GDB_FR_REG20 ((GDB_FR_REG19) + LONGSIZE) /* 20 */ -#define GDB_FR_REG21 ((GDB_FR_REG20) + LONGSIZE) /* 21 */ -#define GDB_FR_REG22 ((GDB_FR_REG21) + LONGSIZE) /* 22 */ -#define GDB_FR_REG23 ((GDB_FR_REG22) + LONGSIZE) /* 23 */ -#define GDB_FR_REG24 ((GDB_FR_REG23) + LONGSIZE) /* 24 */ -#define GDB_FR_REG25 ((GDB_FR_REG24) + LONGSIZE) /* 25 */ -#define GDB_FR_REG26 ((GDB_FR_REG25) + LONGSIZE) /* 26 */ -#define GDB_FR_REG27 ((GDB_FR_REG26) + LONGSIZE) /* 27 */ -#define GDB_FR_REG28 ((GDB_FR_REG27) + LONGSIZE) /* 28 */ -#define GDB_FR_REG29 ((GDB_FR_REG28) + LONGSIZE) /* 29 */ -#define GDB_FR_REG30 ((GDB_FR_REG29) + LONGSIZE) /* 30 */ -#define GDB_FR_REG31 ((GDB_FR_REG30) + LONGSIZE) /* 31 */ +#define GDB_FR_REG0 (PTRSIZE*6) /* 0 */ +#define GDB_FR_REG1 ((GDB_FR_REG0) + LONGSIZE) /* 1 */ +#define GDB_FR_REG2 ((GDB_FR_REG1) + LONGSIZE) /* 2 */ +#define GDB_FR_REG3 ((GDB_FR_REG2) + LONGSIZE) /* 3 */ +#define GDB_FR_REG4 ((GDB_FR_REG3) + LONGSIZE) /* 4 */ +#define GDB_FR_REG5 ((GDB_FR_REG4) + LONGSIZE) /* 5 */ +#define GDB_FR_REG6 ((GDB_FR_REG5) + LONGSIZE) /* 6 */ +#define GDB_FR_REG7 ((GDB_FR_REG6) + LONGSIZE) /* 7 */ +#define GDB_FR_REG8 ((GDB_FR_REG7) + LONGSIZE) /* 8 */ +#define GDB_FR_REG9 ((GDB_FR_REG8) + LONGSIZE) /* 9 */ +#define GDB_FR_REG10 ((GDB_FR_REG9) + LONGSIZE) /* 10 */ +#define GDB_FR_REG11 ((GDB_FR_REG10) + LONGSIZE) /* 11 */ +#define GDB_FR_REG12 ((GDB_FR_REG11) + LONGSIZE) /* 12 */ +#define GDB_FR_REG13 ((GDB_FR_REG12) + LONGSIZE) /* 13 */ +#define GDB_FR_REG14 ((GDB_FR_REG13) + LONGSIZE) /* 14 */ +#define GDB_FR_REG15 ((GDB_FR_REG14) + LONGSIZE) /* 15 */ +#define GDB_FR_REG16 ((GDB_FR_REG15) + LONGSIZE) /* 16 */ +#define GDB_FR_REG17 ((GDB_FR_REG16) + LONGSIZE) /* 17 */ +#define GDB_FR_REG18 ((GDB_FR_REG17) + LONGSIZE) /* 18 */ +#define GDB_FR_REG19 ((GDB_FR_REG18) + LONGSIZE) /* 19 */ +#define GDB_FR_REG20 ((GDB_FR_REG19) + LONGSIZE) /* 20 */ +#define GDB_FR_REG21 ((GDB_FR_REG20) + LONGSIZE) /* 21 */ +#define GDB_FR_REG22 ((GDB_FR_REG21) + LONGSIZE) /* 22 */ +#define GDB_FR_REG23 ((GDB_FR_REG22) + LONGSIZE) /* 23 */ +#define GDB_FR_REG24 ((GDB_FR_REG23) + LONGSIZE) /* 24 */ +#define GDB_FR_REG25 ((GDB_FR_REG24) + LONGSIZE) /* 25 */ +#define GDB_FR_REG26 ((GDB_FR_REG25) + LONGSIZE) /* 26 */ +#define GDB_FR_REG27 ((GDB_FR_REG26) + LONGSIZE) /* 27 */ +#define GDB_FR_REG28 ((GDB_FR_REG27) + LONGSIZE) /* 28 */ +#define GDB_FR_REG29 ((GDB_FR_REG28) + LONGSIZE) /* 29 */ +#define GDB_FR_REG30 ((GDB_FR_REG29) + LONGSIZE) /* 30 */ +#define GDB_FR_REG31 ((GDB_FR_REG30) + LONGSIZE) /* 31 */ /* * Saved special registers */ -#define GDB_FR_STATUS ((GDB_FR_REG31) + LONGSIZE) /* 32 */ -#define GDB_FR_LO ((GDB_FR_STATUS) + LONGSIZE) /* 33 */ -#define GDB_FR_HI ((GDB_FR_LO) + LONGSIZE) /* 34 */ -#define GDB_FR_BADVADDR ((GDB_FR_HI) + LONGSIZE) /* 35 */ -#define GDB_FR_CAUSE ((GDB_FR_BADVADDR) + LONGSIZE) /* 36 */ -#define GDB_FR_EPC ((GDB_FR_CAUSE) + LONGSIZE) /* 37 */ +#define GDB_FR_STATUS ((GDB_FR_REG31) + LONGSIZE) /* 32 */ +#define GDB_FR_LO ((GDB_FR_STATUS) + LONGSIZE) /* 33 */ +#define GDB_FR_HI ((GDB_FR_LO) + LONGSIZE) /* 34 */ +#define GDB_FR_BADVADDR ((GDB_FR_HI) + LONGSIZE) /* 35 */ +#define GDB_FR_CAUSE ((GDB_FR_BADVADDR) + LONGSIZE) /* 36 */ +#define GDB_FR_EPC ((GDB_FR_CAUSE) + LONGSIZE) /* 37 */ ///* // * Saved floating point registers // */ -//#define GDB_FR_FPR0 ((GDB_FR_EPC) + LONGSIZE) /* 38 */ -//#define GDB_FR_FPR1 ((GDB_FR_FPR0) + LONGSIZE) /* 39 */ -//#define GDB_FR_FPR2 ((GDB_FR_FPR1) + LONGSIZE) /* 40 */ -//#define GDB_FR_FPR3 ((GDB_FR_FPR2) + LONGSIZE) /* 41 */ -//#define GDB_FR_FPR4 ((GDB_FR_FPR3) + LONGSIZE) /* 42 */ -//#define GDB_FR_FPR5 ((GDB_FR_FPR4) + LONGSIZE) /* 43 */ -//#define GDB_FR_FPR6 ((GDB_FR_FPR5) + LONGSIZE) /* 44 */ -//#define GDB_FR_FPR7 ((GDB_FR_FPR6) + LONGSIZE) /* 45 */ -//#define GDB_FR_FPR8 ((GDB_FR_FPR7) + LONGSIZE) /* 46 */ -//#define GDB_FR_FPR9 ((GDB_FR_FPR8) + LONGSIZE) /* 47 */ -//#define GDB_FR_FPR10 ((GDB_FR_FPR9) + LONGSIZE) /* 48 */ -//#define GDB_FR_FPR11 ((GDB_FR_FPR10) + LONGSIZE) /* 49 */ -//#define GDB_FR_FPR12 ((GDB_FR_FPR11) + LONGSIZE) /* 50 */ -//#define GDB_FR_FPR13 ((GDB_FR_FPR12) + LONGSIZE) /* 51 */ -//#define GDB_FR_FPR14 ((GDB_FR_FPR13) + LONGSIZE) /* 52 */ -//#define GDB_FR_FPR15 ((GDB_FR_FPR14) + LONGSIZE) /* 53 */ -//#define GDB_FR_FPR16 ((GDB_FR_FPR15) + LONGSIZE) /* 54 */ -//#define GDB_FR_FPR17 ((GDB_FR_FPR16) + LONGSIZE) /* 55 */ -//#define GDB_FR_FPR18 ((GDB_FR_FPR17) + LONGSIZE) /* 56 */ -//#define GDB_FR_FPR19 ((GDB_FR_FPR18) + LONGSIZE) /* 57 */ -//#define GDB_FR_FPR20 ((GDB_FR_FPR19) + LONGSIZE) /* 58 */ -//#define GDB_FR_FPR21 ((GDB_FR_FPR20) + LONGSIZE) /* 59 */ -//#define GDB_FR_FPR22 ((GDB_FR_FPR21) + LONGSIZE) /* 60 */ -//#define GDB_FR_FPR23 ((GDB_FR_FPR22) + LONGSIZE) /* 61 */ -//#define GDB_FR_FPR24 ((GDB_FR_FPR23) + LONGSIZE) /* 62 */ -//#define GDB_FR_FPR25 ((GDB_FR_FPR24) + LONGSIZE) /* 63 */ -//#define GDB_FR_FPR26 ((GDB_FR_FPR25) + LONGSIZE) /* 64 */ -//#define GDB_FR_FPR27 ((GDB_FR_FPR26) + LONGSIZE) /* 65 */ -//#define GDB_FR_FPR28 ((GDB_FR_FPR27) + LONGSIZE) /* 66 */ -//#define GDB_FR_FPR29 ((GDB_FR_FPR28) + LONGSIZE) /* 67 */ -//#define GDB_FR_FPR30 ((GDB_FR_FPR29) + LONGSIZE) /* 68 */ -//#define GDB_FR_FPR31 ((GDB_FR_FPR30) + LONGSIZE) /* 69 */ +//#define GDB_FR_FPR0 ((GDB_FR_EPC) + LONGSIZE) /* 38 */ +//#define GDB_FR_FPR1 ((GDB_FR_FPR0) + LONGSIZE) /* 39 */ +//#define GDB_FR_FPR2 ((GDB_FR_FPR1) + LONGSIZE) /* 40 */ +//#define GDB_FR_FPR3 ((GDB_FR_FPR2) + LONGSIZE) /* 41 */ +//#define GDB_FR_FPR4 ((GDB_FR_FPR3) + LONGSIZE) /* 42 */ +//#define GDB_FR_FPR5 ((GDB_FR_FPR4) + LONGSIZE) /* 43 */ +//#define GDB_FR_FPR6 ((GDB_FR_FPR5) + LONGSIZE) /* 44 */ +//#define GDB_FR_FPR7 ((GDB_FR_FPR6) + LONGSIZE) /* 45 */ +//#define GDB_FR_FPR8 ((GDB_FR_FPR7) + LONGSIZE) /* 46 */ +//#define GDB_FR_FPR9 ((GDB_FR_FPR8) + LONGSIZE) /* 47 */ +//#define GDB_FR_FPR10 ((GDB_FR_FPR9) + LONGSIZE) /* 48 */ +//#define GDB_FR_FPR11 ((GDB_FR_FPR10) + LONGSIZE) /* 49 */ +//#define GDB_FR_FPR12 ((GDB_FR_FPR11) + LONGSIZE) /* 50 */ +//#define GDB_FR_FPR13 ((GDB_FR_FPR12) + LONGSIZE) /* 51 */ +//#define GDB_FR_FPR14 ((GDB_FR_FPR13) + LONGSIZE) /* 52 */ +//#define GDB_FR_FPR15 ((GDB_FR_FPR14) + LONGSIZE) /* 53 */ +//#define GDB_FR_FPR16 ((GDB_FR_FPR15) + LONGSIZE) /* 54 */ +//#define GDB_FR_FPR17 ((GDB_FR_FPR16) + LONGSIZE) /* 55 */ +//#define GDB_FR_FPR18 ((GDB_FR_FPR17) + LONGSIZE) /* 56 */ +//#define GDB_FR_FPR19 ((GDB_FR_FPR18) + LONGSIZE) /* 57 */ +//#define GDB_FR_FPR20 ((GDB_FR_FPR19) + LONGSIZE) /* 58 */ +//#define GDB_FR_FPR21 ((GDB_FR_FPR20) + LONGSIZE) /* 59 */ +//#define GDB_FR_FPR22 ((GDB_FR_FPR21) + LONGSIZE) /* 60 */ +//#define GDB_FR_FPR23 ((GDB_FR_FPR22) + LONGSIZE) /* 61 */ +//#define GDB_FR_FPR24 ((GDB_FR_FPR23) + LONGSIZE) /* 62 */ +//#define GDB_FR_FPR25 ((GDB_FR_FPR24) + LONGSIZE) /* 63 */ +//#define GDB_FR_FPR26 ((GDB_FR_FPR25) + LONGSIZE) /* 64 */ +//#define GDB_FR_FPR27 ((GDB_FR_FPR26) + LONGSIZE) /* 65 */ +//#define GDB_FR_FPR28 ((GDB_FR_FPR27) + LONGSIZE) /* 66 */ +//#define GDB_FR_FPR29 ((GDB_FR_FPR28) + LONGSIZE) /* 67 */ +//#define GDB_FR_FPR30 ((GDB_FR_FPR29) + LONGSIZE) /* 68 */ +//#define GDB_FR_FPR31 ((GDB_FR_FPR30) + LONGSIZE) /* 69 */ // -//#define GDB_FR_FSR ((GDB_FR_FPR31) + LONGSIZE) /* 70 */ -//#define GDB_FR_FIR ((GDB_FR_FSR) + LONGSIZE) /* 71 */ -//#define GDB_FR_FRP ((GDB_FR_FIR) + LONGSIZE) /* 72 */ +//#define GDB_FR_FSR ((GDB_FR_FPR31) + LONGSIZE) /* 70 */ +//#define GDB_FR_FIR ((GDB_FR_FSR) + LONGSIZE) /* 71 */ +//#define GDB_FR_FRP ((GDB_FR_FIR) + LONGSIZE) /* 72 */ // -//#define GDB_FR_DUMMY ((GDB_FR_FRP) + LONGSIZE) /* 73, unused ??? */ +//#define GDB_FR_DUMMY ((GDB_FR_FRP) + LONGSIZE) /* 73, unused ??? */ // ///* // * Again, CP0 registers // */ -//#define GDB_FR_CP0_INDEX ((GDB_FR_DUMMY) + LONGSIZE) /* 74 */ -#define GDB_FR_FRP ((GDB_FR_EPC) + LONGSIZE) /* 72 */ -#define GDB_FR_CP0_INDEX ((GDB_FR_FRP) + LONGSIZE) /* 74 */ +//#define GDB_FR_CP0_INDEX ((GDB_FR_DUMMY) + LONGSIZE) /* 74 */ +#define GDB_FR_FRP ((GDB_FR_EPC) + LONGSIZE) /* 72 */ +#define GDB_FR_CP0_INDEX ((GDB_FR_FRP) + LONGSIZE) /* 74 */ -#define GDB_FR_CP0_RANDOM ((GDB_FR_CP0_INDEX) + LONGSIZE) /* 75 */ -#define GDB_FR_CP0_ENTRYLO0 ((GDB_FR_CP0_RANDOM) + LONGSIZE)/* 76 */ -#define GDB_FR_CP0_ENTRYLO1 ((GDB_FR_CP0_ENTRYLO0) + LONGSIZE)/* 77 */ -#define GDB_FR_CP0_CONTEXT ((GDB_FR_CP0_ENTRYLO1) + LONGSIZE)/* 78 */ -#define GDB_FR_CP0_PAGEMASK ((GDB_FR_CP0_CONTEXT) + LONGSIZE)/* 79 */ -#define GDB_FR_CP0_WIRED ((GDB_FR_CP0_PAGEMASK) + LONGSIZE)/* 80 */ -#define GDB_FR_CP0_REG7 ((GDB_FR_CP0_WIRED) + LONGSIZE) /* 81 */ -#define GDB_FR_CP0_REG8 ((GDB_FR_CP0_REG7) + LONGSIZE) /* 82 */ -#define GDB_FR_CP0_REG9 ((GDB_FR_CP0_REG8) + LONGSIZE) /* 83 */ -#define GDB_FR_CP0_ENTRYHI ((GDB_FR_CP0_REG9) + LONGSIZE) /* 84 */ -#define GDB_FR_CP0_REG11 ((GDB_FR_CP0_ENTRYHI) + LONGSIZE)/* 85 */ -#define GDB_FR_CP0_REG12 ((GDB_FR_CP0_REG11) + LONGSIZE) /* 86 */ -#define GDB_FR_CP0_REG13 ((GDB_FR_CP0_REG12) + LONGSIZE) /* 87 */ -#define GDB_FR_CP0_REG14 ((GDB_FR_CP0_REG13) + LONGSIZE) /* 88 */ -#define GDB_FR_CP0_PRID ((GDB_FR_CP0_REG14) + LONGSIZE) /* 89 */ +#define GDB_FR_CP0_RANDOM ((GDB_FR_CP0_INDEX) + LONGSIZE) /* 75 */ +#define GDB_FR_CP0_ENTRYLO0 ((GDB_FR_CP0_RANDOM) + LONGSIZE)/* 76 */ +#define GDB_FR_CP0_ENTRYLO1 ((GDB_FR_CP0_ENTRYLO0) + LONGSIZE)/* 77 */ +#define GDB_FR_CP0_CONTEXT ((GDB_FR_CP0_ENTRYLO1) + LONGSIZE)/* 78 */ +#define GDB_FR_CP0_PAGEMASK ((GDB_FR_CP0_CONTEXT) + LONGSIZE)/* 79 */ +#define GDB_FR_CP0_WIRED ((GDB_FR_CP0_PAGEMASK) + LONGSIZE)/* 80 */ +#define GDB_FR_CP0_REG7 ((GDB_FR_CP0_WIRED) + LONGSIZE) /* 81 */ +#define GDB_FR_CP0_REG8 ((GDB_FR_CP0_REG7) + LONGSIZE) /* 82 */ +#define GDB_FR_CP0_REG9 ((GDB_FR_CP0_REG8) + LONGSIZE) /* 83 */ +#define GDB_FR_CP0_ENTRYHI ((GDB_FR_CP0_REG9) + LONGSIZE) /* 84 */ +#define GDB_FR_CP0_REG11 ((GDB_FR_CP0_ENTRYHI) + LONGSIZE)/* 85 */ +#define GDB_FR_CP0_REG12 ((GDB_FR_CP0_REG11) + LONGSIZE) /* 86 */ +#define GDB_FR_CP0_REG13 ((GDB_FR_CP0_REG12) + LONGSIZE) /* 87 */ +#define GDB_FR_CP0_REG14 ((GDB_FR_CP0_REG13) + LONGSIZE) /* 88 */ +#define GDB_FR_CP0_PRID ((GDB_FR_CP0_REG14) + LONGSIZE) /* 89 */ -#define GDB_FR_SIZE ((((GDB_FR_CP0_PRID) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1)) +#define GDB_FR_SIZE ((((GDB_FR_CP0_PRID) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1)) /* * This is the same as above, but for the high-level @@ -146,15 +146,15 @@ */ typedef struct pt_regs_s { - /* Saved main processor registers. */ - rt_base_t regs[32]; - /* Saved special registers. */ - rt_base_t cp0_status; - rt_base_t hi; - rt_base_t lo; - rt_base_t cp0_badvaddr; - rt_base_t cp0_cause; - rt_base_t cp0_epc; + /* Saved main processor registers. */ + rt_base_t regs[32]; + /* Saved special registers. */ + rt_base_t cp0_status; + rt_base_t hi; + rt_base_t lo; + rt_base_t cp0_badvaddr; + rt_base_t cp0_cause; + rt_base_t cp0_epc; } pt_regs_t; typedef void (* exception_func_t)(pt_regs_t *regs); diff --git a/libcpu/mips/common/mips.h b/libcpu/mips/common/mips.h index a4bc74a050..f7f87aced9 100644 --- a/libcpu/mips/common/mips.h +++ b/libcpu/mips/common/mips.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/mips/common/mips_addrspace.h b/libcpu/mips/common/mips_addrspace.h index 5a101e1c0c..7a3ff76f13 100644 --- a/libcpu/mips/common/mips_addrspace.h +++ b/libcpu/mips/common/mips_addrspace.h @@ -19,15 +19,15 @@ #define _ATYPE_ #define _ATYPE32_ #define _ATYPE64_ -#define _CONST64_(x) x +#define _CONST64_(x) x #else -#define _ATYPE_ __PTRDIFF_TYPE__ -#define _ATYPE32_ int -#define _ATYPE64_ __s64 +#define _ATYPE_ __PTRDIFF_TYPE__ +#define _ATYPE32_ int +#define _ATYPE64_ __s64 #ifdef CONFIG_64BIT -#define _CONST64_(x) x ## L +#define _CONST64_(x) x ## L #else -#define _CONST64_(x) x ## LL +#define _CONST64_(x) x ## LL #endif #endif @@ -38,21 +38,21 @@ #define _ACAST32_ #define _ACAST64_ #else -#define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */ -#define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */ +#define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */ +#define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */ #endif /* * Returns the kernel segment base of a given address */ -#define KSEGX(a) ((_ACAST32_ (a)) & 0xe0000000) +#define KSEGX(a) ((_ACAST32_ (a)) & 0xe0000000) /* * Returns the physical address of a CKSEGx / XKPHYS address */ -#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff) -#define XPHYSADDR(a) ((_ACAST64_(a)) & \ - _CONST64_(0x000000ffffffffff)) +#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff) +#define XPHYSADDR(a) ((_ACAST64_(a)) & \ + _CONST64_(0x000000ffffffffff)) #ifdef CONFIG_64BIT @@ -61,73 +61,73 @@ * The compatibility segments use the full 64-bit sign extended value. Note * the R8000 doesn't have them so don't reference these in generic MIPS code. */ -#define XKUSEG _CONST64_(0x0000000000000000) -#define XKSSEG _CONST64_(0x4000000000000000) -#define XKPHYS _CONST64_(0x8000000000000000) -#define XKSEG _CONST64_(0xc000000000000000) -#define CKSEG0 _CONST64_(0xffffffff80000000) -#define CKSEG1 _CONST64_(0xffffffffa0000000) -#define CKSSEG _CONST64_(0xffffffffc0000000) -#define CKSEG3 _CONST64_(0xffffffffe0000000) - -#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0) -#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) -#define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2) -#define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3) +#define XKUSEG _CONST64_(0x0000000000000000) +#define XKSSEG _CONST64_(0x4000000000000000) +#define XKPHYS _CONST64_(0x8000000000000000) +#define XKSEG _CONST64_(0xc000000000000000) +#define CKSEG0 _CONST64_(0xffffffff80000000) +#define CKSEG1 _CONST64_(0xffffffffa0000000) +#define CKSSEG _CONST64_(0xffffffffc0000000) +#define CKSEG3 _CONST64_(0xffffffffe0000000) + +#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0) +#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) +#define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2) +#define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3) #else -#define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0BASE) -#define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1BASE) -#define CKSEG2ADDR(a) (CPHYSADDR(a) | KSEG2BASE) -#define CKSEG3ADDR(a) (CPHYSADDR(a) | KSEG3BASE) +#define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0BASE) +#define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1BASE) +#define CKSEG2ADDR(a) (CPHYSADDR(a) | KSEG2BASE) +#define CKSEG3ADDR(a) (CPHYSADDR(a) | KSEG3BASE) /* * Map an address to a certain kernel segment */ -#define KSEG0ADDR(a) (CPHYSADDR(a) | KSEG0BASE) -#define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1BASE) -#define KSEG2ADDR(a) (CPHYSADDR(a) | KSEG2BASE) -#define KSEG3ADDR(a) (CPHYSADDR(a) | KSEG3BASE) +#define KSEG0ADDR(a) (CPHYSADDR(a) | KSEG0BASE) +#define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1BASE) +#define KSEG2ADDR(a) (CPHYSADDR(a) | KSEG2BASE) +#define KSEG3ADDR(a) (CPHYSADDR(a) | KSEG3BASE) /* * Memory segments (32bit kernel mode addresses) * These are the traditional names used in the 32-bit universe. */ -//#define KUSEGBASE 0x00000000 -//#define KSEG0BASE 0x80000000 -//#define KSEG1BASE 0xa0000000 -//#define KSEG2BASE 0xc0000000 -//#define KSEG3BASE 0xe0000000 - -#define CKUSEG 0x00000000 -#define CKSEG0 0x80000000 -#define CKSEG1 0xa0000000 -#define CKSEG2 0xc0000000 -#define CKSEG3 0xe0000000 +//#define KUSEGBASE 0x00000000 +//#define KSEG0BASE 0x80000000 +//#define KSEG1BASE 0xa0000000 +//#define KSEG2BASE 0xc0000000 +//#define KSEG3BASE 0xe0000000 + +#define CKUSEG 0x00000000 +#define CKSEG0 0x80000000 +#define CKSEG1 0xa0000000 +#define CKSEG2 0xc0000000 +#define CKSEG3 0xe0000000 #endif /* * Cache modes for XKPHYS address conversion macros */ -#define K_CALG_COH_EXCL1_NOL2 0 -#define K_CALG_COH_SHRL1_NOL2 1 -#define K_CALG_UNCACHED 2 -#define K_CALG_NONCOHERENT 3 -#define K_CALG_COH_EXCL 4 -#define K_CALG_COH_SHAREABLE 5 -#define K_CALG_NOTUSED 6 -#define K_CALG_UNCACHED_ACCEL 7 +#define K_CALG_COH_EXCL1_NOL2 0 +#define K_CALG_COH_SHRL1_NOL2 1 +#define K_CALG_UNCACHED 2 +#define K_CALG_NONCOHERENT 3 +#define K_CALG_COH_EXCL 4 +#define K_CALG_COH_SHAREABLE 5 +#define K_CALG_NOTUSED 6 +#define K_CALG_UNCACHED_ACCEL 7 /* * 64-bit address conversions */ -#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p)) -#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p)) -#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK) -#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \ - (_CONST64_(cm) << 59) | (a)) +#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p)) +#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p)) +#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK) +#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \ + (_CONST64_(cm) << 59) | (a)) /* * Returns the uncached address of a sdram address @@ -137,17 +137,17 @@ /* We use a 36 bit physical address map here and cannot access physical memory directly from core */ #define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000) -#else /* !CONFIG_SOC_AU1X00 */ +#else /* !CONFIG_SOC_AU1X00 */ #define UNCACHED_SDRAM(a) CKSEG1ADDR(a) -#endif /* CONFIG_SOC_AU1X00 */ -#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_SOC_AU1X00 */ +#endif /* __ASSEMBLY__ */ /* * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting * the region, 3 bits for the CCA mode. This leaves 59 bits of which the * R8000 implements most with its 48-bit physical address space. */ -#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */ +#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */ #ifndef CONFIG_CPU_R8000 @@ -156,13 +156,13 @@ * in order to catch bugs in the source code. */ -#define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000) -#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */ +#define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000) +#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */ #endif -#define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK) -#define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE) +#define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK) +#define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE) #ifndef __ASSEMBLY__ @@ -173,18 +173,18 @@ static inline phys_addr_t virt_to_phys(volatile void * address) { #ifndef CONFIG_64BIT - return CPHYSADDR(address); + return CPHYSADDR(address); #else - return XPHYSADDR(address); + return XPHYSADDR(address); #endif } static inline void * phys_to_virt(unsigned long address) { #ifndef CONFIG_64BIT - return (void *)KSEG0ADDR(address); + return (void *)KSEG0ADDR(address); #else - return (void *)CKSEG0ADDR(address); + return (void *)CKSEG0ADDR(address); #endif } #endif diff --git a/libcpu/mips/common/mips_asm.h b/libcpu/mips/common/mips_asm.h index 949cea9019..5a566b3bd8 100644 --- a/libcpu/mips/common/mips_asm.h +++ b/libcpu/mips/common/mips_asm.h @@ -47,31 +47,31 @@ * in makefile. */ #ifdef _BSS_OLD_ -#define BSS .##section bss +#define BSS .##section bss #else -#define BSS .##bss +#define BSS .##bss #endif #define LEAF(name)\ - .##text;\ - .##globl name;\ - .##ent name;\ + .##text;\ + .##globl name;\ + .##ent name;\ name: #define SLEAF(name)\ - .##text;\ - .##ent name;\ + .##text;\ + .##ent name;\ name: #ifdef __ghs__ #define END(name)\ - .##end name + .##end name #else #define END(name)\ - .##size name,.-name;\ - .##end name + .##size name,.-name;\ + .##end name #endif @@ -151,7 +151,7 @@ typedef union tunSU32 #define True !False #ifndef NULL -#define NULL ((void *)0) +#define NULL ((void *)0) #endif//NULL #ifndef MIN @@ -159,31 +159,31 @@ typedef union tunSU32 #endif//MIN #ifndef MAX -#define MAX(x,y) ((x) > (y) ? (x) : (y)) +#define MAX(x,y) ((x) > (y) ? (x) : (y)) #endif//MAX -#define MAXUINT(w) (\ - ((w) == sizeof(U8)) ? 0xFFU :\ - ((w) == sizeof(U16)) ? 0xFFFFU :\ - ((w) == sizeof(U32)) ? 0xFFFFFFFFU : 0\ - ) +#define MAXUINT(w) (\ + ((w) == sizeof(U8)) ? 0xFFU :\ + ((w) == sizeof(U16)) ? 0xFFFFU :\ + ((w) == sizeof(U32)) ? 0xFFFFFFFFU : 0\ + ) -#define MAXINT(w) (\ - ((w) == sizeof(S8)) ? 0x7F :\ - ((w) == sizeof(S16)) ? 0x7FFF :\ - ((w) == sizeof(S32)) ? 0x7FFFFFFF : 0\ - ) +#define MAXINT(w) (\ + ((w) == sizeof(S8)) ? 0x7F :\ + ((w) == sizeof(S16)) ? 0x7FFF :\ + ((w) == sizeof(S32)) ? 0x7FFFFFFF : 0\ + ) -#define MSK(n) ((1 << (n)) - 1) +#define MSK(n) ((1 << (n)) - 1) -#define KUSEG_MSK 0x80000000 -#define KSEG_MSK 0xE0000000 +#define KUSEG_MSK 0x80000000 +#define KSEG_MSK 0xE0000000 -#define KUSEGBASE 0x00000000 -#define KSEG0BASE 0x80000000 -#define KSEG1BASE 0xA0000000 -#define KSSEGBASE 0xC0000000 -#define KSEG3BASE 0xE0000000 +#define KUSEGBASE 0x00000000 +#define KSEG0BASE 0x80000000 +#define KSEG1BASE 0xA0000000 +#define KSSEGBASE 0xC0000000 +#define KSEG3BASE 0xE0000000 /* Below macros perform the following functions : * @@ -197,8 +197,8 @@ typedef union tunSU32 * KSEG1A : Same as KSEG1 but operates on register rather than constant. * PHYSA : Same as PHYS but operates on register rather than constant. * CACHED : Alias for KSEG0 macro . - * (Note that KSEG0 cache attribute is determined by K0 - * field of Config register, but this is typically cached). + * (Note that KSEG0 cache attribute is determined by K0 + * field of Config register, but this is typically cached). * UNCACHED : Alias for KSEG1 macro . */ #ifdef __ASSEMBLY__ @@ -208,117 +208,117 @@ typedef union tunSU32 #define KSEG3(addr) (((addr) & ~KSEG_MSK) | KSEG3BASE) #define KUSEG(addr) (((addr) & ~KUSEG_MSK) | KUSEGBASE) #define PHYS(addr) ( (addr) & ~KSEG_MSK) -#define KSEG0A(reg) and reg, ~KSEG_MSK; or reg, KSEG0BASE -#define KSEG1A(reg) and reg, ~KSEG_MSK; or reg, KSEG1BASE -#define PHYSA(reg) and reg, ~KSEG_MSK +#define KSEG0A(reg) and reg, ~KSEG_MSK; or reg, KSEG0BASE +#define KSEG1A(reg) and reg, ~KSEG_MSK; or reg, KSEG1BASE +#define PHYSA(reg) and reg, ~KSEG_MSK #else #define KSEG0(addr) (((U32)(addr) & ~KSEG_MSK) | KSEG0BASE) #define KSEG1(addr) (((U32)(addr) & ~KSEG_MSK) | KSEG1BASE) -#define KSSEG(addr) (((U32)(addr) & ~KSEG_MSK) | KSSEGBASE) -#define KSEG3(addr) (((U32)(addr) & ~KSEG_MSK) | KSEG3BASE) -#define KUSEG(addr) (((U32)(addr) & ~KUSEG_MSK) | KUSEGBASE) -#define PHYS(addr) ((U32)(addr) & ~KSEG_MSK) +#define KSSEG(addr) (((U32)(addr) & ~KSEG_MSK) | KSSEGBASE) +#define KSEG3(addr) (((U32)(addr) & ~KSEG_MSK) | KSEG3BASE) +#define KUSEG(addr) (((U32)(addr) & ~KUSEG_MSK) | KUSEGBASE) +#define PHYS(addr) ((U32)(addr) & ~KSEG_MSK) #endif -#define CACHED(addr) KSEG0(addr) -#define UNCACHED(addr) KSEG1(addr) +#define CACHED(addr) KSEG0(addr) +#define UNCACHED(addr) KSEG1(addr) #ifdef __ASSEMBLY__ /* Macroes to access variables at constant addresses * Compensates for signed 16 bit displacement - * Typical use: li a0, HIKSEG1(ATLAS_ASCIIWORD) - * sw v1, LO_OFFS(ATLAS_ASCIIWORD)(a0) + * Typical use: li a0, HIKSEG1(ATLAS_ASCIIWORD) + * sw v1, LO_OFFS(ATLAS_ASCIIWORD)(a0) */ -#define HIKSEG0(addr) ((KSEG0(addr) + 0x8000) & 0xffff0000) -#define HIKSEG1(addr) ((KSEG1(addr) + 0x8000) & 0xffff0000) -#define HI_PART(addr) (((addr) + 0x8000) & 0xffff0000) -#define LO_OFFS(addr) ((addr) & 0xffff) +#define HIKSEG0(addr) ((KSEG0(addr) + 0x8000) & 0xffff0000) +#define HIKSEG1(addr) ((KSEG1(addr) + 0x8000) & 0xffff0000) +#define HI_PART(addr) (((addr) + 0x8000) & 0xffff0000) +#define LO_OFFS(addr) ((addr) & 0xffff) #endif /* Most/Least significant 32 bit from 64 bit double word */ -#define HI32(data64) ((U32)(data64 >> 32)) -#define LO32(data64) ((U32)(data64 & 0xFFFFFFFF)) +#define HI32(data64) ((U32)(data64 >> 32)) +#define LO32(data64) ((U32)(data64 & 0xFFFFFFFF)) #if ((!defined(__ASSEMBLY__)) && (!defined(__LANGUAGE_ASSEMBLY))) -#define REG8( addr ) (*(volatile U8 *) (addr)) -#define REG16( addr ) (*(volatile U16 *)(addr)) -#define REG32( addr ) (*(volatile U32 *)(addr)) -#define REG64( addr ) (*(volatile U64 *)(addr)) +#define REG8( addr ) (*(volatile U8 *) (addr)) +#define REG16( addr ) (*(volatile U16 *)(addr)) +#define REG32( addr ) (*(volatile U32 *)(addr)) +#define REG64( addr ) (*(volatile U64 *)(addr)) #endif /* Register field mapping */ -#define REGFIELD(reg, rfld) (((reg) & rfld##_MSK) >> rfld##_SHF) +#define REGFIELD(reg, rfld) (((reg) & rfld##_MSK) >> rfld##_SHF) -/* absolute register address, access */ -#define REGA(addr) REG32(addr) +/* absolute register address, access */ +#define REGA(addr) REG32(addr) -/* physical register address, access: base address + offsett */ -#define REGP(base,phys) REG32( (U32)(base) + (phys) ) +/* physical register address, access: base address + offsett */ +#define REGP(base,phys) REG32( (U32)(base) + (phys) ) -/* relative register address, access: base address + offsett */ +/* relative register address, access: base address + offsett */ #define REG(base,offs) REG32( (U32)(base) + offs##_##OFS ) -/* relative register address, access: base address + offsett */ +/* relative register address, access: base address + offsett */ #define REG_8(base,offs) REG8( (U32)(base) + offs##_##OFS ) -/* relative register address, access: base address + offsett */ +/* relative register address, access: base address + offsett */ #define REG_16(base,offs) REG16( (U32)(base) + offs##_##OFS ) -/* relative register address, access: base address + offsett */ +/* relative register address, access: base address + offsett */ #define REG_64(base,offs) REG64( (U32)(base) + offs##_##OFS ) /************************************** * Macroes not used by YAMON any more * (kept for backwards compatibility) */ -/* register read field */ -#define REGARD(addr,fld) ((REGA(addr) & addr##_##fld##_##MSK) \ - >> addr##_##fld##_##SHF) +/* register read field */ +#define REGARD(addr,fld) ((REGA(addr) & addr##_##fld##_##MSK) \ + >> addr##_##fld##_##SHF) -/* register write numeric field value */ -#define REGAWRI(addr,fld,intval) ((REGA(addr) & ~(addr##_##fld##_##MSK))\ - | ((intval) << addr##_##fld##_##SHF)) +/* register write numeric field value */ +#define REGAWRI(addr,fld,intval) ((REGA(addr) & ~(addr##_##fld##_##MSK))\ + | ((intval) << addr##_##fld##_##SHF)) -/* register write enumerated field value */ -#define REGAWRE(addr,fld,enumval) ((REGA(addr) & ~(addr##_##fld##_##MSK))\ - | ((addr##_##fld##_##enumval) << addr##_##fld##_##SHF)) +/* register write enumerated field value */ +#define REGAWRE(addr,fld,enumval) ((REGA(addr) & ~(addr##_##fld##_##MSK))\ + | ((addr##_##fld##_##enumval) << addr##_##fld##_##SHF)) /* Examples: * - * exccode = REGARD(CPU_CAUSE,EXC); + * exccode = REGARD(CPU_CAUSE,EXC); * - * REGA(SDR_CONTROL) = REGAWRI(OSG_CONTROL,TMO,17) - * | REGAWRE(OSG_CONTROL,DTYPE,PC1); + * REGA(SDR_CONTROL) = REGAWRI(OSG_CONTROL,TMO,17) + * | REGAWRE(OSG_CONTROL,DTYPE,PC1); */ -/* register read field */ -#define REGRD(base,offs,fld) ((REG(base,offs) & offs##_##fld##_##MSK) \ - >> offs##_##fld##_##SHF) +/* register read field */ +#define REGRD(base,offs,fld) ((REG(base,offs) & offs##_##fld##_##MSK) \ + >> offs##_##fld##_##SHF) -/* register write numeric field value */ -#define REGWRI(base,offs,fld,intval)((REG(base,offs)& ~(offs##_##fld##_##MSK))\ +/* register write numeric field value */ +#define REGWRI(base,offs,fld,intval)((REG(base,offs)& ~(offs##_##fld##_##MSK))\ | (((intval) << offs##_##fld##_##SHF) & offs##_##fld##_##MSK)) -/* register write enumerated field value */ -#define REGWRE(base,offs,fld,enumval)((REG(base,offs) & ~(offs##_##fld##_##MSK))\ - | ((offs##_##fld##_##enumval) << offs##_##fld##_##SHF)) +/* register write enumerated field value */ +#define REGWRE(base,offs,fld,enumval)((REG(base,offs) & ~(offs##_##fld##_##MSK))\ + | ((offs##_##fld##_##enumval) << offs##_##fld##_##SHF)) -/* physical register read field */ -#define REGPRD(base,phys,fld) ((REGP(base,phys) & phys##_##fld##_##MSK) \ - >> phys##_##fld##_##SHF) +/* physical register read field */ +#define REGPRD(base,phys,fld) ((REGP(base,phys) & phys##_##fld##_##MSK) \ + >> phys##_##fld##_##SHF) -/* physical register write numeric field value */ -#define REGPWRI(base,phys,fld,intval)((REGP(base,phys)& ~(phys##_##fld##_##MSK))\ - | ((intval) << phys##_##fld##_##SHF)) +/* physical register write numeric field value */ +#define REGPWRI(base,phys,fld,intval)((REGP(base,phys)& ~(phys##_##fld##_##MSK))\ + | ((intval) << phys##_##fld##_##SHF)) -/* physical register write enumerated field value */ -#define REGPWRE(base,phys,fld,enumval)((REGP(base,phys) & ~(phys##_##fld##_##MSK))\ - | ((phys##_##fld##_##enumval) << phys##_##fld##_##SHF)) +/* physical register write enumerated field value */ +#define REGPWRE(base,phys,fld,enumval)((REGP(base,phys) & ~(phys##_##fld##_##MSK))\ + | ((phys##_##fld##_##enumval) << phys##_##fld##_##SHF)) /* * End of macroes not used by YAMON any more *********************************************/ @@ -330,14 +330,14 @@ typedef union tunSU32 /* Set byte address to little endian format */ #ifdef EL -#define SWAP_BYTEADDR_EL(addr) addr +#define SWAP_BYTEADDR_EL(addr) addr #else #define SWAP_BYTEADDR_EL(addr) SWAP_BYTEADDR32( addr ) #endif /* Set byte address to big endian format */ #ifdef EB -#define SWAP_BYTEADDR_EB(addr) addr +#define SWAP_BYTEADDR_EB(addr) addr #else #define SWAP_BYTEADDR_EB(addr) SWAP_BYTEADDR32( addr ) #endif diff --git a/libcpu/mips/common/mips_cache.c b/libcpu/mips/common/mips_cache.c index d89a05e8e6..1f20e15e56 100644 --- a/libcpu/mips/common/mips_cache.c +++ b/libcpu/mips/common/mips_cache.c @@ -14,7 +14,7 @@ extern void cache_init(rt_ubase_t cache_size, rt_ubase_t cache_line_size); void r4k_cache_init(void) { -// cache_init(dcache_size, cpu_dcache_line_size); +// cache_init(dcache_size, cpu_dcache_line_size); } void r4k_cache_flush_all(void) @@ -31,7 +31,7 @@ void r4k_icache_flush_all(void) void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size) { - rt_ubase_t end, a; + rt_ubase_t end, a; if (size > g_mips_core.icache_size) { @@ -39,7 +39,7 @@ void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size) } else { - rt_ubase_t ic_lsize = g_mips_core.icache_line_size; + rt_ubase_t ic_lsize = g_mips_core.icache_line_size; a = addr & ~(ic_lsize - 1); end = ((addr + size) - 1) & ~(ic_lsize - 1); @@ -55,8 +55,8 @@ void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size) void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size) { - rt_ubase_t end, a; - rt_ubase_t ic_lsize = g_mips_core.icache_line_size; + rt_ubase_t end, a; + rt_ubase_t ic_lsize = g_mips_core.icache_line_size; a = addr & ~(ic_lsize - 1); end = ((addr + size) - 1) & ~(ic_lsize - 1); @@ -71,7 +71,7 @@ void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size) void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size) { - rt_ubase_t end, a; + rt_ubase_t end, a; rt_ubase_t dc_lsize = g_mips_core.dcache_line_size; a = addr & ~(dc_lsize - 1); @@ -87,7 +87,7 @@ void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size) void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size) { - rt_ubase_t end, a; + rt_ubase_t end, a; if (size >= g_mips_core.dcache_size) { @@ -95,7 +95,7 @@ void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size) } else { - rt_ubase_t dc_lsize = g_mips_core.dcache_line_size; + rt_ubase_t dc_lsize = g_mips_core.dcache_line_size; a = addr & ~(dc_lsize - 1); end = ((addr + size) - 1) & ~(dc_lsize - 1); diff --git a/libcpu/mips/common/mips_cache.h b/libcpu/mips/common/mips_cache.h index 17a728df7e..c260ed3047 100644 --- a/libcpu/mips/common/mips_cache.h +++ b/libcpu/mips/common/mips_cache.h @@ -106,7 +106,7 @@ enum dma_data_direction #define INDEX_STORE_DATA_D 0x1d #define INDEX_STORE_DATA_S 0x1f -#define cache_op(op, addr) \ +#define cache_op(op, addr) \ __asm__ __volatile__( \ ".set push\n" \ ".set noreorder\n" \ @@ -116,95 +116,95 @@ enum dma_data_direction : \ : "i" (op), "R" (*(unsigned char *)(addr))) -#define cache16_unroll32(base, op) \ - __asm__ __volatile__( \ - " .set noreorder \n" \ - " .set mips3 \n" \ - " cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \ - " cache %1, 0x020(%0); cache %1, 0x030(%0) \n" \ - " cache %1, 0x040(%0); cache %1, 0x050(%0) \n" \ - " cache %1, 0x060(%0); cache %1, 0x070(%0) \n" \ - " cache %1, 0x080(%0); cache %1, 0x090(%0) \n" \ - " cache %1, 0x0a0(%0); cache %1, 0x0b0(%0) \n" \ - " cache %1, 0x0c0(%0); cache %1, 0x0d0(%0) \n" \ - " cache %1, 0x0e0(%0); cache %1, 0x0f0(%0) \n" \ - " cache %1, 0x100(%0); cache %1, 0x110(%0) \n" \ - " cache %1, 0x120(%0); cache %1, 0x130(%0) \n" \ - " cache %1, 0x140(%0); cache %1, 0x150(%0) \n" \ - " cache %1, 0x160(%0); cache %1, 0x170(%0) \n" \ - " cache %1, 0x180(%0); cache %1, 0x190(%0) \n" \ - " cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \ - " cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \ - " cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \ - " .set mips0 \n" \ - " .set reorder \n" \ - : \ - : "r" (base), \ - "i" (op)); +#define cache16_unroll32(base, op) \ + __asm__ __volatile__( \ + " .set noreorder \n" \ + " .set mips3 \n" \ + " cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \ + " cache %1, 0x020(%0); cache %1, 0x030(%0) \n" \ + " cache %1, 0x040(%0); cache %1, 0x050(%0) \n" \ + " cache %1, 0x060(%0); cache %1, 0x070(%0) \n" \ + " cache %1, 0x080(%0); cache %1, 0x090(%0) \n" \ + " cache %1, 0x0a0(%0); cache %1, 0x0b0(%0) \n" \ + " cache %1, 0x0c0(%0); cache %1, 0x0d0(%0) \n" \ + " cache %1, 0x0e0(%0); cache %1, 0x0f0(%0) \n" \ + " cache %1, 0x100(%0); cache %1, 0x110(%0) \n" \ + " cache %1, 0x120(%0); cache %1, 0x130(%0) \n" \ + " cache %1, 0x140(%0); cache %1, 0x150(%0) \n" \ + " cache %1, 0x160(%0); cache %1, 0x170(%0) \n" \ + " cache %1, 0x180(%0); cache %1, 0x190(%0) \n" \ + " cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \ + " cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \ + " cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \ + " .set mips0 \n" \ + " .set reorder \n" \ + : \ + : "r" (base), \ + "i" (op)); static inline void flush_icache_line_indexed(rt_ubase_t addr) { - cache_op(INDEX_INVALIDATE_I, addr); + cache_op(INDEX_INVALIDATE_I, addr); } static inline void flush_dcache_line_indexed(rt_ubase_t addr) { - cache_op(INDEX_WRITEBACK_INV_D, addr); + cache_op(INDEX_WRITEBACK_INV_D, addr); } static inline void flush_icache_line(rt_ubase_t addr) { - cache_op(HIT_INVALIDATE_I, addr); + cache_op(HIT_INVALIDATE_I, addr); } static inline void lock_icache_line(rt_ubase_t addr) { - cache_op(FETCH_AND_LOCK_I, addr); + cache_op(FETCH_AND_LOCK_I, addr); } static inline void lock_dcache_line(rt_ubase_t addr) { - cache_op(FETCH_AND_LOCK_D, addr); + cache_op(FETCH_AND_LOCK_D, addr); } static inline void flush_dcache_line(rt_ubase_t addr) { - cache_op(HIT_WRITEBACK_INV_D, addr); + cache_op(HIT_WRITEBACK_INV_D, addr); } static inline void invalidate_dcache_line(rt_ubase_t addr) { - cache_op(HIT_INVALIDATE_D, addr); + cache_op(HIT_INVALIDATE_D, addr); } static inline void blast_dcache16(void) { - rt_ubase_t start = KSEG0BASE; - rt_ubase_t end = start + g_mips_core.dcache_size; - rt_ubase_t addr; + rt_ubase_t start = KSEG0BASE; + rt_ubase_t end = start + g_mips_core.dcache_size; + rt_ubase_t addr; - for (addr = start; addr < end; addr += g_mips_core.dcache_line_size) - cache16_unroll32(addr, INDEX_WRITEBACK_INV_D); + for (addr = start; addr < end; addr += g_mips_core.dcache_line_size) + cache16_unroll32(addr, INDEX_WRITEBACK_INV_D); } static inline void inv_dcache16(void) { - rt_ubase_t start = KSEG0BASE; - rt_ubase_t end = start + g_mips_core.dcache_size; - rt_ubase_t addr; + rt_ubase_t start = KSEG0BASE; + rt_ubase_t end = start + g_mips_core.dcache_size; + rt_ubase_t addr; - for (addr = start; addr < end; addr += g_mips_core.dcache_line_size) - cache16_unroll32(addr, HIT_INVALIDATE_D); + for (addr = start; addr < end; addr += g_mips_core.dcache_line_size) + cache16_unroll32(addr, HIT_INVALIDATE_D); } static inline void blast_icache16(void) { - rt_ubase_t start = KSEG0BASE; - rt_ubase_t end = start + g_mips_core.icache_size; - rt_ubase_t addr; + rt_ubase_t start = KSEG0BASE; + rt_ubase_t end = start + g_mips_core.icache_size; + rt_ubase_t addr; - for (addr = start; addr < end; addr += g_mips_core.icache_line_size) - cache16_unroll32(addr, INDEX_INVALIDATE_I); + for (addr = start; addr < end; addr += g_mips_core.icache_line_size) + cache16_unroll32(addr, INDEX_INVALIDATE_I); } void r4k_cache_init(void); diff --git a/libcpu/mips/common/mips_cfg.h b/libcpu/mips/common/mips_cfg.h index 8385ce34c2..0dff9b787d 100644 --- a/libcpu/mips/common/mips_cfg.h +++ b/libcpu/mips/common/mips_cfg.h @@ -24,7 +24,7 @@ typedef struct mips32_core_cfg // uint16_t dcache_ways; uint16_t dcache_size; - uint16_t max_tlb_entries; /* number of tlb entry */ + uint16_t max_tlb_entries; /* number of tlb entry */ } mips32_core_cfg_t; extern mips32_core_cfg_t g_mips_core; diff --git a/libcpu/mips/common/mips_context.h b/libcpu/mips/common/mips_context.h index 9e23c3864b..4663530123 100644 --- a/libcpu/mips/common/mips_context.h +++ b/libcpu/mips/common/mips_context.h @@ -11,12 +11,12 @@ #ifndef _MIPS_CONTEXT_ASM_H_ #define _MIPS_CONTEXT_ASM_H_ -#define CONTEXT_SIZE ( STK_CTX_SIZE + FPU_ADJ ) +#define CONTEXT_SIZE ( STK_CTX_SIZE + FPU_ADJ ) #ifdef __mips_hard_float -#define FPU_ADJ (32 * 4 + 8) /* FP0-FP31 + CP1_STATUS */ -#define FPU_CTX ( CONTEXT_SIZE - FPU_ADJ ) +#define FPU_ADJ (32 * 4 + 8) /* FP0-FP31 + CP1_STATUS */ +#define FPU_CTX ( CONTEXT_SIZE - FPU_ADJ ) #else -#define FPU_ADJ 0 +#define FPU_ADJ 0 #endif @@ -29,237 +29,237 @@ #endif .macro SAVE_CONTEXT - .set push - .set noat - .set noreorder - .set volatile - - //save SP - move k1, sp - move k0, sp - subu sp, k1, CONTEXT_SIZE - sw k0, (29 * 4)(sp) - - //save REG - sw $0, ( 0 * 4)(sp) - sw $1, ( 1 * 4)(sp) - sw $2, ( 2 * 4)(sp) - sw $3, ( 3 * 4)(sp) - sw $4, ( 4 * 4)(sp) - sw $5, ( 5 * 4)(sp) - sw $6, ( 6 * 4)(sp) - sw $7, ( 7 * 4)(sp) - sw $8, ( 8 * 4)(sp) - sw $9, ( 9 * 4)(sp) - sw $10, (10 * 4)(sp) - sw $11, (11 * 4)(sp) - sw $12, (12 * 4)(sp) - sw $13, (13 * 4)(sp) - sw $14, (14 * 4)(sp) - sw $15, (15 * 4)(sp) - sw $16, (16 * 4)(sp) - sw $17, (17 * 4)(sp) - sw $18, (18 * 4)(sp) - sw $19, (19 * 4)(sp) - sw $20, (20 * 4)(sp) - sw $21, (21 * 4)(sp) - sw $22, (22 * 4)(sp) - sw $23, (23 * 4)(sp) - sw $24, (24 * 4)(sp) - sw $25, (25 * 4)(sp) - /* K0 K1 */ - sw $28, (28 * 4)(sp) - /* SP */ - sw $30, (30 * 4)(sp) - sw $31, (31 * 4)(sp) - - /* STATUS CAUSE EPC.... */ - mfc0 $2, CP0_STATUS - sw $2, STK_OFFSET_SR(sp) - - mfc0 $2, CP0_CAUSE - sw $2, STK_OFFSET_CAUSE(sp) - - mfc0 $2, CP0_BADVADDR - sw $2, STK_OFFSET_BADVADDR(sp) - - MFC0 $2, CP0_EPC - sw $2, STK_OFFSET_EPC(sp) - - mfhi $2 - sw $2, STK_OFFSET_HI(sp) - - mflo $2 - sw $2, STK_OFFSET_LO(sp) + .set push + .set noat + .set noreorder + .set volatile + + //save SP + move k1, sp + move k0, sp + subu sp, k1, CONTEXT_SIZE + sw k0, (29 * 4)(sp) + + //save REG + sw $0, ( 0 * 4)(sp) + sw $1, ( 1 * 4)(sp) + sw $2, ( 2 * 4)(sp) + sw $3, ( 3 * 4)(sp) + sw $4, ( 4 * 4)(sp) + sw $5, ( 5 * 4)(sp) + sw $6, ( 6 * 4)(sp) + sw $7, ( 7 * 4)(sp) + sw $8, ( 8 * 4)(sp) + sw $9, ( 9 * 4)(sp) + sw $10, (10 * 4)(sp) + sw $11, (11 * 4)(sp) + sw $12, (12 * 4)(sp) + sw $13, (13 * 4)(sp) + sw $14, (14 * 4)(sp) + sw $15, (15 * 4)(sp) + sw $16, (16 * 4)(sp) + sw $17, (17 * 4)(sp) + sw $18, (18 * 4)(sp) + sw $19, (19 * 4)(sp) + sw $20, (20 * 4)(sp) + sw $21, (21 * 4)(sp) + sw $22, (22 * 4)(sp) + sw $23, (23 * 4)(sp) + sw $24, (24 * 4)(sp) + sw $25, (25 * 4)(sp) + /* K0 K1 */ + sw $28, (28 * 4)(sp) + /* SP */ + sw $30, (30 * 4)(sp) + sw $31, (31 * 4)(sp) + + /* STATUS CAUSE EPC.... */ + mfc0 $2, CP0_STATUS + sw $2, STK_OFFSET_SR(sp) + + mfc0 $2, CP0_CAUSE + sw $2, STK_OFFSET_CAUSE(sp) + + mfc0 $2, CP0_BADVADDR + sw $2, STK_OFFSET_BADVADDR(sp) + + MFC0 $2, CP0_EPC + sw $2, STK_OFFSET_EPC(sp) + + mfhi $2 + sw $2, STK_OFFSET_HI(sp) + + mflo $2 + sw $2, STK_OFFSET_LO(sp) #ifdef __mips_hard_float - add a0, sp,STK_CTX_SIZE + add a0, sp,STK_CTX_SIZE - mfc0 t0, CP0_STATUS - .set push - .set at - or t0, M_StatusCU1 - .set push - mtc0 t0, CP0_STATUS + mfc0 t0, CP0_STATUS + .set push + .set at + or t0, M_StatusCU1 + .set push + mtc0 t0, CP0_STATUS - cfc1 t0, CP1_STATUS + cfc1 t0, CP1_STATUS sw t0 , 0x00(a0) - swc1 $f0,(0x04 * 1)(a0) - swc1 $f1,(0x04 * 2)(a0) - swc1 $f2,(0x04 * 3)(a0) - swc1 $f3,(0x04 * 4)(a0) - swc1 $f4,(0x04 * 5)(a0) - swc1 $f5,(0x04 * 6)(a0) - swc1 $f6,(0x04 * 7)(a0) - swc1 $f7,(0x04 * 8)(a0) - swc1 $f8,(0x04 * 9)(a0) - swc1 $f9,(0x04 * 10)(a0) - swc1 $f10,(0x04 * 11)(a0) - swc1 $f11,(0x04 * 12)(a0) - swc1 $f12,(0x04 * 13)(a0) - swc1 $f13,(0x04 * 14)(a0) - swc1 $f14,(0x04 * 15)(a0) - swc1 $f15,(0x04 * 16)(a0) - swc1 $f16,(0x04 * 17)(a0) - swc1 $f17,(0x04 * 18)(a0) - swc1 $f18,(0x04 * 19)(a0) - swc1 $f19,(0x04 * 20)(a0) - swc1 $f20,(0x04 * 21)(a0) - swc1 $f21,(0x04 * 22)(a0) - swc1 $f22,(0x04 * 23)(a0) - swc1 $f23,(0x04 * 24)(a0) - swc1 $f24,(0x04 * 25)(a0) - swc1 $f25,(0x04 * 26)(a0) - swc1 $f26,(0x04 * 27)(a0) - swc1 $f27,(0x04 * 28)(a0) - swc1 $f28,(0x04 * 29)(a0) - swc1 $f29,(0x04 * 30)(a0) - swc1 $f30,(0x04 * 31)(a0) - swc1 $f31,(0x04 * 32)(a0) - - nop + swc1 $f0,(0x04 * 1)(a0) + swc1 $f1,(0x04 * 2)(a0) + swc1 $f2,(0x04 * 3)(a0) + swc1 $f3,(0x04 * 4)(a0) + swc1 $f4,(0x04 * 5)(a0) + swc1 $f5,(0x04 * 6)(a0) + swc1 $f6,(0x04 * 7)(a0) + swc1 $f7,(0x04 * 8)(a0) + swc1 $f8,(0x04 * 9)(a0) + swc1 $f9,(0x04 * 10)(a0) + swc1 $f10,(0x04 * 11)(a0) + swc1 $f11,(0x04 * 12)(a0) + swc1 $f12,(0x04 * 13)(a0) + swc1 $f13,(0x04 * 14)(a0) + swc1 $f14,(0x04 * 15)(a0) + swc1 $f15,(0x04 * 16)(a0) + swc1 $f16,(0x04 * 17)(a0) + swc1 $f17,(0x04 * 18)(a0) + swc1 $f18,(0x04 * 19)(a0) + swc1 $f19,(0x04 * 20)(a0) + swc1 $f20,(0x04 * 21)(a0) + swc1 $f21,(0x04 * 22)(a0) + swc1 $f22,(0x04 * 23)(a0) + swc1 $f23,(0x04 * 24)(a0) + swc1 $f24,(0x04 * 25)(a0) + swc1 $f25,(0x04 * 26)(a0) + swc1 $f26,(0x04 * 27)(a0) + swc1 $f27,(0x04 * 28)(a0) + swc1 $f28,(0x04 * 29)(a0) + swc1 $f29,(0x04 * 30)(a0) + swc1 $f30,(0x04 * 31)(a0) + swc1 $f31,(0x04 * 32)(a0) + + nop #endif - //restore a0 - lw a0, (REG_A0 * 4)(sp) + //restore a0 + lw a0, (REG_A0 * 4)(sp) - .set pop + .set pop .endm .macro RESTORE_CONTEXT - .set push - .set noat - .set noreorder - .set volatile + .set push + .set noat + .set noreorder + .set volatile #ifdef __mips_hard_float - add a0, sp,STK_CTX_SIZE + add a0, sp,STK_CTX_SIZE - mfc0 t0, CP0_STATUS - .set push - .set at + mfc0 t0, CP0_STATUS + .set push + .set at or t0, M_StatusCU1 - .set noat - mtc0 t0, CP0_STATUS + .set noat + mtc0 t0, CP0_STATUS lw t0 , 0x00(a0) - lwc1 $f0,(0x04 * 1)(a0) - lwc1 $f1,(0x04 * 2)(a0) - lwc1 $f2,(0x04 * 3)(a0) - lwc1 $f3,(0x04 * 4)(a0) - lwc1 $f4,(0x04 * 5)(a0) - lwc1 $f5,(0x04 * 6)(a0) - lwc1 $f6,(0x04 * 7)(a0) - lwc1 $f7,(0x04 * 8)(a0) - lwc1 $f8,(0x04 * 9)(a0) - lwc1 $f9,(0x04 * 10)(a0) - lwc1 $f10,(0x04 * 11)(a0) - lwc1 $f11,(0x04 * 12)(a0) - lwc1 $f12,(0x04 * 13)(a0) - lwc1 $f13,(0x04 * 14)(a0) - lwc1 $f14,(0x04 * 15)(a0) - lwc1 $f15,(0x04 * 16)(a0) - lwc1 $f16,(0x04 * 17)(a0) - lwc1 $f17,(0x04 * 18)(a0) - lwc1 $f18,(0x04 * 19)(a0) - lwc1 $f19,(0x04 * 20)(a0) - lwc1 $f20,(0x04 * 21)(a0) - lwc1 $f21,(0x04 * 22)(a0) - lwc1 $f22,(0x04 * 23)(a0) - lwc1 $f23,(0x04 * 24)(a0) - lwc1 $f24,(0x04 * 25)(a0) - lwc1 $f25,(0x04 * 26)(a0) - lwc1 $f26,(0x04 * 27)(a0) - lwc1 $f27,(0x04 * 28)(a0) - lwc1 $f28,(0x04 * 29)(a0) - lwc1 $f29,(0x04 * 30)(a0) - lwc1 $f30,(0x04 * 31)(a0) - lwc1 $f31,(0x04 * 32)(a0) - ctc1 t0, CP1_STATUS ;/* restore fpp status reg */ - - nop + lwc1 $f0,(0x04 * 1)(a0) + lwc1 $f1,(0x04 * 2)(a0) + lwc1 $f2,(0x04 * 3)(a0) + lwc1 $f3,(0x04 * 4)(a0) + lwc1 $f4,(0x04 * 5)(a0) + lwc1 $f5,(0x04 * 6)(a0) + lwc1 $f6,(0x04 * 7)(a0) + lwc1 $f7,(0x04 * 8)(a0) + lwc1 $f8,(0x04 * 9)(a0) + lwc1 $f9,(0x04 * 10)(a0) + lwc1 $f10,(0x04 * 11)(a0) + lwc1 $f11,(0x04 * 12)(a0) + lwc1 $f12,(0x04 * 13)(a0) + lwc1 $f13,(0x04 * 14)(a0) + lwc1 $f14,(0x04 * 15)(a0) + lwc1 $f15,(0x04 * 16)(a0) + lwc1 $f16,(0x04 * 17)(a0) + lwc1 $f17,(0x04 * 18)(a0) + lwc1 $f18,(0x04 * 19)(a0) + lwc1 $f19,(0x04 * 20)(a0) + lwc1 $f20,(0x04 * 21)(a0) + lwc1 $f21,(0x04 * 22)(a0) + lwc1 $f22,(0x04 * 23)(a0) + lwc1 $f23,(0x04 * 24)(a0) + lwc1 $f24,(0x04 * 25)(a0) + lwc1 $f25,(0x04 * 26)(a0) + lwc1 $f26,(0x04 * 27)(a0) + lwc1 $f27,(0x04 * 28)(a0) + lwc1 $f28,(0x04 * 29)(a0) + lwc1 $f29,(0x04 * 30)(a0) + lwc1 $f30,(0x04 * 31)(a0) + lwc1 $f31,(0x04 * 32)(a0) + ctc1 t0, CP1_STATUS ;/* restore fpp status reg */ + + nop #endif - /* ͨ通用寄存器 */ - /* ZERO */ - lw $1, ( 1 * 4)(sp) - /* V0 */ - lw $3, ( 3 * 4)(sp) - lw $4, ( 4 * 4)(sp) - lw $5, ( 5 * 4)(sp) - lw $6, ( 6 * 4)(sp) - lw $7, ( 7 * 4)(sp) - lw $8, ( 8 * 4)(sp) - lw $9, ( 9 * 4)(sp) - lw $10, (10 * 4)(sp) - lw $11, (11 * 4)(sp) - lw $12, (12 * 4)(sp) - lw $13, (13 * 4)(sp) - lw $14, (14 * 4)(sp) - lw $15, (15 * 4)(sp) - lw $16, (16 * 4)(sp) - lw $17, (17 * 4)(sp) - lw $18, (18 * 4)(sp) - lw $19, (19 * 4)(sp) - lw $20, (20 * 4)(sp) - lw $21, (21 * 4)(sp) - lw $22, (22 * 4)(sp) - lw $23, (23 * 4)(sp) - lw $24, (24 * 4)(sp) - lw $25, (25 * 4)(sp) - lw $26, (26 * 4)(sp) - lw $27, (27 * 4)(sp) - lw $28, (28 * 4)(sp) - /* SP */ - lw $30, (30 * 4)(sp) - lw $31, (31 * 4)(sp) - - - /* STATUS CAUSE EPC.... */ - lw $2, STK_OFFSET_HI(sp) - mthi $2 - lw $2, STK_OFFSET_LO(sp) - mtlo $2 - - lw $2, STK_OFFSET_SR(sp) - mtc0 $2, CP0_STATUS - - lw $2, STK_OFFSET_BADVADDR(sp) - mtc0 $2, CP0_BADVADDR - - lw $2, STK_OFFSET_CAUSE(sp) - mtc0 $2, CP0_CAUSE - - lw $2, STK_OFFSET_EPC(sp) - MTC0 $2, CP0_EPC - - //restore $2 - lw $2, ( 2 * 4)(sp) - //restore sp - lw $29, (29 * 4)(sp) - - eret - nop + /* ͨ通用寄存器 */ + /* ZERO */ + lw $1, ( 1 * 4)(sp) + /* V0 */ + lw $3, ( 3 * 4)(sp) + lw $4, ( 4 * 4)(sp) + lw $5, ( 5 * 4)(sp) + lw $6, ( 6 * 4)(sp) + lw $7, ( 7 * 4)(sp) + lw $8, ( 8 * 4)(sp) + lw $9, ( 9 * 4)(sp) + lw $10, (10 * 4)(sp) + lw $11, (11 * 4)(sp) + lw $12, (12 * 4)(sp) + lw $13, (13 * 4)(sp) + lw $14, (14 * 4)(sp) + lw $15, (15 * 4)(sp) + lw $16, (16 * 4)(sp) + lw $17, (17 * 4)(sp) + lw $18, (18 * 4)(sp) + lw $19, (19 * 4)(sp) + lw $20, (20 * 4)(sp) + lw $21, (21 * 4)(sp) + lw $22, (22 * 4)(sp) + lw $23, (23 * 4)(sp) + lw $24, (24 * 4)(sp) + lw $25, (25 * 4)(sp) + lw $26, (26 * 4)(sp) + lw $27, (27 * 4)(sp) + lw $28, (28 * 4)(sp) + /* SP */ + lw $30, (30 * 4)(sp) + lw $31, (31 * 4)(sp) + + + /* STATUS CAUSE EPC.... */ + lw $2, STK_OFFSET_HI(sp) + mthi $2 + lw $2, STK_OFFSET_LO(sp) + mtlo $2 + + lw $2, STK_OFFSET_SR(sp) + mtc0 $2, CP0_STATUS + + lw $2, STK_OFFSET_BADVADDR(sp) + mtc0 $2, CP0_BADVADDR + + lw $2, STK_OFFSET_CAUSE(sp) + mtc0 $2, CP0_CAUSE + + lw $2, STK_OFFSET_EPC(sp) + MTC0 $2, CP0_EPC + + //restore $2 + lw $2, ( 2 * 4)(sp) + //restore sp + lw $29, (29 * 4)(sp) + + eret + nop .set pop .endm #endif diff --git a/libcpu/mips/common/mips_def.h b/libcpu/mips/common/mips_def.h index 1727684f50..3ac965f65a 100644 --- a/libcpu/mips/common/mips_def.h +++ b/libcpu/mips/common/mips_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -35,24 +35,24 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define S_InstnOpcode 26 -#define M_InstnOpcode (0x3f << S_InstnOpcode) -#define S_InstnRS 21 -#define M_InstnRS (0x1f << S_InstnRS) -#define S_InstnRT 16 -#define M_InstnRT (0x1f << S_InstnRT) -#define S_InstnRD 11 -#define M_InstnRD (0x1f << S_InstnRD) -#define S_InstnSA 6 -#define M_InstnSA (0x1f << S_InstnSA) -#define S_InstnTcode 6 -#define M_InstnTcode (0x3ff << S_InstnTcode) -#define S_InstnBcode 6 -#define M_InstnBcode (0xfffff << S_InstnBcode) -#define S_InstnFunc 0 -#define M_InstnFunc (0x3f << S_InstnFunc) -#define S_InstnSel 0 -#define M_InstnSel (0x7 << S_InstnSel) +#define S_InstnOpcode 26 +#define M_InstnOpcode (0x3f << S_InstnOpcode) +#define S_InstnRS 21 +#define M_InstnRS (0x1f << S_InstnRS) +#define S_InstnRT 16 +#define M_InstnRT (0x1f << S_InstnRT) +#define S_InstnRD 11 +#define M_InstnRD (0x1f << S_InstnRD) +#define S_InstnSA 6 +#define M_InstnSA (0x1f << S_InstnSA) +#define S_InstnTcode 6 +#define M_InstnTcode (0x3ff << S_InstnTcode) +#define S_InstnBcode 6 +#define M_InstnBcode (0xfffff << S_InstnBcode) +#define S_InstnFunc 0 +#define M_InstnFunc (0x3f << S_InstnFunc) +#define S_InstnSel 0 +#define M_InstnSel (0x7 << S_InstnSel) /* * I-Type (load, store, branch, immediate) @@ -64,8 +64,8 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define S_InstnOffset 0 -#define M_InstnOffset (0xffff << S_InstnOffset) +#define S_InstnOffset 0 +#define M_InstnOffset (0xffff << S_InstnOffset) /* * I-Type (pref) @@ -77,8 +77,8 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define S_InstnHint S_InstnRT -#define M_InstnHint M_InstnRT +#define S_InstnHint S_InstnRT +#define M_InstnHint M_InstnRT /* * J-Type (jump) @@ -90,8 +90,8 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define S_InstnJIndex 0 -#define M_InstnJIndex (0x03ffffff << S_InstnJIndex) +#define S_InstnJIndex 0 +#define M_InstnJIndex (0x03ffffff << S_InstnJIndex) /* * FP R-Type (operate) @@ -103,14 +103,14 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define S_InstnFmt S_InstnRS -#define M_InstnFmt M_InstnRS -#define S_InstnFT S_InstnRT -#define M_InstnFT M_InstnRT -#define S_InstnFS S_InstnRD -#define M_InstnFS M_InstnRD -#define S_InstnFD S_InstnSA -#define M_InstnFD M_InstnSA +#define S_InstnFmt S_InstnRS +#define M_InstnFmt M_InstnRS +#define S_InstnFT S_InstnRT +#define M_InstnFT M_InstnRT +#define S_InstnFS S_InstnRD +#define M_InstnFS M_InstnRD +#define S_InstnFD S_InstnSA +#define M_InstnFD M_InstnSA /* * FP R-Type (cpu <-> cpu data movement)) @@ -122,8 +122,8 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define S_InstnSub S_InstnRS -#define M_InstnSub M_InstnRS +#define S_InstnSub S_InstnRS +#define M_InstnSub M_InstnRS /* * FP R-Type (compare) @@ -137,10 +137,10 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define S_InstnCCcmp 8 -#define M_InstnCCcmp (0x7 << S_InstnCCcmp) -#define S_InstnCABS 6 -#define M_InstnCABS (0x1 << S_InstnCABS) +#define S_InstnCCcmp 8 +#define M_InstnCCcmp (0x7 << S_InstnCCcmp) +#define S_InstnCABS 6 +#define M_InstnCABS (0x1 << S_InstnCABS) /* * FP R-Type (FPR conditional move on FP cc) @@ -153,12 +153,12 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define S_InstnCC 18 -#define M_InstnCC (0x7 << S_InstnCC) -#define S_InstnND 17 -#define M_InstnND (0x1 << S_InstnND) -#define S_InstnTF 16 -#define M_InstnTF (0x1 << S_InstnTF) +#define S_InstnCC 18 +#define M_InstnCC (0x7 << S_InstnCC) +#define S_InstnND 17 +#define M_InstnND (0x1 << S_InstnND) +#define S_InstnTF 16 +#define M_InstnTF (0x1 << S_InstnTF) /* * FP R-Type (3-operand operate) @@ -170,12 +170,12 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define S_InstnFR S_InstnRS -#define M_InstnFR M_InstnRS -#define S_InstnOp4 3 -#define M_InstnOp4 (0x7 << S_InstnOp4) -#define S_InstnFmt3 0 -#define M_InstnFmt3 (0x7 << S_InstnFmt3) +#define S_InstnFR S_InstnRS +#define M_InstnFR M_InstnRS +#define S_InstnOp4 3 +#define M_InstnOp4 (0x7 << S_InstnOp4) +#define S_InstnFmt3 0 +#define M_InstnFmt3 (0x7 << S_InstnFmt3) /* * FP R-Type (Indexed load, store) @@ -196,8 +196,8 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define S_InstnHintX S_InstnRD -#define M_InstnHintX M_InstnRD +#define S_InstnHintX S_InstnRD +#define M_InstnHintX M_InstnRD /* * FP R-Type (GPR conditional move on FP cc) @@ -239,19 +239,19 @@ */ #ifdef MIPSADDR64 -#define A_K0BASE UNS64Const(0xffffffff80000000) -#define A_K1BASE UNS64Const(0xffffffffa0000000) -#define A_K2BASE UNS64Const(0xffffffffc0000000) -#define A_K3BASE UNS64Const(0xffffffffe0000000) -#define A_REGION UNS64Const(0xc000000000000000) -#define A_XKPHYS_ATTR UNS64Const(0x3800000000000000) +#define A_K0BASE UNS64Const(0xffffffff80000000) +#define A_K1BASE UNS64Const(0xffffffffa0000000) +#define A_K2BASE UNS64Const(0xffffffffc0000000) +#define A_K3BASE UNS64Const(0xffffffffe0000000) +#define A_REGION UNS64Const(0xc000000000000000) +#define A_XKPHYS_ATTR UNS64Const(0x3800000000000000) #else -#define A_K0BASE 0x80000000 -#define A_K1BASE 0xa0000000 -#define A_K2BASE 0xc0000000 -#define A_K3BASE 0xe0000000 +#define A_K0BASE 0x80000000 +#define A_K1BASE 0xa0000000 +#define A_K2BASE 0xc0000000 +#define A_K3BASE 0xe0000000 #endif -#define M_KMAPPED 0x40000000 /* KnSEG address is mapped if bit is one */ +#define M_KMAPPED 0x40000000 /* KnSEG address is mapped if bit is one */ #ifdef MIPS_Model64 @@ -352,41 +352,41 @@ /* * Cache encodings */ -#define K_CachePriI 0 /* Primary Icache */ -#define K_CachePriD 1 /* Primary Dcache */ -#define K_CachePriU 1 /* Unified primary */ -#define K_CacheTerU 2 /* Unified Tertiary */ -#define K_CacheSecU 3 /* Unified secondary */ +#define K_CachePriI 0 /* Primary Icache */ +#define K_CachePriD 1 /* Primary Dcache */ +#define K_CachePriU 1 /* Unified primary */ +#define K_CacheTerU 2 /* Unified Tertiary */ +#define K_CacheSecU 3 /* Unified secondary */ /* * Function encodings */ -#define S_CacheFunc 2 /* Amount to shift function encoding within 5-bit field */ -#define K_CacheIndexInv 0 /* Index invalidate */ -#define K_CacheIndexWBInv 0 /* Index writeback invalidate */ -#define K_CacheIndexLdTag 1 /* Index load tag */ -#define K_CacheIndexStTag 2 /* Index store tag */ -#define K_CacheHitInv 4 /* Hit Invalidate */ -#define K_CacheFill 5 /* Fill (Icache only) */ -#define K_CacheHitWBInv 5 /* Hit writeback invalidate */ -#define K_CacheHitWB 6 /* Hit writeback */ -#define K_CacheFetchLock 7 /* Fetch and lock */ - -#define ICIndexInv ((K_CacheIndexInv << S_CacheFunc) | K_CachePriI) -#define DCIndexWBInv ((K_CacheIndexWBInv << S_CacheFunc) | K_CachePriD) -#define DCIndexInv DCIndexWBInv -#define ICIndexLdTag ((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriI) -#define DCIndexLdTag ((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriD) -#define ICIndexStTag ((K_CacheIndexStTag << S_CacheFunc) | K_CachePriI) -#define DCIndexStTag ((K_CacheIndexStTag << S_CacheFunc) | K_CachePriD) -#define ICHitInv ((K_CacheHitInv << S_CacheFunc) | K_CachePriI) -#define DCHitInv ((K_CacheHitInv << S_CacheFunc) | K_CachePriD) -#define ICFill ((K_CacheFill << S_CacheFunc) | K_CachePriI) -#define DCHitWBInv ((K_CacheHitWBInv << S_CacheFunc) | K_CachePriD) -#define DCHitWB ((K_CacheHitWB << S_CacheFunc) | K_CachePriD) -#define ICFetchLock ((K_CacheFetchLock << S_CacheFunc) | K_CachePriI) -#define DCFetchLock ((K_CacheFetchLock << S_CacheFunc) | K_CachePriD) +#define S_CacheFunc 2 /* Amount to shift function encoding within 5-bit field */ +#define K_CacheIndexInv 0 /* Index invalidate */ +#define K_CacheIndexWBInv 0 /* Index writeback invalidate */ +#define K_CacheIndexLdTag 1 /* Index load tag */ +#define K_CacheIndexStTag 2 /* Index store tag */ +#define K_CacheHitInv 4 /* Hit Invalidate */ +#define K_CacheFill 5 /* Fill (Icache only) */ +#define K_CacheHitWBInv 5 /* Hit writeback invalidate */ +#define K_CacheHitWB 6 /* Hit writeback */ +#define K_CacheFetchLock 7 /* Fetch and lock */ + +#define ICIndexInv ((K_CacheIndexInv << S_CacheFunc) | K_CachePriI) +#define DCIndexWBInv ((K_CacheIndexWBInv << S_CacheFunc) | K_CachePriD) +#define DCIndexInv DCIndexWBInv +#define ICIndexLdTag ((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriI) +#define DCIndexLdTag ((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriD) +#define ICIndexStTag ((K_CacheIndexStTag << S_CacheFunc) | K_CachePriI) +#define DCIndexStTag ((K_CacheIndexStTag << S_CacheFunc) | K_CachePriD) +#define ICHitInv ((K_CacheHitInv << S_CacheFunc) | K_CachePriI) +#define DCHitInv ((K_CacheHitInv << S_CacheFunc) | K_CachePriD) +#define ICFill ((K_CacheFill << S_CacheFunc) | K_CachePriI) +#define DCHitWBInv ((K_CacheHitWBInv << S_CacheFunc) | K_CachePriD) +#define DCHitWB ((K_CacheHitWB << S_CacheFunc) | K_CachePriD) +#define ICFetchLock ((K_CacheFetchLock << S_CacheFunc) | K_CachePriI) +#define DCFetchLock ((K_CacheFetchLock << S_CacheFunc) | K_CachePriD) /* @@ -395,14 +395,14 @@ ************************************************************************* */ -#define PrefLoad 0 -#define PrefStore 1 -#define PrefLoadStreamed 4 -#define PrefStoreStreamed 5 -#define PrefLoadRetained 6 -#define PrefStoreRetained 7 -#define PrefWBInval 25 -#define PrefNudge 25 +#define PrefLoad 0 +#define PrefStore 1 +#define PrefLoadStreamed 4 +#define PrefStoreStreamed 5 +#define PrefLoadRetained 6 +#define PrefStoreRetained 7 +#define PrefWBInval 25 +#define PrefNudge 25 /* @@ -418,38 +418,38 @@ ************************************************************************* */ #ifdef __ASSEMBLY__ -#define zero $0 -#define AT $1 -#define v0 $2 -#define v1 $3 -#define a0 $4 -#define a1 $5 -#define a2 $6 -#define a3 $7 -#define t0 $8 -#define t1 $9 -#define t2 $10 -#define t3 $11 -#define t4 $12 -#define t5 $13 -#define t6 $14 -#define t7 $15 -#define s0 $16 -#define s1 $17 -#define s2 $18 -#define s3 $19 -#define s4 $20 -#define s5 $21 -#define s6 $22 -#define s7 $23 -#define t8 $24 -#define t9 $25 -#define k0 $26 -#define k1 $27 -#define gp $28 -#define sp $29 -#define fp $30 -#define ra $31 +#define zero $0 +#define AT $1 +#define v0 $2 +#define v1 $3 +#define a0 $4 +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define t0 $8 +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define t5 $13 +#define t6 $14 +#define t7 $15 +#define s0 $16 +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 +#define t9 $25 +#define k0 $26 +#define k1 $27 +#define gp $28 +#define sp $29 +#define fp $30 +#define ra $31 /* * The following registers are used by the AVP environment and @@ -457,8 +457,8 @@ */ #ifdef MIPSAVPENV -#define repc $25 /* Expected exception PC */ -#define tid $30 /* Current test case address */ +#define repc $25 /* Expected exception PC */ +#define tid $30 /* Current test case address */ #endif @@ -472,53 +472,53 @@ * Removing them causes assembly rather than runtime errors for tests that * use the `r' names. * - * - r25 (repc) is used as the expected PC on an exception - * - r26-r27 (k0, k1) are used in the exception handler - * - r30 (tid) is used as the current test address - */ - -#define r0 $0 -#define r1 $1 -#define r2 $2 -#define r3 $3 -#define r4 $4 -#define r5 $5 -#define r6 $6 -#define r7 $7 -#define r8 $8 -#define r9 $9 -#define r10 $10 -#define r11 $11 -#define r12 $12 -#define r13 $13 -#define r14 $14 -#define r15 $15 -#define r16 $16 -#define r17 $17 -#define r18 $18 -#define r19 $19 -#define r20 $20 -#define r21 $21 -#define r22 $22 -#define r23 $23 -#define r24 $24 + * - r25 (repc) is used as the expected PC on an exception + * - r26-r27 (k0, k1) are used in the exception handler + * - r30 (tid) is used as the current test address + */ + +#define r0 $0 +#define r1 $1 +#define r2 $2 +#define r3 $3 +#define r4 $4 +#define r5 $5 +#define r6 $6 +#define r7 $7 +#define r8 $8 +#define r9 $9 +#define r10 $10 +#define r11 $11 +#define r12 $12 +#define r13 $13 +#define r14 $14 +#define r15 $15 +#define r16 $16 +#define r17 $17 +#define r18 $18 +#define r19 $19 +#define r20 $20 +#define r21 $21 +#define r22 $22 +#define r23 $23 +#define r24 $24 #ifdef MIPSAVPENV -#define r25 r25_unknown -#define r26 r26_unknown -#define r27 r27_unknown +#define r25 r25_unknown +#define r26 r26_unknown +#define r27 r27_unknown #else -#define r25 $25 -#define r26 $26 -#define r27 $27 +#define r25 $25 +#define r26 $26 +#define r27 $27 #endif -#define r28 $28 -#define r29 $29 +#define r28 $28 +#define r29 $29 #ifdef MIPSAVPENV -#define r30 r30_unknown +#define r30 r30_unknown #else -#define r30 $30 +#define r30 $30 #endif -#define r31 $31 +#define r31 $31 #endif @@ -531,40 +531,40 @@ * to the assembler register name ($n). */ -#define R_r0 0 -#define R_r1 1 -#define R_r2 2 -#define R_r3 3 -#define R_r4 4 -#define R_r5 5 -#define R_r6 6 -#define R_r7 7 -#define R_r8 8 -#define R_r9 9 -#define R_r10 10 -#define R_r11 11 -#define R_r12 12 -#define R_r13 13 -#define R_r14 14 -#define R_r15 15 -#define R_r16 16 -#define R_r17 17 -#define R_r18 18 -#define R_r19 19 -#define R_r20 20 -#define R_r21 21 -#define R_r22 22 -#define R_r23 23 -#define R_r24 24 -#define R_r25 25 -#define R_r26 26 -#define R_r27 27 -#define R_r28 28 -#define R_r29 29 -#define R_r30 30 -#define R_r31 31 -#define R_hi 32 /* Hi register */ -#define R_lo 33 /* Lo register */ +#define R_r0 0 +#define R_r1 1 +#define R_r2 2 +#define R_r3 3 +#define R_r4 4 +#define R_r5 5 +#define R_r6 6 +#define R_r7 7 +#define R_r8 8 +#define R_r9 9 +#define R_r10 10 +#define R_r11 11 +#define R_r12 12 +#define R_r13 13 +#define R_r14 14 +#define R_r15 15 +#define R_r16 16 +#define R_r17 17 +#define R_r18 18 +#define R_r19 19 +#define R_r20 20 +#define R_r21 21 +#define R_r22 22 +#define R_r23 23 +#define R_r24 24 +#define R_r25 25 +#define R_r26 26 +#define R_r27 27 +#define R_r28 28 +#define R_r29 29 +#define R_r30 30 +#define R_r31 31 +#define R_hi 32 /* Hi register */ +#define R_lo 33 /* Lo register */ /* @@ -575,37 +575,37 @@ * These definitions provide the bit mask corresponding to the GPR number */ -#define M_AT (1<<1) -#define M_v0 (1<<2) -#define M_v1 (1<<3) -#define M_a0 (1<<4) -#define M_a1 (1<<5) -#define M_a2 (1<<6) -#define M_a3 (1<<7) -#define M_t0 (1<<8) -#define M_t1 (1<<9) -#define M_t2 (1<<10) -#define M_t3 (1<<11) -#define M_t4 (1<<12) -#define M_t5 (1<<13) -#define M_t6 (1<<14) -#define M_t7 (1<<15) -#define M_s0 (1<<16) -#define M_s1 (1<<17) -#define M_s2 (1<<18) -#define M_s3 (1<<19) -#define M_s4 (1<<20) -#define M_s5 (1<<21) -#define M_s6 (1<<22) -#define M_s7 (1<<23) -#define M_t8 (1<<24) -#define M_t9 (1<<25) -#define M_k0 (1<<26) -#define M_k1 (1<<27) -#define M_gp (1<<28) -#define M_sp (1<<29) -#define M_fp (1<<30) -#define M_ra (1<<31) +#define M_AT (1<<1) +#define M_v0 (1<<2) +#define M_v1 (1<<3) +#define M_a0 (1<<4) +#define M_a1 (1<<5) +#define M_a2 (1<<6) +#define M_a3 (1<<7) +#define M_t0 (1<<8) +#define M_t1 (1<<9) +#define M_t2 (1<<10) +#define M_t3 (1<<11) +#define M_t4 (1<<12) +#define M_t5 (1<<13) +#define M_t6 (1<<14) +#define M_t7 (1<<15) +#define M_s0 (1<<16) +#define M_s1 (1<<17) +#define M_s2 (1<<18) +#define M_s3 (1<<19) +#define M_s4 (1<<20) +#define M_s5 (1<<21) +#define M_s6 (1<<22) +#define M_s7 (1<<23) +#define M_t8 (1<<24) +#define M_t9 (1<<25) +#define M_k0 (1<<26) +#define M_k1 (1<<27) +#define M_gp (1<<28) +#define M_sp (1<<29) +#define M_fp (1<<30) +#define M_ra (1<<31) /* @@ -614,16 +614,16 @@ ************************************************************************* * Each register has the following definitions: * - * C0_rrr The register number (as a $n value) - * R_C0_rrr The register index (as an integer corresponding - * to the register number) + * C0_rrr The register number (as a $n value) + * R_C0_rrr The register index (as an integer corresponding + * to the register number) * * Each field in a register has the following definitions: * - * S_rrrfff The shift count required to right-justify - * the field. This corresponds to the bit - * number of the right-most bit in the field. - * M_rrrfff The Mask required to isolate the field. + * S_rrrfff The shift count required to right-justify + * the field. This corresponds to the bit + * number of the right-most bit in the field. + * M_rrrfff The Mask required to isolate the field. * * Register diagrams included below as comments correspond to the * MIPS32 and MIPS64 architecture specifications. Refer to other @@ -643,18 +643,18 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_Index $0 -#define R_C0_Index 0 -#define C0_INX C0_Index /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_Index $0 +#define R_C0_Index 0 +#define C0_INX C0_Index /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define S_IndexP 31 /* Probe failure (R)*/ -#define M_IndexP (0x1 << S_IndexP) +#define S_IndexP 31 /* Probe failure (R)*/ +#define M_IndexP (0x1 << S_IndexP) -#define S_IndexIndex 0 /* TLB index (R/W)*/ -#define M_IndexIndex (0x3f << S_IndexIndex) +#define S_IndexIndex 0 /* TLB index (R/W)*/ +#define M_IndexIndex (0x3f << S_IndexIndex) -#define M_Index0Fields 0x7fffffc0 -#define M_IndexRFields 0x80000000 +#define M_Index0Fields 0x7fffffc0 +#define M_IndexRFields 0x80000000 /* @@ -669,15 +669,15 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_Random $1 -#define R_C0_Random 1 -#define C0_RAND $1 /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_Random $1 +#define R_C0_Random 1 +#define C0_RAND $1 /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define S_RandomIndex 0 /* TLB random index (R)*/ -#define M_RandomIndex (0x3f << S_RandomIndex) +#define S_RandomIndex 0 /* TLB random index (R)*/ +#define M_RandomIndex (0x3f << S_RandomIndex) -#define M_Random0Fields 0xffffffc0 -#define M_RandomRFields 0x0000003f +#define M_Random0Fields 0xffffffc0 +#define M_RandomRFields 0x0000003f /* @@ -692,42 +692,42 @@ * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_EntryLo0 $2 -#define R_C0_EntryLo0 2 -#define C0_TLBLO_0 C0_EntryLo0 /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_EntryLo0 $2 +#define R_C0_EntryLo0 2 +#define C0_TLBLO_0 C0_EntryLo0 /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define S_EntryLoPFN 6 /* PFN (R/W) */ -#define M_EntryLoPFN (0xffffff << S_EntryLoPFN) -#define S_EntryLoC 3 /* Coherency attribute (R/W) */ -#define M_EntryLoC (0x7 << S_EntryLoC) -#define S_EntryLoD 2 /* Dirty (R/W) */ -#define M_EntryLoD (0x1 << S_EntryLoD) -#define S_EntryLoV 1 /* Valid (R/W) */ -#define M_EntryLoV (0x1 << S_EntryLoV) -#define S_EntryLoG 0 /* Global (R/W) */ -#define M_EntryLoG (0x1 << S_EntryLoG) -#define M_EntryLoOddPFN (0x1 << S_EntryLoPFN) /* Odd PFN bit */ -#define S_EntryLo_RS K_PageAlign /* Right-justify PFN */ -#define S_EntryLo_LS S_EntryLoPFN /* Position PFN to appropriate position */ +#define S_EntryLoPFN 6 /* PFN (R/W) */ +#define M_EntryLoPFN (0xffffff << S_EntryLoPFN) +#define S_EntryLoC 3 /* Coherency attribute (R/W) */ +#define M_EntryLoC (0x7 << S_EntryLoC) +#define S_EntryLoD 2 /* Dirty (R/W) */ +#define M_EntryLoD (0x1 << S_EntryLoD) +#define S_EntryLoV 1 /* Valid (R/W) */ +#define M_EntryLoV (0x1 << S_EntryLoV) +#define S_EntryLoG 0 /* Global (R/W) */ +#define M_EntryLoG (0x1 << S_EntryLoG) +#define M_EntryLoOddPFN (0x1 << S_EntryLoPFN) /* Odd PFN bit */ +#define S_EntryLo_RS K_PageAlign /* Right-justify PFN */ +#define S_EntryLo_LS S_EntryLoPFN /* Position PFN to appropriate position */ -#define M_EntryLo0Fields 0x00000000 -#define M_EntryLoRFields 0xc0000000 -#define M_EntryLo0Fields64 UNS64Const(0x0000000000000000) -#define M_EntryLoRFields64 UNS64Const(0xffffffffc0000000) +#define M_EntryLo0Fields 0x00000000 +#define M_EntryLoRFields 0xc0000000 +#define M_EntryLo0Fields64 UNS64Const(0x0000000000000000) +#define M_EntryLoRFields64 UNS64Const(0xffffffffc0000000) /* * Cache attribute values in the C field of EntryLo and the * K0 field of Config */ -#define K_CacheAttrCWTnWA 0 /* Cacheable, write-thru, no write allocate */ -#define K_CacheAttrCWTWA 1 /* Cacheable, write-thru, write allocate */ -#define K_CacheAttrU 2 /* Uncached */ -#define K_CacheAttrC 3 /* Cacheable */ -#define K_CacheAttrCN 3 /* Cacheable, non-coherent */ -#define K_CacheAttrCCE 4 /* Cacheable, coherent, exclusive */ -#define K_CacheAttrCCS 5 /* Cacheable, coherent, shared */ -#define K_CacheAttrCCU 6 /* Cacheable, coherent, update */ -#define K_CacheAttrUA 7 /* Uncached accelerated */ +#define K_CacheAttrCWTnWA 0 /* Cacheable, write-thru, no write allocate */ +#define K_CacheAttrCWTWA 1 /* Cacheable, write-thru, write allocate */ +#define K_CacheAttrU 2 /* Uncached */ +#define K_CacheAttrC 3 /* Cacheable */ +#define K_CacheAttrCN 3 /* Cacheable, non-coherent */ +#define K_CacheAttrCCE 4 /* Cacheable, coherent, exclusive */ +#define K_CacheAttrCCS 5 /* Cacheable, coherent, shared */ +#define K_CacheAttrCCU 6 /* Cacheable, coherent, update */ +#define K_CacheAttrUA 7 /* Uncached accelerated */ /* @@ -742,9 +742,9 @@ * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_EntryLo1 $3 -#define R_C0_EntryLo1 3 -#define C0_TLBLO_1 C0_EntryLo1 /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_EntryLo1 $3 +#define R_C0_EntryLo1 3 +#define C0_TLBLO_1 C0_EntryLo1 /* OBSOLETE - DO NOT USE IN NEW CODE */ /* * Field definitions are as given for EntryLo0 above @@ -763,21 +763,21 @@ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_Context $4 -#define R_C0_Context 4 -#define C0_CTXT C0_Context /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_Context $4 +#define R_C0_Context 4 +#define C0_CTXT C0_Context /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define S_ContextPTEBase 23 /* PTE base (R/W) */ -#define M_ContextPTEBase (0x1ff << S_ContextPTEBase) -#define S_ContextBadVPN 4 /* BadVPN2 (R) */ -#define M_ContextBadVPN (0x7ffff << S_ContextBadVPN) -#define S_ContextBadVPN_LS 9 /* Position BadVPN to bit 31 */ -#define S_ContextBadVPN_RS 13 /* Right-justify shifted BadVPN field */ +#define S_ContextPTEBase 23 /* PTE base (R/W) */ +#define M_ContextPTEBase (0x1ff << S_ContextPTEBase) +#define S_ContextBadVPN 4 /* BadVPN2 (R) */ +#define M_ContextBadVPN (0x7ffff << S_ContextBadVPN) +#define S_ContextBadVPN_LS 9 /* Position BadVPN to bit 31 */ +#define S_ContextBadVPN_RS 13 /* Right-justify shifted BadVPN field */ -#define M_Context0Fields 0x0000000f -#define M_ContextRFields 0x007ffff0 -#define M_Context0Fields64 UNS64Const(0x000000000000000f) -#define M_ContextRFields64 UNS64Const(0x00000000007ffff0) +#define M_Context0Fields 0x0000000f +#define M_ContextRFields 0x007ffff0 +#define M_Context0Fields64 UNS64Const(0x000000000000000f) +#define M_ContextRFields64 UNS64Const(0x00000000007ffff0) /* @@ -792,34 +792,34 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_PageMask $5 -#define R_C0_PageMask 5 /* Mask (R/W) */ -#define C0_PGMASK C0_PageMask /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_PageMask $5 +#define R_C0_PageMask 5 /* Mask (R/W) */ +#define C0_PGMASK C0_PageMask /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define S_PageMaskMask 13 -#define M_PageMaskMask (0xfff << S_PageMaskMask) +#define S_PageMaskMask 13 +#define M_PageMaskMask (0xfff << S_PageMaskMask) -#define M_PageMask0Fields 0xfe001fff -#define M_PageMaskRFields 0x00000000 +#define M_PageMask0Fields 0xfe001fff +#define M_PageMaskRFields 0x00000000 /* * Values in the Mask field */ -#define K_PageMask4K 0x000 /* K_PageMasknn values are values for use */ -#define K_PageMask16K 0x003 /* with KReqPageAttributes or KReqPageMask macros */ -#define K_PageMask64K 0x00f -#define K_PageMask256K 0x03f -#define K_PageMask1M 0x0ff -#define K_PageMask4M 0x3ff -#define K_PageMask16M 0xfff +#define K_PageMask4K 0x000 /* K_PageMasknn values are values for use */ +#define K_PageMask16K 0x003 /* with KReqPageAttributes or KReqPageMask macros */ +#define K_PageMask64K 0x00f +#define K_PageMask256K 0x03f +#define K_PageMask1M 0x0ff +#define K_PageMask4M 0x3ff +#define K_PageMask16M 0xfff -#define M_PageMask4K (K_PageMask4K << S_PageMaskMask) /* M_PageMasknn values are masks */ -#define M_PageMask16K (K_PageMask16K << S_PageMaskMask) /* in position in the PageMask register */ -#define M_PageMask64K (K_PageMask64K << S_PageMaskMask) -#define M_PageMask256K (K_PageMask256K << S_PageMaskMask) -#define M_PageMask1M (K_PageMask1M << S_PageMaskMask) -#define M_PageMask4M (K_PageMask4M << S_PageMaskMask) -#define M_PageMask16M (K_PageMask16M << S_PageMaskMask) +#define M_PageMask4K (K_PageMask4K << S_PageMaskMask) /* M_PageMasknn values are masks */ +#define M_PageMask16K (K_PageMask16K << S_PageMaskMask) /* in position in the PageMask register */ +#define M_PageMask64K (K_PageMask64K << S_PageMaskMask) +#define M_PageMask256K (K_PageMask256K << S_PageMaskMask) +#define M_PageMask1M (K_PageMask1M << S_PageMaskMask) +#define M_PageMask4M (K_PageMask4M << S_PageMaskMask) +#define M_PageMask16M (K_PageMask16M << S_PageMaskMask) /* @@ -834,15 +834,15 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_Wired $6 -#define R_C0_Wired 6 -#define C0_TLBWIRED C0_Wired /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_Wired $6 +#define R_C0_Wired 6 +#define C0_TLBWIRED C0_Wired /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define S_WiredIndex 0 /* TLB wired boundary (R/W) */ -#define M_WiredIndex (0x3f << S_WiredIndex) +#define S_WiredIndex 0 /* TLB wired boundary (R/W) */ +#define M_WiredIndex (0x3f << S_WiredIndex) -#define M_Wired0Fields 0xffffffc0 -#define M_WiredRFields 0x00000000 +#define M_Wired0Fields 0xffffffc0 +#define M_WiredRFields 0x00000000 /* @@ -857,16 +857,16 @@ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_BadVAddr $8 -#define R_C0_BadVAddr 8 -#define C0_BADVADDR C0_BadVAddr /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_BadVAddr $8 +#define R_C0_BadVAddr 8 +#define C0_BADVADDR C0_BadVAddr /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define M_BadVAddrOddPage K_PageSize /* Even/Odd VA bit for pair of PAs */ +#define M_BadVAddrOddPage K_PageSize /* Even/Odd VA bit for pair of PAs */ -#define M_BadVAddr0Fields 0x00000000 -#define M_BadVAddrRFields 0xffffffff -#define M_BadVAddr0Fields64 UNS64Const(0x0000000000000000) -#define M_BadVAddrRFields64 UNS64Const(0xffffffffffffffff) +#define M_BadVAddr0Fields 0x00000000 +#define M_BadVAddrRFields 0xffffffff +#define M_BadVAddr0Fields64 UNS64Const(0x0000000000000000) +#define M_BadVAddrRFields64 UNS64Const(0xffffffffffffffff) /* ************************************************************************ @@ -880,12 +880,12 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_Count $9 -#define R_C0_Count 9 -#define C0_COUNT C0_Count /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_Count $9 +#define R_C0_Count 9 +#define C0_COUNT C0_Count /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define M_Count0Fields 0x00000000 -#define M_CountRFields 0x00000000 +#define M_Count0Fields 0x00000000 +#define M_CountRFields 0x00000000 /* @@ -900,23 +900,23 @@ * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_EntryHi $10 -#define R_C0_EntryHi 10 -#define C0_TLBHI C0_EntryHi /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_EntryHi $10 +#define R_C0_EntryHi 10 +#define C0_TLBHI C0_EntryHi /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define S_EntryHiR64 62 /* Region (R/W) */ -#define M_EntryHiR64 UNS64Const(0xc000000000000000) -#define S_EntryHiVPN2 13 /* VPN/2 (R/W) */ -#define M_EntryHiVPN2 (0x7ffff << S_EntryHiVPN2) -#define M_EntryHiVPN264 UNS64Const(0x000000ffffffe000) -#define S_EntryHiASID 0 /* ASID (R/W) */ -#define M_EntryHiASID (0xff << S_EntryHiASID) -#define S_EntryHiVPN_Shf S_EntryHiVPN2 +#define S_EntryHiR64 62 /* Region (R/W) */ +#define M_EntryHiR64 UNS64Const(0xc000000000000000) +#define S_EntryHiVPN2 13 /* VPN/2 (R/W) */ +#define M_EntryHiVPN2 (0x7ffff << S_EntryHiVPN2) +#define M_EntryHiVPN264 UNS64Const(0x000000ffffffe000) +#define S_EntryHiASID 0 /* ASID (R/W) */ +#define M_EntryHiASID (0xff << S_EntryHiASID) +#define S_EntryHiVPN_Shf S_EntryHiVPN2 -#define M_EntryHi0Fields 0x00001f00 -#define M_EntryHiRFields 0x00000000 -#define M_EntryHi0Fields64 UNS64Const(0x0000000000001f00) -#define M_EntryHiRFields64 UNS64Const(0x3fffff0000000000) +#define M_EntryHi0Fields 0x00001f00 +#define M_EntryHiRFields 0x00000000 +#define M_EntryHi0Fields64 UNS64Const(0x0000000000001f00) +#define M_EntryHiRFields64 UNS64Const(0x3fffff0000000000) /* @@ -931,12 +931,12 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_Compare $11 -#define R_C0_Compare 11 -#define C0_COMPARE C0_Compare /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_Compare $11 +#define R_C0_Compare 11 +#define C0_COMPARE C0_Compare /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define M_Compare0Fields 0x00000000 -#define M_CompareRFields 0x00000000 +#define M_Compare0Fields 0x00000000 +#define M_CompareRFields 0x00000000 /* @@ -953,86 +953,86 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_Status $12 -#define R_C0_Status 12 -#define C0_SR C0_Status /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define S_StatusCU 28 /* Coprocessor enable (R/W) */ -#define M_StatusCU (0xf << S_StatusCU) -#define S_StatusCU3 31 -#define M_StatusCU3 (0x1 << S_StatusCU3) -#define S_StatusCU2 30 -#define M_StatusCU2 (0x1 << S_StatusCU2) -#define S_StatusCU1 29 -#define M_StatusCU1 (0x1 << S_StatusCU1) -#define S_StatusCU0 28 -#define M_StatusCU0 (0x1 << S_StatusCU0) -#define S_StatusRP 27 /* Enable reduced power mode (R/W) */ -#define M_StatusRP (0x1 << S_StatusRP) -#define S_StatusFR 26 /* Enable 64-bit FPRs (MIPS64 only) (R/W) */ -#define M_StatusFR (0x1 << S_StatusFR) -#define S_StatusRE 25 /* Enable reverse endian (R/W) */ -#define M_StatusRE (0x1 << S_StatusRE) -#define S_StatusMX 24 /* Enable access to MDMX resources (MIPS64 only) (R/W) */ -#define M_StatusMX (0x1 << S_StatusMX) -#define S_StatusPX 23 /* Enable access to 64-bit instructions/data (MIPS64 only) (R/W) */ -#define M_StatusPX (0x1 << S_StatusPX) -#define S_StatusBEV 22 /* Enable Boot Exception Vectors (R/W) */ -#define M_StatusBEV (0x1 << S_StatusBEV) -#define S_StatusTS 21 /* Denote TLB shutdown (R/W) */ -#define M_StatusTS (0x1 << S_StatusTS) -#define S_StatusSR 20 /* Denote soft reset (R/W) */ -#define M_StatusSR (0x1 << S_StatusSR) -#define S_StatusNMI 19 -#define M_StatusNMI (0x1 << S_StatusNMI) /* Denote NMI (R/W) */ -#define S_StatusIM 8 /* Interrupt mask (R/W) */ -#define M_StatusIM (0xff << S_StatusIM) -#define S_StatusIM7 15 -#define M_StatusIM7 (0x1 << S_StatusIM7) -#define S_StatusIM6 14 -#define M_StatusIM6 (0x1 << S_StatusIM6) -#define S_StatusIM5 13 -#define M_StatusIM5 (0x1 << S_StatusIM5) -#define S_StatusIM4 12 -#define M_StatusIM4 (0x1 << S_StatusIM4) -#define S_StatusIM3 11 -#define M_StatusIM3 (0x1 << S_StatusIM3) -#define S_StatusIM2 10 -#define M_StatusIM2 (0x1 << S_StatusIM2) -#define S_StatusIM1 9 -#define M_StatusIM1 (0x1 << S_StatusIM1) -#define S_StatusIM0 8 -#define M_StatusIM0 (0x1 << S_StatusIM0) -#define S_StatusKX 7 /* Enable access to extended kernel addresses (MIPS64 only) (R/W) */ -#define M_StatusKX (0x1 << S_StatusKX) -#define S_StatusSX 6 /* Enable access to extended supervisor addresses (MIPS64 only) (R/W) */ -#define M_StatusSX (0x1 << S_StatusSX) -#define S_StatusUX 5 /* Enable access to extended user addresses (MIPS64 only) (R/W) */ -#define M_StatusUX (0x1 << S_StatusUX) -#define S_StatusKSU 3 /* Two-bit current mode (R/W) */ -#define M_StatusKSU (0x3 << S_StatusKSU) -#define S_StatusUM 4 /* User mode if supervisor mode not implemented (R/W) */ -#define M_StatusUM (0x1 << S_StatusUM) -#define S_StatusSM 3 /* Supervisor mode (R/W) */ -#define M_StatusSM (0x1 << S_StatusSM) -#define S_StatusERL 2 /* Denotes error level (R/W) */ -#define M_StatusERL (0x1 << S_StatusERL) -#define S_StatusEXL 1 /* Denotes exception level (R/W) */ -#define M_StatusEXL (0x1 << S_StatusEXL) -#define S_StatusIE 0 /* Enables interrupts (R/W) */ -#define M_StatusIE (0x1 << S_StatusIE) - -#define M_Status0Fields 0x00040000 -#define M_StatusRFields 0x058000e0 /* FR, MX, PX, KX, SX, UX unused in MIPS32 */ -#define M_Status0Fields64 0x00040000 -#define M_StatusRFields64 0x00000000 +#define C0_Status $12 +#define R_C0_Status 12 +#define C0_SR C0_Status /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define S_StatusCU 28 /* Coprocessor enable (R/W) */ +#define M_StatusCU (0xf << S_StatusCU) +#define S_StatusCU3 31 +#define M_StatusCU3 (0x1 << S_StatusCU3) +#define S_StatusCU2 30 +#define M_StatusCU2 (0x1 << S_StatusCU2) +#define S_StatusCU1 29 +#define M_StatusCU1 (0x1 << S_StatusCU1) +#define S_StatusCU0 28 +#define M_StatusCU0 (0x1 << S_StatusCU0) +#define S_StatusRP 27 /* Enable reduced power mode (R/W) */ +#define M_StatusRP (0x1 << S_StatusRP) +#define S_StatusFR 26 /* Enable 64-bit FPRs (MIPS64 only) (R/W) */ +#define M_StatusFR (0x1 << S_StatusFR) +#define S_StatusRE 25 /* Enable reverse endian (R/W) */ +#define M_StatusRE (0x1 << S_StatusRE) +#define S_StatusMX 24 /* Enable access to MDMX resources (MIPS64 only) (R/W) */ +#define M_StatusMX (0x1 << S_StatusMX) +#define S_StatusPX 23 /* Enable access to 64-bit instructions/data (MIPS64 only) (R/W) */ +#define M_StatusPX (0x1 << S_StatusPX) +#define S_StatusBEV 22 /* Enable Boot Exception Vectors (R/W) */ +#define M_StatusBEV (0x1 << S_StatusBEV) +#define S_StatusTS 21 /* Denote TLB shutdown (R/W) */ +#define M_StatusTS (0x1 << S_StatusTS) +#define S_StatusSR 20 /* Denote soft reset (R/W) */ +#define M_StatusSR (0x1 << S_StatusSR) +#define S_StatusNMI 19 +#define M_StatusNMI (0x1 << S_StatusNMI) /* Denote NMI (R/W) */ +#define S_StatusIM 8 /* Interrupt mask (R/W) */ +#define M_StatusIM (0xff << S_StatusIM) +#define S_StatusIM7 15 +#define M_StatusIM7 (0x1 << S_StatusIM7) +#define S_StatusIM6 14 +#define M_StatusIM6 (0x1 << S_StatusIM6) +#define S_StatusIM5 13 +#define M_StatusIM5 (0x1 << S_StatusIM5) +#define S_StatusIM4 12 +#define M_StatusIM4 (0x1 << S_StatusIM4) +#define S_StatusIM3 11 +#define M_StatusIM3 (0x1 << S_StatusIM3) +#define S_StatusIM2 10 +#define M_StatusIM2 (0x1 << S_StatusIM2) +#define S_StatusIM1 9 +#define M_StatusIM1 (0x1 << S_StatusIM1) +#define S_StatusIM0 8 +#define M_StatusIM0 (0x1 << S_StatusIM0) +#define S_StatusKX 7 /* Enable access to extended kernel addresses (MIPS64 only) (R/W) */ +#define M_StatusKX (0x1 << S_StatusKX) +#define S_StatusSX 6 /* Enable access to extended supervisor addresses (MIPS64 only) (R/W) */ +#define M_StatusSX (0x1 << S_StatusSX) +#define S_StatusUX 5 /* Enable access to extended user addresses (MIPS64 only) (R/W) */ +#define M_StatusUX (0x1 << S_StatusUX) +#define S_StatusKSU 3 /* Two-bit current mode (R/W) */ +#define M_StatusKSU (0x3 << S_StatusKSU) +#define S_StatusUM 4 /* User mode if supervisor mode not implemented (R/W) */ +#define M_StatusUM (0x1 << S_StatusUM) +#define S_StatusSM 3 /* Supervisor mode (R/W) */ +#define M_StatusSM (0x1 << S_StatusSM) +#define S_StatusERL 2 /* Denotes error level (R/W) */ +#define M_StatusERL (0x1 << S_StatusERL) +#define S_StatusEXL 1 /* Denotes exception level (R/W) */ +#define M_StatusEXL (0x1 << S_StatusEXL) +#define S_StatusIE 0 /* Enables interrupts (R/W) */ +#define M_StatusIE (0x1 << S_StatusIE) + +#define M_Status0Fields 0x00040000 +#define M_StatusRFields 0x058000e0 /* FR, MX, PX, KX, SX, UX unused in MIPS32 */ +#define M_Status0Fields64 0x00040000 +#define M_StatusRFields64 0x00000000 /* * Values in the KSU field */ -#define K_StatusKSU_U 2 /* User mode in KSU field */ -#define K_StatusKSU_S 1 /* Supervisor mode in KSU field */ -#define K_StatusKSU_K 0 /* Kernel mode in KSU field */ +#define K_StatusKSU_U 2 /* User mode in KSU field */ +#define K_StatusKSU_S 1 /* Supervisor mode in KSU field */ +#define K_StatusKSU_K 0 /* Kernel mode in KSU field */ /* @@ -1049,101 +1049,101 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_Cause $13 -#define R_C0_Cause 13 -#define C0_CAUSE C0_Cause /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define S_CauseBD 31 -#define M_CauseBD (0x1 << S_CauseBD) -#define S_CauseCE 28 -#define M_CauseCE (0x3<< S_CauseCE) -#define S_CauseIV 23 -#define M_CauseIV (0x1 << S_CauseIV) -#define S_CauseWP 22 -#define M_CauseWP (0x1 << S_CauseWP) -#define S_CauseIP 8 -#define M_CauseIP (0xff << S_CauseIP) -#define S_CauseIPEXT 10 -#define M_CauseIPEXT (0x3f << S_CauseIPEXT) -#define S_CauseIP7 15 -#define M_CauseIP7 (0x1 << S_CauseIP7) -#define S_CauseIP6 14 -#define M_CauseIP6 (0x1 << S_CauseIP6) -#define S_CauseIP5 13 -#define M_CauseIP5 (0x1 << S_CauseIP5) -#define S_CauseIP4 12 -#define M_CauseIP4 (0x1 << S_CauseIP4) -#define S_CauseIP3 11 -#define M_CauseIP3 (0x1 << S_CauseIP3) -#define S_CauseIP2 10 -#define M_CauseIP2 (0x1 << S_CauseIP2) -#define S_CauseIP1 9 -#define M_CauseIP1 (0x1 << S_CauseIP1) -#define S_CauseIP0 8 -#define M_CauseIP0 (0x1 << S_CauseIP0) -#define S_CauseExcCode 2 -#define M_CauseExcCode (0x1f << S_CauseExcCode) - -#define M_Cause0Fields 0x4f3f0083 -#define M_CauseRFields 0xb000fc7c +#define C0_Cause $13 +#define R_C0_Cause 13 +#define C0_CAUSE C0_Cause /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define S_CauseBD 31 +#define M_CauseBD (0x1 << S_CauseBD) +#define S_CauseCE 28 +#define M_CauseCE (0x3<< S_CauseCE) +#define S_CauseIV 23 +#define M_CauseIV (0x1 << S_CauseIV) +#define S_CauseWP 22 +#define M_CauseWP (0x1 << S_CauseWP) +#define S_CauseIP 8 +#define M_CauseIP (0xff << S_CauseIP) +#define S_CauseIPEXT 10 +#define M_CauseIPEXT (0x3f << S_CauseIPEXT) +#define S_CauseIP7 15 +#define M_CauseIP7 (0x1 << S_CauseIP7) +#define S_CauseIP6 14 +#define M_CauseIP6 (0x1 << S_CauseIP6) +#define S_CauseIP5 13 +#define M_CauseIP5 (0x1 << S_CauseIP5) +#define S_CauseIP4 12 +#define M_CauseIP4 (0x1 << S_CauseIP4) +#define S_CauseIP3 11 +#define M_CauseIP3 (0x1 << S_CauseIP3) +#define S_CauseIP2 10 +#define M_CauseIP2 (0x1 << S_CauseIP2) +#define S_CauseIP1 9 +#define M_CauseIP1 (0x1 << S_CauseIP1) +#define S_CauseIP0 8 +#define M_CauseIP0 (0x1 << S_CauseIP0) +#define S_CauseExcCode 2 +#define M_CauseExcCode (0x1f << S_CauseExcCode) + +#define M_Cause0Fields 0x4f3f0083 +#define M_CauseRFields 0xb000fc7c /* * Values in the CE field */ -#define K_CauseCE0 0 /* Coprocessor 0 in the CE field */ -#define K_CauseCE1 1 /* Coprocessor 1 in the CE field */ -#define K_CauseCE2 2 /* Coprocessor 2 in the CE field */ -#define K_CauseCE3 3 /* Coprocessor 3 in the CE field */ +#define K_CauseCE0 0 /* Coprocessor 0 in the CE field */ +#define K_CauseCE1 1 /* Coprocessor 1 in the CE field */ +#define K_CauseCE2 2 /* Coprocessor 2 in the CE field */ +#define K_CauseCE3 3 /* Coprocessor 3 in the CE field */ /* * Values in the ExcCode field */ -#define EX_INT 0 /* Interrupt */ -#define EXC_INT (EX_INT << S_CauseExcCode) -#define EX_MOD 1 /* TLB modified */ -#define EXC_MOD (EX_MOD << S_CauseExcCode) -#define EX_TLBL 2 /* TLB exception (load or ifetch) */ -#define EXC_TLBL (EX_TLBL << S_CauseExcCode) -#define EX_TLBS 3 /* TLB exception (store) */ -#define EXC_TLBS (EX_TLBS << S_CauseExcCode) -#define EX_ADEL 4 /* Address error (load or ifetch) */ -#define EXC_ADEL (EX_ADEL << S_CauseExcCode) -#define EX_ADES 5 /* Address error (store) */ -#define EXC_ADES (EX_ADES << S_CauseExcCode) -#define EX_IBE 6 /* Instruction Bus Error */ -#define EXC_IBE (EX_IBE << S_CauseExcCode) -#define EX_DBE 7 /* Data Bus Error */ -#define EXC_DBE (EX_DBE << S_CauseExcCode) -#define EX_SYS 8 /* Syscall */ -#define EXC_SYS (EX_SYS << S_CauseExcCode) -#define EX_SYSCALL EX_SYS -#define EXC_SYSCALL EXC_SYS -#define EX_BP 9 /* Breakpoint */ -#define EXC_BP (EX_BP << S_CauseExcCode) -#define EX_BREAK EX_BP -#define EXC_BREAK EXC_BP -#define EX_RI 10 /* Reserved instruction */ -#define EXC_RI (EX_RI << S_CauseExcCode) -#define EX_CPU 11 /* CoProcessor Unusable */ -#define EXC_CPU (EX_CPU << S_CauseExcCode) -#define EX_OV 12 /* OVerflow */ -#define EXC_OV (EX_OV << S_CauseExcCode) -#define EX_TR 13 /* Trap instruction */ -#define EXC_TR (EX_TR << S_CauseExcCode) -#define EX_TRAP EX_TR -#define EXC_TRAP EXC_TR -#define EX_FPE 15 /* floating point exception */ -#define EXC_FPE (EX_FPE << S_CauseExcCode) -#define EX_C2E 18 /* COP2 exception */ -#define EXC_C2E (EX_C2E << S_CauseExcCode) -#define EX_MDMX 22 /* MDMX exception */ -#define EXC_MDMX (EX_MDMX << S_CauseExcCode) -#define EX_WATCH 23 /* Watch exception */ -#define EXC_WATCH (EX_WATCH << S_CauseExcCode) -#define EX_MCHECK 24 /* Machine check exception */ -#define EXC_MCHECK (EX_MCHECK << S_CauseExcCode) -#define EX_CacheErr 30 /* Cache error caused re-entry to Debug Mode */ -#define EXC_CacheErr (EX_CacheErr << S_CauseExcCode) +#define EX_INT 0 /* Interrupt */ +#define EXC_INT (EX_INT << S_CauseExcCode) +#define EX_MOD 1 /* TLB modified */ +#define EXC_MOD (EX_MOD << S_CauseExcCode) +#define EX_TLBL 2 /* TLB exception (load or ifetch) */ +#define EXC_TLBL (EX_TLBL << S_CauseExcCode) +#define EX_TLBS 3 /* TLB exception (store) */ +#define EXC_TLBS (EX_TLBS << S_CauseExcCode) +#define EX_ADEL 4 /* Address error (load or ifetch) */ +#define EXC_ADEL (EX_ADEL << S_CauseExcCode) +#define EX_ADES 5 /* Address error (store) */ +#define EXC_ADES (EX_ADES << S_CauseExcCode) +#define EX_IBE 6 /* Instruction Bus Error */ +#define EXC_IBE (EX_IBE << S_CauseExcCode) +#define EX_DBE 7 /* Data Bus Error */ +#define EXC_DBE (EX_DBE << S_CauseExcCode) +#define EX_SYS 8 /* Syscall */ +#define EXC_SYS (EX_SYS << S_CauseExcCode) +#define EX_SYSCALL EX_SYS +#define EXC_SYSCALL EXC_SYS +#define EX_BP 9 /* Breakpoint */ +#define EXC_BP (EX_BP << S_CauseExcCode) +#define EX_BREAK EX_BP +#define EXC_BREAK EXC_BP +#define EX_RI 10 /* Reserved instruction */ +#define EXC_RI (EX_RI << S_CauseExcCode) +#define EX_CPU 11 /* CoProcessor Unusable */ +#define EXC_CPU (EX_CPU << S_CauseExcCode) +#define EX_OV 12 /* OVerflow */ +#define EXC_OV (EX_OV << S_CauseExcCode) +#define EX_TR 13 /* Trap instruction */ +#define EXC_TR (EX_TR << S_CauseExcCode) +#define EX_TRAP EX_TR +#define EXC_TRAP EXC_TR +#define EX_FPE 15 /* floating point exception */ +#define EXC_FPE (EX_FPE << S_CauseExcCode) +#define EX_C2E 18 /* COP2 exception */ +#define EXC_C2E (EX_C2E << S_CauseExcCode) +#define EX_MDMX 22 /* MDMX exception */ +#define EXC_MDMX (EX_MDMX << S_CauseExcCode) +#define EX_WATCH 23 /* Watch exception */ +#define EXC_WATCH (EX_WATCH << S_CauseExcCode) +#define EX_MCHECK 24 /* Machine check exception */ +#define EXC_MCHECK (EX_MCHECK << S_CauseExcCode) +#define EX_CacheErr 30 /* Cache error caused re-entry to Debug Mode */ +#define EXC_CacheErr (EX_CacheErr << S_CauseExcCode) /* @@ -1158,13 +1158,13 @@ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_EPC $14 -#define R_C0_EPC 14 +#define C0_EPC $14 +#define R_C0_EPC 14 -#define M_EPC0Fields 0x00000000 -#define M_EPCRFields 0x00000000 -#define M_EPC0Fields64 UNS64Const(0x0000000000000000) -#define M_EPCRFields64 UNS64Const(0x0000000000000000) +#define M_EPC0Fields 0x00000000 +#define M_EPCRFields 0x00000000 +#define M_EPC0Fields64 UNS64Const(0x0000000000000000) +#define M_EPCRFields64 UNS64Const(0x0000000000000000) /* ************************************************************************ @@ -1178,25 +1178,25 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_PRId $15 -#define R_C0_PRId 15 -#define C0_PRID C0_PRID /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_PRId $15 +#define R_C0_PRId 15 +#define C0_PRID C0_PRID /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define S_PRIdCoOpt 24 /* Company options (R) */ -#define M_PRIdCoOpt (0xff << S_PRIdCoOpt) -#define S_PRIdCoID 16 /* Company ID (R) */ -#define M_PRIdCoID (0xff << S_PRIdCoID) -#define S_PRIdImp 8 /* Implementation ID (R) */ -#define M_PRIdImp (0xff << S_PRIdImp) -#define S_PRIdRev 0 /* Revision (R) */ -#define M_PRIdRev (0xff << S_PRIdRev) +#define S_PRIdCoOpt 24 /* Company options (R) */ +#define M_PRIdCoOpt (0xff << S_PRIdCoOpt) +#define S_PRIdCoID 16 /* Company ID (R) */ +#define M_PRIdCoID (0xff << S_PRIdCoID) +#define S_PRIdImp 8 /* Implementation ID (R) */ +#define M_PRIdImp (0xff << S_PRIdImp) +#define S_PRIdRev 0 /* Revision (R) */ +#define M_PRIdRev (0xff << S_PRIdRev) -#define M_PRId0Fields 0x00000000 -#define M_PRIdRFields 0xffffffff +#define M_PRId0Fields 0x00000000 +#define M_PRIdRFields 0xffffffff /* * Values in the Company ID field */ -#define K_PRIdCoID_MIPS 1 +#define K_PRIdCoID_MIPS 1 #define K_PRIdCoID_Broadcom 2 #define K_PRIdCoID_Alchemy 3 #define K_PRIdCoID_SiByte 4 @@ -1208,21 +1208,21 @@ /* * Values in the implementation number field */ -#define K_PRIdImp_Jade 0x80 -#define K_PRIdImp_Opal 0x81 -#define K_PRIdImp_Ruby 0x82 -#define K_PRIdImp_JadeLite 0x83 +#define K_PRIdImp_Jade 0x80 +#define K_PRIdImp_Opal 0x81 +#define K_PRIdImp_Ruby 0x82 +#define K_PRIdImp_JadeLite 0x83 #define K_PRIdImp_4KEc 0x84 /* Emerald with TLB MMU */ #define K_PRIdImp_4KEmp 0x85 /* Emerald with FM MMU */ #define K_PRIdImp_4KSc 0x86 /* Coral */ -#define K_PRIdImp_R3000 0x01 -#define K_PRIdImp_R4000 0x04 -#define K_PRIdImp_R10000 0x09 -#define K_PRIdImp_R4300 0x0b -#define K_PRIdImp_R5000 0x23 -#define K_PRIdImp_R5200 0x28 -#define K_PRIdImp_R5400 0x54 +#define K_PRIdImp_R3000 0x01 +#define K_PRIdImp_R4000 0x04 +#define K_PRIdImp_R10000 0x09 +#define K_PRIdImp_R4300 0x0b +#define K_PRIdImp_R5000 0x23 +#define K_PRIdImp_R5200 0x28 +#define K_PRIdImp_R5400 0x54 /* ************************************************************************ @@ -1237,24 +1237,24 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_Config $16 -#define R_C0_Config 16 -#define C0_CONFIG C0_Config /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_Config $16 +#define R_C0_Config 16 +#define C0_CONFIG C0_Config /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define S_ConfigMore 31 /* Additional config registers present (R) */ -#define M_ConfigMore (0x1 << S_ConfigMore) -#define S_ConfigImpl 16 /* Implementation-specific fields */ -#define M_ConfigImpl (0x7fff << S_ConfigImpl) -#define S_ConfigBE 15 /* Denotes big-endian operation (R) */ -#define M_ConfigBE (0x1 << S_ConfigBE) -#define S_ConfigAT 13 /* Architecture type (R) */ -#define M_ConfigAT (0x3 << S_ConfigAT) -#define S_ConfigAR 10 /* Architecture revision (R) */ -#define M_ConfigAR (0x7 << S_ConfigAR) -#define S_ConfigMT 7 /* MMU Type (R) */ -#define M_ConfigMT (0x7 << S_ConfigMT) -#define S_ConfigK0 0 /* Kseg0 coherency algorithm (R/W) */ -#define M_ConfigK0 (0x7 << S_ConfigK0) +#define S_ConfigMore 31 /* Additional config registers present (R) */ +#define M_ConfigMore (0x1 << S_ConfigMore) +#define S_ConfigImpl 16 /* Implementation-specific fields */ +#define M_ConfigImpl (0x7fff << S_ConfigImpl) +#define S_ConfigBE 15 /* Denotes big-endian operation (R) */ +#define M_ConfigBE (0x1 << S_ConfigBE) +#define S_ConfigAT 13 /* Architecture type (R) */ +#define M_ConfigAT (0x3 << S_ConfigAT) +#define S_ConfigAR 10 /* Architecture revision (R) */ +#define M_ConfigAR (0x7 << S_ConfigAR) +#define S_ConfigMT 7 /* MMU Type (R) */ +#define M_ConfigMT (0x7 << S_ConfigMT) +#define S_ConfigK0 0 /* Kseg0 coherency algorithm (R/W) */ +#define M_ConfigK0 (0x7 << S_ConfigK0) /* * The following definitions are technically part of the "reserved for @@ -1263,28 +1263,28 @@ * references. For that reason, they are included here, but may be * overridden by true implementation-specific definitions */ -#define S_ConfigK23 28 /* Kseg2/3 coherency algorithm (FM MMU only) (R/W) */ -#define M_ConfigK23 (0x7 << S_ConfigK23) -#define S_ConfigKU 25 /* Kuseg coherency algorithm (FM MMU only) (R/W) */ -#define M_ConfigKU (0x7 << S_ConfigKU) +#define S_ConfigK23 28 /* Kseg2/3 coherency algorithm (FM MMU only) (R/W) */ +#define M_ConfigK23 (0x7 << S_ConfigK23) +#define S_ConfigKU 25 /* Kuseg coherency algorithm (FM MMU only) (R/W) */ +#define M_ConfigKU (0x7 << S_ConfigKU) -#define M_Config0Fields 0x00000078 -#define M_ConfigRFields 0x8000ff80 +#define M_Config0Fields 0x00000078 +#define M_ConfigRFields 0x8000ff80 /* * Values in the AT field */ -#define K_ConfigAT_MIPS32 0 /* MIPS32 */ -#define K_ConfigAT_MIPS64S 1 /* MIPS64 with 32-bit addresses */ -#define K_ConfigAT_MIPS64 2 /* MIPS64 with 32/64-bit addresses */ +#define K_ConfigAT_MIPS32 0 /* MIPS32 */ +#define K_ConfigAT_MIPS64S 1 /* MIPS64 with 32-bit addresses */ +#define K_ConfigAT_MIPS64 2 /* MIPS64 with 32/64-bit addresses */ /* * Values in the MT field */ -#define K_ConfigMT_NoMMU 0 /* No MMU */ -#define K_ConfigMT_TLBMMU 1 /* Standard TLB MMU */ -#define K_ConfigMT_BATMMU 2 /* Standard BAT MMU */ -#define K_ConfigMT_FMMMU 3 /* Standard Fixed Mapping MMU */ +#define K_ConfigMT_NoMMU 0 /* No MMU */ +#define K_ConfigMT_TLBMMU 1 /* Standard TLB MMU */ +#define K_ConfigMT_BATMMU 2 /* Standard BAT MMU */ +#define K_ConfigMT_FMMMU 3 /* Standard Fixed Mapping MMU */ /* @@ -1300,72 +1300,72 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_Config1 $16,1 -#define R_C0_Config1 16 - -#define S_Config1More 31 /* Additional Config registers present (R) */ -#define M_Config1More (0x1 << S_Config1More) -#define S_Config1MMUSize 25 /* Number of MMU entries - 1 (R) */ -#define M_Config1MMUSize (0x3f << S_Config1MMUSize) -#define S_Config1IS 22 /* Icache sets per way (R) */ -#define M_Config1IS (0x7 << S_Config1IS) -#define S_Config1IL 19 /* Icache line size (R) */ -#define M_Config1IL (0x7 << S_Config1IL) -#define S_Config1IA 16 /* Icache associativity - 1 (R) */ -#define M_Config1IA (0x7 << S_Config1IA) -#define S_Config1DS 13 /* Dcache sets per way (R) */ -#define M_Config1DS (0x7 << S_Config1DS) -#define S_Config1DL 10 /* Dcache line size (R) */ -#define M_Config1DL (0x7 << S_Config1DL) -#define S_Config1DA 7 /* Dcache associativity (R) */ -#define M_Config1DA (0x7 << S_Config1DA) -#define S_Config1C2 6 /* Coprocessor 2 present (R) */ -#define M_Config1C2 (0x1 << S_Config1C2) -#define S_Config1MD 5 /* Denotes MDMX present (R) */ -#define M_Config1MD (0x1 << S_Config1MD) -#define S_Config1PC 4 /* Denotes performance counters present (R) */ -#define M_Config1PC (0x1 << S_Config1PC) -#define S_Config1WR 3 /* Denotes watch registers present (R) */ -#define M_Config1WR (0x1 << S_Config1WR) -#define S_Config1CA 2 /* Denotes MIPS-16 present (R) */ -#define M_Config1CA (0x1 << S_Config1CA) -#define S_Config1EP 1 /* Denotes EJTAG present (R) */ -#define M_Config1EP (0x1 << S_Config1EP) -#define S_Config1FP 0 /* Denotes floating point present (R) */ -#define M_Config1FP (0x1 << S_Config1FP) - -#define M_Config10Fields 0x00000060 -#define M_Config1RFields 0x7fffff9f +#define C0_Config1 $16,1 +#define R_C0_Config1 16 + +#define S_Config1More 31 /* Additional Config registers present (R) */ +#define M_Config1More (0x1 << S_Config1More) +#define S_Config1MMUSize 25 /* Number of MMU entries - 1 (R) */ +#define M_Config1MMUSize (0x3f << S_Config1MMUSize) +#define S_Config1IS 22 /* Icache sets per way (R) */ +#define M_Config1IS (0x7 << S_Config1IS) +#define S_Config1IL 19 /* Icache line size (R) */ +#define M_Config1IL (0x7 << S_Config1IL) +#define S_Config1IA 16 /* Icache associativity - 1 (R) */ +#define M_Config1IA (0x7 << S_Config1IA) +#define S_Config1DS 13 /* Dcache sets per way (R) */ +#define M_Config1DS (0x7 << S_Config1DS) +#define S_Config1DL 10 /* Dcache line size (R) */ +#define M_Config1DL (0x7 << S_Config1DL) +#define S_Config1DA 7 /* Dcache associativity (R) */ +#define M_Config1DA (0x7 << S_Config1DA) +#define S_Config1C2 6 /* Coprocessor 2 present (R) */ +#define M_Config1C2 (0x1 << S_Config1C2) +#define S_Config1MD 5 /* Denotes MDMX present (R) */ +#define M_Config1MD (0x1 << S_Config1MD) +#define S_Config1PC 4 /* Denotes performance counters present (R) */ +#define M_Config1PC (0x1 << S_Config1PC) +#define S_Config1WR 3 /* Denotes watch registers present (R) */ +#define M_Config1WR (0x1 << S_Config1WR) +#define S_Config1CA 2 /* Denotes MIPS-16 present (R) */ +#define M_Config1CA (0x1 << S_Config1CA) +#define S_Config1EP 1 /* Denotes EJTAG present (R) */ +#define M_Config1EP (0x1 << S_Config1EP) +#define S_Config1FP 0 /* Denotes floating point present (R) */ +#define M_Config1FP (0x1 << S_Config1FP) + +#define M_Config10Fields 0x00000060 +#define M_Config1RFields 0x7fffff9f /* * The following macro generates a table that is indexed * by the Icache or Dcache sets field in Config1 and * contains the decoded value of sets per way */ -#define Config1CacheSets() \ - HALF(64); \ - HALF(128); \ - HALF(256); \ - HALF(512); \ - HALF(1024); \ - HALF(2048); \ - HALF(4096); \ - HALF(8192); +#define Config1CacheSets() \ + HALF(64); \ + HALF(128); \ + HALF(256); \ + HALF(512); \ + HALF(1024); \ + HALF(2048); \ + HALF(4096); \ + HALF(8192); /* * The following macro generates a table that is indexed * by the Icache or Dcache line size field in Config1 and * contains the decoded value of the cache line size, in bytes */ -#define Config1CacheLineSize() \ - HALF(0); \ - HALF(4); \ - HALF(8); \ - HALF(16); \ - HALF(32); \ - HALF(64); \ - HALF(128); \ - HALF(256); +#define Config1CacheLineSize() \ + HALF(0); \ + HALF(4); \ + HALF(8); \ + HALF(16); \ + HALF(32); \ + HALF(64); \ + HALF(128); \ + HALF(256); /* @@ -1381,18 +1381,18 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_Config2 $16,2 -#define R_C0_Config2 16 +#define C0_Config2 $16,2 +#define R_C0_Config2 16 -#define S_Config2More 31 /* Additional Config registers present (R) */ -#define M_Config2More (0x1 << S_Config2More) -#define S_Config2SM 1 /* Denotes SmartMIPS ASE present (R) */ -#define M_Config2SM (0x1 << S_Config2SM) -#define S_Config2TL 0 /* Denotes Tracing Logic present (R) */ -#define M_Config2TL (0x1 << S_Config2TL) +#define S_Config2More 31 /* Additional Config registers present (R) */ +#define M_Config2More (0x1 << S_Config2More) +#define S_Config2SM 1 /* Denotes SmartMIPS ASE present (R) */ +#define M_Config2SM (0x1 << S_Config2SM) +#define S_Config2TL 0 /* Denotes Tracing Logic present (R) */ +#define M_Config2TL (0x1 << S_Config2TL) -#define M_Config20Fields 0xfffffffc -#define M_Config2RFields 0x00000003 +#define M_Config20Fields 0xfffffffc +#define M_Config2RFields 0x00000003 /* ************************************************************************ @@ -1406,14 +1406,14 @@ * +-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_LLAddr $17 -#define R_C0_LLAddr 17 -#define C0_LLADDR C0_LLAddr /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_LLAddr $17 +#define R_C0_LLAddr 17 +#define C0_LLADDR C0_LLAddr /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define M_LLAddr0Fields 0x00000000 -#define M_LLAddrRFields 0x00000000 -#define M_LLAddr0Fields64 UNS64Const(0x0000000000000000) -#define M_LLAddrRFields64 UNS64Const(0x0000000000000000) +#define M_LLAddr0Fields 0x00000000 +#define M_LLAddrRFields 0x00000000 +#define M_LLAddr0Fields64 UNS64Const(0x0000000000000000) +#define M_LLAddrRFields64 UNS64Const(0x0000000000000000) /* @@ -1428,25 +1428,25 @@ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_WatchLo $18 -#define R_C0_WatchLo 18 -#define C0_WATCHLO C0_WatchLo /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_WatchLo $18 +#define R_C0_WatchLo 18 +#define C0_WATCHLO C0_WatchLo /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define S_WatchLoVAddr 3 /* Watch virtual address (R/W) */ -#define M_WatchLoVAddr (0x1fffffff << S_WatchLoVAddr) -#define S_WatchLoI 2 /* Enable Istream watch (R/W) */ -#define M_WatchLoI (0x1 << S_WatchLoI) -#define S_WatchLoR 1 /* Enable data read watch (R/W) */ -#define M_WatchLoR (0x1 << S_WatchLoR) -#define S_WatchLoW 0 /* Enable data write watch (R/W) */ -#define M_WatchLoW (0x1 << S_WatchLoW) +#define S_WatchLoVAddr 3 /* Watch virtual address (R/W) */ +#define M_WatchLoVAddr (0x1fffffff << S_WatchLoVAddr) +#define S_WatchLoI 2 /* Enable Istream watch (R/W) */ +#define M_WatchLoI (0x1 << S_WatchLoI) +#define S_WatchLoR 1 /* Enable data read watch (R/W) */ +#define M_WatchLoR (0x1 << S_WatchLoR) +#define S_WatchLoW 0 /* Enable data write watch (R/W) */ +#define M_WatchLoW (0x1 << S_WatchLoW) -#define M_WatchLo0Fields 0x00000000 -#define M_WatchLoRFields 0x00000000 -#define M_WatchLo0Fields64 UNS64Const(0x0000000000000000) -#define M_WatchLoRFields64 UNS64Const(0x0000000000000000) +#define M_WatchLo0Fields 0x00000000 +#define M_WatchLoRFields 0x00000000 +#define M_WatchLo0Fields64 UNS64Const(0x0000000000000000) +#define M_WatchLoRFields64 UNS64Const(0x0000000000000000) -#define M_WatchLoEnables (M_WatchLoI | M_WatchLoR | M_WatchLoW) +#define M_WatchLoEnables (M_WatchLoI | M_WatchLoR | M_WatchLoW) /* @@ -1461,21 +1461,21 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_WatchHi $19 -#define R_C0_WatchHi 19 -#define C0_WATCHHI C0_WatchHi /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_WatchHi $19 +#define R_C0_WatchHi 19 +#define C0_WATCHHI C0_WatchHi /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define S_WatchHiM 31 /* Denotes additional Watch registers present (R) */ -#define M_WatchHiM (0x1 << S_WatchHiM) -#define S_WatchHiG 30 /* Enable ASID-independent Watch match (R/W) */ -#define M_WatchHiG (0x1 << S_WatchHiG) -#define S_WatchHiASID 16 /* ASID value to match (R/W) */ -#define M_WatchHiASID (0xff << S_WatchHiASID) -#define S_WatchHiMask 3 /* Address inhibit mask (R/W) */ -#define M_WatchHiMask (0x1ff << S_WatchHiMask) +#define S_WatchHiM 31 /* Denotes additional Watch registers present (R) */ +#define M_WatchHiM (0x1 << S_WatchHiM) +#define S_WatchHiG 30 /* Enable ASID-independent Watch match (R/W) */ +#define M_WatchHiG (0x1 << S_WatchHiG) +#define S_WatchHiASID 16 /* ASID value to match (R/W) */ +#define M_WatchHiASID (0xff << S_WatchHiASID) +#define S_WatchHiMask 3 /* Address inhibit mask (R/W) */ +#define M_WatchHiMask (0x1ff << S_WatchHiMask) -#define M_WatchHi0Fields 0x3f00f007 -#define M_WatchHiRFields 0x80000000 +#define M_WatchHi0Fields 0x3f00f007 +#define M_WatchHiRFields 0x80000000 /* @@ -1490,14 +1490,14 @@ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_XContext $20 -#define R_C0_XContext 20 -#define C0_EXTCTXT C0_XContext /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_XContext $20 +#define R_C0_XContext 20 +#define C0_EXTCTXT C0_XContext /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define S_XContextBadVPN2 4 /* BadVPN2 (R) */ -#define S_XContextBadVPN S_XContextBadVPN2 +#define S_XContextBadVPN2 4 /* BadVPN2 (R) */ +#define S_XContextBadVPN S_XContextBadVPN2 -#define M_XContext0Fields 0x0000000f +#define M_XContext0Fields 0x0000000f /* @@ -1519,60 +1519,60 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_Debug $23 /* EJTAG */ -#define R_C0_Debug 23 - -#define S_DebugDBD 31 /* Debug branch delay (R) */ -#define M_DebugDBD (0x1 << S_DebugDBD) -#define S_DebugDM 30 /* Debug mode (R) */ -#define M_DebugDM (0x1 << S_DebugDM) -#define S_DebugNoDCR 29 /* No debug control register present (R) */ -#define M_DebugNoDCR (0x1 << S_DebugNoDCR) -#define S_DebugLSNM 28 /* Load/Store Normal Memory (R/W) */ -#define M_DebugLSNM (0x1 << S_DebugLSNM) -#define S_DebugDoze 27 /* Doze (R) */ -#define M_DebugDoze (0x1 << S_DebugDoze) -#define S_DebugHalt 26 /* Halt (R) */ -#define M_DebugHalt (0x1 << S_DebugHalt) -#define S_DebugCountDM 25 /* Count register behavior in debug mode (R/W) */ -#define M_DebugCountDM (0x1 << S_DebugCountDM) -#define S_DebugIBusEP 24 /* Imprecise Instn Bus Error Pending (R/W) */ -#define M_DebugIBusEP (0x1 << S_DebugIBusEP) -#define S_DebugMCheckP 23 /* Imprecise Machine Check Pending (R/W) */ -#define M_DebugMCheckP (0x1 << S_DebugMCheckP) -#define S_DebugCacheEP 22 /* Imprecise Cache Error Pending (R/W) */ -#define M_DebugCacheEP (0x1 << S_DebugCacheEP) -#define S_DebugDBusEP 21 /* Imprecise Data Bus Error Pending (R/W) */ -#define M_DebugDBusEP (0x1 << S_DebugDBusEP) -#define S_DebugIEXI 20 /* Imprecise Exception Inhibit (R/W) */ -#define M_DebugIEXI (0x1 << S_DebugIEXI) -#define S_DebugDDBSImpr 19 /* Debug data break store imprecise (R) */ -#define M_DebugDDBSImpr (0x1 << S_DebugDDBSImpr) -#define S_DebugDDBLImpr 18 /* Debug data break load imprecise (R) */ -#define M_DebugDDBLImpr (0x1 << S_DebugDDBLImpr) -#define S_DebugEJTAGver 15 /* EJTAG version number (R) */ -#define M_DebugEJTAGver (0x7 << S_DebugEJTAGver) -#define S_DebugDExcCode 10 /* Debug exception code (R) */ -#define M_DebugDExcCode (0x1f << S_DebugDExcCode) -#define S_DebugNoSSt 9 /* No single step implemented (R) */ -#define M_DebugNoSSt (0x1 << S_DebugNoSSt) -#define S_DebugSSt 8 /* Single step enable (R/W) */ -#define M_DebugSSt (0x1 << S_DebugSSt) -#define S_DebugDINT 5 /* Debug interrupt (R) */ -#define M_DebugDINT (0x1 << S_DebugDINT) -#define S_DebugDIB 4 /* Debug instruction break (R) */ -#define M_DebugDIB (0x1 << S_DebugDIB) -#define S_DebugDDBS 3 /* Debug data break store (R) */ -#define M_DebugDDBS (0x1 << S_DebugDDBS) -#define S_DebugDDBL 2 /* Debug data break load (R) */ -#define M_DebugDDBL (0x1 << S_DebugDDBL) -#define S_DebugDBp 1 /* Debug breakpoint (R) */ -#define M_DebugDBp (0x1 << S_DebugDBp) -#define S_DebugDSS 0 /* Debug single step (R) */ -#define M_DebugDSS (0x1 << S_DebugDSS) - -#define M_Debug0Fields 0x01f000c0 -#define M_DebugRFields 0xec0ffe3f +#define C0_Debug $23 /* EJTAG */ +#define R_C0_Debug 23 + +#define S_DebugDBD 31 /* Debug branch delay (R) */ +#define M_DebugDBD (0x1 << S_DebugDBD) +#define S_DebugDM 30 /* Debug mode (R) */ +#define M_DebugDM (0x1 << S_DebugDM) +#define S_DebugNoDCR 29 /* No debug control register present (R) */ +#define M_DebugNoDCR (0x1 << S_DebugNoDCR) +#define S_DebugLSNM 28 /* Load/Store Normal Memory (R/W) */ +#define M_DebugLSNM (0x1 << S_DebugLSNM) +#define S_DebugDoze 27 /* Doze (R) */ +#define M_DebugDoze (0x1 << S_DebugDoze) +#define S_DebugHalt 26 /* Halt (R) */ +#define M_DebugHalt (0x1 << S_DebugHalt) +#define S_DebugCountDM 25 /* Count register behavior in debug mode (R/W) */ +#define M_DebugCountDM (0x1 << S_DebugCountDM) +#define S_DebugIBusEP 24 /* Imprecise Instn Bus Error Pending (R/W) */ +#define M_DebugIBusEP (0x1 << S_DebugIBusEP) +#define S_DebugMCheckP 23 /* Imprecise Machine Check Pending (R/W) */ +#define M_DebugMCheckP (0x1 << S_DebugMCheckP) +#define S_DebugCacheEP 22 /* Imprecise Cache Error Pending (R/W) */ +#define M_DebugCacheEP (0x1 << S_DebugCacheEP) +#define S_DebugDBusEP 21 /* Imprecise Data Bus Error Pending (R/W) */ +#define M_DebugDBusEP (0x1 << S_DebugDBusEP) +#define S_DebugIEXI 20 /* Imprecise Exception Inhibit (R/W) */ +#define M_DebugIEXI (0x1 << S_DebugIEXI) +#define S_DebugDDBSImpr 19 /* Debug data break store imprecise (R) */ +#define M_DebugDDBSImpr (0x1 << S_DebugDDBSImpr) +#define S_DebugDDBLImpr 18 /* Debug data break load imprecise (R) */ +#define M_DebugDDBLImpr (0x1 << S_DebugDDBLImpr) +#define S_DebugEJTAGver 15 /* EJTAG version number (R) */ +#define M_DebugEJTAGver (0x7 << S_DebugEJTAGver) +#define S_DebugDExcCode 10 /* Debug exception code (R) */ +#define M_DebugDExcCode (0x1f << S_DebugDExcCode) +#define S_DebugNoSSt 9 /* No single step implemented (R) */ +#define M_DebugNoSSt (0x1 << S_DebugNoSSt) +#define S_DebugSSt 8 /* Single step enable (R/W) */ +#define M_DebugSSt (0x1 << S_DebugSSt) +#define S_DebugDINT 5 /* Debug interrupt (R) */ +#define M_DebugDINT (0x1 << S_DebugDINT) +#define S_DebugDIB 4 /* Debug instruction break (R) */ +#define M_DebugDIB (0x1 << S_DebugDIB) +#define S_DebugDDBS 3 /* Debug data break store (R) */ +#define M_DebugDDBS (0x1 << S_DebugDDBS) +#define S_DebugDDBL 2 /* Debug data break load (R) */ +#define M_DebugDDBL (0x1 << S_DebugDDBL) +#define S_DebugDBp 1 /* Debug breakpoint (R) */ +#define M_DebugDBp (0x1 << S_DebugDBp) +#define S_DebugDSS 0 /* Debug single step (R) */ +#define M_DebugDSS (0x1 << S_DebugDSS) + +#define M_Debug0Fields 0x01f000c0 +#define M_DebugRFields 0xec0ffe3f /* @@ -1588,13 +1588,13 @@ */ -#define C0_DEPC $24 -#define R_C0_DEPC 24 +#define C0_DEPC $24 +#define R_C0_DEPC 24 -#define M_DEEPC0Fields 0x00000000 -#define M_DEEPCRFields 0x00000000 -#define M_DEEPC0Fields64 UNS64Const(0x0000000000000000) -#define M_DEEPCRFields64 UNS64Const(0x0000000000000000) +#define M_DEEPC0Fields 0x00000000 +#define M_DEEPCRFields 0x00000000 +#define M_DEEPC0Fields64 UNS64Const(0x0000000000000000) +#define M_DEEPCRFields64 UNS64Const(0x0000000000000000) /* @@ -1618,28 +1618,28 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_PerfCnt $25 -#define R_C0_PerfCnt 25 -#define C0_PRFCNT0 C0_PerfCnt /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define C0_PRFCNT1 C0_PerfCnt /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_PerfCnt $25 +#define R_C0_PerfCnt 25 +#define C0_PRFCNT0 C0_PerfCnt /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_PRFCNT1 C0_PerfCnt /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define S_PerfCntM 31 /* More performance counters exist (R) */ -#define M_PerfCntM (1 << S_PerfCntM) -#define S_PerfCntEvent 5 /* Enabled event (R/W) */ -#define M_PerfCntEvent (0x3f << S_PerfCntEvent) -#define S_PerfCntIE 4 /* Interrupt Enable (R/W) */ -#define M_PerfCntIE (1 << S_PerfCntIE) -#define S_PerfCntU 3 /* Enable counting in User Mode (R/W) */ -#define M_PerfCntU (1 << S_PerfCntU) -#define S_PerfCntS 2 /* Enable counting in Supervisor Mode (R/W) */ -#define M_PerfCntS (1 << S_PerfCntS) -#define S_PerfCntK 1 /* Enable counting in Kernel Mode (R/W) */ -#define M_PerfCntK (1 << S_PerfCntK) -#define S_PerfCntEXL 0 /* Enable counting while EXL==1 (R/W) */ -#define M_PerfCntEXL (1 << S_PerfCntEXL) +#define S_PerfCntM 31 /* More performance counters exist (R) */ +#define M_PerfCntM (1 << S_PerfCntM) +#define S_PerfCntEvent 5 /* Enabled event (R/W) */ +#define M_PerfCntEvent (0x3f << S_PerfCntEvent) +#define S_PerfCntIE 4 /* Interrupt Enable (R/W) */ +#define M_PerfCntIE (1 << S_PerfCntIE) +#define S_PerfCntU 3 /* Enable counting in User Mode (R/W) */ +#define M_PerfCntU (1 << S_PerfCntU) +#define S_PerfCntS 2 /* Enable counting in Supervisor Mode (R/W) */ +#define M_PerfCntS (1 << S_PerfCntS) +#define S_PerfCntK 1 /* Enable counting in Kernel Mode (R/W) */ +#define M_PerfCntK (1 << S_PerfCntK) +#define S_PerfCntEXL 0 /* Enable counting while EXL==1 (R/W) */ +#define M_PerfCntEXL (1 << S_PerfCntEXL) -#define M_PerfCnt0Fields 0x7ffff800 -#define M_PerfCntRFields 0x80000000 +#define M_PerfCnt0Fields 0x7ffff800 +#define M_PerfCntRFields 0x80000000 /* @@ -1654,13 +1654,13 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_ErrCtl $26 -#define R_C0_ErrCtl 26 -#define C0_ECC $26 /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define R_C0_ECC 26 /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_ErrCtl $26 +#define R_C0_ErrCtl 26 +#define C0_ECC $26 /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define R_C0_ECC 26 /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define M_ErrCtl0Fields 0x00000000 -#define M_ErrCtlRFields 0x00000000 +#define M_ErrCtl0Fields 0x00000000 +#define M_ErrCtlRFields 0x00000000 /* @@ -1675,12 +1675,12 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_CacheErr $27 -#define R_C0_CacheErr 27 -#define C0_CACHE_ERR C0_CacheErr /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_CacheErr $27 +#define R_C0_CacheErr 27 +#define C0_CACHE_ERR C0_CacheErr /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define M_CacheErr0Fields 0x00000000 -#define M_CachErrRFields 0x00000000 +#define M_CacheErr0Fields 0x00000000 +#define M_CachErrRFields 0x00000000 /* @@ -1695,9 +1695,9 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_TagLo $28 -#define R_C0_TagLo 28 -#define C0_TAGLO C0_TagLo /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_TagLo $28 +#define R_C0_TagLo 28 +#define C0_TAGLO C0_TagLo /* OBSOLETE - DO NOT USE IN NEW CODE */ /* * Some implementations use separate TagLo registers for the @@ -1705,11 +1705,11 @@ * definitions can be used in relevant code */ -#define C0_ITagLo $28,0 -#define C0_DTagLo $28,2 +#define C0_ITagLo $28,0 +#define C0_DTagLo $28,2 -#define M_TagLo0Fields 0x00000000 -#define M_TagLoRFields 0x00000000 +#define M_TagLo0Fields 0x00000000 +#define M_TagLoRFields 0x00000000 /* @@ -1724,8 +1724,8 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_DataLo $28,1 -#define R_C0_DataLo 28 +#define C0_DataLo $28,1 +#define R_C0_DataLo 28 /* * Some implementations use separate DataLo registers for the @@ -1733,11 +1733,11 @@ * definitions can be used in relevant code */ -#define C0_IDataLo $28,1 -#define C0_DDataLo $28,3 +#define C0_IDataLo $28,1 +#define C0_DDataLo $28,3 -#define M_DataLo0Fields 0x00000000 -#define M_DataLoRFields 0xffffffff +#define M_DataLo0Fields 0x00000000 +#define M_DataLoRFields 0xffffffff /* @@ -1752,9 +1752,9 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_TagHi $29 -#define R_C0_TagHi 29 -#define C0_TAGHI C0_TagHi /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_TagHi $29 +#define R_C0_TagHi 29 +#define C0_TAGHI C0_TagHi /* OBSOLETE - DO NOT USE IN NEW CODE */ /* * Some implementations use separate TagHi registers for the @@ -1762,11 +1762,11 @@ * definitions can be used in relevant code */ -#define C0_ITagHi $29,0 -#define C0_DTagHi $29,2 +#define C0_ITagHi $29,0 +#define C0_DTagHi $29,2 -#define M_TagHi0Fields 0x00000000 -#define M_TagHiRFields 0x00000000 +#define M_TagHi0Fields 0x00000000 +#define M_TagHiRFields 0x00000000 /* @@ -1781,8 +1781,8 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_DataHi $29,1 -#define R_C0_DataHi 29 +#define C0_DataHi $29,1 +#define R_C0_DataHi 29 /* * Some implementations use separate DataHi registers for the @@ -1790,11 +1790,11 @@ * definitions can be used in relevant code */ -#define C0_IDataHi $29,1 -#define C0_DDataHi $29,3 +#define C0_IDataHi $29,1 +#define C0_DDataHi $29,3 -#define M_DataHi0Fields 0x00000000 -#define M_DataHiRFields 0xffffffff +#define M_DataHi0Fields 0x00000000 +#define M_DataHiRFields 0xffffffff /* @@ -1809,14 +1809,14 @@ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_ErrorEPC $30 -#define R_C0_ErrorEPC 30 -#define C0_ERROR_EPC C0_ErrorEPC /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_ErrorEPC $30 +#define R_C0_ErrorEPC 30 +#define C0_ERROR_EPC C0_ErrorEPC /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define M_ErrorEPC0Fields 0x00000000 -#define M_ErrorEPCRFields 0x00000000 -#define M_ErrorEPC0Fields64 UNS64Const(0x0000000000000000) -#define M_ErrorEPCRFields64 UNS64Const(0x0000000000000000) +#define M_ErrorEPC0Fields 0x00000000 +#define M_ErrorEPCRFields 0x00000000 +#define M_ErrorEPC0Fields64 UNS64Const(0x0000000000000000) +#define M_ErrorEPCRFields64 UNS64Const(0x0000000000000000) /* @@ -1831,13 +1831,13 @@ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_DESAVE $31 -#define R_C0_DESAVE 31 +#define C0_DESAVE $31 +#define R_C0_DESAVE 31 -#define M_DESAVE0Fields 0x00000000 -#define M_DESAVERFields 0x00000000 -#define M_DESAVE0Fields64 UNS64Const(0x0000000000000000) -#define M_DESAVERFields64 UNS64Const(0x0000000000000000) +#define M_DESAVE0Fields 0x00000000 +#define M_DESAVERFields 0x00000000 +#define M_DESAVE0Fields64 UNS64Const(0x0000000000000000) +#define M_DESAVERFields64 UNS64Const(0x0000000000000000) /* @@ -1853,38 +1853,38 @@ ************************************************************************* */ -#define fp0 $f0 -#define fp1 $f1 -#define fp2 $f2 -#define fp3 $f3 -#define fp4 $f4 -#define fp5 $f5 -#define fp6 $f6 -#define fp7 $f7 -#define fp8 $f8 -#define fp9 $f9 -#define fp10 $f10 -#define fp11 $f11 -#define fp12 $f12 -#define fp13 $f13 -#define fp14 $f14 -#define fp15 $f15 -#define fp16 $f16 -#define fp17 $f17 -#define fp18 $f18 -#define fp19 $f19 -#define fp20 $f20 -#define fp21 $f21 -#define fp22 $f22 -#define fp23 $f23 -#define fp24 $f24 -#define fp25 $f25 -#define fp26 $f26 -#define fp27 $f27 -#define fp28 $f28 -#define fp29 $f29 -#define fp30 $f30 -#define fp31 $f31 +#define fp0 $f0 +#define fp1 $f1 +#define fp2 $f2 +#define fp3 $f3 +#define fp4 $f4 +#define fp5 $f5 +#define fp6 $f6 +#define fp7 $f7 +#define fp8 $f8 +#define fp9 $f9 +#define fp10 $f10 +#define fp11 $f11 +#define fp12 $f12 +#define fp13 $f13 +#define fp14 $f14 +#define fp15 $f15 +#define fp16 $f16 +#define fp17 $f17 +#define fp18 $f18 +#define fp19 $f19 +#define fp20 $f20 +#define fp21 $f21 +#define fp22 $f22 +#define fp23 $f23 +#define fp24 $f24 +#define fp25 $f25 +#define fp26 $f26 +#define fp27 $f27 +#define fp28 $f28 +#define fp29 $f29 +#define fp30 $f30 +#define fp31 $f31 /* * The following definitions are used to convert an FPR name @@ -1892,39 +1892,39 @@ * This is used in macro substitution in the AVPs. */ -#define fp1_even $f0 -#define fp3_even $f2 -#define fp5_even $f4 -#define fp7_even $f6 -#define fp9_even $f8 -#define fp11_even $f10 -#define fp13_even $f12 -#define fp15_even $f14 -#define fp17_even $f16 -#define fp19_even $f18 -#define fp21_even $f20 -#define fp23_even $f22 -#define fp25_even $f24 -#define fp27_even $f26 -#define fp29_even $f28 -#define fp31_even $f30 - -#define fp0_odd $f1 -#define fp2_odd $f3 -#define fp4_odd $f5 -#define fp6_odd $f7 -#define fp8_odd $f9 -#define fp10_odd $f11 -#define fp12_odd $f13 -#define fp14_odd $f15 -#define fp16_odd $f17 -#define fp18_odd $f19 -#define fp20_odd $f21 -#define fp22_odd $f23 -#define fp24_odd $f25 -#define fp26_odd $f27 -#define fp28_odd $f29 -#define fp30_odd $f31 +#define fp1_even $f0 +#define fp3_even $f2 +#define fp5_even $f4 +#define fp7_even $f6 +#define fp9_even $f8 +#define fp11_even $f10 +#define fp13_even $f12 +#define fp15_even $f14 +#define fp17_even $f16 +#define fp19_even $f18 +#define fp21_even $f20 +#define fp23_even $f22 +#define fp25_even $f24 +#define fp27_even $f26 +#define fp29_even $f28 +#define fp31_even $f30 + +#define fp0_odd $f1 +#define fp2_odd $f3 +#define fp4_odd $f5 +#define fp6_odd $f7 +#define fp8_odd $f9 +#define fp10_odd $f11 +#define fp12_odd $f13 +#define fp14_odd $f15 +#define fp16_odd $f17 +#define fp18_odd $f19 +#define fp20_odd $f21 +#define fp22_odd $f23 +#define fp24_odd $f25 +#define fp26_odd $f27 +#define fp28_odd $f29 +#define fp30_odd $f31 /* @@ -1936,38 +1936,38 @@ * to the assembler register name ($n). */ -#define R_fp0 0 -#define R_fp1 1 -#define R_fp2 2 -#define R_fp3 3 -#define R_fp4 4 -#define R_fp5 5 -#define R_fp6 6 -#define R_fp7 7 -#define R_fp8 8 -#define R_fp9 9 -#define R_fp10 10 -#define R_fp11 11 -#define R_fp12 12 -#define R_fp13 13 -#define R_fp14 14 -#define R_fp15 15 -#define R_fp16 16 -#define R_fp17 17 -#define R_fp18 18 -#define R_fp19 19 -#define R_fp20 20 -#define R_fp21 21 -#define R_fp22 22 -#define R_fp23 23 -#define R_fp24 24 -#define R_fp25 25 -#define R_fp26 26 -#define R_fp27 27 -#define R_fp28 28 -#define R_fp29 29 -#define R_fp30 30 -#define R_fp31 31 +#define R_fp0 0 +#define R_fp1 1 +#define R_fp2 2 +#define R_fp3 3 +#define R_fp4 4 +#define R_fp5 5 +#define R_fp6 6 +#define R_fp7 7 +#define R_fp8 8 +#define R_fp9 9 +#define R_fp10 10 +#define R_fp11 11 +#define R_fp12 12 +#define R_fp13 13 +#define R_fp14 14 +#define R_fp15 15 +#define R_fp16 16 +#define R_fp17 17 +#define R_fp18 18 +#define R_fp19 19 +#define R_fp20 20 +#define R_fp21 21 +#define R_fp22 22 +#define R_fp23 23 +#define R_fp24 24 +#define R_fp25 25 +#define R_fp26 26 +#define R_fp27 27 +#define R_fp28 28 +#define R_fp29 29 +#define R_fp30 30 +#define R_fp31 31 /* @@ -1976,11 +1976,11 @@ ************************************************************************* */ -#define fc0 $0 -#define fc25 $25 -#define fc26 $26 -#define fc28 $28 -#define fc31 $31 +#define fc0 $0 +#define fc25 $25 +#define fc26 $26 +#define fc28 $28 +#define fc31 $31 /* @@ -1992,11 +1992,11 @@ * to the assembler register name ($n). */ -#define R_fc0 0 -#define R_fc25 25 -#define R_fc26 26 -#define R_fc28 28 -#define R_fc31 31 +#define R_fc0 0 +#define R_fc25 25 +#define R_fc26 26 +#define R_fc28 28 +#define R_fc31 31 /* @@ -2005,14 +2005,14 @@ ************************************************************************* */ -#define cc0 $fcc0 -#define cc1 $fcc1 -#define cc2 $fcc2 -#define cc3 $fcc3 -#define cc4 $fcc4 -#define cc5 $fcc5 -#define cc6 $fcc6 -#define cc7 $fcc7 +#define cc0 $fcc0 +#define cc1 $fcc1 +#define cc2 $fcc2 +#define cc3 $fcc3 +#define cc4 $fcc4 +#define cc5 $fcc5 +#define cc6 $fcc6 +#define cc7 $fcc7 /* @@ -2024,14 +2024,14 @@ * to the assembler register name ($n). */ -#define R_cc0 0 -#define R_cc1 1 -#define R_cc2 2 -#define R_cc3 3 -#define R_cc4 4 -#define R_cc5 5 -#define R_cc6 6 -#define R_cc7 7 +#define R_cc0 0 +#define R_cc1 1 +#define R_cc2 2 +#define R_cc3 3 +#define R_cc4 4 +#define R_cc5 5 +#define R_cc6 6 +#define R_cc7 7 /* @@ -2047,27 +2047,27 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C1_FIR $0 -#define R_C1_FIR 0 +#define C1_FIR $0 +#define R_C1_FIR 0 -#define S_FIRConfigS 16 -#define M_FIRConfigS (0x1 << S_FIRConfigS) -#define S_FIRConfigD 17 -#define M_FIRConfigD (0x1 << S_FIRConfigD) -#define S_FIRConfigPS 18 -#define M_FIRConfigPS (0x1 << S_FIRConfigPS) -#define S_FIRConfig3D 19 -#define M_FIRConfig3D (0x1 << S_FIRConfig3D) -#define M_FIRConfigAll (M_FIRConfigS|M_FIRConfigD|M_FIRConfigPS|M_FIRConfig3D) +#define S_FIRConfigS 16 +#define M_FIRConfigS (0x1 << S_FIRConfigS) +#define S_FIRConfigD 17 +#define M_FIRConfigD (0x1 << S_FIRConfigD) +#define S_FIRConfigPS 18 +#define M_FIRConfigPS (0x1 << S_FIRConfigPS) +#define S_FIRConfig3D 19 +#define M_FIRConfig3D (0x1 << S_FIRConfig3D) +#define M_FIRConfigAll (M_FIRConfigS|M_FIRConfigD|M_FIRConfigPS|M_FIRConfig3D) -#define S_FIRImp 8 -#define M_FIRImp (0xff << S_FIRImp) +#define S_FIRImp 8 +#define M_FIRImp (0xff << S_FIRImp) -#define S_FIRRev 0 -#define M_FIRRev (0xff << S_FIRRev) +#define S_FIRRev 0 +#define M_FIRRev (0xff << S_FIRRev) -#define M_FIR0Fields 0xfff00000 -#define M_FIRRFields 0x000fffff +#define M_FIR0Fields 0xfff00000 +#define M_FIRRFields 0x000fffff /* ************************************************************************ @@ -2081,30 +2081,30 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C1_FCCR $25 -#define R_C1_FCCR 25 +#define C1_FCCR $25 +#define R_C1_FCCR 25 -#define S_FCCRCC 0 -#define M_FCCRCC (0xff << S_FCCRCC) -#define S_FCCRCC7 7 -#define M_FCCRCC7 (0x1 << S_FCCRCC7) -#define S_FCCRCC6 6 -#define M_FCCRCC6 (0x1 << S_FCCRCC6) -#define S_FCCRCC5 5 -#define M_FCCRCC5 (0x1 << S_FCCRCC5) -#define S_FCCRCC4 4 -#define M_FCCRCC4 (0x1 << S_FCCRCC4) -#define S_FCCRCC3 3 -#define M_FCCRCC3 (0x1 << S_FCCRCC3) -#define S_FCCRCC2 2 -#define M_FCCRCC2 (0x1 << S_FCCRCC2) -#define S_FCCRCC1 1 -#define M_FCCRCC1 (0x1 << S_FCCRCC1) -#define S_FCCRCC0 0 -#define M_FCCRCC0 (0x1 << S_FCCRCC0) +#define S_FCCRCC 0 +#define M_FCCRCC (0xff << S_FCCRCC) +#define S_FCCRCC7 7 +#define M_FCCRCC7 (0x1 << S_FCCRCC7) +#define S_FCCRCC6 6 +#define M_FCCRCC6 (0x1 << S_FCCRCC6) +#define S_FCCRCC5 5 +#define M_FCCRCC5 (0x1 << S_FCCRCC5) +#define S_FCCRCC4 4 +#define M_FCCRCC4 (0x1 << S_FCCRCC4) +#define S_FCCRCC3 3 +#define M_FCCRCC3 (0x1 << S_FCCRCC3) +#define S_FCCRCC2 2 +#define M_FCCRCC2 (0x1 << S_FCCRCC2) +#define S_FCCRCC1 1 +#define M_FCCRCC1 (0x1 << S_FCCRCC1) +#define S_FCCRCC0 0 +#define M_FCCRCC0 (0x1 << S_FCCRCC0) -#define M_FCCR0Fields 0xffffff00 -#define M_FCCRRFields 0x000000ff +#define M_FCCR0Fields 0xffffff00 +#define M_FCCRRFields 0x000000ff /* @@ -2120,39 +2120,39 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C1_FEXR $26 -#define R_C1_FEXR 26 +#define C1_FEXR $26 +#define R_C1_FEXR 26 -#define S_FEXRExc 12 -#define M_FEXRExc (0x3f << S_FEXRExc) -#define S_FEXRExcE 17 -#define M_FEXRExcE (0x1 << S_FEXRExcE) -#define S_FEXRExcV 16 -#define M_FEXRExcV (0x1 << S_FEXRExcV) -#define S_FEXRExcZ 15 -#define M_FEXRExcZ (0x1 << S_FEXRExcZ) -#define S_FEXRExcO 14 -#define M_FEXRExcO (0x1 << S_FEXRExcO) -#define S_FEXRExcU 13 -#define M_FEXRExcU (0x1 << S_FEXRExcU) -#define S_FEXRExcI 12 -#define M_FEXRExcI (0x1 << S_FEXRExcI) +#define S_FEXRExc 12 +#define M_FEXRExc (0x3f << S_FEXRExc) +#define S_FEXRExcE 17 +#define M_FEXRExcE (0x1 << S_FEXRExcE) +#define S_FEXRExcV 16 +#define M_FEXRExcV (0x1 << S_FEXRExcV) +#define S_FEXRExcZ 15 +#define M_FEXRExcZ (0x1 << S_FEXRExcZ) +#define S_FEXRExcO 14 +#define M_FEXRExcO (0x1 << S_FEXRExcO) +#define S_FEXRExcU 13 +#define M_FEXRExcU (0x1 << S_FEXRExcU) +#define S_FEXRExcI 12 +#define M_FEXRExcI (0x1 << S_FEXRExcI) -#define S_FEXRFlg 2 -#define M_FEXRFlg (0x1f << S_FEXRFlg) -#define S_FEXRFlgV 6 -#define M_FEXRFlgV (0x1 << S_FEXRFlgV) -#define S_FEXRFlgZ 5 -#define M_FEXRFlgZ (0x1 << S_FEXRFlgZ) -#define S_FEXRFlgO 4 -#define M_FEXRFlgO (0x1 << S_FEXRFlgO) -#define S_FEXRFlgU 3 -#define M_FEXRFlgU (0x1 << S_FEXRFlgU) -#define S_FEXRFlgI 2 -#define M_FEXRFlgI (0x1 << S_FEXRFlgI) +#define S_FEXRFlg 2 +#define M_FEXRFlg (0x1f << S_FEXRFlg) +#define S_FEXRFlgV 6 +#define M_FEXRFlgV (0x1 << S_FEXRFlgV) +#define S_FEXRFlgZ 5 +#define M_FEXRFlgZ (0x1 << S_FEXRFlgZ) +#define S_FEXRFlgO 4 +#define M_FEXRFlgO (0x1 << S_FEXRFlgO) +#define S_FEXRFlgU 3 +#define M_FEXRFlgU (0x1 << S_FEXRFlgU) +#define S_FEXRFlgI 2 +#define M_FEXRFlgI (0x1 << S_FEXRFlgI) -#define M_FEXR0Fields 0xfffc0f83 -#define M_FEXRRFields 0x00000000 +#define M_FEXR0Fields 0xfffc0f83 +#define M_FEXRRFields 0x00000000 /* @@ -2168,30 +2168,30 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C1_FENR $28 -#define R_C1_FENR 28 +#define C1_FENR $28 +#define R_C1_FENR 28 -#define S_FENREna 7 -#define M_FENREna (0x1f << S_FENREna) -#define S_FENREnaV 11 -#define M_FENREnaV (0x1 << S_FENREnaV) -#define S_FENREnaZ 10 -#define M_FENREnaZ (0x1 << S_FENREnaZ) -#define S_FENREnaO 9 -#define M_FENREnaO (0x1 << S_FENREnaO) -#define S_FENREnaU 8 -#define M_FENREnaU (0x1 << S_FENREnaU) -#define S_FENREnaI 7 -#define M_FENREnaI (0x1 << S_FENREnaI) +#define S_FENREna 7 +#define M_FENREna (0x1f << S_FENREna) +#define S_FENREnaV 11 +#define M_FENREnaV (0x1 << S_FENREnaV) +#define S_FENREnaZ 10 +#define M_FENREnaZ (0x1 << S_FENREnaZ) +#define S_FENREnaO 9 +#define M_FENREnaO (0x1 << S_FENREnaO) +#define S_FENREnaU 8 +#define M_FENREnaU (0x1 << S_FENREnaU) +#define S_FENREnaI 7 +#define M_FENREnaI (0x1 << S_FENREnaI) -#define S_FENRFS 2 -#define M_FENRFS (0x1 << S_FENRFS) +#define S_FENRFS 2 +#define M_FENRFS (0x1 << S_FENRFS) -#define S_FENRRM 0 -#define M_FENRRM (0x3 << S_FENRRM) +#define S_FENRRM 0 +#define M_FENRRM (0x3 << S_FENRRM) -#define M_FENR0Fields 0xfffff078 -#define M_FENRRFields 0x00000000 +#define M_FENR0Fields 0xfffff078 +#define M_FENRRFields 0x00000000 /* @@ -2207,90 +2207,90 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C1_FCSR $31 -#define R_C1_FCSR 31 - -#define S_FCSRFCC7_1 25 /* Floating point condition codes 7..1 (R/W) */ -#define M_FCSRFCC7_1 (0x7f << S_FCSRFCC7_1) -#define S_FCSRCC7 31 -#define M_FCSRCC7 (0x1 << S_FCSRCC7) -#define S_FCSRCC6 30 -#define M_FCSRCC6 (0x1 << S_FCSRCC6) -#define S_FCSRCC5 29 -#define M_FCSRCC5 (0x1 << S_FCSRCC5) -#define S_FCSRCC4 28 -#define M_FCSRCC4 (0x1 << S_FCSRCC4) -#define S_FCSRCC3 27 -#define M_FCSRCC3 (0x1 << S_FCSRCC3) -#define S_FCSRCC2 26 -#define M_FCSRCC2 (0x1 << S_FCSRCC2) -#define S_FCSRCC1 25 -#define M_FCSRCC1 (0x1 << S_FCSRCC1) - -#define S_FCSRFS 24 /* Flush denorms to zero (R/W) */ -#define M_FCSRFS (0x1 << S_FCSRFS) - -#define S_FCSRCC0 23 /* Floating point condition code 0 (R/W) */ -#define M_FCSRCC0 (0x1 << S_FCSRCC0) -#define S_FCSRCC S_FCSRCC0 -#define M_FCSRCC M_FCSRCC0 - -#define S_FCSRImpl 21 /* Implementation-specific control bits (R/W) */ -#define M_FCSRImpl (0x3 << S_FCSRImpl) - -#define S_FCSRExc 12 /* Exception cause (R/W) */ -#define M_FCSRExc (0x3f << S_FCSRExc) -#define S_FCSRExcE 17 -#define M_FCSRExcE (0x1 << S_FCSRExcE) -#define S_FCSRExcV 16 -#define M_FCSRExcV (0x1 << S_FCSRExcV) -#define S_FCSRExcZ 15 -#define M_FCSRExcZ (0x1 << S_FCSRExcZ) -#define S_FCSRExcO 14 -#define M_FCSRExcO (0x1 << S_FCSRExcO) -#define S_FCSRExcU 13 -#define M_FCSRExcU (0x1 << S_FCSRExcU) -#define S_FCSRExcI 12 -#define M_FCSRExcI (0x1 << S_FCSRExcI) - -#define S_FCSREna 7 /* Exception enable (R/W) */ -#define M_FCSREna (0x1f << S_FCSREna) -#define S_FCSREnaV 11 -#define M_FCSREnaV (0x1 << S_FCSREnaV) -#define S_FCSREnaZ 10 -#define M_FCSREnaZ (0x1 << S_FCSREnaZ) -#define S_FCSREnaO 9 -#define M_FCSREnaO (0x1 << S_FCSREnaO) -#define S_FCSREnaU 8 -#define M_FCSREnaU (0x1 << S_FCSREnaU) -#define S_FCSREnaI 7 -#define M_FCSREnaI (0x1 << S_FCSREnaI) - -#define S_FCSRFlg 2 /* Exception flags (R/W) */ -#define M_FCSRFlg (0x1f << S_FCSRFlg) -#define S_FCSRFlgV 6 -#define M_FCSRFlgV (0x1 << S_FCSRFlgV) -#define S_FCSRFlgZ 5 -#define M_FCSRFlgZ (0x1 << S_FCSRFlgZ) -#define S_FCSRFlgO 4 -#define M_FCSRFlgO (0x1 << S_FCSRFlgO) -#define S_FCSRFlgU 3 -#define M_FCSRFlgU (0x1 << S_FCSRFlgU) -#define S_FCSRFlgI 2 -#define M_FCSRFlgI (0x1 << S_FCSRFlgI) - -#define S_FCSRRM 0 /* Rounding mode (R/W) */ -#define M_FCSRRM (0x3 << S_FCSRRM) - -#define M_FCSR0Fields 0x001c0000 -#define M_FCSRRFields 0x00000000 +#define C1_FCSR $31 +#define R_C1_FCSR 31 + +#define S_FCSRFCC7_1 25 /* Floating point condition codes 7..1 (R/W) */ +#define M_FCSRFCC7_1 (0x7f << S_FCSRFCC7_1) +#define S_FCSRCC7 31 +#define M_FCSRCC7 (0x1 << S_FCSRCC7) +#define S_FCSRCC6 30 +#define M_FCSRCC6 (0x1 << S_FCSRCC6) +#define S_FCSRCC5 29 +#define M_FCSRCC5 (0x1 << S_FCSRCC5) +#define S_FCSRCC4 28 +#define M_FCSRCC4 (0x1 << S_FCSRCC4) +#define S_FCSRCC3 27 +#define M_FCSRCC3 (0x1 << S_FCSRCC3) +#define S_FCSRCC2 26 +#define M_FCSRCC2 (0x1 << S_FCSRCC2) +#define S_FCSRCC1 25 +#define M_FCSRCC1 (0x1 << S_FCSRCC1) + +#define S_FCSRFS 24 /* Flush denorms to zero (R/W) */ +#define M_FCSRFS (0x1 << S_FCSRFS) + +#define S_FCSRCC0 23 /* Floating point condition code 0 (R/W) */ +#define M_FCSRCC0 (0x1 << S_FCSRCC0) +#define S_FCSRCC S_FCSRCC0 +#define M_FCSRCC M_FCSRCC0 + +#define S_FCSRImpl 21 /* Implementation-specific control bits (R/W) */ +#define M_FCSRImpl (0x3 << S_FCSRImpl) + +#define S_FCSRExc 12 /* Exception cause (R/W) */ +#define M_FCSRExc (0x3f << S_FCSRExc) +#define S_FCSRExcE 17 +#define M_FCSRExcE (0x1 << S_FCSRExcE) +#define S_FCSRExcV 16 +#define M_FCSRExcV (0x1 << S_FCSRExcV) +#define S_FCSRExcZ 15 +#define M_FCSRExcZ (0x1 << S_FCSRExcZ) +#define S_FCSRExcO 14 +#define M_FCSRExcO (0x1 << S_FCSRExcO) +#define S_FCSRExcU 13 +#define M_FCSRExcU (0x1 << S_FCSRExcU) +#define S_FCSRExcI 12 +#define M_FCSRExcI (0x1 << S_FCSRExcI) + +#define S_FCSREna 7 /* Exception enable (R/W) */ +#define M_FCSREna (0x1f << S_FCSREna) +#define S_FCSREnaV 11 +#define M_FCSREnaV (0x1 << S_FCSREnaV) +#define S_FCSREnaZ 10 +#define M_FCSREnaZ (0x1 << S_FCSREnaZ) +#define S_FCSREnaO 9 +#define M_FCSREnaO (0x1 << S_FCSREnaO) +#define S_FCSREnaU 8 +#define M_FCSREnaU (0x1 << S_FCSREnaU) +#define S_FCSREnaI 7 +#define M_FCSREnaI (0x1 << S_FCSREnaI) + +#define S_FCSRFlg 2 /* Exception flags (R/W) */ +#define M_FCSRFlg (0x1f << S_FCSRFlg) +#define S_FCSRFlgV 6 +#define M_FCSRFlgV (0x1 << S_FCSRFlgV) +#define S_FCSRFlgZ 5 +#define M_FCSRFlgZ (0x1 << S_FCSRFlgZ) +#define S_FCSRFlgO 4 +#define M_FCSRFlgO (0x1 << S_FCSRFlgO) +#define S_FCSRFlgU 3 +#define M_FCSRFlgU (0x1 << S_FCSRFlgU) +#define S_FCSRFlgI 2 +#define M_FCSRFlgI (0x1 << S_FCSRFlgI) + +#define S_FCSRRM 0 /* Rounding mode (R/W) */ +#define M_FCSRRM (0x3 << S_FCSRRM) + +#define M_FCSR0Fields 0x001c0000 +#define M_FCSRRFields 0x00000000 /* * Values in the rounding mode field (of both FCSR and FCCR) */ -#define K_FCSRRM_RN 0 -#define K_FCSRRM_RZ 1 -#define K_FCSRRM_RP 2 -#define K_FCSRRM_RM 3 +#define K_FCSRRM_RN 0 +#define K_FCSRRM_RZ 1 +#define K_FCSRRM_RP 2 +#define K_FCSRRM_RM 3 #endif /* _COMMON_MIPS_DEF_H_ */ diff --git a/libcpu/mips/common/mips_regs.h b/libcpu/mips/common/mips_regs.h index 429de4c5cb..aa8b5a6cd5 100644 --- a/libcpu/mips/common/mips_regs.h +++ b/libcpu/mips/common/mips_regs.h @@ -17,25 +17,25 @@ #define MIPS_REG_NR 32 typedef struct { - rt_uint32_t regs[MIPS_REG_NR]; /* 32 个通用目的寄存器 */ - rt_uint32_t CP0Status; /* CP0 协处理器状态寄存器 */ - rt_uint32_t CP0DataHI; /* 除数高位寄存器 */ - rt_uint32_t CP0DataLO; /* 除数低位寄存器 */ - rt_uint32_t CP0BadVAddr; /* 出错地址寄存器 */ - rt_uint32_t CP0Cause; /* 产生中断或者异常查看的寄存器*/ - rt_uint32_t CP0EPC; /* 程序计数器寄存器 */ + rt_uint32_t regs[MIPS_REG_NR]; /* 32 个通用目的寄存器 */ + rt_uint32_t CP0Status; /* CP0 协处理器状态寄存器 */ + rt_uint32_t CP0DataHI; /* 除数高位寄存器 */ + rt_uint32_t CP0DataLO; /* 除数低位寄存器 */ + rt_uint32_t CP0BadVAddr; /* 出错地址寄存器 */ + rt_uint32_t CP0Cause; /* 产生中断或者异常查看的寄存器*/ + rt_uint32_t CP0EPC; /* 程序计数器寄存器 */ } mips_reg_ctx; #define MIPS_ARG_REG_NR 4 typedef struct { - rt_uint32_t args[MIPS_ARG_REG_NR]; /* 4 个参数寄存器 */ + rt_uint32_t args[MIPS_ARG_REG_NR]; /* 4 个参数寄存器 */ } mips_arg_ctx; struct linkctx { - rt_uint32_t id; - struct linkctx *next; + rt_uint32_t id; + struct linkctx *next; }; struct fpctx @@ -51,8 +51,8 @@ struct fp32ctx struct fpctx fp; union { - double d[16]; /* even doubles */ - float s[32]; /* even singles, padded */ + double d[16]; /* even doubles */ + float s[32]; /* even singles, padded */ }; }; @@ -61,15 +61,15 @@ struct fp64ctx struct fpctx fp; union { - double d[32]; /* even doubles, followed by odd doubles */ - float s[64]; /* even singles, followed by odd singles, padded */ + double d[32]; /* even doubles, followed by odd doubles */ + float s[64]; /* even singles, followed by odd singles, padded */ }; }; #endif /* !defined(__ASSEMBLY__) && !defined(ASSEMBLY) */ -#define MIPS_STK_CTX_WORD_SIZE 38 -#define SZREG 4 +#define MIPS_STK_CTX_WORD_SIZE 38 +#define SZREG 4 /********************************************************************************************************* MIPS 的寄存器索引 *********************************************************************************************************/ @@ -117,8 +117,8 @@ struct fp64ctx #define STK_OFFSET_LAST ((MIPS_STK_CTX_WORD_SIZE - 1) * SZREG) -#define FP32CTX_CSR ((SZREG)*2) -#define FP64CTX_CSR ((SZREG)*2) +#define FP32CTX_CSR ((SZREG)*2) +#define FP64CTX_CSR ((SZREG)*2) #define LINKCTX_ID ((SZREG)*0) #define LINKCTX_NEXT ((SZREG)*1) @@ -128,61 +128,61 @@ struct fp64ctx #define LINKCTX_TYPE_FMSA 0x463D5341 #define LINKCTX_TYPE_DSP 0x00445350 #define LINKCTX_TYPE_STKSWP 0x53574150 -#define LINKCTX_TYPE_XPA 0x00585041 - -#define FP32CTX_0 ((SZREG)*4) -#define FP32CTX_2 (FP32CTX_0 + (1 * 8)) -#define FP32CTX_4 (FP32CTX_0 + (2 * 8)) -#define FP32CTX_6 (FP32CTX_0 + (3 * 8)) -#define FP32CTX_8 (FP32CTX_0 + (4 * 8)) -#define FP32CTX_10 (FP32CTX_0 + (5 * 8)) -#define FP32CTX_12 (FP32CTX_0 + (6 * 8)) -#define FP32CTX_14 (FP32CTX_0 + (7 * 8)) -#define FP32CTX_16 (FP32CTX_0 + (8 * 8)) -#define FP32CTX_18 (FP32CTX_0 + (9 * 8)) -#define FP32CTX_20 (FP32CTX_0 + (10 * 8)) -#define FP32CTX_22 (FP32CTX_0 + (11 * 8)) -#define FP32CTX_24 (FP32CTX_0 + (12 * 8)) -#define FP32CTX_26 (FP32CTX_0 + (13 * 8)) -#define FP32CTX_28 (FP32CTX_0 + (14 * 8)) -#define FP32CTX_30 (FP32CTX_0 + (15 * 8)) -#define FP32CTX_SIZE (FP32CTX_30 + (17 * 8)) - -#define FP64CTX_0 ((SZREG)*4) -#define FP64CTX_2 (FP64CTX_0 + (1 * 8)) -#define FP64CTX_4 (FP64CTX_0 + (2 * 8)) -#define FP64CTX_6 (FP64CTX_0 + (3 * 8)) -#define FP64CTX_8 (FP64CTX_0 + (4 * 8)) -#define FP64CTX_10 (FP64CTX_0 + (5 * 8)) -#define FP64CTX_12 (FP64CTX_0 + (6 * 8)) -#define FP64CTX_14 (FP64CTX_0 + (7 * 8)) -#define FP64CTX_16 (FP64CTX_0 + (8 * 8)) -#define FP64CTX_18 (FP64CTX_0 + (9 * 8)) -#define FP64CTX_20 (FP64CTX_0 + (10 * 8)) -#define FP64CTX_22 (FP64CTX_0 + (11 * 8)) -#define FP64CTX_24 (FP64CTX_0 + (12 * 8)) -#define FP64CTX_26 (FP64CTX_0 + (13 * 8)) -#define FP64CTX_28 (FP64CTX_0 + (14 * 8)) -#define FP64CTX_30 (FP64CTX_0 + (15 * 8)) -#define FP64CTX_1 (FP64CTX_30 + (1 * 8)) -#define FP64CTX_3 (FP64CTX_30 + (2 * 8)) -#define FP64CTX_5 (FP64CTX_30 + (3 * 8)) -#define FP64CTX_7 (FP64CTX_30 + (4 * 8)) -#define FP64CTX_9 (FP64CTX_30 + (5 * 8)) -#define FP64CTX_11 (FP64CTX_30 + (6 * 8)) -#define FP64CTX_13 (FP64CTX_30 + (7 * 8)) -#define FP64CTX_15 (FP64CTX_30 + (8 * 8)) -#define FP64CTX_17 (FP64CTX_30 + (9 * 8)) -#define FP64CTX_19 (FP64CTX_30 + (10 * 8)) -#define FP64CTX_21 (FP64CTX_30 + (11 * 8)) -#define FP64CTX_23 (FP64CTX_30 + (12 * 8)) -#define FP64CTX_25 (FP64CTX_30 + (13 * 8)) -#define FP64CTX_27 (FP64CTX_30 + (14 * 8)) -#define FP64CTX_29 (FP64CTX_30 + (15 * 8)) -#define FP64CTX_31 (FP64CTX_30 + (16 * 8)) -#define FP64CTX_SIZE (FP64CTX_31 + (17 * 8)) - -#define FPCTX_SIZE() (mips_getsr() & ST0_FR ? FP64CTX_SIZE : FP32CTX_SIZE) +#define LINKCTX_TYPE_XPA 0x00585041 + +#define FP32CTX_0 ((SZREG)*4) +#define FP32CTX_2 (FP32CTX_0 + (1 * 8)) +#define FP32CTX_4 (FP32CTX_0 + (2 * 8)) +#define FP32CTX_6 (FP32CTX_0 + (3 * 8)) +#define FP32CTX_8 (FP32CTX_0 + (4 * 8)) +#define FP32CTX_10 (FP32CTX_0 + (5 * 8)) +#define FP32CTX_12 (FP32CTX_0 + (6 * 8)) +#define FP32CTX_14 (FP32CTX_0 + (7 * 8)) +#define FP32CTX_16 (FP32CTX_0 + (8 * 8)) +#define FP32CTX_18 (FP32CTX_0 + (9 * 8)) +#define FP32CTX_20 (FP32CTX_0 + (10 * 8)) +#define FP32CTX_22 (FP32CTX_0 + (11 * 8)) +#define FP32CTX_24 (FP32CTX_0 + (12 * 8)) +#define FP32CTX_26 (FP32CTX_0 + (13 * 8)) +#define FP32CTX_28 (FP32CTX_0 + (14 * 8)) +#define FP32CTX_30 (FP32CTX_0 + (15 * 8)) +#define FP32CTX_SIZE (FP32CTX_30 + (17 * 8)) + +#define FP64CTX_0 ((SZREG)*4) +#define FP64CTX_2 (FP64CTX_0 + (1 * 8)) +#define FP64CTX_4 (FP64CTX_0 + (2 * 8)) +#define FP64CTX_6 (FP64CTX_0 + (3 * 8)) +#define FP64CTX_8 (FP64CTX_0 + (4 * 8)) +#define FP64CTX_10 (FP64CTX_0 + (5 * 8)) +#define FP64CTX_12 (FP64CTX_0 + (6 * 8)) +#define FP64CTX_14 (FP64CTX_0 + (7 * 8)) +#define FP64CTX_16 (FP64CTX_0 + (8 * 8)) +#define FP64CTX_18 (FP64CTX_0 + (9 * 8)) +#define FP64CTX_20 (FP64CTX_0 + (10 * 8)) +#define FP64CTX_22 (FP64CTX_0 + (11 * 8)) +#define FP64CTX_24 (FP64CTX_0 + (12 * 8)) +#define FP64CTX_26 (FP64CTX_0 + (13 * 8)) +#define FP64CTX_28 (FP64CTX_0 + (14 * 8)) +#define FP64CTX_30 (FP64CTX_0 + (15 * 8)) +#define FP64CTX_1 (FP64CTX_30 + (1 * 8)) +#define FP64CTX_3 (FP64CTX_30 + (2 * 8)) +#define FP64CTX_5 (FP64CTX_30 + (3 * 8)) +#define FP64CTX_7 (FP64CTX_30 + (4 * 8)) +#define FP64CTX_9 (FP64CTX_30 + (5 * 8)) +#define FP64CTX_11 (FP64CTX_30 + (6 * 8)) +#define FP64CTX_13 (FP64CTX_30 + (7 * 8)) +#define FP64CTX_15 (FP64CTX_30 + (8 * 8)) +#define FP64CTX_17 (FP64CTX_30 + (9 * 8)) +#define FP64CTX_19 (FP64CTX_30 + (10 * 8)) +#define FP64CTX_21 (FP64CTX_30 + (11 * 8)) +#define FP64CTX_23 (FP64CTX_30 + (12 * 8)) +#define FP64CTX_25 (FP64CTX_30 + (13 * 8)) +#define FP64CTX_27 (FP64CTX_30 + (14 * 8)) +#define FP64CTX_29 (FP64CTX_30 + (15 * 8)) +#define FP64CTX_31 (FP64CTX_30 + (16 * 8)) +#define FP64CTX_SIZE (FP64CTX_31 + (17 * 8)) + +#define FPCTX_SIZE() (mips_getsr() & ST0_FR ? FP64CTX_SIZE : FP32CTX_SIZE) /* * The following macros are especially useful for __asm__ @@ -265,7 +265,7 @@ struct fp64ctx /* * TX39 Series */ -#define CP0_TX39_CACHE $7 +#define CP0_TX39_CACHE $7 /* * Coprocessor 1 (FPU) register names @@ -332,38 +332,38 @@ struct fp64ctx /* Why doesn't stupidity hurt ... */ -#define PM_1K 0x00000000 -#define PM_4K 0x00001800 -#define PM_16K 0x00007800 -#define PM_64K 0x0001f800 -#define PM_256K 0x0007f800 +#define PM_1K 0x00000000 +#define PM_4K 0x00001800 +#define PM_16K 0x00007800 +#define PM_64K 0x0001f800 +#define PM_256K 0x0007f800 #else -#define PM_4K 0x00000000 -#define PM_16K 0x00006000 -#define PM_64K 0x0001e000 -#define PM_256K 0x0007e000 -#define PM_1M 0x001fe000 -#define PM_4M 0x007fe000 -#define PM_16M 0x01ffe000 -#define PM_64M 0x07ffe000 -#define PM_256M 0x1fffe000 +#define PM_4K 0x00000000 +#define PM_16K 0x00006000 +#define PM_64K 0x0001e000 +#define PM_256K 0x0007e000 +#define PM_1M 0x001fe000 +#define PM_4M 0x007fe000 +#define PM_16M 0x01ffe000 +#define PM_64M 0x07ffe000 +#define PM_256M 0x1fffe000 #endif /* * Values used for computation of new tlb entries */ -#define PL_4K 12 -#define PL_16K 14 -#define PL_64K 16 -#define PL_256K 18 -#define PL_1M 20 -#define PL_4M 22 -#define PL_16M 24 -#define PL_64M 26 -#define PL_256M 28 +#define PL_4K 12 +#define PL_16K 14 +#define PL_64K 16 +#define PL_256K 18 +#define PL_1M 20 +#define PL_4M 22 +#define PL_16M 24 +#define PL_64M 26 +#define PL_256M 28 /* * R4x00 interrupt enable / cause bits @@ -392,234 +392,234 @@ struct fp64ctx /* * Bitfields in the R4xx0 cp0 status register */ -#define ST0_IE 0x00000001 -#define ST0_EXL 0x00000002 -#define ST0_ERL 0x00000004 -#define ST0_KSU 0x00000018 -# define KSU_USER 0x00000010 -# define KSU_SUPERVISOR 0x00000008 -# define KSU_KERNEL 0x00000000 -#define ST0_UX 0x00000020 -#define ST0_SX 0x00000040 -#define ST0_KX 0x00000080 -#define ST0_DE 0x00010000 -#define ST0_CE 0x00020000 +#define ST0_IE 0x00000001 +#define ST0_EXL 0x00000002 +#define ST0_ERL 0x00000004 +#define ST0_KSU 0x00000018 +# define KSU_USER 0x00000010 +# define KSU_SUPERVISOR 0x00000008 +# define KSU_KERNEL 0x00000000 +#define ST0_UX 0x00000020 +#define ST0_SX 0x00000040 +#define ST0_KX 0x00000080 +#define ST0_DE 0x00010000 +#define ST0_CE 0x00020000 /* * Bitfields in the R[23]000 cp0 status register. */ #define ST0_IEC 0x00000001 -#define ST0_KUC 0x00000002 -#define ST0_IEP 0x00000004 -#define ST0_KUP 0x00000008 -#define ST0_IEO 0x00000010 -#define ST0_KUO 0x00000020 +#define ST0_KUC 0x00000002 +#define ST0_IEP 0x00000004 +#define ST0_KUP 0x00000008 +#define ST0_IEO 0x00000010 +#define ST0_KUO 0x00000020 /* bits 6 & 7 are reserved on R[23]000 */ -#define ST0_ISC 0x00010000 -#define ST0_SWC 0x00020000 -#define ST0_CM 0x00080000 +#define ST0_ISC 0x00010000 +#define ST0_SWC 0x00020000 +#define ST0_CM 0x00080000 /* * Bits specific to the R4640/R4650 */ -#define ST0_UM (_ULCAST_(1) << 4) -#define ST0_IL (_ULCAST_(1) << 23) -#define ST0_DL (_ULCAST_(1) << 24) +#define ST0_UM (_ULCAST_(1) << 4) +#define ST0_IL (_ULCAST_(1) << 23) +#define ST0_DL (_ULCAST_(1) << 24) /* * Bitfields in the TX39 family CP0 Configuration Register 3 */ -#define TX39_CONF_ICS_SHIFT 19 -#define TX39_CONF_ICS_MASK 0x00380000 -#define TX39_CONF_ICS_1KB 0x00000000 -#define TX39_CONF_ICS_2KB 0x00080000 -#define TX39_CONF_ICS_4KB 0x00100000 -#define TX39_CONF_ICS_8KB 0x00180000 -#define TX39_CONF_ICS_16KB 0x00200000 - -#define TX39_CONF_DCS_SHIFT 16 -#define TX39_CONF_DCS_MASK 0x00070000 -#define TX39_CONF_DCS_1KB 0x00000000 -#define TX39_CONF_DCS_2KB 0x00010000 -#define TX39_CONF_DCS_4KB 0x00020000 -#define TX39_CONF_DCS_8KB 0x00030000 -#define TX39_CONF_DCS_16KB 0x00040000 - -#define TX39_CONF_CWFON 0x00004000 -#define TX39_CONF_WBON 0x00002000 -#define TX39_CONF_RF_SHIFT 10 -#define TX39_CONF_RF_MASK 0x00000c00 -#define TX39_CONF_DOZE 0x00000200 -#define TX39_CONF_HALT 0x00000100 -#define TX39_CONF_LOCK 0x00000080 -#define TX39_CONF_ICE 0x00000020 -#define TX39_CONF_DCE 0x00000010 -#define TX39_CONF_IRSIZE_SHIFT 2 -#define TX39_CONF_IRSIZE_MASK 0x0000000c -#define TX39_CONF_DRSIZE_SHIFT 0 -#define TX39_CONF_DRSIZE_MASK 0x00000003 +#define TX39_CONF_ICS_SHIFT 19 +#define TX39_CONF_ICS_MASK 0x00380000 +#define TX39_CONF_ICS_1KB 0x00000000 +#define TX39_CONF_ICS_2KB 0x00080000 +#define TX39_CONF_ICS_4KB 0x00100000 +#define TX39_CONF_ICS_8KB 0x00180000 +#define TX39_CONF_ICS_16KB 0x00200000 + +#define TX39_CONF_DCS_SHIFT 16 +#define TX39_CONF_DCS_MASK 0x00070000 +#define TX39_CONF_DCS_1KB 0x00000000 +#define TX39_CONF_DCS_2KB 0x00010000 +#define TX39_CONF_DCS_4KB 0x00020000 +#define TX39_CONF_DCS_8KB 0x00030000 +#define TX39_CONF_DCS_16KB 0x00040000 + +#define TX39_CONF_CWFON 0x00004000 +#define TX39_CONF_WBON 0x00002000 +#define TX39_CONF_RF_SHIFT 10 +#define TX39_CONF_RF_MASK 0x00000c00 +#define TX39_CONF_DOZE 0x00000200 +#define TX39_CONF_HALT 0x00000100 +#define TX39_CONF_LOCK 0x00000080 +#define TX39_CONF_ICE 0x00000020 +#define TX39_CONF_DCE 0x00000010 +#define TX39_CONF_IRSIZE_SHIFT 2 +#define TX39_CONF_IRSIZE_MASK 0x0000000c +#define TX39_CONF_DRSIZE_SHIFT 0 +#define TX39_CONF_DRSIZE_MASK 0x00000003 /* * Status register bits available in all MIPS CPUs. */ -#define ST0_IM 0x0000ff00 -#define STATUSB_IP0 8 -#define STATUSF_IP0 (_ULCAST_(1) << 8) -#define STATUSB_IP1 9 -#define STATUSF_IP1 (_ULCAST_(1) << 9) -#define STATUSB_IP2 10 -#define STATUSF_IP2 (_ULCAST_(1) << 10) -#define STATUSB_IP3 11 -#define STATUSF_IP3 (_ULCAST_(1) << 11) -#define STATUSB_IP4 12 -#define STATUSF_IP4 (_ULCAST_(1) << 12) -#define STATUSB_IP5 13 -#define STATUSF_IP5 (_ULCAST_(1) << 13) -#define STATUSB_IP6 14 -#define STATUSF_IP6 (_ULCAST_(1) << 14) -#define STATUSB_IP7 15 -#define STATUSF_IP7 (_ULCAST_(1) << 15) -#define STATUSB_IP8 0 -#define STATUSF_IP8 (_ULCAST_(1) << 0) -#define STATUSB_IP9 1 -#define STATUSF_IP9 (_ULCAST_(1) << 1) -#define STATUSB_IP10 2 -#define STATUSF_IP10 (_ULCAST_(1) << 2) -#define STATUSB_IP11 3 -#define STATUSF_IP11 (_ULCAST_(1) << 3) -#define STATUSB_IP12 4 -#define STATUSF_IP12 (_ULCAST_(1) << 4) -#define STATUSB_IP13 5 -#define STATUSF_IP13 (_ULCAST_(1) << 5) -#define STATUSB_IP14 6 -#define STATUSF_IP14 (_ULCAST_(1) << 6) -#define STATUSB_IP15 7 -#define STATUSF_IP15 (_ULCAST_(1) << 7) -#define ST0_CH 0x00040000 -#define ST0_SR 0x00100000 -#define ST0_TS 0x00200000 -#define ST0_BEV 0x00400000 -#define ST0_RE 0x02000000 -#define ST0_FR 0x04000000 -#define ST0_CU 0xf0000000 -#define ST0_CU0 0x10000000 -#define ST0_CU1 0x20000000 -#define ST0_CU1_SHIFT 29 -#define ST0_CU2 0x40000000 -#define ST0_CU3 0x80000000 -#define ST0_XX 0x80000000 /* MIPS IV naming */ +#define ST0_IM 0x0000ff00 +#define STATUSB_IP0 8 +#define STATUSF_IP0 (_ULCAST_(1) << 8) +#define STATUSB_IP1 9 +#define STATUSF_IP1 (_ULCAST_(1) << 9) +#define STATUSB_IP2 10 +#define STATUSF_IP2 (_ULCAST_(1) << 10) +#define STATUSB_IP3 11 +#define STATUSF_IP3 (_ULCAST_(1) << 11) +#define STATUSB_IP4 12 +#define STATUSF_IP4 (_ULCAST_(1) << 12) +#define STATUSB_IP5 13 +#define STATUSF_IP5 (_ULCAST_(1) << 13) +#define STATUSB_IP6 14 +#define STATUSF_IP6 (_ULCAST_(1) << 14) +#define STATUSB_IP7 15 +#define STATUSF_IP7 (_ULCAST_(1) << 15) +#define STATUSB_IP8 0 +#define STATUSF_IP8 (_ULCAST_(1) << 0) +#define STATUSB_IP9 1 +#define STATUSF_IP9 (_ULCAST_(1) << 1) +#define STATUSB_IP10 2 +#define STATUSF_IP10 (_ULCAST_(1) << 2) +#define STATUSB_IP11 3 +#define STATUSF_IP11 (_ULCAST_(1) << 3) +#define STATUSB_IP12 4 +#define STATUSF_IP12 (_ULCAST_(1) << 4) +#define STATUSB_IP13 5 +#define STATUSF_IP13 (_ULCAST_(1) << 5) +#define STATUSB_IP14 6 +#define STATUSF_IP14 (_ULCAST_(1) << 6) +#define STATUSB_IP15 7 +#define STATUSF_IP15 (_ULCAST_(1) << 7) +#define ST0_CH 0x00040000 +#define ST0_SR 0x00100000 +#define ST0_TS 0x00200000 +#define ST0_BEV 0x00400000 +#define ST0_RE 0x02000000 +#define ST0_FR 0x04000000 +#define ST0_CU 0xf0000000 +#define ST0_CU0 0x10000000 +#define ST0_CU1 0x20000000 +#define ST0_CU1_SHIFT 29 +#define ST0_CU2 0x40000000 +#define ST0_CU3 0x80000000 +#define ST0_XX 0x80000000 /* MIPS IV naming */ /* * Bitfields and bit numbers in the coprocessor 0 cause register. * * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. */ -#define CAUSEB_EXCCODE 2 -#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) -#define CAUSEB_IP 8 -#define CAUSEF_IP (_ULCAST_(255) << 8) -#define CAUSEB_IP0 8 -#define CAUSEF_IP0 (_ULCAST_(1) << 8) -#define CAUSEB_IP1 9 -#define CAUSEF_IP1 (_ULCAST_(1) << 9) -#define CAUSEB_IP2 10 -#define CAUSEF_IP2 (_ULCAST_(1) << 10) -#define CAUSEB_IP3 11 -#define CAUSEF_IP3 (_ULCAST_(1) << 11) -#define CAUSEB_IP4 12 -#define CAUSEF_IP4 (_ULCAST_(1) << 12) -#define CAUSEB_IP5 13 -#define CAUSEF_IP5 (_ULCAST_(1) << 13) -#define CAUSEB_IP6 14 -#define CAUSEF_IP6 (_ULCAST_(1) << 14) -#define CAUSEB_IP7 15 -#define CAUSEF_IP7 (_ULCAST_(1) << 15) -#define CAUSEB_IV 23 -#define CAUSEF_IV (_ULCAST_(1) << 23) -#define CAUSEB_CE 28 -#define CAUSEF_CE (_ULCAST_(3) << 28) -#define CAUSEB_BD 31 -#define CAUSEF_BD (_ULCAST_(1) << 31) +#define CAUSEB_EXCCODE 2 +#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) +#define CAUSEB_IP 8 +#define CAUSEF_IP (_ULCAST_(255) << 8) +#define CAUSEB_IP0 8 +#define CAUSEF_IP0 (_ULCAST_(1) << 8) +#define CAUSEB_IP1 9 +#define CAUSEF_IP1 (_ULCAST_(1) << 9) +#define CAUSEB_IP2 10 +#define CAUSEF_IP2 (_ULCAST_(1) << 10) +#define CAUSEB_IP3 11 +#define CAUSEF_IP3 (_ULCAST_(1) << 11) +#define CAUSEB_IP4 12 +#define CAUSEF_IP4 (_ULCAST_(1) << 12) +#define CAUSEB_IP5 13 +#define CAUSEF_IP5 (_ULCAST_(1) << 13) +#define CAUSEB_IP6 14 +#define CAUSEF_IP6 (_ULCAST_(1) << 14) +#define CAUSEB_IP7 15 +#define CAUSEF_IP7 (_ULCAST_(1) << 15) +#define CAUSEB_IV 23 +#define CAUSEF_IV (_ULCAST_(1) << 23) +#define CAUSEB_CE 28 +#define CAUSEF_CE (_ULCAST_(3) << 28) +#define CAUSEB_BD 31 +#define CAUSEF_BD (_ULCAST_(1) << 31) /* * Bits in the coprocessor 0 config register. */ /* Generic bits. */ -#define CONF_CM_CACHABLE_NO_WA 0 -#define CONF_CM_CACHABLE_WA 1 -#define CONF_CM_UNCACHED 2 -#define CONF_CM_CACHABLE_NONCOHERENT 3 -#define CONF_CM_CACHABLE_CE 4 -#define CONF_CM_CACHABLE_COW 5 -#define CONF_CM_CACHABLE_CUW 6 -#define CONF_CM_CACHABLE_ACCELERATED 7 -#define CONF_CM_CMASK 7 -#define CONF_BE (_ULCAST_(1) << 15) +#define CONF_CM_CACHABLE_NO_WA 0 +#define CONF_CM_CACHABLE_WA 1 +#define CONF_CM_UNCACHED 2 +#define CONF_CM_CACHABLE_NONCOHERENT 3 +#define CONF_CM_CACHABLE_CE 4 +#define CONF_CM_CACHABLE_COW 5 +#define CONF_CM_CACHABLE_CUW 6 +#define CONF_CM_CACHABLE_ACCELERATED 7 +#define CONF_CM_CMASK 7 +#define CONF_BE (_ULCAST_(1) << 15) /* Bits common to various processors. */ -#define CONF_CU (_ULCAST_(1) << 3) -#define CONF_DB (_ULCAST_(1) << 4) -#define CONF_IB (_ULCAST_(1) << 5) -#define CONF_DC (_ULCAST_(7) << 6) -#define CONF_IC (_ULCAST_(7) << 9) -#define CONF_EB (_ULCAST_(1) << 13) -#define CONF_EM (_ULCAST_(1) << 14) -#define CONF_SM (_ULCAST_(1) << 16) -#define CONF_SC (_ULCAST_(1) << 17) -#define CONF_EW (_ULCAST_(3) << 18) -#define CONF_EP (_ULCAST_(15)<< 24) -#define CONF_EC (_ULCAST_(7) << 28) -#define CONF_CM (_ULCAST_(1) << 31) +#define CONF_CU (_ULCAST_(1) << 3) +#define CONF_DB (_ULCAST_(1) << 4) +#define CONF_IB (_ULCAST_(1) << 5) +#define CONF_DC (_ULCAST_(7) << 6) +#define CONF_IC (_ULCAST_(7) << 9) +#define CONF_EB (_ULCAST_(1) << 13) +#define CONF_EM (_ULCAST_(1) << 14) +#define CONF_SM (_ULCAST_(1) << 16) +#define CONF_SC (_ULCAST_(1) << 17) +#define CONF_EW (_ULCAST_(3) << 18) +#define CONF_EP (_ULCAST_(15)<< 24) +#define CONF_EC (_ULCAST_(7) << 28) +#define CONF_CM (_ULCAST_(1) << 31) /* Bits specific to the R4xx0. */ -#define R4K_CONF_SW (_ULCAST_(1) << 20) -#define R4K_CONF_SS (_ULCAST_(1) << 21) -#define R4K_CONF_SB (_ULCAST_(3) << 22) +#define R4K_CONF_SW (_ULCAST_(1) << 20) +#define R4K_CONF_SS (_ULCAST_(1) << 21) +#define R4K_CONF_SB (_ULCAST_(3) << 22) /* Bits specific to the R5000. */ -#define R5K_CONF_SE (_ULCAST_(1) << 12) -#define R5K_CONF_SS (_ULCAST_(3) << 20) +#define R5K_CONF_SE (_ULCAST_(1) << 12) +#define R5K_CONF_SS (_ULCAST_(3) << 20) /* Bits specific to the R10000. */ -#define R10K_CONF_DN (_ULCAST_(3) << 3) -#define R10K_CONF_CT (_ULCAST_(1) << 5) -#define R10K_CONF_PE (_ULCAST_(1) << 6) -#define R10K_CONF_PM (_ULCAST_(3) << 7) -#define R10K_CONF_EC (_ULCAST_(15)<< 9) -#define R10K_CONF_SB (_ULCAST_(1) << 13) -#define R10K_CONF_SK (_ULCAST_(1) << 14) -#define R10K_CONF_SS (_ULCAST_(7) << 16) -#define R10K_CONF_SC (_ULCAST_(7) << 19) -#define R10K_CONF_DC (_ULCAST_(7) << 26) -#define R10K_CONF_IC (_ULCAST_(7) << 29) +#define R10K_CONF_DN (_ULCAST_(3) << 3) +#define R10K_CONF_CT (_ULCAST_(1) << 5) +#define R10K_CONF_PE (_ULCAST_(1) << 6) +#define R10K_CONF_PM (_ULCAST_(3) << 7) +#define R10K_CONF_EC (_ULCAST_(15)<< 9) +#define R10K_CONF_SB (_ULCAST_(1) << 13) +#define R10K_CONF_SK (_ULCAST_(1) << 14) +#define R10K_CONF_SS (_ULCAST_(7) << 16) +#define R10K_CONF_SC (_ULCAST_(7) << 19) +#define R10K_CONF_DC (_ULCAST_(7) << 26) +#define R10K_CONF_IC (_ULCAST_(7) << 29) /* Bits specific to the VR41xx. */ -#define VR41_CONF_CS (_ULCAST_(1) << 12) -#define VR41_CONF_M16 (_ULCAST_(1) << 20) -#define VR41_CONF_AD (_ULCAST_(1) << 23) +#define VR41_CONF_CS (_ULCAST_(1) << 12) +#define VR41_CONF_M16 (_ULCAST_(1) << 20) +#define VR41_CONF_AD (_ULCAST_(1) << 23) /* Bits specific to the R30xx. */ -#define R30XX_CONF_FDM (_ULCAST_(1) << 19) -#define R30XX_CONF_REV (_ULCAST_(1) << 22) -#define R30XX_CONF_AC (_ULCAST_(1) << 23) -#define R30XX_CONF_RF (_ULCAST_(1) << 24) -#define R30XX_CONF_HALT (_ULCAST_(1) << 25) -#define R30XX_CONF_FPINT (_ULCAST_(7) << 26) -#define R30XX_CONF_DBR (_ULCAST_(1) << 29) -#define R30XX_CONF_SB (_ULCAST_(1) << 30) -#define R30XX_CONF_LOCK (_ULCAST_(1) << 31) +#define R30XX_CONF_FDM (_ULCAST_(1) << 19) +#define R30XX_CONF_REV (_ULCAST_(1) << 22) +#define R30XX_CONF_AC (_ULCAST_(1) << 23) +#define R30XX_CONF_RF (_ULCAST_(1) << 24) +#define R30XX_CONF_HALT (_ULCAST_(1) << 25) +#define R30XX_CONF_FPINT (_ULCAST_(7) << 26) +#define R30XX_CONF_DBR (_ULCAST_(1) << 29) +#define R30XX_CONF_SB (_ULCAST_(1) << 30) +#define R30XX_CONF_LOCK (_ULCAST_(1) << 31) /* Bits specific to the TX49. */ -#define TX49_CONF_DC (_ULCAST_(1) << 16) -#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ -#define TX49_CONF_HALT (_ULCAST_(1) << 18) -#define TX49_CONF_CWFON (_ULCAST_(1) << 27) +#define TX49_CONF_DC (_ULCAST_(1) << 16) +#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ +#define TX49_CONF_HALT (_ULCAST_(1) << 18) +#define TX49_CONF_CWFON (_ULCAST_(1) << 27) /* Bits specific to the MIPS32/64 PRA. */ -#define MIPS_CONF_MT (_ULCAST_(7) << 7) -#define MIPS_CONF_AR (_ULCAST_(7) << 10) -#define MIPS_CONF_AT (_ULCAST_(3) << 13) -#define MIPS_CONF_M (_ULCAST_(1) << 31) +#define MIPS_CONF_MT (_ULCAST_(7) << 7) +#define MIPS_CONF_AR (_ULCAST_(7) << 10) +#define MIPS_CONF_AT (_ULCAST_(3) << 13) +#define MIPS_CONF_M (_ULCAST_(1) << 31) /* * R10000 performance counter definitions. @@ -632,50 +632,50 @@ struct fp64ctx /* * Events counted by counter #0 */ -#define CE0_CYCLES 0 -#define CE0_INSN_ISSUED 1 -#define CE0_LPSC_ISSUED 2 -#define CE0_S_ISSUED 3 -#define CE0_SC_ISSUED 4 -#define CE0_SC_FAILED 5 -#define CE0_BRANCH_DECODED 6 -#define CE0_QW_WB_SECONDARY 7 -#define CE0_CORRECTED_ECC_ERRORS 8 -#define CE0_ICACHE_MISSES 9 -#define CE0_SCACHE_I_MISSES 10 -#define CE0_SCACHE_I_WAY_MISSPREDICTED 11 -#define CE0_EXT_INTERVENTIONS_REQ 12 -#define CE0_EXT_INVALIDATE_REQ 13 -#define CE0_VIRTUAL_COHERENCY_COND 14 -#define CE0_INSN_GRADUATED 15 +#define CE0_CYCLES 0 +#define CE0_INSN_ISSUED 1 +#define CE0_LPSC_ISSUED 2 +#define CE0_S_ISSUED 3 +#define CE0_SC_ISSUED 4 +#define CE0_SC_FAILED 5 +#define CE0_BRANCH_DECODED 6 +#define CE0_QW_WB_SECONDARY 7 +#define CE0_CORRECTED_ECC_ERRORS 8 +#define CE0_ICACHE_MISSES 9 +#define CE0_SCACHE_I_MISSES 10 +#define CE0_SCACHE_I_WAY_MISSPREDICTED 11 +#define CE0_EXT_INTERVENTIONS_REQ 12 +#define CE0_EXT_INVALIDATE_REQ 13 +#define CE0_VIRTUAL_COHERENCY_COND 14 +#define CE0_INSN_GRADUATED 15 /* * Events counted by counter #1 */ -#define CE1_CYCLES 0 -#define CE1_INSN_GRADUATED 1 -#define CE1_LPSC_GRADUATED 2 -#define CE1_S_GRADUATED 3 -#define CE1_SC_GRADUATED 4 -#define CE1_FP_INSN_GRADUATED 5 -#define CE1_QW_WB_PRIMARY 6 -#define CE1_TLB_REFILL 7 -#define CE1_BRANCH_MISSPREDICTED 8 -#define CE1_DCACHE_MISS 9 -#define CE1_SCACHE_D_MISSES 10 -#define CE1_SCACHE_D_WAY_MISSPREDICTED 11 -#define CE1_EXT_INTERVENTION_HITS 12 -#define CE1_EXT_INVALIDATE_REQ 13 -#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14 -#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15 +#define CE1_CYCLES 0 +#define CE1_INSN_GRADUATED 1 +#define CE1_LPSC_GRADUATED 2 +#define CE1_S_GRADUATED 3 +#define CE1_SC_GRADUATED 4 +#define CE1_FP_INSN_GRADUATED 5 +#define CE1_QW_WB_PRIMARY 6 +#define CE1_TLB_REFILL 7 +#define CE1_BRANCH_MISSPREDICTED 8 +#define CE1_DCACHE_MISS 9 +#define CE1_SCACHE_D_MISSES 10 +#define CE1_SCACHE_D_WAY_MISSPREDICTED 11 +#define CE1_EXT_INTERVENTION_HITS 12 +#define CE1_EXT_INVALIDATE_REQ 13 +#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14 +#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15 /* * These flags define in which priviledge mode the counters count events */ -#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */ -#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */ -#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */ -#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */ +#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */ +#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */ +#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */ +#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */ #ifndef __ASSEMBLY__ @@ -713,272 +713,272 @@ struct fp64ctx * Macros to access the system control coprocessor */ -#define __read_32bit_c0_register(source, sel) \ -({ int __res; \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mfc0\t%0, " #source "\n\t" \ - : "=r" (__res)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mfc0\t%0, " #source ", " #sel "\n\t" \ - ".set\tmips0\n\t" \ - : "=r" (__res)); \ - __res; \ +#define __read_32bit_c0_register(source, sel) \ +({ int __res; \ + if (sel == 0) \ + __asm__ __volatile__( \ + "mfc0\t%0, " #source "\n\t" \ + : "=r" (__res)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips32\n\t" \ + "mfc0\t%0, " #source ", " #sel "\n\t" \ + ".set\tmips0\n\t" \ + : "=r" (__res)); \ + __res; \ }) -#define __read_64bit_c0_register(source, sel) \ -({ unsigned long __res; \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips3\n\t" \ - "dmfc0\t%0, " #source "\n\t" \ - ".set\tmips0" \ - : "=r" (__res)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmfc0\t%0, " #source ", " #sel "\n\t" \ - ".set\tmips0" \ - : "=r" (__res)); \ - __res; \ +#define __read_64bit_c0_register(source, sel) \ +({ unsigned long __res; \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips3\n\t" \ + "dmfc0\t%0, " #source "\n\t" \ + ".set\tmips0" \ + : "=r" (__res)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmfc0\t%0, " #source ", " #sel "\n\t" \ + ".set\tmips0" \ + : "=r" (__res)); \ + __res; \ }) -#define __write_32bit_c0_register(register, sel, value) \ -do { \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mtc0\t%z0, " #register "\n\t" \ - : : "Jr" (value)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mtc0\t%z0, " #register ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "Jr" (value)); \ +#define __write_32bit_c0_register(register, sel, value) \ +do { \ + if (sel == 0) \ + __asm__ __volatile__( \ + "mtc0\t%z0, " #register "\n\t" \ + : : "Jr" (value)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips32\n\t" \ + "mtc0\t%z0, " #register ", " #sel "\n\t" \ + ".set\tmips0" \ + : : "Jr" (value)); \ } while (0) -#define __write_64bit_c0_register(register, sel, value) \ -do { \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips3\n\t" \ - "dmtc0\t%z0, " #register "\n\t" \ - ".set\tmips0" \ - : : "Jr" (value)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmtc0\t%z0, " #register ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "Jr" (value)); \ +#define __write_64bit_c0_register(register, sel, value) \ +do { \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips3\n\t" \ + "dmtc0\t%z0, " #register "\n\t" \ + ".set\tmips0" \ + : : "Jr" (value)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmtc0\t%z0, " #register ", " #sel "\n\t" \ + ".set\tmips0" \ + : : "Jr" (value)); \ } while (0) -#define __read_ulong_c0_register(reg, sel) \ - ((sizeof(unsigned long) == 4) ? \ - __read_32bit_c0_register(reg, sel) : \ - __read_64bit_c0_register(reg, sel)) - -#define __write_ulong_c0_register(reg, sel, val) \ -do { \ - if (sizeof(unsigned long) == 4) \ - __write_32bit_c0_register(reg, sel, val); \ - else \ - __write_64bit_c0_register(reg, sel, val); \ +#define __read_ulong_c0_register(reg, sel) \ + ((sizeof(unsigned long) == 4) ? \ + __read_32bit_c0_register(reg, sel) : \ + __read_64bit_c0_register(reg, sel)) + +#define __write_ulong_c0_register(reg, sel, val) \ +do { \ + if (sizeof(unsigned long) == 4) \ + __write_32bit_c0_register(reg, sel, val); \ + else \ + __write_64bit_c0_register(reg, sel, val); \ } while (0) /* * These versions are only needed for systems with more than 38 bits of * physical address space running the 32-bit kernel. That's none atm :-) */ -#define __read_64bit_c0_split(source, sel) \ -({ \ - unsigned long long val; \ - unsigned long flags; \ - \ - local_irq_save(flags); \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmfc0\t%M0, " #source "\n\t" \ - "dsll\t%L0, %M0, 32\n\t" \ - "dsrl\t%M0, %M0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - ".set\tmips0" \ - : "=r" (val)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmfc0\t%M0, " #source ", " #sel "\n\t" \ - "dsll\t%L0, %M0, 32\n\t" \ - "dsrl\t%M0, %M0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - ".set\tmips0" \ - : "=r" (val)); \ - local_irq_restore(flags); \ - \ - val; \ +#define __read_64bit_c0_split(source, sel) \ +({ \ + unsigned long long val; \ + unsigned long flags; \ + \ + local_irq_save(flags); \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmfc0\t%M0, " #source "\n\t" \ + "dsll\t%L0, %M0, 32\n\t" \ + "dsrl\t%M0, %M0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + ".set\tmips0" \ + : "=r" (val)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmfc0\t%M0, " #source ", " #sel "\n\t" \ + "dsll\t%L0, %M0, 32\n\t" \ + "dsrl\t%M0, %M0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + ".set\tmips0" \ + : "=r" (val)); \ + local_irq_restore(flags); \ + \ + val; \ }) -#define __write_64bit_c0_split(source, sel, val) \ -do { \ - unsigned long flags; \ - \ - local_irq_save(flags); \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dsll\t%L0, %L0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - "dsll\t%M0, %M0, 32\n\t" \ - "or\t%L0, %L0, %M0\n\t" \ - "dmtc0\t%L0, " #source "\n\t" \ - ".set\tmips0" \ - : : "r" (val)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dsll\t%L0, %L0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - "dsll\t%M0, %M0, 32\n\t" \ - "or\t%L0, %L0, %M0\n\t" \ - "dmtc0\t%L0, " #source ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "r" (val)); \ - local_irq_restore(flags); \ +#define __write_64bit_c0_split(source, sel, val) \ +do { \ + unsigned long flags; \ + \ + local_irq_save(flags); \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dsll\t%L0, %L0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + "dsll\t%M0, %M0, 32\n\t" \ + "or\t%L0, %L0, %M0\n\t" \ + "dmtc0\t%L0, " #source "\n\t" \ + ".set\tmips0" \ + : : "r" (val)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dsll\t%L0, %L0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + "dsll\t%M0, %M0, 32\n\t" \ + "or\t%L0, %L0, %M0\n\t" \ + "dmtc0\t%L0, " #source ", " #sel "\n\t" \ + ".set\tmips0" \ + : : "r" (val)); \ + local_irq_restore(flags); \ } while (0) -#define read_c0_index() __read_32bit_c0_register($0, 0) -#define write_c0_index(val) __write_32bit_c0_register($0, 0, val) +#define read_c0_index() __read_32bit_c0_register($0, 0) +#define write_c0_index(val) __write_32bit_c0_register($0, 0, val) -#define read_c0_entrylo0() __read_ulong_c0_register($2, 0) -#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) +#define read_c0_entrylo0() __read_ulong_c0_register($2, 0) +#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) -#define read_c0_entrylo1() __read_ulong_c0_register($3, 0) -#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) +#define read_c0_entrylo1() __read_ulong_c0_register($3, 0) +#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) -#define read_c0_conf() __read_32bit_c0_register($3, 0) -#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) +#define read_c0_conf() __read_32bit_c0_register($3, 0) +#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) -#define read_c0_context() __read_ulong_c0_register($4, 0) -#define write_c0_context(val) __write_ulong_c0_register($4, 0, val) +#define read_c0_context() __read_ulong_c0_register($4, 0) +#define write_c0_context(val) __write_ulong_c0_register($4, 0, val) -#define read_c0_pagemask() __read_32bit_c0_register($5, 0) -#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) +#define read_c0_pagemask() __read_32bit_c0_register($5, 0) +#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) -#define read_c0_wired() __read_32bit_c0_register($6, 0) -#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) +#define read_c0_wired() __read_32bit_c0_register($6, 0) +#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) -#define read_c0_info() __read_32bit_c0_register($7, 0) +#define read_c0_info() __read_32bit_c0_register($7, 0) -#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ -#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) +#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ +#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) -#define read_c0_count() __read_32bit_c0_register($9, 0) -#define write_c0_count(val) __write_32bit_c0_register($9, 0, val) +#define read_c0_count() __read_32bit_c0_register($9, 0) +#define write_c0_count(val) __write_32bit_c0_register($9, 0, val) -#define read_c0_entryhi() __read_ulong_c0_register($10, 0) -#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) +#define read_c0_entryhi() __read_ulong_c0_register($10, 0) +#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) -#define read_c0_compare() __read_32bit_c0_register($11, 0) -#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) +#define read_c0_compare() __read_32bit_c0_register($11, 0) +#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) -#define read_c0_status() __read_32bit_c0_register($12, 0) -#define write_c0_status(val) __write_32bit_c0_register($12, 0, val) +#define read_c0_status() __read_32bit_c0_register($12, 0) +#define write_c0_status(val) __write_32bit_c0_register($12, 0, val) -#define read_c0_cause() __read_32bit_c0_register($13, 0) -#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) +#define read_c0_cause() __read_32bit_c0_register($13, 0) +#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) -#define read_c0_prid() __read_32bit_c0_register($15, 0) +#define read_c0_prid() __read_32bit_c0_register($15, 0) -#define read_c0_config() __read_32bit_c0_register($16, 0) -#define read_c0_config1() __read_32bit_c0_register($16, 1) -#define read_c0_config2() __read_32bit_c0_register($16, 2) -#define read_c0_config3() __read_32bit_c0_register($16, 3) -#define write_c0_config(val) __write_32bit_c0_register($16, 0, val) -#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) -#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) -#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) +#define read_c0_config() __read_32bit_c0_register($16, 0) +#define read_c0_config1() __read_32bit_c0_register($16, 1) +#define read_c0_config2() __read_32bit_c0_register($16, 2) +#define read_c0_config3() __read_32bit_c0_register($16, 3) +#define write_c0_config(val) __write_32bit_c0_register($16, 0, val) +#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) +#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) +#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) /* * The WatchLo register. There may be upto 8 of them. */ -#define read_c0_watchlo0() __read_ulong_c0_register($18, 0) -#define read_c0_watchlo1() __read_ulong_c0_register($18, 1) -#define read_c0_watchlo2() __read_ulong_c0_register($18, 2) -#define read_c0_watchlo3() __read_ulong_c0_register($18, 3) -#define read_c0_watchlo4() __read_ulong_c0_register($18, 4) -#define read_c0_watchlo5() __read_ulong_c0_register($18, 5) -#define read_c0_watchlo6() __read_ulong_c0_register($18, 6) -#define read_c0_watchlo7() __read_ulong_c0_register($18, 7) -#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) -#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) -#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) -#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) -#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) -#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) -#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) -#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) +#define read_c0_watchlo0() __read_ulong_c0_register($18, 0) +#define read_c0_watchlo1() __read_ulong_c0_register($18, 1) +#define read_c0_watchlo2() __read_ulong_c0_register($18, 2) +#define read_c0_watchlo3() __read_ulong_c0_register($18, 3) +#define read_c0_watchlo4() __read_ulong_c0_register($18, 4) +#define read_c0_watchlo5() __read_ulong_c0_register($18, 5) +#define read_c0_watchlo6() __read_ulong_c0_register($18, 6) +#define read_c0_watchlo7() __read_ulong_c0_register($18, 7) +#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) +#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) +#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) +#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) +#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) +#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) +#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) +#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) /* * The WatchHi register. There may be upto 8 of them. */ -#define read_c0_watchhi0() __read_32bit_c0_register($19, 0) -#define read_c0_watchhi1() __read_32bit_c0_register($19, 1) -#define read_c0_watchhi2() __read_32bit_c0_register($19, 2) -#define read_c0_watchhi3() __read_32bit_c0_register($19, 3) -#define read_c0_watchhi4() __read_32bit_c0_register($19, 4) -#define read_c0_watchhi5() __read_32bit_c0_register($19, 5) -#define read_c0_watchhi6() __read_32bit_c0_register($19, 6) -#define read_c0_watchhi7() __read_32bit_c0_register($19, 7) - -#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) -#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) -#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) -#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) -#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) -#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) -#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) -#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) - -#define read_c0_xcontext() __read_ulong_c0_register($20, 0) -#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) - -#define read_c0_intcontrol() __read_32bit_c0_register($20, 1) +#define read_c0_watchhi0() __read_32bit_c0_register($19, 0) +#define read_c0_watchhi1() __read_32bit_c0_register($19, 1) +#define read_c0_watchhi2() __read_32bit_c0_register($19, 2) +#define read_c0_watchhi3() __read_32bit_c0_register($19, 3) +#define read_c0_watchhi4() __read_32bit_c0_register($19, 4) +#define read_c0_watchhi5() __read_32bit_c0_register($19, 5) +#define read_c0_watchhi6() __read_32bit_c0_register($19, 6) +#define read_c0_watchhi7() __read_32bit_c0_register($19, 7) + +#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) +#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) +#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) +#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) +#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) +#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) +#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) +#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) + +#define read_c0_xcontext() __read_ulong_c0_register($20, 0) +#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) + +#define read_c0_intcontrol() __read_32bit_c0_register($20, 1) #define write_c0_intcontrol(val) __write_32bit_c0_register($20, 1, val) -#define read_c0_framemask() __read_32bit_c0_register($21, 0) -#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) +#define read_c0_framemask() __read_32bit_c0_register($21, 0) +#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) -#define read_c0_debug() __read_32bit_c0_register($23, 0) -#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) +#define read_c0_debug() __read_32bit_c0_register($23, 0) +#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) -#define read_c0_depc() __read_ulong_c0_register($24, 0) -#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) +#define read_c0_depc() __read_ulong_c0_register($24, 0) +#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) -#define read_c0_ecc() __read_32bit_c0_register($26, 0) -#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) +#define read_c0_ecc() __read_32bit_c0_register($26, 0) +#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) -#define read_c0_derraddr0() __read_ulong_c0_register($26, 1) -#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) +#define read_c0_derraddr0() __read_ulong_c0_register($26, 1) +#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) -#define read_c0_cacheerr() __read_32bit_c0_register($27, 0) +#define read_c0_cacheerr() __read_32bit_c0_register($27, 0) -#define read_c0_derraddr1() __read_ulong_c0_register($27, 1) -#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) +#define read_c0_derraddr1() __read_ulong_c0_register($27, 1) +#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) -#define read_c0_taglo() __read_32bit_c0_register($28, 0) -#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) +#define read_c0_taglo() __read_32bit_c0_register($28, 0) +#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) -#define read_c0_taghi() __read_32bit_c0_register($29, 0) -#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) +#define read_c0_taghi() __read_32bit_c0_register($29, 0) +#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) -#define read_c0_errorepc() __read_ulong_c0_register($30, 0) -#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) +#define read_c0_errorepc() __read_ulong_c0_register($30, 0) +#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) -#define read_c0_epc() __read_ulong_c0_register($14, 0) -#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) +#define read_c0_epc() __read_ulong_c0_register($14, 0) +#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) #if 1 /* @@ -987,20 +987,20 @@ do { \ #define read_32bit_cp0_register(source) \ ({ int __res; \ __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ "mfc0\t%0,"STR(source)"\n\t" \ - ".set\tpop" \ + ".set\tpop" \ : "=r" (__res)); \ __res;}) #define read_32bit_cp0_set1_register(source) \ ({ int __res; \ __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ "cfc0\t%0,"STR(source)"\n\t" \ - ".set\tpop" \ + ".set\tpop" \ : "=r" (__res)); \ __res;}) @@ -1018,14 +1018,14 @@ do { \ #define write_32bit_cp0_register(register,value) \ __asm__ __volatile__( \ - "mtc0\t%0,"STR(register)"\n\t" \ - "nop" \ + "mtc0\t%0,"STR(register)"\n\t" \ + "nop" \ : : "r" (value)); #define write_32bit_cp0_set1_register(register,value) \ __asm__ __volatile__( \ - "ctc0\t%0,"STR(register)"\n\t" \ - "nop" \ + "ctc0\t%0,"STR(register)"\n\t" \ + "nop" \ : : "r" (value)); #define write_64bit_cp0_register(register,value) \ @@ -1041,16 +1041,16 @@ do { \ #define read_mips32_cp0_config1() \ ({ int __res; \ __asm__ __volatile__( \ - ".set\tnoreorder\n\t" \ - ".set\tnoat\n\t" \ - "#.set\tmips64\n\t" \ - "#mfc0\t$1, $16, 1\n\t" \ - "#.set\tmips0\n\t" \ - ".word\t0x40018001\n\t" \ - "move\t%0,$1\n\t" \ - ".set\tat\n\t" \ - ".set\treorder" \ - :"=r" (__res)); \ + ".set\tnoreorder\n\t" \ + ".set\tnoat\n\t" \ + "#.set\tmips64\n\t" \ + "#mfc0\t$1, $16, 1\n\t" \ + "#.set\tmips0\n\t" \ + ".word\t0x40018001\n\t" \ + "move\t%0,$1\n\t" \ + ".set\tat\n\t" \ + ".set\treorder" \ + :"=r" (__res)); \ __res;}) #endif @@ -1059,95 +1059,95 @@ do { \ */ #define read_32bit_cp1_register(source) \ ({ int __res; \ - __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ + __asm__ __volatile__( \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ "cfc1\t%0,"STR(source)"\n\t" \ - ".set\tpop" \ + ".set\tpop" \ : "=r" (__res)); \ __res;}) /* TLB operations. */ static inline void tlb_probe(void) { - __asm__ __volatile__( - ".set noreorder\n\t" - "tlbp\n\t" - ".set reorder"); + __asm__ __volatile__( + ".set noreorder\n\t" + "tlbp\n\t" + ".set reorder"); } static inline void tlb_read(void) { - __asm__ __volatile__( - ".set noreorder\n\t" - "tlbr\n\t" - ".set reorder"); + __asm__ __volatile__( + ".set noreorder\n\t" + "tlbr\n\t" + ".set reorder"); } static inline void tlb_write_indexed(void) { - __asm__ __volatile__( - ".set noreorder\n\t" - "tlbwi\n\t" - ".set reorder"); + __asm__ __volatile__( + ".set noreorder\n\t" + "tlbwi\n\t" + ".set reorder"); } static inline void tlb_write_random(void) { - __asm__ __volatile__( - ".set noreorder\n\t" - "tlbwr\n\t" - ".set reorder"); + __asm__ __volatile__( + ".set noreorder\n\t" + "tlbwr\n\t" + ".set reorder"); } /* * Manipulate bits in a c0 register. */ -#define __BUILD_SET_C0(name,register) \ -static inline unsigned int \ -set_c0_##name(unsigned int set) \ -{ \ - unsigned int res; \ - \ - res = read_c0_##name(); \ - res |= set; \ - write_c0_##name(res); \ - \ - return res; \ -} \ - \ -static inline unsigned int \ -clear_c0_##name(unsigned int clear) \ -{ \ - unsigned int res; \ - \ - res = read_c0_##name(); \ - res &= ~clear; \ - write_c0_##name(res); \ - \ - return res; \ -} \ - \ -static inline unsigned int \ -change_c0_##name(unsigned int change, unsigned int new) \ -{ \ - unsigned int res; \ - \ - res = read_c0_##name(); \ - res &= ~change; \ - res |= (new & change); \ - write_c0_##name(res); \ - \ - return res; \ +#define __BUILD_SET_C0(name,register) \ +static inline unsigned int \ +set_c0_##name(unsigned int set) \ +{ \ + unsigned int res; \ + \ + res = read_c0_##name(); \ + res |= set; \ + write_c0_##name(res); \ + \ + return res; \ +} \ + \ +static inline unsigned int \ +clear_c0_##name(unsigned int clear) \ +{ \ + unsigned int res; \ + \ + res = read_c0_##name(); \ + res &= ~clear; \ + write_c0_##name(res); \ + \ + return res; \ +} \ + \ +static inline unsigned int \ +change_c0_##name(unsigned int change, unsigned int new) \ +{ \ + unsigned int res; \ + \ + res = read_c0_##name(); \ + res &= ~change; \ + res |= (new & change); \ + write_c0_##name(res); \ + \ + return res; \ } __BUILD_SET_C0(status,CP0_STATUS) __BUILD_SET_C0(cause,CP0_CAUSE) __BUILD_SET_C0(config,CP0_CONFIG) -#define set_cp0_status(x) set_c0_status(x) -#define set_cp0_cause(x) set_c0_cause(x) -#define set_cp0_config(x) set_c0_config(x) +#define set_cp0_status(x) set_c0_status(x) +#define set_cp0_cause(x) set_c0_cause(x) +#define set_cp0_config(x) set_c0_config(x) #endif /* !__ASSEMBLY__ */ diff --git a/libcpu/mips/common/mipscfg.h b/libcpu/mips/common/mipscfg.h index b4f30615f8..f4761be73d 100644 --- a/libcpu/mips/common/mipscfg.h +++ b/libcpu/mips/common/mipscfg.h @@ -24,7 +24,7 @@ typedef struct mips32_core_cfg rt_uint16_t dcache_lines_per_way; rt_uint16_t dcache_ways; - rt_uint16_t max_tlb_entries; /* number of tlb entry */ + rt_uint16_t max_tlb_entries; /* number of tlb entry */ } mips32_core_cfg_t; extern mips32_core_cfg_t g_mips_core; diff --git a/libcpu/mips/loongson_1b/cache.c b/libcpu/mips/loongson_1b/cache.c index 842f392cb7..ccfdda95d3 100644 --- a/libcpu/mips/loongson_1b/cache.c +++ b/libcpu/mips/loongson_1b/cache.c @@ -12,12 +12,12 @@ * 2010-07-09 Bernard first version * 2011-08-08 lgnq modified for LS1B */ - + #include #include "../common/mipsregs.h" -#define K0BASE 0x80000000 -#define PRID_LS1B 0x4220 +#define K0BASE 0x80000000 +#define PRID_LS1B 0x4220 extern void Clear_TagLo (void); extern void Invalidate_Icache_Ls1b(unsigned int); @@ -26,21 +26,21 @@ extern void Invalidate_Dcache_Fill_Ls1b(unsigned int); extern void Writeback_Invalidate_Dcache(unsigned int); extern void enable_cpu_cache(void); -typedef struct cacheinfo_t +typedef struct cacheinfo_t { - unsigned int icache_size; - unsigned int dcache_size; - unsigned int icacheline_size; - unsigned int dcacheline_size; + unsigned int icache_size; + unsigned int dcache_size; + unsigned int icacheline_size; + unsigned int dcacheline_size; } cacheinfo_t ; -typedef struct cacheop_t +typedef struct cacheop_t { - void (*Clear_TagLo) (void); - void (*Invalidate_Icache) (unsigned int); - void (*Invalidate_Dcache_Fill) (unsigned int); - void (*Invalidate_Dcache_ClearTag) (unsigned int); - void (*Init_Cache)(void); + void (*Clear_TagLo) (void); + void (*Invalidate_Icache) (unsigned int); + void (*Invalidate_Dcache_Fill) (unsigned int); + void (*Invalidate_Dcache_ClearTag) (unsigned int); + void (*Init_Cache)(void); } cacheop_t ; static cacheop_t cacheop, *pcacheop; @@ -53,24 +53,24 @@ int identify_cpu(void) pcacheop = &cacheop; pcacheinfo = &cacheinfo; - rt_kprintf("CPU configure: 0x%08x\n", read_c0_config()); + rt_kprintf("CPU configure: 0x%08x\n", read_c0_config()); cpu_id = read_c0_prid(); switch (cpu_id) - { - case PRID_LS1B: - rt_kprintf("CPU:LS1B\n"); - pcacheop->Clear_TagLo = Clear_TagLo; - pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1b; - pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1b; - pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1b; - break; - default: - rt_kprintf("Unknown CPU type, system halted!\n"); - while (1) - { - ; - } - break; + { + case PRID_LS1B: + rt_kprintf("CPU:LS1B\n"); + pcacheop->Clear_TagLo = Clear_TagLo; + pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1b; + pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1b; + pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1b; + break; + default: + rt_kprintf("Unknown CPU type, system halted!\n"); + while (1) + { + ; + } + break; } return 0; @@ -89,7 +89,7 @@ void probe_cache(void) icache_sets = 64 << ((config1 >> 22) & 7); icache_ways = 1 + ((config1 >> 16) & 7); icache_size = icache_sets * icache_ways * icache_line_size; - + if ((dcache_line_size = ((config1 >> 10) & 7))) dcache_line_size = 2 << dcache_line_size; else @@ -97,7 +97,7 @@ void probe_cache(void) dcache_sets = 64 << ((config1 >> 13) & 7); dcache_ways = 1 + ((config1 >> 7) & 7); dcache_size = dcache_sets * dcache_ways * dcache_line_size; - + rt_kprintf("DCache %2dkb, linesize %d bytes.\n", dcache_size >> 10, dcache_line_size); rt_kprintf("ICache %2dkb, linesize %d bytes.\n", icache_size >> 10, icache_line_size); @@ -111,120 +111,120 @@ void probe_cache(void) void invalidate_writeback_dcache_all(void) { - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->dcache_size); - - while (start < end) - { - Writeback_Invalidate_Dcache(start); //hit writeback invalidate - start += pcacheinfo->dcacheline_size; - } + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->dcache_size); + + while (start < end) + { + Writeback_Invalidate_Dcache(start); //hit writeback invalidate + start += pcacheinfo->dcacheline_size; + } } void invalidate_writeback_dcache(unsigned long addr, int size) { - unsigned long start, end; - - start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size); - end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size); - - while (start dcacheline_size; - } + unsigned long start, end; + + start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size); + end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size); + + while (start dcacheline_size; + } } void invalidate_icache_all(void) { - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->icache_size); - - while (start < end) - { - pcacheop->Invalidate_Icache(start); - start += pcacheinfo->icacheline_size; - } + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->icache_size); + + while (start < end) + { + pcacheop->Invalidate_Icache(start); + start += pcacheinfo->icacheline_size; + } } void invalidate_dcache_all(void) -{ - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->dcache_size); - while (start icacheline_size; - } +{ + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->dcache_size); + while (start icacheline_size; + } } //with cache disabled void init_dcache(void) { - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->dcache_size); + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->dcache_size); - while (start < end) - { - pcacheop->Invalidate_Dcache_ClearTag(start); - start += pcacheinfo->dcacheline_size; - } + while (start < end) + { + pcacheop->Invalidate_Dcache_ClearTag(start); + start += pcacheinfo->dcacheline_size; + } } void rt_hw_cache_init(void) { unsigned int start, end; - - /* 1. identify cpu and probe cache */ - identify_cpu(); - probe_cache(); - start = K0BASE; - end = (start + pcacheinfo->icache_size); + /* 1. identify cpu and probe cache */ + identify_cpu(); + probe_cache(); + + start = K0BASE; + end = (start + pcacheinfo->icache_size); /* - * 2. clear CP0 taglo/taghi register; + * 2. clear CP0 taglo/taghi register; */ pcacheop->Clear_TagLo(); - /* - * 3. invalidate instruction cache; + /* + * 3. invalidate instruction cache; */ - while (start < end) + while (start < end) { - pcacheop->Invalidate_Icache(start); //index invalidate icache - start += pcacheinfo->icacheline_size; + pcacheop->Invalidate_Icache(start); //index invalidate icache + start += pcacheinfo->icacheline_size; } /* - * 4. invalidate data cache; + * 4. invalidate data cache; */ start = K0BASE; end = (start + pcacheinfo->dcache_size); - while(start < end) + while(start < end) { - pcacheop->Invalidate_Dcache_ClearTag(start); - start += pcacheinfo->dcacheline_size; + pcacheop->Invalidate_Dcache_ClearTag(start); + start += pcacheinfo->dcacheline_size; } start = K0BASE; - while(start < end) + while(start < end) { - pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache - start += pcacheinfo->dcacheline_size; + pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache + start += pcacheinfo->dcacheline_size; } start = K0BASE; - while(start < end) + while(start < end) { - pcacheop->Invalidate_Dcache_ClearTag(start); - start += pcacheinfo->dcacheline_size; + pcacheop->Invalidate_Dcache_ClearTag(start); + start += pcacheinfo->dcacheline_size; } - /* enable cache */ - enable_cpu_cache(); - rt_kprintf("enable cpu cache done\n"); + /* enable cache */ + enable_cpu_cache(); + rt_kprintf("enable cpu cache done\n"); - return ; + return ; } diff --git a/libcpu/mips/loongson_1b/cache.h b/libcpu/mips/loongson_1b/cache.h index b5c2d4501e..8ca015ef4f 100644 --- a/libcpu/mips/loongson_1b/cache.h +++ b/libcpu/mips/loongson_1b/cache.h @@ -12,8 +12,8 @@ * 2010-07-09 Bernard first version * 2011-08-08 lgnq modified for LS1B */ -#ifndef __CACHE_H__ -#define __CACHE_H__ +#ifndef __CACHE_H__ +#define __CACHE_H__ /* * Cache Operations @@ -22,31 +22,31 @@ #define Index_Writeback_Inv_D 0x01 #define Index_Invalidate_SI 0x02 #define Index_Writeback_Inv_SD 0x03 -#define Index_Load_Tag_I 0x04 -#define Index_Load_Tag_D 0x05 -#define Index_Load_Tag_SI 0x06 -#define Index_Load_Tag_SD 0x07 -#define Index_Store_Tag_I 0x08 -#define Index_Store_Tag_D 0x09 -#define Index_Store_Tag_SI 0x0A -#define Index_Store_Tag_SD 0x0B -#define Create_Dirty_Excl_D 0x0d -#define Create_Dirty_Excl_SD 0x0f -#define Hit_Invalidate_I 0x10 -#define Hit_Invalidate_D 0x11 -#define Hit_Invalidate_SI 0x12 -#define Hit_Invalidate_SD 0x13 -#define Fill 0x14 -#define Hit_Writeback_Inv_D 0x15 +#define Index_Load_Tag_I 0x04 +#define Index_Load_Tag_D 0x05 +#define Index_Load_Tag_SI 0x06 +#define Index_Load_Tag_SD 0x07 +#define Index_Store_Tag_I 0x08 +#define Index_Store_Tag_D 0x09 +#define Index_Store_Tag_SI 0x0A +#define Index_Store_Tag_SD 0x0B +#define Create_Dirty_Excl_D 0x0d +#define Create_Dirty_Excl_SD 0x0f +#define Hit_Invalidate_I 0x10 +#define Hit_Invalidate_D 0x11 +#define Hit_Invalidate_SI 0x12 +#define Hit_Invalidate_SD 0x13 +#define Fill 0x14 +#define Hit_Writeback_Inv_D 0x15 /* 0x16 is unused */ -#define Hit_Writeback_Inv_SD 0x17 -#define Hit_Writeback_I 0x18 -#define Hit_Writeback_D 0x19 +#define Hit_Writeback_Inv_SD 0x17 +#define Hit_Writeback_I 0x18 +#define Hit_Writeback_D 0x19 /* 0x1a is unused */ -#define Hit_Writeback_SD 0x1b +#define Hit_Writeback_SD 0x1b /* 0x1c is unused */ /* 0x1e is unused */ -#define Hit_Set_Virtual_SI 0x1e -#define Hit_Set_Virtual_SD 0x1f +#define Hit_Set_Virtual_SI 0x1e +#define Hit_Set_Virtual_SD 0x1f #endif diff --git a/libcpu/mips/loongson_1b/cpuport.c b/libcpu/mips/loongson_1b/cpuport.c index c095c04814..23399800f5 100644 --- a/libcpu/mips/loongson_1b/cpuport.c +++ b/libcpu/mips/loongson_1b/cpuport.c @@ -28,13 +28,13 @@ */ void rt_hw_cpu_reset(void) { - /* open the watch-dog */ - WDT_EN = 0x01; /* watch dog enable */ - WDT_TIMER = 0x01; /* watch dog will be timeout after 1 tick */ - WDT_SET = 0x01; /* watch dog start */ + /* open the watch-dog */ + WDT_EN = 0x01; /* watch dog enable */ + WDT_TIMER = 0x01; /* watch dog will be timeout after 1 tick */ + WDT_SET = 0x01; /* watch dog start */ - rt_kprintf("reboot system...\n"); - while (1); + rt_kprintf("reboot system...\n"); + while (1); } /** @@ -43,9 +43,9 @@ void rt_hw_cpu_reset(void) */ void rt_hw_cpu_shutdown(void) { - rt_kprintf("shutdown...\n"); + rt_kprintf("shutdown...\n"); - while (1); + while (1); } extern rt_uint32_t cp0_get_cause(void); @@ -65,59 +65,59 @@ extern rt_uint32_t cp0_get_lo(void); */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) { - rt_uint32_t *stk; + rt_uint32_t *stk; static rt_uint32_t g_sr = 0; if (g_sr == 0) { - g_sr = cp0_get_status(); - g_sr &= 0xfffffffe; - g_sr |= 0x8401; + g_sr = cp0_get_status(); + g_sr &= 0xfffffffe; + g_sr |= 0x8401; } /** Start at stack top */ stk = (rt_uint32_t *)stack_addr; - *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */ - *(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */ - *(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */ - *(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */ - *(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */ - *(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */ - *(--stk) = (rt_uint32_t) texit; /* ra */ - *(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */ - *(--stk) = (rt_uint32_t) stack_addr; /* sp */ - *(--stk) = (rt_uint32_t) 0x0000001c; /* gp */ - *(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */ - *(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */ - *(--stk) = (rt_uint32_t) 0x00000019; /* t9 */ - *(--stk) = (rt_uint32_t) 0x00000018; /* t8 */ - *(--stk) = (rt_uint32_t) 0x00000017; /* s7 */ - *(--stk) = (rt_uint32_t) 0x00000016; /* s6 */ - *(--stk) = (rt_uint32_t) 0x00000015; /* s5 */ - *(--stk) = (rt_uint32_t) 0x00000014; /* s4 */ - *(--stk) = (rt_uint32_t) 0x00000013; /* s3 */ - *(--stk) = (rt_uint32_t) 0x00000012; /* s2 */ - *(--stk) = (rt_uint32_t) 0x00000011; /* s1 */ - *(--stk) = (rt_uint32_t) 0x00000010; /* s0 */ - *(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */ - *(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */ - *(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */ - *(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */ - *(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */ - *(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */ - *(--stk) = (rt_uint32_t) 0x00000009; /* t1 */ - *(--stk) = (rt_uint32_t) 0x00000008; /* t0 */ - *(--stk) = (rt_uint32_t) 0x00000007; /* a3 */ - *(--stk) = (rt_uint32_t) 0x00000006; /* a2 */ - *(--stk) = (rt_uint32_t) 0x00000005; /* a1 */ - *(--stk) = (rt_uint32_t) parameter; /* a0 */ - *(--stk) = (rt_uint32_t) 0x00000003; /* v1 */ - *(--stk) = (rt_uint32_t) 0x00000002; /* v0 */ - *(--stk) = (rt_uint32_t) 0x00000001; /* at */ - *(--stk) = (rt_uint32_t) 0x00000000; /* zero */ + *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */ + *(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */ + *(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */ + *(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */ + *(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */ + *(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */ + *(--stk) = (rt_uint32_t) texit; /* ra */ + *(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */ + *(--stk) = (rt_uint32_t) stack_addr; /* sp */ + *(--stk) = (rt_uint32_t) 0x0000001c; /* gp */ + *(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */ + *(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */ + *(--stk) = (rt_uint32_t) 0x00000019; /* t9 */ + *(--stk) = (rt_uint32_t) 0x00000018; /* t8 */ + *(--stk) = (rt_uint32_t) 0x00000017; /* s7 */ + *(--stk) = (rt_uint32_t) 0x00000016; /* s6 */ + *(--stk) = (rt_uint32_t) 0x00000015; /* s5 */ + *(--stk) = (rt_uint32_t) 0x00000014; /* s4 */ + *(--stk) = (rt_uint32_t) 0x00000013; /* s3 */ + *(--stk) = (rt_uint32_t) 0x00000012; /* s2 */ + *(--stk) = (rt_uint32_t) 0x00000011; /* s1 */ + *(--stk) = (rt_uint32_t) 0x00000010; /* s0 */ + *(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */ + *(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */ + *(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */ + *(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */ + *(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */ + *(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */ + *(--stk) = (rt_uint32_t) 0x00000009; /* t1 */ + *(--stk) = (rt_uint32_t) 0x00000008; /* t0 */ + *(--stk) = (rt_uint32_t) 0x00000007; /* a3 */ + *(--stk) = (rt_uint32_t) 0x00000006; /* a2 */ + *(--stk) = (rt_uint32_t) 0x00000005; /* a1 */ + *(--stk) = (rt_uint32_t) parameter; /* a0 */ + *(--stk) = (rt_uint32_t) 0x00000003; /* v1 */ + *(--stk) = (rt_uint32_t) 0x00000002; /* v0 */ + *(--stk) = (rt_uint32_t) 0x00000001; /* at */ + *(--stk) = (rt_uint32_t) 0x00000000; /* zero */ - /* return task's current stack address */ - return (rt_uint8_t *)stk; + /* return task's current stack address */ + return (rt_uint8_t *)stk; } /*@}*/ diff --git a/libcpu/mips/loongson_1b/exception.c b/libcpu/mips/loongson_1b/exception.c index 4a3745cbc5..dbcec42ab6 100644 --- a/libcpu/mips/loongson_1b/exception.c +++ b/libcpu/mips/loongson_1b/exception.c @@ -25,7 +25,7 @@ /** * exception handle table */ -#define RT_EXCEPTION_MAX 8 +#define RT_EXCEPTION_MAX 8 exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX]; /** @@ -47,45 +47,45 @@ exception_func_t rt_set_except_vector(int n, exception_func_t func) void tlb_refill_handler(void) { - rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc()); - rt_hw_cpu_shutdown(); + rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc()); + rt_hw_cpu_shutdown(); } void cache_error_handler(void) { - rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc()); - rt_hw_cpu_shutdown(); + rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc()); + rt_hw_cpu_shutdown(); } static void unhandled_exception_handle(pt_regs_t *regs) { - rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause()); + rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause()); } void install_default_execpt_handle(void) { - rt_int32_t i; + rt_int32_t i; - for (i=0; i> 8; - - for (index = RT_EXCEPTION_MAX; index > 0; index --) - { - if (cause & (1 << index)) - { - sys_exception_handlers[index](regs); - cause &= ~(1 << index); - } - } + rt_uint32_t cause; + rt_uint32_t index; + + cause = (read_c0_cause() & read_c0_config()); + cause = (cause & 0xfc00) >> 8; + + for (index = RT_EXCEPTION_MAX; index > 0; index --) + { + if (cause & (1 << index)) + { + sys_exception_handlers[index](regs); + cause &= ~(1 << index); + } + } } /*@}*/ diff --git a/libcpu/mips/loongson_1b/interrupt.c b/libcpu/mips/loongson_1b/interrupt.c index 998d1e4918..4af9319c55 100644 --- a/libcpu/mips/loongson_1b/interrupt.c +++ b/libcpu/mips/loongson_1b/interrupt.c @@ -51,7 +51,7 @@ void rt_hw_interrupt_init(void) rt_int32_t idx; /* pci active low */ - ls1b_hw0_icregs->int_pol = -1; //must be done here 20110802 lgnq + ls1b_hw0_icregs->int_pol = -1; //must be done here 20110802 lgnq /* make all interrupts level triggered */ (ls1b_hw0_icregs+0)->int_edge = 0x0000e000; /* mask all interrupts */ diff --git a/libcpu/mips/loongson_1b/ls1b.h b/libcpu/mips/loongson_1b/ls1b.h index 34393a3448..3dab7f9da2 100644 --- a/libcpu/mips/loongson_1b/ls1b.h +++ b/libcpu/mips/loongson_1b/ls1b.h @@ -1,7 +1,7 @@ /* * File : ls1b.h * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2011, RT-Thread Develop Team + * COPYRIGHT (C) 2006-2021, RT-Thread Develop Team * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at @@ -17,35 +17,35 @@ #include "../common/mipsregs.h" -#define LS1B_ACPI_IRQ 0 -#define LS1B_HPET_IRQ 1 -#define LS1B_UART0_IRQ 2 -#define LS1B_UART1_IRQ 3 -#define LS1B_UART2_IRQ 4 -#define LS1B_UART3_IRQ 5 -#define LS1B_CAN0_IRQ 6 -#define LS1B_CAN1_IRQ 7 -#define LS1B_SPI0_IRQ 8 -#define LS1B_SPI1_IRQ 9 -#define LS1B_AC97_IRQ 10 -#define LS1B_MS_IRQ 11 -#define LS1B_KB_IRQ 12 -#define LS1B_DMA0_IRQ 13 -#define LS1B_DMA1_IRQ 14 -#define LS1B_NAND_IRQ 15 -#define LS1B_I2C0_IRQ 16 -#define LS1B_I2C1_IRQ 17 -#define LS1B_PWM0_IRQ 18 -#define LS1B_PWM1_IRQ 19 -#define LS1B_PWM2_IRQ 20 -#define LS1B_PWM3_IRQ 21 -#define LS1B_LPC_IRQ 22 -#define LS1B_EHCI_IRQ 32 -#define LS1B_OHCI_IRQ 33 -#define LS1B_GMAC1_IRQ 34 -#define LS1B_GMAC2_IRQ 35 -#define LS1B_SATA_IRQ 36 -#define LS1B_GPU_IRQ 37 +#define LS1B_ACPI_IRQ 0 +#define LS1B_HPET_IRQ 1 +#define LS1B_UART0_IRQ 2 +#define LS1B_UART1_IRQ 3 +#define LS1B_UART2_IRQ 4 +#define LS1B_UART3_IRQ 5 +#define LS1B_CAN0_IRQ 6 +#define LS1B_CAN1_IRQ 7 +#define LS1B_SPI0_IRQ 8 +#define LS1B_SPI1_IRQ 9 +#define LS1B_AC97_IRQ 10 +#define LS1B_MS_IRQ 11 +#define LS1B_KB_IRQ 12 +#define LS1B_DMA0_IRQ 13 +#define LS1B_DMA1_IRQ 14 +#define LS1B_NAND_IRQ 15 +#define LS1B_I2C0_IRQ 16 +#define LS1B_I2C1_IRQ 17 +#define LS1B_PWM0_IRQ 18 +#define LS1B_PWM1_IRQ 19 +#define LS1B_PWM2_IRQ 20 +#define LS1B_PWM3_IRQ 21 +#define LS1B_LPC_IRQ 22 +#define LS1B_EHCI_IRQ 32 +#define LS1B_OHCI_IRQ 33 +#define LS1B_GMAC1_IRQ 34 +#define LS1B_GMAC2_IRQ 35 +#define LS1B_SATA_IRQ 36 +#define LS1B_GPU_IRQ 37 #define LS1B_PCI_INTA_IRQ 38 #define LS1B_PCI_INTB_IRQ 39 #define LS1B_PCI_INTC_IRQ 40 @@ -56,13 +56,13 @@ #define LS1B_GPIO_IRQ_COUNT 96 #define LS1B_GPIO_LAST_IRQ (LS1B_GPIO_FIRST_IRQ + LS1B_GPIO_IRQ_COUNT-1) -#define INT_PCI_INTA (1<<6) -#define INT_PCI_INTB (1<<7) -#define INT_PCI_INTC (1<<8) -#define INT_PCI_INTD (1<<9) +#define INT_PCI_INTA (1<<6) +#define INT_PCI_INTB (1<<7) +#define INT_PCI_INTC (1<<8) +#define INT_PCI_INTD (1<<9) #define LS1B_LAST_IRQ 159 -#define MIPS_CPU_TIMER_IRQ 167 +#define MIPS_CPU_TIMER_IRQ 167 #define LS1B_INTREG_BASE 0xbfd01040 #define LS1B_DMA_IRQ_BASE 168 @@ -70,71 +70,71 @@ struct ls1b_intc_regs { - volatile unsigned int int_isr; - volatile unsigned int int_en; - volatile unsigned int int_set; - volatile unsigned int int_clr; /* offset 0x10*/ - volatile unsigned int int_pol; - volatile unsigned int int_edge; /* offset 0 */ -}; + volatile unsigned int int_isr; + volatile unsigned int int_en; + volatile unsigned int int_set; + volatile unsigned int int_clr; /* offset 0x10*/ + volatile unsigned int int_pol; + volatile unsigned int int_edge; /* offset 0 */ +}; struct ls1b_cop_global_regs { - volatile unsigned int control; - volatile unsigned int rd_inten; - volatile unsigned int wr_inten; - volatile unsigned int rd_intisr; /* offset 0x10*/ - volatile unsigned int wr_intisr; - unsigned int unused[11]; -} ; + volatile unsigned int control; + volatile unsigned int rd_inten; + volatile unsigned int wr_inten; + volatile unsigned int rd_intisr; /* offset 0x10*/ + volatile unsigned int wr_intisr; + unsigned int unused[11]; +} ; struct ls1b_cop_channel_regs { - volatile unsigned int rd_control; - volatile unsigned int rd_src; - volatile unsigned int rd_cnt; - volatile unsigned int rd_status; /* offset 0x10*/ - volatile unsigned int wr_control; - volatile unsigned int wr_src; - volatile unsigned int wr_cnt; - volatile unsigned int wr_status; /* offset 0x10*/ -} ; + volatile unsigned int rd_control; + volatile unsigned int rd_src; + volatile unsigned int rd_cnt; + volatile unsigned int rd_status; /* offset 0x10*/ + volatile unsigned int wr_control; + volatile unsigned int wr_src; + volatile unsigned int wr_cnt; + volatile unsigned int wr_status; /* offset 0x10*/ +} ; struct ls1b_cop_regs { - struct ls1b_cop_global_regs global; - struct ls1b_cop_channel_regs chan[8][2]; + struct ls1b_cop_global_regs global; + struct ls1b_cop_channel_regs chan[8][2]; } ; -#define __REG8(addr) *((volatile unsigned char *)(addr)) -#define __REG16(addr) *((volatile unsigned short *)(addr)) -#define __REG32(addr) *((volatile unsigned int *)(addr)) - -#define GMAC0_BASE 0xBFE10000 -#define GMAC0_DMA_BASE 0xBFE11000 -#define GMAC1_BASE 0xBFE20000 -#define GMAC1_DMA_BASE 0xBFE21000 -#define I2C0_BASE 0xBFE58000 -#define PWM0_BASE 0xBFE5C000 -#define PWM1_BASE 0xBFE5C010 -#define PWM2_BASE 0xBFE5C020 -#define PWM3_BASE 0xBFE5C030 -#define WDT_BASE 0xBFE5C060 -#define RTC_BASE 0xBFE64000 -#define I2C1_BASE 0xBFE68000 -#define I2C2_BASE 0xBFE70000 -#define AC97_BASE 0xBFE74000 -#define NAND_BASE 0xBFE78000 -#define SPI_BASE 0xBFE80000 -#define CAN1_BASE 0xBF004300 -#define CAN0_BASE 0xBF004400 +#define __REG8(addr) *((volatile unsigned char *)(addr)) +#define __REG16(addr) *((volatile unsigned short *)(addr)) +#define __REG32(addr) *((volatile unsigned int *)(addr)) + +#define GMAC0_BASE 0xBFE10000 +#define GMAC0_DMA_BASE 0xBFE11000 +#define GMAC1_BASE 0xBFE20000 +#define GMAC1_DMA_BASE 0xBFE21000 +#define I2C0_BASE 0xBFE58000 +#define PWM0_BASE 0xBFE5C000 +#define PWM1_BASE 0xBFE5C010 +#define PWM2_BASE 0xBFE5C020 +#define PWM3_BASE 0xBFE5C030 +#define WDT_BASE 0xBFE5C060 +#define RTC_BASE 0xBFE64000 +#define I2C1_BASE 0xBFE68000 +#define I2C2_BASE 0xBFE70000 +#define AC97_BASE 0xBFE74000 +#define NAND_BASE 0xBFE78000 +#define SPI_BASE 0xBFE80000 +#define CAN1_BASE 0xBF004300 +#define CAN0_BASE 0xBF004400 /* Watch Dog registers */ -#define WDT_EN __REG32(WDT_BASE + 0x00) -#define WDT_SET __REG32(WDT_BASE + 0x04) -#define WDT_TIMER __REG32(WDT_BASE + 0x08) +#define WDT_EN __REG32(WDT_BASE + 0x00) +#define WDT_SET __REG32(WDT_BASE + 0x04) +#define WDT_TIMER __REG32(WDT_BASE + 0x08) -#define PLL_FREQ __REG32(0xbfe78030) -#define PLL_DIV_PARAM __REG32(0xbfe78034) +#define PLL_FREQ __REG32(0xbfe78030) +#define PLL_DIV_PARAM __REG32(0xbfe78034) #endif diff --git a/libcpu/mips/loongson_1b/mipscfg.c b/libcpu/mips/loongson_1b/mipscfg.c index 10dd3fee9e..73e9efd965 100644 --- a/libcpu/mips/loongson_1b/mipscfg.c +++ b/libcpu/mips/loongson_1b/mipscfg.c @@ -17,18 +17,18 @@ mips32_core_cfg_t g_mips_core = { - 16, /* icache_line_size */ - 256, /* icache_lines_per_way */ - 4, /* icache_ways */ - 16, /* dcache_line_size */ - 256, /* dcache_lines_per_way */ - 4, /* dcache_ways */ - 16, /* max_tlb_entries */ + 16, /* icache_line_size */ + 256, /* icache_lines_per_way */ + 4, /* icache_ways */ + 16, /* dcache_line_size */ + 256, /* dcache_lines_per_way */ + 4, /* dcache_ways */ + 16, /* max_tlb_entries */ }; static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) { - rt_uint16_t rets = 1; + rt_uint16_t rets = 1; while (n--) rets *= b; @@ -38,7 +38,7 @@ static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) static rt_uint16_t m_log2(rt_uint16_t b) { - rt_uint16_t rets = 0; + rt_uint16_t rets = 0; while (b != 1) { @@ -54,29 +54,29 @@ static rt_uint16_t m_log2(rt_uint16_t b) */ void mips32_cfg_init(void) { - rt_uint16_t val; - rt_uint32_t cp0_config1; + rt_uint16_t val; + rt_uint32_t cp0_config1; - cp0_config1 = read_c0_config(); - if (cp0_config1 & 0x80000000) - { - cp0_config1 = read_c0_config1(); + cp0_config1 = read_c0_config(); + if (cp0_config1 & 0x80000000) + { + cp0_config1 = read_c0_config1(); - val = (cp0_config1 & (7<<22))>>22; - g_mips_core.icache_lines_per_way = 64 * m_pow(2, val); - val = (cp0_config1 & (7<<19))>>19; - g_mips_core.icache_line_size = 2 * m_pow(2, val); - val = (cp0_config1 & (7<<16))>>16; - g_mips_core.icache_ways = val + 1; + val = (cp0_config1 & (7<<22))>>22; + g_mips_core.icache_lines_per_way = 64 * m_pow(2, val); + val = (cp0_config1 & (7<<19))>>19; + g_mips_core.icache_line_size = 2 * m_pow(2, val); + val = (cp0_config1 & (7<<16))>>16; + g_mips_core.icache_ways = val + 1; - val = (cp0_config1 & (7<<13))>>13; - g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val); - val = (cp0_config1 & (7<<10))>>10; - g_mips_core.dcache_line_size = 2 * m_pow(2, val); - val = (cp0_config1 & (7<<7))>>7; - g_mips_core.dcache_ways = val + 1; + val = (cp0_config1 & (7<<13))>>13; + g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val); + val = (cp0_config1 & (7<<10))>>10; + g_mips_core.dcache_line_size = 2 * m_pow(2, val); + val = (cp0_config1 & (7<<7))>>7; + g_mips_core.dcache_ways = val + 1; - val = (cp0_config1 & (0x3F<<25))>>25; - g_mips_core.max_tlb_entries = val + 1; - } + val = (cp0_config1 & (0x3F<<25))>>25; + g_mips_core.max_tlb_entries = val + 1; + } } diff --git a/libcpu/mips/loongson_1c/cache.c b/libcpu/mips/loongson_1c/cache.c index bf97db9b4e..c755c0e4e8 100644 --- a/libcpu/mips/loongson_1c/cache.c +++ b/libcpu/mips/loongson_1c/cache.c @@ -13,12 +13,12 @@ * 2011-08-08 lgnq modified for LS1B * 2015-07-08 chinesebear modified for loongson 1c */ - + #include #include "../common/mipsregs.h" -#define K0BASE 0x80000000 -#define PRID_LS1C 0x4220 +#define K0BASE 0x80000000 +#define PRID_LS1C 0x4220 extern void Clear_TagLo (void); extern void Invalidate_Icache_Ls1c(unsigned int); @@ -27,21 +27,21 @@ extern void Invalidate_Dcache_Fill_Ls1c(unsigned int); extern void Writeback_Invalidate_Dcache(unsigned int); extern void enable_cpu_cache(void); -typedef struct cacheinfo_t +typedef struct cacheinfo_t { - unsigned int icache_size; - unsigned int dcache_size; - unsigned int icacheline_size; - unsigned int dcacheline_size; + unsigned int icache_size; + unsigned int dcache_size; + unsigned int icacheline_size; + unsigned int dcacheline_size; } cacheinfo_t ; -typedef struct cacheop_t +typedef struct cacheop_t { - void (*Clear_TagLo) (void); - void (*Invalidate_Icache) (unsigned int); - void (*Invalidate_Dcache_Fill) (unsigned int); - void (*Invalidate_Dcache_ClearTag) (unsigned int); - void (*Init_Cache)(void); + void (*Clear_TagLo) (void); + void (*Invalidate_Icache) (unsigned int); + void (*Invalidate_Dcache_Fill) (unsigned int); + void (*Invalidate_Dcache_ClearTag) (unsigned int); + void (*Init_Cache)(void); } cacheop_t ; static cacheop_t cacheop, *pcacheop; @@ -54,24 +54,24 @@ int identify_cpu(void) pcacheop = &cacheop; pcacheinfo = &cacheinfo; - rt_kprintf("CPU configure: 0x%08x\n", read_c0_config()); + rt_kprintf("CPU configure: 0x%08x\n", read_c0_config()); cpu_id = read_c0_prid(); switch (cpu_id) - { - case PRID_LS1C: - rt_kprintf("CPU:Loongson 1C\n"); - pcacheop->Clear_TagLo = Clear_TagLo; - pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1c; - pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1c; - pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1c; - break; - default: - rt_kprintf("Unknown CPU type, system halted!\n"); - while (1) - { - ; - } - break; + { + case PRID_LS1C: + rt_kprintf("CPU:Loongson 1C\n"); + pcacheop->Clear_TagLo = Clear_TagLo; + pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1c; + pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1c; + pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1c; + break; + default: + rt_kprintf("Unknown CPU type, system halted!\n"); + while (1) + { + ; + } + break; } return 0; @@ -90,7 +90,7 @@ void probe_cache(void) icache_sets = 64 << ((config1 >> 22) & 7); icache_ways = 1 + ((config1 >> 16) & 7); icache_size = icache_sets * icache_ways * icache_line_size; - + if ((dcache_line_size = ((config1 >> 10) & 7))) dcache_line_size = 2 << dcache_line_size; else @@ -98,7 +98,7 @@ void probe_cache(void) dcache_sets = 64 << ((config1 >> 13) & 7); dcache_ways = 1 + ((config1 >> 7) & 7); dcache_size = dcache_sets * dcache_ways * dcache_line_size; - + rt_kprintf("DCache %2dkb, linesize %d bytes.\n", dcache_size >> 10, dcache_line_size); rt_kprintf("ICache %2dkb, linesize %d bytes.\n", icache_size >> 10, icache_line_size); @@ -112,122 +112,122 @@ void probe_cache(void) void invalidate_writeback_dcache_all(void) { - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->dcache_size); - - while (start < end) - { - Writeback_Invalidate_Dcache(start); //hit writeback invalidate - start += pcacheinfo->dcacheline_size; - } + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->dcache_size); + + while (start < end) + { + Writeback_Invalidate_Dcache(start); //hit writeback invalidate + start += pcacheinfo->dcacheline_size; + } } void invalidate_writeback_dcache(unsigned long addr, int size) { - unsigned long start, end; - - start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size); - end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size); - - while (start dcacheline_size; - } + unsigned long start, end; + + start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size); + end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size); + + while (start dcacheline_size; + } } void invalidate_icache_all(void) { - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->icache_size); - - while (start < end) - { - pcacheop->Invalidate_Icache(start); - start += pcacheinfo->icacheline_size; - } + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->icache_size); + + while (start < end) + { + pcacheop->Invalidate_Icache(start); + start += pcacheinfo->icacheline_size; + } } void invalidate_dcache_all(void) -{ - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->dcache_size); - while (start icacheline_size; - } +{ + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->dcache_size); + while (start icacheline_size; + } } //with cache disabled void init_dcache(void) { - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->dcache_size); + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->dcache_size); - while (start < end) - { - pcacheop->Invalidate_Dcache_ClearTag(start); - start += pcacheinfo->dcacheline_size; - } + while (start < end) + { + pcacheop->Invalidate_Dcache_ClearTag(start); + start += pcacheinfo->dcacheline_size; + } } void rt_hw_cache_init(void) { unsigned int start, end; - - /* 1. identify cpu and probe cache */ - identify_cpu(); - probe_cache(); - start = K0BASE; - end = (start + pcacheinfo->icache_size); + /* 1. identify cpu and probe cache */ + identify_cpu(); + probe_cache(); + + start = K0BASE; + end = (start + pcacheinfo->icache_size); /* - * 2. clear CP0 taglo/taghi register; + * 2. clear CP0 taglo/taghi register; */ pcacheop->Clear_TagLo(); - /* - * 3. invalidate instruction cache; + /* + * 3. invalidate instruction cache; */ - while (start < end) + while (start < end) { - pcacheop->Invalidate_Icache(start); //index invalidate icache - start += pcacheinfo->icacheline_size; + pcacheop->Invalidate_Icache(start); //index invalidate icache + start += pcacheinfo->icacheline_size; } /* - * 4. invalidate data cache; + * 4. invalidate data cache; */ start = K0BASE; end = (start + pcacheinfo->dcache_size); - while(start < end) + while(start < end) { - pcacheop->Invalidate_Dcache_ClearTag(start); - start += pcacheinfo->dcacheline_size; + pcacheop->Invalidate_Dcache_ClearTag(start); + start += pcacheinfo->dcacheline_size; } start = K0BASE; - while(start < end) + while(start < end) { - pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache - start += pcacheinfo->dcacheline_size; + pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache + start += pcacheinfo->dcacheline_size; } start = K0BASE; - while(start < end) + while(start < end) { - pcacheop->Invalidate_Dcache_ClearTag(start); - start += pcacheinfo->dcacheline_size; + pcacheop->Invalidate_Dcache_ClearTag(start); + start += pcacheinfo->dcacheline_size; } - /* enable cache */ - enable_cpu_cache(); - rt_kprintf("enable cpu cache done\n"); + /* enable cache */ + enable_cpu_cache(); + rt_kprintf("enable cpu cache done\n"); - return ; + return ; } diff --git a/libcpu/mips/loongson_1c/cache.h b/libcpu/mips/loongson_1c/cache.h index b5c2d4501e..8ca015ef4f 100644 --- a/libcpu/mips/loongson_1c/cache.h +++ b/libcpu/mips/loongson_1c/cache.h @@ -12,8 +12,8 @@ * 2010-07-09 Bernard first version * 2011-08-08 lgnq modified for LS1B */ -#ifndef __CACHE_H__ -#define __CACHE_H__ +#ifndef __CACHE_H__ +#define __CACHE_H__ /* * Cache Operations @@ -22,31 +22,31 @@ #define Index_Writeback_Inv_D 0x01 #define Index_Invalidate_SI 0x02 #define Index_Writeback_Inv_SD 0x03 -#define Index_Load_Tag_I 0x04 -#define Index_Load_Tag_D 0x05 -#define Index_Load_Tag_SI 0x06 -#define Index_Load_Tag_SD 0x07 -#define Index_Store_Tag_I 0x08 -#define Index_Store_Tag_D 0x09 -#define Index_Store_Tag_SI 0x0A -#define Index_Store_Tag_SD 0x0B -#define Create_Dirty_Excl_D 0x0d -#define Create_Dirty_Excl_SD 0x0f -#define Hit_Invalidate_I 0x10 -#define Hit_Invalidate_D 0x11 -#define Hit_Invalidate_SI 0x12 -#define Hit_Invalidate_SD 0x13 -#define Fill 0x14 -#define Hit_Writeback_Inv_D 0x15 +#define Index_Load_Tag_I 0x04 +#define Index_Load_Tag_D 0x05 +#define Index_Load_Tag_SI 0x06 +#define Index_Load_Tag_SD 0x07 +#define Index_Store_Tag_I 0x08 +#define Index_Store_Tag_D 0x09 +#define Index_Store_Tag_SI 0x0A +#define Index_Store_Tag_SD 0x0B +#define Create_Dirty_Excl_D 0x0d +#define Create_Dirty_Excl_SD 0x0f +#define Hit_Invalidate_I 0x10 +#define Hit_Invalidate_D 0x11 +#define Hit_Invalidate_SI 0x12 +#define Hit_Invalidate_SD 0x13 +#define Fill 0x14 +#define Hit_Writeback_Inv_D 0x15 /* 0x16 is unused */ -#define Hit_Writeback_Inv_SD 0x17 -#define Hit_Writeback_I 0x18 -#define Hit_Writeback_D 0x19 +#define Hit_Writeback_Inv_SD 0x17 +#define Hit_Writeback_I 0x18 +#define Hit_Writeback_D 0x19 /* 0x1a is unused */ -#define Hit_Writeback_SD 0x1b +#define Hit_Writeback_SD 0x1b /* 0x1c is unused */ /* 0x1e is unused */ -#define Hit_Set_Virtual_SI 0x1e -#define Hit_Set_Virtual_SD 0x1f +#define Hit_Set_Virtual_SI 0x1e +#define Hit_Set_Virtual_SD 0x1f #endif diff --git a/libcpu/mips/loongson_1c/cpuport.c b/libcpu/mips/loongson_1c/cpuport.c index 03fdc2a514..147f4882bf 100644 --- a/libcpu/mips/loongson_1c/cpuport.c +++ b/libcpu/mips/loongson_1c/cpuport.c @@ -31,13 +31,13 @@ register rt_uint32_t $GP __asm__ ("$28"); */ void rt_hw_cpu_reset(void) { - /* open the watch-dog */ - WDT_EN = 0x01; /* watch dog enable */ - WDT_TIMER = 0x01; /* watch dog will be timeout after 1 tick */ - WDT_SET = 0x01; /* watch dog start */ + /* open the watch-dog */ + WDT_EN = 0x01; /* watch dog enable */ + WDT_TIMER = 0x01; /* watch dog will be timeout after 1 tick */ + WDT_SET = 0x01; /* watch dog start */ - rt_kprintf("reboot system...\n"); - while (1); + rt_kprintf("reboot system...\n"); + while (1); } /** @@ -46,9 +46,9 @@ void rt_hw_cpu_reset(void) */ void rt_hw_cpu_shutdown(void) { - rt_kprintf("shutdown...\n"); + rt_kprintf("shutdown...\n"); - while (1); + while (1); } extern rt_uint32_t cp0_get_cause(void); @@ -68,73 +68,73 @@ extern rt_uint32_t cp0_get_lo(void); */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) { - rt_uint32_t *stk; + rt_uint32_t *stk; static rt_uint32_t g_sr = 0; - static rt_uint32_t g_gp = 0; + static rt_uint32_t g_gp = 0; if (g_sr == 0) { - g_sr = cp0_get_status(); - g_sr &= 0xfffffffe; - g_sr |= 0x8401; + g_sr = cp0_get_status(); + g_sr &= 0xfffffffe; + g_sr |= 0x8401; - g_gp = $GP; + g_gp = $GP; } /** Start at stack top */ stk = (rt_uint32_t *)stack_addr; - *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */ - *(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */ - *(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */ - *(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */ - *(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */ - *(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */ - *(--stk) = (rt_uint32_t) texit; /* ra */ - *(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */ - *(--stk) = (rt_uint32_t) stack_addr; /* sp */ - *(--stk) = (rt_uint32_t) g_gp; /* gp */ - *(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */ - *(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */ - *(--stk) = (rt_uint32_t) 0x00000019; /* t9 */ - *(--stk) = (rt_uint32_t) 0x00000018; /* t8 */ - *(--stk) = (rt_uint32_t) 0x00000017; /* s7 */ - *(--stk) = (rt_uint32_t) 0x00000016; /* s6 */ - *(--stk) = (rt_uint32_t) 0x00000015; /* s5 */ - *(--stk) = (rt_uint32_t) 0x00000014; /* s4 */ - *(--stk) = (rt_uint32_t) 0x00000013; /* s3 */ - *(--stk) = (rt_uint32_t) 0x00000012; /* s2 */ - *(--stk) = (rt_uint32_t) 0x00000011; /* s1 */ - *(--stk) = (rt_uint32_t) 0x00000010; /* s0 */ - *(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */ - *(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */ - *(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */ - *(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */ - *(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */ - *(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */ - *(--stk) = (rt_uint32_t) 0x00000009; /* t1 */ - *(--stk) = (rt_uint32_t) 0x00000008; /* t0 */ - *(--stk) = (rt_uint32_t) 0x00000007; /* a3 */ - *(--stk) = (rt_uint32_t) 0x00000006; /* a2 */ - *(--stk) = (rt_uint32_t) 0x00000005; /* a1 */ - *(--stk) = (rt_uint32_t) parameter; /* a0 */ - *(--stk) = (rt_uint32_t) 0x00000003; /* v1 */ - *(--stk) = (rt_uint32_t) 0x00000002; /* v0 */ - *(--stk) = (rt_uint32_t) 0x00000001; /* at */ - *(--stk) = (rt_uint32_t) 0x00000000; /* zero */ - - /* return task's current stack address */ - return (rt_uint8_t *)stk; + *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */ + *(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */ + *(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */ + *(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */ + *(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */ + *(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */ + *(--stk) = (rt_uint32_t) texit; /* ra */ + *(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */ + *(--stk) = (rt_uint32_t) stack_addr; /* sp */ + *(--stk) = (rt_uint32_t) g_gp; /* gp */ + *(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */ + *(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */ + *(--stk) = (rt_uint32_t) 0x00000019; /* t9 */ + *(--stk) = (rt_uint32_t) 0x00000018; /* t8 */ + *(--stk) = (rt_uint32_t) 0x00000017; /* s7 */ + *(--stk) = (rt_uint32_t) 0x00000016; /* s6 */ + *(--stk) = (rt_uint32_t) 0x00000015; /* s5 */ + *(--stk) = (rt_uint32_t) 0x00000014; /* s4 */ + *(--stk) = (rt_uint32_t) 0x00000013; /* s3 */ + *(--stk) = (rt_uint32_t) 0x00000012; /* s2 */ + *(--stk) = (rt_uint32_t) 0x00000011; /* s1 */ + *(--stk) = (rt_uint32_t) 0x00000010; /* s0 */ + *(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */ + *(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */ + *(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */ + *(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */ + *(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */ + *(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */ + *(--stk) = (rt_uint32_t) 0x00000009; /* t1 */ + *(--stk) = (rt_uint32_t) 0x00000008; /* t0 */ + *(--stk) = (rt_uint32_t) 0x00000007; /* a3 */ + *(--stk) = (rt_uint32_t) 0x00000006; /* a2 */ + *(--stk) = (rt_uint32_t) 0x00000005; /* a1 */ + *(--stk) = (rt_uint32_t) parameter; /* a0 */ + *(--stk) = (rt_uint32_t) 0x00000003; /* v1 */ + *(--stk) = (rt_uint32_t) 0x00000002; /* v0 */ + *(--stk) = (rt_uint32_t) 0x00000001; /* at */ + *(--stk) = (rt_uint32_t) 0x00000000; /* zero */ + + /* return task's current stack address */ + return (rt_uint8_t *)stk; } #define cache_op(op,addr) \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noreorder \n" \ - " .set mips3\n\t \n" \ - " cache %0, %1 \n" \ - " .set pop \n" \ - : \ - : "i" (op), "R" (*(unsigned char *)(addr))) + __asm__ __volatile__( \ + " .set push \n" \ + " .set noreorder \n" \ + " .set mips3\n\t \n" \ + " cache %0, %1 \n" \ + " .set pop \n" \ + : \ + : "i" (op), "R" (*(unsigned char *)(addr))) #if defined(CONFIG_CPU_LOONGSON2) #define Hit_Invalidate_I 0x00 @@ -148,17 +148,17 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_ad void flush_cache(unsigned long start_addr, unsigned long size) { - unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; - unsigned long addr = start_addr & ~(lsize - 1); - unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); - - while (1) { - cache_op(Hit_Writeback_Inv_D, addr); - cache_op(Hit_Invalidate_I, addr); - if (addr == aend) - break; - addr += lsize; - } + unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; + unsigned long addr = start_addr & ~(lsize - 1); + unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); + + while (1) { + cache_op(Hit_Writeback_Inv_D, addr); + cache_op(Hit_Invalidate_I, addr); + if (addr == aend) + break; + addr += lsize; + } } diff --git a/libcpu/mips/loongson_1c/exception.c b/libcpu/mips/loongson_1c/exception.c index 4a3745cbc5..dbcec42ab6 100644 --- a/libcpu/mips/loongson_1c/exception.c +++ b/libcpu/mips/loongson_1c/exception.c @@ -25,7 +25,7 @@ /** * exception handle table */ -#define RT_EXCEPTION_MAX 8 +#define RT_EXCEPTION_MAX 8 exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX]; /** @@ -47,45 +47,45 @@ exception_func_t rt_set_except_vector(int n, exception_func_t func) void tlb_refill_handler(void) { - rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc()); - rt_hw_cpu_shutdown(); + rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc()); + rt_hw_cpu_shutdown(); } void cache_error_handler(void) { - rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc()); - rt_hw_cpu_shutdown(); + rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc()); + rt_hw_cpu_shutdown(); } static void unhandled_exception_handle(pt_regs_t *regs) { - rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause()); + rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause()); } void install_default_execpt_handle(void) { - rt_int32_t i; + rt_int32_t i; - for (i=0; i> 8; - - for (index = RT_EXCEPTION_MAX; index > 0; index --) - { - if (cause & (1 << index)) - { - sys_exception_handlers[index](regs); - cause &= ~(1 << index); - } - } + rt_uint32_t cause; + rt_uint32_t index; + + cause = (read_c0_cause() & read_c0_config()); + cause = (cause & 0xfc00) >> 8; + + for (index = RT_EXCEPTION_MAX; index > 0; index --) + { + if (cause & (1 << index)) + { + sys_exception_handlers[index](regs); + cause &= ~(1 << index); + } + } } /*@}*/ diff --git a/libcpu/mips/loongson_1c/mipscfg.c b/libcpu/mips/loongson_1c/mipscfg.c index 10dd3fee9e..73e9efd965 100644 --- a/libcpu/mips/loongson_1c/mipscfg.c +++ b/libcpu/mips/loongson_1c/mipscfg.c @@ -17,18 +17,18 @@ mips32_core_cfg_t g_mips_core = { - 16, /* icache_line_size */ - 256, /* icache_lines_per_way */ - 4, /* icache_ways */ - 16, /* dcache_line_size */ - 256, /* dcache_lines_per_way */ - 4, /* dcache_ways */ - 16, /* max_tlb_entries */ + 16, /* icache_line_size */ + 256, /* icache_lines_per_way */ + 4, /* icache_ways */ + 16, /* dcache_line_size */ + 256, /* dcache_lines_per_way */ + 4, /* dcache_ways */ + 16, /* max_tlb_entries */ }; static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) { - rt_uint16_t rets = 1; + rt_uint16_t rets = 1; while (n--) rets *= b; @@ -38,7 +38,7 @@ static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) static rt_uint16_t m_log2(rt_uint16_t b) { - rt_uint16_t rets = 0; + rt_uint16_t rets = 0; while (b != 1) { @@ -54,29 +54,29 @@ static rt_uint16_t m_log2(rt_uint16_t b) */ void mips32_cfg_init(void) { - rt_uint16_t val; - rt_uint32_t cp0_config1; + rt_uint16_t val; + rt_uint32_t cp0_config1; - cp0_config1 = read_c0_config(); - if (cp0_config1 & 0x80000000) - { - cp0_config1 = read_c0_config1(); + cp0_config1 = read_c0_config(); + if (cp0_config1 & 0x80000000) + { + cp0_config1 = read_c0_config1(); - val = (cp0_config1 & (7<<22))>>22; - g_mips_core.icache_lines_per_way = 64 * m_pow(2, val); - val = (cp0_config1 & (7<<19))>>19; - g_mips_core.icache_line_size = 2 * m_pow(2, val); - val = (cp0_config1 & (7<<16))>>16; - g_mips_core.icache_ways = val + 1; + val = (cp0_config1 & (7<<22))>>22; + g_mips_core.icache_lines_per_way = 64 * m_pow(2, val); + val = (cp0_config1 & (7<<19))>>19; + g_mips_core.icache_line_size = 2 * m_pow(2, val); + val = (cp0_config1 & (7<<16))>>16; + g_mips_core.icache_ways = val + 1; - val = (cp0_config1 & (7<<13))>>13; - g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val); - val = (cp0_config1 & (7<<10))>>10; - g_mips_core.dcache_line_size = 2 * m_pow(2, val); - val = (cp0_config1 & (7<<7))>>7; - g_mips_core.dcache_ways = val + 1; + val = (cp0_config1 & (7<<13))>>13; + g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val); + val = (cp0_config1 & (7<<10))>>10; + g_mips_core.dcache_line_size = 2 * m_pow(2, val); + val = (cp0_config1 & (7<<7))>>7; + g_mips_core.dcache_ways = val + 1; - val = (cp0_config1 & (0x3F<<25))>>25; - g_mips_core.max_tlb_entries = val + 1; - } + val = (cp0_config1 & (0x3F<<25))>>25; + g_mips_core.max_tlb_entries = val + 1; + } } diff --git a/libcpu/mips/pic32/cpuport.c b/libcpu/mips/pic32/cpuport.c index 3f08d57167..089f652bce 100644 --- a/libcpu/mips/pic32/cpuport.c +++ b/libcpu/mips/pic32/cpuport.c @@ -45,51 +45,51 @@ rt_uint32_t __attribute__((nomips16)) _get_gp(void) */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) { - rt_uint32_t *stk; + rt_uint32_t *stk; /** Start at stack top */ stk = (rt_uint32_t *)stack_addr; - *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */ - *(--stk) = (rt_uint32_t) 0x00800000; /* c0_cause: IV=1, */ - *(--stk) = (rt_uint32_t) 0; /* c0_badvaddr */ - *(--stk) = (rt_uint32_t) 0; /* lo */ - *(--stk) = (rt_uint32_t) 0; /* hi */ - *(--stk) = (rt_uint32_t) 1; /* C0_SR: IE = En, */ - *(--stk) = (rt_uint32_t) texit; /* 31 ra */ - *(--stk) = (rt_uint32_t) 0x0000001e; /* 30 s8 */ - *(--stk) = (rt_uint32_t) stack_addr; /* 29 sp */ - *(--stk) = (rt_uint32_t) _get_gp(); /* 28 gp */ - *(--stk) = (rt_uint32_t) 0x0000001b; /* 27 k1 */ - *(--stk) = (rt_uint32_t) 0x0000001a; /* 26 k0 */ - *(--stk) = (rt_uint32_t) 0x00000019; /* 25 t9 */ - *(--stk) = (rt_uint32_t) 0x00000018; /* 24 t8 */ - *(--stk) = (rt_uint32_t) 0x00000017; /* 23 s7 */ - *(--stk) = (rt_uint32_t) 0x00000016; /* 22 s6 */ - *(--stk) = (rt_uint32_t) 0x00000015; /* 21 s5 */ - *(--stk) = (rt_uint32_t) 0x00000014; /* 20 s4 */ - *(--stk) = (rt_uint32_t) 0x00000013; /* 19 s3 */ - *(--stk) = (rt_uint32_t) 0x00000012; /* 18 s2 */ - *(--stk) = (rt_uint32_t) 0x00000011; /* 17 s1 */ - *(--stk) = (rt_uint32_t) 0x00000010; /* 16 s0 */ - *(--stk) = (rt_uint32_t) 0x0000000f; /* 15 t7 */ - *(--stk) = (rt_uint32_t) 0x0000000e; /* 14 t6 */ - *(--stk) = (rt_uint32_t) 0x0000000d; /* 13 t5 */ - *(--stk) = (rt_uint32_t) 0x0000000c; /* 12 t4 */ - *(--stk) = (rt_uint32_t) 0x0000000b; /* 11 t3 */ - *(--stk) = (rt_uint32_t) 0x0000000a; /* 10 t2 */ - *(--stk) = (rt_uint32_t) 0x00000009; /* 9 t1 */ - *(--stk) = (rt_uint32_t) 0x00000008; /* 8 t0 */ - *(--stk) = (rt_uint32_t) 0x00000007; /* 7 a3 */ - *(--stk) = (rt_uint32_t) 0x00000006; /* 6 a2 */ - *(--stk) = (rt_uint32_t) 0x00000005; /* 5 a1 */ - *(--stk) = (rt_uint32_t) parameter; /* 4 a0 */ - *(--stk) = (rt_uint32_t) 0x00000003; /* 3 v1 */ - *(--stk) = (rt_uint32_t) 0x00000002; /* 2 v0 */ - *(--stk) = (rt_uint32_t) 0x00000001; /* 1 at */ - *(--stk) = (rt_uint32_t) 0x00000000; /* 0 zero */ + *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */ + *(--stk) = (rt_uint32_t) 0x00800000; /* c0_cause: IV=1, */ + *(--stk) = (rt_uint32_t) 0; /* c0_badvaddr */ + *(--stk) = (rt_uint32_t) 0; /* lo */ + *(--stk) = (rt_uint32_t) 0; /* hi */ + *(--stk) = (rt_uint32_t) 1; /* C0_SR: IE = En, */ + *(--stk) = (rt_uint32_t) texit; /* 31 ra */ + *(--stk) = (rt_uint32_t) 0x0000001e; /* 30 s8 */ + *(--stk) = (rt_uint32_t) stack_addr; /* 29 sp */ + *(--stk) = (rt_uint32_t) _get_gp(); /* 28 gp */ + *(--stk) = (rt_uint32_t) 0x0000001b; /* 27 k1 */ + *(--stk) = (rt_uint32_t) 0x0000001a; /* 26 k0 */ + *(--stk) = (rt_uint32_t) 0x00000019; /* 25 t9 */ + *(--stk) = (rt_uint32_t) 0x00000018; /* 24 t8 */ + *(--stk) = (rt_uint32_t) 0x00000017; /* 23 s7 */ + *(--stk) = (rt_uint32_t) 0x00000016; /* 22 s6 */ + *(--stk) = (rt_uint32_t) 0x00000015; /* 21 s5 */ + *(--stk) = (rt_uint32_t) 0x00000014; /* 20 s4 */ + *(--stk) = (rt_uint32_t) 0x00000013; /* 19 s3 */ + *(--stk) = (rt_uint32_t) 0x00000012; /* 18 s2 */ + *(--stk) = (rt_uint32_t) 0x00000011; /* 17 s1 */ + *(--stk) = (rt_uint32_t) 0x00000010; /* 16 s0 */ + *(--stk) = (rt_uint32_t) 0x0000000f; /* 15 t7 */ + *(--stk) = (rt_uint32_t) 0x0000000e; /* 14 t6 */ + *(--stk) = (rt_uint32_t) 0x0000000d; /* 13 t5 */ + *(--stk) = (rt_uint32_t) 0x0000000c; /* 12 t4 */ + *(--stk) = (rt_uint32_t) 0x0000000b; /* 11 t3 */ + *(--stk) = (rt_uint32_t) 0x0000000a; /* 10 t2 */ + *(--stk) = (rt_uint32_t) 0x00000009; /* 9 t1 */ + *(--stk) = (rt_uint32_t) 0x00000008; /* 8 t0 */ + *(--stk) = (rt_uint32_t) 0x00000007; /* 7 a3 */ + *(--stk) = (rt_uint32_t) 0x00000006; /* 6 a2 */ + *(--stk) = (rt_uint32_t) 0x00000005; /* 5 a1 */ + *(--stk) = (rt_uint32_t) parameter; /* 4 a0 */ + *(--stk) = (rt_uint32_t) 0x00000003; /* 3 v1 */ + *(--stk) = (rt_uint32_t) 0x00000002; /* 2 v0 */ + *(--stk) = (rt_uint32_t) 0x00000001; /* 1 at */ + *(--stk) = (rt_uint32_t) 0x00000000; /* 0 zero */ - /* return task's current stack address */ - return (rt_uint8_t *)stk; + /* return task's current stack address */ + return (rt_uint8_t *)stk; } diff --git a/libcpu/nios/nios_ii/stack.c b/libcpu/nios/nios_ii/stack.c index 125bf2c578..463ba0df96 100644 --- a/libcpu/nios/nios_ii/stack.c +++ b/libcpu/nios/nios_ii/stack.c @@ -1,7 +1,7 @@ /* * File : stack.c * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2011, RT-Thread Development Team + * COPYRIGHT (C) 2006-2021, RT-Thread Development Team * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at @@ -30,43 +30,43 @@ * @return stack address */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) + rt_uint8_t *stack_addr, void *texit) { - unsigned long *stk; + unsigned long *stk; - stk = (unsigned long *)stack_addr; - *(stk) = 0x01; /* status */ - *(--stk) = (unsigned long)texit; /* ra */ - *(--stk) = 0xdeadbeef; /* fp */ - *(--stk) = 0xdeadbeef; /* r23 */ - *(--stk) = 0xdeadbeef; /* r22 */ - *(--stk) = 0xdeadbeef; /* r21 */ - *(--stk) = 0xdeadbeef; /* r20 */ - *(--stk) = 0xdeadbeef; /* r19 */ - *(--stk) = 0xdeadbeef; /* r18 */ - *(--stk) = 0xdeadbeef; /* r17 */ - *(--stk) = 0xdeadbeef; /* r16 */ -// *(--stk) = 0xdeadbeef; /* r15 */ -// *(--stk) = 0xdeadbeef; /* r14 */ -// *(--stk) = 0xdeadbeef; /* r13 */ -// *(--stk) = 0xdeadbeef; /* r12 */ -// *(--stk) = 0xdeadbeef; /* r11 */ -// *(--stk) = 0xdeadbeef; /* r10 */ -// *(--stk) = 0xdeadbeef; /* r9 */ -// *(--stk) = 0xdeadbeef; /* r8 */ - *(--stk) = 0xdeadbeef; /* r7 */ - *(--stk) = 0xdeadbeef; /* r6 */ - *(--stk) = 0xdeadbeef; /* r5 */ - *(--stk) = (unsigned long)parameter; /* r4 argument */ - *(--stk) = 0xdeadbeef; /* r3 */ - *(--stk) = 0xdeadbeef; /* r2 */ - *(--stk) = (unsigned long)tentry; /* pc */ + stk = (unsigned long *)stack_addr; + *(stk) = 0x01; /* status */ + *(--stk) = (unsigned long)texit; /* ra */ + *(--stk) = 0xdeadbeef; /* fp */ + *(--stk) = 0xdeadbeef; /* r23 */ + *(--stk) = 0xdeadbeef; /* r22 */ + *(--stk) = 0xdeadbeef; /* r21 */ + *(--stk) = 0xdeadbeef; /* r20 */ + *(--stk) = 0xdeadbeef; /* r19 */ + *(--stk) = 0xdeadbeef; /* r18 */ + *(--stk) = 0xdeadbeef; /* r17 */ + *(--stk) = 0xdeadbeef; /* r16 */ +// *(--stk) = 0xdeadbeef; /* r15 */ +// *(--stk) = 0xdeadbeef; /* r14 */ +// *(--stk) = 0xdeadbeef; /* r13 */ +// *(--stk) = 0xdeadbeef; /* r12 */ +// *(--stk) = 0xdeadbeef; /* r11 */ +// *(--stk) = 0xdeadbeef; /* r10 */ +// *(--stk) = 0xdeadbeef; /* r9 */ +// *(--stk) = 0xdeadbeef; /* r8 */ + *(--stk) = 0xdeadbeef; /* r7 */ + *(--stk) = 0xdeadbeef; /* r6 */ + *(--stk) = 0xdeadbeef; /* r5 */ + *(--stk) = (unsigned long)parameter; /* r4 argument */ + *(--stk) = 0xdeadbeef; /* r3 */ + *(--stk) = 0xdeadbeef; /* r2 */ + *(--stk) = (unsigned long)tentry; /* pc */ -// *(stk) = (unsigned long)tentry; /* thread entry (ra) */ -// *(--stk) = (unsigned long)parameter; /* thread argument, r4 */ +// *(stk) = (unsigned long)tentry; /* thread entry (ra) */ +// *(--stk) = (unsigned long)parameter; /* thread argument, r4 */ - /* return task's current stack address */ - return (rt_uint8_t *)stk; + /* return task's current stack address */ + return (rt_uint8_t *)stk; } /*@}*/ diff --git a/libcpu/ppc/common/stack.c b/libcpu/ppc/common/stack.c index 570e9ba046..de9d7d2016 100644 --- a/libcpu/ppc/common/stack.c +++ b/libcpu/ppc/common/stack.c @@ -1,7 +1,7 @@ /* * File : stack.c * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2011, RT-Thread Development Team + * COPYRIGHT (C) 2006-2021, RT-Thread Development Team * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at @@ -9,7 +9,7 @@ * * Change Logs: * Date Author Notes - * 2011-02-14 Fred first implementation for + * 2011-02-14 Fred first implementation for */ #include diff --git a/libcpu/ppc/ppc405/interrupt.c b/libcpu/ppc/ppc405/interrupt.c index 27a528e2f0..f072dd07e1 100644 --- a/libcpu/ppc/ppc405/interrupt.c +++ b/libcpu/ppc/ppc405/interrupt.c @@ -28,18 +28,18 @@ rt_uint32_t rt_thread_switch_interrput_flag; rt_isr_handler_t rt_hw_interrupt_handler(rt_uint32_t vector, void* param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); - return RT_NULL; + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + return RT_NULL; } void uic_irq_ack(unsigned int vec) { - mtdcr(uic0sr, UIC_MASK(vec)); + mtdcr(uic0sr, UIC_MASK(vec)); } void uic_int_handler (unsigned int vec) { - rt_interrupt_enter(); + rt_interrupt_enter(); /* Allow external interrupts to the CPU. */ if (isr_table [vec].handler != 0) @@ -47,91 +47,91 @@ void uic_int_handler (unsigned int vec) (*isr_table[vec].handler)(vec, isr_table[vec].param); } uic_irq_ack(vec); - + rt_interrupt_leave(); } /* handler for UIC interrupt */ void uic_interrupt(rt_uint32_t uic_base, int vec_base) { - int vec; - rt_uint32_t uic_msr; - rt_uint32_t msr_shift; - - /* - * Read masked interrupt status register to determine interrupt source - */ - uic_msr = get_dcr(uic_base + UIC_MSR); - msr_shift = uic_msr; - vec = vec_base; - - while (msr_shift != 0) - { - if (msr_shift & 0x80000000) - uic_int_handler(vec); - - /* - * Shift msr to next position and increment vector - */ - msr_shift <<= 1; - vec++; - } + int vec; + rt_uint32_t uic_msr; + rt_uint32_t msr_shift; + + /* + * Read masked interrupt status register to determine interrupt source + */ + uic_msr = get_dcr(uic_base + UIC_MSR); + msr_shift = uic_msr; + vec = vec_base; + + while (msr_shift != 0) + { + if (msr_shift & 0x80000000) + uic_int_handler(vec); + + /* + * Shift msr to next position and increment vector + */ + msr_shift <<= 1; + vec++; + } } -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, void* param, const char* name) { - int intVal; + int intVal; rt_isr_handler_t old_handler; - if (((int)vector < 0) || ((int) vector >= MAX_HANDLERS)) - { + if (((int)vector < 0) || ((int) vector >= MAX_HANDLERS)) + { return RT_NULL; /* out of range */ - } - + } + /* install the handler in the system interrupt table */ intVal = rt_hw_interrupt_disable (); /* lock interrupts to prevent races */ old_handler = isr_table[vector].handler; isr_table[vector].handler = new_handler; isr_table[vector].param = param; - + rt_hw_interrupt_enable (intVal); } void rt_hw_interrupt_mask(int vector) { - mtdcr(uic0er, mfdcr(uic0er) & ~UIC_MASK(vector)); + mtdcr(uic0er, mfdcr(uic0er) & ~UIC_MASK(vector)); } void rt_hw_interrupt_unmask(int vector) { - mtdcr(uic0er, mfdcr(uic0er) | UIC_MASK(vector)); + mtdcr(uic0er, mfdcr(uic0er) | UIC_MASK(vector)); } void rt_hw_interrupt_init() { - int vector; + int vector; rt_uint32_t pit_value; pit_value = RT_TICK_PER_SECOND * (100000000 / RT_CPU_FREQ); /* enable pit */ - mtspr(SPRN_PIT, pit_value); - mtspr(SPRN_TCR, 0x4400000); + mtspr(SPRN_PIT, pit_value); + mtspr(SPRN_TCR, 0x4400000); - /* set default interrupt handler */ + /* set default interrupt handler */ for (vector = 0; vector < MAX_HANDLERS; vector++) { - isr_table [vector].handler = (rt_isr_handler_t)rt_hw_interrupt_handler; + isr_table [vector].handler = (rt_isr_handler_t)rt_hw_interrupt_handler; isr_table [vector].param = RT_NULL; } - /* initialize interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrput_flag = 0; + /* initialize interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrput_flag = 0; } /*@}*/ diff --git a/libcpu/rx/cpuport.c b/libcpu/rx/cpuport.c index 681c0e8e6e..ba8b6ff779 100644 --- a/libcpu/rx/cpuport.c +++ b/libcpu/rx/cpuport.c @@ -34,9 +34,9 @@ rt_uint32_t rt_thread_switch_interrupt_flag; /* stack frame*/ struct stack_frame { - rt_uint32_t ACCLO; + rt_uint32_t ACCLO; rt_uint32_t ACCHI; - rt_uint32_t FPSW; + rt_uint32_t FPSW; rt_uint32_t R1; rt_uint32_t R2; rt_uint32_t R3; @@ -53,21 +53,21 @@ struct stack_frame rt_uint32_t R14; rt_uint32_t R15; //there is not R0 register,it is special for stack pointer - rt_uint32_t PC; - rt_uint32_t PSW; + rt_uint32_t PC; + rt_uint32_t PSW; }; /** * Initilial the thread stack. - * + * * @author LXZ (2014/11/8) - * - * @param void* tentry - * @param void* parameter - * @param rt_uint8_t* stack_addr - * @param void* texit - * - * @return rt_uint8_t* + * + * @param void* tentry + * @param void* parameter + * @param rt_uint8_t* stack_addr + * @param void* texit + * + * @return rt_uint8_t* */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) @@ -77,7 +77,7 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, unsigned long i; stk = (unsigned long *)stack_addr; - *(stk) = (unsigned long)texit; + *(stk) = (unsigned long)texit; stack_frame = (struct stack_frame *)(stack_addr - sizeof(struct stack_frame)) ; //Initilial all register @@ -85,12 +85,12 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, { ((rt_uint32_t *)stack_frame)[i] = 0xdeadbeef; } - + stack_frame->PSW = (unsigned long)0x00030000 ; /* psw */ stack_frame->PC = (unsigned long)tentry; /* thread entery*/ stack_frame->R1 = (unsigned long )parameter; /* r1 : parameter */ stack_frame->FPSW = 0x00000100; /* fpsw */ - + return(rt_uint8_t *)stack_frame; } @@ -99,16 +99,16 @@ extern void list_thread(void); #endif extern rt_thread_t rt_current_thread; /** - * deal exception - * + * deal exception + * * @author LXZ (2014/11/8) - * - * @param struct stack_frame* exception_contex + * + * @param struct stack_frame* exception_contex */ void rt_hw_hard_fault_exception(struct stack_frame* exception_contex) { if (exception_contex != RT_NULL) { - rt_kprintf("psw: 0x%08x\n", exception_contex->PSW); + rt_kprintf("psw: 0x%08x\n", exception_contex->PSW); rt_kprintf("pc: 0x%08x\n", exception_contex->PC); rt_kprintf("r0: 0x%08x\n", exception_contex->R1); rt_kprintf("r0: 0x%08x\n", exception_contex->R2); @@ -134,17 +134,17 @@ void rt_hw_hard_fault_exception(struct stack_frame* exception_contex) list_thread(); #endif while (1); - + } /** * switch thread in interrupt - * + * * @author LXZ (2014/11/8) - * - * @param rt_uint32_t from - * @param rt_uint32_t to + * + * @param rt_uint32_t from + * @param rt_uint32_t to */ void rt_hw_context_switch(rt_uint32_t from, rt_uint32_t to) { @@ -159,11 +159,11 @@ void rt_hw_context_switch(rt_uint32_t from, rt_uint32_t to) } /** * switch thread out the interrupt - * + * * @author LXZ (2014/11/8) - * - * @param rt_uint32_t from - * @param rt_uint32_t to + * + * @param rt_uint32_t from + * @param rt_uint32_t to */ void rt_hw_context_switch_interrupt(rt_uint32_t from, rt_uint32_t to) { @@ -179,7 +179,7 @@ void rt_hw_context_switch_interrupt(rt_uint32_t from, rt_uint32_t to) /** * shut down the chip - * + * * @author LXZ (2014/11/8) */ void rt_hw_cpu_shutdown(void) @@ -190,10 +190,10 @@ void rt_hw_cpu_shutdown(void) } /** * switch to the first thread,it just call one time - * + * * @author LXZ (2014/11/8) - * - * @param rt_uint32_t to + * + * @param rt_uint32_t to */ void rt_hw_context_switch_to(rt_uint32_t to) { diff --git a/libcpu/ti-dsp/c28x/cpuport.c b/libcpu/ti-dsp/c28x/cpuport.c index 3f88606c65..33b6923aaf 100644 --- a/libcpu/ti-dsp/c28x/cpuport.c +++ b/libcpu/ti-dsp/c28x/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/unicore32/sep6200/cpu.c b/libcpu/unicore32/sep6200/cpu.c index 01da33ad93..8d0b86dae3 100644 --- a/libcpu/unicore32/sep6200/cpu.c +++ b/libcpu/unicore32/sep6200/cpu.c @@ -20,23 +20,23 @@ #ifdef __GNUC__ rt_inline void cache_invalid(void) { - __asm__ volatile ("movc p0.c5, r1, #28\n" - "nop;nop;nop;nop;nop;nop;nop;nop;\n" - : - : - :"memory", "cc" - ); + __asm__ volatile ("movc p0.c5, r1, #28\n" + "nop;nop;nop;nop;nop;nop;nop;nop;\n" + : + : + :"memory", "cc" + ); } rt_inline void cache_enable(void) { - __asm__ volatile ( "movc r1, p0.c1, #0\n" - "or r1, r1, #0xc\n" - "movc p0.c1, r1, #0\n" - "nop;nop;nop;nop;nop;nop;nop;nop;\n" - : - : - :"r0", "memory", "cc"); + __asm__ volatile ( "movc r1, p0.c1, #0\n" + "or r1, r1, #0xc\n" + "movc p0.c1, r1, #0\n" + "nop;nop;nop;nop;nop;nop;nop;nop;\n" + : + : + :"r0", "memory", "cc"); } rt_inline void clean_dcache(void) @@ -45,8 +45,8 @@ rt_inline void clean_dcache(void) "movc p0.c5, ip, #10\n" "nop; nop; nop; nop; nop; nop; nop; nop\n" : - : - :"ip", "memory", "cc"); + : + :"ip", "memory", "cc"); } rt_inline rt_uint32_t icache_status(void) @@ -77,7 +77,7 @@ rt_inline rt_uint32_t dcache_status(void) rt_inline void dcache_flush(void) { - __asm__ volatile ( "mov ip, #0\n" + __asm__ volatile ( "mov ip, #0\n" "movc p0.c5, ip, #14\n" "nop; nop; nop; nop; nop; nop; nop; nop\n" : @@ -87,7 +87,7 @@ rt_inline void dcache_flush(void) rt_inline void icache_invalid(void) { - __asm__ volatile ( "mov r0, #0\n" + __asm__ volatile ( "mov r0, #0\n" "movc p0.c5, r0, #20\n" "nop; nop; nop; nop; nop; nop; nop; nop\n" : @@ -107,8 +107,8 @@ rt_inline void dcache_invalid(void) rt_inline void icache_disable(void) { - icache_invalid(); - __asm__ volatile ( "movc r0, p0.c1, #0\n" + icache_invalid(); + __asm__ volatile ( "movc r0, p0.c1, #0\n" "andn r0, r0, #8\n" "movc p0.c1, r0, #0\n" : @@ -118,8 +118,8 @@ rt_inline void icache_disable(void) rt_inline void dcache_disable(void) { - dcache_flush(); - __asm__ volatile ( "movc r0, p0.c1, #0\n" + dcache_flush(); + __asm__ volatile ( "movc r0, p0.c1, #0\n" "andn r0, r0, #20\n" "movc p0.c1, r0, #0\n" : @@ -170,7 +170,7 @@ rt_inline void dcache_enable(void) */ void rt_hw_cpu_icache_enable() { - icache_enable(); + icache_enable(); } /** @@ -179,7 +179,7 @@ void rt_hw_cpu_icache_enable() */ void rt_hw_cpu_icache_disable() { - icache_disable(); + icache_disable(); } /** @@ -188,7 +188,7 @@ void rt_hw_cpu_icache_disable() */ rt_base_t rt_hw_cpu_icache_status() { - return icache_status(); + return icache_status(); } /** @@ -197,7 +197,7 @@ rt_base_t rt_hw_cpu_icache_status() */ void rt_hw_cpu_dcache_enable() { - dcache_enable(); + dcache_enable(); } /** @@ -206,7 +206,7 @@ void rt_hw_cpu_dcache_enable() */ void rt_hw_cpu_dcache_disable() { - dcache_disable(); + dcache_disable(); } /** @@ -215,29 +215,29 @@ void rt_hw_cpu_dcache_disable() */ rt_base_t rt_hw_cpu_dcache_status() { - return dcache_status(); + return dcache_status(); } static void sep6200_reset(rt_uint32_t addr) { __asm__ volatile ( "mov ip, #0\n" - "movc p0.c5, ip, #28\n" /*Cache invalidate all*/ - "movc p0.c6, ip, #6\n" /*TLB invalidate all*/ - "nop;nop;nop;nop;nop;nop;nop;nop;\n" - "movc ip, p0.c1, #0\n" /*ctrl register*/ - "andn ip, ip, #0x000f\n" /*disable caches and mmu*/ - "movc p0.c1, ip, #0\n" - "nop\n" - "mov pc, %0\n" - "nop;nop;nop;nop;nop;nop;nop;nop;\n" - : "=&r" (addr) - : - :"memory", "cc"); + "movc p0.c5, ip, #28\n" /*Cache invalidate all*/ + "movc p0.c6, ip, #6\n" /*TLB invalidate all*/ + "nop;nop;nop;nop;nop;nop;nop;nop;\n" + "movc ip, p0.c1, #0\n" /*ctrl register*/ + "andn ip, ip, #0x000f\n" /*disable caches and mmu*/ + "movc p0.c1, ip, #0\n" + "nop\n" + "mov pc, %0\n" + "nop;nop;nop;nop;nop;nop;nop;nop;\n" + : "=&r" (addr) + : + :"memory", "cc"); } static void sep6200_poweroff(void) { - rt_kprintf("sep6200 power off not implemented\n"); + rt_kprintf("sep6200 power off not implemented\n"); while(1); } @@ -248,12 +248,12 @@ static void sep6200_poweroff(void) void rt_hw_cpu_reset() { - rt_kprintf("Soft reset, Restarting system...\n"); - sep6200_reset(0); + rt_kprintf("Soft reset, Restarting system...\n"); + sep6200_reset(0); - while(1); /* loop forever and wait for reset to happen */ + while(1); /* loop forever and wait for reset to happen */ - /* NEVER REACHED */ + /* NEVER REACHED */ } /** @@ -262,15 +262,15 @@ void rt_hw_cpu_reset() */ void rt_hw_cpu_shutdown() { - rt_uint32_t level; - rt_kprintf("shutdown...\n"); - - level = rt_hw_interrupt_disable(); - sep6200_poweroff(); - while (level) - { - RT_ASSERT(0); - } + rt_uint32_t level; + rt_kprintf("shutdown...\n"); + + level = rt_hw_interrupt_disable(); + sep6200_poweroff(); + while (level) + { + RT_ASSERT(0); + } } /*@}*/ diff --git a/libcpu/unicore32/sep6200/interrupt.c b/libcpu/unicore32/sep6200/interrupt.c index 2737849903..b34e648630 100644 --- a/libcpu/unicore32/sep6200/interrupt.c +++ b/libcpu/unicore32/sep6200/interrupt.c @@ -12,38 +12,38 @@ #include #include -#define MAX_HANDLERS 64 +#define MAX_HANDLERS 64 #define SEP6200_IRQ_TYPE 0 #define SEP6200_FIQ_TYPE 1 -#define int_enable_all() \ - do { \ - *(volatile unsigned long*)SEP6200_VIC_INT_EN_L = ~0x0;\ - *(volatile unsigned long*)SEP6200_VIC_INT_EN_H = ~0x0;\ - }while(0) -#define int_disable_all() \ - do { \ - *(volatile unsigned long*)SEP6200_VIC_INT_EN_L = 0x0;\ - *(volatile unsigned long*)SEP6200_VIC_INT_EN_H = 0x0;\ - }while(0) -#define mask_all_int(int_type) \ - do { \ - if (int_type == SEP6200_IRQ_TYPE){ \ - *(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = 0x1;\ - } else if (int_type == SEP6200_FIQ_TYPE) {\ - *(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = 0x2;\ - }\ - }while(0) +#define int_enable_all() \ + do { \ + *(volatile unsigned long*)SEP6200_VIC_INT_EN_L = ~0x0;\ + *(volatile unsigned long*)SEP6200_VIC_INT_EN_H = ~0x0;\ + }while(0) +#define int_disable_all() \ + do { \ + *(volatile unsigned long*)SEP6200_VIC_INT_EN_L = 0x0;\ + *(volatile unsigned long*)SEP6200_VIC_INT_EN_H = 0x0;\ + }while(0) +#define mask_all_int(int_type) \ + do { \ + if (int_type == SEP6200_IRQ_TYPE){ \ + *(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = 0x1;\ + } else if (int_type == SEP6200_FIQ_TYPE) {\ + *(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = 0x2;\ + }\ + }while(0) #define unmask_all_int(int_type)\ - do { \ - if (int_type == SEP6200_IRQ_TYPE){ \ - *(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = ~0x1;\ - } else if (int_type == SEP6200_FIQ_TYPE) {\ - *(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = ~0x2;\ - }\ - }while(0) + do { \ + if (int_type == SEP6200_IRQ_TYPE){ \ + *(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = ~0x1;\ + } else if (int_type == SEP6200_FIQ_TYPE) {\ + *(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = ~0x2;\ + }\ + }while(0) #define SEP6200_INT_SET(intnum) \ do{ \ @@ -99,27 +99,27 @@ void rt_hw_interrupt_umask(int irq); rt_inline void sep6200_irq_enable(rt_uint32_t irq) { - SEP6200_INT_ENABLE(irq); + SEP6200_INT_ENABLE(irq); } rt_inline void sep6200_irq_disable(rt_uint32_t irq) { - SEP6200_INT_DISABLE(irq); + SEP6200_INT_DISABLE(irq); } rt_inline void sep6200_irq_unmask(rt_uint32_t irq) { - SEP6200_INT_ENABLE(irq); + SEP6200_INT_ENABLE(irq); } rt_inline void sep6200_irq_mask(rt_uint32_t irq) { - SEP6200_INT_DISABLE(irq); + SEP6200_INT_DISABLE(irq); } rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); - return RT_NULL; + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + return RT_NULL; } /** @@ -127,26 +127,26 @@ rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector) */ void rt_hw_interrupt_init(void) { - rt_int32_t i; - register rt_uint32_t idx; - - - /* init exceptions table */ - for(idx=0; idx < MAX_HANDLERS; idx++) - { - isr_table[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle; - } - int_disable_all(); - mask_all_int(SEP6200_FIQ_TYPE); - - //int_enable_all(); - unmask_all_int(SEP6200_IRQ_TYPE); - - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + rt_int32_t i; + register rt_uint32_t idx; + + + /* init exceptions table */ + for(idx=0; idx < MAX_HANDLERS; idx++) + { + isr_table[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle; + } + int_disable_all(); + mask_all_int(SEP6200_FIQ_TYPE); + + //int_enable_all(); + unmask_all_int(SEP6200_IRQ_TYPE); + + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; } @@ -157,11 +157,11 @@ void rt_hw_interrupt_init(void) */ void rt_hw_interrupt_mask(int irq) { - if (irq >= MAX_HANDLERS) { - rt_kprintf("Wrong irq num to mask\n"); - } else { - sep6200_irq_mask(irq); - } + if (irq >= MAX_HANDLERS) { + rt_kprintf("Wrong irq num to mask\n"); + } else { + sep6200_irq_mask(irq); + } } @@ -171,11 +171,11 @@ void rt_hw_interrupt_mask(int irq) */ void rt_hw_interrupt_umask(int irq) { - if (irq >= MAX_HANDLERS) { - rt_kprintf("Wrong irq num to unmask\n"); - } else { - sep6200_irq_unmask(irq); - } + if (irq >= MAX_HANDLERS) { + rt_kprintf("Wrong irq num to unmask\n"); + } else { + sep6200_irq_unmask(irq); + } } /** @@ -196,7 +196,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, if (handler != RT_NULL) { #ifdef RT_USING_INTERRUPT_INFO - rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); + rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); #endif /* RT_USING_INTERRUPT_INFO */ isr_table[vector].handler = handler; isr_table[vector].param = param; diff --git a/libcpu/unicore32/sep6200/sep6200.h b/libcpu/unicore32/sep6200/sep6200.h index 9aced7fbbb..773b505a02 100644 --- a/libcpu/unicore32/sep6200/sep6200.h +++ b/libcpu/unicore32/sep6200/sep6200.h @@ -15,58 +15,58 @@ /*Core definations*/ #define PRIVMODE 0x13 -#define Mode_USR 0x10 -#define Mode_REAL 0x11 -#define Mode_IRQ 0x12 -#define Mode_PRIV 0x13 -#define Mode_TRAP 0x17 -#define Mode_EXT 0x1B -#define Mode_SUSR 0x1F +#define Mode_USR 0x10 +#define Mode_REAL 0x11 +#define Mode_IRQ 0x12 +#define Mode_PRIV 0x13 +#define Mode_TRAP 0x17 +#define Mode_EXT 0x1B +#define Mode_SUSR 0x1F /* * Address */ -#define SEP6200_VIC_BASE 0xb0000000 -#define SEP6200_PMU_BASE 0xb0001000 -#define SEP6200_RTC_BASE 0xb0002000 -#define SEP6200_TIMER_BASE 0xb0003000 -#define SEP6200_PWM_BASE 0xb0004000 -#define SEP6200_GPIO_BASE 0xb0006000 -#define SEP6200_TOUCH_ADC 0xb0007000 -#define SEP6200_SYSCTL_BASE 0xb0008000 -#define SEP6200_UART0_BASE 0xb1000000 -#define SEP6200_UART1_BASE 0xb1001000 -#define SEP6200_UART2_BASE 0xb1002000 -#define SEP6200_UART3_BASE 0xb1003000 -#define SEP6200_SSI1_BASE 0xb1004000 -#define SEP6200_SSI2_BASE 0xb1005000 -#define SEP6200_SSI3_BASE 0xb1006000 -#define SEP6200_I2C_BASE 0xb1007000 -#define SEP6200_I2S_BASE 0xb1008000 +#define SEP6200_VIC_BASE 0xb0000000 +#define SEP6200_PMU_BASE 0xb0001000 +#define SEP6200_RTC_BASE 0xb0002000 +#define SEP6200_TIMER_BASE 0xb0003000 +#define SEP6200_PWM_BASE 0xb0004000 +#define SEP6200_GPIO_BASE 0xb0006000 +#define SEP6200_TOUCH_ADC 0xb0007000 +#define SEP6200_SYSCTL_BASE 0xb0008000 +#define SEP6200_UART0_BASE 0xb1000000 +#define SEP6200_UART1_BASE 0xb1001000 +#define SEP6200_UART2_BASE 0xb1002000 +#define SEP6200_UART3_BASE 0xb1003000 +#define SEP6200_SSI1_BASE 0xb1004000 +#define SEP6200_SSI2_BASE 0xb1005000 +#define SEP6200_SSI3_BASE 0xb1006000 +#define SEP6200_I2C_BASE 0xb1007000 +#define SEP6200_I2S_BASE 0xb1008000 #define SEP6200_USB_BASE 0xb1010000 #define SEP6200_DMAC2_BASE 0xb1011000 #define SEP6200_ESRAM_BASE 0xb2000000 -#define SEP6200_NORREG_BASE0xb2020000 -#define SEP6200_SDIO1_BASE 0xb2022000 -#define SEP6200_SDIO2_BASE 0xb2023000 -#define SEP6200_LCDC_BASE 0xb2025000 -#define SEP6200_VPU_BASE 0xb2026000 -#define SEP6200_DMAC1_BASE 0xb2027000 -#define SEP6200_DDR2_REG 0xb3000000 -#define SEP6200_DDR_MEM 0x40000000 +#define SEP6200_NORREG_BASE0xb2020000 +#define SEP6200_SDIO1_BASE 0xb2022000 +#define SEP6200_SDIO2_BASE 0xb2023000 +#define SEP6200_LCDC_BASE 0xb2025000 +#define SEP6200_VPU_BASE 0xb2026000 +#define SEP6200_DMAC1_BASE 0xb2027000 +#define SEP6200_DDR2_REG 0xb3000000 +#define SEP6200_DDR_MEM 0x40000000 -#define SEP6200_UART0_DLBL (SEP6200_UART0_BASE+0x00) -#define SEP6200_UART0_RXFIFO (SEP6200_UART0_BASE+0x00) -#define SEP6200_UART0_TXFIFO (SEP6200_UART0_BASE+0x00) -#define SEP6200_UART0_DLBH (SEP6200_UART0_BASE+0x04) -#define SEP6200_UART0_IER (SEP6200_UART0_BASE+0x04) -#define SEP6200_UART0_IIR (SEP6200_UART0_BASE+0x08) -#define SEP6200_UART0_FCR (SEP6200_UART0_BASE+0x08) -#define SEP6200_UART0_LCR (SEP6200_UART0_BASE+0x0c) -#define SEP6200_UART0_MCR (SEP6200_UART0_BASE+0x10) -#define SEP6200_UART0_LSR (SEP6200_UART0_BASE+0x14) -#define SEP6200_UART0_MSR (SEP6200_UART0_BASE+0x18) +#define SEP6200_UART0_DLBL (SEP6200_UART0_BASE+0x00) +#define SEP6200_UART0_RXFIFO (SEP6200_UART0_BASE+0x00) +#define SEP6200_UART0_TXFIFO (SEP6200_UART0_BASE+0x00) +#define SEP6200_UART0_DLBH (SEP6200_UART0_BASE+0x04) +#define SEP6200_UART0_IER (SEP6200_UART0_BASE+0x04) +#define SEP6200_UART0_IIR (SEP6200_UART0_BASE+0x08) +#define SEP6200_UART0_FCR (SEP6200_UART0_BASE+0x08) +#define SEP6200_UART0_LCR (SEP6200_UART0_BASE+0x0c) +#define SEP6200_UART0_MCR (SEP6200_UART0_BASE+0x10) +#define SEP6200_UART0_LSR (SEP6200_UART0_BASE+0x14) +#define SEP6200_UART0_MSR (SEP6200_UART0_BASE+0x18) #define SEP6200_TIMER_T1LCR (SEP6200_TIMER_BASE + 0X000) @@ -348,7 +348,7 @@ typedef void (*FP)(); /* program start address */ #ifndef _BOOL_TYPE_ #define _BOOL_TYPE_ -typedef int BOOL; /* Boolean value. TRUE (1) or FALSE (0). */ +typedef int BOOL; /* Boolean value. TRUE (1) or FALSE (0). */ #endif typedef int ER; /* Error code. A signed integer. */ @@ -368,88 +368,88 @@ typedef int ER; /* Error code. A signed integer. */ /*Macros for debug*/ #define EOUT(fmt,...) \ - do \ - { \ - rt_kprintf("EOUT:(%s:%i) ",__FILE__,__LINE__); \ - rt_kprintf(fmt,##__VA_ARGS__); \ - }while(0) + do \ + { \ + rt_kprintf("EOUT:(%s:%i) ",__FILE__,__LINE__); \ + rt_kprintf(fmt,##__VA_ARGS__); \ + }while(0) #define RT_DEBUG #ifdef RT_DEBUG - #define DBOUT(fmt,...) \ - do \ - { \ - rt_kprintf("DBOUT:(%s:%i) ",__FILE__,__LINE__); \ - rt_kprintf(fmt,##__VA_ARGS__); \ - }while(0) + #define DBOUT(fmt,...) \ + do \ + { \ + rt_kprintf("DBOUT:(%s:%i) ",__FILE__,__LINE__); \ + rt_kprintf(fmt,##__VA_ARGS__); \ + }while(0) #else - #define DBOUT(fmt,...) \ - do{}while(0) + #define DBOUT(fmt,...) \ + do{}while(0) #endif -#ifdef RT_DEBUG - #define ASSERT(arg) \ - if((arg) == 0) \ - { \ - while(1) \ - { \ - rt_kprintf("have a assert failure\n"); \ - } \ - } +#ifdef RT_DEBUG + #define ASSERT(arg) \ + if((arg) == 0) \ + { \ + while(1) \ + { \ + rt_kprintf("have a assert failure\n"); \ + } \ + } #else - #define ASSERT(arg) \ - do \ - { \ - }while(0) + #define ASSERT(arg) \ + do \ + { \ + }while(0) #endif #define write_reg(reg,value) \ - do \ - { \ - *(RP)(reg) = value; \ - }while(0) + do \ + { \ + *(RP)(reg) = value; \ + }while(0) #define read_reg(reg) (*(RP)reg) struct rt_hw_register { - rt_uint32_t r0; - rt_uint32_t r1; - rt_uint32_t r2; - rt_uint32_t r3; - rt_uint32_t r4; - rt_uint32_t r5; - rt_uint32_t r6; - rt_uint32_t r7; - rt_uint32_t r8; - rt_uint32_t r9; - rt_uint32_t r10; - rt_uint32_t r11; - rt_uint32_t r12; - rt_uint32_t r13; - rt_uint32_t r14; - rt_uint32_t r15; - rt_uint32_t r16; - rt_uint32_t r17; - rt_uint32_t r18; - rt_uint32_t r19; - rt_uint32_t r20; - rt_uint32_t r21; - rt_uint32_t r22; - rt_uint32_t r23; - rt_uint32_t r24; - rt_uint32_t sb; - rt_uint32_t sl; - rt_uint32_t fp; - rt_uint32_t ip; - rt_uint32_t sp; - rt_uint32_t lr; - rt_uint32_t pc; - rt_uint32_t asr; - rt_uint32_t bsr; - rt_uint32_t ORIG_r0; + rt_uint32_t r0; + rt_uint32_t r1; + rt_uint32_t r2; + rt_uint32_t r3; + rt_uint32_t r4; + rt_uint32_t r5; + rt_uint32_t r6; + rt_uint32_t r7; + rt_uint32_t r8; + rt_uint32_t r9; + rt_uint32_t r10; + rt_uint32_t r11; + rt_uint32_t r12; + rt_uint32_t r13; + rt_uint32_t r14; + rt_uint32_t r15; + rt_uint32_t r16; + rt_uint32_t r17; + rt_uint32_t r18; + rt_uint32_t r19; + rt_uint32_t r20; + rt_uint32_t r21; + rt_uint32_t r22; + rt_uint32_t r23; + rt_uint32_t r24; + rt_uint32_t sb; + rt_uint32_t sl; + rt_uint32_t fp; + rt_uint32_t ip; + rt_uint32_t sp; + rt_uint32_t lr; + rt_uint32_t pc; + rt_uint32_t asr; + rt_uint32_t bsr; + rt_uint32_t ORIG_r0; }; /*@}*/ diff --git a/libcpu/unicore32/sep6200/serial.c b/libcpu/unicore32/sep6200/serial.c index 9b594d87be..f91834b6a7 100644 --- a/libcpu/unicore32/sep6200/serial.c +++ b/libcpu/unicore32/sep6200/serial.c @@ -5,7 +5,7 @@ * * Change Logs: * Date Author Notes - * 2013-03-16 Peng Fan Modified from sep4020 + * 2013-03-16 Peng Fan Modified from sep4020 */ #include #include @@ -22,204 +22,204 @@ */ static rt_err_t rt_serial_init (rt_device_t dev) { - struct serial_device* uart = (struct serial_device*) dev->user_data; + struct serial_device* uart = (struct serial_device*) dev->user_data; - if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) - { + if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) + { - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_memset(uart->int_rx->rx_buffer, 0, - sizeof(uart->int_rx->rx_buffer)); - uart->int_rx->read_index = uart->int_rx->save_index = 0; - } + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_memset(uart->int_rx->rx_buffer, 0, + sizeof(uart->int_rx->rx_buffer)); + uart->int_rx->read_index = uart->int_rx->save_index = 0; + } - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - rt_memset(uart->int_tx->tx_buffer, 0, - sizeof(uart->int_tx->tx_buffer)); - uart->int_tx->write_index = uart->int_tx->save_index = 0; - } + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + rt_memset(uart->int_tx->tx_buffer, 0, + sizeof(uart->int_tx->tx_buffer)); + uart->int_tx->write_index = uart->int_tx->save_index = 0; + } - dev->flag |= RT_DEVICE_FLAG_ACTIVATED; - } + dev->flag |= RT_DEVICE_FLAG_ACTIVATED; + } - return RT_EOK; + return RT_EOK; } /* save a char to serial buffer */ static void rt_serial_savechar(struct serial_device* uart, char ch) { - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch; - uart->int_rx->save_index ++; - if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->save_index = 0; - - /* if the next position is read index, discard this 'read char' */ - if (uart->int_rx->save_index == uart->int_rx->read_index) - { - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch; + uart->int_rx->save_index ++; + if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->save_index = 0; + + /* if the next position is read index, discard this 'read char' */ + if (uart->int_rx->save_index == uart->int_rx->read_index) + { + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); } static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) { - RT_ASSERT(dev != RT_NULL); - return RT_EOK; + RT_ASSERT(dev != RT_NULL); + return RT_EOK; } static rt_err_t rt_serial_close(rt_device_t dev) { - RT_ASSERT(dev != RT_NULL); - return RT_EOK; + RT_ASSERT(dev != RT_NULL); + return RT_EOK; } static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - rt_err_t err_code; - struct serial_device* uart; - - ptr = buffer; - err_code = RT_EOK; - uart = (struct serial_device*)dev->user_data; - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_base_t level; - - /* interrupt mode Rx */ - while (size) - { - if (uart->int_rx->read_index != uart->int_rx->save_index) - { - *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; - size --; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } - else - { - /* set error code */ - err_code = -RT_EEMPTY; - break; - } - } - } - else - { - /* polling mode */ - while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) - { - while (uart->uart_device->lsr & USTAT_RCV_READY) - { - *ptr = uart->uart_device->dlbl_fifo.txfifo & 0xff; - ptr ++; - } - } - } - - /* set error code */ - rt_set_errno(err_code); - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + rt_uint8_t* ptr; + rt_err_t err_code; + struct serial_device* uart; + + ptr = buffer; + err_code = RT_EOK; + uart = (struct serial_device*)dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_base_t level; + + /* interrupt mode Rx */ + while (size) + { + if (uart->int_rx->read_index != uart->int_rx->save_index) + { + *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; + size --; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + else + { + /* set error code */ + err_code = -RT_EEMPTY; + break; + } + } + } + else + { + /* polling mode */ + while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) + { + while (uart->uart_device->lsr & USTAT_RCV_READY) + { + *ptr = uart->uart_device->dlbl_fifo.txfifo & 0xff; + ptr ++; + } + } + } + + /* set error code */ + rt_set_errno(err_code); + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; } static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - rt_err_t err_code; - struct serial_device* uart; - - err_code = RT_EOK; - ptr = (rt_uint8_t*)buffer; - uart = (struct serial_device*)dev->user_data; - - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - /* interrupt mode Tx */ - while (uart->int_tx->save_index != uart->int_tx->write_index) - { - /* save on tx buffer */ - uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++; - - -- size; - - /* move to next position */ - uart->int_tx->save_index ++; - - /* wrap save index */ - if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE) - uart->int_tx->save_index = 0; - } - - /* set error code */ - if (size > 0) - err_code = -RT_EFULL; - } - else - { - /* polling mode */ - while (size) - { - /* - * to be polite with serial console add a line feed - * to the carriage return character - */ - if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM)) - { - while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); - uart->uart_device->dlbl_fifo.txfifo = '\r'; - } - - while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); - uart->uart_device->dlbl_fifo.txfifo = (*ptr & 0x1FF); - - ++ptr; --size; - } - } - - /* set error code */ - rt_set_errno(err_code); - - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + rt_uint8_t* ptr; + rt_err_t err_code; + struct serial_device* uart; + + err_code = RT_EOK; + ptr = (rt_uint8_t*)buffer; + uart = (struct serial_device*)dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* interrupt mode Tx */ + while (uart->int_tx->save_index != uart->int_tx->write_index) + { + /* save on tx buffer */ + uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++; + + -- size; + + /* move to next position */ + uart->int_tx->save_index ++; + + /* wrap save index */ + if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE) + uart->int_tx->save_index = 0; + } + + /* set error code */ + if (size > 0) + err_code = -RT_EFULL; + } + else + { + /* polling mode */ + while (size) + { + /* + * to be polite with serial console add a line feed + * to the carriage return character + */ + if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM)) + { + while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); + uart->uart_device->dlbl_fifo.txfifo = '\r'; + } + + while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); + uart->uart_device->dlbl_fifo.txfifo = (*ptr & 0x1FF); + + ++ptr; --size; + } + } + + /* set error code */ + rt_set_errno(err_code); + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; } static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) { - RT_ASSERT(dev != RT_NULL); - - switch (cmd) - { - case RT_DEVICE_CTRL_SUSPEND: - /* suspend device */ - dev->flag |= RT_DEVICE_FLAG_SUSPENDED; - break; - - case RT_DEVICE_CTRL_RESUME: - /* resume device */ - dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; - break; - } - - return RT_EOK; + RT_ASSERT(dev != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_SUSPEND: + /* suspend device */ + dev->flag |= RT_DEVICE_FLAG_SUSPENDED; + break; + + case RT_DEVICE_CTRL_RESUME: + /* resume device */ + dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; + break; + } + + return RT_EOK; } /* @@ -227,49 +227,49 @@ static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) */ rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial) { - RT_ASSERT(device != RT_NULL); - - device->type = RT_Device_Class_Char; - device->rx_indicate = RT_NULL; - device->tx_complete = RT_NULL; - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; - device->user_data = serial; - - /* register a character device */ - return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); + RT_ASSERT(device != RT_NULL); + + device->type = RT_Device_Class_Char; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; + device->user_data = serial; + + /* register a character device */ + return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); } /* ISR for serial interrupt */ void rt_hw_serial_isr(rt_device_t device) { - struct serial_device* uart = (struct serial_device*) device->user_data; + struct serial_device* uart = (struct serial_device*) device->user_data; - /* interrupt mode receive */ - RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); + /* interrupt mode receive */ + RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); - /* save on rx buffer */ - while (uart->uart_device->lsr & USTAT_RCV_READY) - { - rt_serial_savechar(uart, uart->uart_device->dlbl_fifo.rxfifo & 0xff); - } + /* save on rx buffer */ + while (uart->uart_device->lsr & USTAT_RCV_READY) + { + rt_serial_savechar(uart, uart->uart_device->dlbl_fifo.rxfifo & 0xff); + } - /* invoke callback */ - if (device->rx_indicate != RT_NULL) - { - rt_size_t rx_length; + /* invoke callback */ + if (device->rx_indicate != RT_NULL) + { + rt_size_t rx_length; - /* get rx length */ - rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? - UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : - uart->int_rx->save_index - uart->int_rx->read_index; + /* get rx length */ + rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? + UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : + uart->int_rx->save_index - uart->int_rx->read_index; - device->rx_indicate(device, rx_length); - } + device->rx_indicate(device, rx_length); + } } /*@}*/ diff --git a/libcpu/unicore32/sep6200/serial.h b/libcpu/unicore32/sep6200/serial.h index beeceb6165..dcfdc517d4 100644 --- a/libcpu/unicore32/sep6200/serial.h +++ b/libcpu/unicore32/sep6200/serial.h @@ -16,73 +16,73 @@ #include -#define USTAT_RCV_READY 0x01 /* receive data ready */ -#define USTAT_OVERRUN 0x02 /* overrun */ -#define USTAT_PARITY_ERR 0x04 /* parity error */ -#define USTAT_FRAME_ERROR 0x08 /* frame error */ -#define USTAT_BREAK 0x10 /* break */ -#define USTAT_TXB_EMPTY 0x40 /* tx buffer empty */ -#define USTAT_RCV_ERR 0x80 /* receive error */ +#define USTAT_RCV_READY 0x01 /* receive data ready */ +#define USTAT_OVERRUN 0x02 /* overrun */ +#define USTAT_PARITY_ERR 0x04 /* parity error */ +#define USTAT_FRAME_ERROR 0x08 /* frame error */ +#define USTAT_BREAK 0x10 /* break */ +#define USTAT_TXB_EMPTY 0x40 /* tx buffer empty */ +#define USTAT_RCV_ERR 0x80 /* receive error */ -#define BPS 115200 /* serial baudrate */ +#define BPS 115200 /* serial baudrate */ -#define UART_RX_BUFFER_SIZE 64 -#define UART_TX_BUFFER_SIZE 64 +#define UART_RX_BUFFER_SIZE 64 +#define UART_TX_BUFFER_SIZE 64 /*For sep6200's uart have several secondary function*/ /*we use union to decribe it*/ union dlbl_fifo { - rt_uint32_t dlbl; - rt_uint32_t rxfifo; - rt_uint32_t txfifo; + rt_uint32_t dlbl; + rt_uint32_t rxfifo; + rt_uint32_t txfifo; }; union dlbh_ier { - rt_uint32_t dlbh; - rt_uint32_t ier; + rt_uint32_t dlbh; + rt_uint32_t ier; }; union iir_fcr { - rt_uint32_t iir; - rt_uint32_t fcr; + rt_uint32_t iir; + rt_uint32_t fcr; }; struct serial_int_rx { - rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; - rt_uint32_t read_index, save_index; + rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; + rt_uint32_t read_index, save_index; }; struct serial_int_tx { - rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; - rt_uint32_t write_index, save_index; + rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; + rt_uint32_t write_index, save_index; }; typedef struct uartport { - union dlbl_fifo dlbl_fifo; - union dlbh_ier dlbh_ier; - union iir_fcr iir_fcr; - rt_uint32_t lcr; - rt_uint32_t mcr; - rt_uint32_t lsr; - rt_uint32_t msr; + union dlbl_fifo dlbl_fifo; + union dlbh_ier dlbh_ier; + union iir_fcr iir_fcr; + rt_uint32_t lcr; + rt_uint32_t mcr; + rt_uint32_t lsr; + rt_uint32_t msr; }uartport; struct serial_device { - uartport* uart_device; + uartport* uart_device; - /* rx structure */ - struct serial_int_rx* int_rx; + /* rx structure */ + struct serial_int_rx* int_rx; - /* tx structure */ - struct serial_int_tx* int_tx; + /* tx structure */ + struct serial_int_tx* int_tx; }; rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial); diff --git a/libcpu/unicore32/sep6200/stack.c b/libcpu/unicore32/sep6200/stack.c index 71b917c214..049b075f6c 100644 --- a/libcpu/unicore32/sep6200/stack.c +++ b/libcpu/unicore32/sep6200/stack.c @@ -28,47 +28,47 @@ */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) + rt_uint8_t *stack_addr, void *texit) { - rt_uint32_t *stk; + rt_uint32_t *stk; - stk = (rt_uint32_t*)stack_addr; - *(stk) = (rt_uint32_t)tentry; /* entry point */ - *(--stk) = (rt_uint32_t)texit; /* lr */ - *(--stk) = 0; /* r28 */ - *(--stk) = 0; /* r27 */ - *(--stk) = 0; /* r26 */ - *(--stk) = 0; /* r25 */ - *(--stk) = 0; /* r24 */ - *(--stk) = 0; /* r23 */ - *(--stk) = 0; /* r22 */ - *(--stk) = 0; /* r21 */ - *(--stk) = 0; /* r20 */ - *(--stk) = 0; /* r19 */ - *(--stk) = 0; /* r18 */ - *(--stk) = 0; /* r17 */ - *(--stk) = 0; /* r16 */ - *(--stk) = 0; /* r15 */ - *(--stk) = 0; /* r14 */ - *(--stk) = 0; /* r13 */ - *(--stk) = 0; /* r12 */ - *(--stk) = 0; /* r11 */ - *(--stk) = 0; /* r10 */ - *(--stk) = 0; /* r9 */ - *(--stk) = 0; /* r8 */ - *(--stk) = 0; /* r7 */ - *(--stk) = 0; /* r6 */ - *(--stk) = 0; /* r5 */ - *(--stk) = 0; /* r4 */ - *(--stk) = 0; /* r3 */ - *(--stk) = 0; /* r2 */ - *(--stk) = 0; /* r1 */ - *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ - *(--stk) = Mode_PRIV; /* asr */ - *(--stk) = Mode_PRIV; /* bsr */ /*why both PRIV do not need switch?*/ + stk = (rt_uint32_t*)stack_addr; + *(stk) = (rt_uint32_t)tentry; /* entry point */ + *(--stk) = (rt_uint32_t)texit; /* lr */ + *(--stk) = 0; /* r28 */ + *(--stk) = 0; /* r27 */ + *(--stk) = 0; /* r26 */ + *(--stk) = 0; /* r25 */ + *(--stk) = 0; /* r24 */ + *(--stk) = 0; /* r23 */ + *(--stk) = 0; /* r22 */ + *(--stk) = 0; /* r21 */ + *(--stk) = 0; /* r20 */ + *(--stk) = 0; /* r19 */ + *(--stk) = 0; /* r18 */ + *(--stk) = 0; /* r17 */ + *(--stk) = 0; /* r16 */ + *(--stk) = 0; /* r15 */ + *(--stk) = 0; /* r14 */ + *(--stk) = 0; /* r13 */ + *(--stk) = 0; /* r12 */ + *(--stk) = 0; /* r11 */ + *(--stk) = 0; /* r10 */ + *(--stk) = 0; /* r9 */ + *(--stk) = 0; /* r8 */ + *(--stk) = 0; /* r7 */ + *(--stk) = 0; /* r6 */ + *(--stk) = 0; /* r5 */ + *(--stk) = 0; /* r4 */ + *(--stk) = 0; /* r3 */ + *(--stk) = 0; /* r2 */ + *(--stk) = 0; /* r1 */ + *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ + *(--stk) = Mode_PRIV; /* asr */ + *(--stk) = Mode_PRIV; /* bsr */ /*why both PRIV do not need switch?*/ - /* return task's current stack address */ - return (rt_uint8_t *)stk; + /* return task's current stack address */ + return (rt_uint8_t *)stk; } /*@}*/ diff --git a/libcpu/unicore32/sep6200/trap.c b/libcpu/unicore32/sep6200/trap.c index b7d564aa57..f2f342cfbe 100644 --- a/libcpu/unicore32/sep6200/trap.c +++ b/libcpu/unicore32/sep6200/trap.c @@ -28,16 +28,16 @@ extern struct rt_thread *rt_current_thread; void rt_hw_show_register (struct rt_hw_register *regs) { - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x r11:0x%08x\n", regs->r8, regs->r9, regs->r10,regs->r11); - rt_kprintf("r12:0x%08x r13:0x%08x r14:0x%08x r15:0x%08x\n", regs->r12,regs->r13,regs->r14,regs->r15); - rt_kprintf("r16:0x%08x r17:0x%08x r18:0x%08x r19:0x%08x\n", regs->r16,regs->r17,regs->r18,regs->r19); - rt_kprintf("r20:0x%08x r21:0x%08x r22:0x%08x r23:0x%08x\n", regs->r20,regs->r21,regs->r22,regs->r23); - rt_kprintf("r24:0x%08x sb:0x%08x sl:0x%08xfp :0x%08x ip :0x%08x\n",regs->r24,regs->sb,regs->sl,regs->fp,regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("asr:0x%08x bsr:0x%08x\n", regs->asr,regs->bsr); + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x r11:0x%08x\n", regs->r8, regs->r9, regs->r10,regs->r11); + rt_kprintf("r12:0x%08x r13:0x%08x r14:0x%08x r15:0x%08x\n", regs->r12,regs->r13,regs->r14,regs->r15); + rt_kprintf("r16:0x%08x r17:0x%08x r18:0x%08x r19:0x%08x\n", regs->r16,regs->r17,regs->r18,regs->r19); + rt_kprintf("r20:0x%08x r21:0x%08x r22:0x%08x r23:0x%08x\n", regs->r20,regs->r21,regs->r22,regs->r23); + rt_kprintf("r24:0x%08x sb:0x%08x sl:0x%08xfp :0x%08x ip :0x%08x\n",regs->r24,regs->sb,regs->sl,regs->fp,regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("asr:0x%08x bsr:0x%08x\n", regs->asr,regs->bsr); } /** @@ -50,13 +50,13 @@ void rt_hw_show_register (struct rt_hw_register *regs) */ void rt_hw_trap_extn(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("extn instruction\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); - rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); + rt_kprintf("extn instruction\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -70,10 +70,10 @@ void rt_hw_trap_extn(struct rt_hw_register *regs) */ void rt_hw_trap_swi(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("software interrupt\n"); - rt_hw_cpu_shutdown(); + rt_kprintf("software interrupt\n"); + rt_hw_cpu_shutdown(); } /** @@ -86,13 +86,13 @@ void rt_hw_trap_swi(struct rt_hw_register *regs) */ void rt_hw_trap_pabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("prefetch abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); - rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); + rt_kprintf("prefetch abort\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -105,13 +105,13 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs) */ void rt_hw_trap_dabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("data abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); - rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); + rt_kprintf("data abort\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -123,9 +123,9 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs) */ void rt_hw_trap_resv(struct rt_hw_register *regs) { - rt_kprintf("not used\n"); - rt_hw_show_register(regs); - rt_hw_cpu_shutdown(); + rt_kprintf("not used\n"); + rt_hw_show_register(regs); + rt_hw_cpu_shutdown(); } extern struct rt_irq_desc isr_table[]; @@ -138,7 +138,7 @@ void rt_hw_trap_irq(void) void *param; /* get the interrupt number */ - irq = *(RP)(SEP6200_VIC_IRQ_VECTOR_NUM); + irq = *(RP)(SEP6200_VIC_IRQ_VECTOR_NUM); /* get interrupt service routine */ isr_func = isr_table[irq].handler; @@ -148,13 +148,13 @@ void rt_hw_trap_irq(void) isr_func(irq, param); #ifdef RT_USING_INTERRUPT_INFO - isr_table[irq].counter++; + isr_table[irq].counter++; #endif /* RT_USING_INTERRUPT_INFO */ } void rt_hw_trap_fiq() { - rt_kprintf("fast interrupt request\n"); + rt_kprintf("fast interrupt request\n"); } /*@}*/ diff --git a/libcpu/xilinx/microblaze/cpu.c b/libcpu/xilinx/microblaze/cpu.c index 50a0e34dcd..f5294a17e1 100755 --- a/libcpu/xilinx/microblaze/cpu.c +++ b/libcpu/xilinx/microblaze/cpu.c @@ -28,8 +28,8 @@ void rt_hw_cpu_reset() */ void rt_hw_cpu_shutdown() { - rt_kprintf("shutdown...\n"); + rt_kprintf("shutdown...\n"); - while (1); + while (1); } diff --git a/libcpu/xilinx/microblaze/serial.c b/libcpu/xilinx/microblaze/serial.c index 17cca9f84d..1902f11710 100755 --- a/libcpu/xilinx/microblaze/serial.c +++ b/libcpu/xilinx/microblaze/serial.c @@ -12,7 +12,7 @@ * 2006-08-23 Bernard first version * 2009-05-14 Bernard add RT-THread device interface * - * 2011-12-17 nl1031 MicroBlaze + * 2011-12-17 nl1031 MicroBlaze */ #include @@ -22,23 +22,23 @@ typedef volatile rt_uint32_t REG32; struct rt_mb_uart_lite_hw { - REG32 Rx_FIFO; // Receiver Holding Register - REG32 Tx_FIFO; // Transmitter Holding Register - REG32 STAT_REG; // Channel Status Register - REG32 CTRL_REG; // Control Register + REG32 Rx_FIFO; // Receiver Holding Register + REG32 Tx_FIFO; // Transmitter Holding Register + REG32 STAT_REG; // Channel Status Register + REG32 CTRL_REG; // Control Register }; struct rt_mb_uart_lite { - struct rt_device parent; + struct rt_device parent; - struct rt_mb_uart_lite_hw* hw_base; - rt_uint16_t peripheral_id; - rt_uint32_t baudrate; + struct rt_mb_uart_lite_hw* hw_base; + rt_uint16_t peripheral_id; + rt_uint32_t baudrate; - /* reception field */ - rt_uint16_t save_index, read_index; - rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; + /* reception field */ + rt_uint16_t save_index, read_index; + rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; }; #ifdef RT_USING_UART1 struct rt_mb_uart_lite serial1; @@ -46,271 +46,271 @@ struct rt_mb_uart_lite serial1; static void rt_hw_serial_isr(void) { - unsigned int status; - rt_base_t level; - struct rt_device* device; - struct rt_mb_uart_lite* serial = RT_NULL; + unsigned int status; + rt_base_t level; + struct rt_device* device; + struct rt_mb_uart_lite* serial = RT_NULL; #ifdef RT_USING_UART1 - /* serial 1 */ - serial = &serial1; + /* serial 1 */ + serial = &serial1; #endif - RT_ASSERT(serial != RT_NULL); - - /* get generic device object */ - device = (rt_device_t)serial; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - /* get uart status register */ - status = serial->hw_base->STAT_REG; - while (status & XUL_SR_RX_FIFO_VALID_DATA) - { - /* get received character */ - serial->rx_buffer[serial->save_index] = serial->hw_base->Rx_FIFO; - - /* move to next position */ - serial->save_index ++; - if (serial->save_index >= RT_UART_RX_BUFFER_SIZE) - serial->save_index = 0; - - /* if the next position is read index, discard this 'read char' */ - if (serial->save_index == serial->read_index) - { - serial->read_index ++; - if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) - serial->read_index = 0; - } - status = serial->hw_base->STAT_REG; - } - /* enable interrupt */ - rt_hw_interrupt_enable(level); - - /* indicate to upper layer application */ - if (device->rx_indicate != RT_NULL) - device->rx_indicate(device, 1); + RT_ASSERT(serial != RT_NULL); + + /* get generic device object */ + device = (rt_device_t)serial; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + /* get uart status register */ + status = serial->hw_base->STAT_REG; + while (status & XUL_SR_RX_FIFO_VALID_DATA) + { + /* get received character */ + serial->rx_buffer[serial->save_index] = serial->hw_base->Rx_FIFO; + + /* move to next position */ + serial->save_index ++; + if (serial->save_index >= RT_UART_RX_BUFFER_SIZE) + serial->save_index = 0; + + /* if the next position is read index, discard this 'read char' */ + if (serial->save_index == serial->read_index) + { + serial->read_index ++; + if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) + serial->read_index = 0; + } + status = serial->hw_base->STAT_REG; + } + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + /* indicate to upper layer application */ + if (device->rx_indicate != RT_NULL) + device->rx_indicate(device, 1); } static rt_err_t rt_serial_init (rt_device_t dev) { - struct rt_mb_uart_lite* serial = (struct rt_mb_uart_lite*) dev; + struct rt_mb_uart_lite* serial = (struct rt_mb_uart_lite*) dev; - RT_ASSERT(serial != RT_NULL); + RT_ASSERT(serial != RT_NULL); - RT_ASSERT(serial->peripheral_id != XPAR_UARTLITE_1_DEVICE_ID); + RT_ASSERT(serial->peripheral_id != XPAR_UARTLITE_1_DEVICE_ID); - /* reset rx index */ - serial->save_index = 0; - serial->read_index = 0; + /* reset rx index */ + serial->save_index = 0; + serial->read_index = 0; - /* reset rx buffer */ - rt_memset(serial->rx_buffer, 0, RT_UART_RX_BUFFER_SIZE); + /* reset rx buffer */ + rt_memset(serial->rx_buffer, 0, RT_UART_RX_BUFFER_SIZE); - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) { - struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev; - RT_ASSERT(serial != RT_NULL); + struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev; + RT_ASSERT(serial != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* enable UART rx interrupt */ - serial->hw_base->CTRL_REG = XUL_CR_ENABLE_INTR; /* enable interrupt */ + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* enable UART rx interrupt */ + serial->hw_base->CTRL_REG = XUL_CR_ENABLE_INTR; /* enable interrupt */ - /* install UART handler */ - rt_hw_interrupt_install(serial->peripheral_id, (rt_isr_handler_t)rt_hw_serial_isr, RT_NULL); - rt_hw_interrupt_umask(serial->peripheral_id); - } + /* install UART handler */ + rt_hw_interrupt_install(serial->peripheral_id, (rt_isr_handler_t)rt_hw_serial_isr, RT_NULL); + rt_hw_interrupt_umask(serial->peripheral_id); + } - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_close(rt_device_t dev) { - struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev; - RT_ASSERT(serial != RT_NULL); + struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev; + RT_ASSERT(serial != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* disable interrupt */ - serial->hw_base->CTRL_REG = 0; /* RxReady interrupt */ - } + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* disable interrupt */ + serial->hw_base->CTRL_REG = 0; /* RxReady interrupt */ + } - return RT_EOK; + return RT_EOK; } static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev; - RT_ASSERT(serial != RT_NULL); - - /* point to buffer */ - ptr = (rt_uint8_t*) buffer; - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - while (size) - { - /* interrupt receive */ - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - if (serial->read_index != serial->save_index) - { - *ptr = serial->rx_buffer[serial->read_index]; - - serial->read_index ++; - if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) - serial->read_index = 0; - } - else - { - /* no data in rx buffer */ - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - break; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - - ptr ++; size --; - } - - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; - } - else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) - { - /* not support right now */ - RT_ASSERT(0); - } - else - { - /* poll mode */ - while (size) - { - /* Wait for Full Rx Buffer */ - while (!(serial->hw_base->STAT_REG & XUL_SR_RX_FIFO_VALID_DATA)); - - /* Read Character */ - *ptr = serial->hw_base->Rx_FIFO; - ptr ++; - size --; - } - - return (rt_size_t)ptr - (rt_size_t)buffer; - } - - return 0; + rt_uint8_t* ptr; + struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev; + RT_ASSERT(serial != RT_NULL); + + /* point to buffer */ + ptr = (rt_uint8_t*) buffer; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + while (size) + { + /* interrupt receive */ + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + if (serial->read_index != serial->save_index) + { + *ptr = serial->rx_buffer[serial->read_index]; + + serial->read_index ++; + if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) + serial->read_index = 0; + } + else + { + /* no data in rx buffer */ + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + ptr ++; size --; + } + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) + { + /* not support right now */ + RT_ASSERT(0); + } + else + { + /* poll mode */ + while (size) + { + /* Wait for Full Rx Buffer */ + while (!(serial->hw_base->STAT_REG & XUL_SR_RX_FIFO_VALID_DATA)); + + /* Read Character */ + *ptr = serial->hw_base->Rx_FIFO; + ptr ++; + size --; + } + + return (rt_size_t)ptr - (rt_size_t)buffer; + } + + return 0; } static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev; - RT_ASSERT(serial != RT_NULL); - - ptr = (rt_uint8_t*) buffer; - if (dev->open_flag & RT_DEVICE_OFLAG_WRONLY) - { - if (dev->flag & RT_DEVICE_FLAG_STREAM) - { - /* it's a stream mode device */ - while (size) - { - /* stream mode */ - if (*ptr == '\n') - { - while (!(serial->hw_base->STAT_REG & XUL_SR_TX_FIFO_EMPTY)); - serial->hw_base->Tx_FIFO = '\r'; - } - - /* Wait for Empty Tx Buffer */ - while (!(serial->hw_base->STAT_REG & XUL_SR_TX_FIFO_EMPTY)); - - /* Transmit Character */ - serial->hw_base->Tx_FIFO = *ptr; - if (*ptr & 1) - rt_hw_board_led_on(2); - else - rt_hw_board_led_off(2); - ptr ++; size --; - } - } - else - { - while (size) - { - /* Wait for Empty Tx Buffer */ - while (!(serial->hw_base->STAT_REG & XUL_SR_TX_FIFO_EMPTY)); - - /* Transmit Character */ - serial->hw_base->Tx_FIFO = *ptr; - if (*ptr & 1) - rt_hw_board_led_on(2); - else - rt_hw_board_led_off(2); - ptr ++; size --; - } - } - } - - return (rt_size_t)ptr - (rt_size_t)buffer; + rt_uint8_t* ptr; + struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev; + RT_ASSERT(serial != RT_NULL); + + ptr = (rt_uint8_t*) buffer; + if (dev->open_flag & RT_DEVICE_OFLAG_WRONLY) + { + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* it's a stream mode device */ + while (size) + { + /* stream mode */ + if (*ptr == '\n') + { + while (!(serial->hw_base->STAT_REG & XUL_SR_TX_FIFO_EMPTY)); + serial->hw_base->Tx_FIFO = '\r'; + } + + /* Wait for Empty Tx Buffer */ + while (!(serial->hw_base->STAT_REG & XUL_SR_TX_FIFO_EMPTY)); + + /* Transmit Character */ + serial->hw_base->Tx_FIFO = *ptr; + if (*ptr & 1) + rt_hw_board_led_on(2); + else + rt_hw_board_led_off(2); + ptr ++; size --; + } + } + else + { + while (size) + { + /* Wait for Empty Tx Buffer */ + while (!(serial->hw_base->STAT_REG & XUL_SR_TX_FIFO_EMPTY)); + + /* Transmit Character */ + serial->hw_base->Tx_FIFO = *ptr; + if (*ptr & 1) + rt_hw_board_led_on(2); + else + rt_hw_board_led_off(2); + ptr ++; size --; + } + } + } + + return (rt_size_t)ptr - (rt_size_t)buffer; } static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) { - return RT_EOK; + return RT_EOK; } rt_err_t rt_hw_serial_init() { - rt_device_t device; + rt_device_t device; #ifndef RT_USING_CONSOLE - int Status; + int Status; - /* - * Initialize the UartLite driver so that it is ready to use. - */ - Status = XUartLite_Initialize(&uart_lite, RS232_DEVICE_ID); - if (Status != XST_SUCCESS) - { - return; - } + /* + * Initialize the UartLite driver so that it is ready to use. + */ + Status = XUartLite_Initialize(&uart_lite, RS232_DEVICE_ID); + if (Status != XST_SUCCESS) + { + return; + } #endif #ifdef RT_USING_UART1 - device = (rt_device_t) &serial1; - - /* init serial device private data */ - serial1.hw_base = (struct rt_mb_uart_lite_hw*)XPAR_USB_UART_BASEADDR; - serial1.peripheral_id = XPAR_UARTLITE_1_DEVICE_ID; - serial1.baudrate = 115200; - - /* set device virtual interface */ - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; - - /* register uart1 on device subsystem */ - rt_device_register(device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); + device = (rt_device_t) &serial1; + + /* init serial device private data */ + serial1.hw_base = (struct rt_mb_uart_lite_hw*)XPAR_USB_UART_BASEADDR; + serial1.peripheral_id = XPAR_UARTLITE_1_DEVICE_ID; + serial1.baudrate = 115200; + + /* set device virtual interface */ + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; + + /* register uart1 on device subsystem */ + rt_device_register(device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); #endif - return RT_EOK; + return RT_EOK; } diff --git a/libcpu/xilinx/microblaze/stack.c b/libcpu/xilinx/microblaze/stack.c index 686fc078a3..87f1dfa014 100755 --- a/libcpu/xilinx/microblaze/stack.c +++ b/libcpu/xilinx/microblaze/stack.c @@ -29,43 +29,43 @@ extern void *_SDA2_BASE_; * @return stack address */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) + rt_uint8_t *stack_addr, void *texit) { - unsigned long *stk; + unsigned long *stk; - stk = (unsigned long *)stack_addr; - stk--; - stk--; - *stk-- = 0; /* r31 */ - *stk-- = 0; /* r30 */ - *stk-- = 0; /* r29 */ - *stk-- = 0; /* r28 */ - *stk-- = 0; /* r27 */ - *stk-- = 0; /* r26 */ - *stk-- = 0; /* r25 */ - *stk-- = 0; /* r24 */ - *stk-- = 0; /* r23 */ - *stk-- = 0; /* r22 */ - *stk-- = 0; /* r21 */ - *stk-- = 0; /* r20 */ - *stk-- = 0; /* r19 */ - *stk-- = 0; /* r18 */ - *stk-- = 0; /* r17 */ - *stk-- = (unsigned long)texit - 8; /* r15 = task return address*/ - *stk-- = (unsigned long)tentry; /* r14 = entry address*/ - *stk-- = (unsigned long)&_SDA_BASE_; /* r13 */ - *stk-- = 0; /* r12 */ - *stk-- = 0; /* r11 */ - *stk-- = 0; /* r10 */ - *stk-- = 0; /* r09 */ - *stk-- = 0; /* r08 */ - *stk-- = 0; /* r07 */ - *stk-- = 0; /* r06 */ - *stk-- = (unsigned long) parameter; /* r05 */ - *stk-- = 0; /* r04 */ - *stk-- = 0; /* r03 */ - *stk-- = (unsigned long)&_SDA2_BASE_; /* r02 */ - *stk = 2; /* enable interrupt */ - return (rt_uint8_t *)stk; + stk = (unsigned long *)stack_addr; + stk--; + stk--; + *stk-- = 0; /* r31 */ + *stk-- = 0; /* r30 */ + *stk-- = 0; /* r29 */ + *stk-- = 0; /* r28 */ + *stk-- = 0; /* r27 */ + *stk-- = 0; /* r26 */ + *stk-- = 0; /* r25 */ + *stk-- = 0; /* r24 */ + *stk-- = 0; /* r23 */ + *stk-- = 0; /* r22 */ + *stk-- = 0; /* r21 */ + *stk-- = 0; /* r20 */ + *stk-- = 0; /* r19 */ + *stk-- = 0; /* r18 */ + *stk-- = 0; /* r17 */ + *stk-- = (unsigned long)texit - 8; /* r15 = task return address*/ + *stk-- = (unsigned long)tentry; /* r14 = entry address*/ + *stk-- = (unsigned long)&_SDA_BASE_; /* r13 */ + *stk-- = 0; /* r12 */ + *stk-- = 0; /* r11 */ + *stk-- = 0; /* r10 */ + *stk-- = 0; /* r09 */ + *stk-- = 0; /* r08 */ + *stk-- = 0; /* r07 */ + *stk-- = 0; /* r06 */ + *stk-- = (unsigned long) parameter; /* r05 */ + *stk-- = 0; /* r04 */ + *stk-- = 0; /* r03 */ + *stk-- = (unsigned long)&_SDA2_BASE_; /* r02 */ + *stk = 2; /* enable interrupt */ + return (rt_uint8_t *)stk; } diff --git a/libcpu/xilinx/microblaze/trap.c b/libcpu/xilinx/microblaze/trap.c index 3b3f98d105..bcfb3cc492 100755 --- a/libcpu/xilinx/microblaze/trap.c +++ b/libcpu/xilinx/microblaze/trap.c @@ -10,13 +10,13 @@ * Change Logs: * Date Author Notes * 2006-08-23 Bernard first version - * 2011-12-17 nl1031 for MicroBlaze + * 2011-12-17 nl1031 for MicroBlaze * */ -#include -#include "xparameters.h" -#include "xintc.h" +#include +#include "xparameters.h" +#include "xintc.h" #include "xintc_i.h" #include "xintc_l.h" @@ -33,7 +33,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag; void rt_hw_interrupt_handler(int vector) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } /** @@ -41,24 +41,24 @@ void rt_hw_interrupt_handler(int vector) */ void rt_hw_interrupt_init() { - rt_base_t index; + rt_base_t index; - XIntc_Config *CfgPtr; + XIntc_Config *CfgPtr; CfgPtr = &XIntc_ConfigTable[0]; - for (index = 0; index < MAX_HANDLERS; index ++) - { - CfgPtr->HandlerTable[index].Handler = (XInterruptHandler)rt_hw_interrupt_handler; - } + for (index = 0; index < MAX_HANDLERS; index ++) + { + CfgPtr->HandlerTable[index].Handler = (XInterruptHandler)rt_hw_interrupt_handler; + } - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; } /** @@ -67,8 +67,8 @@ void rt_hw_interrupt_init() */ void rt_hw_interrupt_mask(int vector) { - /* disable interrupt */ - XIntc_Disable(&int_ctl,vector); + /* disable interrupt */ + XIntc_Disable(&int_ctl,vector); } /** @@ -77,7 +77,7 @@ void rt_hw_interrupt_mask(int vector) */ void rt_hw_interrupt_umask(int vector) { - XIntc_Enable(&int_ctl,vector); + XIntc_Enable(&int_ctl,vector); } /** @@ -88,15 +88,15 @@ void rt_hw_interrupt_umask(int vector) */ void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler) { - XIntc_Config *CfgPtr; + XIntc_Config *CfgPtr; CfgPtr = &XIntc_ConfigTable[0]; - if(vector >= 0 && vector < MAX_HANDLERS) - { - if (*old_handler != RT_NULL) *old_handler = (rt_isr_handler_t)CfgPtr->HandlerTable[vector].Handler; - if (new_handler != RT_NULL) CfgPtr->HandlerTable[vector].Handler = (XInterruptHandler)new_handler; - } + if(vector >= 0 && vector < MAX_HANDLERS) + { + if (*old_handler != RT_NULL) *old_handler = (rt_isr_handler_t)CfgPtr->HandlerTable[vector].Handler; + if (new_handler != RT_NULL) CfgPtr->HandlerTable[vector].Handler = (XInterruptHandler)new_handler; + } } /*****************************************************************************/ @@ -117,7 +117,7 @@ void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_ha * calling an interrupt handler. * * -* @return None. +* @return None. * * @note * @@ -131,81 +131,81 @@ void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_ha void rt_hw_trap_irq(void ) { - u32 intr_status; - u32 intr_mask = 1; - int intr_number; - volatile u32 reg; /* used as bit bucket */ - XIntc_Config *cfg_ptr; - - - /* Get the configuration data using the device ID */ - cfg_ptr = &XIntc_ConfigTable[0]; - - /* Get the interrupts that are waiting to be serviced */ - intr_status = XIntc_GetIntrStatus(XPAR_INTC_0_BASEADDR); - - /* Service each interrupt that is active and enabled by checking each - * bit in the register from LSB to MSB which corresponds to an interrupt - * intput signal - */ - for (intr_number = 0; intr_number < XPAR_INTC_MAX_NUM_INTR_INPUTS; intr_number++) - { - if (intr_status & 1) - { - XIntc_VectorTableEntry *table_ptr; - - /* If the interrupt has been setup to acknowledge it - * before servicing the interrupt, then ack it - */ - if (cfg_ptr->AckBeforeService & intr_mask) - { - XIntc_AckIntr(cfg_ptr->BaseAddress, intr_mask); - } - - /* The interrupt is active and enabled, call the - * interrupt handler that was setup with the specified - * parameter - */ - table_ptr = &(cfg_ptr->HandlerTable[intr_number]); - table_ptr->Handler(table_ptr->CallBackRef); - - /* If the interrupt has been setup to acknowledge it - * after it has been serviced then ack it - */ - if ((cfg_ptr->AckBeforeService & intr_mask) == 0) - { - XIntc_AckIntr(cfg_ptr->BaseAddress, intr_mask); - } - - /* - * Read the ISR again to handle architectures with posted write - * bus access issues. - */ - reg = XIntc_GetIntrStatus(cfg_ptr->BaseAddress); - - /* - * If only the highest priority interrupt is to be - * serviced, exit loop and return after servicing - * the interrupt - */ - if (cfg_ptr->Options == XIN_SVC_SGL_ISR_OPTION) - { - return; - } - } - - /* Move to the next interrupt to check */ - intr_mask <<= 1; - intr_status >>= 1; - - /* If there are no other bits set indicating that all interrupts - * have been serviced, then exit the loop - */ - if (intr_status == 0) - { - break; - } - } + u32 intr_status; + u32 intr_mask = 1; + int intr_number; + volatile u32 reg; /* used as bit bucket */ + XIntc_Config *cfg_ptr; + + + /* Get the configuration data using the device ID */ + cfg_ptr = &XIntc_ConfigTable[0]; + + /* Get the interrupts that are waiting to be serviced */ + intr_status = XIntc_GetIntrStatus(XPAR_INTC_0_BASEADDR); + + /* Service each interrupt that is active and enabled by checking each + * bit in the register from LSB to MSB which corresponds to an interrupt + * intput signal + */ + for (intr_number = 0; intr_number < XPAR_INTC_MAX_NUM_INTR_INPUTS; intr_number++) + { + if (intr_status & 1) + { + XIntc_VectorTableEntry *table_ptr; + + /* If the interrupt has been setup to acknowledge it + * before servicing the interrupt, then ack it + */ + if (cfg_ptr->AckBeforeService & intr_mask) + { + XIntc_AckIntr(cfg_ptr->BaseAddress, intr_mask); + } + + /* The interrupt is active and enabled, call the + * interrupt handler that was setup with the specified + * parameter + */ + table_ptr = &(cfg_ptr->HandlerTable[intr_number]); + table_ptr->Handler(table_ptr->CallBackRef); + + /* If the interrupt has been setup to acknowledge it + * after it has been serviced then ack it + */ + if ((cfg_ptr->AckBeforeService & intr_mask) == 0) + { + XIntc_AckIntr(cfg_ptr->BaseAddress, intr_mask); + } + + /* + * Read the ISR again to handle architectures with posted write + * bus access issues. + */ + reg = XIntc_GetIntrStatus(cfg_ptr->BaseAddress); + + /* + * If only the highest priority interrupt is to be + * serviced, exit loop and return after servicing + * the interrupt + */ + if (cfg_ptr->Options == XIN_SVC_SGL_ISR_OPTION) + { + return; + } + } + + /* Move to the next interrupt to check */ + intr_mask <<= 1; + intr_status >>= 1; + + /* If there are no other bits set indicating that all interrupts + * have been serviced, then exit the loop + */ + if (intr_status == 0) + { + break; + } + } } diff --git a/src/clock.c b/src/clock.c index 6bdfd21e91..c473b4f276 100644 --- a/src/clock.c +++ b/src/clock.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -111,7 +111,7 @@ rt_tick_t rt_tick_from_millisecond(rt_int32_t ms) tick = RT_TICK_PER_SECOND * (ms / 1000); tick += (RT_TICK_PER_SECOND * (ms % 1000) + 999) / 1000; } - + /* return the calculated tick */ return tick; } diff --git a/src/components.c b/src/components.c index c25c91dcba..ed9d5c3c4e 100644 --- a/src/components.c +++ b/src/components.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -173,7 +173,7 @@ void main_thread_entry(void *parameter) { extern int main(void); extern int $Super$$main(void); - + #ifdef RT_USING_COMPONENTS_INIT /* RT-Thread components initialization */ rt_components_init(); diff --git a/src/cpu.c b/src/cpu.c index 5cba05fe70..a8fcb06d23 100644 --- a/src/cpu.c +++ b/src/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/src/device.c b/src/device.c index a4f004fb69..388c2ecf12 100644 --- a/src/device.c +++ b/src/device.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/src/idle.c b/src/idle.c index 84f851ca1e..54cc088fd4 100644 --- a/src/idle.c +++ b/src/idle.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -194,7 +194,7 @@ static void rt_thread_idle_entry(void *parameter) #endif rt_thread_idle_excute(); -#ifdef RT_USING_PM +#ifdef RT_USING_PM rt_system_power_manager(); #endif } diff --git a/src/ipc.c b/src/ipc.c index dd7c1d8619..cb15c9b05b 100644 --- a/src/ipc.c +++ b/src/ipc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -119,7 +119,7 @@ rt_inline rt_err_t rt_ipc_list_suspend(rt_list_t *list, break; default: - break; + break; } return RT_EOK; @@ -912,7 +912,7 @@ rt_err_t rt_mutex_release(rt_mutex_t mutex) rt_hw_interrupt_enable(temp); /* enable interrupt */ return -RT_EFULL; /* value overflowed */ } - + /* clear owner */ mutex->owner = RT_NULL; mutex->original_priority = 0xff; @@ -1233,11 +1233,11 @@ rt_err_t rt_event_recv(rt_event_t event, /* set received event */ if (recved) *recved = (event->set & set); - - /* fill thread event info */ + + /* fill thread event info */ thread->event_set = (event->set & set); thread->event_info = option; - + /* received event */ if (option & RT_EVENT_FLAG_CLEAR) event->set &= ~set; @@ -1603,7 +1603,7 @@ rt_err_t rt_mb_send_wait(rt_mailbox_t mb, ++ mb->in_offset; if (mb->in_offset >= mb->size) mb->in_offset = 0; - + if(mb->entry < RT_MB_ENTRY_MAX) { /* increase message entry */ @@ -1614,7 +1614,7 @@ rt_err_t rt_mb_send_wait(rt_mailbox_t mb, rt_hw_interrupt_enable(temp); /* enable interrupt */ return -RT_EFULL; /* value overflowed */ } - + /* resume suspended thread */ if (!rt_list_isempty(&mb->parent.suspend_thread)) { @@ -2298,7 +2298,7 @@ rt_err_t rt_mq_urgent(rt_mq_t mq, const void *buffer, rt_size_t size) rt_hw_interrupt_enable(temp); /* enable interrupt */ return -RT_EFULL; /* value overflowed */ } - + /* resume suspended thread */ if (!rt_list_isempty(&mq->parent.suspend_thread)) { diff --git a/src/irq.c b/src/irq.c index 8b4d0d0a9e..c163c35544 100644 --- a/src/irq.c +++ b/src/irq.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,7 +20,7 @@ static void (*rt_interrupt_leave_hook)(void); /** * @ingroup Hook - * This function set a hook function when the system enter a interrupt + * This function set a hook function when the system enter a interrupt * * @note the hook function must be simple and never be blocked or suspend. */ @@ -30,7 +30,7 @@ void rt_interrupt_enter_sethook(void (*hook)(void)) } /** * @ingroup Hook - * This function set a hook function when the system exit a interrupt. + * This function set a hook function when the system exit a interrupt. * * @note the hook function must be simple and never be blocked or suspend. */ diff --git a/src/kservice.c b/src/kservice.c index 0a74f05268..ea9bd87b45 100644 --- a/src/kservice.c +++ b/src/kservice.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -456,7 +456,7 @@ RTM_EXPORT(rt_strncmp); rt_int32_t rt_strcmp(const char *cs, const char *ct) { while (*cs && *cs == *ct) - { + { cs++; ct++; } @@ -1127,10 +1127,10 @@ rt_device_t rt_console_set_device(const char *name) /* find new console device */ new_device = rt_device_find(name); - + /* check whether it's a same device */ if (new_device == old_device) return RT_NULL; - + if (new_device != RT_NULL) { if (_console_device != RT_NULL) diff --git a/src/mem.c b/src/mem.c index c03c8b3452..ac0d27f2c3 100644 --- a/src/mem.c +++ b/src/mem.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -489,7 +489,7 @@ void *rt_realloc(void *rmem, rt_size_t newsize) { ((struct heap_mem *)&heap_ptr[mem2->next])->prev = ptr2; } - + if (mem2 < lfree) { /* the splited struct is now the lowest */ diff --git a/src/memheap.c b/src/memheap.c index afa06fb9bf..358974b0ee 100644 --- a/src/memheap.c +++ b/src/memheap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 */ @@ -126,7 +126,7 @@ rt_err_t rt_memheap_detach(struct rt_memheap *heap) RT_ASSERT(heap); RT_ASSERT(rt_object_get_type(&heap->parent) == RT_Object_Class_MemHeap); RT_ASSERT(rt_object_is_systemobject(&heap->parent)); - + rt_sem_detach(&heap->lock); rt_object_detach(&(heap->parent)); diff --git a/src/mempool.c b/src/mempool.c index db614032aa..1de48940d7 100644 --- a/src/mempool.c +++ b/src/mempool.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/src/object.c b/src/object.c index dc3354f76d..8414a63e7e 100644 --- a/src/object.c +++ b/src/object.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -212,7 +212,7 @@ void rt_system_object_init(void) /** * This function will return the specified type of object information. * - * @param type the type of object, which can be + * @param type the type of object, which can be * RT_Object_Class_Thread/Semaphore/Mutex... etc * * @return the object type information or RT_NULL @@ -232,7 +232,7 @@ RTM_EXPORT(rt_object_get_information); /** * This function will return the length of object list in object container. * - * @param type the type of object, which can be + * @param type the type of object, which can be * RT_Object_Class_Thread/Semaphore/Mutex... etc * @return the length of object list */ @@ -259,10 +259,10 @@ int rt_object_get_length(enum rt_object_class_type type) RTM_EXPORT(rt_object_get_length); /** - * This function will copy the object pointer of the specified type, + * This function will copy the object pointer of the specified type, * with the maximum size specified by maxlen. * - * @param type the type of object, which can be + * @param type the type of object, which can be * RT_Object_Class_Thread/Semaphore/Mutex... etc * @param pointers the pointers will be saved to * @param maxlen the maximum number of pointers can be saved diff --git a/src/scheduler.c b/src/scheduler.c index 7ff529f5ee..9114bdcdc6 100644 --- a/src/scheduler.c +++ b/src/scheduler.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/src/signal.c b/src/signal.c index 02a975ee6f..08e79bcb2e 100644 --- a/src/signal.c +++ b/src/signal.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/src/slab.c b/src/slab.c index 0872ecf092..12ca1a938c 100644 --- a/src/slab.c +++ b/src/slab.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/src/thread.c b/src/thread.c index f20ca0c316..3351e35cf9 100644 --- a/src/thread.c +++ b/src/thread.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * -- cgit v1.3.1