Release
Notes for STM32F4xx CMSIS
Copyright 2017 STMicroelectronics
Update History
-V2.6.3 / 08-February-2019
+Update History
+V2.6.6 / 12-February-2021
+ Main +Changes+ + +
- system_stm32f4xx.c:
- Protect +Vector table modification following SRAM or FLASH preprocessor +directive by a generic preprocessor directive : USER_VECT_TAB_ADDRESS
- Update SystemInit_ExtMemCtl() API to initialize the tmpreg variable before each time out loop condition.
- Add License.md and Readme.md files required for GitHub publication
- Improve GCC startup files robustness.
- Fix wrong value for GPIO_MODER_MODE8_Msk and GPIO_MODER_MODE2_Pos.
- Update max number of host channels in FS for STM32F446:
- Update USB_OTG_FS_HOST_MAX_CHANNEL_NBR value from 8 to 12.
- Add SMBDEN and SMBHEN bit definition for STM32F410Tx device.
V2.6.5 / 10-February-2020
+ Main +Changes+ + +
- All header files
- Update to use new BSD License format
- MDK-ARM startup files
- Update to fix invalid config wizard annotations
V2.6.4 / 06-December-2019
+ Main +Changes+ + +
- stm32f446xx.h file
- Update to support HW flow control on UART4 and UART5 instances
- stm32f412xx.h, stm32f413xx.h and stm32f423xx.h files
- Remove unused IS_USB_ALL_INSTANCE() assert macro
- All header files
- Remove unused IS_TIM_SYNCHRO_INSTANCE() assert macro
- system_stm32f4xx.c file
- Update SystemInit() API to don't reset RCC registers to its reset values
V2.6.3 / 08-February-2019
Main Changes@@ -185,24 +204,24 @@ Changes
Remove PWR_CSR_WUPP define: feature not available on STM32F469xx/479xx devices -
V2.6.2 / 06-October-2017
+V2.6.2 / 06-October-2017
Main Changes-
- Remove Date and Version from all header files
- USB_OTG register clean up: remove duplicated bits definitions
- stm32f401xc.h, stm32f401xe.h, stm32f411xe.h files
- Remove BKPSRAM_BASE define: feature not available
- stm32f405xx.h, stm32f407xx.h files
- Rename HASH_RNG_IRQn to RNG_IRQn: HASH instance not available
- stm32f410xx.h, stm32f412xx.h, stm32f413xx.h, stm32f423xx.h files
- Add missing wake-up pins defines
- stm32f412cx.h files
- Add support of USART3 instance
V2.6.1 / 14-February-2017
Main +- Remove Date and Version from all header files
- USB_OTG register clean up: remove duplicated bits definitions
- stm32f401xc.h, stm32f401xe.h, stm32f411xe.h files
- Remove BKPSRAM_BASE define: feature not available
- stm32f405xx.h, stm32f407xx.h files
- Rename HASH_RNG_IRQn to RNG_IRQn: HASH instance not available
- stm32f410xx.h, stm32f412xx.h, stm32f413xx.h, stm32f423xx.h files
- Add missing wake-up pins defines
- stm32f412cx.h files
- Add support of USART3 instance
V2.6.1 / 14-February-2017
Main Changes-
- General updates in header files to support LL drivers
- Align Bit naming for RCC_CSR register (ex: RCC_CSR_PADRSTF --> RCC_CSR_PINRSTF)
- Add new defines for RCC features support:
- RCC PLLI2S and RCC PLLSAI support
- RCC PLLR I2S clock source and RCC PLLR system clock support
- RCC SAI1A PLL source and RCC SAI1B PLL source support
- RCC AHB2 support
- Add RCC_DCKCFGR_PLLI2SDIVQ_X and RCC_DCKCFGR_PLLSAIDIVQ_X bits definition
- Add new defines for RCC_PLLI2SCFGR_RST_VALUE, RCC_PLLSAICFGR_RST_VALUE and RCC_PLLCFGR_RST_VALUE
- Add new defines for RTC features support:
- RTC Tamper 2 support
- RTC AF2 mapping support
- Align Bit naming for RTC_CR and RTC_TAFCR registers (ex: RTC_CR_BCK --> RTC_CR_BKP)
- Add new define to manage RTC backup register number: RTC_BKP_NUMBER
- Rename IS_UART_INSTANCE() macro to IS_UART_HALFDUPLEX_INSTANCE()
- Add new defines to check LIN instance: IS_UART_LIN_INSTANCE
- Remove USART6 instance from STM32F410Tx header file
- Rename IS_I2S_ALL_INSTANCE_EXT() macro to IS_I2S_EXT_ALL_INSTANCEE()
- Add IS_I2S_APB1_INSTANCE() macro to check if I2S instance mapping: API1 or APB2
- Remove SPI_I2S_SUPPORT define for SPI I2S features support: I2S feature is available on all STM32F4xx devices
- Add SPI_I2S_FULLDUPLEX_SUPPORT define for STM32F413xx/423xx devices
- Align SPI_I2SCFGR bit naming: SPI_I2SCFGR_ASTRTEN bit is missing for STM32F412xx devices
- Add new I2S_APB1_APB2_FEATURE define for STM32F4xx devices where I2S IP's are splited between RCC APB1 and APB2 interfaces
- Add new FLASH_SR_RDERR define in FLASH_SR register
- Add FLASH_OTP_BASE and FLASH_OTP_END defnes to manage FLASH OPT area
- Add bit definitions for ETH_MACDBGR register
- Add new defines ADC1_COMMON_BASE and ADC123_COMMON_BASE to replace ADC_BASE define
- Add new defines ADC1_COMMON and ADC123_COMMON to replace ADC define
- Add new ADC macros: IS_ADC_COMMON_INSTANCE() and IS_ADC_MULTIMODE_MASTER_INSTANCE()
- Add new defines for ADC multi mode features support
- Add new ADC aliases ADC_CDR_RDATA_MST and ADC_CDR_RDATA_SLV for compatibilities with all STM32 Families
- Update TIM CNT and ARR register mask on 32-bits
- Add new TIM_OR_TI1_RMP define in TIM_OR register
- Add new TIM macros to check TIM feature instance support:
- IS_TIM_COUNTER_MODE_SELECT_INSTANCE()
- IS_TIM_CLOCK_DIVISION_INSTANCE()
- IS_TIM_COMMUTATION_EVENT_INSTANCE()
- IS_TIM_OCXREF_CLEAR_INSTANCE()
- IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE()
- IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE()
- IS_TIM_REPETITION_COUNTER_INSTANCE()
- IS_TIM_ENCODER_INTERFACE_INSTANCE()
- IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE()
- IS_TIM_BREAK_INSTANCE()
- CAN_IER register clean up: remove duplicated bit definitions
- USB_OTG register: fix the wrong defined values for USB_OTG_GAHBCFG bits
V2.6.0 / 04-November-2016
Main +- General updates in header files to support LL drivers
- Align Bit naming for RCC_CSR register (ex: RCC_CSR_PADRSTF --> RCC_CSR_PINRSTF)
- Add new defines for RCC features support:
- RCC PLLI2S and RCC PLLSAI support
- RCC PLLR I2S clock source and RCC PLLR system clock support
- RCC SAI1A PLL source and RCC SAI1B PLL source support
- RCC AHB2 support
- Add RCC_DCKCFGR_PLLI2SDIVQ_X and RCC_DCKCFGR_PLLSAIDIVQ_X bits definition
- Add new defines for RCC_PLLI2SCFGR_RST_VALUE, RCC_PLLSAICFGR_RST_VALUE and RCC_PLLCFGR_RST_VALUE
- Add new defines for RTC features support:
- RTC Tamper 2 support
- RTC AF2 mapping support
- Align Bit naming for RTC_CR and RTC_TAFCR registers (ex: RTC_CR_BCK --> RTC_CR_BKP)
- Add new define to manage RTC backup register number: RTC_BKP_NUMBER
- Rename IS_UART_INSTANCE() macro to IS_UART_HALFDUPLEX_INSTANCE()
- Add new defines to check LIN instance: IS_UART_LIN_INSTANCE
- Remove USART6 instance from STM32F410Tx header file
- Rename IS_I2S_ALL_INSTANCE_EXT() macro to IS_I2S_EXT_ALL_INSTANCEE()
- Add IS_I2S_APB1_INSTANCE() macro to check if I2S instance mapping: API1 or APB2
- Remove SPI_I2S_SUPPORT define for SPI I2S features support: I2S feature is available on all STM32F4xx devices
- Add SPI_I2S_FULLDUPLEX_SUPPORT define for STM32F413xx/423xx devices
- Align SPI_I2SCFGR bit naming: SPI_I2SCFGR_ASTRTEN bit is missing for STM32F412xx devices
- Add new I2S_APB1_APB2_FEATURE define for STM32F4xx devices where I2S IP's are splited between RCC APB1 and APB2 interfaces
- Add new FLASH_SR_RDERR define in FLASH_SR register
- Add FLASH_OTP_BASE and FLASH_OTP_END defnes to manage FLASH OPT area
- Add bit definitions for ETH_MACDBGR register
- Add new defines ADC1_COMMON_BASE and ADC123_COMMON_BASE to replace ADC_BASE define
- Add new defines ADC1_COMMON and ADC123_COMMON to replace ADC define
- Add new ADC macros: IS_ADC_COMMON_INSTANCE() and IS_ADC_MULTIMODE_MASTER_INSTANCE()
- Add new defines for ADC multi mode features support
- Add new ADC aliases ADC_CDR_RDATA_MST and ADC_CDR_RDATA_SLV for compatibilities with all STM32 Families
- Update TIM CNT and ARR register mask on 32-bits
- Add new TIM_OR_TI1_RMP define in TIM_OR register
- Add new TIM macros to check TIM feature instance support:
- IS_TIM_COUNTER_MODE_SELECT_INSTANCE()
- IS_TIM_CLOCK_DIVISION_INSTANCE()
- IS_TIM_COMMUTATION_EVENT_INSTANCE()
- IS_TIM_OCXREF_CLEAR_INSTANCE()
- IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE()
- IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE()
- IS_TIM_REPETITION_COUNTER_INSTANCE()
- IS_TIM_ENCODER_INTERFACE_INSTANCE()
- IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE()
- IS_TIM_BREAK_INSTANCE()
- CAN_IER register clean up: remove duplicated bit definitions
- USB_OTG register: fix the wrong defined values for USB_OTG_GAHBCFG bits
V2.6.0 / 04-November-2016
Main Changes- Add support of STM32F413xx and STM32F423xx devices
- Add "stm32f413xx.h" and "stm32f423xx.h" files
-
-
Add startup files "startup_stm32f413xx.s" and "startup_stm32f423xx.s" for EWARM, MDK-ARM and SW4STM32 toolchains
- Add Linker files "stm32f413xx_flash.icf", "stm32f413xx_sram.icf", "stm32f423xx_flash.icf" and "stm32f423xx_sram.icf" used within EWARM Workspaces
- All header files
- Use _Pos and _Mask macro for all Bit Definitions
- Update LPTIM_OR Bit Definition
- Update the defined frequencies by scale for USB exported constants
- Add UID_BASE, FLASHSIZE_BASE and PACKAGE_BASE defines
- Add new define DAC_CHANNEL2_SUPPORT to manage DAC channel2 support
- Use new DAC1 naming
- Rename PWR_CSR_UDSWRDY define to PWR_CSR_UDRDY in PWR_CSR register
- Align Bit naming for EXTI_IMR and EXTI_EMR registers (ex: EXTI_IMR_MR0 --> EXTI_IMR_IM0)
- Add new EXTI_IMR_IM define in EXTI_IMR register
- Add missing DMA registers definition
- Add macro to check SMBUS instance support
- stm32f412cx.h, stm32f412zx.h, stm32f412vx.h, stm32f412rx.h files
- Add missing SYSCFG register: CFGR2
- stm32f405xx.h, stm32f407xx.h, stm32f427xx.h, stm32f429xx.h files
- Remove HASH_RNG_IRQn in IRQn_Type enumeration
- stm32f405xx.h, stm32f407xx.h, stm32f415xx.h, stm32f417xx.h files
- Remove I2C FLTR register as not supported
- stm32f407xx.h, stm32f417xx.h, stm32f427xx.h, stm32f429xx.h, stm32f437xx.h, stm32f439xx.h, stm32f469xx.h, stm32f479xx.h files
- Add missing Bit Definition of ETH_MACDBGR register
- system_stm32f4xx.c file
- Add APBPrescTable declaration
V2.5.1 / 28-June-2016
Main +Add startup files "startup_stm32f413xx.s" and "startup_stm32f423xx.s" for EWARM, MDK-ARM and SW4STM32 toolchains
- Use _Pos and _Mask macro for all Bit Definitions
- Update LPTIM_OR Bit Definition
- Update the defined frequencies by scale for USB exported constants
- Add UID_BASE, FLASHSIZE_BASE and PACKAGE_BASE defines
- Add new define DAC_CHANNEL2_SUPPORT to manage DAC channel2 support
- Use new DAC1 naming
- Rename PWR_CSR_UDSWRDY define to PWR_CSR_UDRDY in PWR_CSR register
- Align Bit naming for EXTI_IMR and EXTI_EMR registers (ex: EXTI_IMR_MR0 --> EXTI_IMR_IM0)
- Add new EXTI_IMR_IM define in EXTI_IMR register
- Add missing DMA registers definition
- Add macro to check SMBUS instance support
- Add missing SYSCFG register: CFGR2
- Remove HASH_RNG_IRQn in IRQn_Type enumeration
- Remove I2C FLTR register as not supported
- Add missing Bit Definition of ETH_MACDBGR register
- Add APBPrescTable declaration
V2.5.1 / 28-June-2016
Main Changes-
- stm32f412rx.h, stm32f412vx.h and stm32f412zx.h files:
Add QSPI1_V2_1L define to manage the QSPI DMA2 limitation
V2.5.0 / 22-April-2016
Main +- stm32f412rx.h, stm32f412vx.h and stm32f412zx.h files:
Add QSPI1_V2_1L define to manage the QSPI DMA2 limitation
V2.5.0 / 22-April-2016
Main Changes-
- Add support of STM32F412Cx, STM32F412Rx, STM32F412Vx and STM32F412Zx devices
Add "stm32f412Cx.h", "stm32f412Rx.h", "stm32f412Vx.h" and "stm32f412Zx.h" files
Add startup files "startup_stm32f412cx.s", "startup_stm32f412rx.s", "startup_stm32f412vx.s" and "startup_stm32f412zx.s" for EWARM, MDK-ARM and SW4STM32 toolchains
- Add Linker files "stm32f412cx_flash.icf", "stm32f412cx_sram.icf", "stm32f412rx_flash.icf", "stm32f412rx_sram.icf", "stm32f412vx_flash.icf", "stm32f412vx_sram.icf", "stm32f412zx_flash.icf" and "stm32f412zx_sram.icf" used within EWARM Workspaces
- Header files for all STM32 devices
- Remove uint32_t cast and keep only Misra Cast (U) to avoid two types cast duplication
- Correct some bits definition to be in line with naming used in the Reference Manual
- WWDG_CR_Tx changed to WWDG_CR_T_x
- WWDG_CFR_Wx changed to WWDG_CFR_W_x
- WWDG_CFR_WDGTBx changed to WWDG_CFR_WDGTB_x
- stm32f407xx.h, stm32f417xx.h, stm32f427xx.h, stm32f429xx.h, stm32f437xx.h, stm32f439xx.h, stm32f446xx.h, stm32f469xx.h, stm32f479xx.h files
- Correct some bits definition to be in line with naming used in the Reference Manual
- DCMI_RISR_x changed to DCMI_RIS_x
- DCMI_RISR_OVF_RIS changed to DCMI_RIS_OVR_RIS
- DCMI_IER_OVF_IE changed to DCMI_IER_OVR_IE
- stm32f427xx.h, stm32f429xx.h, stm32f437xx.h, stm32f439xx.h, stm32f469xx.h, stm32f479xx.h, stm32f446xx.h files
- Correct some bits definition to be in line with naming used in the Reference Manual
- SAI_xFRCR_FSPO changed to SAI_xFRCR_FSPOL
- Rename IS_SAI_BLOCK_PERIPH to IS_SAI_ALL_INSTANCE
- stm32f410cx.h, stm32f410rx.h, stm32f410tx.h files and stm32f446xx.h
- Remove FMPI2C_CR1_SWRST and FMPI2C_CR1_WUPEN Bit definition for I2C_CR1 register
- stm32f407xx.h, stm32f417xx.h, stm32f427xx.h, stm32f437xx.h, stm32f439xx.h, stm32f469xx.h, stm32f479xx.h files
- Add missing bits definitions for DMA2D_CR, DMA2D_FGPFCCR, DMA2D_BGPFCCR, DMA2D_OPFCCR registers
- stm32f401xc.h, stm32f401xe.h, stm32f411xe.h files
- Add missing RCC_DCKCFGR register in RCC_TypeDef structure
- Add missing Bit definition for RCC_DCKCFGR register
- system_stm32f4xx.c
- Update SystemInit_ExtMemCtl() API to fix delay optimization problem with GCC compiler: index variable is declared as volatile
- stm32f4xx.h
- Rename __STM32F4xx_CMSIS_DEVICE_VERSION_xx defines to __STM32F4_CMSIS_VERSION_xx (MISRA-C 2004 rule 5.1)
V2.4.3 / 29-January-2016
Main +- Add support of STM32F412Cx, STM32F412Rx, STM32F412Vx and STM32F412Zx devices
Add "stm32f412Cx.h", "stm32f412Rx.h", "stm32f412Vx.h" and "stm32f412Zx.h" files
Add startup files "startup_stm32f412cx.s", "startup_stm32f412rx.s", "startup_stm32f412vx.s" and "startup_stm32f412zx.s" for EWARM, MDK-ARM and SW4STM32 toolchains
- Add Linker files "stm32f412cx_flash.icf", "stm32f412cx_sram.icf", "stm32f412rx_flash.icf", "stm32f412rx_sram.icf", "stm32f412vx_flash.icf", "stm32f412vx_sram.icf", "stm32f412zx_flash.icf" and "stm32f412zx_sram.icf" used within EWARM Workspaces
- Header files for all STM32 devices
- Remove uint32_t cast and keep only Misra Cast (U) to avoid two types cast duplication
- Correct some bits definition to be in line with naming used in the Reference Manual
- WWDG_CR_Tx changed to WWDG_CR_T_x
- WWDG_CFR_Wx changed to WWDG_CFR_W_x
- WWDG_CFR_WDGTBx changed to WWDG_CFR_WDGTB_x
- stm32f407xx.h, stm32f417xx.h, stm32f427xx.h, stm32f429xx.h, stm32f437xx.h, stm32f439xx.h, stm32f446xx.h, stm32f469xx.h, stm32f479xx.h files
- Correct some bits definition to be in line with naming used in the Reference Manual
- DCMI_RISR_x changed to DCMI_RIS_x
- DCMI_RISR_OVF_RIS changed to DCMI_RIS_OVR_RIS
- DCMI_IER_OVF_IE changed to DCMI_IER_OVR_IE
- stm32f427xx.h, stm32f429xx.h, stm32f437xx.h, stm32f439xx.h, stm32f469xx.h, stm32f479xx.h, stm32f446xx.h files
- Correct some bits definition to be in line with naming used in the Reference Manual
- SAI_xFRCR_FSPO changed to SAI_xFRCR_FSPOL
- Rename IS_SAI_BLOCK_PERIPH to IS_SAI_ALL_INSTANCE
- stm32f410cx.h, stm32f410rx.h, stm32f410tx.h files and stm32f446xx.h
- Remove FMPI2C_CR1_SWRST and FMPI2C_CR1_WUPEN Bit definition for I2C_CR1 register
- stm32f407xx.h, stm32f417xx.h, stm32f427xx.h, stm32f437xx.h, stm32f439xx.h, stm32f469xx.h, stm32f479xx.h files
- Add missing bits definitions for DMA2D_CR, DMA2D_FGPFCCR, DMA2D_BGPFCCR, DMA2D_OPFCCR registers
- stm32f401xc.h, stm32f401xe.h, stm32f411xe.h files
- Add missing RCC_DCKCFGR register in RCC_TypeDef structure
- Add missing Bit definition for RCC_DCKCFGR register
- system_stm32f4xx.c
- Update SystemInit_ExtMemCtl() API to fix delay optimization problem with GCC compiler: index variable is declared as volatile
- stm32f4xx.h
- Rename __STM32F4xx_CMSIS_DEVICE_VERSION_xx defines to __STM32F4_CMSIS_VERSION_xx (MISRA-C 2004 rule 5.1)
V2.4.3 / 29-January-2016
Main Changes-
Header file for all STM32 devices @@ -210,21 +229,21 @@ STM32 devicesRename ADC overrun flags definitions : ADC_CSR_DOVR1, ADC_CSR_DOVR2 and ADC_CSR_DOVR3 are replaced respectively by ADC_CSR_OVR1, ADC_CSR_OVR2 and -ADC_CSR_OVR3 to be aligned with reference manuals
- Add missing bits definitions for DAC : DAC_CR_DMAUDRIE1 and DAC_CR_DMAUDRIE2
- Update CMSIS driver to be compliant with MISRA C 2004 rule 10.6
- Remove the double definition of USB_OTG_HS_MAX_IN_ENDPOINTS and add a new one for USB_OTG_HS_MAX_OUT_ENDPOINTS
- Change the bit definition value of QUADSPI_CR_FTHRES
- Rename the LTDC_GCR_DTEN to LTDC_GCR_DEN in order to be aligned with the reference manual
- Rename DCMI_MISR bit definitions to DCMI_MIS
- Rename DCMI_ICR_OVF_ISC to DCMI_ICR_OVR_ISC
- Add missing bits definitions for DCMI_ESCR, DCMI_ESUR, DCMI_CWSTRT, DCMI_CWSIZE, DCMI_DR registers
- Rename DCMI_MISR bit definitions to DCMI_MIS
- Rename DCMI_ICR_OVF_ISC to DCMI_ICR_OVR_ISC
- Add missing bits definitions for DCMI_ESCR, DCMI_ESUR, DCMI_CWSTRT, DCMI_CWSIZE, DCMI_DR registers
- Update the LPTIM SNGSTRT defined value
- Rename the DMA2D_IFSR bit definitions to DMA2D_IFCR
- Correct a wrong value of SAI_xCR2_CPL definition bit
V2.4.2 / 13-November-2015
+ADC_CSR_OVR3 to be aligned with reference manuals- Change the bit definition value of QUADSPI_CR_FTHRES
- Rename the LTDC_GCR_DTEN to LTDC_GCR_DEN in order to be aligned with the reference manual
- Rename DCMI_MISR bit definitions to DCMI_MIS
- Rename DCMI_ICR_OVF_ISC to DCMI_ICR_OVR_ISC
- Add missing bits definitions for DCMI_ESCR, DCMI_ESUR, DCMI_CWSTRT, DCMI_CWSIZE, DCMI_DR registers
- Rename DCMI_MISR bit definitions to DCMI_MIS
- Rename DCMI_ICR_OVF_ISC to DCMI_ICR_OVR_ISC
- Add missing bits definitions for DCMI_ESCR, DCMI_ESUR, DCMI_CWSTRT, DCMI_CWSIZE, DCMI_DR registers
- Update the LPTIM SNGSTRT defined value
- Rename the DMA2D_IFSR bit definitions to DMA2D_IFCR
- Correct a wrong value of SAI_xCR2_CPL definition bit
V2.4.2 / 13-November-2015
Main Changes
-
system_stm32f4xx.c file
- update SystemInit_ExtMemCtl() function implementation to allow the possibility -of simultaneous use of DATA_IN_ExtSRAM and DATA_IN_ExtSDRAM
- stm32f4xx.h file
- add symbols for STM32F411xC devices
- stm32f405xx.h, stm32f407xx.h, stm32f415xx.h, stm32f417xx.h files
- add FSMC_BCRx_CPSIZE bits definitions
- remove FSMC_BWTRx_CLKDIV and FSMC_BWTRx_DATLAT bits definitions
- stm32f429xx.h, stm32f427xx.h, stm32f437xx.h files
- add FMC_BCRx_CPSIZE bits definitions
- remove FMC_BWTRx_CLKDIV and FMC_BWTRx_DATLAT bits definitions
- stm32f446xx.h, stm32f469xx.h and stm32f479xx.h
- update USB_OTG_GlobalTypeDef registers structure to remove ADP control registers
- add USB_OTG_DOEPMSK_OTEPSPRM and USB_OTG_DOEPINT_OTEPSPR bits definitions
- Remove ADP related bits definitions
- add IS_PCD_ALL_INSTANCE() and IS_HCD_ALL_INSTANCE() macros
V2.4.1 / +of simultaneous use of DATA_IN_ExtSRAM and DATA_IN_ExtSDRAM
- add symbols for STM32F411xC devices
- add FSMC_BCRx_CPSIZE bits definitions
- remove FSMC_BWTRx_CLKDIV and FSMC_BWTRx_DATLAT bits definitions
- add FMC_BCRx_CPSIZE bits definitions
- remove FMC_BWTRx_CLKDIV and FMC_BWTRx_DATLAT bits definitions
- update USB_OTG_GlobalTypeDef registers structure to remove ADP control registers
- add USB_OTG_DOEPMSK_OTEPSPRM and USB_OTG_DOEPINT_OTEPSPR bits definitions
- Remove ADP related bits definitions
- add IS_PCD_ALL_INSTANCE() and IS_HCD_ALL_INSTANCE() macros
V2.4.1 / 09-October-2015
Main Changes
- "stm32f469xx.h",
"stm32f479xx.h"
- Update
-bits definition for DSI_WPCR and DSI_TCCR registers
- Update
-bits definition for DSI_WPCR and DSI_TCCR registers
V2.4.0 / 14-August-2015
+bits definition for DSI_WPCR and DSI_TCCR registersV2.4.0 / 14-August-2015
Main Changes
-
Add support of STM32F469xx and STM32F479xx devices
@@ -238,15 +257,15 @@ Changes
-
Add "stm32f410cx.h", "stm32f410tx.h" and "stm32f410rx.h" files
-
-
Add startup files "startup_stm32f410cx.s", "startup_stm32f410rx.s" and "startup_stm32f410tx.s" for EWARM, MDK-ARM and SW4STM32 toolchains
- Add Linker files "stm32f410cx_flash.icf", "stm32f410cx_sram.icf", "stm32f410rx_flash.icf", "stm32f410tx_sram.icf", "stm32f410tx_flash.icf", and "stm32f410rx_sram.icf" used within EWARM Workspaces
V2.3.2 / 26-June-2015
+Add startup files "startup_stm32f410cx.s", "startup_stm32f410rx.s" and "startup_stm32f410tx.s" for EWARM, MDK-ARM and SW4STM32 toolchains
V2.3.2 / 26-June-2015
Main -Changes
- "stm32f405xx.h", "stm32f407xx.h", "stm32f415xx.h" and "stm32f417xx.h"
- Update FSMC_BTRx_DATAST and FSMC_BWTRx_DATAST (where x can be 1, 2, 3 and 4) mask on 8bits instead of 4bits
- "stm32f427xx.h", "stm32f437xx.h", "stm32f429xx.h" and "stm32f439xx.h"
- Update the defined mask value for SAI_xSR_FLVL_2
- "stm32f415xx.h", "stm32f417xx.h", "stm32f437xx.h" and "stm32f439xx.h"
- HASH alignement with bits namming used in documentation
- Rename HASH_IMR_DINIM to HASH_IMR_DINIE
- Rename HASH_IMR_DCIM to HASH_IMR_DCIE
- Rename HASH_STR_NBW to HASH_STR_NBW
- system_stm32f4xx.c
- Remove __IO on constant table declaration
- Implement workaround to cover RCC limitation regarding peripheral enable delay
- SystemInit_ExtMemCtl() update GPIO configuration when external SDRAM is used
V2.3.1 / 03-April-2015
+Changes- "stm32f405xx.h", "stm32f407xx.h", "stm32f415xx.h" and "stm32f417xx.h"
- Update FSMC_BTRx_DATAST and FSMC_BWTRx_DATAST (where x can be 1, 2, 3 and 4) mask on 8bits instead of 4bits
- "stm32f427xx.h", "stm32f437xx.h", "stm32f429xx.h" and "stm32f439xx.h"
- Update the defined mask value for SAI_xSR_FLVL_2
- "stm32f415xx.h", "stm32f417xx.h", "stm32f437xx.h" and "stm32f439xx.h"
- HASH alignement with bits namming used in documentation
- Rename HASH_IMR_DINIM to HASH_IMR_DINIE
- Rename HASH_IMR_DCIM to HASH_IMR_DCIE
- Rename HASH_STR_NBW to HASH_STR_NBW
- system_stm32f4xx.c
- Remove __IO on constant table declaration
- Implement workaround to cover RCC limitation regarding peripheral enable delay
- SystemInit_ExtMemCtl() update GPIO configuration when external SDRAM is used
V2.3.1 / 03-April-2015
Main Changes-
Header file for all STM32 devices
-- Update SRAM2, SRAM3 and BKPSRAM Bit-Banding base address defined values
- Keep reference to SRAM3 only for STM32F42xx and STM32F43xx devices
- Remove CCMDATARAM_BB_BASE: the CCM Data RAM region is not accessible via Bit-Banding
- Update the RTC_PRER_PREDIV_S defined value to 0x00007FFF instead of 0x00001FFF
V2.3.0 / 02-March-2015
+- Update SRAM2, SRAM3 and BKPSRAM Bit-Banding base address defined values
- Keep reference to SRAM3 only for STM32F42xx and STM32F43xx devices
- Remove CCMDATARAM_BB_BASE: the CCM Data RAM region is not accessible via Bit-Banding
- Update the RTC_PRER_PREDIV_S defined value to 0x00007FFF instead of 0x00001FFF
V2.3.0 / 02-March-2015
Main
Changes
-
@@ -259,7 +278,7 @@ Changes
- Add missing bits definition in the EXTI IMR, EMR, RTSR, FTSR, SWIER and PR registers
- Update RCC_AHB1RSTR_OTGHRST bit definition
- Update PWR_CR_VOS bits definition for STM32F40xx and STM32F41xx devices
update SAI_xCR1_MCKDIV bit definition
V2.2.0 /
+V2.2.0 /
15-December-2014
Main
Changes
@@ -284,7 +303,7 @@ definition for CAN, FMC and USB peripherals
GPIO_TypeDef: change the BSRR register definition, the two 16-bits definition BSRRH and BSRRL -are merged in a single 32-bits definition BSRR
V2.1.0 / 19-June-2014
+are merged in a single 32-bits definition BSRRV2.1.0 / 19-June-2014
Main
Changes
-
V2.0.0 / 18-February-2014
+V2.0.0 / 18-February-2014
@@ -522,7 +541,7 @@ ChangesV1.3.0 / 08-November-2013
+V1.3.0 / 08-November-2013
Main
Changes
V1.2.1 /
+ V1.2.1 /
19-September-2013
Main
@@ -546,7 +565,7 @@ Changes
system_stm32f4xx.c : Update FMC SDRAM configuration (RBURST mode activation)
Update startup files "startup_stm32f427_437xx.s" and "startup_stm32f429_439xx.s" for TrueSTUDIO and Ride toolchains and maintain the old name of startup files for legacy purpose
- V1.2.0 /
+ V1.2.0 /
11-September-2013
Main
@@ -565,7 +584,7 @@ STOP Mode current, SAI, PCROP, SDRAM and DMA2DUpdate the system configuration to support all STM32F4xx Family devices.
- V1.1.0 /
+ V1.1.0 /
11-January-2013
Main
@@ -592,23 +611,23 @@ address and data lines
of PSRAM (PSRAM is available only on STM324xG-EVAL RevA) and update timing
values
-V1.0.2 / 05-March-2012
+V1.0.2 / 05-March-2012
Main
Changes
- - All source files: license disclaimer text update and add link to the License file on ST Internet.
V1.0.1 / 28-December-2011
Main
+ - All source files: license disclaimer text update and add link to the License file on ST Internet.
V1.0.1 / 28-December-2011
Main
Changes
-- All source files: update disclaimer to add reference to the new license agreement
- stm32f4xx.h
- Correct bit definition: RCC_AHB2RSTR_HSAHRST changed to RCC_AHB2RSTR_HASHRST
V1.0.0 / 30-September-2011
Main
+- All source files: update disclaimer to add reference to the new license agreement
- stm32f4xx.h
- Correct bit definition: RCC_AHB2RSTR_HSAHRST changed to RCC_AHB2RSTR_HASHRST
V1.0.0 / 30-September-2011
Main
Changes
-- First official release for STM32F40x/41x devices
- Add startup file for TASKING toolchain
- system_stm32f4xx.c: driver's comments update
V1.0.0RC2 / 26-September-2011
Main
+- First official release for STM32F40x/41x devices
- Add startup file for TASKING toolchain
- system_stm32f4xx.c: driver's comments update
V1.0.0RC2 / 26-September-2011
Main
Changes
-- Official version (V1.0.0) Release Candidate2 for STM32F40x/41x devices
- stm32f4xx.h
- Add define for Cortex-M4 revision __CM4_REV
- Correct RCC_CFGR_PPRE2_DIV16 bit (in RCC_CFGR register) value to 0x0000E000
- Correct some bits definition to be in line with naming used in the Reference Manual (RM0090)
- GPIO_OTYPER_IDR_x changed to GPIO_IDR_IDR_x
- GPIO_OTYPER_ODR_x changed to GPIO_ODR_ODR_x
- SYSCFG_PMC_MII_RMII changed to SYSCFG_PMC_MII_RMII_SEL
- RCC_APB2RSTR_SPI1 changed to RCC_APB2RSTR_SPI1RST
- DBGMCU_APB1_FZ_DBG_IWDEG_STOP changed to DBGMCU_APB1_FZ_DBG_IWDG_STOP
- PWR_CR_PMODE changed to PWR_CR_VOS
- PWR_CSR_REGRDY changed to PWR_CSR_VOSRDY
- Add new define RCC_AHB1ENR_CCMDATARAMEN
- Add new defines SRAM2_BASE, CCMDATARAM_BASE and BKPSRAM_BASE
- GPIO_TypeDef structure: in the comment change AFR[2] address mapping to 0x20-0x24 instead of 0x24-0x28
- system_stm32f4xx.c
- SystemInit(): add code to enable the FPU
- SetSysClock(): change PWR_CR_PMODE by PWR_CR_VOS
- SystemInit_ExtMemCtl(): remove commented values
- startup (for all compilers)
- Delete code used to enable the FPU (moved to system_stm32f4xx.c file)
- File’s header updated
V1.0.0RC1 / 25-August-2011
Main
+- Official version (V1.0.0) Release Candidate2 for STM32F40x/41x devices
- stm32f4xx.h
- Add define for Cortex-M4 revision __CM4_REV
- Correct RCC_CFGR_PPRE2_DIV16 bit (in RCC_CFGR register) value to 0x0000E000
- Correct some bits definition to be in line with naming used in the Reference Manual (RM0090)
- GPIO_OTYPER_IDR_x changed to GPIO_IDR_IDR_x
- GPIO_OTYPER_ODR_x changed to GPIO_ODR_ODR_x
- SYSCFG_PMC_MII_RMII changed to SYSCFG_PMC_MII_RMII_SEL
- RCC_APB2RSTR_SPI1 changed to RCC_APB2RSTR_SPI1RST
- DBGMCU_APB1_FZ_DBG_IWDEG_STOP changed to DBGMCU_APB1_FZ_DBG_IWDG_STOP
- PWR_CR_PMODE changed to PWR_CR_VOS
- PWR_CSR_REGRDY changed to PWR_CSR_VOSRDY
- Add new define RCC_AHB1ENR_CCMDATARAMEN
- Add new defines SRAM2_BASE, CCMDATARAM_BASE and BKPSRAM_BASE
- GPIO_TypeDef structure: in the comment change AFR[2] address mapping to 0x20-0x24 instead of 0x24-0x28
- system_stm32f4xx.c
- SystemInit(): add code to enable the FPU
- SetSysClock(): change PWR_CR_PMODE by PWR_CR_VOS
- SystemInit_ExtMemCtl(): remove commented values
- startup (for all compilers)
- Delete code used to enable the FPU (moved to system_stm32f4xx.c file)
- File’s header updated
V1.0.0RC1 / 25-August-2011
Main
Changes
- Official version (V1.0.0) Release Candidate1 for STM32F4xx devices
-License
+License
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f401xc.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f401xc.s
index 457838798b..8891f3b391 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f401xc.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f401xc.s
@@ -1,4 +1,4 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;*******************************************************************************
;* File Name : startup_stm32f401xc.s
;* Author : MCD Application Team
;* Description : STM32F401xc devices vector table for MDK-ARM toolchain.
@@ -10,33 +10,20 @@
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;********************************************************************************
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; Stack Configuration
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f401xe.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f401xe.s
index cf71ee356c..b93f10fea8 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f401xe.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f401xe.s
@@ -1,4 +1,4 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;*******************************************************************************
;* File Name : startup_stm32f401xe.s
;* Author : MCD Application Team
;* Description : STM32F401xe devices vector table for MDK-ARM toolchain.
@@ -10,33 +10,20 @@
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;********************************************************************************
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; Stack Configuration
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f405xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f405xx.s
index 0afddd07da..9d88f9ebf9 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f405xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f405xx.s
@@ -1,4 +1,4 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;*******************************************************************************
;* File Name : startup_stm32f405xx.s
;* Author : MCD Application Team
;* Description : STM32F405xx devices vector table for MDK-ARM toolchain.
@@ -10,33 +10,20 @@
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;********************************************************************************
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; Stack Configuration
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f407xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f407xx.s
index a7dea7cf76..c36bd576e0 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f407xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f407xx.s
@@ -1,4 +1,4 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;*******************************************************************************
;* File Name : startup_stm32f407xx.s
;* Author : MCD Application Team
;* Description : STM32F407xx devices vector table for MDK-ARM toolchain.
@@ -10,33 +10,20 @@
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;********************************************************************************
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; Stack Configuration
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f410cx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f410cx.s
index b902f5096c..254c002c45 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f410cx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f410cx.s
@@ -1,4 +1,4 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;*******************************************************************************
;* File Name : startup_stm32f410cx.s
;* Author : MCD Application Team
;* Description : STM32F410Cx devices vector table for MDK-ARM toolchain.
@@ -10,33 +10,20 @@
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;********************************************************************************
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; Stack Configuration
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f410rx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f410rx.s
index 55b064958d..947961af91 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f410rx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f410rx.s
@@ -1,4 +1,4 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;*******************************************************************************
;* File Name : startup_stm32f410rx.s
;* Author : MCD Application Team
;* Description : STM32F410Rx devices vector table for MDK-ARM toolchain.
@@ -10,33 +10,20 @@
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;********************************************************************************
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; Stack Configuration
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f410tx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f410tx.s
index bfe2f48dbe..f34bd48444 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f410tx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f410tx.s
@@ -1,4 +1,4 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;*******************************************************************************
;* File Name : startup_stm32f410tx.s
;* Author : MCD Application Team
;* Description : STM32F410Tx devices vector table for MDK-ARM toolchain.
@@ -10,33 +10,20 @@
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;********************************************************************************
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; Stack Configuration
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f411xe.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f411xe.s
index 376d7f5845..c322baf3f8 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f411xe.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f411xe.s
@@ -1,4 +1,4 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;*******************************************************************************
;* File Name : startup_stm32f411xe.s
;* Author : MCD Application Team
;* Description : STM32F411xExx devices vector table for MDK-ARM toolchain.
@@ -10,33 +10,20 @@
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;********************************************************************************
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; Stack Configuration
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f412cx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f412cx.s
index e6ec194302..403265593e 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f412cx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f412cx.s
@@ -1,4 +1,4 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;*******************************************************************************
;* File Name : startup_stm32f412cx.s
;* Author : MCD Application Team
;* Description : STM32F412Cx devices vector table for MDK-ARM toolchain.
@@ -10,33 +10,20 @@
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;********************************************************************************
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; Stack Configuration
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f412rx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f412rx.s
index 6c2889ad89..a51dc7bd8f 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f412rx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f412rx.s
@@ -1,4 +1,4 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;*******************************************************************************
;* File Name : startup_stm32f412rx.s
;* Author : MCD Application Team
;* Description : STM32F412Rx devices vector table for MDK-ARM toolchain.
@@ -10,33 +10,20 @@
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;********************************************************************************
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; Stack Configuration
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f412vx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f412vx.s
index 54a12a0ce1..eb18b03f38 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f412vx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f412vx.s
@@ -1,4 +1,4 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;*******************************************************************************
;* File Name : startup_stm32f412vx.s
;* Author : MCD Application Team
;* Description : STM32F412Vx devices vector table for MDK-ARM toolchain.
@@ -10,33 +10,20 @@
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;********************************************************************************
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; Stack Configuration
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f412zx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f412zx.s
index 1d431435f2..bd08326790 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f412zx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f412zx.s
@@ -1,4 +1,4 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;*******************************************************************************
;* File Name : startup_stm32f412zx.s
;* Author : MCD Application Team
;* Description : STM32F412Zx devices vector table for MDK-ARM toolchain.
@@ -10,33 +10,20 @@
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;********************************************************************************
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; Stack Configuration
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f413xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f413xx.s
index c83376b4ba..0cbea10153 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f413xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f413xx.s
@@ -1,4 +1,4 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;*******************************************************************************
;* File Name : startup_stm32f413xx.s
;* Author : MCD Application Team
;* Description : STM32F413xx devices vector table for MDK-ARM toolchain.
@@ -10,33 +10,20 @@
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;********************************************************************************
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; Stack Configuration
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f415xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f415xx.s
index 0959b624a6..efb68fd141 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f415xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f415xx.s
@@ -1,4 +1,4 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;*******************************************************************************
;* File Name : startup_stm32f415xx.s
;* Author : MCD Application Team
;* Description : STM32F415xx devices vector table for MDK-ARM toolchain.
@@ -10,33 +10,20 @@
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;********************************************************************************
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; Stack Configuration
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f417xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f417xx.s
index b5d80d85cc..863060b0e1 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f417xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f417xx.s
@@ -1,4 +1,4 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;*******************************************************************************
;* File Name : startup_stm32f417xx.s
;* Author : MCD Application Team
;* Description : STM32F417xx devices vector table for MDK-ARM toolchain.
@@ -10,33 +10,20 @@
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;********************************************************************************
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; Stack Configuration
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f423xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f423xx.s
index c1a5664a23..f10a7d0ed0 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f423xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f423xx.s
@@ -1,4 +1,4 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;*******************************************************************************
;* File Name : startup_stm32f423xx.s
;* Author : MCD Application Team
;* Description : STM32F423xx devices vector table for MDK-ARM toolchain.
@@ -10,33 +10,20 @@
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;********************************************************************************
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; Stack Configuration
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f427xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f427xx.s
index 418965aefb..22f8094401 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f427xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f427xx.s
@@ -1,4 +1,4 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;*******************************************************************************
;* File Name : startup_stm32f427xx.s
;* Author : MCD Application Team
;* Description : STM32F427x devices vector table for MDK-ARM toolchain.
@@ -8,33 +8,20 @@
;* - Set the vector table entries with the exceptions ISR address
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;********************************************************************************
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; Stack Configuration
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f429xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f429xx.s
index 6ba6ac7fc7..d3a0a94b2e 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f429xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f429xx.s
@@ -1,4 +1,4 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;*******************************************************************************
;* File Name : startup_stm32f429xx.s
;* Author : MCD Application Team
;* Description : STM32F429x devices vector table for MDK-ARM toolchain.
@@ -10,33 +10,20 @@
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;********************************************************************************
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; Stack Configuration
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f437xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f437xx.s
index faefef0b90..89c118a2dd 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f437xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f437xx.s
@@ -1,4 +1,4 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;*******************************************************************************
;* File Name : startup_stm32f437xx.s
;* Author : MCD Application Team
;* Description : STM32F437x devices vector table for MDK-ARM toolchain.
@@ -10,33 +10,20 @@
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;********************************************************************************
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; Stack Configuration
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f439xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f439xx.s
index 85721e8285..8c62fd23ec 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f439xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f439xx.s
@@ -1,4 +1,4 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;*******************************************************************************
;* File Name : startup_stm32f439xx.s
;* Author : MCD Application Team
;* Description : STM32F439x devices vector table for MDK-ARM toolchain.
@@ -10,33 +10,20 @@
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;********************************************************************************
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; Stack Configuration
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f446xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f446xx.s
index de75b4cce5..cc93ad7e49 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f446xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f446xx.s
@@ -1,4 +1,4 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;*******************************************************************************
;* File Name : startup_stm32f446xx.s
;* Author : MCD Application Team
;* Description : STM32F446x devices vector table for MDK-ARM toolchain.
@@ -8,33 +8,20 @@
;* - Set the vector table entries with the exceptions ISR address
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;********************************************************************************
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; Stack Configuration
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f469xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f469xx.s
index c6dfa08c67..8101aaeeca 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f469xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f469xx.s
@@ -1,4 +1,4 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;*******************************************************************************
;* File Name : startup_stm32f469xx.s
;* Author : MCD Application Team
;* Description : STM32F469x devices vector table for MDK-ARM toolchain.
@@ -10,33 +10,20 @@
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;********************************************************************************
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; Stack Configuration
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f479xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f479xx.s
index 888ec221b9..c66dfb2be2 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f479xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f479xx.s
@@ -1,4 +1,4 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;*******************************************************************************
;* File Name : startup_stm32f479xx.s
;* Author : MCD Application Team
;* Description : STM32F479x devices vector table for MDK-ARM toolchain.
@@ -10,33 +10,20 @@
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;********************************************************************************
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; Stack Configuration
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xc.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xc.s
index 325f119fc4..413ff2dd1c 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xc.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xc.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xe.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xe.s
index eb8959e0b2..9c0365b0a2 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xe.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xe.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,37 +62,40 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
bx lr
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f405xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f405xx.s
index 628c57efec..9329632479 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f405xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f405xx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s
index 75c97e9abc..8c1612047c 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410cx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410cx.s
index d44de86099..c063b38d80 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410cx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410cx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410rx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410rx.s
index 2c8250aa7d..525f9b9ec7 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410rx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410rx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410tx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410tx.s
index 43bde68565..f9533d1a67 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410tx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410tx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f411xe.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f411xe.s
index ad12201155..bc1631b935 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f411xe.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f411xe.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412cx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412cx.s
index 30301904d2..cfdb79bc02 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412cx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412cx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,37 +62,40 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
bx lr
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412rx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412rx.s
index 06377d97d7..05dce21556 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412rx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412rx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412vx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412vx.s
index 4c5a42e865..b6e99badf0 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412vx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412vx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412zx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412zx.s
index 10411aa683..035a4723f3 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412zx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412zx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f413xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f413xx.s
index 77d079cfa6..e4fdc23516 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f413xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f413xx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f415xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f415xx.s
index 36aca9cc04..ad0b242df1 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f415xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f415xx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f417xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f417xx.s
index 4e9c137d09..70b7e981c6 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f417xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f417xx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f423xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f423xx.s
index c9e93753fd..92d6e1ffea 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f423xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f423xx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f427xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f427xx.s
index 6cb9fb655e..6384221551 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f427xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f427xx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,37 +62,40 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
bx lr
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f429xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f429xx.s
index d0d3b3a329..b0311ffc4e 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f429xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f429xx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f437xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f437xx.s
index 46468d362d..a110faf141 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f437xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f437xx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f439xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f439xx.s
index b97cfc3e22..4bd6b6fd0a 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f439xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f439xx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f446xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f446xx.s
index a751533537..804f286bdd 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f446xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f446xx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f469xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f469xx.s
index b7a127f9c4..c52b895e93 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f469xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f469xx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f479xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f479xx.s
index 2b9c91064e..cc70ac5b6f 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f479xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f479xx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f401xc.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f401xc.s
index f987c5339a..a326e61ab9 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f401xc.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f401xc.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f401xc.s
;* Author : MCD Application Team
;* Description : STM32F401xCxx devices vector table for EWARM toolchain.
@@ -13,29 +13,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f401xe.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f401xe.s
index 68bf762b91..1342ced8bb 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f401xe.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f401xe.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f401xe.s
;* Author : MCD Application Team
;* Description : STM32F401xExx devices vector table for EWARM toolchain.
@@ -13,29 +13,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f405xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f405xx.s
index f4ca8320fe..ab5c263e5f 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f405xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f405xx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f405xx.s
;* Author : MCD Application Team
;* Description : STM32F405xx devices vector table for EWARM toolchain.
@@ -12,29 +12,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f407xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f407xx.s
index 57738bbdc3..261246e249 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f407xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f407xx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f407xx.s
;* Author : MCD Application Team
;* Description : STM32F407xx devices vector table for EWARM toolchain.
@@ -12,29 +12,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f410cx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f410cx.s
index 2c66d25424..0a545d352a 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f410cx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f410cx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f410cx.s
;* Author : MCD Application Team
;* Description : STM32F410Cx devices vector table for EWARM toolchain.
@@ -13,29 +13,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f410rx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f410rx.s
index f301994f41..933e77a38e 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f410rx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f410rx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f410rx.s
;* Author : MCD Application Team
;* Description : STM32F410Rx devices vector table for EWARM toolchain.
@@ -13,29 +13,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f410tx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f410tx.s
index 20c8d53c17..3315a9be11 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f410tx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f410tx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f410tx.s
;* Author : MCD Application Team
;* Description : STM32F410Tx devices vector table for EWARM toolchain.
@@ -13,29 +13,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f411xe.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f411xe.s
index b56c8f521d..9f2a6c67e0 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f411xe.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f411xe.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f411xe.s
;* Author : MCD Application Team
;* Description : STM32F411xExx devices vector table for EWARM toolchain.
@@ -13,29 +13,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f412cx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f412cx.s
index dd77bf0cd7..d561b12bbc 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f412cx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f412cx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f412cx.s
;* Author : MCD Application Team
;* Description : STM32F412Cx devices vector table for EWARM toolchain.
@@ -13,29 +13,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f412rx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f412rx.s
index 14bb437fcc..220280b28c 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f412rx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f412rx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f412rx.s
;* Author : MCD Application Team
;* Description : STM32F412Rx devices vector table for EWARM toolchain.
@@ -13,29 +13,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f412vx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f412vx.s
index 4312c16f9c..107ca64263 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f412vx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f412vx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f412vx.s
;* Author : MCD Application Team
;* Description : STM32F412Vx devices vector table for EWARM toolchain.
@@ -13,29 +13,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f412zx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f412zx.s
index f065a99560..cd4189e6da 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f412zx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f412zx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f412zx.s
;* Author : MCD Application Team
;* Description : STM32F412Zx devices vector table for EWARM toolchain.
@@ -13,29 +13,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f413xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f413xx.s
index da2b6b6924..4ae7c197ba 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f413xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f413xx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f413xx.s
;* Author : MCD Application Team
;* Description : STM32F413xx devices vector table for EWARM toolchain.
@@ -13,29 +13,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f415xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f415xx.s
index 932a34d2ad..9a8070dc02 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f415xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f415xx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f415xx.s
;* Author : MCD Application Team
;* Description : STM32F415xx devices vector table for EWARM toolchain.
@@ -12,29 +12,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f417xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f417xx.s
index 0a087c423e..dd9a54dad2 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f417xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f417xx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f417xx.s
;* Author : MCD Application Team
;* Description : STM32F417xx devices vector table for EWARM toolchain.
@@ -12,29 +12,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f423xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f423xx.s
index a1c60ae46a..b154532aa4 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f423xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f423xx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f423xx.s
;* Author : MCD Application Team
;* Description : STM32F423xx devices vector table for EWARM toolchain.
@@ -13,29 +13,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f427xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f427xx.s
index c3e08b6aa5..28912fe2b4 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f427xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f427xx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f427xx.s
;* Author : MCD Application Team
;* Description : STM32F427xx devices vector table for EWARM toolchain.
@@ -12,29 +12,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f429xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f429xx.s
index 242307e967..475dc6b763 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f429xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f429xx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f429xx.s
;* Author : MCD Application Team
;* Description : STM32F429xx devices vector table for EWARM toolchain.
@@ -12,29 +12,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f437xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f437xx.s
index 4ad01cf25a..d8703371cd 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f437xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f437xx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f437xx.s
;* Author : MCD Application Team
;* Description : STM32F437xx devices vector table for EWARM toolchain.
@@ -12,29 +12,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f439xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f439xx.s
index 59e3fef3d4..d91d4919ba 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f439xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f439xx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f439xx.s
;* Author : MCD Application Team
;* Description : STM32F439xx devices vector table for EWARM toolchain.
@@ -12,29 +12,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f446xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f446xx.s
index 85c7c51f69..b3d6720043 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f446xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f446xx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f446xx.s
;* Author : MCD Application Team
;* Description : STM32F446xx devices vector table for EWARM toolchain.
@@ -12,29 +12,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f469xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f469xx.s
index 4089305089..d1f8f3a280 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f469xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f469xx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f469xx.s
;* Author : MCD Application Team
;* Description : STM32F469xx devices vector table for EWARM toolchain.
@@ -12,29 +12,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f479xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f479xx.s
index 88eaddcf3f..3b8cac9ae0 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f479xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f479xx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f479xx.s
;* Author : MCD Application Team
;* Description : STM32F479xx devices vector table for EWARM toolchain.
@@ -12,29 +12,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;* © Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c
index 3303f969d9..d1acf9ed2e 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c
@@ -22,29 +22,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -103,11 +87,29 @@
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
STM32F479xx */
-/*!< Uncomment the following line if you need to relocate your vector Table in
- Internal SRAM. */
+/* Note: Following vector table addresses must be defined in line with linker
+ configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+ anywhere in Flash or Sram, else the vector table is kept at the automatic
+ remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+/*!< Uncomment the following line if you need to relocate your vector Table
+ in Sram else user remap will be done in Flash. */
/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
- This value must be a multiple of 0x200. */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+#else
+#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+#endif /* VECT_TAB_SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
/******************************************************************************/
/**
@@ -169,35 +171,15 @@ void SystemInit(void)
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
#endif
- /* Reset the RCC clock configuration to the default reset state ------------*/
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
-
- /* Reset CFGR register */
- RCC->CFGR = 0x00000000;
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFF;
-
- /* Reset PLLCFGR register */
- RCC->PLLCFGR = 0x24003010;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000;
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
- /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
+ /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
}
/**
@@ -403,6 +385,7 @@ void SystemInit_ExtMemCtl(void)
/* PALL command */
FMC_Bank5_6->SDCMR = 0x00000012;
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
@@ -411,6 +394,7 @@ void SystemInit_ExtMemCtl(void)
/* Auto refresh command */
FMC_Bank5_6->SDCMR = 0x00000073;
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
@@ -419,6 +403,7 @@ void SystemInit_ExtMemCtl(void)
/* MRD register program */
FMC_Bank5_6->SDCMR = 0x00046014;
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
@@ -608,6 +593,7 @@ void SystemInit_ExtMemCtl(void)
/* PALL command */
FMC_Bank5_6->SDCMR = 0x00000012;
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
@@ -620,6 +606,7 @@ void SystemInit_ExtMemCtl(void)
#else
FMC_Bank5_6->SDCMR = 0x00000073;
#endif /* STM32F446xx */
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
@@ -632,6 +619,7 @@ void SystemInit_ExtMemCtl(void)
#else
FMC_Bank5_6->SDCMR = 0x00046014;
#endif /* STM32F446xx */
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
index 889db8f18f..299ed70498 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
@@ -7,7 +7,7 @@
******************************************************************************
* @attention
*
- * © Copyright (c) 2018 STMicroelectronics.
+ * © Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -23,7 +23,7 @@
#define STM32_HAL_LEGACY
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -38,7 +38,6 @@
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
-
/**
* @}
*/
@@ -236,6 +235,16 @@
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
+#if defined(STM32G4) || defined(STM32H7)
+#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
+#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
+#endif
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
+#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
+#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
+#endif
+
/**
* @}
*/
@@ -296,8 +305,22 @@
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
+#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
+#endif
+
#endif /* STM32L4 */
+#if defined(STM32G0)
+#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
+#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM
+#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM
+
+#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM
+#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM
+#endif
+
#if defined(STM32H7)
#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
@@ -355,6 +378,9 @@
#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
+#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT
+#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
+
#endif /* STM32H7 */
/**
@@ -450,7 +476,9 @@
#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
-#endif
+#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
+#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
+#endif /* STM32H7 */
/**
* @}
@@ -486,6 +514,13 @@
#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
+#if defined(STM32G4)
+
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster
+#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD
+#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
+#endif /* STM32G4 */
/**
* @}
*/
@@ -494,7 +529,7 @@
/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
* @{
*/
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7)
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
@@ -547,30 +582,37 @@
#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
-#endif
+
+#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \
+ defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx)
+#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
+#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
+#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
+#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
+#endif /* STM32H7 */
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32H7)
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32H7*/
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB*/
#if defined(STM32L1)
- #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
- #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
- #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
- #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
+#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
#endif /* STM32L1 */
#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
- #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
- #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
- #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
#endif /* STM32F0 || STM32F3 || STM32F1 */
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
@@ -599,6 +641,146 @@
#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
+
+#if defined(STM32G4)
+#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig
+#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
+#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable
+#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset
+#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A
+#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B
+#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
+#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
+#endif /* STM32G4 */
+
+#if defined(STM32H7)
+#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+
+#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+#endif /* STM32H7 */
+
+#if defined(STM32F3)
+/** @brief Constants defining available sources associated to external events.
+ */
+#define HRTIM_EVENTSRC_1 (0x00000000U)
+#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0)
+#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
+#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
+
+/** @brief Constants defining the DLL calibration periods (in micro seconds)
+ */
+#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
+#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
+#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
+#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
+
+#endif /* STM32F3 */
/**
* @}
*/
@@ -738,6 +920,17 @@
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
+#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
+#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
+#endif
+
+#if defined(STM32L4) || defined(STM32L5)
+#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER
+#elif defined(STM32G4)
+#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED
+#endif
+
/**
* @}
*/
@@ -748,16 +941,15 @@
#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
#if defined(STM32H7)
- #define I2S_IT_TXE I2S_IT_TXP
- #define I2S_IT_RXNE I2S_IT_RXP
+#define I2S_IT_TXE I2S_IT_TXP
+#define I2S_IT_RXNE I2S_IT_RXP
- #define I2S_FLAG_TXE I2S_FLAG_TXP
- #define I2S_FLAG_RXNE I2S_FLAG_RXP
- #define I2S_FLAG_FRE I2S_FLAG_TIFRE
+#define I2S_FLAG_TXE I2S_FLAG_TXP
+#define I2S_FLAG_RXNE I2S_FLAG_RXP
#endif
#if defined(STM32F7)
- #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
+#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
#endif
/**
* @}
@@ -824,6 +1016,16 @@
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
+#if defined(STM32H7)
+#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
+#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
+
+#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
+#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
+#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
+#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
+#endif /* STM32H7 */
+
/**
* @}
*/
@@ -882,16 +1084,16 @@
#if defined(STM32H7)
- #define SPI_FLAG_TXE SPI_FLAG_TXP
- #define SPI_FLAG_RXNE SPI_FLAG_RXP
+#define SPI_FLAG_TXE SPI_FLAG_TXP
+#define SPI_FLAG_RXNE SPI_FLAG_RXP
- #define SPI_IT_TXE SPI_IT_TXP
- #define SPI_IT_RXNE SPI_IT_RXP
+#define SPI_IT_TXE SPI_IT_TXP
+#define SPI_IT_RXNE SPI_IT_RXP
- #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
- #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
- #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
- #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
+#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
+#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
+#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
+#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
#endif /* STM32H7 */
@@ -971,6 +1173,24 @@
#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
#endif
+#if defined(STM32H7)
+#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1
+#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2
+#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1
+#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2
+#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1
+#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2
+#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1
+#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1
+#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2
+#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1
+#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2
+#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2
+#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1
+#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2
+#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
+#endif
+
/**
* @}
*/
@@ -1199,6 +1419,30 @@
#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
+
+#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
+
+#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
+#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
+#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT
+#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT
+
+#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt
+#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End
+#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT
+#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt
+#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End
+#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT
+#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt
+#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End
+#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
+#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
+
+#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
/**
* @}
*/
@@ -1212,7 +1456,8 @@
#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
-#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
+ )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
#if defined(STM32L0)
@@ -1220,7 +1465,15 @@
#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
#endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
-#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
+ )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
+#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
+#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
+#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
+#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
+#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode
+#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */
+
/**
* @}
*/
@@ -1236,9 +1489,9 @@
#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
- /**
+/**
* @}
- */
+ */
/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
* @{
@@ -1248,18 +1501,21 @@
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
-#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\
+ )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7)
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
-#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 */
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
#if defined(STM32F4)
#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
@@ -1271,13 +1527,20 @@
#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA
#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA
#endif /* STM32F4 */
- /**
+/**
* @}
- */
+ */
/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
* @{
*/
+
+#if defined(STM32G0)
+#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
+#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
+#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
+#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
+#endif
#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
@@ -1321,9 +1584,9 @@
#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
- /**
+/**
* @}
- */
+ */
/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
* @{
@@ -1350,14 +1613,14 @@
#define HAL_TIM_DMAError TIM_DMAError
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
-#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0)
+#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
-#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */
+#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
/**
* @}
*/
@@ -1572,15 +1835,15 @@
#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
#if defined(STM32H7)
- #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
- #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
- #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
- #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
#else
- #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
- #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
- #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
- #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
#endif /* STM32H7 */
#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
@@ -1791,8 +2054,8 @@
*/
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
- ((WAVE) == DAC_WAVE_NOISE)|| \
- ((WAVE) == DAC_WAVE_TRIANGLE))
+ ((WAVE) == DAC_WAVE_NOISE)|| \
+ ((WAVE) == DAC_WAVE_TRIANGLE))
/**
* @}
@@ -1848,7 +2111,7 @@
#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
#if defined(STM32H7)
- #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
+#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
#endif
/**
@@ -1985,7 +2248,8 @@
#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
-#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\
+ )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
@@ -2476,12 +2740,28 @@
#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
+
+#if defined(STM32H7)
+#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE
+#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
+
+#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/
+#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
+
+
+#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
+#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
+#endif
+
#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
+
#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
@@ -2814,6 +3094,15 @@
#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
+#if defined(STM32L1)
+#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
+#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
+#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
+#endif /* STM32L1 */
+
#if defined(STM32F4)
#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
@@ -2928,9 +3217,8 @@
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
-#if defined(STM32L4)
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
-#elif defined(STM32WB) || defined(STM32G0)
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
#endif
@@ -3058,7 +3346,7 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
-#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx)
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@@ -3078,19 +3366,19 @@
#else
#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
#endif /* STM32F1 */
#define IS_ALARM IS_RTC_ALARM
@@ -3166,22 +3454,22 @@
#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
-#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
-#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
-#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
+#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
+#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
+#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
/* alias CMSIS for compatibilities */
#define SDIO_IRQn SDMMC1_IRQn
#define SDIO_IRQHandler SDMMC1_IRQHandler
#endif
-#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2)
+#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
#endif
-#if defined(STM32H7)
+#if defined(STM32H7) || defined(STM32L5)
#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
@@ -3274,6 +3562,13 @@
#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7)
+#define USART_OVERSAMPLING_16 0x00000000U
+#define USART_OVERSAMPLING_8 USART_CR1_OVER8
+
+#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
+ ((__SAMPLING__) == USART_OVERSAMPLING_8))
+#endif /* STM32F0 || STM32F3 || STM32F7 */
/**
* @}
*/
@@ -3421,18 +3716,28 @@
/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
* @{
*/
-#if defined (STM32H7) || defined (STM32F3)
-#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
-#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
-#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
-#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
-#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
-#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
+#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
+#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
+#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
+#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
+#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
+#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
+#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
#endif
/**
* @}
*/
+/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
+#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
+#endif /* STM32L4 || STM32F4 || STM32F7 */
+/**
+ * @}
+ */
+
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
* @{
*/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/Legacy/stm32f4xx_hal_can_legacy.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/Legacy/stm32f4xx_hal_can_legacy.h
index 7788f06c2c..aacf0f0727 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/Legacy/stm32f4xx_hal_can_legacy.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/Legacy/stm32f4xx_hal_can_legacy.h
@@ -6,13 +6,29 @@
******************************************************************************
* @attention
*
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
+ * © COPYRIGHT(c) 2017 STMicroelectronics
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h
index 5b800df7de..209864d530 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h
@@ -197,6 +197,18 @@ typedef enum
* @}
*/
+/* Exported variables --------------------------------------------------------*/
+
+/** @addtogroup HAL_Exported_Variables
+ * @{
+ */
+extern __IO uint32_t uwTick;
+extern uint32_t uwTickPrio;
+extern HAL_TickFreqTypeDef uwTickFreq;
+/**
+ * @}
+ */
+
/* Exported functions --------------------------------------------------------*/
/** @addtogroup HAL_Exported_Functions
* @{
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h
index badeabc401..a041e76965 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h
@@ -28,6 +28,9 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
+/* Include low level driver */
+#include "stm32f4xx_ll_adc.h"
+
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h
index ed38931dc0..b0cdd2abd3 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h
@@ -304,17 +304,18 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
*/
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \
- defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
- defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+ defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \
+ defined(STM32F412Cx)
#define IS_ADC_CHANNEL(CHANNEL) ((CHANNEL) <= ADC_CHANNEL_18)
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE ||
- STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE ||
+ STM32F410xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+
+#if defined(STM32F411xE) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || \
+ defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx)
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18) || \
((CHANNEL) == ADC_CHANNEL_TEMPSENSOR))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+#endif /* STM32F411xE || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \
((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h
index 0611a6521a..062abd6925 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h
@@ -255,7 +255,7 @@ typedef enum
HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID = 0x08U, /*!< CAN Rx FIFO 1 message pending callback ID */
HAL_CAN_RX_FIFO1_FULL_CB_ID = 0x09U, /*!< CAN Rx FIFO 1 full callback ID */
HAL_CAN_SLEEP_CB_ID = 0x0AU, /*!< CAN Sleep callback ID */
- HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID = 0x0BU, /*!< CAN Wake Up fropm Rx msg callback ID */
+ HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID = 0x0BU, /*!< CAN Wake Up from Rx msg callback ID */
HAL_CAN_ERROR_CB_ID = 0x0CU, /*!< CAN Error callback ID */
HAL_CAN_MSPINIT_CB_ID = 0x0DU, /*!< CAN MspInit callback ID */
@@ -295,11 +295,11 @@ typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to
#define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */
#define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */
#define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
-#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 1 transmit failure due to tranmit error */
-#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
-#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to tranmit error */
-#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
-#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 1 transmit failure due to tranmit error */
+#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 0 transmit failure due to transmit error */
+#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 1 transmit failure due to arbitration lost */
+#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to transmit error */
+#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 2 transmit failure due to arbitration lost */
+#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 2 transmit failure due to transmit error */
#define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */
#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */
#define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cec.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cec.h
index 3519cbd863..f371a9cf13 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cec.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cec.h
@@ -121,7 +121,7 @@ typedef struct
* b6 Error information
* 0 : No Error
* 1 : Error
- * b5 IP initilisation status
+ * b5 IP initialization status
* 0 : Reset (IP not initialized)
* 1 : Init done (IP initialized. HAL CEC Init function already called)
* b4-b3 (not used)
@@ -138,7 +138,7 @@ typedef struct
* RxState value coding follow below described bitmap :
* b7-b6 (not used)
* xx : Should be set to 00
- * b5 IP initilisation status
+ * b5 IP initialization status
* 0 : Reset (IP not initialized)
* 1 : Init done (IP initialized)
* b4-b2 (not used)
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_conf_template.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_conf_template.h
index 37c8780fa4..afa2f56876 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_conf_template.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_conf_template.h
@@ -79,6 +79,7 @@
#define HAL_PCD_MODULE_ENABLED
#define HAL_HCD_MODULE_ENABLED
#define HAL_FMPI2C_MODULE_ENABLED
+#define HAL_FMPSMBUS_MODULE_ENABLED
#define HAL_SPDIFRX_MODULE_ENABLED
#define HAL_DFSDM_MODULE_ENABLED
#define HAL_LPTIM_MODULE_ENABLED
@@ -163,6 +164,7 @@
#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */
+#define USE_HAL_FMPSMBUS_REGISTER_CALLBACKS 0U /* FMPSMBUS register callback disabled */
#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */
@@ -451,6 +453,10 @@
#include "stm32f4xx_hal_fmpi2c.h"
#endif /* HAL_FMPI2C_MODULE_ENABLED */
+#ifdef HAL_FMPSMBUS_MODULE_ENABLED
+ #include "stm32f4xx_hal_fmpsmbus.h"
+#endif /* HAL_FMPSMBUS_MODULE_ENABLED */
+
#ifdef HAL_SPDIFRX_MODULE_ENABLED
#include "stm32f4xx_hal_spdifrx.h"
#endif /* HAL_SPDIFRX_MODULE_ENABLED */
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cryp.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cryp.h
index 8251ebd255..8596fe7d21 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cryp.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cryp.h
@@ -6,23 +6,23 @@
******************************************************************************
* @attention
*
- * © Copyright (c) 2016 STMicroelectronics.
+ * © Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
+ * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_CRYP_H
#define __STM32F4xx_HAL_CRYP_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
@@ -51,87 +51,98 @@ typedef struct
{
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
This parameter can be a value of @ref CRYP_Data_Type */
- uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
+ uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
128 or 256 bit key length in TinyAES This parameter can be a value of @ref CRYP_Key_Size */
- uint32_t* pKey; /*!< The key used for encryption/decryption */
- uint32_t* pInitVect; /*!< The initialization vector used also as initialization
+ uint32_t *pKey; /*!< The key used for encryption/decryption */
+ uint32_t *pInitVect; /*!< The initialization vector used also as initialization
counter in CTR mode */
- uint32_t Algorithm; /*!< DES/ TDES Algorithm ECB/CBC
+ uint32_t Algorithm; /*!< DES/ TDES Algorithm ECB/CBC
AES Algorithm ECB/CBC/CTR/GCM or CCM
This parameter can be a value of @ref CRYP_Algorithm_Mode */
- uint32_t* Header; /*!< used only in AES GCM and CCM Algorithm for authentication,
+ uint32_t *Header; /*!< used only in AES GCM and CCM Algorithm for authentication,
GCM : also known as Additional Authentication Data
CCM : named B1 composed of the associated data length and Associated Data. */
uint32_t HeaderSize; /*!< The size of header buffer in word */
- uint32_t* B0; /*!< B0 is first authentication block used only in AES CCM mode */
+ uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */
uint32_t DataWidthUnit; /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
+ uint32_t HeaderWidthUnit; /*!< Header Width Unit, this parameter can be value of @ref CRYP_Header_Width_Unit*/
+ uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization
+ Vector only once and to skip configuration for consecutive processings.
+ This parameter can be a value of @ref CRYP_Configuration_Skip */
-}CRYP_ConfigTypeDef;
+} CRYP_ConfigTypeDef;
/**
* @brief CRYP State Structure definition
*/
-
+
typedef enum
{
HAL_CRYP_STATE_RESET = 0x00U, /*!< CRYP not yet initialized or disabled */
HAL_CRYP_STATE_READY = 0x01U, /*!< CRYP initialized and ready for use */
HAL_CRYP_STATE_BUSY = 0x02U /*!< CRYP BUSY, internal processing is ongoing */
-}HAL_CRYP_STATETypeDef;
-
+} HAL_CRYP_STATETypeDef;
+
/**
* @brief CRYP handle Structure definition
*/
-
+
typedef struct __CRYP_HandleTypeDef
{
#if defined (CRYP)
- CRYP_TypeDef *Instance; /*!< CRYP registers base address */
+ CRYP_TypeDef *Instance; /*!< CRYP registers base address */
#else /* AES*/
- AES_TypeDef *Instance; /*!< AES Register base address */
+ AES_TypeDef *Instance; /*!< AES Register base address */
#endif /* End AES or CRYP */
- CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */
-
- FunctionalState AutoKeyDerivation; /*!< Used only in TinyAES to allows to bypass or not key write-up before decryption.
- This parameter can be a value of ENABLE/DISABLE */
-
- uint32_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
+ CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */
+
+ FunctionalState AutoKeyDerivation; /*!< Used only in TinyAES to allows to bypass or not key write-up before decryption.
+ This parameter can be a value of ENABLE/DISABLE */
+
+ uint32_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
+
+ uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
- uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
+ __IO uint16_t CrypHeaderCount; /*!< Counter of header data */
- __IO uint16_t CrypHeaderCount; /*!< Counter of header data */
-
- __IO uint16_t CrypInCount; /*!< Counter of input data */
+ __IO uint16_t CrypInCount; /*!< Counter of input data */
- __IO uint16_t CrypOutCount; /*!< Counter of output data */
-
- uint16_t Size; /*!< length of input data in word */
+ __IO uint16_t CrypOutCount; /*!< Counter of output data */
- uint32_t Phase; /*!< CRYP peripheral phase */
+ uint16_t Size; /*!< length of input data in word */
- DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */
+ uint32_t Phase; /*!< CRYP peripheral phase */
- DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */
+ DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */
- HAL_LockTypeDef Lock; /*!< CRYP locking object */
+ DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< CRYP locking object */
+
+ __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
+
+ __IO uint32_t ErrorCode; /*!< CRYP peripheral error code */
+
+ uint32_t KeyIVConfig; /*!< CRYP peripheral Key and IV configuration flag, used when
+ configuration can be skipped */
+
+ uint32_t SizesSum; /*!< Sum of successive payloads lengths (in bytes), stored
+ for a single signature computation after several
+ messages processing */
- __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
-
- __IO uint32_t ErrorCode; /*!< CRYP peripheral error code */
-
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
- void (*InCpltCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Input FIFO transfer completed callback */
- void (*OutCpltCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Output FIFO transfer completed callback */
- void (*ErrorCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Error callback */
-
- void (* MspInitCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Msp Init callback */
- void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Msp DeInit callback */
+ void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Input FIFO transfer completed callback */
+ void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Output FIFO transfer completed callback */
+ void (*ErrorCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Error callback */
-#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
-}CRYP_HandleTypeDef;
+ void (* MspInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp Init callback */
+ void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp DeInit callback */
+
+#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
+} CRYP_HandleTypeDef;
/**
@@ -152,7 +163,7 @@ typedef enum
HAL_CRYP_MSPINIT_CB_ID = 0x04U, /*!< CRYP MspInit callback ID */
HAL_CRYP_MSPDEINIT_CB_ID = 0x05U /*!< CRYP MspDeInit callback ID */
-}HAL_CRYP_CallbackIDTypeDef;
+} HAL_CRYP_CallbackIDTypeDef;
/**
* @}
*/
@@ -162,7 +173,7 @@ typedef enum
* @{
*/
-typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< pointer to a common CRYP callback function */
+typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< pointer to a common CRYP callback function */
/**
* @}
@@ -181,7 +192,7 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
#define HAL_CRYP_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_CRYP_ERROR_WRITE 0x00000001U /*!< Write error */
#define HAL_CRYP_ERROR_READ 0x00000002U /*!< Read error */
-#define HAL_CRYP_ERROR_DMA 0x00000004U /*!< DMA error */
+#define HAL_CRYP_ERROR_DMA 0x00000004U /*!< DMA error */
#define HAL_CRYP_ERROR_BUSY 0x00000008U /*!< Busy flag error */
#define HAL_CRYP_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */
#define HAL_CRYP_ERROR_NOT_SUPPORTED 0x00000020U /*!< Not supported mode */
@@ -189,21 +200,32 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
#define HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid Callback error */
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
-/**
+/**
* @}
*/
-/** @defgroup CRYP_Data_Width_Unit CRYP Data Width Unit
+/** @defgroup CRYP_Data_Width_Unit CRYP Data Width Unit
* @{
*/
#define CRYP_DATAWIDTHUNIT_WORD 0x00000000U /*!< By default, size unit is word */
-#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is word */
+#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is word */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Header_Width_Unit CRYP Header Width Unit
+ * @{
+ */
-/**
+#define CRYP_HEADERWIDTHUNIT_WORD 0x00000000U /*!< By default, header size unit is word */
+#define CRYP_HEADERWIDTHUNIT_BYTE 0x00000001U /*!< By default, header size unit is byte */
+
+/**
* @}
- */
-
+ */
+
/** @defgroup CRYP_Algorithm_Mode CRYP Algorithm Mode
* @{
*/
@@ -212,14 +234,14 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
#define CRYP_DES_ECB CRYP_CR_ALGOMODE_DES_ECB
#define CRYP_DES_CBC CRYP_CR_ALGOMODE_DES_CBC
#define CRYP_TDES_ECB CRYP_CR_ALGOMODE_TDES_ECB
-#define CRYP_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC
+#define CRYP_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC
#define CRYP_AES_ECB CRYP_CR_ALGOMODE_AES_ECB
#define CRYP_AES_CBC CRYP_CR_ALGOMODE_AES_CBC
#define CRYP_AES_CTR CRYP_CR_ALGOMODE_AES_CTR
#if defined (CRYP_CR_ALGOMODE_AES_GCM)
-#define CRYP_AES_GCM CRYP_CR_ALGOMODE_AES_GCM
+#define CRYP_AES_GCM CRYP_CR_ALGOMODE_AES_GCM
#define CRYP_AES_CCM CRYP_CR_ALGOMODE_AES_CCM
-#endif /* GCM CCM defined*/
+#endif /* GCM CCM defined*/
#else /* AES*/
#define CRYP_AES_ECB 0x00000000U /*!< Electronic codebook chaining algorithm */
#define CRYP_AES_CBC AES_CR_CHMOD_0 /*!< Cipher block chaining algorithm */
@@ -228,7 +250,7 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
#define CRYP_AES_CCM AES_CR_CHMOD_2 /*!< Counter with Cipher Mode */
#endif /* End AES or CRYP */
-/**
+/**
* @}
*/
@@ -240,10 +262,10 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
#define CRYP_KEYSIZE_192B CRYP_CR_KEYSIZE_0
#define CRYP_KEYSIZE_256B CRYP_CR_KEYSIZE_1
#else /* AES*/
-#define CRYP_KEYSIZE_128B 0x00000000U /*!< 128-bit long key */
-#define CRYP_KEYSIZE_256B AES_CR_KEYSIZE /*!< 256-bit long key */
+#define CRYP_KEYSIZE_128B 0x00000000U /*!< 128-bit long key */
+#define CRYP_KEYSIZE_256B AES_CR_KEYSIZE /*!< 256-bit long key */
#endif /* End AES or CRYP */
-/**
+/**
* @}
*/
@@ -261,15 +283,15 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
#define CRYP_DATATYPE_8B AES_CR_DATATYPE_1 /*!< 8-bit data type (byte swapping) */
#define CRYP_DATATYPE_1B AES_CR_DATATYPE /*!< 1-bit data type (bit swapping) */
#endif /* End AES or CRYP */
-
-/**
+
+/**
* @}
*/
/** @defgroup CRYP_Interrupt CRYP Interrupt
* @{
*/
-#if defined (CRYP)
+#if defined (CRYP)
#define CRYP_IT_INI CRYP_IMSCR_INIM /*!< Input FIFO Interrupt */
#define CRYP_IT_OUTI CRYP_IMSCR_OUTIM /*!< Output FIFO Interrupt */
#else /* AES*/
@@ -297,7 +319,7 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
or a key preparation (for AES decryption). */
/* Flags in the RISR register */
#define CRYP_FLAG_OUTRIS 0x01000002U /*!< Output FIFO service raw interrupt status */
-#define CRYP_FLAG_INRIS 0x01000001U /*!< Input FIFO service raw interrupt status*/
+#define CRYP_FLAG_INRIS 0x01000001U /*!< Input FIFO service raw interrupt status*/
#else /* AES*/
/* status flags */
#define CRYP_FLAG_BUSY AES_SR_BUSY /*!< GCM process suspension forbidden */
@@ -312,7 +334,18 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
/**
* @}
*/
-
+
+/** @defgroup CRYP_Configuration_Skip CRYP Key and IV Configuration Skip Mode
+ * @{
+ */
+
+#define CRYP_KEYIVCONFIG_ALWAYS 0x00000000U /*!< Peripheral Key and IV configuration to do systematically */
+#define CRYP_KEYIVCONFIG_ONCE 0x00000001U /*!< Peripheral Key and IV configuration to do only once */
+
+/**
+ * @}
+ */
+
/**
* @}
@@ -336,7 +369,7 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
#else
#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_CRYP_STATE_RESET)
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
-
+
/**
* @brief Enable/Disable the CRYP peripheral.
* @param __HANDLE__: specifies the CRYP handle.
@@ -345,33 +378,33 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
#if defined(CRYP)
#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_CRYPEN)
#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CRYP_CR_CRYPEN)
-#else /* AES*/
+#else /* AES*/
#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= AES_CR_EN)
#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~AES_CR_EN)
-#endif /* End AES or CRYP */
+#endif /* End AES or CRYP */
/** @brief Check whether the specified CRYP status flag is set or not.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values for TinyAES:
- * @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden
- * @arg @ref CRYP_IT_WRERR Write Error
- * @arg @ref CRYP_IT_RDERR Read Error
- * @arg @ref CRYP_IT_CCF Computation Complete
+ * @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden
+ * @arg @ref CRYP_IT_WRERR Write Error
+ * @arg @ref CRYP_IT_RDERR Read Error
+ * @arg @ref CRYP_IT_CCF Computation Complete
* This parameter can be one of the following values for CRYP:
- * @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
- * or a key preparation (for AES decryption).
+ * @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
+ * or a key preparation (for AES decryption).
* @arg CRYP_FLAG_IFEM: Input FIFO is empty
* @arg CRYP_FLAG_IFNF: Input FIFO is not full
* @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
* @arg CRYP_FLAG_OFNE: Output FIFO is not empty
* @arg CRYP_FLAG_OFFU: Output FIFO is full
- * @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
- * @retval The state of __FLAG__ (TRUE or FALSE).
+ * @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
+ * @retval The state of __FLAG__ (TRUE or FALSE).
*/
#define CRYP_FLAG_MASK 0x0000001FU
-#if defined(CRYP)
+#if defined(CRYP)
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
- ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
+ ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
#else /* AES*/
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
#endif /* End AES or CRYP */
@@ -380,12 +413,12 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
* @param __FLAG__: specifies the flag to clear.
* This parameter can be one of the following values:
* @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
- * @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
+ * @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
* @param __HANDLE__: specifies the CRYP handle.
* @retval None
*/
-#if defined(AES)
+#if defined(AES)
#define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT((__HANDLE__)->Instance->CR, (__FLAG__))
@@ -393,37 +426,39 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
* @param __INTERRUPT__: CRYP interrupt source to check
* This parameter can be one of the following values for TinyAES:
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
- * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
+ * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
* @param __HANDLE__: specifies the CRYP handle.
* @retval State of interruption (TRUE or FALSE).
*/
-#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\
+ & (__INTERRUPT__)) == (__INTERRUPT__))
#endif /* AES */
/** @brief Check whether the specified CRYP interrupt is set or not.
* @param __INTERRUPT__: specifies the interrupt to check.
* This parameter can be one of the following values for TinyAES:
- * @arg @ref CRYP_IT_WRERR Write Error
- * @arg @ref CRYP_IT_RDERR Read Error
- * @arg @ref CRYP_IT_CCF Computation Complete
+ * @arg @ref CRYP_IT_WRERR Write Error
+ * @arg @ref CRYP_IT_RDERR Read Error
+ * @arg @ref CRYP_IT_CCF Computation Complete
* This parameter can be one of the following values for CRYP:
* @arg CRYP_IT_INI: Input FIFO service masked interrupt status
* @arg CRYP_IT_OUTI: Output FIFO service masked interrupt status
* @param __HANDLE__: specifies the CRYP handle.
* @retval The state of __INTERRUPT__ (TRUE or FALSE).
*/
-#if defined(CRYP)
-#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
+#if defined(CRYP)
+#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR\
+ & (__INTERRUPT__)) == (__INTERRUPT__))
#else /* AES*/
#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
#endif /* End AES or CRYP */
/**
- * @brief Enable the CRYP interrupt.
+ * @brief Enable the CRYP interrupt.
* @param __INTERRUPT__: CRYP Interrupt.
- * This parameter can be one of the following values for TinyAES:
+ * This parameter can be one of the following values for TinyAES:
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
* This parameter can be one of the following values for CRYP:
@@ -432,16 +467,16 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
* @param __HANDLE__: specifies the CRYP handle.
* @retval None
*/
-#if defined(CRYP)
+#if defined(CRYP)
#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__))
-#else /* AES*/
+#else /* AES*/
#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
#endif /* End AES or CRYP */
/**
* @brief Disable the CRYP interrupt.
* @param __INTERRUPT__: CRYP Interrupt.
- * This parameter can be one of the following values for TinyAES:
+ * This parameter can be one of the following values for TinyAES:
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
* This parameter can be one of the following values for CRYP:
@@ -450,9 +485,9 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
* @param __HANDLE__: specifies the CRYP handle.
* @retval None
*/
-#if defined(CRYP)
+#if defined(CRYP)
#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__))
-#else /* AES*/
+#else /* AES*/
#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
#endif /* End AES or CRYP */
@@ -462,7 +497,7 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
#if defined (CRYP_CR_ALGOMODE_AES_GCM)|| defined (AES)
/* Include CRYP HAL Extended module */
#include "stm32f4xx_hal_cryp_ex.h"
-#endif /* AES or GCM CCM defined*/
+#endif /* AES or GCM CCM defined*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
* @{
@@ -470,28 +505,31 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
/** @addtogroup CRYP_Exported_Functions_Group1
* @{
- */
+ */
HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
-HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf );
-HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf );
+HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
+HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID,
+ pCRYP_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
/**
* @}
- */
+ */
/** @addtogroup CRYP_Exported_Functions_Group2
* @{
- */
+ */
/* encryption/decryption ***********************************/
-HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
+ uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
@@ -499,12 +537,12 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu
/**
* @}
- */
+ */
/** @addtogroup CRYP_Exported_Functions_Group3
* @{
- */
+ */
/* Interrupt Handler functions **********************************************/
void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
@@ -515,8 +553,8 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
/**
* @}
- */
-
+ */
+
/**
* @}
*/
@@ -532,32 +570,32 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
#if defined(CRYP)
#if defined (CRYP_CR_ALGOMODE_AES_GCM)
#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_DES_ECB) || \
- ((ALGORITHM) == CRYP_DES_CBC) || \
- ((ALGORITHM) == CRYP_TDES_ECB) || \
- ((ALGORITHM) == CRYP_TDES_CBC) || \
- ((ALGORITHM) == CRYP_AES_ECB) || \
- ((ALGORITHM) == CRYP_AES_CBC) || \
- ((ALGORITHM) == CRYP_AES_CTR) || \
- ((ALGORITHM) == CRYP_AES_GCM) || \
- ((ALGORITHM) == CRYP_AES_CCM))
+ ((ALGORITHM) == CRYP_DES_CBC) || \
+ ((ALGORITHM) == CRYP_TDES_ECB) || \
+ ((ALGORITHM) == CRYP_TDES_CBC) || \
+ ((ALGORITHM) == CRYP_AES_ECB) || \
+ ((ALGORITHM) == CRYP_AES_CBC) || \
+ ((ALGORITHM) == CRYP_AES_CTR) || \
+ ((ALGORITHM) == CRYP_AES_GCM) || \
+ ((ALGORITHM) == CRYP_AES_CCM))
#else /*NO GCM CCM */
#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_DES_ECB) || \
- ((ALGORITHM) == CRYP_DES_CBC) || \
- ((ALGORITHM) == CRYP_TDES_ECB) || \
- ((ALGORITHM) == CRYP_TDES_CBC) || \
- ((ALGORITHM) == CRYP_AES_ECB) || \
- ((ALGORITHM) == CRYP_AES_CBC) || \
- ((ALGORITHM) == CRYP_AES_CTR))
-#endif /* GCM CCM defined*/
+ ((ALGORITHM) == CRYP_DES_CBC) || \
+ ((ALGORITHM) == CRYP_TDES_ECB) || \
+ ((ALGORITHM) == CRYP_TDES_CBC) || \
+ ((ALGORITHM) == CRYP_AES_ECB) || \
+ ((ALGORITHM) == CRYP_AES_CBC) || \
+ ((ALGORITHM) == CRYP_AES_CTR))
+#endif /* GCM CCM defined*/
#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B) || \
((KEYSIZE) == CRYP_KEYSIZE_192B) || \
((KEYSIZE) == CRYP_KEYSIZE_256B))
-#else /* AES*/
+#else /* AES*/
#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_AES_ECB) || \
- ((ALGORITHM) == CRYP_AES_CBC) || \
- ((ALGORITHM) == CRYP_AES_CTR) || \
- ((ALGORITHM) == CRYP_AES_GCM_GMAC)|| \
- ((ALGORITHM) == CRYP_AES_CCM))
+ ((ALGORITHM) == CRYP_AES_CBC) || \
+ ((ALGORITHM) == CRYP_AES_CTR) || \
+ ((ALGORITHM) == CRYP_AES_GCM_GMAC)|| \
+ ((ALGORITHM) == CRYP_AES_CCM))
#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B) || \
@@ -569,6 +607,8 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
((DATATYPE) == CRYP_DATATYPE_8B) || \
((DATATYPE) == CRYP_DATATYPE_1B))
+#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
+ ((CONFIG) == CRYP_KEYIVCONFIG_ONCE))
/**
* @}
*/
@@ -585,7 +625,7 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
/**
* @}
- */
+ */
/* Private defines -----------------------------------------------------------*/
/** @defgroup CRYP_Private_Defines CRYP Private Defines
* @{
@@ -593,8 +633,8 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
/**
* @}
- */
-
+ */
+
/* Private variables ---------------------------------------------------------*/
/** @defgroup CRYP_Private_Variables CRYP Private Variables
* @{
@@ -602,7 +642,7 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
/**
* @}
- */
+ */
/* Private functions prototypes ----------------------------------------------*/
/** @defgroup CRYP_Private_Functions_Prototypes CRYP Private Functions Prototypes
* @{
@@ -620,21 +660,21 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
/**
* @}
*/
-
-
+
+
/**
* @}
- */
+ */
/**
* @}
- */
+ */
#endif /* TinyAES or CRYP*/
/**
* @}
- */
+ */
#ifdef __cplusplus
}
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cryp_ex.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cryp_ex.h
index f93a3b789a..251e94b1da 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cryp_ex.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cryp_ex.h
@@ -6,23 +6,23 @@
******************************************************************************
* @attention
*
- * © Copyright (c) 2016 STMicroelectronics.
+ * © Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
+ * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_CRYP_EX_H
#define __STM32F4xx_HAL_CRYP_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -35,14 +35,14 @@
/** @addtogroup CRYPEx
* @{
*/
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
/** @defgroup CRYPEx_Exported_Types CRYPEx Exported types
* @{
*/
/**
* @}
- */
+ */
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRYPEx_Exported_Constants CRYPEx Exported constants
* @{
@@ -50,8 +50,8 @@
/**
* @}
- */
-
+ */
+
/* Private types -------------------------------------------------------------*/
/** @defgroup CRYPEx_Private_Types CRYPEx Private Types
* @{
@@ -59,7 +59,7 @@
/**
* @}
- */
+ */
/* Private variables ---------------------------------------------------------*/
/** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables
@@ -68,7 +68,7 @@
/**
* @}
- */
+ */
/* Private constants ---------------------------------------------------------*/
/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
@@ -77,17 +77,17 @@
/**
* @}
- */
+ */
/* Private macros ------------------------------------------------------------*/
/** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros
* @{
*/
- /**
+/**
* @}
- */
-
+ */
+
/* Private functions ---------------------------------------------------------*/
/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
* @{
@@ -104,7 +104,7 @@
#if defined (CRYP) || defined (AES)
/** @addtogroup CRYPEx_Exported_Functions_Group1
* @{
- */
+ */
HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
/**
@@ -112,10 +112,10 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
*/
#endif /* CRYP||AES */
-#if defined (AES)
+#if defined (AES)
/** @addtogroup CRYPEx_Exported_Functions_Group2
* @{
- */
+ */
void HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
void HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
/**
@@ -125,16 +125,16 @@ void HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
/**
* @}
- */
-
+ */
+
/**
* @}
- */
+ */
/**
* @}
- */
-
+ */
+
#ifdef __cplusplus
}
#endif
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac.h
index fc9ce32efb..a1f49eae9e 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * © Copyright (c) 2017 STMicroelectronics.
+ * © Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -18,36 +18,34 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_DAC_H
-#define __STM32F4xx_HAL_DAC_H
+#ifndef STM32F4xx_HAL_DAC_H
+#define STM32F4xx_HAL_DAC_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
- defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
- defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx)
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
-/** @addtogroup STM32F4xx_HAL_Driver
- * @{
- */
+#if defined(DAC)
/** @addtogroup DAC
* @{
*/
/* Exported types ------------------------------------------------------------*/
+
/** @defgroup DAC_Exported_Types DAC Exported Types
* @{
*/
-/**
- * @brief HAL State structures definition
+/**
+ * @brief HAL State structures definition
*/
typedef enum
{
@@ -56,16 +54,17 @@ typedef enum
HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */
HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */
HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */
-}HAL_DAC_StateTypeDef;
-
-/**
- * @brief DAC handle Structure definition
+
+} HAL_DAC_StateTypeDef;
+
+/**
+ * @brief DAC handle Structure definition
*/
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
typedef struct __DAC_HandleTypeDef
#else
typedef struct
-#endif
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
{
DAC_TypeDef *Instance; /*!< Register base address */
@@ -80,32 +79,35 @@ typedef struct
__IO uint32_t ErrorCode; /*!< DAC Error code */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
- void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
- void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
- void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
- void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
- void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
- void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
- void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
- void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
-
- void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac);
- void (* MspDeInitCallback ) (struct __DAC_HandleTypeDef *hdac);
+ void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
+ void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
+ void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
+ void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
+#if defined(DAC_CHANNEL2_SUPPORT)
+ void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
+ void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
+ void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
+ void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+ void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac);
+ void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-}DAC_HandleTypeDef;
+} DAC_HandleTypeDef;
-/**
- * @brief DAC Configuration regular Channel structure definition
+/**
+ * @brief DAC Configuration regular Channel structure definition
*/
typedef struct
{
- uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
- This parameter can be a value of @ref DAC_trigger_selection */
+ uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
+ This parameter can be a value of @ref DAC_trigger_selection */
- uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
- This parameter can be a value of @ref DAC_output_buffer */
-}DAC_ChannelConfTypeDef;
+ uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+ This parameter can be a value of @ref DAC_output_buffer */
+
+} DAC_ChannelConfTypeDef;
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/**
@@ -117,25 +119,29 @@ typedef enum
HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */
HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */
HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */
+#if defined(DAC_CHANNEL2_SUPPORT)
HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */
HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */
HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */
HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */
- HAL_DAC_MSP_INIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
- HAL_DAC_MSP_DEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
+#endif /* DAC_CHANNEL2_SUPPORT */
+ HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
+ HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */
-}HAL_DAC_CallbackIDTypeDef;
+} HAL_DAC_CallbackIDTypeDef;
/**
* @brief HAL DAC Callback pointer definition
*/
typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
+
/** @defgroup DAC_Exported_Constants DAC Exported Constants
* @{
*/
@@ -144,77 +150,89 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
* @{
*/
#define HAL_DAC_ERROR_NONE 0x00U /*!< No error */
-#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DAM underrun error */
-#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DAM underrun error */
+#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DMA underrun error */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DMA underrun error */
+#endif /* DAC_CHANNEL2_SUPPORT */
#define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */
+#define HAL_DAC_ERROR_TIMEOUT 0x08U /*!< Timeout error */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
#define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
/**
* @}
*/
-/** @defgroup DAC_trigger_selection DAC Trigger Selection
+/** @defgroup DAC_trigger_selection DAC trigger selection
* @{
*/
+#define DAC_TRIGGER_NONE 0x00000000UL /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */
+#define DAC_TRIGGER_T2_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T6_TRGO ( DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */
+#define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_SOFTWARE (DAC_CR_TSEL1 | DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */
-#define DAC_TRIGGER_NONE 0x00000000U /*!< Conversion is automatic once the DAC1_DHRxxxx register
- has been loaded, and not by external trigger */
-#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T8_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
-
-#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
/**
* @}
*/
-/** @defgroup DAC_output_buffer DAC Output Buffer
+/** @defgroup DAC_output_buffer DAC output buffer
* @{
*/
#define DAC_OUTPUTBUFFER_ENABLE 0x00000000U
-#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
+#define DAC_OUTPUTBUFFER_DISABLE (DAC_CR_BOFF1)
+
/**
* @}
*/
-/** @defgroup DAC_Channel_selection DAC Channel Selection
+/** @defgroup DAC_Channel_selection DAC Channel selection
* @{
*/
#define DAC_CHANNEL_1 0x00000000U
+#if defined(DAC_CHANNEL2_SUPPORT)
#define DAC_CHANNEL_2 0x00000010U
+#endif /* DAC_CHANNEL2_SUPPORT */
/**
* @}
*/
-/** @defgroup DAC_data_alignment DAC Data Alignment
+/** @defgroup DAC_data_alignment DAC data alignment
* @{
*/
#define DAC_ALIGN_12B_R 0x00000000U
#define DAC_ALIGN_12B_L 0x00000004U
#define DAC_ALIGN_8B_R 0x00000008U
+
/**
* @}
*/
-/** @defgroup DAC_flags_definition DAC Flags Definition
+/** @defgroup DAC_flags_definition DAC flags definition
* @{
- */
-#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
-#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
+ */
+#define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)
+#endif /* DAC_CHANNEL2_SUPPORT */
+
/**
* @}
*/
-/** @defgroup DAC_IT_definition DAC IT Definition
+/** @defgroup DAC_IT_definition DAC IT definition
* @{
- */
-#define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
-#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
+ */
+#define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1)
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2)
+#endif /* DAC_CHANNEL2_SUPPORT */
+
/**
* @}
*/
@@ -224,233 +242,241 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
*/
/* Exported macro ------------------------------------------------------------*/
+
/** @defgroup DAC_Exported_Macros DAC Exported Macros
* @{
*/
-/** @brief Reset DAC handle state
+/** @brief Reset DAC handle state.
* @param __HANDLE__ specifies the DAC handle.
* @retval None
*/
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \
- (__HANDLE__)->State = HAL_DAC_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
+#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_DAC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
#else
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-/** @brief Enable the DAC channel
+/** @brief Enable the DAC channel.
* @param __HANDLE__ specifies the DAC handle.
* @param __DAC_Channel__ specifies the DAC channel
* @retval None
*/
-#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
+#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
+ ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
-/** @brief Disable the DAC channel
+/** @brief Disable the DAC channel.
* @param __HANDLE__ specifies the DAC handle
* @param __DAC_Channel__ specifies the DAC channel.
* @retval None
*/
-#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
+#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
+ ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
-/** @brief Enable the DAC interrupt
+/** @brief Set DHR12R1 alignment.
+ * @param __ALIGNMENT__ specifies the DAC alignment
+ * @retval None
+ */
+#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__))
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/** @brief Set DHR12R2 alignment.
+ * @param __ALIGNMENT__ specifies the DAC alignment
+ * @retval None
+ */
+#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__))
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/** @brief Set DHR12RD alignment.
+ * @param __ALIGNMENT__ specifies the DAC alignment
+ * @retval None
+ */
+#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__))
+
+/** @brief Enable the DAC interrupt.
* @param __HANDLE__ specifies the DAC handle
* @param __INTERRUPT__ specifies the DAC interrupt.
+ * This parameter can be any combination of the following values:
+ * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
+ * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
* @retval None
*/
#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
-/** @brief Disable the DAC interrupt
+/** @brief Disable the DAC interrupt.
* @param __HANDLE__ specifies the DAC handle
* @param __INTERRUPT__ specifies the DAC interrupt.
+ * This parameter can be any combination of the following values:
+ * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
+ * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
* @retval None
*/
#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
-/** @brief Checks if the specified DAC interrupt source is enabled or disabled.
+/** @brief Check whether the specified DAC interrupt source is enabled or not.
* @param __HANDLE__ DAC handle
* @param __INTERRUPT__ DAC interrupt source to check
* This parameter can be any combination of the following values:
- * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
- * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
+ * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
+ * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
* @retval State of interruption (SET or RESET)
*/
-#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\
+ & (__INTERRUPT__)) == (__INTERRUPT__))
/** @brief Get the selected DAC's flag status.
* @param __HANDLE__ specifies the DAC handle.
- * @param __FLAG__ specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
- * @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
+ * @param __FLAG__ specifies the DAC flag to get.
+ * This parameter can be any combination of the following values:
+ * @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
+ * @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
* @retval None
*/
#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clear the DAC's flag.
* @param __HANDLE__ specifies the DAC handle.
- * @param __FLAG__ specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
- * @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
+ * @param __FLAG__ specifies the DAC flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
+ * @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
* @retval None
*/
#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
+
/**
* @}
*/
-/* Include DAC HAL Extension module */
-#include "stm32f4xx_hal_dac_ex.h"
+/* Private macro -------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DAC_Exported_Functions
+/** @defgroup DAC_Private_Macros DAC Private Macros
* @{
*/
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
+ ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
+ ((CHANNEL) == DAC_CHANNEL_2))
+#else
+#define IS_DAC_CHANNEL(CHANNEL) ((CHANNEL) == DAC_CHANNEL_1)
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
+ ((ALIGN) == DAC_ALIGN_12B_L) || \
+ ((ALIGN) == DAC_ALIGN_8B_R))
+
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL)
-/** @addtogroup DAC_Exported_Functions_Group1
- * @{
- */
-/* Initialization/de-initialization functions *********************************/
-HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
-HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
-void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
-void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
/**
* @}
*/
-/** @addtogroup DAC_Exported_Functions_Group2
+/* Include DAC HAL Extended module */
+#include "stm32f4xx_hal_dac_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup DAC_Exported_Functions
* @{
*/
-/* I/O operation functions ****************************************************/
-HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
-HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
-/**
- * @}
- */
-/** @addtogroup DAC_Exported_Functions_Group3
+/** @addtogroup DAC_Exported_Functions_Group1
* @{
*/
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac);
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac);
+void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac);
+void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
+
/**
* @}
*/
-/** @addtogroup DAC_Exported_Functions_Group4
+/** @addtogroup DAC_Exported_Functions_Group2
* @{
*/
-/* Peripheral State functions *************************************************/
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
-void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
-uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
-
-void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
-void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
+ uint32_t Alignment);
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
+
+void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac);
+void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac);
void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/* DAC callback registering/unregistering */
-HAL_StatusTypeDef HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
+ pDAC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-/**
- * @}
- */
/**
* @}
*/
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup DAC_Private_Constants DAC Private Constants
+
+/** @addtogroup DAC_Exported_Functions_Group3
* @{
*/
-
+/* Peripheral Control functions ***********************************************/
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
/**
* @}
*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DAC_Private_Macros DAC Private Macros
+/** @addtogroup DAC_Exported_Functions_Group4
* @{
*/
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
-#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
- ((ALIGN) == DAC_ALIGN_12B_L) || \
- ((ALIGN) == DAC_ALIGN_8B_R))
-#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
- ((CHANNEL) == DAC_CHANNEL_2))
-#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
- ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
-
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
- ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
- ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
-
-/** @brief Set DHR12R1 alignment
- * @param __ALIGNMENT__ specifies the DAC alignment
- * @retval None
- */
-#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008U + (__ALIGNMENT__))
-
-/** @brief Set DHR12R2 alignment
- * @param __ALIGNMENT__ specifies the DAC alignment
- * @retval None
- */
-#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014U) + (__ALIGNMENT__))
+/* Peripheral State and Error functions ***************************************/
+HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac);
+uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
-/** @brief Set DHR12RD alignment
- * @param __ALIGNMENT__ specifies the DAC alignment
- * @retval None
+/**
+ * @}
*/
-#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020U + (__ALIGNMENT__))
/**
* @}
*/
-/* Private functions ---------------------------------------------------------*/
/** @defgroup DAC_Private_Functions DAC Private Functions
* @{
*/
+void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
+void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
+void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
- STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
- STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx ||\
- STM32F413xx || STM32F423xx */
/**
* @}
*/
+#endif /* DAC */
+
/**
* @}
*/
-
+
#ifdef __cplusplus
}
#endif
-#endif /*__STM32F4xx_HAL_DAC_H */
+
+#endif /* STM32F4xx_HAL_DAC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac_ex.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac_ex.h
index 4e9793a561..03159d4fe5 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac_ex.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac_ex.h
@@ -1,12 +1,12 @@
/**
******************************************************************************
- * @file stm32f4xx_hal_dac.h
+ * @file stm32f4xx_hal_dac_ex.h
* @author MCD Application Team
- * @brief Header file of DAC HAL Extension module.
+ * @brief Header file of DAC HAL Extended module.
******************************************************************************
* @attention
*
- * © Copyright (c) 2017 STMicroelectronics.
+ * © Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -18,89 +18,66 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_DAC_EX_H
-#define __STM32F4xx_HAL_DAC_EX_H
+#ifndef STM32F4xx_HAL_DAC_EX_H
+#define STM32F4xx_HAL_DAC_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
- defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
- defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx)
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
-/** @addtogroup STM32F4xx_HAL_Driver
- * @{
- */
+#if defined(DAC)
/** @addtogroup DACEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DACEx_Exported_Constants DAC Exported Constants
- * @{
- */
-/** @defgroup DACEx_lfsrunmask_triangleamplitude DAC LFS Run Mask Triangle Amplitude
- * @{
- */
-#define DAC_LFSRUNMASK_BIT0 0x00000000U /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
-#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
-#define DAC_TRIANGLEAMPLITUDE_1 0x00000000U /*!< Select max triangle amplitude of 1 */
-#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
-#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
-#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
-#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
-#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
-#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
-#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
-#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
-#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
-#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
-#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
/**
- * @}
+ * @brief HAL State structures definition
*/
-/**
- * @}
- */
+/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DACEx_Exported_Functions
+/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
* @{
*/
-/** @addtogroup DACEx_Exported_Functions_Group1
+/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude
* @{
*/
-/* Extension features functions ***********************************************/
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
-HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
+#define DAC_LFSRUNMASK_BIT0 0x00000000UL /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TRIANGLEAMPLITUDE_1 0x00000000UL /*!< Select max triangle amplitude of 1 */
+#define DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
+#define DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 7 */
+#define DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
+#define DAC_TRIANGLEAMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Select max triangle amplitude of 31 */
+#define DAC_TRIANGLEAMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
+#define DAC_TRIANGLEAMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 127 */
+#define DAC_TRIANGLEAMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
+#define DAC_TRIANGLEAMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Select max triangle amplitude of 511 */
+#define DAC_TRIANGLEAMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TRIANGLEAMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TRIANGLEAMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
-void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
/**
* @}
*/
@@ -108,21 +85,25 @@ void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
/**
* @}
*/
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup DACEx_Private_Constants DAC Private Constants
- * @{
- */
-/**
- * @}
- */
+/* Exported macro ------------------------------------------------------------*/
+
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DACEx_Private_Macros DAC Private Macros
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup DACEx_Private_Macros DACEx Private Macros
* @{
*/
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+ ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
@@ -151,33 +132,76 @@ void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
* @}
*/
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup DACEx_Private_Functions DAC Private Functions
+/* Exported functions --------------------------------------------------------*/
+/* Extended features functions ***********************************************/
+
+/** @addtogroup DACEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DACEx_Exported_Functions_Group2
+ * @{
+ */
+/* IO operation functions *****************************************************/
+
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+#endif
+HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac);
+HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac);
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac);
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+#endif
+void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac);
+void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac);
+void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac);
+void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DACEx_Private_Functions
* @{
*/
+#if defined(DAC_CHANNEL2_SUPPORT)
+/* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */
+/* are called by HAL_DAC_Start_DMA */
void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
-void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
+void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
+#endif /* DAC_CHANNEL2_SUPPORT */
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
- STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
- STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx ||\
- STM32F413xx || STM32F423xx */
/**
* @}
*/
+#endif /* DAC */
+
/**
* @}
*/
-
+
#ifdef __cplusplus
}
#endif
-#endif /*__STM32F4xx_HAL_DAC_EX_H */
+#endif /* STM32F4xx_HAL_DAC_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dcmi.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dcmi.h
index 021f37e4ee..2a9edb6c47 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dcmi.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dcmi.h
@@ -48,6 +48,16 @@
/** @defgroup DCMI_Exported_Types DCMI Exported Types
* @{
*/
+/**
+ * @brief DCMI Embedded Synchronisation CODE Init structure definition
+ */
+typedef struct
+{
+ uint8_t FrameStartUnmask; /*!< Specifies the frame start delimiter unmask. */
+ uint8_t LineStartUnmask; /*!< Specifies the line start delimiter unmask. */
+ uint8_t LineEndUnmask; /*!< Specifies the line end delimiter unmask. */
+ uint8_t FrameEndUnmask; /*!< Specifies the frame end delimiter unmask. */
+}DCMI_SyncUnmaskTypeDef;
/**
* @brief HAL DCMI State structures definition
*/
@@ -458,6 +468,7 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi);
HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask);
/**
* @}
*/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h
index e32e362ddd..975f70bd4b 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h
@@ -107,7 +107,14 @@ typedef enum
}while (0U)
#endif /* USE_RTOS */
-#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
+ #ifndef __weak
+ #define __weak __attribute__((weak))
+ #endif
+ #ifndef __packed
+ #define __packed __attribute__((packed))
+ #endif
+#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
@@ -118,7 +125,14 @@ typedef enum
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
-#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
+ #ifndef __ALIGN_BEGIN
+ #define __ALIGN_BEGIN
+ #endif
+ #ifndef __ALIGN_END
+ #define __ALIGN_END __attribute__ ((aligned (4)))
+ #endif
+#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif /* __ALIGN_END */
@@ -130,7 +144,7 @@ typedef enum
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
- #if defined (__CC_ARM) /* ARM Compiler */
+ #if defined (__CC_ARM) /* ARM Compiler V5*/
#define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
@@ -142,9 +156,9 @@ typedef enum
/**
* @brief __RAM_FUNC definition
*/
-#if defined ( __CC_ARM )
-/* ARM Compiler
- ------------
+#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+/* ARM Compiler V4/V5 and V6
+ --------------------------
RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate source module.
Using the 'Options for File' dialog you can simply change the 'Code / Const'
@@ -174,9 +188,9 @@ typedef enum
/**
* @brief __NOINLINE definition
*/
-#if defined ( __CC_ARM ) || defined ( __GNUC__ )
-/* ARM & GNUCompiler
- ----------------
+#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
+/* ARM V4/V5 and V6 & GNU Compiler
+ -------------------------------
*/
#define __NOINLINE __attribute__ ( (noinline) )
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma2d.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma2d.h
index 5bb7b6dfba..158ed67d0e 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma2d.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma2d.h
@@ -22,11 +22,9 @@
#define STM32F4xx_HAL_DMA2D_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-#if defined (DMA2D)
-
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -34,6 +32,8 @@
* @{
*/
+#if defined (DMA2D)
+
/** @addtogroup DMA2D DMA2D
* @brief DMA2D HAL module driver
* @{
@@ -71,7 +71,8 @@ typedef struct
This parameter can be one value of @ref DMA2D_Output_Color_Mode. */
uint32_t OutputOffset; /*!< Specifies the Offset value.
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
+ This parameter must be a number between
+ Min_Data = 0x0000 and Max_Data = 0x3FFF. */
@@ -85,7 +86,8 @@ typedef struct
typedef struct
{
uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset.
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
+ This parameter must be a number between
+ Min_Data = 0x0000 and Max_Data = 0x3FFF. */
uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode.
This parameter can be one value of @ref DMA2D_Input_Color_Mode. */
@@ -93,9 +95,12 @@ typedef struct
uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode.
This parameter can be one value of @ref DMA2D_Alpha_Mode. */
- uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below.
- @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between
+ uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value
+ in case of A8 or A4 color mode.
+ This parameter must be a number between Min_Data = 0x00
+ and Max_Data = 0xFF except for the color modes detailed below.
+ @note In case of A8 or A4 color mode (ARGB),
+ this parameter must be a number between
Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where
- InputAlpha[24:31] is the alpha value ALPHA[0:7]
- InputAlpha[16:23] is the red value RED[0:7]
@@ -116,46 +121,46 @@ typedef enum
HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */
HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */
-}HAL_DMA2D_StateTypeDef;
+} HAL_DMA2D_StateTypeDef;
/**
* @brief DMA2D handle Structure definition
*/
typedef struct __DMA2D_HandleTypeDef
{
- DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */
+ DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */
- DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */
+ DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */
- void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback. */
+ void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer complete callback. */
- void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback. */
+ void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer error callback. */
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
- void (* LineEventCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D line event callback. */
+ void (* LineEventCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D line event callback. */
- void (* CLUTLoadingCpltCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D CLUT loading completion callback. */
+ void (* CLUTLoadingCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D CLUT loading completion callback */
- void (* MspInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp Init callback. */
+ void (* MspInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp Init callback. */
- void (* MspDeInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp DeInit callback. */
+ void (* MspDeInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp DeInit callback. */
#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
- DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
+ DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
- HAL_LockTypeDef Lock; /*!< DMA2D lock. */
+ HAL_LockTypeDef Lock; /*!< DMA2D lock. */
- __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */
+ __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */
- __IO uint32_t ErrorCode; /*!< DMA2D error code. */
+ __IO uint32_t ErrorCode; /*!< DMA2D error code. */
} DMA2D_HandleTypeDef;
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
/**
* @brief HAL DMA2D Callback pointer definition
*/
-typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Pointer to a DMA2D common callback function */
+typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d); /*!< Pointer to a DMA2D common callback function */
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
/**
* @}
@@ -226,10 +231,10 @@ typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Poin
/** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode
* @{
*/
-#define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */
+#define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */
#define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */
#define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value
- with original alpha channel value */
+ with original alpha channel value */
/**
* @}
*/
@@ -277,7 +282,8 @@ typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Poin
/** @defgroup DMA2D_Aliases DMA2D API Aliases
* @{
*/
-#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */
+#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort
+ for compatibility with legacy code */
/**
* @}
*/
@@ -294,7 +300,7 @@ typedef enum
HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U, /*!< DMA2D transfer error callback ID */
HAL_DMA2D_LINEEVENT_CB_ID = 0x04U, /*!< DMA2D line event callback ID */
HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U, /*!< DMA2D CLUT loading completion callback ID */
-}HAL_DMA2D_CallbackIDTypeDef;
+} HAL_DMA2D_CallbackIDTypeDef;
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
@@ -311,10 +317,10 @@ typedef enum
* @retval None
*/
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
-#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
+#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
}while(0)
#else
#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
@@ -420,12 +426,13 @@ typedef enum
/* Initialization and de-initialization functions *******************************/
HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
-HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
-void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
-void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d);
+void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d);
+void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID,
+ pDMA2D_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
@@ -439,14 +446,22 @@ HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_
*/
/* IO operation functions *******************************************************/
-HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
-HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
-HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
-HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
+ uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
+ uint32_t DstAddress, uint32_t Width, uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
+ uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
+ uint32_t DstAddress, uint32_t Width, uint32_t Height);
HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
+ uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
+ uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
@@ -566,13 +581,16 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
/** @defgroup DMA2D_Private_Macros DMA2D Private Macros
* @{
*/
-#define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER) || ((LAYER) == DMA2D_FOREGROUND_LAYER))
+#define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER)\
+ || ((LAYER) == DMA2D_FOREGROUND_LAYER))
#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
-#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \
- ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
+#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || \
+ ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \
+ ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || \
+ ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE)
@@ -580,11 +598,16 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
#define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
-#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \
- ((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
- ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \
- ((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \
- ((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \
+#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || \
+ ((INPUT_CM) == DMA2D_INPUT_RGB888) || \
+ ((INPUT_CM) == DMA2D_INPUT_RGB565) || \
+ ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
+ ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || \
+ ((INPUT_CM) == DMA2D_INPUT_L8) || \
+ ((INPUT_CM) == DMA2D_INPUT_AL44) || \
+ ((INPUT_CM) == DMA2D_INPUT_AL88) || \
+ ((INPUT_CM) == DMA2D_INPUT_L4) || \
+ ((INPUT_CM) == DMA2D_INPUT_A8) || \
((INPUT_CM) == DMA2D_INPUT_A4))
#define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
@@ -599,11 +622,11 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
#define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
- ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
- ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
+ ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
+ ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
- ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
- ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
+ ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
+ ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
/**
* @}
*/
@@ -612,12 +635,12 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
* @}
*/
+#endif /* defined (DMA2D) */
+
/**
* @}
*/
-#endif /* defined (DMA2D) */
-
#ifdef __cplusplus
}
#endif
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dsi.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dsi.h
index df61c5e30d..716dea17da 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dsi.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dsi.h
@@ -25,10 +25,11 @@
extern "C" {
#endif
-#if defined(DSI)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
+#if defined(DSI)
+
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
@@ -347,6 +348,9 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to
#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
/* Exported constants --------------------------------------------------------*/
+/** @defgroup DSI_Exported_Constants DSI Exported Constants
+ * @{
+ */
/** @defgroup DSI_DCS_Command DSI DCS Command
* @{
*/
@@ -908,10 +912,18 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to
* @}
*/
+/**
+ * @}
+ */
+
/* Exported macros -----------------------------------------------------------*/
+/** @defgroup DSI_Exported_Macros DSI Exported Macros
+ * @{
+ */
+
/**
* @brief Reset DSI handle state.
- * @param __HANDLE__: DSI handle
+ * @param __HANDLE__ DSI handle
* @retval None
*/
#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
@@ -1101,6 +1113,10 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to
*/
#define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER & (__INTERRUPT__))
+/**
+ * @}
+ */
+
/* Exported functions --------------------------------------------------------*/
/** @defgroup DSI_Exported_Functions DSI Exported Functions
* @{
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h
index 24dccffee3..857011236b 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h
@@ -44,9 +44,7 @@ extern "C" {
*/
typedef enum
{
- HAL_EXTI_COMMON_CB_ID = 0x00U,
- HAL_EXTI_RISING_CB_ID = 0x01U,
- HAL_EXTI_FALLING_CB_ID = 0x02U,
+ HAL_EXTI_COMMON_CB_ID = 0x00U
} EXTI_CallbackIDTypeDef;
/**
@@ -55,8 +53,7 @@ typedef enum
typedef struct
{
uint32_t Line; /*!< Exti line number */
- void (* RisingCallback)(void); /*!< Exti rising callback */
- void (* FallingCallback)(void); /*!< Exti falling callback */
+ void (* PendingCallback)(void); /*!< Exti pending callback */
} EXTI_HandleTypeDef;
/**
@@ -69,7 +66,10 @@ typedef struct
uint32_t Mode; /*!< The Exit Mode to be configured for a core.
This parameter can be a combination of @ref EXTI_Mode */
uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
- can be a value of @ref EXTI_Trigger */
+ can be a value of @ref EXTI_Trigger */
+ uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
+ This parameter is only possible for line 0 to 15. It
+ can be a value of @ref EXTI_GPIOSel */
} EXTI_ConfigTypeDef;
/**
@@ -84,29 +84,44 @@ typedef struct
/** @defgroup EXTI_Line EXTI Line
* @{
*/
-#define EXTI_LINE_0 EXTI_IMR_IM0 /*!< External interrupt line 0 */
-#define EXTI_LINE_1 EXTI_IMR_IM1 /*!< External interrupt line 1 */
-#define EXTI_LINE_2 EXTI_IMR_IM2 /*!< External interrupt line 2 */
-#define EXTI_LINE_3 EXTI_IMR_IM3 /*!< External interrupt line 3 */
-#define EXTI_LINE_4 EXTI_IMR_IM4 /*!< External interrupt line 4 */
-#define EXTI_LINE_5 EXTI_IMR_IM5 /*!< External interrupt line 5 */
-#define EXTI_LINE_6 EXTI_IMR_IM6 /*!< External interrupt line 6 */
-#define EXTI_LINE_7 EXTI_IMR_IM7 /*!< External interrupt line 7 */
-#define EXTI_LINE_8 EXTI_IMR_IM8 /*!< External interrupt line 8 */
-#define EXTI_LINE_9 EXTI_IMR_IM9 /*!< External interrupt line 9 */
-#define EXTI_LINE_10 EXTI_IMR_IM10 /*!< External interrupt line 10 */
-#define EXTI_LINE_11 EXTI_IMR_IM11 /*!< External interrupt line 11 */
-#define EXTI_LINE_12 EXTI_IMR_IM12 /*!< External interrupt line 12 */
-#define EXTI_LINE_13 EXTI_IMR_IM13 /*!< External interrupt line 13 */
-#define EXTI_LINE_14 EXTI_IMR_IM14 /*!< External interrupt line 14 */
-#define EXTI_LINE_15 EXTI_IMR_IM15 /*!< External interrupt line 15 */
-#define EXTI_LINE_16 EXTI_IMR_IM16 /*!< External interrupt line 16 Connected to the PVD Output */
-#define EXTI_LINE_17 EXTI_IMR_IM17 /*!< External interrupt line 17 Connected to the RTC Alarm event */
-#define EXTI_LINE_18 EXTI_IMR_IM18 /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */
-#define EXTI_LINE_19 EXTI_IMR_IM19 /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
-#define EXTI_LINE_20 EXTI_IMR_IM20 /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */
-#define EXTI_LINE_21 EXTI_IMR_IM21 /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
-#define EXTI_LINE_22 EXTI_IMR_IM22 /*!< External interrupt line 22 Connected to the RTC Wakeup event */
+#define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */
+#define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */
+#define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */
+#define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */
+#define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */
+#define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */
+#define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */
+#define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */
+#define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */
+#define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */
+#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */
+#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */
+#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */
+#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */
+#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */
+#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */
+#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */
+#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */
+#if defined(EXTI_IMR_IM18)
+#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */
+#else
+#define EXTI_LINE_18 (EXTI_RESERVED | 0x12u) /*!< No interrupt supported in this line */
+#endif /* EXTI_IMR_IM18 */
+#if defined(EXTI_IMR_IM19)
+#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
+#else
+#define EXTI_LINE_19 (EXTI_RESERVED | 0x13u) /*!< No interrupt supported in this line */
+#endif /* EXTI_IMR_IM19 */
+#if defined(EXTI_IMR_IM20)
+#define EXTI_LINE_20 (EXTI_CONFIG | 0x14u) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */
+#else
+#define EXTI_LINE_20 (EXTI_RESERVED | 0x14u) /*!< No interrupt supported in this line */
+#endif /* EXTI_IMR_IM20 */
+#define EXTI_LINE_21 (EXTI_CONFIG | 0x15u) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
+#define EXTI_LINE_22 (EXTI_CONFIG | 0x16u) /*!< External interrupt line 22 Connected to the RTC Wakeup event */
+#if defined(EXTI_IMR_IM23)
+#define EXTI_LINE_23 (EXTI_CONFIG | 0x17u) /*!< External interrupt line 23 Connected to the LPTIM1 asynchronous event */
+#endif /* EXTI_IMR_IM23 */
/**
* @}
@@ -115,8 +130,9 @@ typedef struct
/** @defgroup EXTI_Mode EXTI Mode
* @{
*/
-#define EXTI_MODE_INTERRUPT 0x00000000U
-#define EXTI_MODE_EVENT 0x00000004U
+#define EXTI_MODE_NONE 0x00000000u
+#define EXTI_MODE_INTERRUPT 0x00000001u
+#define EXTI_MODE_EVENT 0x00000002u
/**
* @}
*/
@@ -125,13 +141,50 @@ typedef struct
* @{
*/
-#define EXTI_TRIGGER_RISING 0x00000008U
-#define EXTI_TRIGGER_FALLING 0x0000000CU
-#define EXTI_TRIGGER_RISING_FALLING 0x00000010U
+#define EXTI_TRIGGER_NONE 0x00000000u
+#define EXTI_TRIGGER_RISING 0x00000001u
+#define EXTI_TRIGGER_FALLING 0x00000002u
+#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
/**
* @}
*/
-
+
+/** @defgroup EXTI_GPIOSel EXTI GPIOSel
+ * @brief
+ * @{
+ */
+#define EXTI_GPIOA 0x00000000u
+#define EXTI_GPIOB 0x00000001u
+#define EXTI_GPIOC 0x00000002u
+#if defined (GPIOD)
+#define EXTI_GPIOD 0x00000003u
+#endif /* GPIOD */
+#if defined (GPIOE)
+#define EXTI_GPIOE 0x00000004u
+#endif /* GPIOE */
+#if defined (GPIOF)
+#define EXTI_GPIOF 0x00000005u
+#endif /* GPIOF */
+#if defined (GPIOG)
+#define EXTI_GPIOG 0x00000006u
+#endif /* GPIOG */
+#if defined (GPIOH)
+#define EXTI_GPIOH 0x00000007u
+#endif /* GPIOH */
+#if defined (GPIOI)
+#define EXTI_GPIOI 0x00000008u
+#endif /* GPIOI */
+#if defined (GPIOJ)
+#define EXTI_GPIOJ 0x00000009u
+#endif /* GPIOJ */
+#if defined (GPIOK)
+#define EXTI_GPIOK 0x0000000Au
+#endif /* GPIOK */
+
+/**
+ * @}
+ */
+
/**
* @}
*/
@@ -149,6 +202,20 @@ typedef struct
/** @defgroup EXTI_Private_Constants EXTI Private Constants
* @{
*/
+/**
+ * @brief EXTI Line property definition
+ */
+#define EXTI_PROPERTY_SHIFT 24u
+#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
+#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
+#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
+#define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO)
+
+/**
+ * @brief EXTI bit usage
+ */
+#define EXTI_PIN_MASK 0x0000001Fu
+
/**
* @brief EXTI Mask for interrupt & event mode
*/
@@ -157,12 +224,16 @@ typedef struct
/**
* @brief EXTI Mask for trigger possibilities
*/
-#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING | EXTI_TRIGGER_RISING_FALLING)
+#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
/**
* @brief EXTI Line number
*/
+#if defined(EXTI_IMR_IM23)
+#define EXTI_LINE_NB 24UL
+#else
#define EXTI_LINE_NB 23UL
+#endif /* EXTI_IMR_IM23 */
/**
* @}
@@ -172,37 +243,70 @@ typedef struct
/** @defgroup EXTI_Private_Macros EXTI Private Macros
* @{
*/
-#define IS_EXTI_LINE(__LINE__) (((__LINE__) == EXTI_LINE_0) || \
- ((__LINE__) == EXTI_LINE_1) || \
- ((__LINE__) == EXTI_LINE_2) || \
- ((__LINE__) == EXTI_LINE_3) || \
- ((__LINE__) == EXTI_LINE_4) || \
- ((__LINE__) == EXTI_LINE_5) || \
- ((__LINE__) == EXTI_LINE_6) || \
- ((__LINE__) == EXTI_LINE_7) || \
- ((__LINE__) == EXTI_LINE_8) || \
- ((__LINE__) == EXTI_LINE_9) || \
- ((__LINE__) == EXTI_LINE_10) || \
- ((__LINE__) == EXTI_LINE_11) || \
- ((__LINE__) == EXTI_LINE_12) || \
- ((__LINE__) == EXTI_LINE_13) || \
- ((__LINE__) == EXTI_LINE_14) || \
- ((__LINE__) == EXTI_LINE_15) || \
- ((__LINE__) == EXTI_LINE_16) || \
- ((__LINE__) == EXTI_LINE_17) || \
- ((__LINE__) == EXTI_LINE_18) || \
- ((__LINE__) == EXTI_LINE_19) || \
- ((__LINE__) == EXTI_LINE_20) || \
- ((__LINE__) == EXTI_LINE_21) || \
- ((__LINE__) == EXTI_LINE_22))
-
-#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & ~EXTI_MODE_MASK) == 0x00U))
-
-#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U)
-
-#define IS_EXTI_PENDING_EDGE(__LINE__) (((__LINE__) == EXTI_TRIGGER_FALLING) || \
- ((__LINE__) == EXTI_TRIGGER_RISING) || \
- ((__LINE__) == EXTI_TRIGGER_RISING_FALLING))
+#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \
+ ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
+ (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
+ (((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
+
+#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \
+ (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))
+
+#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
+
+#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)
+
+#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
+
+#if !defined (GPIOD)
+#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
+ ((__PORT__) == EXTI_GPIOB) || \
+ ((__PORT__) == EXTI_GPIOC) || \
+ ((__PORT__) == EXTI_GPIOH))
+#elif !defined (GPIOE)
+#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
+ ((__PORT__) == EXTI_GPIOB) || \
+ ((__PORT__) == EXTI_GPIOC) || \
+ ((__PORT__) == EXTI_GPIOD) || \
+ ((__PORT__) == EXTI_GPIOH))
+#elif !defined (GPIOF)
+#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
+ ((__PORT__) == EXTI_GPIOB) || \
+ ((__PORT__) == EXTI_GPIOC) || \
+ ((__PORT__) == EXTI_GPIOD) || \
+ ((__PORT__) == EXTI_GPIOE) || \
+ ((__PORT__) == EXTI_GPIOH))
+#elif !defined (GPIOI)
+#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
+ ((__PORT__) == EXTI_GPIOB) || \
+ ((__PORT__) == EXTI_GPIOC) || \
+ ((__PORT__) == EXTI_GPIOD) || \
+ ((__PORT__) == EXTI_GPIOE) || \
+ ((__PORT__) == EXTI_GPIOF) || \
+ ((__PORT__) == EXTI_GPIOG) || \
+ ((__PORT__) == EXTI_GPIOH))
+#elif !defined (GPIOJ)
+#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
+ ((__PORT__) == EXTI_GPIOB) || \
+ ((__PORT__) == EXTI_GPIOC) || \
+ ((__PORT__) == EXTI_GPIOD) || \
+ ((__PORT__) == EXTI_GPIOE) || \
+ ((__PORT__) == EXTI_GPIOF) || \
+ ((__PORT__) == EXTI_GPIOG) || \
+ ((__PORT__) == EXTI_GPIOH) || \
+ ((__PORT__) == EXTI_GPIOI))
+#else
+#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
+ ((__PORT__) == EXTI_GPIOB) || \
+ ((__PORT__) == EXTI_GPIOC) || \
+ ((__PORT__) == EXTI_GPIOD) || \
+ ((__PORT__) == EXTI_GPIOE) || \
+ ((__PORT__) == EXTI_GPIOF) || \
+ ((__PORT__) == EXTI_GPIOG) || \
+ ((__PORT__) == EXTI_GPIOH) || \
+ ((__PORT__) == EXTI_GPIOI) || \
+ ((__PORT__) == EXTI_GPIOJ) || \
+ ((__PORT__) == EXTI_GPIOK))
+#endif /* GPIOD */
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U)
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c.h
index f0fd230e80..270a92b747 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c.h
@@ -496,7 +496,8 @@ typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint
*
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
-#define __HAL_FMPI2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_FMPI2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \
+ (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified FMPI2C flag is set or not.
* @param __HANDLE__ specifies the FMPI2C Handle.
@@ -522,7 +523,8 @@ typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint
* @retval The new state of __FLAG__ (SET or RESET).
*/
#define FMPI2C_FLAG_MASK (0x0001FFFFU)
-#define __HAL_FMPI2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+#define __HAL_FMPI2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \
+ (__FLAG__)) == (__FLAG__)) ? SET : RESET)
/** @brief Clear the FMPI2C pending flags which are cleared by writing 1 in a specific bit.
* @param __HANDLE__ specifies the FMPI2C Handle.
@@ -542,7 +544,7 @@ typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint
* @retval None
*/
#define __HAL_FMPI2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == FMPI2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
- : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
+ : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
/** @brief Enable the specified FMPI2C peripheral.
* @param __HANDLE__ specifies the FMPI2C Handle.
@@ -584,7 +586,8 @@ void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_FMPI2C_RegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, HAL_FMPI2C_CallbackIDTypeDef CallbackID, pFMPI2C_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FMPI2C_RegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, HAL_FMPI2C_CallbackIDTypeDef CallbackID,
+ pFMPI2C_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_FMPI2C_UnRegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, HAL_FMPI2C_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_FMPI2C_RegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2c, pFMPI2C_AddrCallbackTypeDef pCallback);
@@ -599,49 +602,70 @@ HAL_StatusTypeDef HAL_FMPI2C_UnRegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2
*/
/* IO operation functions ****************************************************/
/******* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout);
HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint32_t Trials,
+ uint32_t Timeout);
/******* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size);
HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-
-HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions);
HAL_StatusTypeDef HAL_FMPI2C_EnableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c);
HAL_StatusTypeDef HAL_FMPI2C_DisableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c);
HAL_StatusTypeDef HAL_FMPI2C_Master_Abort_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress);
/******* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size);
HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-
-HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions);
/**
* @}
*/
/** @addtogroup FMPI2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
- * @{
- */
+ * @{
+ */
/******* FMPI2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
void HAL_FMPI2C_EV_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c);
void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c);
@@ -733,7 +757,8 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c);
#define IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPI2C_OTHER_FRAME) || \
((REQUEST) == FMPI2C_OTHER_AND_LAST_FRAME))
-#define FMPI2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_RD_WRN)))
+#define FMPI2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
+ (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_RD_WRN)))
#define FMPI2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) >> 16U))
#define FMPI2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) >> 16U))
@@ -744,13 +769,15 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c);
#define IS_FMPI2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define IS_FMPI2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
-#define FMPI2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
+#define FMPI2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \
+ (uint16_t)(0xFF00U))) >> 8U)))
#define FMPI2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define FMPI2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPI2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & (~FMPI2C_CR2_RD_WRN)) : \
- (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN)))
+ (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN)))
-#define FMPI2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & FMPI2C_FLAG_MASK)) == ((__FLAG__) & FMPI2C_FLAG_MASK)) ? SET : RESET)
+#define FMPI2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & FMPI2C_FLAG_MASK)) == \
+ ((__FLAG__) & FMPI2C_FLAG_MASK)) ? SET : RESET)
#define FMPI2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
/**
* @}
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c_ex.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c_ex.h
index 2be2c288e2..326b05853a 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c_ex.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c_ex.h
@@ -39,7 +39,6 @@ extern "C" {
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
-
/** @defgroup FMPI2CEx_Exported_Constants FMPI2C Extended Exported Constants
* @{
*/
@@ -67,22 +66,49 @@ extern "C" {
*/
/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
+/** @defgroup FMPI2CEx_Exported_Macros FMPI2C Extended Exported Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
/** @addtogroup FMPI2CEx_Exported_Functions FMPI2C Extended Exported Functions
* @{
*/
-/** @addtogroup FMPI2CEx_Exported_Functions_Group1 Extended features functions
- * @brief Extended features functions
+/** @addtogroup FMPI2CEx_Exported_Functions_Group1 FMPI2C Extended Filter Mode Functions
* @{
*/
-
/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_FMPI2CEx_ConfigAnalogFilter(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t AnalogFilter);
HAL_StatusTypeDef HAL_FMPI2CEx_ConfigDigitalFilter(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t DigitalFilter);
+/**
+ * @}
+ */
+
+/** @addtogroup FMPI2CEx_Exported_Functions_Group2 FMPI2C Extended WakeUp Mode Functions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @addtogroup FMPI2CEx_Exported_Functions_Group3 FMPI2C Extended FastModePlus Functions
+ * @{
+ */
void HAL_FMPI2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
/* Private constants ---------------------------------------------------------*/
/** @defgroup FMPI2CEx_Private_Constants FMPI2C Extended Private Constants
@@ -98,17 +124,12 @@ void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
* @{
*/
#define IS_FMPI2C_ANALOG_FILTER(FILTER) (((FILTER) == FMPI2C_ANALOGFILTER_ENABLE) || \
- ((FILTER) == FMPI2C_ANALOGFILTER_DISABLE))
+ ((FILTER) == FMPI2C_ANALOGFILTER_DISABLE))
#define IS_FMPI2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define IS_FMPI2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (FMPI2C_FASTMODEPLUS_SCL)) == FMPI2C_FASTMODEPLUS_SCL) || \
- (((__CONFIG__) & (FMPI2C_FASTMODEPLUS_SDA)) == FMPI2C_FASTMODEPLUS_SDA))
-
-
-
-
-
+ (((__CONFIG__) & (FMPI2C_FASTMODEPLUS_SDA)) == FMPI2C_FASTMODEPLUS_SDA))
/**
* @}
*/
@@ -130,14 +151,6 @@ void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
* @}
*/
-/**
- * @}
- */
-
-/**
- * @}
- */
-
#endif /* FMPI2C_CR1_PE */
#ifdef __cplusplus
}
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus.h
new file mode 100644
index 0000000000..c0dce28974
--- /dev/null
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus.h
@@ -0,0 +1,764 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_fmpsmbus.h
+ * @author MCD Application Team
+ * @brief Header file of FMPSMBUS HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F4xx_HAL_FMPSMBUS_H
+#define STM32F4xx_HAL_FMPSMBUS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(FMPI2C_CR1_PE)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+#include "stm32f4xx_hal_fmpsmbus_ex.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FMPSMBUS
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FMPSMBUS_Exported_Types FMPSMBUS Exported Types
+ * @{
+ */
+
+/** @defgroup FMPSMBUS_Configuration_Structure_definition FMPSMBUS Configuration Structure definition
+ * @brief FMPSMBUS Configuration Structure definition
+ * @{
+ */
+typedef struct
+{
+ uint32_t Timing; /*!< Specifies the FMPSMBUS_TIMINGR_register value.
+ This parameter calculated by referring to FMPSMBUS initialization
+ section in Reference manual */
+ uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not.
+ This parameter can be a value of @ref FMPSMBUS_Analog_Filter */
+
+ uint32_t OwnAddress1; /*!< Specifies the first device own address.
+ This parameter can be a 7-bit or 10-bit address. */
+
+ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
+ This parameter can be a value of @ref FMPSMBUS_addressing_mode */
+
+ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
+ This parameter can be a value of @ref FMPSMBUS_dual_addressing_mode */
+
+ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
+ This parameter can be a 7-bit address. */
+
+ uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
+ This parameter can be a value of @ref FMPSMBUS_own_address2_masks. */
+
+ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
+ This parameter can be a value of @ref FMPSMBUS_general_call_addressing_mode. */
+
+ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
+ This parameter can be a value of @ref FMPSMBUS_nostretch_mode */
+
+ uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected.
+ This parameter can be a value of @ref FMPSMBUS_packet_error_check_mode */
+
+ uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected.
+ This parameter can be a value of @ref FMPSMBUS_peripheral_mode */
+
+ uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits FMPSMBUS_TIMEOUT_register value.
+ (Enable bits and different timeout values)
+ This parameter calculated by referring to FMPSMBUS initialization
+ section in Reference manual */
+} FMPSMBUS_InitTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HAL_state_definition HAL state definition
+ * @brief HAL State definition
+ * @{
+ */
+#define HAL_FMPSMBUS_STATE_RESET (0x00000000U) /*!< FMPSMBUS not yet initialized or disabled */
+#define HAL_FMPSMBUS_STATE_READY (0x00000001U) /*!< FMPSMBUS initialized and ready for use */
+#define HAL_FMPSMBUS_STATE_BUSY (0x00000002U) /*!< FMPSMBUS internal process is ongoing */
+#define HAL_FMPSMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */
+#define HAL_FMPSMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */
+#define HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */
+#define HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */
+#define HAL_FMPSMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */
+#define HAL_FMPSMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */
+#define HAL_FMPSMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_Error_Code_definition FMPSMBUS Error Code definition
+ * @brief FMPSMBUS Error Code definition
+ * @{
+ */
+#define HAL_FMPSMBUS_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_FMPSMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */
+#define HAL_FMPSMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */
+#define HAL_FMPSMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */
+#define HAL_FMPSMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */
+#define HAL_FMPSMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */
+#define HAL_FMPSMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */
+#define HAL_FMPSMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */
+#define HAL_FMPSMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */
+#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
+#define HAL_FMPSMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
+#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
+#define HAL_FMPSMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_handle_Structure_definition FMPSMBUS handle Structure definition
+ * @brief FMPSMBUS handle Structure definition
+ * @{
+ */
+#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
+typedef struct __FMPSMBUS_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
+{
+ FMPI2C_TypeDef *Instance; /*!< FMPSMBUS registers base address */
+
+ FMPSMBUS_InitTypeDef Init; /*!< FMPSMBUS communication parameters */
+
+ uint8_t *pBuffPtr; /*!< Pointer to FMPSMBUS transfer buffer */
+
+ uint16_t XferSize; /*!< FMPSMBUS transfer size */
+
+ __IO uint16_t XferCount; /*!< FMPSMBUS transfer counter */
+
+ __IO uint32_t XferOptions; /*!< FMPSMBUS transfer options */
+
+ __IO uint32_t PreviousState; /*!< FMPSMBUS communication Previous state */
+
+ HAL_LockTypeDef Lock; /*!< FMPSMBUS locking object */
+
+ __IO uint32_t State; /*!< FMPSMBUS communication state */
+
+ __IO uint32_t ErrorCode; /*!< FMPSMBUS Error code */
+
+#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
+ void (* MasterTxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Master Tx Transfer completed callback */
+ void (* MasterRxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Master Rx Transfer completed callback */
+ void (* SlaveTxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Slave Tx Transfer completed callback */
+ void (* SlaveRxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Slave Rx Transfer completed callback */
+ void (* ListenCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Listen Complete callback */
+ void (* ErrorCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Error callback */
+
+ void (* AddrCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< FMPSMBUS Slave Address Match callback */
+
+ void (* MspInitCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Msp Init callback */
+ void (* MspDeInitCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Msp DeInit callback */
+
+#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
+} FMPSMBUS_HandleTypeDef;
+
+#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL FMPSMBUS Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_FMPSMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< FMPSMBUS Master Tx Transfer completed callback ID */
+ HAL_FMPSMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< FMPSMBUS Master Rx Transfer completed callback ID */
+ HAL_FMPSMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< FMPSMBUS Slave Tx Transfer completed callback ID */
+ HAL_FMPSMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< FMPSMBUS Slave Rx Transfer completed callback ID */
+ HAL_FMPSMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< FMPSMBUS Listen Complete callback ID */
+ HAL_FMPSMBUS_ERROR_CB_ID = 0x05U, /*!< FMPSMBUS Error callback ID */
+
+ HAL_FMPSMBUS_MSPINIT_CB_ID = 0x06U, /*!< FMPSMBUS Msp Init callback ID */
+ HAL_FMPSMBUS_MSPDEINIT_CB_ID = 0x07U /*!< FMPSMBUS Msp DeInit callback ID */
+
+} HAL_FMPSMBUS_CallbackIDTypeDef;
+
+/**
+ * @brief HAL FMPSMBUS Callback pointer definition
+ */
+typedef void (*pFMPSMBUS_CallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< pointer to an FMPSMBUS callback function */
+typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an FMPSMBUS Address Match callback function */
+
+#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FMPSMBUS_Exported_Constants FMPSMBUS Exported Constants
+ * @{
+ */
+
+/** @defgroup FMPSMBUS_Analog_Filter FMPSMBUS Analog Filter
+ * @{
+ */
+#define FMPSMBUS_ANALOGFILTER_ENABLE (0x00000000U)
+#define FMPSMBUS_ANALOGFILTER_DISABLE FMPI2C_CR1_ANFOFF
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_addressing_mode FMPSMBUS addressing mode
+ * @{
+ */
+#define FMPSMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
+#define FMPSMBUS_ADDRESSINGMODE_10BIT (0x00000002U)
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_dual_addressing_mode FMPSMBUS dual addressing mode
+ * @{
+ */
+
+#define FMPSMBUS_DUALADDRESS_DISABLE (0x00000000U)
+#define FMPSMBUS_DUALADDRESS_ENABLE FMPI2C_OAR2_OA2EN
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_own_address2_masks FMPSMBUS ownaddress2 masks
+ * @{
+ */
+
+#define FMPSMBUS_OA2_NOMASK ((uint8_t)0x00U)
+#define FMPSMBUS_OA2_MASK01 ((uint8_t)0x01U)
+#define FMPSMBUS_OA2_MASK02 ((uint8_t)0x02U)
+#define FMPSMBUS_OA2_MASK03 ((uint8_t)0x03U)
+#define FMPSMBUS_OA2_MASK04 ((uint8_t)0x04U)
+#define FMPSMBUS_OA2_MASK05 ((uint8_t)0x05U)
+#define FMPSMBUS_OA2_MASK06 ((uint8_t)0x06U)
+#define FMPSMBUS_OA2_MASK07 ((uint8_t)0x07U)
+/**
+ * @}
+ */
+
+
+/** @defgroup FMPSMBUS_general_call_addressing_mode FMPSMBUS general call addressing mode
+ * @{
+ */
+#define FMPSMBUS_GENERALCALL_DISABLE (0x00000000U)
+#define FMPSMBUS_GENERALCALL_ENABLE FMPI2C_CR1_GCEN
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_nostretch_mode FMPSMBUS nostretch mode
+ * @{
+ */
+#define FMPSMBUS_NOSTRETCH_DISABLE (0x00000000U)
+#define FMPSMBUS_NOSTRETCH_ENABLE FMPI2C_CR1_NOSTRETCH
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_packet_error_check_mode FMPSMBUS packet error check mode
+ * @{
+ */
+#define FMPSMBUS_PEC_DISABLE (0x00000000U)
+#define FMPSMBUS_PEC_ENABLE FMPI2C_CR1_PECEN
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_peripheral_mode FMPSMBUS peripheral mode
+ * @{
+ */
+#define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_HOST FMPI2C_CR1_SMBHEN
+#define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE (0x00000000U)
+#define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP FMPI2C_CR1_SMBDEN
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_ReloadEndMode_definition FMPSMBUS ReloadEndMode definition
+ * @{
+ */
+
+#define FMPSMBUS_SOFTEND_MODE (0x00000000U)
+#define FMPSMBUS_RELOAD_MODE FMPI2C_CR2_RELOAD
+#define FMPSMBUS_AUTOEND_MODE FMPI2C_CR2_AUTOEND
+#define FMPSMBUS_SENDPEC_MODE FMPI2C_CR2_PECBYTE
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_StartStopMode_definition FMPSMBUS StartStopMode definition
+ * @{
+ */
+
+#define FMPSMBUS_NO_STARTSTOP (0x00000000U)
+#define FMPSMBUS_GENERATE_STOP (uint32_t)(0x80000000U | FMPI2C_CR2_STOP)
+#define FMPSMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN)
+#define FMPSMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START)
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_XferOptions_definition FMPSMBUS XferOptions definition
+ * @{
+ */
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition when direction change
+ * 2- No Restart condition in other use cases
+ */
+#define FMPSMBUS_FIRST_FRAME FMPSMBUS_SOFTEND_MODE
+#define FMPSMBUS_NEXT_FRAME ((uint32_t)(FMPSMBUS_RELOAD_MODE | FMPSMBUS_SOFTEND_MODE))
+#define FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC FMPSMBUS_AUTOEND_MODE
+#define FMPSMBUS_LAST_FRAME_NO_PEC FMPSMBUS_AUTOEND_MODE
+#define FMPSMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_SOFTEND_MODE | FMPSMBUS_SENDPEC_MODE))
+#define FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE))
+#define FMPSMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE))
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition in all use cases (direction change or not)
+ */
+#define FMPSMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
+#define FMPSMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
+#define FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
+#define FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_Interrupt_configuration_definition FMPSMBUS Interrupt configuration definition
+ * @brief FMPSMBUS Interrupt definition
+ * Elements values convention: 0xXXXXXXXX
+ * - XXXXXXXX : Interrupt control mask
+ * @{
+ */
+#define FMPSMBUS_IT_ERRI FMPI2C_CR1_ERRIE
+#define FMPSMBUS_IT_TCI FMPI2C_CR1_TCIE
+#define FMPSMBUS_IT_STOPI FMPI2C_CR1_STOPIE
+#define FMPSMBUS_IT_NACKI FMPI2C_CR1_NACKIE
+#define FMPSMBUS_IT_ADDRI FMPI2C_CR1_ADDRIE
+#define FMPSMBUS_IT_RXI FMPI2C_CR1_RXIE
+#define FMPSMBUS_IT_TXI FMPI2C_CR1_TXIE
+#define FMPSMBUS_IT_TX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI | \
+ FMPSMBUS_IT_TXI)
+#define FMPSMBUS_IT_RX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_NACKI | FMPSMBUS_IT_RXI)
+#define FMPSMBUS_IT_ALERT (FMPSMBUS_IT_ERRI)
+#define FMPSMBUS_IT_ADDR (FMPSMBUS_IT_ADDRI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI)
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_Flag_definition FMPSMBUS Flag definition
+ * @brief Flag definition
+ * Elements values convention: 0xXXXXYYYY
+ * - XXXXXXXX : Flag mask
+ * @{
+ */
+
+#define FMPSMBUS_FLAG_TXE FMPI2C_ISR_TXE
+#define FMPSMBUS_FLAG_TXIS FMPI2C_ISR_TXIS
+#define FMPSMBUS_FLAG_RXNE FMPI2C_ISR_RXNE
+#define FMPSMBUS_FLAG_ADDR FMPI2C_ISR_ADDR
+#define FMPSMBUS_FLAG_AF FMPI2C_ISR_NACKF
+#define FMPSMBUS_FLAG_STOPF FMPI2C_ISR_STOPF
+#define FMPSMBUS_FLAG_TC FMPI2C_ISR_TC
+#define FMPSMBUS_FLAG_TCR FMPI2C_ISR_TCR
+#define FMPSMBUS_FLAG_BERR FMPI2C_ISR_BERR
+#define FMPSMBUS_FLAG_ARLO FMPI2C_ISR_ARLO
+#define FMPSMBUS_FLAG_OVR FMPI2C_ISR_OVR
+#define FMPSMBUS_FLAG_PECERR FMPI2C_ISR_PECERR
+#define FMPSMBUS_FLAG_TIMEOUT FMPI2C_ISR_TIMEOUT
+#define FMPSMBUS_FLAG_ALERT FMPI2C_ISR_ALERT
+#define FMPSMBUS_FLAG_BUSY FMPI2C_ISR_BUSY
+#define FMPSMBUS_FLAG_DIR FMPI2C_ISR_DIR
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup FMPSMBUS_Exported_Macros FMPSMBUS Exported Macros
+ * @{
+ */
+
+/** @brief Reset FMPSMBUS handle state.
+ * @param __HANDLE__ specifies the FMPSMBUS Handle.
+ * @retval None
+ */
+#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
+#define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET)
+#endif
+
+/** @brief Enable the specified FMPSMBUS interrupts.
+ * @param __HANDLE__ specifies the FMPSMBUS Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable
+ * @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable
+ * @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable
+ * @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable
+ * @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable
+ * @arg @ref FMPSMBUS_IT_RXI RX interrupt enable
+ * @arg @ref FMPSMBUS_IT_TXI TX interrupt enable
+ *
+ * @retval None
+ */
+#define __HAL_FMPSMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
+
+/** @brief Disable the specified FMPSMBUS interrupts.
+ * @param __HANDLE__ specifies the FMPSMBUS Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable
+ * @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable
+ * @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable
+ * @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable
+ * @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable
+ * @arg @ref FMPSMBUS_IT_RXI RX interrupt enable
+ * @arg @ref FMPSMBUS_IT_TXI TX interrupt enable
+ *
+ * @retval None
+ */
+#define __HAL_FMPSMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
+
+/** @brief Check whether the specified FMPSMBUS interrupt source is enabled or not.
+ * @param __HANDLE__ specifies the FMPSMBUS Handle.
+ * @param __INTERRUPT__ specifies the FMPSMBUS interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable
+ * @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable
+ * @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable
+ * @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable
+ * @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable
+ * @arg @ref FMPSMBUS_IT_RXI RX interrupt enable
+ * @arg @ref FMPSMBUS_IT_TXI TX interrupt enable
+ *
+ * @retval The new state of __IT__ (SET or RESET).
+ */
+#define __HAL_FMPSMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Check whether the specified FMPSMBUS flag is set or not.
+ * @param __HANDLE__ specifies the FMPSMBUS Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref FMPSMBUS_FLAG_TXE Transmit data register empty
+ * @arg @ref FMPSMBUS_FLAG_TXIS Transmit interrupt status
+ * @arg @ref FMPSMBUS_FLAG_RXNE Receive data register not empty
+ * @arg @ref FMPSMBUS_FLAG_ADDR Address matched (slave mode)
+ * @arg @ref FMPSMBUS_FLAG_AF NACK received flag
+ * @arg @ref FMPSMBUS_FLAG_STOPF STOP detection flag
+ * @arg @ref FMPSMBUS_FLAG_TC Transfer complete (master mode)
+ * @arg @ref FMPSMBUS_FLAG_TCR Transfer complete reload
+ * @arg @ref FMPSMBUS_FLAG_BERR Bus error
+ * @arg @ref FMPSMBUS_FLAG_ARLO Arbitration lost
+ * @arg @ref FMPSMBUS_FLAG_OVR Overrun/Underrun
+ * @arg @ref FMPSMBUS_FLAG_PECERR PEC error in reception
+ * @arg @ref FMPSMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
+ * @arg @ref FMPSMBUS_FLAG_ALERT SMBus alert
+ * @arg @ref FMPSMBUS_FLAG_BUSY Bus busy
+ * @arg @ref FMPSMBUS_FLAG_DIR Transfer direction (slave mode)
+ *
+ * @retval The new state of __FLAG__ (SET or RESET).
+ */
+#define FMPSMBUS_FLAG_MASK (0x0001FFFFU)
+#define __HAL_FMPSMBUS_GET_FLAG(__HANDLE__, __FLAG__) \
+ (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & FMPSMBUS_FLAG_MASK)) == ((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET)
+
+/** @brief Clear the FMPSMBUS pending flags which are cleared by writing 1 in a specific bit.
+ * @param __HANDLE__ specifies the FMPSMBUS Handle.
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg @ref FMPSMBUS_FLAG_ADDR Address matched (slave mode)
+ * @arg @ref FMPSMBUS_FLAG_AF NACK received flag
+ * @arg @ref FMPSMBUS_FLAG_STOPF STOP detection flag
+ * @arg @ref FMPSMBUS_FLAG_BERR Bus error
+ * @arg @ref FMPSMBUS_FLAG_ARLO Arbitration lost
+ * @arg @ref FMPSMBUS_FLAG_OVR Overrun/Underrun
+ * @arg @ref FMPSMBUS_FLAG_PECERR PEC error in reception
+ * @arg @ref FMPSMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
+ * @arg @ref FMPSMBUS_FLAG_ALERT SMBus alert
+ *
+ * @retval None
+ */
+#define __HAL_FMPSMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief Enable the specified FMPSMBUS peripheral.
+ * @param __HANDLE__ specifies the FMPSMBUS Handle.
+ * @retval None
+ */
+#define __HAL_FMPSMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE))
+
+/** @brief Disable the specified FMPSMBUS peripheral.
+ * @param __HANDLE__ specifies the FMPSMBUS Handle.
+ * @retval None
+ */
+#define __HAL_FMPSMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE))
+
+/** @brief Generate a Non-Acknowledge FMPSMBUS peripheral in Slave mode.
+ * @param __HANDLE__ specifies the FMPSMBUS Handle.
+ * @retval None
+ */
+#define __HAL_FMPSMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, FMPI2C_CR2_NACK))
+
+/**
+ * @}
+ */
+
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FMPSMBUS_Private_Macro FMPSMBUS Private Macros
+ * @{
+ */
+
+#define IS_FMPSMBUS_ANALOG_FILTER(FILTER) (((FILTER) == FMPSMBUS_ANALOGFILTER_ENABLE) || \
+ ((FILTER) == FMPSMBUS_ANALOGFILTER_DISABLE))
+
+#define IS_FMPSMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
+
+#define IS_FMPSMBUS_ADDRESSING_MODE(MODE) (((MODE) == FMPSMBUS_ADDRESSINGMODE_7BIT) || \
+ ((MODE) == FMPSMBUS_ADDRESSINGMODE_10BIT))
+
+#define IS_FMPSMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == FMPSMBUS_DUALADDRESS_DISABLE) || \
+ ((ADDRESS) == FMPSMBUS_DUALADDRESS_ENABLE))
+
+#define IS_FMPSMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == FMPSMBUS_OA2_NOMASK) || \
+ ((MASK) == FMPSMBUS_OA2_MASK01) || \
+ ((MASK) == FMPSMBUS_OA2_MASK02) || \
+ ((MASK) == FMPSMBUS_OA2_MASK03) || \
+ ((MASK) == FMPSMBUS_OA2_MASK04) || \
+ ((MASK) == FMPSMBUS_OA2_MASK05) || \
+ ((MASK) == FMPSMBUS_OA2_MASK06) || \
+ ((MASK) == FMPSMBUS_OA2_MASK07))
+
+#define IS_FMPSMBUS_GENERAL_CALL(CALL) (((CALL) == FMPSMBUS_GENERALCALL_DISABLE) || \
+ ((CALL) == FMPSMBUS_GENERALCALL_ENABLE))
+
+#define IS_FMPSMBUS_NO_STRETCH(STRETCH) (((STRETCH) == FMPSMBUS_NOSTRETCH_DISABLE) || \
+ ((STRETCH) == FMPSMBUS_NOSTRETCH_ENABLE))
+
+#define IS_FMPSMBUS_PEC(PEC) (((PEC) == FMPSMBUS_PEC_DISABLE) || \
+ ((PEC) == FMPSMBUS_PEC_ENABLE))
+
+#define IS_FMPSMBUS_PERIPHERAL_MODE(MODE) (((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_HOST) || \
+ ((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE) || \
+ ((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP))
+
+#define IS_FMPSMBUS_TRANSFER_MODE(MODE) (((MODE) == FMPSMBUS_RELOAD_MODE) || \
+ ((MODE) == FMPSMBUS_AUTOEND_MODE) || \
+ ((MODE) == FMPSMBUS_SOFTEND_MODE) || \
+ ((MODE) == FMPSMBUS_SENDPEC_MODE) || \
+ ((MODE) == (FMPSMBUS_RELOAD_MODE | FMPSMBUS_SENDPEC_MODE)) || \
+ ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) || \
+ ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_RELOAD_MODE)) || \
+ ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE | FMPSMBUS_RELOAD_MODE )))
+
+
+#define IS_FMPSMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_GENERATE_STOP) || \
+ ((REQUEST) == FMPSMBUS_GENERATE_START_READ) || \
+ ((REQUEST) == FMPSMBUS_GENERATE_START_WRITE) || \
+ ((REQUEST) == FMPSMBUS_NO_STARTSTOP))
+
+
+#define IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
+ ((REQUEST) == FMPSMBUS_FIRST_FRAME) || \
+ ((REQUEST) == FMPSMBUS_NEXT_FRAME) || \
+ ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == FMPSMBUS_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == FMPSMBUS_FIRST_FRAME_WITH_PEC) || \
+ ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
+ ((REQUEST) == FMPSMBUS_LAST_FRAME_WITH_PEC))
+
+#define IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_OTHER_FRAME_NO_PEC) || \
+ ((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == FMPSMBUS_OTHER_FRAME_WITH_PEC) || \
+ ((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
+
+#define FMPSMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \
+ (uint32_t)~((uint32_t)(FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN | FMPI2C_CR1_PECEN)))
+#define FMPSMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
+ (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_RD_WRN)))
+
+#define FMPSMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPSMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & (~FMPI2C_CR2_RD_WRN)) : \
+ (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN)))
+
+#define FMPSMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) >> 17U)
+#define FMPSMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) >> 16U)
+#define FMPSMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_AUTOEND)
+#define FMPSMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_PECBYTE)
+#define FMPSMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & FMPI2C_CR1_ALERTEN)
+
+#define FMPSMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & FMPSMBUS_FLAG_MASK)) == \
+ ((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET)
+#define FMPSMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
+
+#define IS_FMPSMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
+#define IS_FMPSMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FMPSMBUS_Exported_Functions FMPSMBUS Exported Functions
+ * @{
+ */
+
+/** @addtogroup FMPSMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_FMPSMBUS_Init(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+HAL_StatusTypeDef HAL_FMPSMBUS_DeInit(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+void HAL_FMPSMBUS_MspInit(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+void HAL_FMPSMBUS_MspDeInit(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+HAL_StatusTypeDef HAL_FMPSMBUS_ConfigAnalogFilter(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_FMPSMBUS_ConfigDigitalFilter(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t DigitalFilter);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, HAL_FMPSMBUS_CallbackIDTypeDef CallbackID,
+ pFMPSMBUS_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, HAL_FMPSMBUS_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, pFMPSMBUS_AddrCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @addtogroup FMPSMBUS_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+/** @addtogroup Blocking_mode_Polling Blocking mode Polling
+ * @{
+ */
+/******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_FMPSMBUS_IsDeviceReady(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint32_t Trials,
+ uint32_t Timeout);
+/**
+ * @}
+ */
+
+/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
+ * @{
+ */
+/******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPSMBUS_Master_Abort_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress);
+HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions);
+
+HAL_StatusTypeDef HAL_FMPSMBUS_EnableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+HAL_StatusTypeDef HAL_FMPSMBUS_DisableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+HAL_StatusTypeDef HAL_FMPSMBUS_EnableListen_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+HAL_StatusTypeDef HAL_FMPSMBUS_DisableListen_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+/**
+ * @}
+ */
+
+/** @addtogroup FMPSMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+/******* FMPSMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
+void HAL_FMPSMBUS_EV_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+void HAL_FMPSMBUS_ER_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+void HAL_FMPSMBUS_MasterTxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+void HAL_FMPSMBUS_MasterRxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+void HAL_FMPSMBUS_SlaveTxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+void HAL_FMPSMBUS_SlaveRxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+void HAL_FMPSMBUS_AddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
+void HAL_FMPSMBUS_ListenCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+void HAL_FMPSMBUS_ErrorCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+
+/**
+ * @}
+ */
+
+/** @addtogroup FMPSMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @{
+ */
+
+/* Peripheral State and Errors functions **************************************************/
+uint32_t HAL_FMPSMBUS_GetState(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+uint32_t HAL_FMPSMBUS_GetError(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup FMPSMBUS_Private_Functions FMPSMBUS Private Functions
+ * @{
+ */
+/* Private functions are defined in stm32f4xx_hal_fmpsmbus.c file */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* FMPI2C_CR1_PE */
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32F4xx_HAL_FMPSMBUS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus_ex.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus_ex.h
new file mode 100644
index 0000000000..541ce73228
--- /dev/null
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus_ex.h
@@ -0,0 +1,130 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_fmpsmbus_ex.h
+ * @author MCD Application Team
+ * @brief Header file of FMPSMBUS HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F4xx_HAL_FMPSMBUS_EX_H
+#define STM32F4xx_HAL_FMPSMBUS_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(FMPI2C_CR1_PE)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FMPSMBUSEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FMPSMBUSEx_Exported_Constants FMPSMBUS Extended Exported Constants
+ * @{
+ */
+
+/** @defgroup FMPSMBUSEx_FastModePlus FMPSMBUS Extended Fast Mode Plus
+ * @{
+ */
+#define FMPSMBUS_FASTMODEPLUS_SCL SYSCFG_CFGR_FMPI2C1_SCL /*!< Enable Fast Mode Plus on FMPI2C1 SCL pins */
+#define FMPSMBUS_FASTMODEPLUS_SDA SYSCFG_CFGR_FMPI2C1_SDA /*!< Enable Fast Mode Plus on FMPI2C1 SDA pins */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FMPSMBUSEx_Exported_Macros FMPSMBUS Extended Exported Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FMPSMBUSEx_Exported_Functions FMPSMBUS Extended Exported Functions
+ * @{
+ */
+
+/** @addtogroup FMPSMBUSEx_Exported_Functions_Group3 FMPSMBUS Extended FastModePlus Functions
+ * @{
+ */
+void HAL_FMPSMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
+void HAL_FMPSMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FMPSMBUSEx_Private_Constants FMPSMBUS Extended Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FMPSMBUSEx_Private_Macro FMPSMBUS Extended Private Macros
+ * @{
+ */
+#define IS_FMPSMBUS_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (FMPSMBUS_FASTMODEPLUS_SCL)) == FMPSMBUS_FASTMODEPLUS_SCL) || \
+ (((__CONFIG__) & (FMPSMBUS_FASTMODEPLUS_SDA)) == FMPSMBUS_FASTMODEPLUS_SDA))
+/**
+ * @}
+ */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup FMPSMBUSEx_Private_Functions FMPSMBUS Extended Private Functions
+ * @{
+ */
+/* Private functions are defined in stm32f4xx_hal_fmpfmpsmbus_ex.c file */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* FMPI2C_CR1_PE */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F4xx_HAL_FMPSMBUS_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h
index 5110d634b0..38b567d105 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h
@@ -115,22 +115,23 @@ typedef enum
* - Y : Output type (Push Pull or Open Drain)
* - Z : IO Direction mode (Input, Output, Alternate or Analog)
* @{
- */
-#define GPIO_MODE_INPUT 0x00000000U /*!< Input Floating Mode */
-#define GPIO_MODE_OUTPUT_PP 0x00000001U /*!< Output Push Pull Mode */
-#define GPIO_MODE_OUTPUT_OD 0x00000011U /*!< Output Open Drain Mode */
-#define GPIO_MODE_AF_PP 0x00000002U /*!< Alternate Function Push Pull Mode */
-#define GPIO_MODE_AF_OD 0x00000012U /*!< Alternate Function Open Drain Mode */
-
-#define GPIO_MODE_ANALOG 0x00000003U /*!< Analog Mode */
-
-#define GPIO_MODE_IT_RISING 0x10110000U /*!< External Interrupt Mode with Rising edge trigger detection */
-#define GPIO_MODE_IT_FALLING 0x10210000U /*!< External Interrupt Mode with Falling edge trigger detection */
-#define GPIO_MODE_IT_RISING_FALLING 0x10310000U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-
-#define GPIO_MODE_EVT_RISING 0x10120000U /*!< External Event Mode with Rising edge trigger detection */
-#define GPIO_MODE_EVT_FALLING 0x10220000U /*!< External Event Mode with Falling edge trigger detection */
-#define GPIO_MODE_EVT_RISING_FALLING 0x10320000U /*!< External Event Mode with Rising/Falling edge trigger detection */
+ */
+#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */
+#define GPIO_MODE_OUTPUT_PP (MODE_PP | MODE_OUTPUT) /*!< Output Push Pull Mode */
+#define GPIO_MODE_OUTPUT_OD (MODE_OD | MODE_OUTPUT) /*!< Output Open Drain Mode */
+#define GPIO_MODE_AF_PP (MODE_PP | MODE_AF) /*!< Alternate Function Push Pull Mode */
+#define GPIO_MODE_AF_OD (MODE_OD | MODE_AF) /*!< Alternate Function Open Drain Mode */
+
+#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */
+
+#define GPIO_MODE_IT_RISING (EXTI_MODE | GPIO_MODE_IT | RISING_EDGE) /*!< External Interrupt Mode with Rising edge trigger detection */
+#define GPIO_MODE_IT_FALLING (EXTI_MODE | GPIO_MODE_IT | FALLING_EDGE) /*!< External Interrupt Mode with Falling edge trigger detection */
+#define GPIO_MODE_IT_RISING_FALLING (EXTI_MODE | GPIO_MODE_IT | RISING_EDGE | FALLING_EDGE) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+
+#define GPIO_MODE_EVT_RISING (EXTI_MODE | GPIO_MODE_EVT | RISING_EDGE) /*!< External Event Mode with Rising edge trigger detection */
+#define GPIO_MODE_EVT_FALLING (EXTI_MODE | GPIO_MODE_EVT | FALLING_EDGE) /*!< External Event Mode with Falling edge trigger detection */
+#define GPIO_MODE_EVT_RISING_FALLING (EXTI_MODE | GPIO_MODE_EVT | RISING_EDGE | FALLING_EDGE) /*!< External Event Mode with Rising/Falling edge trigger detection */
+
/**
* @}
*/
@@ -252,6 +253,21 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
/** @defgroup GPIO_Private_Constants GPIO Private Constants
* @{
*/
+#define GPIO_MODE 0x00000003U
+#define EXTI_MODE 0x10000000U
+#define GPIO_MODE_IT 0x00010000U
+#define GPIO_MODE_EVT 0x00020000U
+#define RISING_EDGE 0x00100000U
+#define FALLING_EDGE 0x00200000U
+#define GPIO_OUTPUT_TYPE 0x00000010U
+
+#define MODE_INPUT 0x00000000U /*!< Input Mode */
+#define MODE_OUTPUT 0x00000001U /*!< Output Mode */
+#define MODE_AF 0x00000002U /*!< Alternate Function Mode */
+#define MODE_ANALOG 0x00000003U /*!< Analog Mode */
+
+#define MODE_PP 0x00000000U /*!< Push Pull Mode */
+#define MODE_OD 0x00000010U /*!< Open Drain Mode */
/**
* @}
@@ -262,7 +278,7 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
* @{
*/
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
-#define IS_GPIO_PIN(PIN) ((((PIN) & GPIO_PIN_MASK ) != 0x00U) && (((PIN) & ~GPIO_PIN_MASK) == 0x00U))
+#define IS_GPIO_PIN(PIN) (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00U) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00U))
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
((MODE) == GPIO_MODE_OUTPUT_PP) ||\
((MODE) == GPIO_MODE_OUTPUT_OD) ||\
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h
index aa1e34d884..7db36ccaec 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h
@@ -1442,21 +1442,21 @@
/*----------------------------------------------------------------------------*/
/*---------------------------------------- STM32F401xx------------------------*/
-#if defined(STM32F401xC) || defined(STM32F401xE)
+#if defined(STM32F401xC) || defined(STM32F401xE)
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF12_SDIO) || \
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
- ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF4_I2C1) || \
- ((AF) == GPIO_AF4_I2C2) || ((AF) == GPIO_AF4_I2C3) || \
- ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \
- ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF5_SPI4) || \
- ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
- ((AF) == GPIO_AF8_USART6) || ((AF) == GPIO_AF10_OTG_FS) || \
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM9) || \
+ ((AF) == GPIO_AF3_TIM10) || ((AF) == GPIO_AF3_TIM11) || \
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
+ ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF5_SPI4) || \
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF7_USART1) || \
+ ((AF) == GPIO_AF7_USART2) || ((AF) == GPIO_AF8_USART6) || \
((AF) == GPIO_AF9_I2C2) || ((AF) == GPIO_AF9_I2C3) || \
- ((AF) == GPIO_AF15_EVENTOUT))
-
+ ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF15_EVENTOUT))
#endif /* STM32F401xC || STM32F401xE */
/*----------------------------------------------------------------------------*/
/*---------------------------------------- STM32F410xx------------------------*/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hash.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hash.h
index da6d5d92b4..f7c0b9d73e 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hash.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hash.h
@@ -22,7 +22,7 @@
#define STM32F4xx_HAL_HASH_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -51,7 +51,7 @@ typedef struct
uint32_t KeySize; /*!< The key size is used only in HMAC operation. */
- uint8_t* pKey; /*!< The key is used only in HMAC operation. */
+ uint8_t *pKey; /*!< The key is used only in HMAC operation. */
} HASH_InitTypeDef;
@@ -66,7 +66,7 @@ typedef enum
HAL_HASH_STATE_TIMEOUT = 0x06U, /*!< Timeout state */
HAL_HASH_STATE_ERROR = 0x07U, /*!< Error state */
HAL_HASH_STATE_SUSPENDED = 0x08U /*!< Suspended state */
-}HAL_HASH_StateTypeDef;
+} HAL_HASH_StateTypeDef;
/**
* @brief HAL phase structures definition
@@ -81,7 +81,7 @@ typedef enum
(step 2 consists in entering the message text) */
HAL_HASH_PHASE_HMAC_STEP_3 = 0x05U /*!< HASH peripheral is in HMAC step 3 processing phase
(step 3 consists in entering the outer hash function key) */
-}HAL_HASH_PhaseTypeDef;
+} HAL_HASH_PhaseTypeDef;
/**
* @brief HAL HASH mode suspend definitions
@@ -90,7 +90,7 @@ typedef enum
{
HAL_HASH_SUSPEND_NONE = 0x00U, /*!< HASH peripheral suspension not requested */
HAL_HASH_SUSPEND = 0x01U /*!< HASH peripheral suspension is requested */
-}HAL_HASH_SuspendTypeDef;
+} HAL_HASH_SuspendTypeDef;
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
/**
@@ -103,7 +103,7 @@ typedef enum
HAL_HASH_INPUTCPLT_CB_ID = 0x02U, /*!< HASH input completion callback ID */
HAL_HASH_DGSTCPLT_CB_ID = 0x03U, /*!< HASH digest computation completion callback ID */
HAL_HASH_ERROR_CB_ID = 0x04U, /*!< HASH error callback ID */
-}HAL_HASH_CallbackIDTypeDef;
+} HAL_HASH_CallbackIDTypeDef;
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
@@ -152,16 +152,18 @@ typedef struct
__IO uint32_t ErrorCode; /*!< HASH Error code */
+ __IO uint32_t Accumulation; /*!< HASH multi buffers accumulation flag */
+
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
- void (* InCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH input completion callback */
+ void (* InCpltCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH input completion callback */
- void (* DgstCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH digest computation completion callback */
+ void (* DgstCpltCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH digest computation completion callback */
- void (* ErrorCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH error callback */
+ void (* ErrorCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH error callback */
- void (* MspInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp Init callback */
+ void (* MspInitCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH Msp Init callback */
- void (* MspDeInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp DeInit callback */
+ void (* MspDeInitCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH Msp DeInit callback */
#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
} HASH_HandleTypeDef;
@@ -170,7 +172,7 @@ typedef struct
/**
* @brief HAL HASH Callback pointer definition
*/
-typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer to a HASH common callback functions */
+typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef *hhash); /*!< pointer to a HASH common callback functions */
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
/**
@@ -226,11 +228,11 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
/** @defgroup HASH_flags_definition HASH flags definitions
* @{
*/
-#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : a new block can be entered in the IP */
-#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
-#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
-#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy, processing a block of data */
-#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : the input buffer contains at least one word of data */
+#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : a new block can be entered in the Peripheral */
+#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
+#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
+#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy, processing a block of data */
+#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : the input buffer contains at least one word of data */
/**
* @}
@@ -248,7 +250,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
/** @defgroup HASH_alias HASH API alias
* @{
*/
-#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< HAL_HASHEx_IRQHandler() is re-directed to HAL_HASH_IRQHandler() for compatibility with legacy code */
+#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */
/**
* @}
*/
@@ -276,7 +278,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
*/
/** @brief Check whether or not the specified HASH flag is set.
- * @param __FLAG__: specifies the flag to check.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
* @arg @ref HASH_FLAG_DCIS Digest calculation complete.
@@ -286,12 +288,12 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? \
- ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
- ((HASH->SR & (__FLAG__)) == (__FLAG__)) )
+ ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
+ ((HASH->SR & (__FLAG__)) == (__FLAG__)) )
/** @brief Clear the specified HASH flag.
- * @param __FLAG__: specifies the flag to clear.
+ * @param __FLAG__ specifies the flag to clear.
* This parameter can be one of the following values:
* @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
* @arg @ref HASH_FLAG_DCIS Digest calculation complete
@@ -301,7 +303,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
/** @brief Enable the specified HASH interrupt.
- * @param __INTERRUPT__: specifies the HASH interrupt source to enable.
+ * @param __INTERRUPT__ specifies the HASH interrupt source to enable.
* This parameter can be one of the following values:
* @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)
* @arg @ref HASH_IT_DCI Digest calculation complete
@@ -310,7 +312,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
#define __HAL_HASH_ENABLE_IT(__INTERRUPT__) SET_BIT(HASH->IMR, (__INTERRUPT__))
/** @brief Disable the specified HASH interrupt.
- * @param __INTERRUPT__: specifies the HASH interrupt source to disable.
+ * @param __INTERRUPT__ specifies the HASH interrupt source to disable.
* This parameter can be one of the following values:
* @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)
* @arg @ref HASH_IT_DCI Digest calculation complete
@@ -319,7 +321,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
#define __HAL_HASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(HASH->IMR, (__INTERRUPT__))
/** @brief Reset HASH handle state.
- * @param __HANDLE__: HASH handle.
+ * @param __HANDLE__ HASH handle.
* @retval None
*/
@@ -335,7 +337,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
/** @brief Reset HASH handle status.
- * @param __HANDLE__: HASH handle.
+ * @param __HANDLE__ HASH handle.
* @retval None
*/
#define __HAL_HASH_RESET_HANDLE_STATUS(__HANDLE__) ((__HANDLE__)->Status = HAL_OK)
@@ -362,9 +364,9 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
/**
* @brief Set the number of valid bits in the last word written in data register DIN.
- * @param __SIZE__: size in bytes of last data written in Data register.
+ * @param __SIZE__ size in bytes of last data written in Data register.
* @retval None
-*/
+ */
#define __HAL_HASH_SET_NBVALIDBITS(__SIZE__) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * ((__SIZE__) % 4U))
/**
@@ -388,11 +390,11 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
*/
#if defined(HASH_CR_MDMAT)
#define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1) ? 20U : \
- ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ? 28U : \
- ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ? 32U : 16U ) ) )
+ ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ? 28U : \
+ ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ? 32U : 16U ) ) )
#else
#define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1) ? 20U : 16)
-#endif
+#endif /* HASH_CR_MDMAT*/
/**
* @brief Return number of words already pushed in the FIFO.
* @retval Number of words already pushed in the FIFO
@@ -401,7 +403,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
/**
* @brief Ensure that HASH input data type is valid.
- * @param __DATATYPE__: HASH input data type.
+ * @param __DATATYPE__ HASH input data type.
* @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)
*/
#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \
@@ -409,21 +411,11 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
((__DATATYPE__) == HASH_DATATYPE_8B) || \
((__DATATYPE__) == HASH_DATATYPE_1B))
-
-
-/**
- * @brief Ensure that input data buffer size is valid for multi-buffer HASH
- * processing in polling mode.
- * @note This check is valid only for multi-buffer HASH processing in polling mode.
- * @param __SIZE__: input data buffer size.
- * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
- */
-#define IS_HASH_POLLING_MULTIBUFFER_SIZE(__SIZE__) (((__SIZE__) % 4U) == 0U)
/**
* @brief Ensure that input data buffer size is valid for multi-buffer HASH
* processing in DMA mode.
* @note This check is valid only for multi-buffer HASH processing in DMA mode.
- * @param __SIZE__: input data buffer size.
+ * @param __SIZE__ input data buffer size.
* @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
*/
#define IS_HASH_DMA_MULTIBUFFER_SIZE(__SIZE__) ((READ_BIT(HASH->CR, HASH_CR_MDMAT) == 0U) || (((__SIZE__) % 4U) == 0U))
@@ -432,21 +424,22 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
* @brief Ensure that input data buffer size is valid for multi-buffer HMAC
* processing in DMA mode.
* @note This check is valid only for multi-buffer HMAC processing in DMA mode.
- * @param __HANDLE__: HASH handle.
- * @param __SIZE__: input data buffer size.
+ * @param __HANDLE__ HASH handle.
+ * @param __SIZE__ input data buffer size.
* @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
*/
-#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4U) == 0U))
+#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET)\
+ || (((__SIZE__) % 4U) == 0U))
/**
* @brief Ensure that handle phase is set to HASH processing.
- * @param __HANDLE__: HASH handle.
+ * @param __HANDLE__ HASH handle.
* @retval SET (handle phase is set to HASH processing) or RESET (handle phase is not set to HASH processing)
*/
#define IS_HASH_PROCESSING(__HANDLE__) ((__HANDLE__)->Phase == HAL_HASH_PHASE_PROCESS)
/**
* @brief Ensure that handle phase is set to HMAC processing.
- * @param __HANDLE__: HASH handle.
+ * @param __HANDLE__ HASH handle.
* @retval SET (handle phase is set to HMAC processing) or RESET (handle phase is not set to HMAC processing)
*/
#define IS_HMAC_PROCESSING(__HANDLE__) (((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || \
@@ -479,7 +472,8 @@ void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID,
+ pHASH_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
@@ -494,10 +488,17 @@ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HAS
/* HASH processing using polling *********************************************/
-HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
+
/**
* @}
@@ -508,8 +509,16 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *p
*/
/* HASH processing using IT **************************************************/
-HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
/**
* @}
@@ -521,9 +530,9 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
/* HASH processing using DMA *************************************************/
HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
/**
* @}
@@ -534,8 +543,10 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBu
*/
/* HASH-MAC processing using polling *****************************************/
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout);
/**
* @}
@@ -545,8 +556,10 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
* @{
*/
-HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
/**
* @}
@@ -572,8 +585,8 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn
/* Peripheral State methods **************************************************/
HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash);
-void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
-void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
+void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer);
+void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer);
void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash);
@@ -593,13 +606,18 @@ uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash);
*/
/* Private functions */
-HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
-HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Algorithm);
HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
-HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
-HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout, uint32_t Algorithm);
+HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Algorithm);
HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hash_ex.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hash_ex.h
index e594b63b2b..0a9844c0ae 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hash_ex.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hash_ex.h
@@ -22,7 +22,7 @@
#define STM32F4xx_HAL_HASH_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -51,10 +51,16 @@
* @{
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
/**
* @}
@@ -64,8 +70,16 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_
* @{
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
/**
* @}
@@ -75,9 +89,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
* @{
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
/**
* @}
@@ -86,8 +100,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p
/** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode
* @{
*/
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
/**
* @}
*/
@@ -96,8 +112,10 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
* @{
*/
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
/**
* @}
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h
index 5f4cccdc5b..c9ac38a956 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h
@@ -33,7 +33,7 @@ extern "C" {
* @{
*/
-/** @addtogroup HCD
+/** @addtogroup HCD HCD
* @{
*/
@@ -109,8 +109,12 @@ typedef struct
* @{
*/
#define HCD_SPEED_HIGH USBH_HS_SPEED
-#define HCD_SPEED_FULL USBH_FS_SPEED
-#define HCD_SPEED_LOW USBH_LS_SPEED
+#define HCD_SPEED_FULL USBH_FSLS_SPEED
+#define HCD_SPEED_LOW USBH_FSLS_SPEED
+
+#define HCD_DEVICE_SPEED_HIGH 0U
+#define HCD_DEVICE_SPEED_FULL 1U
+#define HCD_DEVICE_SPEED_LOW 2U
/**
* @}
@@ -143,9 +147,9 @@ typedef struct
/* Exported macro ------------------------------------------------------------*/
/** @defgroup HCD_Exported_Macros HCD Exported Macros
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
#define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
@@ -170,19 +174,15 @@ typedef struct
/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
-HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
- uint8_t ch_num,
- uint8_t epnum,
- uint8_t dev_address,
- uint8_t speed,
- uint8_t ep_type,
- uint16_t mps);
+HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
+ uint8_t epnum, uint8_t dev_address,
+ uint8_t speed, uint8_t ep_type, uint16_t mps);
-HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
-void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
+void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
/** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition
@@ -191,14 +191,14 @@ void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
*/
typedef enum
{
- HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */
- HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */
- HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */
- HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */
- HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */
+ HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */
+ HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */
+ HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */
+ HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */
+ HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */
- HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */
- HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */
+ HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */
+ HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */
} HAL_HCD_CallbackIDTypeDef;
/**
@@ -218,10 +218,16 @@ typedef void (*pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd,
* @}
*/
-HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd,
+ HAL_HCD_CallbackIDTypeDef CallbackID,
+ pHCD_CallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd,
+ HAL_HCD_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd,
+ pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
/**
@@ -232,25 +238,21 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef
/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
-HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
- uint8_t ch_num,
- uint8_t direction,
- uint8_t ep_type,
- uint8_t token,
- uint8_t *pbuff,
- uint16_t length,
- uint8_t do_ping);
+HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
+ uint8_t direction, uint8_t ep_type,
+ uint8_t token, uint8_t *pbuff,
+ uint16_t length, uint8_t do_ping);
/* Non-Blocking mode: Interrupt */
-void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
- uint8_t chnum,
- HCD_URBStateTypeDef urb_state);
+void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_WKUP_IRQHandler(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum,
+ HCD_URBStateTypeDef urb_state);
/**
* @}
*/
@@ -259,9 +261,9 @@ void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
-HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
/**
* @}
*/
@@ -272,10 +274,11 @@ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
*/
HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
+
/**
* @}
*/
@@ -286,36 +289,17 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
/* Private macros ------------------------------------------------------------*/
/** @defgroup HCD_Private_Macros HCD Private Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup HCD_Private_Functions_Prototypes HCD Private Functions Prototypes
* @{
*/
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup HCD_Private_Functions HCD Private Functions
- * @{
- */
-
/**
* @}
*/
+/* Private functions prototypes ----------------------------------------------*/
-/**
+ /**
* @}
*/
-
-/**
+ /**
* @}
*/
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h
index 2f3f947c4d..9a622b82b3 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h
@@ -85,7 +85,7 @@ typedef struct
* 01 : Abort (Abort user request on going)
* 10 : Timeout
* 11 : Error
- * b5 Peripheral initilisation status
+ * b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
* 1 : Init done (Peripheral initialized and ready to use. HAL I2C Init function called)
* b4 (not used)
@@ -170,6 +170,7 @@ typedef enum
#define HAL_I2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout Error */
#define HAL_I2C_ERROR_SIZE 0x00000040U /*!< Size Management error */
#define HAL_I2C_ERROR_DMA_PARAM 0x00000080U /*!< DMA Parameter Error */
+#define HAL_I2C_WRONG_START 0x00000200U /*!< Wrong start Error */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
#define HAL_I2C_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid Callback error */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
@@ -181,7 +182,11 @@ typedef enum
* @brief I2C handle Structure definition
* @{
*/
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
typedef struct __I2C_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
{
I2C_TypeDef *Instance; /*!< I2C registers base address */
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h
index 6530a5c2ee..1e9676f868 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h
@@ -181,6 +181,7 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid Callback error */
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+#define HAL_I2S_ERROR_BUSY_LINE_RX (0x00000040U) /*!< Busy Rx Line error */
/**
* @}
*/
@@ -286,7 +287,8 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
#define I2S_FLAG_BSY SPI_SR_BSY
-#define I2S_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY)
+#define I2S_FLAG_MASK (SPI_SR_RXNE\
+ | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY)
/**
* @}
*/
@@ -337,7 +339,7 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
} while(0)
#else
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
-#endif
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/** @brief Enable the specified SPI peripheral (in I2S mode).
* @param __HANDLE__ specifies the I2S Handle.
@@ -383,7 +385,8 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
* @arg I2S_IT_ERR: Error interrupt enable
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
+ & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks whether the specified I2S flag is set or not.
* @param __HANDLE__ specifies the I2S Handle.
@@ -405,19 +408,28 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
* @retval None
*/
#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
- __IO uint32_t tmpreg_ovr = 0x00U; \
- tmpreg_ovr = (__HANDLE__)->Instance->DR; \
- tmpreg_ovr = (__HANDLE__)->Instance->SR; \
- UNUSED(tmpreg_ovr); \
+ __IO uint32_t tmpreg_ovr = 0x00U; \
+ tmpreg_ovr = (__HANDLE__)->Instance->DR; \
+ tmpreg_ovr = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg_ovr); \
}while(0U)
/** @brief Clears the I2S UDR pending flag.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\
- __IO uint32_t tmpreg_udr = 0x00U;\
- tmpreg_udr = ((__HANDLE__)->Instance->SR);\
- UNUSED(tmpreg_udr); \
+ __IO uint32_t tmpreg_udr = 0x00U;\
+ tmpreg_udr = ((__HANDLE__)->Instance->SR);\
+ UNUSED(tmpreg_udr); \
+ }while(0U)
+/** @brief Flush the I2S DR Register.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_FLUSH_RX_DR(__HANDLE__) do{\
+ __IO uint32_t tmpreg_dr = 0x00U;\
+ tmpreg_dr = ((__HANDLE__)->Instance->DR);\
+ UNUSED(tmpreg_dr); \
}while(0U)
/**
* @}
@@ -442,7 +454,8 @@ void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
+ pI2S_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/**
@@ -497,21 +510,13 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2S_Private_Constants I2S Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2S_Private_Macros I2S Private Macros
* @{
*/
/** @brief Check whether the specified SPI flag is set or not.
- * @param __SR__ copy of I2S SR regsiter.
+ * @param __SR__ copy of I2S SR register.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
@@ -522,10 +527,11 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
* @arg I2S_FLAG_BSY: Busy flag
* @retval SET or RESET.
*/
-#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
+#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__)\
+ & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
/** @brief Check whether the specified SPI Interrupt is set or not.
- * @param __CR2__ copy of I2S CR2 regsiter.
+ * @param __CR2__ copy of I2S CR2 register.
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
* This parameter can be one of the following values:
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
@@ -533,7 +539,8 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
* @arg I2S_IT_ERR: Error interrupt enable
* @retval SET or RESET.
*/
-#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__)\
+ & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks if I2S Mode parameter is in allowed range.
* @param __MODE__ specifies the I2S Mode.
@@ -561,7 +568,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \
((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
- ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
+ ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
#define IS_I2S_FULLDUPLEX_MODE(MODE) (((MODE) == I2S_FULLDUPLEXMODE_DISABLE) || \
((MODE) == I2S_FULLDUPLEXMODE_ENABLE))
@@ -572,7 +579,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
* @retval None
*/
#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \
- ((__CPOL__) == I2S_CPOL_HIGH))
+ ((__CPOL__) == I2S_CPOL_HIGH))
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || defined(STM32F479xx)
#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s_ex.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s_ex.h
index 19cd806181..10335f49f4 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s_ex.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s_ex.h
@@ -74,7 +74,8 @@ extern "C" {
* @arg I2S_IT_ERR: Error interrupt enable
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_I2SEXT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((I2SxEXT((__HANDLE__)->Instance)->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_I2SEXT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((I2SxEXT((__HANDLE__)->Instance)->CR2\
+ & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks whether the specified I2SExt flag is set or not.
* @param __HANDLE__ specifies the I2S Handle.
@@ -96,19 +97,29 @@ extern "C" {
* @retval None
*/
#define __HAL_I2SEXT_CLEAR_OVRFLAG(__HANDLE__) do{ \
- __IO uint32_t tmpreg_ovr = 0x00U; \
- tmpreg_ovr = I2SxEXT((__HANDLE__)->Instance)->DR;\
- tmpreg_ovr = I2SxEXT((__HANDLE__)->Instance)->SR;\
- UNUSED(tmpreg_ovr); \
+ __IO uint32_t tmpreg_ovr = 0x00U; \
+ tmpreg_ovr = I2SxEXT((__HANDLE__)->Instance)->DR;\
+ tmpreg_ovr = I2SxEXT((__HANDLE__)->Instance)->SR;\
+ UNUSED(tmpreg_ovr); \
}while(0U)
/** @brief Clears the I2SExt UDR pending flag.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2SEXT_CLEAR_UDRFLAG(__HANDLE__) do{ \
- __IO uint32_t tmpreg_udr = 0x00U; \
- tmpreg_udr = I2SxEXT((__HANDLE__)->Instance)->SR;\
- UNUSED(tmpreg_udr); \
+ __IO uint32_t tmpreg_udr = 0x00U; \
+ tmpreg_udr = I2SxEXT((__HANDLE__)->Instance)->SR;\
+ UNUSED(tmpreg_udr); \
+ }while(0U)
+/** @brief Flush the I2S and I2SExt DR Registers.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2SEXT_FLUSH_RX_DR(__HANDLE__) do{ \
+ __IO uint32_t tmpreg_dr = 0x00U; \
+ tmpreg_dr = I2SxEXT((__HANDLE__)->Instance)->DR; \
+ tmpreg_dr = ((__HANDLE__)->Instance->DR); \
+ UNUSED(tmpreg_dr); \
}while(0U)
/**
* @}
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_irda.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_irda.h
index b30945e78f..4d83abc22d 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_irda.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_irda.h
@@ -83,9 +83,9 @@ typedef struct
* 01 : (Not Used)
* 10 : Timeout
* 11 : Error
- * b5 IP initilisation status
+ * b5 IP initialisation status
* 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized. HAL IRDA Init function already called)
+ * 1 : Init done (IP initialized. HAL IRDA Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
@@ -100,9 +100,9 @@ typedef struct
* RxState value coding follow below described bitmap :
* b7-b6 (not used)
* xx : Should be set to 00
- * b5 IP initilisation status
+ * b5 IP initialisation status
* 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized)
+ * 1 : Init done (IP initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
@@ -642,11 +642,11 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
#define IS_IRDA_BAUDRATE(BAUDRATE) ((BAUDRATE) < 115201U)
-#define IRDA_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
+#define IRDA_DIV(_PCLK_, _BAUD_) ((uint32_t)((((uint64_t)(_PCLK_))*25U)/(4U*(((uint64_t)(_BAUD_))))))
#define IRDA_DIVMANT(_PCLK_, _BAUD_) (IRDA_DIV((_PCLK_), (_BAUD_))/100U)
-#define IRDA_DIVFRAQ(_PCLK_, _BAUD_) (((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
+#define IRDA_DIVFRAQ(_PCLK_, _BAUD_) ((((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U) + 50U) / 100U)
/* UART BRR = mantissa + overflow + fraction
= (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h
index ced1099f31..32f5ff027a 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h
@@ -84,13 +84,10 @@ typedef struct
#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
-
/**
* @}
*/
-
-
/**
* @}
*/
@@ -128,7 +125,7 @@ typedef struct
* @{
*/
/* Initialization/Start functions ********************************************/
-HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
/**
* @}
*/
@@ -137,7 +134,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
* @{
*/
/* I/O operation functions ****************************************************/
-HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
/**
* @}
*/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_lptim.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_lptim.h
index 39a8164553..a5ab815fdd 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_lptim.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_lptim.h
@@ -4,7 +4,7 @@
* @author MCD Application Team
* @brief Header file of LPTIM HAL module.
******************************************************************************
- * @attention
+ * @attention
*
* © Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
@@ -13,7 +13,8 @@
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
- * ******************************************************************************
+ *
+ ******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@@ -355,10 +356,10 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
*/
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \
- (__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
+ (__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
#else
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
@@ -376,6 +377,8 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @note The following sequence is required to solve LPTIM disable HW limitation.
* Please check Errata Sheet ES0335 for more details under "MCU may remain
* stuck in LPTIM interrupt when entering Stop mode" section.
+ * @note Please call @ref HAL_LPTIM_GetState() after a call to __HAL_LPTIM_DISABLE to
+ * check for TIMEOUT.
* @retval None
*/
#define __HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__)
@@ -398,6 +401,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @param __HANDLE__ LPTIM handle
* @param __VALUE__ Autoreload value
* @retval None
+ * @note The ARR register can only be modified when the LPTIM instance is enabled.
*/
#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
@@ -406,6 +410,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @param __HANDLE__ LPTIM handle
* @param __VALUE__ Compare value
* @retval None
+ * @note The CMP register can only be modified when the LPTIM instance is enabled.
*/
#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
@@ -454,6 +459,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
* @retval None.
+ * @note The LPTIM interrupts can only be enabled when the LPTIM instance is disabled.
*/
#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
@@ -470,6 +476,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
* @retval None.
+ * @note The LPTIM interrupts can only be disabled when the LPTIM instance is disabled.
*/
#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
@@ -488,7 +495,8 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @retval Interrupt status.
*/
-#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\
+ & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief LPTIM Option Register
* @param __HANDLE__ LPTIM handle
@@ -506,49 +514,58 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @brief Enable interrupt on the LPTIM Wake-up Timer associated Exti line.
* @retval None
*/
-#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR\
+ |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Disable interrupt on the LPTIM Wake-up Timer associated Exti line.
* @retval None
*/
-#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR\
+ &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
/**
* @brief Enable event on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
-#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR\
+ |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Disable event on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
-#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR\
+ &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
+#if defined(EXTI_IMR_MR23)
/**
* @brief Enable falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
-#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR\
+ |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Disable falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
-#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR\
+ &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
/**
* @brief Enable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
-#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR\
+ |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Disable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
-#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR\
+ &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
/**
* @brief Enable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
@@ -563,26 +580,30 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @retval None.
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\
- __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\
}while(0)
/**
* @brief Check whether the LPTIM Wake-up Timer associated Exti line interrupt flag is set or not.
* @retval Line Status.
*/
-#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR\
+ & LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Clear the LPTIM Wake-up Timer associated Exti line flag.
* @retval None.
*/
-#define __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR\
+ = LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Generate a Software interrupt on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
-#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER\
+ |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+#endif /* EXTI_IMR_MR23 */
/**
* @}
@@ -593,6 +614,10 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @{
*/
+/** @addtogroup LPTIM_Exported_Functions_Group1
+ * @brief Initialization and Configuration functions.
+ * @{
+ */
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
@@ -600,7 +625,14 @@ HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
/* MSP functions *************************************************************/
void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
+/**
+ * @}
+ */
+/** @addtogroup LPTIM_Exported_Functions_Group2
+ * @brief Start-Stop operation functions.
+ * @{
+ */
/* Start/Stop operation functions *********************************************/
/* ################################# PWM Mode ################################*/
/* Blocking mode: Polling */
@@ -649,12 +681,26 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+/**
+ * @}
+ */
+/** @addtogroup LPTIM_Exported_Functions_Group3
+ * @brief Read operation functions.
+ * @{
+ */
/* Reading operation functions ************************************************/
uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
+/**
+ * @}
+ */
+/** @addtogroup LPTIM_Exported_Functions_Group4
+ * @brief LPTIM IRQ handler and callback functions.
+ * @{
+ */
/* LPTIM IRQ functions *******************************************************/
void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
@@ -669,12 +715,23 @@ void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID,
+ pLPTIM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+/** @addtogroup LPTIM_Group5
+ * @brief Peripheral State functions.
+ * @{
+ */
/* Peripheral State functions ************************************************/
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
+/**
+ * @}
+ */
/**
* @}
@@ -739,13 +796,13 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
-#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
- ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
- ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
- ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
- ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
- ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
- ((__TRIG__) == LPTIM_TRIGSOURCE_5))
+#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_5))
#define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING ) || \
((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING ) || \
@@ -778,7 +835,7 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
* @{
*/
-void LPTIM_Disable(LPTIM_HandleTypeDef *lptim);
+void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim);
/**
* @}
*/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc.h
index a862f2cc8e..0cab8446ef 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc.h
@@ -25,11 +25,10 @@
extern "C" {
#endif
-#if defined (LTDC)
-
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
+#if defined (LTDC)
/** @addtogroup STM32F4xx_HAL_Driver
* @{
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc_ex.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc_ex.h
index b46457fea4..37a5fdf47a 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc_ex.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc_ex.h
@@ -25,10 +25,11 @@
extern "C" {
#endif
-#if defined (LTDC) && defined (DSI)
-
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
+
+#if defined (LTDC) && defined (DSI)
+
#include "stm32f4xx_hal_dsi.h"
/** @addtogroup STM32F4xx_HAL_Driver
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_mmc.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_mmc.h
index 90a44befcd..e65172acd6 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_mmc.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_mmc.h
@@ -12,25 +12,21 @@
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_MMC_H
-#define __STM32F4xx_HAL_MMC_H
+#ifndef STM32F4xx_HAL_MMC_H
+#define STM32F4xx_HAL_MMC_H
+
+#if defined(SDIO)
#ifdef __cplusplus
extern "C" {
#endif
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
- defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
- defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_ll_sdmmc.h"
@@ -38,8 +34,7 @@
* @{
*/
-/** @defgroup MMC MMC
- * @brief MMC HAL module driver
+/** @addtogroup MMC
* @{
*/
@@ -59,7 +54,7 @@ typedef enum
HAL_MMC_STATE_BUSY = 0x00000003U, /*!< MMC process ongoing */
HAL_MMC_STATE_PROGRAMMING = 0x00000004U, /*!< MMC Programming State */
HAL_MMC_STATE_RECEIVING = 0x00000005U, /*!< MMC Receinving State */
- HAL_MMC_STATE_TRANSFER = 0x00000006U, /*!< MMC Transfert State */
+ HAL_MMC_STATE_TRANSFER = 0x00000006U, /*!< MMC Transfer State */
HAL_MMC_STATE_ERROR = 0x0000000FU /*!< MMC is in error state */
}HAL_MMC_StateTypeDef;
/**
@@ -69,18 +64,17 @@ typedef enum
/** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure
* @{
*/
-typedef enum
-{
- HAL_MMC_CARD_READY = 0x00000001U, /*!< Card state is ready */
- HAL_MMC_CARD_IDENTIFICATION = 0x00000002U, /*!< Card is in identification state */
- HAL_MMC_CARD_STANDBY = 0x00000003U, /*!< Card is in standby state */
- HAL_MMC_CARD_TRANSFER = 0x00000004U, /*!< Card is in transfer state */
- HAL_MMC_CARD_SENDING = 0x00000005U, /*!< Card is sending an operation */
- HAL_MMC_CARD_RECEIVING = 0x00000006U, /*!< Card is receiving operation information */
- HAL_MMC_CARD_PROGRAMMING = 0x00000007U, /*!< Card is in programming state */
- HAL_MMC_CARD_DISCONNECTED = 0x00000008U, /*!< Card is disconnected */
- HAL_MMC_CARD_ERROR = 0x000000FFU /*!< Card response Error */
-}HAL_MMC_CardStateTypeDef;
+typedef uint32_t HAL_MMC_CardStateTypeDef;
+
+#define HAL_MMC_CARD_READY 0x00000001U /*!< Card state is ready */
+#define HAL_MMC_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */
+#define HAL_MMC_CARD_STANDBY 0x00000003U /*!< Card is in standby state */
+#define HAL_MMC_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */
+#define HAL_MMC_CARD_SENDING 0x00000005U /*!< Card is sending an operation */
+#define HAL_MMC_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */
+#define HAL_MMC_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */
+#define HAL_MMC_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */
+#define HAL_MMC_CARD_ERROR 0x000000FFU /*!< Card response Error */
/**
* @}
*/
@@ -121,17 +115,17 @@ typedef struct __MMC_HandleTypeDef
typedef struct
#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
{
- MMC_TypeDef *Instance; /*!< MMC registers base address */
+ MMC_TypeDef *Instance; /*!< MMC registers base address */
MMC_InitTypeDef Init; /*!< MMC required parameters */
HAL_LockTypeDef Lock; /*!< MMC locking object */
- uint32_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */
+ uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */
uint32_t TxXferSize; /*!< MMC Tx Transfer size */
- uint32_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */
+ uint8_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */
uint32_t RxXferSize; /*!< MMC Rx Transfer size */
@@ -146,11 +140,12 @@ typedef struct
DMA_HandleTypeDef *hdmatx; /*!< MMC Tx DMA handle parameters */
HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */
-
+
uint32_t CSD[4U]; /*!< MMC card specific data table */
uint32_t CID[4U]; /*!< MMC card identification number table */
- #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
void (* TxCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
void (* RxCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
void (* ErrorCallback) (struct __MMC_HandleTypeDef *hmmc);
@@ -199,7 +194,7 @@ typedef struct
__IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
__IO uint8_t Reserved3; /*!< Reserved */
__IO uint8_t ContentProtectAppli; /*!< Content protection application */
- __IO uint8_t FileFormatGrouop; /*!< File format group */
+ __IO uint8_t FileFormatGroup; /*!< File format group */
__IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
__IO uint8_t PermWrProtect; /*!< Permanent write protection */
__IO uint8_t TempWrProtect; /*!< Temporary write protection */
@@ -234,28 +229,8 @@ typedef struct
* @}
*/
-/** @defgroup MMC_Exported_Types_Group6 MMC Card Status returned by ACMD13
- * @{
- */
-typedef struct
-{
- __IO uint8_t DataBusWidth; /*!< Shows the currently defined data bus width */
- __IO uint8_t SecuredMode; /*!< Card is in secured mode of operation */
- __IO uint16_t CardType; /*!< Carries information about card type */
- __IO uint32_t ProtectedAreaSize; /*!< Carries information about the capacity of protected area */
- __IO uint8_t SpeedClass; /*!< Carries information about the speed class of the card */
- __IO uint8_t PerformanceMove; /*!< Carries information about the card's performance move */
- __IO uint8_t AllocationUnitSize; /*!< Carries information about the card's allocation unit size */
- __IO uint16_t EraseSize; /*!< Determines the number of AUs to be erased in one operation */
- __IO uint8_t EraseTimeout; /*!< Determines the timeout for any number of AU erase */
- __IO uint8_t EraseOffset; /*!< Carries information about the erase offset */
-
-}HAL_MMC_CardStatusTypeDef;
-/**
- * @}
- */
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
-/** @defgroup MMC_Exported_Types_Group7 MMC Callback ID enumeration definition
+/** @defgroup MMC_Exported_Types_Group6 MMC Callback ID enumeration definition
* @{
*/
typedef enum
@@ -268,15 +243,15 @@ typedef enum
HAL_MMC_MSP_INIT_CB_ID = 0x10U, /*!< MMC MspInit Callback ID */
HAL_MMC_MSP_DEINIT_CB_ID = 0x11U /*!< MMC MspDeInit Callback ID */
}HAL_MMC_CallbackIDTypeDef;
-/**
+/**
* @}
*/
-/** @defgroup MMC_Exported_Types_Group7 MMC Callback pointer definition
+/** @defgroup MMC_Exported_Types_Group7 MMC Callback pointer definition
* @{
*/
typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
-/**
+/**
* @}
*/
#endif
@@ -289,9 +264,7 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
* @{
*/
-#define BLOCKSIZE 512U /*!< Block size is 512 bytes */
-
-#define CAPACITY 0x400000U /*!< Log Block Nuumber for 2 G bytes Cards */
+#define MMC_BLOCKSIZE 512U /*!< Block size is 512 bytes */
/** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition
* @{
@@ -332,6 +305,7 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
+
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */
#endif
@@ -339,16 +313,16 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
* @}
*/
-/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration structure
+/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration
* @{
*/
-#define MMC_CONTEXT_NONE 0x00000000U /*!< None */
-#define MMC_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */
-#define MMC_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */
-#define MMC_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */
-#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */
-#define MMC_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */
-#define MMC_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */
+#define MMC_CONTEXT_NONE 0x00000000U /*!< None */
+#define MMC_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */
+#define MMC_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */
+#define MMC_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */
+#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */
+#define MMC_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */
+#define MMC_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */
/**
* @}
@@ -372,8 +346,9 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
/** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards
* @{
*/
-#define MMC_HIGH_VOLTAGE_CARD 0x00000000U
-#define MMC_DUAL_VOLTAGE_CARD 0x00000001U
+#define MMC_LOW_CAPACITY_CARD 0x00000000U /*!< MMC Card Capacity <=2Gbytes */
+#define MMC_HIGH_CAPACITY_CARD 0x00000001U /*!< MMC Card Capacity >2Gbytes and <2Tbytes */
+
/**
* @}
*/
@@ -427,8 +402,8 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
/**
* @brief Enable the MMC device interrupt.
- * @param __HANDLE__ MMC Handle
- * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled.
+ * @param __HANDLE__: MMC Handle
+ * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -438,7 +413,7 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
@@ -458,8 +433,8 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
/**
* @brief Disable the MMC device interrupt.
- * @param __HANDLE__ MMC Handle
- * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled.
+ * @param __HANDLE__: MMC Handle
+ * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -469,7 +444,7 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
@@ -489,8 +464,8 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
/**
* @brief Check whether the specified MMC flag is set or not.
- * @param __HANDLE__ MMC Handle
- * @param __FLAG__ specifies the flag to check.
+ * @param __HANDLE__: MMC Handle
+ * @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
@@ -500,7 +475,7 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDIO_FLAG_CMDACT: Command transfer in progress
* @arg SDIO_FLAG_TXACT: Data transmit in progress
@@ -520,8 +495,8 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
/**
* @brief Clear the MMC's pending flags.
- * @param __HANDLE__ MMC Handle
- * @param __FLAG__ specifies the flag to clear.
+ * @param __HANDLE__: MMC Handle
+ * @param __FLAG__: specifies the flag to clear.
* This parameter can be one or a combination of the following values:
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
@@ -531,7 +506,7 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
* @retval None
@@ -540,8 +515,8 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
/**
* @brief Check whether the specified MMC interrupt has occurred or not.
- * @param __HANDLE__ MMC Handle
- * @param __INTERRUPT__ specifies the SDMMC interrupt source to check.
+ * @param __HANDLE__: MMC Handle
+ * @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
* This parameter can be one of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -551,7 +526,7 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
@@ -571,8 +546,8 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
/**
* @brief Clear the MMC's interrupt pending bits.
- * @param __HANDLE__ MMC Handle
- * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * @param __HANDLE__: MMC Handle
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -582,7 +557,12 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
* @retval None
*/
@@ -605,6 +585,7 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc);
HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc);
void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc);
void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc);
+
/**
* @}
*/
@@ -652,9 +633,9 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32
* @{
*/
HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc);
-HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID);
-HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD);
-HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);
+HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID);
+HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD);
+HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);
/**
* @}
*/
@@ -740,6 +721,7 @@ HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc);
* @}
*/
+
/**
* @}
*/
@@ -752,15 +734,12 @@ HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc);
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
- STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
- STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
-
#ifdef __cplusplus
}
#endif
+#endif /* SDIO */
-#endif /* __STM32F4xx_HAL_MMC_H */
+#endif /* STM32F4xx_HAL_MMC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h
index 2db595c44c..87b9efa0a9 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h
@@ -96,16 +96,16 @@ typedef struct __PCD_HandleTypeDef
typedef struct
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
- PCD_TypeDef *Instance; /*!< Register base address */
- PCD_InitTypeDef Init; /*!< PCD required parameters */
- __IO uint8_t USB_Address; /*!< USB Address */
- PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
- PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
- HAL_LockTypeDef Lock; /*!< PCD peripheral status */
- __IO PCD_StateTypeDef State; /*!< PCD communication state */
- __IO uint32_t ErrorCode; /*!< PCD Error code */
- uint32_t Setup[12]; /*!< Setup packet buffer */
- PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
+ PCD_TypeDef *Instance; /*!< Register base address */
+ PCD_InitTypeDef Init; /*!< PCD required parameters */
+ __IO uint8_t USB_Address; /*!< USB Address */
+ PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
+ PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
+ HAL_LockTypeDef Lock; /*!< PCD peripheral status */
+ __IO PCD_StateTypeDef State; /*!< PCD communication state */
+ __IO uint32_t ErrorCode; /*!< PCD Error code */
+ uint32_t Setup[12]; /*!< Setup packet buffer */
+ PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
uint32_t BESL;
@@ -187,9 +187,9 @@ typedef struct
/* Exported macros -----------------------------------------------------------*/
/** @defgroup PCD_Exported_Macros PCD Exported Macros
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
@@ -199,12 +199,11 @@ typedef struct
#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
-#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
- ~(USB_OTG_PCGCCTL_STOPCLK)
+#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK)
-#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
+#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
-#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
+#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
@@ -212,20 +211,20 @@ typedef struct
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
- do { \
- EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE); \
- EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE; \
- } while(0U)
+ do { \
+ EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE); \
+ EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE; \
+ } while(0U)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
- do { \
- EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
- EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
- } while(0U)
+ do { \
+ EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
+ EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
+ } while(0U)
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
@@ -260,7 +259,7 @@ typedef enum
HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */
HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */
HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */
- HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
+ HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */
HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */
@@ -287,25 +286,41 @@ typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgType
* @}
*/
-HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
+ HAL_PCD_CallbackIDTypeDef CallbackID,
+ pPCD_CallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd,
+ HAL_PCD_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_DataOutStageCallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_DataInStageCallbackTypeDef pCallback);
+
HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_IsoOutIncpltCallbackTypeDef pCallback);
+
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_IsoInIncpltCallbackTypeDef pCallback);
+
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_BcdCallbackTypeDef pCallback);
+
HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_LpmCallbackTypeDef pCallback);
+
HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/**
@@ -320,6 +335,7 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_WKUP_IRQHandler(PCD_HandleTypeDef *hpcd);
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
@@ -344,16 +360,24 @@ void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
+ uint16_t ep_mps, uint8_t ep_type);
+
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
-uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
+ uint8_t *pBuf, uint32_t len);
+
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
+ uint8_t *pBuf, uint32_t len);
+
+
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+
+uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
/**
* @}
*/
@@ -379,14 +403,6 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @{
*/
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
-#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 0x08U
-#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
-#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
-
-#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 0x08U
-#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
-#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
-
#define USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */
#define USB_OTG_HS_WAKEUP_EXTI_LINE (0x1U << 20) /*!< USB HS EXTI Line WakeUp Interrupt */
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
@@ -427,8 +443,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
/* Private macros ------------------------------------------------------------*/
/** @defgroup PCD_Private_Macros PCD Private Macros
- * @{
- */
+ * @{
+ */
/**
* @}
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_qspi.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_qspi.h
index 4c5de584d8..97e9324f34 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_qspi.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_qspi.h
@@ -6,82 +6,74 @@
******************************************************************************
* @attention
*
- * © Copyright (c) 2017 STMicroelectronics.
+ * © Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
+ * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_QSPI_H
-#define __STM32F4xx_HAL_QSPI_H
+#ifndef STM32F4xx_HAL_QSPI_H
+#define STM32F4xx_HAL_QSPI_H
#ifdef __cplusplus
extern "C" {
#endif
-#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
- defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
+#if defined(QUADSPI)
+
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
/** @addtogroup QSPI
* @{
- */
+ */
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
/** @defgroup QSPI_Exported_Types QSPI Exported Types
* @{
*/
-
-/**
- * @brief QSPI Init structure definition
- */
+/**
+ * @brief QSPI Init structure definition
+ */
typedef struct
{
uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
- This parameter can be a number between 0 and 255 */
-
+ This parameter can be a number between 0 and 255 */
uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
This parameter can be a value between 1 and 32 */
-
- uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
+ uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
This parameter can be a value of @ref QSPI_SampleShifting */
-
- uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
- required to address the flash memory. The flash capacity can be up to 4GB
- (addressed using 32 bits) in indirect mode, but the addressable space in
+ uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
+ required to address the flash memory. The flash capacity can be up to 4GB
+ (addressed using 32 bits) in indirect mode, but the addressable space in
memory-mapped mode is limited to 256MB
This parameter can be a number between 0 and 31 */
-
- uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
+ uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
of clock cycles which the chip select must remain high between commands.
- This parameter can be a value of @ref QSPI_ChipSelectHighTime */
-
+ This parameter can be a value of @ref QSPI_ChipSelectHighTime */
uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
This parameter can be a value of @ref QSPI_ClockMode */
-
uint32_t FlashID; /* Specifies the Flash which will be used,
This parameter can be a value of @ref QSPI_Flash_Select */
-
uint32_t DualFlash; /* Specifies the Dual Flash Mode State
This parameter can be a value of @ref QSPI_DualFlash_Mode */
}QSPI_InitTypeDef;
-/**
- * @brief HAL QSPI State structures definition
- */
+/**
+ * @brief HAL QSPI State structures definition
+ */
typedef enum
{
HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */
@@ -134,17 +126,17 @@ typedef struct
#endif
}QSPI_HandleTypeDef;
-/**
- * @brief QSPI Command structure definition
+/**
+ * @brief QSPI Command structure definition
*/
typedef struct
{
uint32_t Instruction; /* Specifies the Instruction to be sent
This parameter can be a value (8-bit) between 0x00 and 0xFF */
uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
- This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFFU */
+ This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
- This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFFU */
+ This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
uint32_t AddressSize; /* Specifies the Address Size
This parameter can be a value of @ref QSPI_AddressSize */
uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
@@ -159,29 +151,29 @@ typedef struct
This parameter can be a value of @ref QSPI_AlternateBytesMode */
uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
This parameter can be a value of @ref QSPI_DataMode */
- uint32_t NbData; /* Specifies the number of data to transfer.
- This parameter can be any value between 0 and 0xFFFFFFFFU (0 means undefined length
+ uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes)
+ This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
until end of memory)*/
uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
This parameter can be a value of @ref QSPI_DdrMode */
- uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of
- system clock in DDR mode.
+ uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the data
+ output by one half of system clock in DDR mode.
This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
- uint32_t SIOOMode; /* Specifies the send instruction only once mode
+ uint32_t SIOOMode; /* Specifies the send instruction only once mode
This parameter can be a value of @ref QSPI_SIOOMode */
}QSPI_CommandTypeDef;
-/**
- * @brief QSPI Auto Polling mode configuration structure definition
+/**
+ * @brief QSPI Auto Polling mode configuration structure definition
*/
typedef struct
{
uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
- This parameter can be any value between 0 and 0xFFFFFFFFU */
- uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
- This parameter can be any value between 0 and 0xFFFFFFFFU */
+ This parameter can be any value between 0 and 0xFFFFFFFF */
+ uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
+ This parameter can be any value between 0 and 0xFFFFFFFF */
uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
- This parameter can be any value between 0 and 0xFFFFU */
+ This parameter can be any value between 0 and 0xFFFF */
uint32_t StatusBytesSize; /* Specifies the size of the status bytes received.
This parameter can be any value between 1 and 4 */
uint32_t MatchMode; /* Specifies the method used for determining a match.
@@ -190,14 +182,14 @@ typedef struct
This parameter can be a value of @ref QSPI_AutomaticStop */
}QSPI_AutoPollingTypeDef;
-/**
- * @brief QSPI Memory Mapped mode configuration structure definition
+/**
+ * @brief QSPI Memory Mapped mode configuration structure definition
*/
typedef struct
{
uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
- This parameter can be any value between 0 and 0xFFFFU */
- uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select.
+ This parameter can be any value between 0 and 0xFFFF */
+ uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select.
This parameter can be a value of @ref QSPI_TimeOutActivation */
}QSPI_MemoryMappedTypeDef;
@@ -235,41 +227,42 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_Exported_Constants QSPI Exported Constants
* @{
*/
+
/** @defgroup QSPI_ErrorCode QSPI Error Code
* @{
- */
-#define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */
-#define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */
-#define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */
-#define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */
+ */
+#define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */
+#define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */
+#define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */
+#define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
#define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */
#endif
/**
* @}
- */
-
+ */
+
/** @defgroup QSPI_SampleShifting QSPI Sample Shifting
* @{
*/
-#define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!State = HAL_QSPI_STATE_RESET)
#endif
-/** @brief Enable QSPI
- * @param __HANDLE__ specifies the QSPI Handle.
+/** @brief Enable the QSPI peripheral.
+ * @param __HANDLE__ : specifies the QSPI Handle.
* @retval None
- */
+ */
#define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
-/** @brief Disable QSPI
- * @param __HANDLE__ specifies the QSPI Handle.
+/** @brief Disable the QSPI peripheral.
+ * @param __HANDLE__ : specifies the QSPI Handle.
* @retval None
*/
#define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
-/** @brief Enables the specified QSPI interrupt.
- * @param __HANDLE__ specifies the QSPI Handle.
- * @param __INTERRUPT__ specifies the QSPI interrupt source to enable.
+/** @brief Enable the specified QSPI interrupt.
+ * @param __HANDLE__ : specifies the QSPI Handle.
+ * @param __INTERRUPT__ : specifies the QSPI interrupt source to enable.
* This parameter can be one of the following values:
- * @arg QSPI_IT_TO: QSPI Time out interrupt
+ * @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
@@ -503,9 +496,9 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
-/** @brief Disables the specified QSPI interrupt.
- * @param __HANDLE__ specifies the QSPI Handle.
- * @param __INTERRUPT__ specifies the QSPI interrupt source to disable.
+/** @brief Disable the specified QSPI interrupt.
+ * @param __HANDLE__ : specifies the QSPI Handle.
+ * @param __INTERRUPT__ : specifies the QSPI interrupt source to disable.
* This parameter can be one of the following values:
* @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
@@ -516,39 +509,39 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
*/
#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
-/** @brief Checks whether the specified QSPI interrupt source is enabled.
- * @param __HANDLE__ specifies the QSPI Handle.
- * @param __INTERRUPT__ specifies the QSPI interrupt source to check.
+/** @brief Check whether the specified QSPI interrupt source is enabled or not.
+ * @param __HANDLE__ : specifies the QSPI Handle.
+ * @param __INTERRUPT__ : specifies the QSPI interrupt source to check.
* This parameter can be one of the following values:
- * @arg QSPI_IT_TO: QSPI Time out interrupt
+ * @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
* @arg QSPI_IT_TE: QSPI Transfer error interrupt
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
*/
-#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
/**
- * @brief Get the selected QSPI's flag status.
- * @param __HANDLE__ specifies the QSPI Handle.
- * @param __FLAG__ specifies the QSPI flag to check.
+ * @brief Check whether the selected QSPI flag is set or not.
+ * @param __HANDLE__ : specifies the QSPI Handle.
+ * @param __FLAG__ : specifies the QSPI flag to check.
* This parameter can be one of the following values:
* @arg QSPI_FLAG_BUSY: QSPI Busy flag
- * @arg QSPI_FLAG_TO: QSPI Time out flag
+ * @arg QSPI_FLAG_TO: QSPI Timeout flag
* @arg QSPI_FLAG_SM: QSPI Status match flag
* @arg QSPI_FLAG_FT: QSPI FIFO threshold flag
* @arg QSPI_FLAG_TC: QSPI Transfer complete flag
* @arg QSPI_FLAG_TE: QSPI Transfer error flag
* @retval None
*/
-#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U)
+#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
/** @brief Clears the specified QSPI's flag status.
- * @param __HANDLE__ specifies the QSPI Handle.
- * @param __FLAG__ specifies the QSPI clear register flag that needs to be set
+ * @param __HANDLE__ : specifies the QSPI Handle.
+ * @param __FLAG__ : specifies the QSPI clear register flag that needs to be set
* This parameter can be one of the following values:
- * @arg QSPI_FLAG_TO: QSPI Time out flag
+ * @arg QSPI_FLAG_TO: QSPI Timeout flag
* @arg QSPI_FLAG_SM: QSPI Status match flag
* @arg QSPI_FLAG_TC: QSPI Transfer complete flag
* @arg QSPI_FLAG_TE: QSPI Transfer error flag
@@ -558,7 +551,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/**
* @}
*/
-
+
/* Exported functions --------------------------------------------------------*/
/** @addtogroup QSPI_Exported_Functions
* @{
@@ -578,7 +571,7 @@ void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
/** @addtogroup QSPI_Exported_Functions_Group2
* @{
- */
+ */
/* IO operation functions *****************************************************/
/* QSPI IRQ handler method */
void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
@@ -599,13 +592,7 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Co
/* QSPI memory-mapped mode */
HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
-/**
- * @}
- */
-/** @addtogroup QSPI_Exported_Functions_Group3
- * @{
- */
/* Callback functions in non-blocking modes ***********************************/
void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi);
@@ -633,9 +620,9 @@ HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi,
* @}
*/
-/** @addtogroup QSPI_Exported_Functions_Group4
+/** @addtogroup QSPI_Exported_Functions_Group3
* @{
- */
+ */
/* Peripheral Control and State functions ************************************/
HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi);
uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi);
@@ -644,187 +631,123 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
+HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint32_t FlashID);
/**
* @}
*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup QSPI_Private_Macros QSPI Private Macros
- * @{
- */
-/** @defgroup QSPI_ClockPrescaler QSPI Clock Prescaler
- * @{
- */
-#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)
/**
* @}
*/
+/* End of exported functions -------------------------------------------------*/
-/** @defgroup QSPI_FifoThreshold QSPI Fifo Threshold
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup QSPI_Private_Macros QSPI Private Macros
* @{
*/
-#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U))
-/**
- * @}
- */
-
-#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
- ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
+#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)
-/** @defgroup QSPI_FlashSize QSPI Flash Size
- * @{
- */
-#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U))
-/**
- * @}
- */
-
-#define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
- ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
- ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
- ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
- ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
- ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
- ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
- ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
-
-#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
- ((CLKMODE) == QSPI_CLOCK_MODE_3))
-
-#define IS_QSPI_FLASH_ID(FLA) (((FLA) == QSPI_FLASH_ID_1) || \
- ((FLA) == QSPI_FLASH_ID_2))
-
-#define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \
- ((MODE) == QSPI_DUALFLASH_DISABLE))
-
-
-/** @defgroup QSPI_Instruction QSPI Instruction
- * @{
- */
-#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU)
-/**
- * @}
- */
+#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U))
-#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \
- ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
- ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
- ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
+#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
+ ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
-#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \
- ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
- ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
- ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
+#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U))
+#define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
-/** @defgroup QSPI_DummyCycles QSPI Dummy Cycles
- * @{
- */
-#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U)
-/**
- * @}
- */
+#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
+ ((CLKMODE) == QSPI_CLOCK_MODE_3))
-#define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \
- ((MODE) == QSPI_INSTRUCTION_1_LINE) || \
- ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
- ((MODE) == QSPI_INSTRUCTION_4_LINES))
+#define IS_QSPI_FLASH_ID(FLASH_ID) (((FLASH_ID) == QSPI_FLASH_ID_1) || \
+ ((FLASH_ID) == QSPI_FLASH_ID_2))
-#define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \
- ((MODE) == QSPI_ADDRESS_1_LINE) || \
- ((MODE) == QSPI_ADDRESS_2_LINES) || \
- ((MODE) == QSPI_ADDRESS_4_LINES))
+#define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \
+ ((MODE) == QSPI_DUALFLASH_DISABLE))
-#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \
- ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \
- ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
- ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
+#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU)
-#define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \
- ((MODE) == QSPI_DATA_1_LINE) || \
- ((MODE) == QSPI_DATA_2_LINES) || \
- ((MODE) == QSPI_DATA_4_LINES))
+#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \
+ ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
+ ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
+ ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
-#define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
- ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
+#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \
+ ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
+ ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
+ ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
-#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
- ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
+#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U)
-#define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
- ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
+#define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \
+ ((MODE) == QSPI_INSTRUCTION_1_LINE) || \
+ ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
+ ((MODE) == QSPI_INSTRUCTION_4_LINES))
-/** @defgroup QSPI_Interval QSPI Interval
- * @{
- */
-#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
-/**
- * @}
- */
+#define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \
+ ((MODE) == QSPI_ADDRESS_1_LINE) || \
+ ((MODE) == QSPI_ADDRESS_2_LINES) || \
+ ((MODE) == QSPI_ADDRESS_4_LINES))
-/** @defgroup QSPI_StatusBytesSize QSPI Status Bytes Size
- * @{
- */
-#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U))
-/**
- * @}
- */
-#define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \
- ((MODE) == QSPI_MATCH_MODE_OR))
-
-#define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
- ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
+#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \
+ ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \
+ ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
+ ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
-#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
- ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
+#define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \
+ ((MODE) == QSPI_DATA_1_LINE) || \
+ ((MODE) == QSPI_DATA_2_LINES) || \
+ ((MODE) == QSPI_DATA_4_LINES))
-/** @defgroup QSPI_TimeOutPeriod QSPI TimeOut Period
- * @{
- */
-#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU)
-/**
- * @}
- */
+#define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
+ ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
-#define IS_QSPI_GET_FLAG(FLAG) (((FLAG) == QSPI_FLAG_BUSY) || \
- ((FLAG) == QSPI_FLAG_TO) || \
- ((FLAG) == QSPI_FLAG_SM) || \
- ((FLAG) == QSPI_FLAG_FT) || \
- ((FLAG) == QSPI_FLAG_TC) || \
- ((FLAG) == QSPI_FLAG_TE))
+#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
+ ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
-#define IS_QSPI_IT(IT) ((((IT) & 0xFFE0FFFFU) == 0x00000000U) && ((IT) != 0x00000000U))
-/**
- * @}
- */
+#define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
+ ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup QSPI_Private_Functions QSPI Private Functions
- * @{
- */
+#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
-/**
- * @}
- */
+#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U))
+
+#define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \
+ ((MODE) == QSPI_MATCH_MODE_OR))
+#define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
+ ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
+
+#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
+ ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
+
+#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU)
/**
- * @}
- */
+* @}
+*/
+/* End of private macros -----------------------------------------------------*/
/**
* @}
*/
-
+
/**
* @}
*/
-#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx ||
- STM32F413xx || STM32F423xx */
+
+#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F4xx_HAL_QSPI_H */
+#endif /* STM32F4xx_HAL_QSPI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h
index 36a639b45f..2eeff3482e 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h
@@ -976,11 +976,10 @@ typedef struct
* a Power On Reset (POR).
* @param __RTCCLKSource__ specifies the RTC clock source.
* This parameter can be one of the following values:
- @arg @ref RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock.
- * @arg @ref RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
- * @arg @ref RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
- * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected
- * as RTC clock, where x:[2,31]
+ * @arg @ref RCC_RTCCLKSOURCE_NO_CLK : No clock selected as RTC clock.
+ * @arg @ref RCC_RTCCLKSOURCE_LSE : LSE selected as RTC clock.
+ * @arg @ref RCC_RTCCLKSOURCE_LSI : LSI selected as RTC clock.
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
* work in STOP and STANDBY modes, and can be used as wake-up source.
* However, when the HSE clock is used as RTC clock source, the RTC
@@ -1007,8 +1006,7 @@ typedef struct
/**
* @brief Get the RTC and HSE clock divider (RTCPRE).
* @retval Returned value can be one of the following values:
- * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected
- * as RTC clock, where x:[2,31]
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
*/
#define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL)
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h
index 0b8152b12e..df6a66ab14 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h
@@ -103,7 +103,7 @@ typedef struct
*/
typedef struct
{
- uint32_t PLLSAIM; /*!< Spcifies division factor for PLL VCO input clock.
+ uint32_t PLLSAIM; /*!< Specifies division factor for PLL VCO input clock.
This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
@@ -4969,7 +4969,6 @@ typedef struct
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
UNUSED(tmpreg); \
} while(0U)
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_USART3_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
@@ -4977,7 +4976,6 @@ typedef struct
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
UNUSED(tmpreg); \
} while(0U)
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
#if defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_UART4_CLK_ENABLE() do { \
@@ -5098,9 +5096,7 @@ typedef struct
#endif /* STM32F413xx || STM32F423xx */
#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
#if defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
@@ -5140,9 +5136,7 @@ typedef struct
#endif /* STM32F413xx || STM32F423xx */
#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx | STM32F423xx */
#if defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
@@ -5171,9 +5165,7 @@ typedef struct
#endif /* STM32F413xx || STM32F423xx */
#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx | STM32F423xx */
#if defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
@@ -5445,9 +5437,7 @@ typedef struct
#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
#endif /* STM32F413xx || STM32F423xx */
#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
#if defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
@@ -5475,9 +5465,7 @@ typedef struct
#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
#endif /* STM32F413xx || STM32F423xx */
#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
#if defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
@@ -5633,9 +5621,7 @@ typedef struct
#endif /* STM32F413xx || STM32F423xx */
#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN))
#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
#if defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
@@ -5664,9 +5650,7 @@ typedef struct
#endif /* STM32F413xx || STM32F423xx */
#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
#if defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
@@ -6384,7 +6368,7 @@ typedef struct
* @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source.
* This parameter can be one of the following values:
* @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
- * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock.
+ * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernel clock.
* @retval None
*/
#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM1_CLKSOURCE__))
@@ -6392,7 +6376,7 @@ typedef struct
/** @brief Macro to get the DFSDM1 clock source.
* @retval The clock source can be one of the following values:
* @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
- * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock.
+ * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernel clock.
*/
#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))
@@ -6420,7 +6404,7 @@ typedef struct
* @param __DFSDM2_CLKSOURCE__ specifies the DFSDM1 clock source.
* This parameter can be one of the following values:
* @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
- * @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernal clock.
+ * @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernel clock.
* @retval None
*/
#define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM2_CLKSOURCE__))
@@ -6428,7 +6412,7 @@ typedef struct
/** @brief Macro to get the DFSDM2 clock source.
* @retval The clock source can be one of the following values:
* @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
- * @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernal clock.
+ * @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernel clock.
*/
#define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))
@@ -6867,16 +6851,8 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void);
/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
* @{
*/
-#if defined(STM32F411xE)
-#define IS_RCC_PLLN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
-#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
-#else /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||
- STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410Tx || STM32F410Cx ||
- STM32F410Rx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Cx || STM32F412Rx ||
- STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
#define IS_RCC_PLLN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
-#endif /* STM32F411xE */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000007FU))
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rng.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rng.h
index a7b1a59804..d2c9937c47 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rng.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rng.h
@@ -22,7 +22,7 @@
#define STM32F4xx_HAL_RNG_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h
index f5fcfdc6a8..9afa8a1407 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h
@@ -105,12 +105,11 @@ typedef struct
with [1 Sec / SecondFraction +1] granularity.
This field will be used only by HAL_RTC_GetTime function */
- uint32_t DayLightSaving; /*!< Specifies DayLight Save Operation.
- This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
+ uint32_t DayLightSaving; /*!< This interface is deprecated. To manage Daylight Saving Time,
+ please use HAL_RTC_DST_xxx functions */
- uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit
- in CR register to store the operation.
- This parameter can be a value of @ref RTC_StoreOperation_Definitions */
+ uint32_t StoreOperation; /*!< This interface is deprecated. To manage Daylight Saving Time,
+ please use HAL_RTC_DST_xxx functions */
}RTC_TimeTypeDef;
/**
@@ -701,6 +700,11 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
+void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc);
+uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai.h
index 16cbccfae7..0307f92333 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai.h
@@ -22,7 +22,7 @@
#define __STM32F4xx_HAL_SAI_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -56,7 +56,7 @@ typedef enum
HAL_SAI_STATE_BUSY_RX = 0x22U, /*!< Data reception process is ongoing */
HAL_SAI_STATE_TIMEOUT = 0x03U, /*!< SAI timeout state */
HAL_SAI_STATE_ERROR = 0x04U /*!< SAI error state */
-}HAL_SAI_StateTypeDef;
+} HAL_SAI_StateTypeDef;
/**
* @brief SAI Callback prototype
@@ -104,9 +104,10 @@ typedef struct
uint32_t AudioFrequency; /*!< Specifies the audio frequency sampling.
This parameter can be a value of @ref SAI_Audio_Frequency */
- uint32_t Mckdiv; /*!< Specifies the master clock divider, the parameter will be used if for
- AudioFrequency the user choice
- This parameter must be a number between Min_Data = 0 and Max_Data = 15 */
+ uint32_t Mckdiv; /*!< Specifies the master clock divider.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 15.
+ @note This parameter is used only if AudioFrequency is set to
+ SAI_AUDIO_FREQUENCY_MCKDIV otherwise it is internally computed. */
uint32_t MonoStereoMode; /*!< Specifies if the mono or stereo mode is selected.
This parameter can be a value of @ref SAI_Mono_Stereo_Mode */
@@ -131,13 +132,14 @@ typedef struct
uint32_t ClockStrobing; /*!< Specifies the SAI Block clock strobing edge sensitivity.
This parameter can be a value of @ref SAI_Block_Clock_Strobing */
-}SAI_InitTypeDef;
+} SAI_InitTypeDef;
/**
* @}
*/
/** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition
* @brief SAI Frame Init structure definition
+ * @note For SPDIF and AC97 protocol, these parameters are not used (set by hardware).
* @{
*/
typedef struct
@@ -161,13 +163,15 @@ typedef struct
uint32_t FSOffset; /*!< Specifies the Frame synchronization Offset.
This parameter can be a value of @ref SAI_Block_FS_Offset */
-}SAI_FrameInitTypeDef;
+} SAI_FrameInitTypeDef;
/**
* @}
*/
/** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition
* @brief SAI Block Slot Init Structure definition
+ * @note For SPDIF protocol, these parameters are not used (set by hardware).
+ * @note For AC97 protocol, only SlotActive parameter is used (the others are set by hardware).
* @{
*/
typedef struct
@@ -183,7 +187,7 @@ typedef struct
uint32_t SlotActive; /*!< Specifies the slots in audio frame that will be activated.
This parameter can be a value of @ref SAI_Block_Slot_Active */
-}SAI_SlotInitTypeDef;
+} SAI_SlotInitTypeDef;
/**
* @}
*/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai_ex.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai_ex.h
index 3398fb2ddf..fbd44979de 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai_ex.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai_ex.h
@@ -15,18 +15,18 @@
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_SAI_EX_H
#define __STM32F4xx_HAL_SAI_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
+#include "stm32f4xx_hal_def.h"
/** @addtogroup STM32F4xx_HAL_Driver
* @{
@@ -45,12 +45,12 @@
/** @defgroup SAI_Clock_Source SAI Clock Source
* @{
*/
-#if defined(STM32F413xx) || defined(STM32F423xx)
+#if defined(STM32F413xx) || defined(STM32F423xx)
#define SAI_CLKSOURCE_PLLI2S 0x00000000U
#define SAI_CLKSOURCE_EXT 0x00100000U
#define SAI_CLKSOURCE_PLLR 0x00200000U
#define SAI_CLKSOURCE_HS 0x00300000U
-#else
+#else
#define SAI_CLKSOURCE_PLLSAI 0x00000000U
#define SAI_CLKSOURCE_PLLI2S 0x00100000U
#define SAI_CLKSOURCE_EXT 0x00200000U
@@ -61,7 +61,7 @@
/**
* @}
*/
-
+
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SAIEx_Exported_Functions
* @{
@@ -85,7 +85,7 @@ uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai);
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
-#if defined(STM32F413xx) || defined(STM32F423xx)
+#if defined(STM32F413xx) || defined(STM32F423xx)
#define IS_SAI_CLK_SOURCE(SOURCE) (((SOURCE) == SAI_CLKSOURCE_PLLI2S) ||\
((SOURCE) == SAI_CLKSOURCE_EXT)||\
((SOURCE) == SAI_CLKSOURCE_PLLR)||\
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h
index edf33c1a10..e82e7e0ce0 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h
@@ -12,24 +12,20 @@
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_SD_H
-#define __STM32F4xx_HAL_SD_H
+#ifndef STM32F4xx_HAL_SD_H
+#define STM32F4xx_HAL_SD_H
#ifdef __cplusplus
extern "C" {
#endif
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
- defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
- defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+#if defined(SDIO)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_ll_sdmmc.h"
@@ -58,8 +54,8 @@ typedef enum
HAL_SD_STATE_TIMEOUT = 0x00000002U, /*!< SD Timeout state */
HAL_SD_STATE_BUSY = 0x00000003U, /*!< SD process ongoing */
HAL_SD_STATE_PROGRAMMING = 0x00000004U, /*!< SD Programming State */
- HAL_SD_STATE_RECEIVING = 0x00000005U, /*!< SD Receinving State */
- HAL_SD_STATE_TRANSFER = 0x00000006U, /*!< SD Transfert State */
+ HAL_SD_STATE_RECEIVING = 0x00000005U, /*!< SD Receiving State */
+ HAL_SD_STATE_TRANSFER = 0x00000006U, /*!< SD Transfer State */
HAL_SD_STATE_ERROR = 0x0000000FU /*!< SD is in error state */
}HAL_SD_StateTypeDef;
/**
@@ -69,18 +65,17 @@ typedef enum
/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure
* @{
*/
-typedef enum
-{
- HAL_SD_CARD_READY = 0x00000001U, /*!< Card state is ready */
- HAL_SD_CARD_IDENTIFICATION = 0x00000002U, /*!< Card is in identification state */
- HAL_SD_CARD_STANDBY = 0x00000003U, /*!< Card is in standby state */
- HAL_SD_CARD_TRANSFER = 0x00000004U, /*!< Card is in transfer state */
- HAL_SD_CARD_SENDING = 0x00000005U, /*!< Card is sending an operation */
- HAL_SD_CARD_RECEIVING = 0x00000006U, /*!< Card is receiving operation information */
- HAL_SD_CARD_PROGRAMMING = 0x00000007U, /*!< Card is in programming state */
- HAL_SD_CARD_DISCONNECTED = 0x00000008U, /*!< Card is disconnected */
- HAL_SD_CARD_ERROR = 0x000000FFU /*!< Card response Error */
-}HAL_SD_CardStateTypeDef;
+typedef uint32_t HAL_SD_CardStateTypeDef;
+
+#define HAL_SD_CARD_READY 0x00000001U /*!< Card state is ready */
+#define HAL_SD_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */
+#define HAL_SD_CARD_STANDBY 0x00000003U /*!< Card is in standby state */
+#define HAL_SD_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */
+#define HAL_SD_CARD_SENDING 0x00000005U /*!< Card is sending an operation */
+#define HAL_SD_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */
+#define HAL_SD_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */
+#define HAL_SD_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */
+#define HAL_SD_CARD_ERROR 0x000000FFU /*!< Card response Error */
/**
* @}
*/
@@ -117,7 +112,11 @@ typedef struct
/**
* @brief SD handle Structure definition
*/
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
typedef struct __SD_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
{
SD_TypeDef *Instance; /*!< SD registers base address */
@@ -125,11 +124,11 @@ typedef struct __SD_HandleTypeDef
HAL_LockTypeDef Lock; /*!< SD locking object */
- uint32_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */
+ uint8_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */
uint32_t TxXferSize; /*!< SD Tx Transfer size */
- uint32_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */
+ uint8_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */
uint32_t RxXferSize; /*!< SD Rx Transfer size */
@@ -139,9 +138,9 @@ typedef struct __SD_HandleTypeDef
__IO uint32_t ErrorCode; /*!< SD Card Error codes */
- DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */
-
DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */
HAL_SD_CardInfoTypeDef SdCard; /*!< SD Card information */
@@ -149,7 +148,7 @@ typedef struct __SD_HandleTypeDef
uint32_t CID[4]; /*!< SD card identification number table */
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
void (* TxCpltCallback) (struct __SD_HandleTypeDef *hsd);
void (* RxCpltCallback) (struct __SD_HandleTypeDef *hsd);
void (* ErrorCallback) (struct __SD_HandleTypeDef *hsd);
@@ -157,7 +156,7 @@ typedef struct __SD_HandleTypeDef
void (* MspInitCallback) (struct __SD_HandleTypeDef *hsd);
void (* MspDeInitCallback) (struct __SD_HandleTypeDef *hsd);
-#endif
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}SD_HandleTypeDef;
/**
@@ -198,7 +197,7 @@ typedef struct
__IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
__IO uint8_t Reserved3; /*!< Reserved */
__IO uint8_t ContentProtectAppli; /*!< Content protection application */
- __IO uint8_t FileFormatGrouop; /*!< File format group */
+ __IO uint8_t FileFormatGroup; /*!< File format group */
__IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
__IO uint8_t PermWrProtect; /*!< Permanent write protection */
__IO uint8_t TempWrProtect; /*!< Temporary write protection */
@@ -206,7 +205,6 @@ typedef struct
__IO uint8_t ECC; /*!< ECC code */
__IO uint8_t CSD_CRC; /*!< CSD CRC */
__IO uint8_t Reserved4; /*!< Always 1 */
-
}HAL_SD_CardCSDTypeDef;
/**
* @}
@@ -254,7 +252,7 @@ typedef struct
* @}
*/
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
/** @defgroup SD_Exported_Types_Group7 SD Callback ID enumeration definition
* @{
*/
@@ -279,7 +277,7 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
/**
* @}
*/
-#endif
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -331,10 +329,9 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
#define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
#define HAL_SD_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */
-#endif
-
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -342,13 +339,13 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration
* @{
*/
-#define SD_CONTEXT_NONE 0x00000000U /*!< None */
-#define SD_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */
-#define SD_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */
-#define SD_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */
-#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */
-#define SD_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */
-#define SD_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */
+#define SD_CONTEXT_NONE 0x00000000U /*!< None */
+#define SD_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */
+#define SD_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */
+#define SD_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */
+#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */
+#define SD_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */
+#define SD_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */
/**
* @}
@@ -357,8 +354,8 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards
* @{
*/
-#define CARD_SDSC 0x00000000U
-#define CARD_SDHC_SDXC 0x00000001U
+#define CARD_SDSC 0x00000000U /*!< SD Standard Capacity <2Go */
+#define CARD_SDHC_SDXC 0x00000001U /*!< SD High Capacity <32Go, SD Extended Capacity <2To */
#define CARD_SECURED 0x00000003U
/**
@@ -387,7 +384,7 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
* @param __HANDLE__ : SD handle.
* @retval None
*/
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_SD_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
@@ -395,7 +392,7 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
} while(0)
#else
#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SD_STATE_RESET)
-#endif
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
/**
* @brief Enable the SD device.
@@ -423,8 +420,8 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
/**
* @brief Enable the SD device interrupt.
- * @param __HANDLE__ SD Handle
- * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled.
+ * @param __HANDLE__: SD Handle
+ * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -434,7 +431,7 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
@@ -447,15 +444,15 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
* @retval None
*/
#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @brief Disable the SD device interrupt.
- * @param __HANDLE__ SD Handle
- * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled.
+ * @param __HANDLE__: SD Handle
+ * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -465,7 +462,7 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
@@ -478,15 +475,15 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
* @retval None
*/
#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @brief Check whether the specified SD flag is set or not.
- * @param __HANDLE__ SD Handle
- * @param __FLAG__ specifies the flag to check.
+ * @param __HANDLE__: SD Handle
+ * @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
@@ -496,7 +493,7 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDIO_FLAG_CMDACT: Command transfer in progress
* @arg SDIO_FLAG_TXACT: Data transmit in progress
@@ -509,15 +506,15 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
* @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
- * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
+ * @arg SDIO_FLAG_SDIOIT: SDIO interrupt received
* @retval The new state of SD FLAG (SET or RESET).
*/
#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
/**
* @brief Clear the SD's pending flags.
- * @param __HANDLE__ SD Handle
- * @param __FLAG__ specifies the flag to clear.
+ * @param __HANDLE__: SD Handle
+ * @param __FLAG__: specifies the flag to clear.
* This parameter can be one or a combination of the following values:
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
@@ -527,17 +524,17 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
+ * @arg SDIO_FLAG_SDIOIT: SDIO interrupt received
* @retval None
*/
#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
/**
* @brief Check whether the specified SD interrupt has occurred or not.
- * @param __HANDLE__ SD Handle
- * @param __INTERRUPT__ specifies the SDMMC interrupt source to check.
+ * @param __HANDLE__: SD Handle
+ * @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
* This parameter can be one of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -547,7 +544,7 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
@@ -560,15 +557,15 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
* @retval The new state of SD IT (SET or RESET).
*/
#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDIO_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @brief Clear the SD's interrupt pending bits.
- * @param __HANDLE__ SD Handle
- * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * @param __HANDLE__: SD Handle
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -578,8 +575,8 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
+ * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
* @retval None
*/
#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
@@ -627,11 +624,12 @@ void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd);
void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd);
void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd);
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
/* SD callback registering/unregistering */
HAL_StatusTypeDef HAL_SD_RegisterCallback (SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId, pSD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId);
-#endif
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -751,15 +749,13 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
- STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
- STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+#endif /* SDIO */
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F4xx_HAL_SD_H */
+#endif /* STM32F4xx_HAL_SD_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smartcard.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smartcard.h
index d329ac85cc..c3d1544455 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smartcard.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smartcard.h
@@ -101,7 +101,7 @@ typedef struct
* 11 : Error
* b5 IP initilisation status
* 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized. HAL SMARTCARD Init function already called)
+ * 1 : Init done (IP initialized. HAL SMARTCARD Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
@@ -118,7 +118,7 @@ typedef struct
* xx : Should be set to 00
* b5 IP initilisation status
* 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized)
+ * 1 : Init done (IP initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
@@ -718,9 +718,9 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
((NACK) == SMARTCARD_NACK_DISABLE))
#define IS_SMARTCARD_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001U)
-#define SMARTCARD_DIV(__PCLK__, __BAUD__) (((__PCLK__)*25U)/(4U*(__BAUD__)))
+#define SMARTCARD_DIV(__PCLK__, __BAUD__) ((uint32_t)((((uint64_t)(__PCLK__))*25U)/(4U*((uint64_t)(__BAUD__)))))
#define SMARTCARD_DIVMANT(__PCLK__, __BAUD__) (SMARTCARD_DIV((__PCLK__), (__BAUD__))/100U)
-#define SMARTCARD_DIVFRAQ(__PCLK__, __BAUD__) (((SMARTCARD_DIV((__PCLK__), (__BAUD__)) - (SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) * 100U)) * 16U + 50U) / 100U)
+#define SMARTCARD_DIVFRAQ(__PCLK__, __BAUD__) ((((SMARTCARD_DIV((__PCLK__), (__BAUD__)) - (SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) * 100U)) * 16U) + 50U) / 100U)
/* SMARTCARD BRR = mantissa + overflow + fraction
= (SMARTCARD DIVMANT << 4) + (SMARTCARD DIVFRAQ & 0xF0) + (SMARTCARD DIVFRAQ & 0x0FU) */
#define SMARTCARD_BRR(__PCLK__, __BAUD__) (((SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) << 4U) + \
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smbus.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smbus.h
index 0c80fd3ac2..056a600d17 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smbus.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smbus.h
@@ -86,7 +86,7 @@ typedef struct
* 01 : Abort (Abort user request on going)
* 10 : Timeout
* 11 : Error
- * b5 IP initilisation status
+ * b5 IP initialisation status
* 0 : Reset (IP not initialized)
* 1 : Init done (IP initialized and ready to use. HAL SMBUS Init function called)
* b4 (not used)
@@ -609,7 +609,7 @@ void HAL_SMBUS_AbortCpltCallback(SMBUS_HandleTypeDef *hsmbus);
* @}
*/
-/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
+/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State, Mode and Error functions
* @{
*/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h
index c220b21748..f2e07c2c0f 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h
@@ -319,7 +319,8 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
-#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE)
+#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\
+ | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE)
/**
* @}
*/
@@ -346,7 +347,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
} while(0)
#else
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
-#endif
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/** @brief Enable the specified SPI interrupts.
* @param __HANDLE__ specifies the SPI Handle.
@@ -382,7 +383,8 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
* @arg SPI_IT_ERR: Error interrupt enable
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
+ & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified SPI flag is set or not.
* @param __HANDLE__ specifies the SPI Handle.
@@ -440,9 +442,9 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
*/
#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
do{ \
- __IO uint32_t tmpreg_fre = 0x00U; \
- tmpreg_fre = (__HANDLE__)->Instance->SR; \
- UNUSED(tmpreg_fre); \
+ __IO uint32_t tmpreg_fre = 0x00U; \
+ tmpreg_fre = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg_fre); \
}while(0U)
/** @brief Enable the SPI peripheral.
@@ -491,7 +493,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
/** @brief Check whether the specified SPI flag is set or not.
- * @param __SR__ copy of SPI SR regsiter.
+ * @param __SR__ copy of SPI SR register.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
@@ -503,10 +505,11 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
* @arg SPI_FLAG_FRE: Frame format error flag
* @retval SET or RESET.
*/
-#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
+#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \
+ ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
/** @brief Check whether the specified SPI Interrupt is set or not.
- * @param __CR2__ copy of SPI CR2 regsiter.
+ * @param __CR2__ copy of SPI CR2 register.
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
* This parameter can be one of the following values:
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
@@ -514,15 +517,16 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
* @arg SPI_IT_ERR: Error interrupt enable
* @retval SET or RESET.
*/
-#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \
+ (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks if SPI Mode parameter is in allowed range.
* @param __MODE__ specifies the SPI Mode.
* This parameter can be a value of @ref SPI_Mode
* @retval None
*/
-#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \
- ((__MODE__) == SPI_MODE_MASTER))
+#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \
+ ((__MODE__) == SPI_MODE_MASTER))
/** @brief Checks if SPI Direction Mode parameter is in allowed range.
* @param __MODE__ specifies the SPI Direction Mode.
@@ -559,25 +563,25 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
* This parameter can be a value of @ref SPI_Clock_Polarity
* @retval None
*/
-#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
- ((__CPOL__) == SPI_POLARITY_HIGH))
+#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
+ ((__CPOL__) == SPI_POLARITY_HIGH))
/** @brief Checks if SPI Clock Phase parameter is in allowed range.
* @param __CPHA__ specifies the SPI Clock Phase.
* This parameter can be a value of @ref SPI_Clock_Phase
* @retval None
*/
-#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
- ((__CPHA__) == SPI_PHASE_2EDGE))
+#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
+ ((__CPHA__) == SPI_PHASE_2EDGE))
/** @brief Checks if SPI Slave Select parameter is in allowed range.
* @param __NSS__ specifies the SPI Slave Select management parameter.
* This parameter can be a value of @ref SPI_Slave_Select_management
* @retval None
*/
-#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \
- ((__NSS__) == SPI_NSS_HARD_INPUT) || \
- ((__NSS__) == SPI_NSS_HARD_OUTPUT))
+#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \
+ ((__NSS__) == SPI_NSS_HARD_INPUT) || \
+ ((__NSS__) == SPI_NSS_HARD_OUTPUT))
/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range.
* @param __PRESCALER__ specifies the SPI Baudrate prescaler.
@@ -598,16 +602,16 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
* This parameter can be a value of @ref SPI_MSB_LSB_transmission
* @retval None
*/
-#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
- ((__BIT__) == SPI_FIRSTBIT_LSB))
+#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
+ ((__BIT__) == SPI_FIRSTBIT_LSB))
/** @brief Checks if SPI TI mode parameter is in allowed range.
* @param __MODE__ specifies the SPI TI mode.
* This parameter can be a value of @ref SPI_TI_mode
* @retval None
*/
-#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \
- ((__MODE__) == SPI_TIMODE_ENABLE))
+#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \
+ ((__MODE__) == SPI_TIMODE_ENABLE))
/** @brief Checks if SPI CRC calculation enabled state is in allowed range.
* @param __CALCULATION__ specifies the SPI CRC calculation enable state.
@@ -622,7 +626,9 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
* This parameter must be a number between Min_Data = 0 and Max_Data = 65535
* @retval None
*/
-#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U))
+#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \
+ ((__POLYNOMIAL__) <= 0xFFFFU) && \
+ (((__POLYNOMIAL__)&0x1U) != 0U))
/** @brief Checks if DMA handle is valid.
* @param __HANDLE__ specifies a DMA Handle.
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h
index 9f79ad9c70..7ec7310380 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h
@@ -167,7 +167,7 @@ typedef struct
This parameter can be a value of @ref TIM_Encoder_Mode */
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+ This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
uint32_t IC1Selection; /*!< Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */
@@ -179,7 +179,7 @@ typedef struct
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+ This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
uint32_t IC2Selection; /*!< Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */
@@ -231,7 +231,12 @@ typedef struct
uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
This parameter can be a value of @ref TIM_Master_Mode_Selection */
uint32_t MasterSlaveMode; /*!< Master/slave mode selection
- This parameter can be a value of @ref TIM_Master_Slave_Mode */
+ This parameter can be a value of @ref TIM_Master_Slave_Mode
+ @note When the Master/slave mode is enabled, the effect of
+ an event on the trigger input (TRGI) is delayed to allow a
+ perfect synchronization between the current timer and its
+ slaves (through TRGO). It is not mandatory in case of timer
+ synchronization mode. */
} TIM_MasterConfigTypeDef;
/**
@@ -289,6 +294,26 @@ typedef enum
HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
} HAL_TIM_StateTypeDef;
+/**
+ * @brief TIM Channel States definition
+ */
+typedef enum
+{
+ HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */
+ HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */
+ HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */
+} HAL_TIM_ChannelStateTypeDef;
+
+/**
+ * @brief DMA Burst States definition
+ */
+typedef enum
+{
+ HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */
+ HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */
+ HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */
+} HAL_TIM_DMABurstStateTypeDef;
+
/**
* @brief HAL Active channel structures definition
*/
@@ -310,13 +335,16 @@ typedef struct __TIM_HandleTypeDef
typedef struct
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
{
- TIM_TypeDef *Instance; /*!< Register base address */
- TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
- HAL_TIM_ActiveChannel Channel; /*!< Active channel */
- DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
- This array is accessed by a @ref DMA_Handle_index */
- HAL_LockTypeDef Lock; /*!< Locking object */
- __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
+ TIM_TypeDef *Instance; /*!< Register base address */
+ TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
+ HAL_TIM_ActiveChannel Channel; /*!< Active channel */
+ DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
+ This array is accessed by a @ref DMA_Handle_index */
+ HAL_LockTypeDef Lock; /*!< Locking object */
+ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
+ __IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /*!< TIM channel operation state */
+ __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */
+ __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
@@ -355,34 +383,34 @@ typedef struct
*/
typedef enum
{
- HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
- ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
- ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
- ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
- ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
- ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
- ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
- ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
- ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
- ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
- ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
- ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
- ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
- ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
- ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
- ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
- ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
- ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
-
- ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
- ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
- ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
- ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
- ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
- ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
- ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
- ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
- ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
+ HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
+ , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
+ , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
+ , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
+ , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
+ , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
+ , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
+ , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
+ , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
+ , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
+ , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
+ , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
+ , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
+ , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
+ , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
+ , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
+ , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
+ , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
+
+ , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
+ , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
+ , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
+ , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
+ , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
+ , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
+ , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
+ , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
+ , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
} HAL_TIM_CallbackIDTypeDef;
/**
@@ -588,6 +616,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @}
*/
+/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
+ * @{
+ */
+#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */
+#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */
+/**
+ * @}
+ */
+
/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
* @{
*/
@@ -809,7 +846,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @{
*/
#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
-#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event
+#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event
(if none of the break inputs BRK and BRK2 is active) */
/**
* @}
@@ -917,24 +954,24 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
* @{
*/
-#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
/**
* @}
*/
@@ -979,25 +1016,45 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @retval None
*/
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
- (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
- (__HANDLE__)->Base_MspInitCallback = NULL; \
- (__HANDLE__)->Base_MspDeInitCallback = NULL; \
- (__HANDLE__)->IC_MspInitCallback = NULL; \
- (__HANDLE__)->IC_MspDeInitCallback = NULL; \
- (__HANDLE__)->OC_MspInitCallback = NULL; \
- (__HANDLE__)->OC_MspDeInitCallback = NULL; \
- (__HANDLE__)->PWM_MspInitCallback = NULL; \
- (__HANDLE__)->PWM_MspDeInitCallback = NULL; \
- (__HANDLE__)->OnePulse_MspInitCallback = NULL; \
- (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
- (__HANDLE__)->Encoder_MspInitCallback = NULL; \
- (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
- (__HANDLE__)->HallSensor_MspInitCallback = NULL; \
- (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
+ (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
+ (__HANDLE__)->Base_MspInitCallback = NULL; \
+ (__HANDLE__)->Base_MspDeInitCallback = NULL; \
+ (__HANDLE__)->IC_MspInitCallback = NULL; \
+ (__HANDLE__)->IC_MspDeInitCallback = NULL; \
+ (__HANDLE__)->OC_MspInitCallback = NULL; \
+ (__HANDLE__)->OC_MspDeInitCallback = NULL; \
+ (__HANDLE__)->PWM_MspInitCallback = NULL; \
+ (__HANDLE__)->PWM_MspDeInitCallback = NULL; \
+ (__HANDLE__)->OnePulse_MspInitCallback = NULL; \
+ (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
+ (__HANDLE__)->Encoder_MspInitCallback = NULL; \
+ (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
+ (__HANDLE__)->HallSensor_MspInitCallback = NULL; \
+ (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
} while(0)
#else
-#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
+ (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
+ } while(0)
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/**
@@ -1020,15 +1077,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @retval None
*/
#define __HAL_TIM_DISABLE(__HANDLE__) \
- do { \
- if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
- { \
- if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
- { \
- (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
- } \
- } \
- } while(0)
+ do { \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
+ { \
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
+ { \
+ (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
+ } \
+ } \
+ } while(0)
/**
* @brief Disable the TIM main Output.
@@ -1037,15 +1094,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
*/
#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
- do { \
- if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
- { \
- if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
- { \
- (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
- } \
- } \
- } while(0)
+ do { \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
+ { \
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
+ { \
+ (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
+ } \
+ } \
+ } while(0)
/**
* @brief Disable the TIM main Output.
@@ -1172,7 +1229,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @arg TIM_IT_BREAK: Break interrupt
* @retval The state of TIM_IT (SET or RESET).
*/
-#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
+ == (__INTERRUPT__)) ? SET : RESET)
/** @brief Clear the TIM interrupt pending bits.
* @param __HANDLE__ TIM handle
@@ -1220,8 +1278,7 @@ mode.
* @param __HANDLE__ TIM handle.
* @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
*/
-#define __HAL_TIM_GET_COUNTER(__HANDLE__) \
- ((__HANDLE__)->Instance->CNT)
+#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
/**
* @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
@@ -1230,18 +1287,17 @@ mode.
* @retval None
*/
#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
- do{ \
- (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
- (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
- } while(0)
+ do{ \
+ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
+ (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
+ } while(0)
/**
* @brief Get the TIM Autoreload Register value on runtime.
* @param __HANDLE__ TIM handle.
* @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
*/
-#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
- ((__HANDLE__)->Instance->ARR)
+#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
/**
* @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
@@ -1254,11 +1310,11 @@ mode.
* @retval None
*/
#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
- do{ \
- (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
- (__HANDLE__)->Instance->CR1 |= (__CKD__); \
- (__HANDLE__)->Init.ClockDivision = (__CKD__); \
- } while(0)
+ do{ \
+ (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
+ (__HANDLE__)->Instance->CR1 |= (__CKD__); \
+ (__HANDLE__)->Init.ClockDivision = (__CKD__); \
+ } while(0)
/**
* @brief Get the TIM Clock Division value on runtime.
@@ -1268,8 +1324,7 @@ mode.
* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
*/
-#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
- ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
+#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
/**
* @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
@@ -1289,10 +1344,10 @@ mode.
* @retval None
*/
#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
- do{ \
- TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
- TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
- } while(0)
+ do{ \
+ TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
+ TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
+ } while(0)
/**
* @brief Get the TIM Input Capture prescaler on runtime.
@@ -1328,10 +1383,10 @@ mode.
* @retval None
*/
#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
- ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
+ ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
/**
* @brief Get the TIM Capture Compare Register value on runtime.
@@ -1345,10 +1400,10 @@ mode.
* @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
*/
#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
- ((__HANDLE__)->Instance->CCR4))
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
+ ((__HANDLE__)->Instance->CCR4))
/**
* @brief Set the TIM Output compare preload.
@@ -1362,10 +1417,10 @@ mode.
* @retval None
*/
#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
- ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
+ ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
/**
* @brief Reset the TIM Output compare preload.
@@ -1379,10 +1434,52 @@ mode.
* @retval None
*/
#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
- ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE))
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
+ ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE))
+
+/**
+ * @brief Enable fast mode for a given channel.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @note When fast mode is enabled an active edge on the trigger input acts
+ * like a compare match on CCx output. Delay to sample the trigger
+ * input and to activate CCx output is reduced to 3 clock cycles.
+ * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
+ ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE))
+
+/**
+ * @brief Disable fast mode for a given channel.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @note When fast mode is disabled CCx output behaves normally depending
+ * on counter and CCRx values even when the trigger is ON. The minimum
+ * delay to activate CCx output when an active edge occurs on the
+ * trigger input is 5 clock cycles.
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
+ ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE))
/**
* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
@@ -1392,8 +1489,7 @@ mode.
* enabled)
* @retval None
*/
-#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
- ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
+#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
/**
* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
@@ -1406,8 +1502,7 @@ mode.
* _ Update generation through the slave mode controller
* @retval None
*/
-#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
- ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
+#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
/**
* @brief Set the TIM Capture x input polarity on runtime.
@@ -1425,10 +1520,10 @@ mode.
* @retval None
*/
#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
- do{ \
- TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
- TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
- }while(0)
+ do{ \
+ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
+ TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
+ }while(0)
/**
* @}
@@ -1504,6 +1599,9 @@ mode.
#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
((__STATE__) == TIM_OCNIDLESTATE_RESET))
+#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \
+ ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
+
#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
@@ -1655,15 +1753,15 @@ mode.
#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
-#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
+#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
@@ -1674,6 +1772,8 @@ mode.
((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
+#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
+
#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
@@ -1681,28 +1781,66 @@ mode.
#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER)
#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
- ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
+ ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
- ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
+ ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
- ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
+ ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
- ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
+ ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
+
+#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
+ (__HANDLE__)->ChannelState[3])
+
+#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
+ ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)))
+
+#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
+ (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \
+ } while(0)
+
+#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
+ (__HANDLE__)->ChannelNState[3])
+
+#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
+ ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
+
+#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
+ (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \
+ } while(0)
/**
* @}
@@ -1840,7 +1978,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel
HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
+ uint32_t *pData2, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
@@ -1864,17 +2003,25 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel);
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
+ uint32_t OutputChannel, uint32_t InputChannel);
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
+ uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
- uint32_t *BurstBuffer, uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
+ uint32_t DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
- uint32_t *BurstBuffer, uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
+ uint32_t DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
@@ -1900,7 +2047,8 @@ void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
+ pTIM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
@@ -1919,6 +2067,11 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
+
+/* Peripheral Channel state functions ************************************************/
+HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
+HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
/**
* @}
*/
@@ -1930,15 +2083,14 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
/* Private functions----------------------------------------------------------*/
/** @defgroup TIM_Private_Functions TIM Private Functions
-* @{
-*/
+ * @{
+ */
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
-void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
void TIM_DMAError(DMA_HandleTypeDef *hdma);
void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
@@ -1950,8 +2102,8 @@ void TIM_ResetCallback(TIM_HandleTypeDef *htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/**
-* @}
-*/
+ * @}
+ */
/* End of private functions --------------------------------------------------*/
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h
index 69b4ca3f59..737fdc4e5e 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h
@@ -129,66 +129,66 @@ typedef struct
* @{
*/
#if defined(SPDIFRX)
-#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
- ((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \
- ((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \
- ((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \
- (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
- ((TIM_REMAP) == TIM_TIM5_LSI) || \
- ((TIM_REMAP) == TIM_TIM5_LSE) || \
- ((TIM_REMAP) == TIM_TIM5_RTC))) || \
- (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
- ((TIM_REMAP) == TIM_TIM11_SPDIFRX) || \
- ((TIM_REMAP) == TIM_TIM11_HSE))))
+#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
+ ((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \
+ ((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \
+ ((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \
+ (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
+ ((TIM_REMAP) == TIM_TIM5_LSI) || \
+ ((TIM_REMAP) == TIM_TIM5_LSE) || \
+ ((TIM_REMAP) == TIM_TIM5_RTC))) || \
+ (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
+ ((TIM_REMAP) == TIM_TIM11_SPDIFRX) || \
+ ((TIM_REMAP) == TIM_TIM11_HSE))))
#elif defined(TIM2)
#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP)
-#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
- ((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \
- ((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \
- ((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \
- (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
- ((TIM_REMAP) == TIM_TIM5_LSI) || \
- ((TIM_REMAP) == TIM_TIM5_LSE) || \
- ((TIM_REMAP) == TIM_TIM5_RTC))) || \
- (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
- ((TIM_REMAP) == TIM_TIM11_HSE))) || \
- (((INSTANCE) == TIM1) && (((TIM_REMAP) == TIM_TIM1_TIM3_TRGO) || \
- ((TIM_REMAP) == TIM_TIM1_LPTIM))) || \
- (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_TIM3_TRGO) || \
- ((TIM_REMAP) == TIM_TIM5_LPTIM))) || \
- (((INSTANCE) == TIM9) && (((TIM_REMAP) == TIM_TIM9_TIM3_TRGO) || \
- ((TIM_REMAP) == TIM_TIM9_LPTIM))))
+#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
+ ((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \
+ ((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \
+ ((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \
+ (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
+ ((TIM_REMAP) == TIM_TIM5_LSI) || \
+ ((TIM_REMAP) == TIM_TIM5_LSE) || \
+ ((TIM_REMAP) == TIM_TIM5_RTC))) || \
+ (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
+ ((TIM_REMAP) == TIM_TIM11_HSE))) || \
+ (((INSTANCE) == TIM1) && (((TIM_REMAP) == TIM_TIM1_TIM3_TRGO) || \
+ ((TIM_REMAP) == TIM_TIM1_LPTIM))) || \
+ (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_TIM3_TRGO) || \
+ ((TIM_REMAP) == TIM_TIM5_LPTIM))) || \
+ (((INSTANCE) == TIM9) && (((TIM_REMAP) == TIM_TIM9_TIM3_TRGO) || \
+ ((TIM_REMAP) == TIM_TIM9_LPTIM))))
#elif defined(TIM8)
-#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
- ((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \
- ((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \
- ((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \
- (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
- ((TIM_REMAP) == TIM_TIM5_LSI) || \
- ((TIM_REMAP) == TIM_TIM5_LSE) || \
- ((TIM_REMAP) == TIM_TIM5_RTC))) || \
- (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
- ((TIM_REMAP) == TIM_TIM11_HSE))))
+#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
+ ((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \
+ ((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \
+ ((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \
+ (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
+ ((TIM_REMAP) == TIM_TIM5_LSI) || \
+ ((TIM_REMAP) == TIM_TIM5_LSE) || \
+ ((TIM_REMAP) == TIM_TIM5_RTC))) || \
+ (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
+ ((TIM_REMAP) == TIM_TIM11_HSE))))
#else
-#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
- ((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_ETH_PTP) || \
- ((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \
- ((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \
- (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
- ((TIM_REMAP) == TIM_TIM5_LSI) || \
- ((TIM_REMAP) == TIM_TIM5_LSE) || \
- ((TIM_REMAP) == TIM_TIM5_RTC))) || \
- (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
- ((TIM_REMAP) == TIM_TIM11_HSE))))
+#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
+ ((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_ETH_PTP) || \
+ ((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \
+ ((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \
+ (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
+ ((TIM_REMAP) == TIM_TIM5_LSI) || \
+ ((TIM_REMAP) == TIM_TIM5_LSE) || \
+ ((TIM_REMAP) == TIM_TIM5_RTC))) || \
+ (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
+ ((TIM_REMAP) == TIM_TIM11_HSE))))
#endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM5_ITR1_RMP */
#else
-#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
- ((((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
- ((TIM_REMAP) == TIM_TIM5_LSI) || \
- ((TIM_REMAP) == TIM_TIM5_LSE) || \
- ((TIM_REMAP) == TIM_TIM5_RTC))) || \
- (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
- ((TIM_REMAP) == TIM_TIM11_HSE))))
+#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
+ ((((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
+ ((TIM_REMAP) == TIM_TIM5_LSI) || \
+ ((TIM_REMAP) == TIM_TIM5_LSE) || \
+ ((TIM_REMAP) == TIM_TIM5_RTC))) || \
+ (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
+ ((TIM_REMAP) == TIM_TIM11_HSE))))
#endif /* SPDIFRX */
/**
@@ -202,9 +202,9 @@ typedef struct
*/
/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
- * @brief Timer Hall Sensor functions
- * @{
- */
+ * @brief Timer Hall Sensor functions
+ * @{
+ */
/* Timer Hall Sensor functions **********************************************/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
@@ -226,9 +226,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
*/
/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
- * @brief Timer Complementary Output Compare functions
- * @{
- */
+ * @brief Timer Complementary Output Compare functions
+ * @{
+ */
/* Timer Complementary Output Compare functions *****************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
@@ -246,9 +246,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
*/
/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
- * @brief Timer Complementary PWM functions
- * @{
- */
+ * @brief Timer Complementary PWM functions
+ * @{
+ */
/* Timer Complementary PWM functions ****************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
@@ -265,9 +265,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
*/
/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
- * @brief Timer Complementary One Pulse functions
- * @{
- */
+ * @brief Timer Complementary One Pulse functions
+ * @{
+ */
/* Timer Complementary One Pulse functions **********************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
@@ -281,15 +281,20 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
*/
/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
- * @brief Peripheral Control functions
- * @{
- */
+ * @brief Peripheral Control functions
+ * @{
+ */
/* Extended Control functions ************************************************/
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig);
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+ TIM_MasterConfigTypeDef *sMasterConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+ TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
/**
* @}
@@ -313,6 +318,7 @@ void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
*/
/* Extended Peripheral State functions ***************************************/
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN);
/**
* @}
*/
@@ -323,7 +329,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
/* End of exported functions -------------------------------------------------*/
/* Private functions----------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
+/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
* @{
*/
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h
index bd47cfbd49..24a41147bb 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h
@@ -88,7 +88,7 @@ typedef struct
* 11 : Error
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
- * 1 : Init done (Peripheral not initialized. HAL UART Init function already called)
+ * 1 : Init done (Peripheral initialized. HAL UART Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
@@ -105,7 +105,7 @@ typedef struct
* xx : Should be set to 00
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
- * 1 : Init done (Peripheral not initialized)
+ * 1 : Init done (Peripheral initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
@@ -135,6 +135,15 @@ typedef enum
Value is allowed for gState only */
} HAL_UART_StateTypeDef;
+/**
+ * @brief HAL UART Reception type definition
+ * @note HAL UART Reception type value aims to identify which type of Reception is ongoing.
+ * It is expected to admit following values :
+ * HAL_UART_RECEPTION_STANDARD = 0x00U,
+ * HAL_UART_RECEPTION_TOIDLE = 0x01U,
+ */
+typedef uint32_t HAL_UART_RxTypeTypeDef;
+
/**
* @brief UART handle Structure definition
*/
@@ -156,6 +165,8 @@ typedef struct __UART_HandleTypeDef
__IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
+ __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */
+
DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */
@@ -181,6 +192,7 @@ typedef struct __UART_HandleTypeDef
void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */
void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */
void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */
+ void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */
void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */
void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */
@@ -213,6 +225,7 @@ typedef enum
* @brief HAL UART Callback pointer definition
*/
typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */
+typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
@@ -369,6 +382,15 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @}
*/
+/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values
+ * @{
+ */
+#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */
+#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */
+/**
+ * @}
+ */
+
/**
* @}
*/
@@ -535,7 +557,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
(((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
-/** @brief Checks whether the specified UART interrupt has occurred or not.
+/** @brief Checks whether the specified UART interrupt source is enabled or not.
* @param __HANDLE__ specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
@@ -682,6 +704,9 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/**
@@ -702,6 +727,11 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData
HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
+
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+
/* Transfer Abort functions */
HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
@@ -720,6 +750,8 @@ void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size);
+
/**
* @}
*/
@@ -798,22 +830,22 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) <= 10500000U)
#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU)
-#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
+#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) ((uint32_t)((((uint64_t)(_PCLK_))*25U)/(4U*((uint64_t)(_BAUD_)))))
#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U)
-#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
+#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U) + 50U) / 100U)
/* UART BRR = mantissa + overflow + fraction
= (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
-#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \
- (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U)) + \
+#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) ((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \
+ (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U) + \
(UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0FU))
-#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_)))
+#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) ((uint32_t)((((uint64_t)(_PCLK_))*25U)/(2U*((uint64_t)(_BAUD_)))))
#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U)
-#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U + 50U) / 100U)
+#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U) + 50U) / 100U)
/* UART BRR = mantissa + overflow + fraction
= (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */
-#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \
- ((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U)) + \
+#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) ((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \
+ ((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U) + \
(UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07U))
/**
@@ -825,6 +857,9 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
* @{
*/
+HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+
/**
* @}
*/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_usart.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_usart.h
index fa2f1dd4ab..8664355c66 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_usart.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_usart.h
@@ -603,11 +603,11 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) <= 12500000U)
-#define USART_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_)))
+#define USART_DIV(_PCLK_, _BAUD_) ((uint32_t)((((uint64_t)(_PCLK_))*25U)/(2U*((uint64_t)(_BAUD_)))))
#define USART_DIVMANT(_PCLK_, _BAUD_) (USART_DIV((_PCLK_), (_BAUD_))/100U)
-#define USART_DIVFRAQ(_PCLK_, _BAUD_) (((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 8U + 50U) / 100U)
+#define USART_DIVFRAQ(_PCLK_, _BAUD_) ((((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 8U) + 50U) / 100U)
/* UART BRR = mantissa + overflow + fraction
= (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_wwdg.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_wwdg.h
index fbc628cfff..017b34df4b 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_wwdg.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_wwdg.h
@@ -22,7 +22,7 @@
#define STM32F4xx_HAL_WWDG_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -56,7 +56,7 @@ typedef struct
uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
- uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.
+ uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interrupt is enable or not.
This parameter can be a value of @ref WWDG_EWI_Mode */
} WWDG_InitTypeDef;
@@ -68,17 +68,17 @@ typedef struct
typedef struct __WWDG_HandleTypeDef
#else
typedef struct
-#endif
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
{
WWDG_TypeDef *Instance; /*!< Register base address */
WWDG_InitTypeDef Init; /*!< WWDG required parameters */
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
- void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */
+ void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */
- void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */
-#endif
+ void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
} WWDG_HandleTypeDef;
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
@@ -87,16 +87,16 @@ typedef struct
*/
typedef enum
{
- HAL_WWDG_EWI_CB_ID = 0x00u, /*!< WWDG EWI callback ID */
- HAL_WWDG_MSPINIT_CB_ID = 0x01u, /*!< WWDG MspInit callback ID */
-}HAL_WWDG_CallbackIDTypeDef;
+ HAL_WWDG_EWI_CB_ID = 0x00U, /*!< WWDG EWI callback ID */
+ HAL_WWDG_MSPINIT_CB_ID = 0x01U, /*!< WWDG MspInit callback ID */
+} HAL_WWDG_CallbackIDTypeDef;
/**
* @brief HAL WWDG Callback pointer definition
*/
-typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef * hppp); /*!< pointer to a WWDG common callback functions */
+typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer to a WWDG common callback functions */
-#endif
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -239,7 +239,8 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef * hppp); /*!< pointer t
* @arg WWDG_IT_EWI: Early Wakeup Interrupt
* @retval state of __INTERRUPT__ (TRUE or FALSE).
*/
-#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR\
+ & (__INTERRUPT__)) == (__INTERRUPT__))
/**
* @}
@@ -259,9 +260,10 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
+ pWWDG_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID);
-#endif
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
/**
* @}
@@ -294,6 +296,6 @@ void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg);
}
#endif
-#endif /* __STM32F4xx_HAL_WWDG_H */
+#endif /* STM32F4xx_HAL_WWDG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h
index 0d5ccb24d4..9348911420 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h
@@ -53,32 +53,32 @@ extern "C" {
/* Internal register offset for ADC group regular sequencer configuration */
/* (offset placed into a spare area of literal definition) */
-#define ADC_SQR1_REGOFFSET 0x00000000U
-#define ADC_SQR2_REGOFFSET 0x00000100U
-#define ADC_SQR3_REGOFFSET 0x00000200U
-#define ADC_SQR4_REGOFFSET 0x00000300U
+#define ADC_SQR1_REGOFFSET 0x00000000UL
+#define ADC_SQR2_REGOFFSET 0x00000100UL
+#define ADC_SQR3_REGOFFSET 0x00000200UL
+#define ADC_SQR4_REGOFFSET 0x00000300UL
#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
/* Definition of ADC group regular sequencer bits information to be inserted */
/* into ADC group regular sequencer ranks literals definition. */
-#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */
-#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */
-#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */
-#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */
-#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */
-#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */
-#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
-#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
-#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
-#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */
-#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */
-#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */
-#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */
-#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */
-#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */
-#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */
+#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */
+#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */
+#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */
+#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */
+#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */
+#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */
+#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
+#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
+#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
+#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */
+#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */
+#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */
+#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */
+#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */
+#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */
+#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */
/* Internal mask for ADC group injected sequencer: */
/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
@@ -88,17 +88,17 @@ extern "C" {
/* Internal register offset for ADC group injected data register */
/* (offset placed into a spare area of literal definition) */
-#define ADC_JDR1_REGOFFSET 0x00000000U
-#define ADC_JDR2_REGOFFSET 0x00000100U
-#define ADC_JDR3_REGOFFSET 0x00000200U
-#define ADC_JDR4_REGOFFSET 0x00000300U
+#define ADC_JDR1_REGOFFSET 0x00000000UL
+#define ADC_JDR2_REGOFFSET 0x00000100UL
+#define ADC_JDR3_REGOFFSET 0x00000200UL
+#define ADC_JDR4_REGOFFSET 0x00000300UL
/* Internal register offset for ADC group injected offset configuration */
/* (offset placed into a spare area of literal definition) */
-#define ADC_JOFR1_REGOFFSET 0x00000000U
-#define ADC_JOFR2_REGOFFSET 0x00001000U
-#define ADC_JOFR3_REGOFFSET 0x00002000U
-#define ADC_JOFR4_REGOFFSET 0x00003000U
+#define ADC_JOFR1_REGOFFSET 0x00000000UL
+#define ADC_JOFR2_REGOFFSET 0x00001000UL
+#define ADC_JOFR3_REGOFFSET 0x00002000UL
+#define ADC_JOFR4_REGOFFSET 0x00003000UL
#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
#define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)
@@ -113,22 +113,22 @@ extern "C" {
/* Mask containing trigger source masks for each of possible */
/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
-#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTSEL) >> (4U * 0U)) | \
- ((ADC_CR2_EXTSEL) >> (4U * 1U)) | \
- ((ADC_CR2_EXTSEL) >> (4U * 2U)) | \
- ((ADC_CR2_EXTSEL) >> (4U * 3U)))
+#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTSEL) >> (4UL * 0UL)) | \
+ ((ADC_CR2_EXTSEL) >> (4UL * 1UL)) | \
+ ((ADC_CR2_EXTSEL) >> (4UL * 2UL)) | \
+ ((ADC_CR2_EXTSEL) >> (4UL * 3UL)))
/* Mask containing trigger edge masks for each of possible */
/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
-#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN) >> (4U * 0U)) | \
- ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) | \
- ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) | \
- ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U)))
+#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN) >> (4UL * 0UL)) | \
+ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 1UL)) | \
+ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 2UL)) | \
+ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 3UL)))
/* Definition of ADC group regular trigger bits information. */
-#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTSEL) */
-#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (28U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTEN) */
+#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (24UL) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTSEL) */
+#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (28UL) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTEN) */
@@ -141,22 +141,22 @@ extern "C" {
/* Mask containing trigger source masks for each of possible */
/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
-#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_JEXTSEL) >> (4U * 0U)) | \
- ((ADC_CR2_JEXTSEL) >> (4U * 1U)) | \
- ((ADC_CR2_JEXTSEL) >> (4U * 2U)) | \
- ((ADC_CR2_JEXTSEL) >> (4U * 3U)))
+#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_JEXTSEL) >> (4UL * 0UL)) | \
+ ((ADC_CR2_JEXTSEL) >> (4UL * 1UL)) | \
+ ((ADC_CR2_JEXTSEL) >> (4UL * 2UL)) | \
+ ((ADC_CR2_JEXTSEL) >> (4UL * 3UL)))
/* Mask containing trigger edge masks for each of possible */
/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
-#define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN) >> (4U * 0U)) | \
- ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) | \
- ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) | \
- ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U)))
+#define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN) >> (4UL * 0UL)) | \
+ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 1UL)) | \
+ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 2UL)) | \
+ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 3UL)))
/* Definition of ADC group injected trigger bits information. */
-#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */
-#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */
+#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (16UL) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */
+#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (20UL) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */
/* Internal mask for ADC channel: */
/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
@@ -166,29 +166,29 @@ extern "C" {
/* - channel sampling time defined by SMPRx register offset */
/* and SMPx bits positions into SMPRx register */
#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH)
-#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
+#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0UL)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
/* Channel differentiation between external and internal channels */
-#define ADC_CHANNEL_ID_INTERNAL_CH 0x80000000U /* Marker of internal channel */
-#define ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000U /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
+#define ADC_CHANNEL_ID_INTERNAL_CH 0x80000000UL /* Marker of internal channel */
+#define ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000UL /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
#define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */
#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT)
/* Internal register offset for ADC channel sampling time configuration */
/* (offset placed into a spare area of literal definition) */
-#define ADC_SMPR1_REGOFFSET 0x00000000U
-#define ADC_SMPR2_REGOFFSET 0x02000000U
+#define ADC_SMPR1_REGOFFSET 0x00000000UL
+#define ADC_SMPR2_REGOFFSET 0x02000000UL
#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
-#define ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000U
-#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
+#define ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000UL
+#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
/* Definition of channels ID number information to be inserted into */
/* channels literals definition. */
-#define ADC_CHANNEL_0_NUMBER 0x00000000U
+#define ADC_CHANNEL_0_NUMBER 0x00000000UL
#define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0)
#define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 )
#define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
@@ -210,25 +210,25 @@ extern "C" {
/* Definition of channels sampling time information to be inserted into */
/* channels literals definition. */
-#define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */
-#define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */
-#define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */
-#define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */
-#define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */
-#define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */
-#define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */
-#define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */
-#define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */
-#define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */
-#define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */
-#define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */
-#define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */
-#define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */
-#define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */
-#define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */
-#define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */
-#define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */
-#define ADC_CHANNEL_18_SMP (ADC_SMPR1_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP18) */
+#define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */
+#define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */
+#define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */
+#define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */
+#define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */
+#define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */
+#define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */
+#define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */
+#define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */
+#define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */
+#define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */
+#define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */
+#define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */
+#define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */
+#define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */
+#define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */
+#define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */
+#define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */
+#define ADC_CHANNEL_18_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP18) */
/* Internal mask for ADC analog watchdog: */
/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
@@ -238,7 +238,7 @@ extern "C" {
/* selection of ADC group (ADC groups regular and-or injected). */
/* Internal register offset for ADC analog watchdog channel configuration */
-#define ADC_AWD_CR1_REGOFFSET 0x00000000U
+#define ADC_AWD_CR1_REGOFFSET 0x00000000UL
#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
@@ -246,24 +246,24 @@ extern "C" {
#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
/* Internal register offset for ADC analog watchdog threshold configuration */
-#define ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000U
-#define ADC_AWD_TR1_LOW_REGOFFSET 0x00000001U
+#define ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000UL
+#define ADC_AWD_TR1_LOW_REGOFFSET 0x00000001UL
#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)
/* ADC registers bits positions */
-#define ADC_CR1_RES_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */
-#define ADC_TR_HT_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
+#define ADC_CR1_RES_BITOFFSET_POS (24UL) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */
+#define ADC_TR_HT_BITOFFSET_POS (16UL) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
/* ADC internal channels related definitions */
/* Internal voltage reference VrefInt */
#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF7A2AU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
-#define VREFINT_CAL_VREF ( 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
+#define VREFINT_CAL_VREF ( 3300UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
/* Temperature sensor */
#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF7A2CU)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF7A2EU)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F4, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
-#define TEMPSENSOR_CAL_VREFANALOG ( 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
+#define TEMPSENSOR_CAL_VREFANALOG ( 3300UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
/**
* @}
@@ -295,7 +295,7 @@ extern "C" {
* @retval Pointer to register address
*/
#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
- ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
+ ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
/**
* @}
@@ -406,7 +406,7 @@ typedef struct
{
uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
- @note On this STM32 serie, setting of external trigger edge is performed
+ @note On this STM32 series, setting of external trigger edge is performed
using function @ref LL_ADC_REG_StartConversionExtTrig().
This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
@@ -460,7 +460,7 @@ typedef struct
{
uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
- @note On this STM32 serie, setting of external trigger edge is performed
+ @note On this STM32 series, setting of external trigger edge is performed
using function @ref LL_ADC_INJ_StartConversionExtTrig().
This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
@@ -504,7 +504,7 @@ typedef struct
#define LL_ADC_FLAG_EOCS ADC_SR_EOC /*!< ADC flag ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
#define LL_ADC_FLAG_OVR ADC_SR_OVR /*!< ADC flag ADC group regular overrun */
#define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conversion start */
-#define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
+#define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
#define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 */
#if defined(ADC_MULTIMODE_SUPPORT)
#define LL_ADC_FLAG_EOCS_MST ADC_CSR_EOC1 /*!< ADC flag ADC multimode master group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
@@ -513,9 +513,9 @@ typedef struct
#define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR1 /*!< ADC flag ADC multimode master group regular overrun */
#define LL_ADC_FLAG_OVR_SLV1 ADC_CSR_OVR2 /*!< ADC flag ADC multimode slave 1 group regular overrun */
#define LL_ADC_FLAG_OVR_SLV2 ADC_CSR_OVR3 /*!< ADC flag ADC multimode slave 2 group regular overrun */
-#define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOC1 /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
-#define LL_ADC_FLAG_JEOS_SLV1 ADC_CSR_JEOC2 /*!< ADC flag ADC multimode slave 1 group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
-#define LL_ADC_FLAG_JEOS_SLV2 ADC_CSR_JEOC3 /*!< ADC flag ADC multimode slave 2 group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
+#define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOC1 /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
+#define LL_ADC_FLAG_JEOS_SLV1 ADC_CSR_JEOC2 /*!< ADC flag ADC multimode slave 1 group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
+#define LL_ADC_FLAG_JEOS_SLV2 ADC_CSR_JEOC3 /*!< ADC flag ADC multimode slave 2 group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
#define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1 /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
#define LL_ADC_FLAG_AWD1_SLV1 ADC_CSR_AWD2 /*!< ADC flag ADC multimode slave 1 analog watchdog 1 */
#define LL_ADC_FLAG_AWD1_SLV2 ADC_CSR_AWD3 /*!< ADC flag ADC multimode slave 2 analog watchdog 1 */
@@ -530,7 +530,7 @@ typedef struct
*/
#define LL_ADC_IT_EOCS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
#define LL_ADC_IT_OVR ADC_CR1_OVRIE /*!< ADC interruption ADC group regular overrun */
-#define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
+#define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
#define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watchdog 1 */
/**
* @}
@@ -542,9 +542,9 @@ typedef struct
/* List of ADC registers intended to be used (most commonly) with */
/* DMA transfer. */
/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
-#define LL_ADC_DMA_REG_REGULAR_DATA 0x00000000U /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
+#define LL_ADC_DMA_REG_REGULAR_DATA 0x00000000UL /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
#if defined(ADC_MULTIMODE_SUPPORT)
-#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI 0x00000001U /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
+#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI 0x00000001UL /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
#endif
/**
* @}
@@ -553,7 +553,7 @@ typedef struct
/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
* @{
*/
-#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000U /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000UL /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 ( ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
#define LL_ADC_CLOCK_SYNC_PCLK_DIV6 (ADC_CCR_ADCPRE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 6 */
#define LL_ADC_CLOCK_SYNC_PCLK_DIV8 (ADC_CCR_ADCPRE_1 | ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 8 */
@@ -569,7 +569,7 @@ typedef struct
/* If they are not listed below, they do not require any specific */
/* path enable. In this case, Access to measurement path is done */
/* only by selecting the corresponding ADC internal channel. */
-#define LL_ADC_PATH_INTERNAL_NONE 0x00000000U /*!< ADC measurement pathes all disabled */
+#define LL_ADC_PATH_INTERNAL_NONE 0x00000000UL /*!< ADC measurement paths all disabled */
#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */
#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */
#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATE) /*!< ADC measurement path to internal channel Vbat */
@@ -580,7 +580,7 @@ typedef struct
/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
* @{
*/
-#define LL_ADC_RESOLUTION_12B 0x00000000U /*!< ADC resolution 12 bits */
+#define LL_ADC_RESOLUTION_12B 0x00000000UL /*!< ADC resolution 12 bits */
#define LL_ADC_RESOLUTION_10B ( ADC_CR1_RES_0) /*!< ADC resolution 10 bits */
#define LL_ADC_RESOLUTION_8B (ADC_CR1_RES_1 ) /*!< ADC resolution 8 bits */
#define LL_ADC_RESOLUTION_6B (ADC_CR1_RES_1 | ADC_CR1_RES_0) /*!< ADC resolution 6 bits */
@@ -591,8 +591,8 @@ typedef struct
/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
* @{
*/
-#define LL_ADC_DATA_ALIGN_RIGHT 0x00000000U /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
-#define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
+#define LL_ADC_DATA_ALIGN_RIGHT 0x00000000UL /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
+#define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
/**
* @}
*/
@@ -600,7 +600,7 @@ typedef struct
/** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection
* @{
*/
-#define LL_ADC_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/
+#define LL_ADC_SEQ_SCAN_DISABLE 0x00000000UL /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/
#define LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */
/**
* @}
@@ -609,9 +609,9 @@ typedef struct
/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
* @{
*/
-#define LL_ADC_GROUP_REGULAR 0x00000001U /*!< ADC group regular (available on all STM32 devices) */
-#define LL_ADC_GROUP_INJECTED 0x00000002U /*!< ADC group injected (not available on all STM32 devices)*/
-#define LL_ADC_GROUP_REGULAR_INJECTED 0x00000003U /*!< ADC both groups regular and injected */
+#define LL_ADC_GROUP_REGULAR 0x00000001UL /*!< ADC group regular (available on all STM32 devices) */
+#define LL_ADC_GROUP_INJECTED 0x00000002UL /*!< ADC group injected (not available on all STM32 devices)*/
+#define LL_ADC_GROUP_REGULAR_INJECTED 0x00000003UL /*!< ADC both groups regular and injected */
/**
* @}
*/
@@ -653,7 +653,7 @@ typedef struct
/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
* @{
*/
-#define LL_ADC_REG_TRIG_SOFTWARE 0x00000000U /*!< ADC group regular conversion trigger internal: SW start. */
+#define LL_ADC_REG_TRIG_SOFTWARE 0x00000000UL /*!< ADC group regular conversion trigger internal: SW start. */
#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
@@ -687,7 +687,7 @@ typedef struct
/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
* @{
*/
-#define LL_ADC_REG_CONV_SINGLE 0x00000000U /*!< ADC conversions are performed in single mode: one conversion per trigger */
+#define LL_ADC_REG_CONV_SINGLE 0x00000000UL /*!< ADC conversions are performed in single mode: one conversion per trigger */
#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
/**
* @}
@@ -696,7 +696,7 @@ typedef struct
/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
* @{
*/
-#define LL_ADC_REG_DMA_TRANSFER_NONE 0x00000000U /*!< ADC conversions are not transferred by DMA */
+#define LL_ADC_REG_DMA_TRANSFER_NONE 0x00000000UL /*!< ADC conversions are not transferred by DMA */
#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DDS | ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
/**
@@ -706,7 +706,7 @@ typedef struct
/** @defgroup ADC_LL_EC_REG_FLAG_EOC_SELECTION ADC group regular - Flag EOC selection (unitary or sequence conversions)
* @{
*/
-#define LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV 0x00000000U /*!< ADC flag EOC (end of unitary conversion) selected */
+#define LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV 0x00000000UL /*!< ADC flag EOC (end of unitary conversion) selected */
#define LL_ADC_REG_FLAG_EOC_UNITARY_CONV (ADC_CR2_EOCS) /*!< ADC flag EOS (end of sequence conversions) selected */
/**
* @}
@@ -715,7 +715,7 @@ typedef struct
/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
* @{
*/
-#define LL_ADC_REG_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+#define LL_ADC_REG_SEQ_SCAN_DISABLE 0x00000000UL /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
@@ -738,7 +738,7 @@ typedef struct
/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
* @{
*/
-#define LL_ADC_REG_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group regular sequencer discontinuous mode disable */
+#define LL_ADC_REG_SEQ_DISCONT_DISABLE 0x00000000UL /*!< ADC group regular sequencer discontinuous mode disable */
#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
@@ -777,7 +777,7 @@ typedef struct
/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
* @{
*/
-#define LL_ADC_INJ_TRIG_SOFTWARE 0x00000000U /*!< ADC group injected conversion trigger internal: SW start. */
+#define LL_ADC_INJ_TRIG_SOFTWARE 0x00000000UL /*!< ADC group injected conversion trigger internal: SW start. */
#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
@@ -811,7 +811,7 @@ typedef struct
/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
* @{
*/
-#define LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000U /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
+#define LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000UL /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
/**
* @}
@@ -821,7 +821,7 @@ typedef struct
/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
* @{
*/
-#define LL_ADC_INJ_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+#define LL_ADC_INJ_SEQ_SCAN_DISABLE 0x00000000UL /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
@@ -832,7 +832,7 @@ typedef struct
/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
* @{
*/
-#define LL_ADC_INJ_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group injected sequencer discontinuous mode disable */
+#define LL_ADC_INJ_SEQ_DISCONT_DISABLE 0x00000000UL /*!< ADC group injected sequencer discontinuous mode disable */
#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
/**
* @}
@@ -841,10 +841,10 @@ typedef struct
/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
* @{
*/
-#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001U) /*!< ADC group injected sequencer rank 1 */
-#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002U) /*!< ADC group injected sequencer rank 2 */
-#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003U) /*!< ADC group injected sequencer rank 3 */
-#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004U) /*!< ADC group injected sequencer rank 4 */
+#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001UL) /*!< ADC group injected sequencer rank 1 */
+#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002UL) /*!< ADC group injected sequencer rank 2 */
+#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003UL) /*!< ADC group injected sequencer rank 3 */
+#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004UL) /*!< ADC group injected sequencer rank 4 */
/**
* @}
*/
@@ -852,7 +852,7 @@ typedef struct
/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
* @{
*/
-#define LL_ADC_SAMPLINGTIME_3CYCLES 0x00000000U /*!< Sampling time 3 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_3CYCLES 0x00000000UL /*!< Sampling time 3 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_15CYCLES (ADC_SMPR1_SMP10_0) /*!< Sampling time 15 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_28CYCLES (ADC_SMPR1_SMP10_1) /*!< Sampling time 28 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_56CYCLES (ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0) /*!< Sampling time 56 ADC clock cycles */
@@ -875,7 +875,7 @@ typedef struct
/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
* @{
*/
-#define LL_ADC_AWD_DISABLE 0x00000000U /*!< ADC analog watchdog monitoring disabled */
+#define LL_ADC_AWD_DISABLE 0x00000000UL /*!< ADC analog watchdog monitoring disabled */
#define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
#define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
@@ -969,7 +969,7 @@ typedef struct
/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
* @{
*/
-#define LL_ADC_MULTI_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */
+#define LL_ADC_MULTI_INDEPENDENT 0x00000000UL /*!< ADC dual mode disabled (ADC independent mode) */
#define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 ) /*!< ADC dual mode enabled: group regular simultaneous */
#define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
#define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected simultaneous */
@@ -992,13 +992,13 @@ typedef struct
/** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
* @{
*/
-#define LL_ADC_MULTI_REG_DMA_EACH_ADC 0x00000000U /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
+#define LL_ADC_MULTI_REG_DMA_EACH_ADC 0x00000000UL /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
#define LL_ADC_MULTI_REG_DMA_LIMIT_1 ( ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */
#define LL_ADC_MULTI_REG_DMA_LIMIT_2 ( ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words one by one, ADC2&1 then ADC1&3 then ADC3&2. */
-#define LL_ADC_MULTI_REG_DMA_LIMIT_3 ( ADC_CCR_DMA_0 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */
+#define LL_ADC_MULTI_REG_DMA_LIMIT_3 ( ADC_CCR_DMA_1 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */
#define LL_ADC_MULTI_REG_DMA_UNLMT_1 (ADC_CCR_DDS | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */
#define LL_ADC_MULTI_REG_DMA_UNLMT_2 (ADC_CCR_DDS | ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words by pairs, ADC2&1 then ADC1&3 then ADC3&2. */
-#define LL_ADC_MULTI_REG_DMA_UNLMT_3 (ADC_CCR_DDS | ADC_CCR_DMA_0 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */
+#define LL_ADC_MULTI_REG_DMA_UNLMT_3 (ADC_CCR_DDS | ADC_CCR_DMA_1 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */
/**
* @}
*/
@@ -1006,7 +1006,7 @@ typedef struct
/** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
* @{
*/
-#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES 0x00000000U /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles*/
+#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES 0x00000000UL /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles*/
#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
@@ -1053,7 +1053,7 @@ typedef struct
/* configuration (system clock versus ADC clock), */
/* and therefore must be defined in user application. */
/* Indications for estimation of ADC timeout delays, for this */
-/* STM32 serie: */
+/* STM32 series: */
/* - ADC enable time: maximum delay is 2us */
/* (refer to device datasheet, parameter "tSTAB") */
/* - ADC conversion time: duration depending on ADC clock and ADC */
@@ -1064,13 +1064,13 @@ typedef struct
/* Delay set to maximum value (refer to device datasheet, */
/* parameter "tSTART"). */
/* Unit: us */
-#define LL_ADC_DELAY_VREFINT_STAB_US ( 10U) /*!< Delay for internal voltage reference stabilization time */
+#define LL_ADC_DELAY_VREFINT_STAB_US ( 10UL) /*!< Delay for internal voltage reference stabilization time */
/* Delay for temperature sensor stabilization time. */
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tSTART"). */
/* Unit: us */
-#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 10U) /*!< Delay for internal voltage reference stabilization time */
+#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 10UL) /*!< Delay for internal voltage reference stabilization time */
/**
* @}
@@ -1192,15 +1192,15 @@ typedef struct
* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
*/
#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
- (((__DECIMAL_NB__) <= 9U) \
+ (((__DECIMAL_NB__) <= 9UL) \
? ( \
((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
- (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
+ (ADC_SMPR2_REGOFFSET | (((uint32_t) (3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
) \
: \
( \
((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
- (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
+ (ADC_SMPR1_REGOFFSET | (((uint32_t) (3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
) \
)
@@ -1251,7 +1251,7 @@ typedef struct
* Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
*/
#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
- (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
+ (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
/**
* @brief Helper macro to convert a channel defined from parameter
@@ -1493,7 +1493,7 @@ typedef struct
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
- ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U )))
+ ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL )))
/**
* @brief Helper macro to get the value of ADC analog watchdog threshold high
@@ -1515,7 +1515,7 @@ typedef struct
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
- ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U )))
+ ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL )))
#if defined(ADC_MULTIMODE_SUPPORT)
/**
@@ -1601,7 +1601,7 @@ typedef struct
* @retval ADC conversion data equivalent voltage value (unit: mVolt)
*/
#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
- (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)))
+ (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL)))
/**
* @brief Helper macro to convert the ADC conversion data from
@@ -1623,8 +1623,8 @@ typedef struct
*/
#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \
(((__DATA__) \
- << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U))) \
- >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)) \
+ << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL))) \
+ >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL)) \
)
/**
@@ -1650,6 +1650,42 @@ typedef struct
/ __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
)
+/**
+ * @brief Helper macro to calculate analog reference voltage (Vref+)
+ * (unit: mVolt) from ADC conversion data of internal voltage
+ * reference VrefInt.
+ * @note Computation is using VrefInt calibration value
+ * stored in system memory for each device during production.
+ * @note This voltage depends on user board environment: voltage level
+ * connected to pin Vref+.
+ * On devices with small package, the pin Vref+ is not present
+ * and internally bonded to pin Vdda.
+ * @note On this STM32 series, calibration data of internal voltage reference
+ * VrefInt corresponds to a resolution of 12 bits,
+ * this is the recommended ADC resolution to convert voltage of
+ * internal voltage reference VrefInt.
+ * Otherwise, this macro performs the processing to scale
+ * ADC conversion data to 12 bits.
+ * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
+ * of internal voltage reference VrefInt (unit: digital value).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @retval Analog reference voltage (unit: mV)
+ */
+#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+ (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
+ / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
+ (__ADC_RESOLUTION__), \
+ LL_ADC_RESOLUTION_12B))
+
+/* Note: On device STM32F4x9, calibration parameter TS_CAL2 is not available. */
+/* Therefore, helper macro __LL_ADC_CALC_TEMPERATURE() is not available.*/
+/* Use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). */
+#if !defined(STM32F469) && !defined(STM32F479xx) && !defined(STM32F429xx) && !defined(STM32F439xx)
/**
* @brief Helper macro to calculate the temperature (unit: degree Celsius)
* from ADC conversion data of internal temperature sensor.
@@ -1677,7 +1713,7 @@ typedef struct
* @note Analog reference voltage (Vref+) must be either known from
* user board environment or can be calculated using ADC measurement
* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
- * @note On this STM32 serie, calibration data of temperature sensor
+ * @note On this STM32 series, calibration data of temperature sensor
* corresponds to a resolution of 12 bits,
* this is the recommended ADC resolution to convert voltage of
* temperature sensor.
@@ -1708,6 +1744,7 @@ typedef struct
) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
) + TEMPSENSOR_CAL1_TEMP \
)
+#endif
/**
* @brief Helper macro to calculate the temperature (unit: degree Celsius)
@@ -1825,7 +1862,7 @@ typedef struct
#if defined(ADC_MULTIMODE_SUPPORT)
__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
{
- register uint32_t data_reg_addr = 0U;
+ uint32_t data_reg_addr = 0UL;
if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
{
@@ -2080,7 +2117,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx)
* @brief Set ADC group regular conversion trigger source:
* internal (SW start) or from external IP (timer event,
* external interrupt line).
- * @note On this STM32 serie, setting of external trigger edge is performed
+ * @note On this STM32 series, setting of external trigger edge is performed
* using function @ref LL_ADC_REG_StartConversionExtTrig().
* @note Availability of parameters of trigger sources from timer
* depends on timers availability on the selected device.
@@ -2109,7 +2146,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx)
*/
__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
{
-/* Note: On this STM32 serie, ADC group regular external trigger edge */
+/* Note: On this STM32 series, ADC group regular external trigger edge */
/* is used to perform a ADC conversion start. */
/* This function does not set external trigger edge. */
/* This feature is set using function */
@@ -2153,11 +2190,11 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
{
- register uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL | ADC_CR2_EXTEN);
+ uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL | ADC_CR2_EXTEN);
/* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
/* corresponding to ADC_CR2_EXTEN {0; 1; 2; 3}. */
- register uint32_t ShiftExten = ((TriggerSource & ADC_CR2_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));
+ uint32_t ShiftExten = ((TriggerSource & ADC_CR2_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
/* Set bitfield corresponding to ADC_CR2_EXTEN and ADC_CR2_EXTSEL */
/* to match with triggers literals definition. */
@@ -2186,7 +2223,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
/**
* @brief Get ADC group regular conversion trigger polarity.
* @note Applicable only for trigger source set to external trigger.
- * @note On this STM32 serie, setting of external trigger edge is performed
+ * @note On this STM32 series, setting of external trigger edge is performed
* using function @ref LL_ADC_REG_StartConversionExtTrig().
* @rmtoll CR2 EXTEN LL_ADC_REG_GetTriggerEdge
* @param ADCx ADC instance
@@ -2228,7 +2265,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
* highest channel number).
* Sequencer ranks are selected using
* function "LL_ADC_REG_SetSequencerChannels()".
- * @note On this STM32 serie, group regular sequencer configuration
+ * @note On this STM32 series, group regular sequencer configuration
* is conditioned to ADC instance sequencer mode.
* If ADC instance sequencer mode is disabled, sequencers of
* all groups (group regular, group injected) can be configured
@@ -2289,7 +2326,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t S
* highest channel number).
* Sequencer ranks are selected using
* function "LL_ADC_REG_SetSequencerChannels()".
- * @note On this STM32 serie, group regular sequencer configuration
+ * @note On this STM32 series, group regular sequencer configuration
* is conditioned to ADC instance sequencer mode.
* If ADC instance sequencer mode is disabled, sequencers of
* all groups (group regular, group injected) can be configured
@@ -2379,13 +2416,13 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
* @note This function performs configuration of:
* - Channels ordering into each rank of scan sequence:
* whatever channel can be placed into whatever rank.
- * @note On this STM32 serie, ADC group regular sequencer is
+ * @note On this STM32 series, ADC group regular sequencer is
* fully configurable: sequencer length and each rank
* affectation to a channel are configurable.
* Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
* @note Depending on devices and packages, some channels may not be available.
* Refer to device datasheet for channels availability.
- * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * @note On this STM32 series, to measure internal channels (VrefInt,
* TempSensor, ...), measurement paths to internal channels must be
* enabled separately.
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
@@ -2457,7 +2494,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra
/* in register and register position depending on parameter "Rank". */
/* Parameters "Rank" and "Channel" are used with masks because containing */
/* other bits reserved for other purpose. */
- register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
MODIFY_REG(*preg,
ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
@@ -2467,7 +2504,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra
/**
* @brief Get ADC group regular sequence: channel on the selected
* scan sequence rank.
- * @note On this STM32 serie, ADC group regular sequencer is
+ * @note On this STM32 series, ADC group regular sequencer is
* fully configurable: sequencer length and each rank
* affectation to a channel are configurable.
* Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
@@ -2550,7 +2587,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
return (uint32_t) (READ_BIT(*preg,
ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
@@ -2715,7 +2752,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef *ADCx)
* @brief Set ADC group injected conversion trigger source:
* internal (SW start) or from external IP (timer event,
* external interrupt line).
- * @note On this STM32 serie, setting of external trigger edge is performed
+ * @note On this STM32 series, setting of external trigger edge is performed
* using function @ref LL_ADC_INJ_StartConversionExtTrig().
* @note Availability of parameters of trigger sources from timer
* depends on timers availability on the selected device.
@@ -2744,7 +2781,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef *ADCx)
*/
__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
{
-/* Note: On this STM32 serie, ADC group injected external trigger edge */
+/* Note: On this STM32 series, ADC group injected external trigger edge */
/* is used to perform a ADC conversion start. */
/* This function does not set external trigger edge. */
/* This feature is set using function */
@@ -2788,11 +2825,11 @@ __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
{
- register uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL | ADC_CR2_JEXTEN);
+ uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL | ADC_CR2_JEXTEN);
/* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
/* corresponding to ADC_CR2_JEXTEN {0; 1; 2; 3}. */
- register uint32_t ShiftExten = ((TriggerSource & ADC_CR2_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U));
+ uint32_t ShiftExten = ((TriggerSource & ADC_CR2_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
/* Set bitfield corresponding to ADC_CR2_JEXTEN and ADC_CR2_JEXTSEL */
/* to match with triggers literals definition. */
@@ -2839,7 +2876,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
* - Sequence length: Number of ranks in the scan sequence.
* - Sequence direction: Unless specified in parameters, sequencer
* scan direction is forward (from rank 1 to rank n).
- * @note On this STM32 serie, group injected sequencer configuration
+ * @note On this STM32 series, group injected sequencer configuration
* is conditioned to ADC instance sequencer mode.
* If ADC instance sequencer mode is disabled, sequencers of
* all groups (group regular, group injected) can be configured
@@ -2867,7 +2904,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t S
* - Sequence length: Number of ranks in the scan sequence.
* - Sequence direction: Unless specified in parameters, sequencer
* scan direction is forward (from rank 1 to rank n).
- * @note On this STM32 serie, group injected sequencer configuration
+ * @note On this STM32 series, group injected sequencer configuration
* is conditioned to ADC instance sequencer mode.
* If ADC instance sequencer mode is disabled, sequencers of
* all groups (group regular, group injected) can be configured
@@ -2926,7 +2963,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
* sequence rank.
* @note Depending on devices and packages, some channels may not be available.
* Refer to device datasheet for channels availability.
- * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * @note On this STM32 series, to measure internal channels (VrefInt,
* TempSensor, ...), measurement paths to internal channels must be
* enabled separately.
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
@@ -2974,11 +3011,11 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra
/* in register depending on parameter "Rank". */
/* Parameters "Rank" and "Channel" are used with masks because containing */
/* other bits reserved for other purpose. */
- register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U;
+ uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1UL;
MODIFY_REG(ADCx->JSQR,
- ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))),
- (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))));
+ ADC_CHANNEL_ID_NUMBER_MASK << (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1))),
+ (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1))));
}
/**
@@ -3039,11 +3076,11 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U;
+ uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1UL;
return (uint32_t)(READ_BIT(ADCx->JSQR,
- ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))))
- >> (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))
+ ADC_CHANNEL_ID_NUMBER_MASK << (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1))))
+ >> (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1)))
);
}
@@ -3119,7 +3156,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
*/
__STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
{
- register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
MODIFY_REG(*preg,
ADC_JOFR1_JOFFSET1,
@@ -3146,7 +3183,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
return (uint32_t)(READ_BIT(*preg,
ADC_JOFR1_JOFFSET1)
@@ -3175,7 +3212,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)
* TS_temp, ...).
* @note Conversion time is the addition of sampling time and processing time.
* Refer to reference manual for ADC processing time of
- * this STM32 serie.
+ * this STM32 series.
* @note In case of ADC conversion of internal channel (VrefInt,
* temperature sensor, ...), a sampling time minimum value
* is required.
@@ -3243,7 +3280,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C
/* in register and register position depending on parameter "Channel". */
/* Parameter "Channel" is used with masks because containing */
/* other bits reserved for other purpose. */
- register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
MODIFY_REG(*preg,
ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
@@ -3257,7 +3294,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C
* of channel mapped on ADC group regular or injected.
* @note Conversion time is the addition of sampling time and processing time.
* Refer to reference manual for ADC processing time of
- * this STM32 serie.
+ * this STM32 series.
* @rmtoll SMPR1 SMP18 LL_ADC_GetChannelSamplingTime\n
* SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n
* SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n
@@ -3316,7 +3353,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C
*/
__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
{
- register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
return (uint32_t)(READ_BIT(*preg,
ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
@@ -3341,7 +3378,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32
* @note In case of need to define a single channel to monitor
* with analog watchdog from sequencer channel definition,
* use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
- * @note On this STM32 serie, there is only 1 kind of analog watchdog
+ * @note On this STM32 series, there is only 1 kind of analog watchdog
* instance:
* - AWD standard (instance AWD1):
* - channels monitored: can monitor 1 channel or all channels.
@@ -3450,7 +3487,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t
* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
* Applicable only when the analog watchdog is set to monitor
* one channel.
- * @note On this STM32 serie, there is only 1 kind of analog watchdog
+ * @note On this STM32 series, there is only 1 kind of analog watchdog
* instance:
* - AWD standard (instance AWD1):
* - channels monitored: can monitor 1 channel or all channels.
@@ -3535,7 +3572,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
* @note In case of ADC resolution different of 12 bits,
* analog watchdog thresholds data require a specific shift.
* Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
- * @note On this STM32 serie, there is only 1 kind of analog watchdog
+ * @note On this STM32 series, there is only 1 kind of analog watchdog
* instance:
* - AWD standard (instance AWD1):
* - channels monitored: can monitor 1 channel or all channels.
@@ -3553,7 +3590,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
*/
__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
{
- register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
MODIFY_REG(*preg,
ADC_HTR_HT,
@@ -3576,7 +3613,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW
*/
__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
{
- register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));
}
@@ -3820,7 +3857,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADC
/**
* @brief Enable the selected ADC instance.
- * @note On this STM32 serie, after ADC enable, a delay for
+ * @note On this STM32 series, after ADC enable, a delay for
* ADC internal analog stabilization is required before performing a
* ADC conversion start.
* Refer to device datasheet, parameter tSTAB.
@@ -3865,7 +3902,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
/**
* @brief Start ADC group regular conversion.
- * @note On this STM32 serie, this function is relevant only for
+ * @note On this STM32 series, this function is relevant only for
* internal trigger (SW start), not for external trigger:
* - If ADC trigger has been set to software start, ADC conversion
* starts immediately.
@@ -3888,7 +3925,7 @@ __STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx)
* @brief Start ADC group regular conversion from external trigger.
* @note ADC conversion will start at next trigger event (on the selected
* trigger edge) following the ADC start conversion command.
- * @note On this STM32 serie, this function is relevant for
+ * @note On this STM32 series, this function is relevant for
* ADC conversion start from external trigger.
* If internal trigger (SW start) is needed, perform ADC conversion
* start using function @ref LL_ADC_REG_StartConversionSWStart().
@@ -3910,7 +3947,7 @@ __STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32
* @note No more ADC conversion will start at next trigger event
* following the ADC stop conversion command.
* If a conversion is on-going, it will be completed.
- * @note On this STM32 serie, there is no specific command
+ * @note On this STM32 series, there is no specific command
* to stop a conversion on-going or to stop ADC converting
* in continuous mode. These actions can be performed
* using function @ref LL_ADC_Disable().
@@ -4038,7 +4075,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef
/**
* @brief Start ADC group injected conversion.
- * @note On this STM32 serie, this function is relevant only for
+ * @note On this STM32 series, this function is relevant only for
* internal trigger (SW start), not for external trigger:
* - If ADC trigger has been set to software start, ADC conversion
* starts immediately.
@@ -4061,7 +4098,7 @@ __STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx)
* @brief Start ADC group injected conversion from external trigger.
* @note ADC conversion will start at next trigger event (on the selected
* trigger edge) following the ADC start conversion command.
- * @note On this STM32 serie, this function is relevant for
+ * @note On this STM32 series, this function is relevant for
* ADC conversion start from external trigger.
* If internal trigger (SW start) is needed, perform ADC conversion
* start using function @ref LL_ADC_INJ_StartConversionSWStart().
@@ -4083,7 +4120,7 @@ __STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32
* @note No more ADC conversion will start at next trigger event
* following the ADC stop conversion command.
* If a conversion is on-going, it will be completed.
- * @note On this STM32 serie, there is no specific command
+ * @note On this STM32 series, there is no specific command
* to stop a conversion on-going or to stop ADC converting
* in continuous mode. These actions can be performed
* using function @ref LL_ADC_Disable().
@@ -4115,7 +4152,7 @@ __STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
return (uint32_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
@@ -4142,7 +4179,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint
*/
__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
return (uint16_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
@@ -4169,7 +4206,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint
*/
__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
return (uint16_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
@@ -4196,7 +4233,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint
*/
__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
return (uint8_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
@@ -4223,7 +4260,7 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32
*/
__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
return (uint8_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
@@ -4273,7 +4310,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
{
- /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* Note: on this STM32 series, there is no flag ADC group injected */
/* end of unitary conversion. */
/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
/* in other STM32 families). */
@@ -4326,7 +4363,7 @@ __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
*/
__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
{
- /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* Note: on this STM32 series, there is no flag ADC group injected */
/* end of unitary conversion. */
/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
/* in other STM32 families). */
@@ -4438,7 +4475,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_OVR(ADC_Common_TypeDef *ADCxy_
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
{
- /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* Note: on this STM32 series, there is no flag ADC group injected */
/* end of unitary conversion. */
/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
/* in other STM32 families). */
@@ -4454,7 +4491,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
{
- /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* Note: on this STM32 series, there is no flag ADC group injected */
/* end of unitary conversion. */
/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
/* in other STM32 families). */
@@ -4470,7 +4507,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_JEOS(ADC_Common_TypeDef *ADCxy
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
{
- /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* Note: on this STM32 series, there is no flag ADC group injected */
/* end of unitary conversion. */
/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
/* in other STM32 families). */
@@ -4558,7 +4595,7 @@ __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
*/
__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
{
- /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* Note: on this STM32 series, there is no flag ADC group injected */
/* end of unitary conversion. */
/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
/* in other STM32 families). */
@@ -4611,7 +4648,7 @@ __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
*/
__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
{
- /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* Note: on this STM32 series, there is no flag ADC group injected */
/* end of unitary conversion. */
/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
/* in other STM32 families). */
@@ -4667,7 +4704,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
*/
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
{
- /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* Note: on this STM32 series, there is no flag ADC group injected */
/* end of unitary conversion. */
/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
/* in other STM32 families). */
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dac.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dac.h
index 55eb09c12d..42031307fa 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dac.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dac.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * © Copyright (c) 2017 STMicroelectronics.
+ * © Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -18,8 +18,8 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_LL_DAC_H
-#define __STM32F4xx_LL_DAC_H
+#ifndef STM32F4xx_LL_DAC_H
+#define STM32F4xx_LL_DAC_H
#ifdef __cplusplus
extern "C" {
@@ -48,52 +48,86 @@ extern "C" {
/* Internal masks for DAC channels definition */
/* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
-/* - channel bits position into register CR */
+/* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */
/* - channel bits position into register SWTRIG */
/* - channel register offset of data holding register DHRx */
/* - channel register offset of data output register DORx */
-#define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
-#define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
+#define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers
+ CR, MCR, CCR, SHHR, SHRR of channel 1 */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers
+ CR, MCR, CCR, SHHR, SHRR of channel 2 */
#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
+#else
+#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET)
+#endif /* DAC_CHANNEL2_SUPPORT */
-#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
+#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
#if defined(DAC_CHANNEL2_SUPPORT)
-#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
+#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
#else
#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1)
#endif /* DAC_CHANNEL2_SUPPORT */
-#define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
-#define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
-#define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
+#define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
+#define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus
+ DHR12Rx channel 1 (shifted left of 20 bits) */
+#define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus
+ DHR12Rx channel 1 (shifted left of 24 bits) */
#if defined(DAC_CHANNEL2_SUPPORT)
-#define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
-#define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
-#define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
+#define DAC_REG_DHR12R2_REGOFFSET 0x00030000UL /* Register offset of DHR12Rx channel 2 versus
+ DHR12Rx channel 1 (shifted left of 16 bits) */
+#define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus
+ DHR12Rx channel 1 (shifted left of 20 bits) */
+#define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus
+ DHR12Rx channel 1 (shifted left of 24 bits) */
#endif /* DAC_CHANNEL2_SUPPORT */
-#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
-#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
-#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
-#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
+#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000UL
+#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
+#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
+#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\
+ | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
-#define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
+#define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
#if defined(DAC_CHANNEL2_SUPPORT)
-#define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
+#define DAC_REG_DOR2_REGOFFSET 0x10000000UL /* Register offset of DORx channel 1 versus
+ DORx channel 2 (shifted left of 28 bits) */
#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
-#else
-#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET)
#endif /* DAC_CHANNEL2_SUPPORT */
+
+#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
+ DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
+#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted
+ to position 0 */
+#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted
+ to position 0 */
+
+#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 16UL /* Position of bits register offset of DHR12Rx
+ channel 1 or 2 versus DHR12Rx channel 1
+ (shifted left of 16 bits) */
+#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx
+ channel 1 or 2 versus DHR12Rx channel 1
+ (shifted left of 20 bits) */
+#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx
+ channel 1 or 2 versus DHR12Rx channel 1
+ (shifted left of 24 bits) */
+#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DORx
+ channel 1 or 2 versus DORx channel 1
+ (shifted left of 28 bits) */
+
/* DAC registers bits positions */
#if defined(DAC_CHANNEL2_SUPPORT)
-#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
-#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
-#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
-#endif /* DAC_CHANNEL2_SUPPORT */
+#endif
+#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
+#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
+#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
/* Miscellaneous data */
-#define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
+#define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12
+ bits (voltage range determined by analog voltage
+ references Vref+ and Vref-, refer to reference manual) */
/**
* @}
@@ -105,27 +139,16 @@ extern "C" {
* @{
*/
-/**
- * @brief Driver macro reserved for internal use: isolate bits with the
- * selected mask and shift them to the register LSB
- * (shift mask on register position bit 0).
- * @param __BITS__ Bits in register 32 bits
- * @param __MASK__ Mask in register 32 bits
- * @retval Bits in register 32 bits
-*/
-#define __DAC_MASK_SHIFT(__BITS__, __MASK__) \
- (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
-
/**
* @brief Driver macro reserved for internal use: set a pointer to
* a register from a register basis from which an offset
* is applied.
* @param __REG__ Register basis from which the offset is applied.
- * @param __REG_OFFFSET__ Offset to be applied (unit number of registers).
+ * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
* @retval Pointer to register address
-*/
+ */
#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
- ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
+ ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
/**
* @}
@@ -143,28 +166,38 @@ extern "C" {
*/
typedef struct
{
- uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
+ uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel:
+ internal (SW start) or from external peripheral
+ (timer event, external interrupt line).
This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
-
- This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_DAC_SetTriggerSource(). */
uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
-
- This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_DAC_SetWaveAutoGeneration(). */
uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
- If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
- If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
- @note If waveform automatic generation mode is disabled, this parameter is discarded.
-
- This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
+ If waveform automatic generation mode is set to noise, this parameter
+ can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
+ If waveform automatic generation mode is set to triangle,
+ this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
+ @note If waveform automatic generation mode is disabled,
+ this parameter is discarded.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_DAC_SetWaveNoiseLFSR(),
+ @ref LL_DAC_SetWaveTriangleAmplitude()
+ depending on the wave automatic generation selected. */
uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
-
- This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
+ This feature can be modified afterwards using unitary
+ function @ref LL_DAC_SetOutputBuffer(). */
} LL_DAC_InitTypeDef;
/**
@@ -183,7 +216,6 @@ typedef struct
*/
/* DAC channel 1 flags */
#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
-
#if defined(DAC_CHANNEL2_SUPPORT)
/* DAC channel 2 flags */
#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
@@ -219,13 +251,13 @@ typedef struct
* @{
*/
#define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
-#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
-#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
+#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM4 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000UL /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM5 TRGO. */
+#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */
/**
* @}
*/
@@ -233,9 +265,9 @@ typedef struct
/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
* @{
*/
-#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */
-#define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
-#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
+#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */
+#define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
+#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
/**
* @}
*/
@@ -243,7 +275,7 @@ typedef struct
/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
* @{
*/
-#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
@@ -262,7 +294,7 @@ typedef struct
/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
* @{
*/
-#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
@@ -281,18 +313,17 @@ typedef struct
/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
* @{
*/
-#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
+#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
/**
* @}
*/
-
/** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
* @{
*/
-#define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */
-#define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */
+#define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */
+#define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */
/**
* @}
*/
@@ -303,15 +334,15 @@ typedef struct
/* List of DAC registers intended to be used (most commonly) with */
/* DMA transfer. */
/* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
-#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */
-#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */
-#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK /*!< DAC channel data holding register 8 bits right aligned */
+#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
+#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
+#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */
/**
* @}
*/
/** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
- * @note Only DAC IP HW delays are defined in DAC LL driver driver,
+ * @note Only DAC peripheral HW delays are defined in DAC LL driver driver,
* not timeout values.
* For details on delays values, refer to descriptions in source code
* above each literal definition.
@@ -330,7 +361,7 @@ typedef struct
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tWAKEUP"). */
/* Unit: us */
-#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
+#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
/* Delay for DAC channel voltage settling time. */
/* Note: DAC channel startup time depends on board application environment: */
@@ -343,7 +374,8 @@ typedef struct
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tSETTLING"). */
/* Unit: us */
-#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */
+#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12UL /*!< Delay for DAC channel voltage settling time */
+
/**
* @}
*/
@@ -397,7 +429,7 @@ typedef struct
* @param __CHANNEL__ This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval 1...2 (value "2" depending on DAC channel 2 availability)
@@ -417,39 +449,39 @@ typedef struct
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
*/
#if defined(DAC_CHANNEL2_SUPPORT)
#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
- (((__DECIMAL_NB__) == 1U) \
+ (((__DECIMAL_NB__) == 1UL) \
? ( \
LL_DAC_CHANNEL_1 \
) \
: \
- (((__DECIMAL_NB__) == 2U) \
+ (((__DECIMAL_NB__) == 2UL) \
? ( \
LL_DAC_CHANNEL_2 \
) \
: \
( \
- 0 \
+ 0UL \
) \
) \
)
#else
#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
- (((__DECIMAL_NB__) == 1U) \
+ (((__DECIMAL_NB__) == 1UL) \
? ( \
LL_DAC_CHANNEL_1 \
) \
: \
( \
- 0 \
+ 0UL \
) \
)
-#endif /* DAC_CHANNEL2_SUPPORT */
+#endif /* DAC_CHANNEL2_SUPPORT */
/**
* @brief Helper macro to define the DAC conversion data full-scale digital
@@ -463,7 +495,7 @@ typedef struct
* @retval ADC conversion data equivalent voltage value (unit: mVolt)
*/
#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
- ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
+ ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
/**
* @brief Helper macro to calculate the DAC conversion data (unit: digital
@@ -474,8 +506,8 @@ typedef struct
* @ref LL_DAC_ConvertData12RightAligned().
* @note Analog reference voltage (Vref+) must be either known from
* user board environment or can be calculated using ADC measurement
- * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
- * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV)
+ * and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
* @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
* (unit: mVolt).
* @param __DAC_RESOLUTION__ This parameter can be one of the following values:
@@ -486,9 +518,9 @@ typedef struct
#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
__DAC_VOLTAGE__,\
__DAC_RESOLUTION__) \
- ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
- / (__VREFANALOG_VOLTAGE__) \
- )
+((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
+ / (__VREFANALOG_VOLTAGE__) \
+)
/**
* @}
@@ -503,10 +535,6 @@ typedef struct
/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
* @{
*/
-/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
- * @{
- */
-
/**
* @brief Set the conversion trigger source for the selected DAC channel.
* @note For conversion trigger source to be effective, DAC trigger
@@ -521,7 +549,7 @@ typedef struct
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param TriggerSource This parameter can be one of the following values:
@@ -554,7 +582,7 @@ __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Cha
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval Returned value can be one of the following values:
@@ -583,7 +611,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param WaveAutoGeneration This parameter can be one of the following values:
@@ -608,7 +636,7 @@ __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DA
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval Returned value can be one of the following values:
@@ -637,7 +665,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param NoiseLFSRMask This parameter can be one of the following values:
@@ -663,7 +691,7 @@ __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Cha
}
/**
- * @brief Set the noise waveform generation for the selected DAC channel:
+ * @brief Get the noise waveform generation for the selected DAC channel:
* Noise mode and parameters LFSR (linear feedback shift register).
* @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
* CR MAMP2 LL_DAC_GetWaveNoiseLFSR
@@ -671,7 +699,7 @@ __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Cha
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval Returned value can be one of the following values:
@@ -709,7 +737,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param TriangleAmplitude This parameter can be one of the following values:
@@ -727,7 +755,8 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
* @retval None
*/
-__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
+__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
+ uint32_t TriangleAmplitude)
{
MODIFY_REG(DACx->CR,
DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
@@ -735,7 +764,7 @@ __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t
}
/**
- * @brief Set the triangle waveform generation for the selected DAC channel:
+ * @brief Get the triangle waveform generation for the selected DAC channel:
* triangle mode and amplitude.
* @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
* CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
@@ -743,7 +772,7 @@ __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval Returned value can be one of the following values:
@@ -775,7 +804,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param OutputBuffer This parameter can be one of the following values:
@@ -798,7 +827,7 @@ __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Chan
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval Returned value can be one of the following values:
@@ -830,7 +859,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval None
@@ -851,7 +880,7 @@ __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval None
@@ -871,16 +900,16 @@ __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channe
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
- return (READ_BIT(DACx->CR,
- DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
- == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
+ return ((READ_BIT(DACx->CR,
+ DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
}
/**
@@ -896,7 +925,8 @@ __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_
* LL_DMA_ConfigAddresses(DMA1,
* LL_DMA_CHANNEL_1,
* (uint32_t)&< array or variable >,
- * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
+ * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1,
+ * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
* LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
* @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
* DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
@@ -908,7 +938,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param Register This parameter can be one of the following values:
@@ -921,7 +951,8 @@ __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_C
{
/* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
/* DAC channel selected. */
- return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register))));
+ return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
+ & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
}
/**
* @}
@@ -942,7 +973,7 @@ __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_C
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval None
@@ -961,7 +992,7 @@ __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval None
@@ -981,16 +1012,16 @@ __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
- return (READ_BIT(DACx->CR,
- DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
- == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
+ return ((READ_BIT(DACx->CR,
+ DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
}
/**
@@ -1009,7 +1040,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channe
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval None
@@ -1028,7 +1059,7 @@ __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channe
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval None
@@ -1048,22 +1079,24 @@ __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Chann
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
- return (READ_BIT(DACx->CR,
- DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
- == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
+ return ((READ_BIT(DACx->CR,
+ DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
}
/**
* @brief Trig DAC conversion by software for the selected DAC channel.
* @note Preliminarily, DAC trigger must be set to software trigger
- * using function @ref LL_DAC_SetTriggerSource()
+ * using function
+ * @ref LL_DAC_Init()
+ * @ref LL_DAC_SetTriggerSource()
* with parameter "LL_DAC_TRIGGER_SOFTWARE".
* and DAC trigger must be enabled using
* function @ref LL_DAC_EnableTrigger().
@@ -1077,7 +1110,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC
* @param DAC_Channel This parameter can a combination of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval None
@@ -1098,7 +1131,7 @@ __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Cha
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
@@ -1106,11 +1139,10 @@ __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Cha
*/
__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
{
- register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK));
-
- MODIFY_REG(*preg,
- DAC_DHR12R1_DACC1DHR,
- Data);
+ __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
+ & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
+
+ MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
}
/**
@@ -1123,7 +1155,7 @@ __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
@@ -1131,11 +1163,10 @@ __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_
*/
__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
{
- register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK));
-
- MODIFY_REG(*preg,
- DAC_DHR12L1_DACC1DHR,
- Data);
+ __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
+ & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
+
+ MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
}
/**
@@ -1148,7 +1179,7 @@ __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param Data Value between Min_Data=0x00 and Max_Data=0xFF
@@ -1156,11 +1187,10 @@ __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t
*/
__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
{
- register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK));
-
- MODIFY_REG(*preg,
- DAC_DHR8R1_DACC1DHR,
- Data);
+ __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
+ & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
+
+ MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
}
#if defined(DAC_CHANNEL2_SUPPORT)
@@ -1175,7 +1205,8 @@ __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t
* @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval None
*/
-__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
+__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
+ uint32_t DataChannel2)
{
MODIFY_REG(DACx->DHR12RD,
(DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
@@ -1193,7 +1224,8 @@ __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uin
* @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval None
*/
-__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
+__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
+ uint32_t DataChannel2)
{
/* Note: Data of DAC channel 2 shift value subtracted of 4 because */
/* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
@@ -1214,14 +1246,15 @@ __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint
* @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
* @retval None
*/
-__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
+__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
+ uint32_t DataChannel2)
{
MODIFY_REG(DACx->DHR8RD,
(DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
}
-
#endif /* DAC_CHANNEL2_SUPPORT */
+
/**
* @brief Retrieve output data currently generated for the selected DAC channel.
* @note Whatever alignment and resolution settings
@@ -1234,15 +1267,16 @@ __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
- register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK));
-
+ __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
+ & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
+
return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
}
@@ -1253,6 +1287,8 @@ __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t D
/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
* @{
*/
+
+
/**
* @brief Get DAC underrun flag for DAC channel 1
* @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
@@ -1261,7 +1297,7 @@ __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t D
*/
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
{
- return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
+ return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
}
#if defined(DAC_CHANNEL2_SUPPORT)
@@ -1273,7 +1309,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
*/
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
{
- return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
+ return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
}
#endif /* DAC_CHANNEL2_SUPPORT */
@@ -1365,7 +1401,7 @@ __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
*/
__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
{
- return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
+ return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
}
#if defined(DAC_CHANNEL2_SUPPORT)
@@ -1377,7 +1413,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
*/
__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
{
- return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
+ return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
}
#endif /* DAC_CHANNEL2_SUPPORT */
@@ -1390,9 +1426,9 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
* @{
*/
-ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
-ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
-void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
+ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx);
+ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct);
+void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
/**
* @}
@@ -1417,6 +1453,6 @@ void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
}
#endif
-#endif /* __STM32F4xx_LL_DAC_H */
+#endif /* STM32F4xx_LL_DAC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h
index a1560d6477..63264e614d 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h
@@ -285,14 +285,24 @@ typedef struct
/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
* @{
*/
-#define LL_DMA_CHANNEL_0 0x00000000U /* Select Channel0 of DMA Instance */
-#define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 /* Select Channel1 of DMA Instance */
-#define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 /* Select Channel2 of DMA Instance */
-#define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1) /* Select Channel3 of DMA Instance */
-#define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 /* Select Channel4 of DMA Instance */
-#define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel5 of DMA Instance */
-#define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel6 of DMA Instance */
-#define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel7 of DMA Instance */
+#define LL_DMA_CHANNEL_0 0x00000000U /* Select Channel0 of DMA Instance */
+#define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 /* Select Channel1 of DMA Instance */
+#define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 /* Select Channel2 of DMA Instance */
+#define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1) /* Select Channel3 of DMA Instance */
+#define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 /* Select Channel4 of DMA Instance */
+#define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel5 of DMA Instance */
+#define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel6 of DMA Instance */
+#define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel7 of DMA Instance */
+#if defined (DMA_SxCR_CHSEL_3)
+#define LL_DMA_CHANNEL_8 DMA_SxCR_CHSEL_3 /* Select Channel8 of DMA Instance */
+#define LL_DMA_CHANNEL_9 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_0) /* Select Channel9 of DMA Instance */
+#define LL_DMA_CHANNEL_10 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1) /* Select Channel10 of DMA Instance */
+#define LL_DMA_CHANNEL_11 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel11 of DMA Instance */
+#define LL_DMA_CHANNEL_12 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2) /* Select Channel12 of DMA Instance */
+#define LL_DMA_CHANNEL_13 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel13 of DMA Instance */
+#define LL_DMA_CHANNEL_14 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel14 of DMA Instance */
+#define LL_DMA_CHANNEL_15 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel15 of DMA Instance */
+#endif /* DMA_SxCR_CHSEL_3 */
/**
* @}
*/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma2d.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma2d.h
index 6864b54c47..a783d058af 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma2d.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma2d.h
@@ -66,73 +66,103 @@ typedef struct
uint32_t Mode; /*!< Specifies the DMA2D transfer mode.
- This parameter can be one value of @ref DMA2D_LL_EC_MODE.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetMode().*/
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetMode(). */
uint32_t ColorMode; /*!< Specifies the color format of the output image.
- This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */
+ This parameter can be modified afterwards using,
+ unitary function @ref LL_DMA2D_SetOutputColorMode(). */
uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
-
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
-
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+ This parameter can be modified afterwards
+ using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
uint32_t OutputRed; /*!< Specifies the Red value of the output image.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
-
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+ This parameter can be modified afterwards
+ using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
- This parameter is not considered if RGB888 or RGB565 color mode is selected.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ This parameter can be modified afterwards using,
+ unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
uint32_t OutputMemoryAddress; /*!< Specifies the memory address.
- - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
+ - This parameter must be a number between:
+ Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */
uint32_t LineOffset; /*!< Specifies the output line offset value.
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffset(). */
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetLineOffset(). */
uint32_t NbrOfLines; /*!< Specifies the number of lines of the area to be transferred.
- - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
+ - This parameter must be a number between:
+ Min_Data = 0x0000 and Max_Data = 0xFFFF.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfLines(). */
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetNbrOfLines(). */
- uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transfered.
+ uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transferred.
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */
+ This parameter can be modified afterwards using,
+ unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */
} LL_DMA2D_InitTypeDef;
@@ -143,7 +173,8 @@ typedef struct
typedef struct
{
uint32_t MemoryAddress; /*!< Specifies the foreground or background memory address.
- - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
+ - This parameter must be a number between:
+ Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
This parameter can be modified afterwards using unitary functions
- @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer,
@@ -213,7 +244,8 @@ typedef struct
- @ref LL_DMA2D_BGND_SetRedColor() for background layer. */
uint32_t CLUTMemoryAddress; /*!< Specifies the foreground or background CLUT memory address.
- - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
+ - This parameter must be a number between:
+ Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
This parameter can be modified afterwards using unitary functions
- @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer,
@@ -231,45 +263,68 @@ typedef struct
uint32_t ColorMode; /*!< Specifies the color format of the output image.
- This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */
+ This parameter can be modified afterwards using
+ unitary function @ref LL_DMA2D_SetOutputColorMode(). */
uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
-
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+ This parameter can be modified afterwards using,
+ unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
-
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between
+ Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
uint32_t OutputRed; /*!< Specifies the Red value of the output image.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
-
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
- This parameter is not considered if RGB888 or RGB565 color mode is selected.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
} LL_DMA2D_ColorTypeDef;
@@ -357,9 +412,11 @@ typedef struct
* @{
*/
#define LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U /*!< No modification of the alpha channel value */
-#define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by programmed alpha value */
-#define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by programmed alpha value
- with original alpha channel value */
+#define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by
+ programmed alpha value */
+#define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by
+ programmed alpha value with,
+ original alpha channel value */
/**
* @}
*/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmpi2c.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmpi2c.h
new file mode 100644
index 0000000000..1f2e707b1a
--- /dev/null
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmpi2c.h
@@ -0,0 +1,2193 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_fmpi2c.h
+ * @author MCD Application Team
+ * @brief Header file of FMPI2C LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F4xx_LL_FMPI2C_H
+#define STM32F4xx_LL_FMPI2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(FMPI2C_CR1_PE)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined (FMPI2C1)
+
+/** @defgroup FMPI2C_LL FMPI2C
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FMPI2C_LL_Private_Constants FMPI2C Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup FMPI2C_LL_Private_Macros FMPI2C Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup FMPI2C_LL_ES_INIT FMPI2C Exported Init structure
+ * @{
+ */
+typedef struct
+{
+ uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
+ This parameter can be a value of @ref FMPI2C_LL_EC_PERIPHERAL_MODE.
+
+ This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetMode(). */
+
+ uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
+ This parameter must be set by referring to the STM32CubeMX Tool and
+ the helper macro @ref __LL_FMPI2C_CONVERT_TIMINGS().
+
+ This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetTiming(). */
+
+ uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
+ This parameter can be a value of @ref FMPI2C_LL_EC_ANALOGFILTER_SELECTION.
+
+ This feature can be modified afterwards using unitary functions @ref LL_FMPI2C_EnableAnalogFilter() or LL_FMPI2C_DisableAnalogFilter(). */
+
+ uint32_t DigitalFilter; /*!< Configures the digital noise filter.
+ This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F.
+
+ This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetDigitalFilter(). */
+
+ uint32_t OwnAddress1; /*!< Specifies the device own address 1.
+ This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF.
+
+ This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetOwnAddress1(). */
+
+ uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
+ This parameter can be a value of @ref FMPI2C_LL_EC_I2C_ACKNOWLEDGE.
+
+ This feature can be modified afterwards using unitary function @ref LL_FMPI2C_AcknowledgeNextData(). */
+
+ uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
+ This parameter can be a value of @ref FMPI2C_LL_EC_OWNADDRESS1.
+
+ This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetOwnAddress1(). */
+} LL_FMPI2C_InitTypeDef;
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FMPI2C_LL_Exported_Constants FMPI2C Exported Constants
+ * @{
+ */
+
+/** @defgroup FMPI2C_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_FMPI2C_WriteReg function
+ * @{
+ */
+#define LL_FMPI2C_ICR_ADDRCF FMPI2C_ICR_ADDRCF /*!< Address Matched flag */
+#define LL_FMPI2C_ICR_NACKCF FMPI2C_ICR_NACKCF /*!< Not Acknowledge flag */
+#define LL_FMPI2C_ICR_STOPCF FMPI2C_ICR_STOPCF /*!< Stop detection flag */
+#define LL_FMPI2C_ICR_BERRCF FMPI2C_ICR_BERRCF /*!< Bus error flag */
+#define LL_FMPI2C_ICR_ARLOCF FMPI2C_ICR_ARLOCF /*!< Arbitration Lost flag */
+#define LL_FMPI2C_ICR_OVRCF FMPI2C_ICR_OVRCF /*!< Overrun/Underrun flag */
+#define LL_FMPI2C_ICR_PECCF FMPI2C_ICR_PECCF /*!< PEC error flag */
+#define LL_FMPI2C_ICR_TIMOUTCF FMPI2C_ICR_TIMOUTCF /*!< Timeout detection flag */
+#define LL_FMPI2C_ICR_ALERTCF FMPI2C_ICR_ALERTCF /*!< Alert flag */
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_FMPI2C_ReadReg function
+ * @{
+ */
+#define LL_FMPI2C_ISR_TXE FMPI2C_ISR_TXE /*!< Transmit data register empty */
+#define LL_FMPI2C_ISR_TXIS FMPI2C_ISR_TXIS /*!< Transmit interrupt status */
+#define LL_FMPI2C_ISR_RXNE FMPI2C_ISR_RXNE /*!< Receive data register not empty */
+#define LL_FMPI2C_ISR_ADDR FMPI2C_ISR_ADDR /*!< Address matched (slave mode) */
+#define LL_FMPI2C_ISR_NACKF FMPI2C_ISR_NACKF /*!< Not Acknowledge received flag */
+#define LL_FMPI2C_ISR_STOPF FMPI2C_ISR_STOPF /*!< Stop detection flag */
+#define LL_FMPI2C_ISR_TC FMPI2C_ISR_TC /*!< Transfer Complete (master mode) */
+#define LL_FMPI2C_ISR_TCR FMPI2C_ISR_TCR /*!< Transfer Complete Reload */
+#define LL_FMPI2C_ISR_BERR FMPI2C_ISR_BERR /*!< Bus error */
+#define LL_FMPI2C_ISR_ARLO FMPI2C_ISR_ARLO /*!< Arbitration lost */
+#define LL_FMPI2C_ISR_OVR FMPI2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */
+#define LL_FMPI2C_ISR_PECERR FMPI2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */
+#define LL_FMPI2C_ISR_TIMEOUT FMPI2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */
+#define LL_FMPI2C_ISR_ALERT FMPI2C_ISR_ALERT /*!< SMBus alert (SMBus mode) */
+#define LL_FMPI2C_ISR_BUSY FMPI2C_ISR_BUSY /*!< Bus busy */
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_FMPI2C_ReadReg and LL_FMPI2C_WriteReg functions
+ * @{
+ */
+#define LL_FMPI2C_CR1_TXIE FMPI2C_CR1_TXIE /*!< TX Interrupt enable */
+#define LL_FMPI2C_CR1_RXIE FMPI2C_CR1_RXIE /*!< RX Interrupt enable */
+#define LL_FMPI2C_CR1_ADDRIE FMPI2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */
+#define LL_FMPI2C_CR1_NACKIE FMPI2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */
+#define LL_FMPI2C_CR1_STOPIE FMPI2C_CR1_STOPIE /*!< STOP detection Interrupt enable */
+#define LL_FMPI2C_CR1_TCIE FMPI2C_CR1_TCIE /*!< Transfer Complete interrupt enable */
+#define LL_FMPI2C_CR1_ERRIE FMPI2C_CR1_ERRIE /*!< Error interrupts enable */
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
+ * @{
+ */
+#define LL_FMPI2C_MODE_I2C 0x00000000U /*!< FMPI2C Master or Slave mode */
+#define LL_FMPI2C_MODE_SMBUS_HOST FMPI2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */
+#define LL_FMPI2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode (Default address not acknowledge) */
+#define LL_FMPI2C_MODE_SMBUS_DEVICE_ARP FMPI2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
+ * @{
+ */
+#define LL_FMPI2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */
+#define LL_FMPI2C_ANALOGFILTER_DISABLE FMPI2C_CR1_ANFOFF /*!< Analog filter is disabled. */
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
+ * @{
+ */
+#define LL_FMPI2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */
+#define LL_FMPI2C_ADDRESSING_MODE_10BIT FMPI2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_OWNADDRESS1 Own Address 1 Length
+ * @{
+ */
+#define LL_FMPI2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */
+#define LL_FMPI2C_OWNADDRESS1_10BIT FMPI2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
+ * @{
+ */
+#define LL_FMPI2C_OWNADDRESS2_NOMASK FMPI2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */
+#define LL_FMPI2C_OWNADDRESS2_MASK01 FMPI2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */
+#define LL_FMPI2C_OWNADDRESS2_MASK02 FMPI2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */
+#define LL_FMPI2C_OWNADDRESS2_MASK03 FMPI2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */
+#define LL_FMPI2C_OWNADDRESS2_MASK04 FMPI2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */
+#define LL_FMPI2C_OWNADDRESS2_MASK05 FMPI2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */
+#define LL_FMPI2C_OWNADDRESS2_MASK06 FMPI2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */
+#define LL_FMPI2C_OWNADDRESS2_MASK07 FMPI2C_OAR2_OA2MASK07 /*!< No comparison is done. All Address2 are acknowledged.*/
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
+ * @{
+ */
+#define LL_FMPI2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */
+#define LL_FMPI2C_NACK FMPI2C_CR2_NACK /*!< NACK is sent after current received byte.*/
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_ADDRSLAVE Slave Address Length
+ * @{
+ */
+#define LL_FMPI2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */
+#define LL_FMPI2C_ADDRSLAVE_10BIT FMPI2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_REQUEST Transfer Request Direction
+ * @{
+ */
+#define LL_FMPI2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */
+#define LL_FMPI2C_REQUEST_READ FMPI2C_CR2_RD_WRN /*!< Master request a read transfer. */
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_MODE Transfer End Mode
+ * @{
+ */
+#define LL_FMPI2C_MODE_RELOAD FMPI2C_CR2_RELOAD /*!< Enable FMPI2C Reload mode. */
+#define LL_FMPI2C_MODE_AUTOEND FMPI2C_CR2_AUTOEND /*!< Enable FMPI2C Automatic end mode with no HW PEC comparison. */
+#define LL_FMPI2C_MODE_SOFTEND 0x00000000U /*!< Enable FMPI2C Software end mode with no HW PEC comparison. */
+#define LL_FMPI2C_MODE_SMBUS_RELOAD LL_FMPI2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
+#define LL_FMPI2C_MODE_SMBUS_AUTOEND_NO_PEC LL_FMPI2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
+#define LL_FMPI2C_MODE_SMBUS_SOFTEND_NO_PEC LL_FMPI2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode with HW PEC comparison. */
+#define LL_FMPI2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_FMPI2C_MODE_AUTOEND | FMPI2C_CR2_PECBYTE) /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
+#define LL_FMPI2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_FMPI2C_MODE_SOFTEND | FMPI2C_CR2_PECBYTE) /*!< Enable SMBUS Software end mode with HW PEC comparison. */
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_GENERATE Start And Stop Generation
+ * @{
+ */
+#define LL_FMPI2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */
+#define LL_FMPI2C_GENERATE_STOP (uint32_t)(0x80000000U | FMPI2C_CR2_STOP) /*!< Generate Stop condition (Size should be set to 0). */
+#define LL_FMPI2C_GENERATE_START_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN) /*!< Generate Start for read request. */
+#define LL_FMPI2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) /*!< Generate Start for write request. */
+#define LL_FMPI2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */
+#define LL_FMPI2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) /*!< Generate Restart for write request, slave 7Bit address. */
+#define LL_FMPI2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN | FMPI2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */
+#define LL_FMPI2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) /*!< Generate Restart for write request, slave 10Bit address.*/
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_DIRECTION Read Write Direction
+ * @{
+ */
+#define LL_FMPI2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, slave enters receiver mode. */
+#define LL_FMPI2C_DIRECTION_READ FMPI2C_ISR_DIR /*!< Read transfer request by master, slave enters transmitter mode.*/
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_DMA_REG_DATA DMA Register Data
+ * @{
+ */
+#define LL_FMPI2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
+#define LL_FMPI2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
+ * @{
+ */
+#define LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect SCL low level timeout. */
+#define LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH FMPI2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
+ * @{
+ */
+#define LL_FMPI2C_SMBUS_TIMEOUTA FMPI2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */
+#define LL_FMPI2C_SMBUS_TIMEOUTB FMPI2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) enable bit */
+#define LL_FMPI2C_SMBUS_ALL_TIMEOUT (uint32_t)(FMPI2C_TIMEOUTR_TIMOUTEN | FMPI2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB (extended clock) enable bits */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FMPI2C_LL_Exported_Macros FMPI2C Exported Macros
+ * @{
+ */
+
+/** @defgroup FMPI2C_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in FMPI2C register
+ * @param __INSTANCE__ FMPI2C Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_FMPI2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in FMPI2C register
+ * @param __INSTANCE__ FMPI2C Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_FMPI2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
+ * @{
+ */
+/**
+ * @brief Configure the SDA setup, hold time and the SCL high, low period.
+ * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
+ * @param __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc)
+ * @param __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc)
+ * @param __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc)
+ * @param __CLOCK_LOW_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc)
+ * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+ */
+#define __LL_FMPI2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \
+ ((((uint32_t)(__PRESCALER__) << FMPI2C_TIMINGR_PRESC_Pos) & FMPI2C_TIMINGR_PRESC) | \
+ (((uint32_t)(__DATA_SETUP_TIME__) << FMPI2C_TIMINGR_SCLDEL_Pos) & FMPI2C_TIMINGR_SCLDEL) | \
+ (((uint32_t)(__DATA_HOLD_TIME__) << FMPI2C_TIMINGR_SDADEL_Pos) & FMPI2C_TIMINGR_SDADEL) | \
+ (((uint32_t)(__CLOCK_HIGH_PERIOD__) << FMPI2C_TIMINGR_SCLH_Pos) & FMPI2C_TIMINGR_SCLH) | \
+ (((uint32_t)(__CLOCK_LOW_PERIOD__) << FMPI2C_TIMINGR_SCLL_Pos) & FMPI2C_TIMINGR_SCLL))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FMPI2C_LL_Exported_Functions FMPI2C Exported Functions
+ * @{
+ */
+
+/** @defgroup FMPI2C_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Enable FMPI2C peripheral (PE = 1).
+ * @rmtoll CR1 PE LL_FMPI2C_Enable
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_Enable(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PE);
+}
+
+/**
+ * @brief Disable FMPI2C peripheral (PE = 0).
+ * @note When PE = 0, the FMPI2C SCL and SDA lines are released.
+ * Internal state machines and status bits are put back to their reset value.
+ * When cleared, PE must be kept low for at least 3 APB clock cycles.
+ * @rmtoll CR1 PE LL_FMPI2C_Disable
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_Disable(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PE);
+}
+
+/**
+ * @brief Check if the FMPI2C peripheral is enabled or disabled.
+ * @rmtoll CR1 PE LL_FMPI2C_IsEnabled
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabled(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PE) == (FMPI2C_CR1_PE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure Noise Filters (Analog and Digital).
+ * @note If the analog filter is also enabled, the digital filter is added to analog filter.
+ * The filters can only be programmed when the FMPI2C is disabled (PE = 0).
+ * @rmtoll CR1 ANFOFF LL_FMPI2C_ConfigFilters\n
+ * CR1 DNF LL_FMPI2C_ConfigFilters
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param AnalogFilter This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_ANALOGFILTER_ENABLE
+ * @arg @ref LL_FMPI2C_ANALOGFILTER_DISABLE
+ * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*tfmpi2cclk).
+ * This parameter is used to configure the digital noise filter on SDA and SCL input.
+ * The digital filter will filter spikes with a length of up to DNF[3:0]*tfmpi2cclk.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ConfigFilters(FMPI2C_TypeDef *FMPI2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
+{
+ MODIFY_REG(FMPI2Cx->CR1, FMPI2C_CR1_ANFOFF | FMPI2C_CR1_DNF, AnalogFilter | (DigitalFilter << FMPI2C_CR1_DNF_Pos));
+}
+
+/**
+ * @brief Configure Digital Noise Filter.
+ * @note If the analog filter is also enabled, the digital filter is added to analog filter.
+ * This filter can only be programmed when the FMPI2C is disabled (PE = 0).
+ * @rmtoll CR1 DNF LL_FMPI2C_SetDigitalFilter
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*tfmpi2cclk).
+ * This parameter is used to configure the digital noise filter on SDA and SCL input.
+ * The digital filter will filter spikes with a length of up to DNF[3:0]*tfmpi2cclk.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetDigitalFilter(FMPI2C_TypeDef *FMPI2Cx, uint32_t DigitalFilter)
+{
+ MODIFY_REG(FMPI2Cx->CR1, FMPI2C_CR1_DNF, DigitalFilter << FMPI2C_CR1_DNF_Pos);
+}
+
+/**
+ * @brief Get the current Digital Noise Filter configuration.
+ * @rmtoll CR1 DNF LL_FMPI2C_GetDigitalFilter
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0xF
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetDigitalFilter(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_DNF) >> FMPI2C_CR1_DNF_Pos);
+}
+
+/**
+ * @brief Enable Analog Noise Filter.
+ * @note This filter can only be programmed when the FMPI2C is disabled (PE = 0).
+ * @rmtoll CR1 ANFOFF LL_FMPI2C_EnableAnalogFilter
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableAnalogFilter(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ANFOFF);
+}
+
+/**
+ * @brief Disable Analog Noise Filter.
+ * @note This filter can only be programmed when the FMPI2C is disabled (PE = 0).
+ * @rmtoll CR1 ANFOFF LL_FMPI2C_DisableAnalogFilter
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableAnalogFilter(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ANFOFF);
+}
+
+/**
+ * @brief Check if Analog Noise Filter is enabled or disabled.
+ * @rmtoll CR1 ANFOFF LL_FMPI2C_IsEnabledAnalogFilter
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledAnalogFilter(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ANFOFF) != (FMPI2C_CR1_ANFOFF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable DMA transmission requests.
+ * @rmtoll CR1 TXDMAEN LL_FMPI2C_EnableDMAReq_TX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableDMAReq_TX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXDMAEN);
+}
+
+/**
+ * @brief Disable DMA transmission requests.
+ * @rmtoll CR1 TXDMAEN LL_FMPI2C_DisableDMAReq_TX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableDMAReq_TX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXDMAEN);
+}
+
+/**
+ * @brief Check if DMA transmission requests are enabled or disabled.
+ * @rmtoll CR1 TXDMAEN LL_FMPI2C_IsEnabledDMAReq_TX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledDMAReq_TX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXDMAEN) == (FMPI2C_CR1_TXDMAEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable DMA reception requests.
+ * @rmtoll CR1 RXDMAEN LL_FMPI2C_EnableDMAReq_RX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableDMAReq_RX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXDMAEN);
+}
+
+/**
+ * @brief Disable DMA reception requests.
+ * @rmtoll CR1 RXDMAEN LL_FMPI2C_DisableDMAReq_RX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableDMAReq_RX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXDMAEN);
+}
+
+/**
+ * @brief Check if DMA reception requests are enabled or disabled.
+ * @rmtoll CR1 RXDMAEN LL_FMPI2C_IsEnabledDMAReq_RX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledDMAReq_RX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXDMAEN) == (FMPI2C_CR1_RXDMAEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get the data register address used for DMA transfer
+ * @rmtoll TXDR TXDATA LL_FMPI2C_DMA_GetRegAddr\n
+ * RXDR RXDATA LL_FMPI2C_DMA_GetRegAddr
+ * @param FMPI2Cx FMPI2C Instance
+ * @param Direction This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_DMA_REG_DATA_TRANSMIT
+ * @arg @ref LL_FMPI2C_DMA_REG_DATA_RECEIVE
+ * @retval Address of data register
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_DMA_GetRegAddr(FMPI2C_TypeDef *FMPI2Cx, uint32_t Direction)
+{
+ uint32_t data_reg_addr;
+
+ if (Direction == LL_FMPI2C_DMA_REG_DATA_TRANSMIT)
+ {
+ /* return address of TXDR register */
+ data_reg_addr = (uint32_t) &(FMPI2Cx->TXDR);
+ }
+ else
+ {
+ /* return address of RXDR register */
+ data_reg_addr = (uint32_t) &(FMPI2Cx->RXDR);
+ }
+
+ return data_reg_addr;
+}
+
+/**
+ * @brief Enable Clock stretching.
+ * @note This bit can only be programmed when the FMPI2C is disabled (PE = 0).
+ * @rmtoll CR1 NOSTRETCH LL_FMPI2C_EnableClockStretching
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableClockStretching(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NOSTRETCH);
+}
+
+/**
+ * @brief Disable Clock stretching.
+ * @note This bit can only be programmed when the FMPI2C is disabled (PE = 0).
+ * @rmtoll CR1 NOSTRETCH LL_FMPI2C_DisableClockStretching
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableClockStretching(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NOSTRETCH);
+}
+
+/**
+ * @brief Check if Clock stretching is enabled or disabled.
+ * @rmtoll CR1 NOSTRETCH LL_FMPI2C_IsEnabledClockStretching
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledClockStretching(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NOSTRETCH) != (FMPI2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable hardware byte control in slave mode.
+ * @rmtoll CR1 SBC LL_FMPI2C_EnableSlaveByteControl
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableSlaveByteControl(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_SBC);
+}
+
+/**
+ * @brief Disable hardware byte control in slave mode.
+ * @rmtoll CR1 SBC LL_FMPI2C_DisableSlaveByteControl
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableSlaveByteControl(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_SBC);
+}
+
+/**
+ * @brief Check if hardware byte control in slave mode is enabled or disabled.
+ * @rmtoll CR1 SBC LL_FMPI2C_IsEnabledSlaveByteControl
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSlaveByteControl(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_SBC) == (FMPI2C_CR1_SBC)) ? 1UL : 0UL);
+}
+
+
+/**
+ * @brief Enable General Call.
+ * @note When enabled the Address 0x00 is ACKed.
+ * @rmtoll CR1 GCEN LL_FMPI2C_EnableGeneralCall
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableGeneralCall(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_GCEN);
+}
+
+/**
+ * @brief Disable General Call.
+ * @note When disabled the Address 0x00 is NACKed.
+ * @rmtoll CR1 GCEN LL_FMPI2C_DisableGeneralCall
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableGeneralCall(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_GCEN);
+}
+
+/**
+ * @brief Check if General Call is enabled or disabled.
+ * @rmtoll CR1 GCEN LL_FMPI2C_IsEnabledGeneralCall
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledGeneralCall(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_GCEN) == (FMPI2C_CR1_GCEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode.
+ * @note Changing this bit is not allowed, when the START bit is set.
+ * @rmtoll CR2 ADD10 LL_FMPI2C_SetMasterAddressingMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param AddressingMode This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_ADDRESSING_MODE_7BIT
+ * @arg @ref LL_FMPI2C_ADDRESSING_MODE_10BIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetMasterAddressingMode(FMPI2C_TypeDef *FMPI2Cx, uint32_t AddressingMode)
+{
+ MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_ADD10, AddressingMode);
+}
+
+/**
+ * @brief Get the Master addressing mode.
+ * @rmtoll CR2 ADD10 LL_FMPI2C_GetMasterAddressingMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_FMPI2C_ADDRESSING_MODE_7BIT
+ * @arg @ref LL_FMPI2C_ADDRESSING_MODE_10BIT
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetMasterAddressingMode(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_ADD10));
+}
+
+/**
+ * @brief Set the Own Address1.
+ * @rmtoll OAR1 OA1 LL_FMPI2C_SetOwnAddress1\n
+ * OAR1 OA1MODE LL_FMPI2C_SetOwnAddress1
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
+ * @param OwnAddrSize This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_OWNADDRESS1_7BIT
+ * @arg @ref LL_FMPI2C_OWNADDRESS1_10BIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetOwnAddress1(FMPI2C_TypeDef *FMPI2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
+{
+ MODIFY_REG(FMPI2Cx->OAR1, FMPI2C_OAR1_OA1 | FMPI2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
+}
+
+/**
+ * @brief Enable acknowledge on Own Address1 match address.
+ * @rmtoll OAR1 OA1EN LL_FMPI2C_EnableOwnAddress1
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableOwnAddress1(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->OAR1, FMPI2C_OAR1_OA1EN);
+}
+
+/**
+ * @brief Disable acknowledge on Own Address1 match address.
+ * @rmtoll OAR1 OA1EN LL_FMPI2C_DisableOwnAddress1
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableOwnAddress1(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->OAR1, FMPI2C_OAR1_OA1EN);
+}
+
+/**
+ * @brief Check if Own Address1 acknowledge is enabled or disabled.
+ * @rmtoll OAR1 OA1EN LL_FMPI2C_IsEnabledOwnAddress1
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledOwnAddress1(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->OAR1, FMPI2C_OAR1_OA1EN) == (FMPI2C_OAR1_OA1EN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set the 7bits Own Address2.
+ * @note This action has no effect if own address2 is enabled.
+ * @rmtoll OAR2 OA2 LL_FMPI2C_SetOwnAddress2\n
+ * OAR2 OA2MSK LL_FMPI2C_SetOwnAddress2
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
+ * @param OwnAddrMask This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_OWNADDRESS2_NOMASK
+ * @arg @ref LL_FMPI2C_OWNADDRESS2_MASK01
+ * @arg @ref LL_FMPI2C_OWNADDRESS2_MASK02
+ * @arg @ref LL_FMPI2C_OWNADDRESS2_MASK03
+ * @arg @ref LL_FMPI2C_OWNADDRESS2_MASK04
+ * @arg @ref LL_FMPI2C_OWNADDRESS2_MASK05
+ * @arg @ref LL_FMPI2C_OWNADDRESS2_MASK06
+ * @arg @ref LL_FMPI2C_OWNADDRESS2_MASK07
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetOwnAddress2(FMPI2C_TypeDef *FMPI2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
+{
+ MODIFY_REG(FMPI2Cx->OAR2, FMPI2C_OAR2_OA2 | FMPI2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
+}
+
+/**
+ * @brief Enable acknowledge on Own Address2 match address.
+ * @rmtoll OAR2 OA2EN LL_FMPI2C_EnableOwnAddress2
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableOwnAddress2(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->OAR2, FMPI2C_OAR2_OA2EN);
+}
+
+/**
+ * @brief Disable acknowledge on Own Address2 match address.
+ * @rmtoll OAR2 OA2EN LL_FMPI2C_DisableOwnAddress2
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableOwnAddress2(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->OAR2, FMPI2C_OAR2_OA2EN);
+}
+
+/**
+ * @brief Check if Own Address1 acknowledge is enabled or disabled.
+ * @rmtoll OAR2 OA2EN LL_FMPI2C_IsEnabledOwnAddress2
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledOwnAddress2(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->OAR2, FMPI2C_OAR2_OA2EN) == (FMPI2C_OAR2_OA2EN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure the SDA setup, hold time and the SCL high, low period.
+ * @note This bit can only be programmed when the FMPI2C is disabled (PE = 0).
+ * @rmtoll TIMINGR TIMINGR LL_FMPI2C_SetTiming
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
+ * @note This parameter is computed with the STM32CubeMX Tool.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetTiming(FMPI2C_TypeDef *FMPI2Cx, uint32_t Timing)
+{
+ WRITE_REG(FMPI2Cx->TIMINGR, Timing);
+}
+
+/**
+ * @brief Get the Timing Prescaler setting.
+ * @rmtoll TIMINGR PRESC LL_FMPI2C_GetTimingPrescaler
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0xF
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetTimingPrescaler(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_PRESC) >> FMPI2C_TIMINGR_PRESC_Pos);
+}
+
+/**
+ * @brief Get the SCL low period setting.
+ * @rmtoll TIMINGR SCLL LL_FMPI2C_GetClockLowPeriod
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetClockLowPeriod(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_SCLL) >> FMPI2C_TIMINGR_SCLL_Pos);
+}
+
+/**
+ * @brief Get the SCL high period setting.
+ * @rmtoll TIMINGR SCLH LL_FMPI2C_GetClockHighPeriod
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetClockHighPeriod(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_SCLH) >> FMPI2C_TIMINGR_SCLH_Pos);
+}
+
+/**
+ * @brief Get the SDA hold time.
+ * @rmtoll TIMINGR SDADEL LL_FMPI2C_GetDataHoldTime
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0xF
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetDataHoldTime(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_SDADEL) >> FMPI2C_TIMINGR_SDADEL_Pos);
+}
+
+/**
+ * @brief Get the SDA setup time.
+ * @rmtoll TIMINGR SCLDEL LL_FMPI2C_GetDataSetupTime
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0xF
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetDataSetupTime(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_SCLDEL) >> FMPI2C_TIMINGR_SCLDEL_Pos);
+}
+
+/**
+ * @brief Configure peripheral mode.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll CR1 SMBHEN LL_FMPI2C_SetMode\n
+ * CR1 SMBDEN LL_FMPI2C_SetMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param PeripheralMode This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_MODE_I2C
+ * @arg @ref LL_FMPI2C_MODE_SMBUS_HOST
+ * @arg @ref LL_FMPI2C_MODE_SMBUS_DEVICE
+ * @arg @ref LL_FMPI2C_MODE_SMBUS_DEVICE_ARP
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetMode(FMPI2C_TypeDef *FMPI2Cx, uint32_t PeripheralMode)
+{
+ MODIFY_REG(FMPI2Cx->CR1, FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN, PeripheralMode);
+}
+
+/**
+ * @brief Get peripheral mode.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll CR1 SMBHEN LL_FMPI2C_GetMode\n
+ * CR1 SMBDEN LL_FMPI2C_GetMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_FMPI2C_MODE_I2C
+ * @arg @ref LL_FMPI2C_MODE_SMBUS_HOST
+ * @arg @ref LL_FMPI2C_MODE_SMBUS_DEVICE
+ * @arg @ref LL_FMPI2C_MODE_SMBUS_DEVICE_ARP
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetMode(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN));
+}
+
+/**
+ * @brief Enable SMBus alert (Host or Device mode)
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note SMBus Device mode:
+ * - SMBus Alert pin is drived low and
+ * Alert Response Address Header acknowledge is enabled.
+ * SMBus Host mode:
+ * - SMBus Alert pin management is supported.
+ * @rmtoll CR1 ALERTEN LL_FMPI2C_EnableSMBusAlert
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableSMBusAlert(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ALERTEN);
+}
+
+/**
+ * @brief Disable SMBus alert (Host or Device mode)
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note SMBus Device mode:
+ * - SMBus Alert pin is not drived (can be used as a standard GPIO) and
+ * Alert Response Address Header acknowledge is disabled.
+ * SMBus Host mode:
+ * - SMBus Alert pin management is not supported.
+ * @rmtoll CR1 ALERTEN LL_FMPI2C_DisableSMBusAlert
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableSMBusAlert(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ALERTEN);
+}
+
+/**
+ * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll CR1 ALERTEN LL_FMPI2C_IsEnabledSMBusAlert
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusAlert(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ALERTEN) == (FMPI2C_CR1_ALERTEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable SMBus Packet Error Calculation (PEC).
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll CR1 PECEN LL_FMPI2C_EnableSMBusPEC
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableSMBusPEC(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PECEN);
+}
+
+/**
+ * @brief Disable SMBus Packet Error Calculation (PEC).
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll CR1 PECEN LL_FMPI2C_DisableSMBusPEC
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableSMBusPEC(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PECEN);
+}
+
+/**
+ * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll CR1 PECEN LL_FMPI2C_IsEnabledSMBusPEC
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusPEC(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PECEN) == (FMPI2C_CR1_PECEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure the SMBus Clock Timeout.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
+ * @rmtoll TIMEOUTR TIMEOUTA LL_FMPI2C_ConfigSMBusTimeout\n
+ * TIMEOUTR TIDLE LL_FMPI2C_ConfigSMBusTimeout\n
+ * TIMEOUTR TIMEOUTB LL_FMPI2C_ConfigSMBusTimeout
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
+ * @param TimeoutAMode This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
+ * @param TimeoutB
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ConfigSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
+ uint32_t TimeoutB)
+{
+ MODIFY_REG(FMPI2Cx->TIMEOUTR, FMPI2C_TIMEOUTR_TIMEOUTA | FMPI2C_TIMEOUTR_TIDLE | FMPI2C_TIMEOUTR_TIMEOUTB,
+ TimeoutA | TimeoutAMode | (TimeoutB << FMPI2C_TIMEOUTR_TIMEOUTB_Pos));
+}
+
+/**
+ * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note These bits can only be programmed when TimeoutA is disabled.
+ * @rmtoll TIMEOUTR TIMEOUTA LL_FMPI2C_SetSMBusTimeoutA
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutA(FMPI2C_TypeDef *FMPI2Cx, uint32_t TimeoutA)
+{
+ WRITE_REG(FMPI2Cx->TIMEOUTR, TimeoutA);
+}
+
+/**
+ * @brief Get the SMBus Clock TimeoutA setting.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll TIMEOUTR TIMEOUTA LL_FMPI2C_GetSMBusTimeoutA
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutA(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->TIMEOUTR, FMPI2C_TIMEOUTR_TIMEOUTA));
+}
+
+/**
+ * @brief Set the SMBus Clock TimeoutA mode.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note This bit can only be programmed when TimeoutA is disabled.
+ * @rmtoll TIMEOUTR TIDLE LL_FMPI2C_SetSMBusTimeoutAMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param TimeoutAMode This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutAMode(FMPI2C_TypeDef *FMPI2Cx, uint32_t TimeoutAMode)
+{
+ WRITE_REG(FMPI2Cx->TIMEOUTR, TimeoutAMode);
+}
+
+/**
+ * @brief Get the SMBus Clock TimeoutA mode.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll TIMEOUTR TIDLE LL_FMPI2C_GetSMBusTimeoutAMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutAMode(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->TIMEOUTR, FMPI2C_TIMEOUTR_TIDLE));
+}
+
+/**
+ * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note These bits can only be programmed when TimeoutB is disabled.
+ * @rmtoll TIMEOUTR TIMEOUTB LL_FMPI2C_SetSMBusTimeoutB
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutB(FMPI2C_TypeDef *FMPI2Cx, uint32_t TimeoutB)
+{
+ WRITE_REG(FMPI2Cx->TIMEOUTR, TimeoutB << FMPI2C_TIMEOUTR_TIMEOUTB_Pos);
+}
+
+/**
+ * @brief Get the SMBus Extended Cumulative Clock TimeoutB setting.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll TIMEOUTR TIMEOUTB LL_FMPI2C_GetSMBusTimeoutB
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutB(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->TIMEOUTR, FMPI2C_TIMEOUTR_TIMEOUTB) >> FMPI2C_TIMEOUTR_TIMEOUTB_Pos);
+}
+
+/**
+ * @brief Enable the SMBus Clock Timeout.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll TIMEOUTR TIMOUTEN LL_FMPI2C_EnableSMBusTimeout\n
+ * TIMEOUTR TEXTEN LL_FMPI2C_EnableSMBusTimeout
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param ClockTimeout This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTB
+ * @arg @ref LL_FMPI2C_SMBUS_ALL_TIMEOUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint32_t ClockTimeout)
+{
+ SET_BIT(FMPI2Cx->TIMEOUTR, ClockTimeout);
+}
+
+/**
+ * @brief Disable the SMBus Clock Timeout.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll TIMEOUTR TIMOUTEN LL_FMPI2C_DisableSMBusTimeout\n
+ * TIMEOUTR TEXTEN LL_FMPI2C_DisableSMBusTimeout
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param ClockTimeout This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTB
+ * @arg @ref LL_FMPI2C_SMBUS_ALL_TIMEOUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint32_t ClockTimeout)
+{
+ CLEAR_BIT(FMPI2Cx->TIMEOUTR, ClockTimeout);
+}
+
+/**
+ * @brief Check if the SMBus Clock Timeout is enabled or disabled.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll TIMEOUTR TIMOUTEN LL_FMPI2C_IsEnabledSMBusTimeout\n
+ * TIMEOUTR TEXTEN LL_FMPI2C_IsEnabledSMBusTimeout
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param ClockTimeout This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTB
+ * @arg @ref LL_FMPI2C_SMBUS_ALL_TIMEOUT
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint32_t ClockTimeout)
+{
+ return ((READ_BIT(FMPI2Cx->TIMEOUTR, (FMPI2C_TIMEOUTR_TIMOUTEN | FMPI2C_TIMEOUTR_TEXTEN)) == (ClockTimeout)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable TXIS interrupt.
+ * @rmtoll CR1 TXIE LL_FMPI2C_EnableIT_TX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableIT_TX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXIE);
+}
+
+/**
+ * @brief Disable TXIS interrupt.
+ * @rmtoll CR1 TXIE LL_FMPI2C_DisableIT_TX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableIT_TX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXIE);
+}
+
+/**
+ * @brief Check if the TXIS Interrupt is enabled or disabled.
+ * @rmtoll CR1 TXIE LL_FMPI2C_IsEnabledIT_TX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_TX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXIE) == (FMPI2C_CR1_TXIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable RXNE interrupt.
+ * @rmtoll CR1 RXIE LL_FMPI2C_EnableIT_RX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableIT_RX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXIE);
+}
+
+/**
+ * @brief Disable RXNE interrupt.
+ * @rmtoll CR1 RXIE LL_FMPI2C_DisableIT_RX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableIT_RX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXIE);
+}
+
+/**
+ * @brief Check if the RXNE Interrupt is enabled or disabled.
+ * @rmtoll CR1 RXIE LL_FMPI2C_IsEnabledIT_RX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_RX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXIE) == (FMPI2C_CR1_RXIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable Address match interrupt (slave mode only).
+ * @rmtoll CR1 ADDRIE LL_FMPI2C_EnableIT_ADDR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableIT_ADDR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ADDRIE);
+}
+
+/**
+ * @brief Disable Address match interrupt (slave mode only).
+ * @rmtoll CR1 ADDRIE LL_FMPI2C_DisableIT_ADDR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableIT_ADDR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ADDRIE);
+}
+
+/**
+ * @brief Check if Address match interrupt is enabled or disabled.
+ * @rmtoll CR1 ADDRIE LL_FMPI2C_IsEnabledIT_ADDR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_ADDR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ADDRIE) == (FMPI2C_CR1_ADDRIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable Not acknowledge received interrupt.
+ * @rmtoll CR1 NACKIE LL_FMPI2C_EnableIT_NACK
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableIT_NACK(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NACKIE);
+}
+
+/**
+ * @brief Disable Not acknowledge received interrupt.
+ * @rmtoll CR1 NACKIE LL_FMPI2C_DisableIT_NACK
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableIT_NACK(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NACKIE);
+}
+
+/**
+ * @brief Check if Not acknowledge received interrupt is enabled or disabled.
+ * @rmtoll CR1 NACKIE LL_FMPI2C_IsEnabledIT_NACK
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_NACK(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NACKIE) == (FMPI2C_CR1_NACKIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable STOP detection interrupt.
+ * @rmtoll CR1 STOPIE LL_FMPI2C_EnableIT_STOP
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableIT_STOP(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_STOPIE);
+}
+
+/**
+ * @brief Disable STOP detection interrupt.
+ * @rmtoll CR1 STOPIE LL_FMPI2C_DisableIT_STOP
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableIT_STOP(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_STOPIE);
+}
+
+/**
+ * @brief Check if STOP detection interrupt is enabled or disabled.
+ * @rmtoll CR1 STOPIE LL_FMPI2C_IsEnabledIT_STOP
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_STOP(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_STOPIE) == (FMPI2C_CR1_STOPIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable Transfer Complete interrupt.
+ * @note Any of these events will generate interrupt :
+ * Transfer Complete (TC)
+ * Transfer Complete Reload (TCR)
+ * @rmtoll CR1 TCIE LL_FMPI2C_EnableIT_TC
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableIT_TC(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TCIE);
+}
+
+/**
+ * @brief Disable Transfer Complete interrupt.
+ * @note Any of these events will generate interrupt :
+ * Transfer Complete (TC)
+ * Transfer Complete Reload (TCR)
+ * @rmtoll CR1 TCIE LL_FMPI2C_DisableIT_TC
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableIT_TC(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TCIE);
+}
+
+/**
+ * @brief Check if Transfer Complete interrupt is enabled or disabled.
+ * @rmtoll CR1 TCIE LL_FMPI2C_IsEnabledIT_TC
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_TC(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TCIE) == (FMPI2C_CR1_TCIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable Error interrupts.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note Any of these errors will generate interrupt :
+ * Arbitration Loss (ARLO)
+ * Bus Error detection (BERR)
+ * Overrun/Underrun (OVR)
+ * SMBus Timeout detection (TIMEOUT)
+ * SMBus PEC error detection (PECERR)
+ * SMBus Alert pin event detection (ALERT)
+ * @rmtoll CR1 ERRIE LL_FMPI2C_EnableIT_ERR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableIT_ERR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ERRIE);
+}
+
+/**
+ * @brief Disable Error interrupts.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note Any of these errors will generate interrupt :
+ * Arbitration Loss (ARLO)
+ * Bus Error detection (BERR)
+ * Overrun/Underrun (OVR)
+ * SMBus Timeout detection (TIMEOUT)
+ * SMBus PEC error detection (PECERR)
+ * SMBus Alert pin event detection (ALERT)
+ * @rmtoll CR1 ERRIE LL_FMPI2C_DisableIT_ERR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableIT_ERR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ERRIE);
+}
+
+/**
+ * @brief Check if Error interrupts are enabled or disabled.
+ * @rmtoll CR1 ERRIE LL_FMPI2C_IsEnabledIT_ERR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_ERR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ERRIE) == (FMPI2C_CR1_ERRIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EF_FLAG_management FLAG_management
+ * @{
+ */
+
+/**
+ * @brief Indicate the status of Transmit data register empty flag.
+ * @note RESET: When next data is written in Transmit data register.
+ * SET: When Transmit data register is empty.
+ * @rmtoll ISR TXE LL_FMPI2C_IsActiveFlag_TXE
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TXE(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TXE) == (FMPI2C_ISR_TXE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Transmit interrupt flag.
+ * @note RESET: When next data is written in Transmit data register.
+ * SET: When Transmit data register is empty.
+ * @rmtoll ISR TXIS LL_FMPI2C_IsActiveFlag_TXIS
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TXIS(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TXIS) == (FMPI2C_ISR_TXIS)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Receive data register not empty flag.
+ * @note RESET: When Receive data register is read.
+ * SET: When the received data is copied in Receive data register.
+ * @rmtoll ISR RXNE LL_FMPI2C_IsActiveFlag_RXNE
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_RXNE(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_RXNE) == (FMPI2C_ISR_RXNE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Address matched flag (slave mode).
+ * @note RESET: Clear default value.
+ * SET: When the received slave address matched with one of the enabled slave address.
+ * @rmtoll ISR ADDR LL_FMPI2C_IsActiveFlag_ADDR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_ADDR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_ADDR) == (FMPI2C_ISR_ADDR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Not Acknowledge received flag.
+ * @note RESET: Clear default value.
+ * SET: When a NACK is received after a byte transmission.
+ * @rmtoll ISR NACKF LL_FMPI2C_IsActiveFlag_NACK
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_NACK(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_NACKF) == (FMPI2C_ISR_NACKF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Stop detection flag.
+ * @note RESET: Clear default value.
+ * SET: When a Stop condition is detected.
+ * @rmtoll ISR STOPF LL_FMPI2C_IsActiveFlag_STOP
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_STOP(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_STOPF) == (FMPI2C_ISR_STOPF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Transfer complete flag (master mode).
+ * @note RESET: Clear default value.
+ * SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
+ * @rmtoll ISR TC LL_FMPI2C_IsActiveFlag_TC
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TC(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TC) == (FMPI2C_ISR_TC)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Transfer complete flag (master mode).
+ * @note RESET: Clear default value.
+ * SET: When RELOAD=1 and NBYTES date have been transferred.
+ * @rmtoll ISR TCR LL_FMPI2C_IsActiveFlag_TCR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TCR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TCR) == (FMPI2C_ISR_TCR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Bus error flag.
+ * @note RESET: Clear default value.
+ * SET: When a misplaced Start or Stop condition is detected.
+ * @rmtoll ISR BERR LL_FMPI2C_IsActiveFlag_BERR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_BERR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_BERR) == (FMPI2C_ISR_BERR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Arbitration lost flag.
+ * @note RESET: Clear default value.
+ * SET: When arbitration lost.
+ * @rmtoll ISR ARLO LL_FMPI2C_IsActiveFlag_ARLO
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_ARLO(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_ARLO) == (FMPI2C_ISR_ARLO)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Overrun/Underrun flag (slave mode).
+ * @note RESET: Clear default value.
+ * SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
+ * @rmtoll ISR OVR LL_FMPI2C_IsActiveFlag_OVR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_OVR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_OVR) == (FMPI2C_ISR_OVR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of SMBus PEC error flag in reception.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note RESET: Clear default value.
+ * SET: When the received PEC does not match with the PEC register content.
+ * @rmtoll ISR PECERR LL_FMPI2C_IsActiveSMBusFlag_PECERR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_PECERR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_PECERR) == (FMPI2C_ISR_PECERR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of SMBus Timeout detection flag.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note RESET: Clear default value.
+ * SET: When a timeout or extended clock timeout occurs.
+ * @rmtoll ISR TIMEOUT LL_FMPI2C_IsActiveSMBusFlag_TIMEOUT
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_TIMEOUT(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TIMEOUT) == (FMPI2C_ISR_TIMEOUT)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of SMBus alert flag.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note RESET: Clear default value.
+ * SET: When SMBus host configuration, SMBus alert enabled and
+ * a falling edge event occurs on SMBA pin.
+ * @rmtoll ISR ALERT LL_FMPI2C_IsActiveSMBusFlag_ALERT
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_ALERT(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_ALERT) == (FMPI2C_ISR_ALERT)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Bus Busy flag.
+ * @note RESET: Clear default value.
+ * SET: When a Start condition is detected.
+ * @rmtoll ISR BUSY LL_FMPI2C_IsActiveFlag_BUSY
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_BUSY(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_BUSY) == (FMPI2C_ISR_BUSY)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear Address Matched flag.
+ * @rmtoll ICR ADDRCF LL_FMPI2C_ClearFlag_ADDR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ClearFlag_ADDR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_ADDRCF);
+}
+
+/**
+ * @brief Clear Not Acknowledge flag.
+ * @rmtoll ICR NACKCF LL_FMPI2C_ClearFlag_NACK
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ClearFlag_NACK(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_NACKCF);
+}
+
+/**
+ * @brief Clear Stop detection flag.
+ * @rmtoll ICR STOPCF LL_FMPI2C_ClearFlag_STOP
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ClearFlag_STOP(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_STOPCF);
+}
+
+/**
+ * @brief Clear Transmit data register empty flag (TXE).
+ * @note This bit can be clear by software in order to flush the transmit data register (TXDR).
+ * @rmtoll ISR TXE LL_FMPI2C_ClearFlag_TXE
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ClearFlag_TXE(FMPI2C_TypeDef *FMPI2Cx)
+{
+ WRITE_REG(FMPI2Cx->ISR, FMPI2C_ISR_TXE);
+}
+
+/**
+ * @brief Clear Bus error flag.
+ * @rmtoll ICR BERRCF LL_FMPI2C_ClearFlag_BERR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ClearFlag_BERR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_BERRCF);
+}
+
+/**
+ * @brief Clear Arbitration lost flag.
+ * @rmtoll ICR ARLOCF LL_FMPI2C_ClearFlag_ARLO
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ClearFlag_ARLO(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_ARLOCF);
+}
+
+/**
+ * @brief Clear Overrun/Underrun flag.
+ * @rmtoll ICR OVRCF LL_FMPI2C_ClearFlag_OVR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ClearFlag_OVR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_OVRCF);
+}
+
+/**
+ * @brief Clear SMBus PEC error flag.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll ICR PECCF LL_FMPI2C_ClearSMBusFlag_PECERR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ClearSMBusFlag_PECERR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_PECCF);
+}
+
+/**
+ * @brief Clear SMBus Timeout detection flag.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll ICR TIMOUTCF LL_FMPI2C_ClearSMBusFlag_TIMEOUT
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ClearSMBusFlag_TIMEOUT(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_TIMOUTCF);
+}
+
+/**
+ * @brief Clear SMBus Alert flag.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll ICR ALERTCF LL_FMPI2C_ClearSMBusFlag_ALERT
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ClearSMBusFlag_ALERT(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_ALERTCF);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EF_Data_Management Data_Management
+ * @{
+ */
+
+/**
+ * @brief Enable automatic STOP condition generation (master mode).
+ * @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
+ * This bit has no effect in slave mode or when RELOAD bit is set.
+ * @rmtoll CR2 AUTOEND LL_FMPI2C_EnableAutoEndMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableAutoEndMode(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_AUTOEND);
+}
+
+/**
+ * @brief Disable automatic STOP condition generation (master mode).
+ * @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
+ * @rmtoll CR2 AUTOEND LL_FMPI2C_DisableAutoEndMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableAutoEndMode(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR2, FMPI2C_CR2_AUTOEND);
+}
+
+/**
+ * @brief Check if automatic STOP condition is enabled or disabled.
+ * @rmtoll CR2 AUTOEND LL_FMPI2C_IsEnabledAutoEndMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledAutoEndMode(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_AUTOEND) == (FMPI2C_CR2_AUTOEND)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable reload mode (master mode).
+ * @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
+ * @rmtoll CR2 RELOAD LL_FMPI2C_EnableReloadMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableReloadMode(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_RELOAD);
+}
+
+/**
+ * @brief Disable reload mode (master mode).
+ * @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
+ * @rmtoll CR2 RELOAD LL_FMPI2C_DisableReloadMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableReloadMode(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR2, FMPI2C_CR2_RELOAD);
+}
+
+/**
+ * @brief Check if reload mode is enabled or disabled.
+ * @rmtoll CR2 RELOAD LL_FMPI2C_IsEnabledReloadMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledReloadMode(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_RELOAD) == (FMPI2C_CR2_RELOAD)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure the number of bytes for transfer.
+ * @note Changing these bits when START bit is set is not allowed.
+ * @rmtoll CR2 NBYTES LL_FMPI2C_SetTransferSize
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetTransferSize(FMPI2C_TypeDef *FMPI2Cx, uint32_t TransferSize)
+{
+ MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_NBYTES, TransferSize << FMPI2C_CR2_NBYTES_Pos);
+}
+
+/**
+ * @brief Get the number of bytes configured for transfer.
+ * @rmtoll CR2 NBYTES LL_FMPI2C_GetTransferSize
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetTransferSize(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_NBYTES) >> FMPI2C_CR2_NBYTES_Pos);
+}
+
+/**
+ * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
+ * @note Usage in Slave mode only.
+ * @rmtoll CR2 NACK LL_FMPI2C_AcknowledgeNextData
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param TypeAcknowledge This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_ACK
+ * @arg @ref LL_FMPI2C_NACK
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_AcknowledgeNextData(FMPI2C_TypeDef *FMPI2Cx, uint32_t TypeAcknowledge)
+{
+ MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_NACK, TypeAcknowledge);
+}
+
+/**
+ * @brief Generate a START or RESTART condition
+ * @note The START bit can be set even if bus is BUSY or FMPI2C is in slave mode.
+ * This action has no effect when RELOAD is set.
+ * @rmtoll CR2 START LL_FMPI2C_GenerateStartCondition
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_GenerateStartCondition(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_START);
+}
+
+/**
+ * @brief Generate a STOP condition after the current byte transfer (master mode).
+ * @rmtoll CR2 STOP LL_FMPI2C_GenerateStopCondition
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_GenerateStopCondition(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_STOP);
+}
+
+/**
+ * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode).
+ * @note The master sends the complete 10bit slave address read sequence :
+ * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
+ * @rmtoll CR2 HEAD10R LL_FMPI2C_EnableAuto10BitRead
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableAuto10BitRead(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR2, FMPI2C_CR2_HEAD10R);
+}
+
+/**
+ * @brief Disable automatic RESTART Read request condition for 10bit address header (master mode).
+ * @note The master only sends the first 7 bits of 10bit address in Read direction.
+ * @rmtoll CR2 HEAD10R LL_FMPI2C_DisableAuto10BitRead
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableAuto10BitRead(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_HEAD10R);
+}
+
+/**
+ * @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
+ * @rmtoll CR2 HEAD10R LL_FMPI2C_IsEnabledAuto10BitRead
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledAuto10BitRead(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_HEAD10R) != (FMPI2C_CR2_HEAD10R)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure the transfer direction (master mode).
+ * @note Changing these bits when START bit is set is not allowed.
+ * @rmtoll CR2 RD_WRN LL_FMPI2C_SetTransferRequest
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param TransferRequest This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_REQUEST_WRITE
+ * @arg @ref LL_FMPI2C_REQUEST_READ
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetTransferRequest(FMPI2C_TypeDef *FMPI2Cx, uint32_t TransferRequest)
+{
+ MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_RD_WRN, TransferRequest);
+}
+
+/**
+ * @brief Get the transfer direction requested (master mode).
+ * @rmtoll CR2 RD_WRN LL_FMPI2C_GetTransferRequest
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_FMPI2C_REQUEST_WRITE
+ * @arg @ref LL_FMPI2C_REQUEST_READ
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetTransferRequest(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_RD_WRN));
+}
+
+/**
+ * @brief Configure the slave address for transfer (master mode).
+ * @note Changing these bits when START bit is set is not allowed.
+ * @rmtoll CR2 SADD LL_FMPI2C_SetSlaveAddr
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetSlaveAddr(FMPI2C_TypeDef *FMPI2Cx, uint32_t SlaveAddr)
+{
+ MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_SADD, SlaveAddr);
+}
+
+/**
+ * @brief Get the slave address programmed for transfer.
+ * @rmtoll CR2 SADD LL_FMPI2C_GetSlaveAddr
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0x3F
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetSlaveAddr(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_SADD));
+}
+
+/**
+ * @brief Handles FMPI2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
+ * @rmtoll CR2 SADD LL_FMPI2C_HandleTransfer\n
+ * CR2 ADD10 LL_FMPI2C_HandleTransfer\n
+ * CR2 RD_WRN LL_FMPI2C_HandleTransfer\n
+ * CR2 START LL_FMPI2C_HandleTransfer\n
+ * CR2 STOP LL_FMPI2C_HandleTransfer\n
+ * CR2 RELOAD LL_FMPI2C_HandleTransfer\n
+ * CR2 NBYTES LL_FMPI2C_HandleTransfer\n
+ * CR2 AUTOEND LL_FMPI2C_HandleTransfer\n
+ * CR2 HEAD10R LL_FMPI2C_HandleTransfer
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param SlaveAddr Specifies the slave address to be programmed.
+ * @param SlaveAddrSize This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_ADDRSLAVE_7BIT
+ * @arg @ref LL_FMPI2C_ADDRSLAVE_10BIT
+ * @param TransferSize Specifies the number of bytes to be programmed.
+ * This parameter must be a value between Min_Data=0 and Max_Data=255.
+ * @param EndMode This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_MODE_RELOAD
+ * @arg @ref LL_FMPI2C_MODE_AUTOEND
+ * @arg @ref LL_FMPI2C_MODE_SOFTEND
+ * @arg @ref LL_FMPI2C_MODE_SMBUS_RELOAD
+ * @arg @ref LL_FMPI2C_MODE_SMBUS_AUTOEND_NO_PEC
+ * @arg @ref LL_FMPI2C_MODE_SMBUS_SOFTEND_NO_PEC
+ * @arg @ref LL_FMPI2C_MODE_SMBUS_AUTOEND_WITH_PEC
+ * @arg @ref LL_FMPI2C_MODE_SMBUS_SOFTEND_WITH_PEC
+ * @param Request This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_GENERATE_NOSTARTSTOP
+ * @arg @ref LL_FMPI2C_GENERATE_STOP
+ * @arg @ref LL_FMPI2C_GENERATE_START_READ
+ * @arg @ref LL_FMPI2C_GENERATE_START_WRITE
+ * @arg @ref LL_FMPI2C_GENERATE_RESTART_7BIT_READ
+ * @arg @ref LL_FMPI2C_GENERATE_RESTART_7BIT_WRITE
+ * @arg @ref LL_FMPI2C_GENERATE_RESTART_10BIT_READ
+ * @arg @ref LL_FMPI2C_GENERATE_RESTART_10BIT_WRITE
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_HandleTransfer(FMPI2C_TypeDef *FMPI2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
+ uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
+{
+ MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_SADD | FMPI2C_CR2_ADD10 |
+ (FMPI2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - FMPI2C_CR2_RD_WRN_Pos))) |
+ FMPI2C_CR2_START | FMPI2C_CR2_STOP | FMPI2C_CR2_RELOAD |
+ FMPI2C_CR2_NBYTES | FMPI2C_CR2_AUTOEND | FMPI2C_CR2_HEAD10R,
+ SlaveAddr | SlaveAddrSize | (TransferSize << FMPI2C_CR2_NBYTES_Pos) | EndMode | Request);
+}
+
+/**
+ * @brief Indicate the value of transfer direction (slave mode).
+ * @note RESET: Write transfer, Slave enters in receiver mode.
+ * SET: Read transfer, Slave enters in transmitter mode.
+ * @rmtoll ISR DIR LL_FMPI2C_GetTransferDirection
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_FMPI2C_DIRECTION_WRITE
+ * @arg @ref LL_FMPI2C_DIRECTION_READ
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetTransferDirection(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_DIR));
+}
+
+/**
+ * @brief Return the slave matched address.
+ * @rmtoll ISR ADDCODE LL_FMPI2C_GetAddressMatchCode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0x00 and Max_Data=0x3F
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetAddressMatchCode(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_ADDCODE) >> FMPI2C_ISR_ADDCODE_Pos << 1);
+}
+
+/**
+ * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received.
+ * This bit has no effect when RELOAD bit is set.
+ * This bit has no effect in device mode when SBC bit is not set.
+ * @rmtoll CR2 PECBYTE LL_FMPI2C_EnableSMBusPECCompare
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableSMBusPECCompare(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_PECBYTE);
+}
+
+/**
+ * @brief Check if the SMBus Packet Error byte internal comparison is requested or not.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll CR2 PECBYTE LL_FMPI2C_IsEnabledSMBusPECCompare
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusPECCompare(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_PECBYTE) == (FMPI2C_CR2_PECBYTE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get the SMBus Packet Error byte calculated.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll PECR PEC LL_FMPI2C_GetSMBusPEC
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusPEC(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->PECR, FMPI2C_PECR_PEC));
+}
+
+/**
+ * @brief Read Receive Data register.
+ * @rmtoll RXDR RXDATA LL_FMPI2C_ReceiveData8
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t LL_FMPI2C_ReceiveData8(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint8_t)(READ_BIT(FMPI2Cx->RXDR, FMPI2C_RXDR_RXDATA));
+}
+
+/**
+ * @brief Write in Transmit Data Register .
+ * @rmtoll TXDR TXDATA LL_FMPI2C_TransmitData8
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_TransmitData8(FMPI2C_TypeDef *FMPI2Cx, uint8_t Data)
+{
+ WRITE_REG(FMPI2Cx->TXDR, Data);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup FMPI2C_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_FMPI2C_Init(FMPI2C_TypeDef *FMPI2Cx, LL_FMPI2C_InitTypeDef *FMPI2C_InitStruct);
+ErrorStatus LL_FMPI2C_DeInit(FMPI2C_TypeDef *FMPI2Cx);
+void LL_FMPI2C_StructInit(LL_FMPI2C_InitTypeDef *FMPI2C_InitStruct);
+
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* FMPI2C1 */
+
+/**
+ * @}
+ */
+
+#endif /* FMPI2C_CR1_PE */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F4xx_LL_FMPI2C_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h
index 3f1b3a1d6e..76e9170a0d 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h
@@ -939,7 +939,8 @@ __STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMas
*/
__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
- WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask);
+ uint32_t odr = READ_REG(GPIOx->ODR);
+ WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
}
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h
index b173cc699b..5a46babfdc 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h
@@ -837,8 +837,8 @@ __STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx)
__STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed,
uint32_t DutyCycle)
{
- register uint32_t freqrange = 0x0U;
- register uint32_t clockconfig = 0x0U;
+ uint32_t freqrange = 0x0U;
+ uint32_t clockconfig = 0x0U;
/* Compute frequency range */
freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock);
@@ -1468,7 +1468,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef *I2Cx)
/**
* @brief Indicate the status of General call address reception (Slave mode).
- * @note RESET: No Generall call address
+ * @note RESET: No General call address
* SET: General call address received.
* @note This status is cleared by hardware after a STOP condition or repeated START condition.
* @rmtoll SR2 GENCALL LL_I2C_IsActiveFlag_GENCALL
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_iwdg.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_iwdg.h
index 5711351180..2f1b844a9c 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_iwdg.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_iwdg.h
@@ -236,7 +236,6 @@ __STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
return (READ_REG(IWDGx->RLR));
}
-
/**
* @}
*/
@@ -283,7 +282,6 @@ __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
* @}
*/
-
/**
* @}
*/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_lptim.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_lptim.h
index 636e5fa4e6..0d8e8eaee8 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_lptim.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_lptim.h
@@ -4,7 +4,7 @@
* @author MCD Application Team
* @brief Header file of LPTIM LL module.
******************************************************************************
- * @attention
+ * @attention
*
* © Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
@@ -155,7 +155,7 @@ typedef struct
/** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
* @{
*/
-#define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
}
/**
@@ -394,7 +405,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx)
* @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
* @note After a write to the LPTIMx_ARR register a new write operation to the
* same register can only be performed when the previous write operation
- * is completed. Any successive write before the ARROK flag be set, will
+ * is completed. Any successive write before the ARROK flag is set, will
* lead to unpredictable results.
* @note autoreload value be strictly greater than the compare value.
* @rmtoll ARR ARR LL_LPTIM_SetAutoReload
@@ -422,7 +433,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx)
* @brief Set the compare value
* @note After a write to the LPTIMx_CMP register a new write operation to the
* same register can only be performed when the previous write operation
- * is completed. Any successive write before the CMPOK flag be set, will
+ * is completed. Any successive write before the CMPOK flag is set, will
* lead to unpredictable results.
* @rmtoll CMP CMP LL_LPTIM_SetCompare
* @param LPTIMx Low-Power Timer instance
@@ -608,6 +619,22 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx)
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
}
+/**
+ * @brief Set LPTIM input 1 source (default GPIO).
+ * @rmtoll OR OR LL_LPTIM_SetInput1Src
+ * @param LPTIMx Low-Power Timer instance
+ * @param Src This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_INPUT1_SRC_PAD_AF
+ * @arg @ref LL_LPTIM_INPUT1_SRC_PAD_PA4
+ * @arg @ref LL_LPTIM_INPUT1_SRC_PAD_PB9
+ * @arg @ref LL_LPTIM_INPUT1_SRC_TIM_DAC
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
+{
+ MODIFY_REG(LPTIMx->OR, LPTIM_OR_OR, Src);
+}
+
/**
* @}
*/
@@ -655,7 +682,7 @@ __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
}
/**
@@ -914,7 +941,7 @@ __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
}
/**
@@ -944,7 +971,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL));
}
/**
@@ -966,7 +993,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
}
/**
@@ -988,7 +1015,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
}
/**
@@ -1010,7 +1037,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL));
}
/**
@@ -1032,7 +1059,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
}
/**
@@ -1054,7 +1081,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
}
/**
@@ -1076,7 +1103,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
}
/**
@@ -1117,7 +1144,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL));
}
/**
@@ -1150,7 +1177,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL));
}
/**
@@ -1183,7 +1210,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL));
}
/**
@@ -1216,7 +1243,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL));
}
/**
@@ -1245,11 +1272,11 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
* @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
* @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
* @param LPTIMx Low-Power Timer instance
- * @retval State of bit (1 or 0).
+ * @retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL));
}
/**
@@ -1278,11 +1305,11 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
* @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
* @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
* @param LPTIMx Low-Power Timer instance
- * @retval State of bit (1 or 0).
+ * @retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL));
}
/**
@@ -1311,11 +1338,11 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
* @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
* @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
* @param LPTIMx Low-Power Timer instance
- * @retval State of bit (1 or 0).
+ * @retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)
{
- return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE)? 1UL : 0UL);
+ return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL);
}
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h
index 0cb40995e4..d4c249fc31 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h
@@ -5338,7 +5338,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
*/
__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ_R, uint32_t PLLDIVQ_R)
{
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
#if defined(RCC_PLLI2SCFGR_PLLI2SM)
MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
@@ -5458,7 +5458,7 @@ __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PL
*/
__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
{
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
#if defined(RCC_PLLI2SCFGR_PLLI2SM)
MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
@@ -5662,7 +5662,7 @@ __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_
*/
__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
{
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
#if defined(RCC_PLLI2SCFGR_PLLI2SM)
MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
@@ -5924,9 +5924,9 @@ __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDivider(void)
__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMainSource(void)
{
#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
- register uint32_t pllsrc = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
- register uint32_t plli2sssrc0 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC);
- register uint32_t plli2sssrc1 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC) >> 15U;
+ uint32_t pllsrc = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
+ uint32_t plli2sssrc0 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC);
+ uint32_t plli2sssrc1 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC) >> 15U;
return (uint32_t)(pllsrc | plli2sssrc0 | plli2sssrc1);
#else
return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h
index 026da3c103..540a0e180d 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h
@@ -12,24 +12,20 @@
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_LL_SDMMC_H
-#define __STM32F4xx_LL_SDMMC_H
+#ifndef STM32F4xx_LL_SDMMC_H
+#define STM32F4xx_LL_SDMMC_H
#ifdef __cplusplus
extern "C" {
#endif
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
- defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
- defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+
+#if defined(SDIO)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -133,196 +129,199 @@ typedef struct
/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
* @{
*/
-#define SDMMC_ERROR_NONE 0x00000000U /*!< No error */
-#define SDMMC_ERROR_CMD_CRC_FAIL 0x00000001U /*!< Command response received (but CRC check failed) */
-#define SDMMC_ERROR_DATA_CRC_FAIL 0x00000002U /*!< Data block sent/received (CRC check failed) */
-#define SDMMC_ERROR_CMD_RSP_TIMEOUT 0x00000004U /*!< Command response timeout */
-#define SDMMC_ERROR_DATA_TIMEOUT 0x00000008U /*!< Data timeout */
-#define SDMMC_ERROR_TX_UNDERRUN 0x00000010U /*!< Transmit FIFO underrun */
-#define SDMMC_ERROR_RX_OVERRUN 0x00000020U /*!< Receive FIFO overrun */
-#define SDMMC_ERROR_ADDR_MISALIGNED 0x00000040U /*!< Misaligned address */
-#define SDMMC_ERROR_BLOCK_LEN_ERR 0x00000080U /*!< Transferred block length is not allowed for the card or the
- number of transferred bytes does not match the block length */
-#define SDMMC_ERROR_ERASE_SEQ_ERR 0x00000100U /*!< An error in the sequence of erase command occurs */
-#define SDMMC_ERROR_BAD_ERASE_PARAM 0x00000200U /*!< An invalid selection for erase groups */
-#define SDMMC_ERROR_WRITE_PROT_VIOLATION 0x00000400U /*!< Attempt to program a write protect block */
-#define SDMMC_ERROR_LOCK_UNLOCK_FAILED 0x00000800U /*!< Sequence or password error has been detected in unlock
- command or if there was an attempt to access a locked card */
-#define SDMMC_ERROR_COM_CRC_FAILED 0x00001000U /*!< CRC check of the previous command failed */
-#define SDMMC_ERROR_ILLEGAL_CMD 0x00002000U /*!< Command is not legal for the card state */
-#define SDMMC_ERROR_CARD_ECC_FAILED 0x00004000U /*!< Card internal ECC was applied but failed to correct the data */
-#define SDMMC_ERROR_CC_ERR 0x00008000U /*!< Internal card controller error */
-#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR 0x00010000U /*!< General or unknown error */
-#define SDMMC_ERROR_STREAM_READ_UNDERRUN 0x00020000U /*!< The card could not sustain data reading in stream rmode */
-#define SDMMC_ERROR_STREAM_WRITE_OVERRUN 0x00040000U /*!< The card could not sustain data programming in stream mode */
-#define SDMMC_ERROR_CID_CSD_OVERWRITE 0x00080000U /*!< CID/CSD overwrite error */
-#define SDMMC_ERROR_WP_ERASE_SKIP 0x00100000U /*!< Only partial address space was erased */
-#define SDMMC_ERROR_CARD_ECC_DISABLED 0x00200000U /*!< Command has been executed without using internal ECC */
-#define SDMMC_ERROR_ERASE_RESET 0x00400000U /*!< Erase sequence was cleared before executing because an out
- of erase sequence command was received */
-#define SDMMC_ERROR_AKE_SEQ_ERR 0x00800000U /*!< Error in sequence of authentication */
-#define SDMMC_ERROR_INVALID_VOLTRANGE 0x01000000U /*!< Error in case of invalid voltage range */
-#define SDMMC_ERROR_ADDR_OUT_OF_RANGE 0x02000000U /*!< Error when addressed block is out of range */
-#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE 0x04000000U /*!< Error when command request is not applicable */
-#define SDMMC_ERROR_INVALID_PARAMETER 0x08000000U /*!< the used parameter is not valid */
-#define SDMMC_ERROR_UNSUPPORTED_FEATURE 0x10000000U /*!< Error when feature is not insupported */
-#define SDMMC_ERROR_BUSY 0x20000000U /*!< Error when transfer process is busy */
-#define SDMMC_ERROR_DMA 0x40000000U /*!< Error while DMA transfer */
-#define SDMMC_ERROR_TIMEOUT 0x80000000U /*!< Timeout error */
+#define SDMMC_ERROR_NONE 0x00000000U /*!< No error */
+#define SDMMC_ERROR_CMD_CRC_FAIL 0x00000001U /*!< Command response received (but CRC check failed) */
+#define SDMMC_ERROR_DATA_CRC_FAIL 0x00000002U /*!< Data block sent/received (CRC check failed) */
+#define SDMMC_ERROR_CMD_RSP_TIMEOUT 0x00000004U /*!< Command response timeout */
+#define SDMMC_ERROR_DATA_TIMEOUT 0x00000008U /*!< Data timeout */
+#define SDMMC_ERROR_TX_UNDERRUN 0x00000010U /*!< Transmit FIFO underrun */
+#define SDMMC_ERROR_RX_OVERRUN 0x00000020U /*!< Receive FIFO overrun */
+#define SDMMC_ERROR_ADDR_MISALIGNED 0x00000040U /*!< Misaligned address */
+#define SDMMC_ERROR_BLOCK_LEN_ERR 0x00000080U /*!< Transferred block length is not allowed for the card or the
+ number of transferred bytes does not match the block length */
+#define SDMMC_ERROR_ERASE_SEQ_ERR 0x00000100U /*!< An error in the sequence of erase command occurs */
+#define SDMMC_ERROR_BAD_ERASE_PARAM 0x00000200U /*!< An invalid selection for erase groups */
+#define SDMMC_ERROR_WRITE_PROT_VIOLATION 0x00000400U /*!< Attempt to program a write protect block */
+#define SDMMC_ERROR_LOCK_UNLOCK_FAILED 0x00000800U /*!< Sequence or password error has been detected in unlock
+ command or if there was an attempt to access a locked card */
+#define SDMMC_ERROR_COM_CRC_FAILED 0x00001000U /*!< CRC check of the previous command failed */
+#define SDMMC_ERROR_ILLEGAL_CMD 0x00002000U /*!< Command is not legal for the card state */
+#define SDMMC_ERROR_CARD_ECC_FAILED 0x00004000U /*!< Card internal ECC was applied but failed to correct the data */
+#define SDMMC_ERROR_CC_ERR 0x00008000U /*!< Internal card controller error */
+#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR 0x00010000U /*!< General or unknown error */
+#define SDMMC_ERROR_STREAM_READ_UNDERRUN 0x00020000U /*!< The card could not sustain data reading in stream rmode */
+#define SDMMC_ERROR_STREAM_WRITE_OVERRUN 0x00040000U /*!< The card could not sustain data programming in stream mode */
+#define SDMMC_ERROR_CID_CSD_OVERWRITE 0x00080000U /*!< CID/CSD overwrite error */
+#define SDMMC_ERROR_WP_ERASE_SKIP 0x00100000U /*!< Only partial address space was erased */
+#define SDMMC_ERROR_CARD_ECC_DISABLED 0x00200000U /*!< Command has been executed without using internal ECC */
+#define SDMMC_ERROR_ERASE_RESET 0x00400000U /*!< Erase sequence was cleared before executing because an out
+ of erase sequence command was received */
+#define SDMMC_ERROR_AKE_SEQ_ERR 0x00800000U /*!< Error in sequence of authentication */
+#define SDMMC_ERROR_INVALID_VOLTRANGE 0x01000000U /*!< Error in case of invalid voltage range */
+#define SDMMC_ERROR_ADDR_OUT_OF_RANGE 0x02000000U /*!< Error when addressed block is out of range */
+#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE 0x04000000U /*!< Error when command request is not applicable */
+#define SDMMC_ERROR_INVALID_PARAMETER 0x08000000U /*!< the used parameter is not valid */
+#define SDMMC_ERROR_UNSUPPORTED_FEATURE 0x10000000U /*!< Error when feature is not insupported */
+#define SDMMC_ERROR_BUSY 0x20000000U /*!< Error when transfer process is busy */
+#define SDMMC_ERROR_DMA 0x40000000U /*!< Error while DMA transfer */
+#define SDMMC_ERROR_TIMEOUT 0x80000000U /*!< Timeout error */
/**
* @brief SDMMC Commands Index
*/
-#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0) /*!< Resets the SD memory card. */
-#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1) /*!< Sends host capacity support information and activates the card's initialization process. */
-#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
-#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3) /*!< Asks the card to publish a new relative address (RCA). */
-#define SDMMC_CMD_SET_DSR ((uint8_t)4) /*!< Programs the DSR of all cards. */
-#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
- operating condition register (OCR) content in the response on the CMD line. */
-#define SDMMC_CMD_HS_SWITCH ((uint8_t)6) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
-#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7) /*!< Selects the card by its own relative address and gets deselected by any other address */
-#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
- and asks the card whether card supports voltage. */
-#define SDMMC_CMD_SEND_CSD ((uint8_t)9) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
-#define SDMMC_CMD_SEND_CID ((uint8_t)10) /*!< Addressed card sends its card identification (CID) on the CMD line. */
-#define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /*!< SD card doesn't support it. */
-#define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12) /*!< Forces the card to stop transmission. */
-#define SDMMC_CMD_SEND_STATUS ((uint8_t)13) /*!< Addressed card sends its status register. */
-#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14) /*!< Reserved */
-#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15) /*!< Sends an addressed card into the inactive state. */
-#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16) /*!< Sets the block length (in bytes for SDSC) for all following block commands
+#define SDMMC_CMD_GO_IDLE_STATE 0U /*!< Resets the SD memory card. */
+#define SDMMC_CMD_SEND_OP_COND 1U /*!< Sends host capacity support information and activates the card's initialization process. */
+#define SDMMC_CMD_ALL_SEND_CID 2U /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
+#define SDMMC_CMD_SET_REL_ADDR 3U /*!< Asks the card to publish a new relative address (RCA). */
+#define SDMMC_CMD_SET_DSR 4U /*!< Programs the DSR of all cards. */
+#define SDMMC_CMD_SDMMC_SEN_OP_COND 5U /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
+ operating condition register (OCR) content in the response on the CMD line. */
+#define SDMMC_CMD_HS_SWITCH 6U /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
+#define SDMMC_CMD_SEL_DESEL_CARD 7U /*!< Selects the card by its own relative address and gets deselected by any other address */
+#define SDMMC_CMD_HS_SEND_EXT_CSD 8U /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
+ and asks the card whether card supports voltage. */
+#define SDMMC_CMD_SEND_CSD 9U /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
+#define SDMMC_CMD_SEND_CID 10U /*!< Addressed card sends its card identification (CID) on the CMD line. */
+#define SDMMC_CMD_READ_DAT_UNTIL_STOP 11U /*!< SD card doesn't support it. */
+#define SDMMC_CMD_STOP_TRANSMISSION 12U /*!< Forces the card to stop transmission. */
+#define SDMMC_CMD_SEND_STATUS 13U /*!< Addressed card sends its status register. */
+#define SDMMC_CMD_HS_BUSTEST_READ 14U /*!< Reserved */
+#define SDMMC_CMD_GO_INACTIVE_STATE 15U /*!< Sends an addressed card into the inactive state. */
+#define SDMMC_CMD_SET_BLOCKLEN 16U /*!< Sets the block length (in bytes for SDSC) for all following block commands
(read, write, lock). Default block length is fixed to 512 Bytes. Not effective
for SDHS and SDXC. */
-#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
+#define SDMMC_CMD_READ_SINGLE_BLOCK 17U /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
fixed 512 bytes in case of SDHC and SDXC. */
-#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18) /*!< Continuously transfers data blocks from card to host until interrupted by
+#define SDMMC_CMD_READ_MULT_BLOCK 18U /*!< Continuously transfers data blocks from card to host until interrupted by
STOP_TRANSMISSION command. */
-#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
-#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /*!< Speed class control command. */
-#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23) /*!< Specify block count for CMD18 and CMD25. */
-#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
+#define SDMMC_CMD_HS_BUSTEST_WRITE 19U /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
+#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP 20U /*!< Speed class control command. */
+#define SDMMC_CMD_SET_BLOCK_COUNT 23U /*!< Specify block count for CMD18 and CMD25. */
+#define SDMMC_CMD_WRITE_SINGLE_BLOCK 24U /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
fixed 512 bytes in case of SDHC and SDXC. */
-#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
-#define SDMMC_CMD_PROG_CID ((uint8_t)26) /*!< Reserved for manufacturers. */
-#define SDMMC_CMD_PROG_CSD ((uint8_t)27) /*!< Programming of the programmable bits of the CSD. */
-#define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28) /*!< Sets the write protection bit of the addressed group. */
-#define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29) /*!< Clears the write protection bit of the addressed group. */
-#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30) /*!< Asks the card to send the status of the write protection bits. */
-#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32) /*!< Sets the address of the first write block to be erased. (For SD card only). */
-#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33) /*!< Sets the address of the last write block of the continuous range to be erased. */
-#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35) /*!< Sets the address of the first write block to be erased. Reserved for each command
+#define SDMMC_CMD_WRITE_MULT_BLOCK 25U /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
+#define SDMMC_CMD_PROG_CID 26U /*!< Reserved for manufacturers. */
+#define SDMMC_CMD_PROG_CSD 27U /*!< Programming of the programmable bits of the CSD. */
+#define SDMMC_CMD_SET_WRITE_PROT 28U /*!< Sets the write protection bit of the addressed group. */
+#define SDMMC_CMD_CLR_WRITE_PROT 29U /*!< Clears the write protection bit of the addressed group. */
+#define SDMMC_CMD_SEND_WRITE_PROT 30U /*!< Asks the card to send the status of the write protection bits. */
+#define SDMMC_CMD_SD_ERASE_GRP_START 32U /*!< Sets the address of the first write block to be erased. (For SD card only). */
+#define SDMMC_CMD_SD_ERASE_GRP_END 33U /*!< Sets the address of the last write block of the continuous range to be erased. */
+#define SDMMC_CMD_ERASE_GRP_START 35U /*!< Sets the address of the first write block to be erased. Reserved for each command
system set by switch function command (CMD6). */
-#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36) /*!< Sets the address of the last write block of the continuous range to be erased.
+#define SDMMC_CMD_ERASE_GRP_END 36U /*!< Sets the address of the last write block of the continuous range to be erased.
Reserved for each command system set by switch function command (CMD6). */
-#define SDMMC_CMD_ERASE ((uint8_t)38) /*!< Reserved for SD security applications. */
-#define SDMMC_CMD_FAST_IO ((uint8_t)39) /*!< SD card doesn't support it (Reserved). */
-#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40) /*!< SD card doesn't support it (Reserved). */
-#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
+#define SDMMC_CMD_ERASE 38U /*!< Reserved for SD security applications. */
+#define SDMMC_CMD_FAST_IO 39U /*!< SD card doesn't support it (Reserved). */
+#define SDMMC_CMD_GO_IRQ_STATE 40U /*!< SD card doesn't support it (Reserved). */
+#define SDMMC_CMD_LOCK_UNLOCK 42U /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
the SET_BLOCK_LEN command. */
-#define SDMMC_CMD_APP_CMD ((uint8_t)55) /*!< Indicates to the card that the next command is an application specific command rather
+#define SDMMC_CMD_APP_CMD 55U /*!< Indicates to the card that the next command is an application specific command rather
than a standard command. */
-#define SDMMC_CMD_GEN_CMD ((uint8_t)56) /*!< Used either to transfer a data block to the card or to get a data block from the card
+#define SDMMC_CMD_GEN_CMD 56U /*!< Used either to transfer a data block to the card or to get a data block from the card
for general purpose/application specific commands. */
-#define SDMMC_CMD_NO_CMD ((uint8_t)64) /*!< No command */
+#define SDMMC_CMD_NO_CMD 64U /*!< No command */
/**
* @brief Following commands are SD Card Specific commands.
* SDMMC_APP_CMD should be sent before sending these commands.
*/
-#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
+#define SDMMC_CMD_APP_SD_SET_BUSWIDTH 6U /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
widths are given in SCR register. */
-#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13) /*!< (ACMD13) Sends the SD status. */
-#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
+#define SDMMC_CMD_SD_APP_STATUS 13U /*!< (ACMD13) Sends the SD status. */
+#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS 22U /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
32bit+CRC data block. */
-#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
+#define SDMMC_CMD_SD_APP_OP_COND 41U /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
send its operating condition register (OCR) content in the response on the CMD line. */
-#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */
-#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51) /*!< Reads the SD Configuration Register (SCR). */
-#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52) /*!< For SD I/O card only, reserved for security specification. */
-#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53) /*!< For SD I/O card only, reserved for security specification. */
+#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT 42U /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */
+#define SDMMC_CMD_SD_APP_SEND_SCR 51U /*!< Reads the SD Configuration Register (SCR). */
+#define SDMMC_CMD_SDMMC_RW_DIRECT 52U /*!< For SD I/O card only, reserved for security specification. */
+#define SDMMC_CMD_SDMMC_RW_EXTENDED 53U /*!< For SD I/O card only, reserved for security specification. */
/**
* @brief Following commands are SD Card Specific security commands.
* SDMMC_CMD_APP_CMD should be sent before sending these commands.
*/
-#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43)
-#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44)
-#define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45)
-#define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46)
-#define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47)
-#define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48)
-#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18)
-#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25)
-#define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38)
-#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49)
-#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48)
+#define SDMMC_CMD_SD_APP_GET_MKB 43U
+#define SDMMC_CMD_SD_APP_GET_MID 44U
+#define SDMMC_CMD_SD_APP_SET_CER_RN1 45U
+#define SDMMC_CMD_SD_APP_GET_CER_RN2 46U
+#define SDMMC_CMD_SD_APP_SET_CER_RES2 47U
+#define SDMMC_CMD_SD_APP_GET_CER_RES1 48U
+#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK 18U
+#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK 25U
+#define SDMMC_CMD_SD_APP_SECURE_ERASE 38U
+#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA 49U
+#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB 48U
/**
* @brief Masks for errors Card Status R1 (OCR Register)
*/
-#define SDMMC_OCR_ADDR_OUT_OF_RANGE 0x80000000U
-#define SDMMC_OCR_ADDR_MISALIGNED 0x40000000U
-#define SDMMC_OCR_BLOCK_LEN_ERR 0x20000000U
-#define SDMMC_OCR_ERASE_SEQ_ERR 0x10000000U
-#define SDMMC_OCR_BAD_ERASE_PARAM 0x08000000U
-#define SDMMC_OCR_WRITE_PROT_VIOLATION 0x04000000U
-#define SDMMC_OCR_LOCK_UNLOCK_FAILED 0x01000000U
-#define SDMMC_OCR_COM_CRC_FAILED 0x00800000U
-#define SDMMC_OCR_ILLEGAL_CMD 0x00400000U
-#define SDMMC_OCR_CARD_ECC_FAILED 0x00200000U
-#define SDMMC_OCR_CC_ERROR 0x00100000U
-#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR 0x00080000U
-#define SDMMC_OCR_STREAM_READ_UNDERRUN 0x00040000U
-#define SDMMC_OCR_STREAM_WRITE_OVERRUN 0x00020000U
-#define SDMMC_OCR_CID_CSD_OVERWRITE 0x00010000U
-#define SDMMC_OCR_WP_ERASE_SKIP 0x00008000U
-#define SDMMC_OCR_CARD_ECC_DISABLED 0x00004000U
-#define SDMMC_OCR_ERASE_RESET 0x00002000U
-#define SDMMC_OCR_AKE_SEQ_ERROR 0x00000008U
-#define SDMMC_OCR_ERRORBITS 0xFDFFE008U
+#define SDMMC_OCR_ADDR_OUT_OF_RANGE 0x80000000U
+#define SDMMC_OCR_ADDR_MISALIGNED 0x40000000U
+#define SDMMC_OCR_BLOCK_LEN_ERR 0x20000000U
+#define SDMMC_OCR_ERASE_SEQ_ERR 0x10000000U
+#define SDMMC_OCR_BAD_ERASE_PARAM 0x08000000U
+#define SDMMC_OCR_WRITE_PROT_VIOLATION 0x04000000U
+#define SDMMC_OCR_LOCK_UNLOCK_FAILED 0x01000000U
+#define SDMMC_OCR_COM_CRC_FAILED 0x00800000U
+#define SDMMC_OCR_ILLEGAL_CMD 0x00400000U
+#define SDMMC_OCR_CARD_ECC_FAILED 0x00200000U
+#define SDMMC_OCR_CC_ERROR 0x00100000U
+#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR 0x00080000U
+#define SDMMC_OCR_STREAM_READ_UNDERRUN 0x00040000U
+#define SDMMC_OCR_STREAM_WRITE_OVERRUN 0x00020000U
+#define SDMMC_OCR_CID_CSD_OVERWRITE 0x00010000U
+#define SDMMC_OCR_WP_ERASE_SKIP 0x00008000U
+#define SDMMC_OCR_CARD_ECC_DISABLED 0x00004000U
+#define SDMMC_OCR_ERASE_RESET 0x00002000U
+#define SDMMC_OCR_AKE_SEQ_ERROR 0x00000008U
+#define SDMMC_OCR_ERRORBITS 0xFDFFE008U
/**
* @brief Masks for R6 Response
*/
-#define SDMMC_R6_GENERAL_UNKNOWN_ERROR 0x00002000U
-#define SDMMC_R6_ILLEGAL_CMD 0x00004000U
-#define SDMMC_R6_COM_CRC_FAILED 0x00008000U
+#define SDMMC_R6_GENERAL_UNKNOWN_ERROR 0x00002000U
+#define SDMMC_R6_ILLEGAL_CMD 0x00004000U
+#define SDMMC_R6_COM_CRC_FAILED 0x00008000U
-#define SDMMC_VOLTAGE_WINDOW_SD 0x80100000U
-#define SDMMC_HIGH_CAPACITY 0x40000000U
-#define SDMMC_STD_CAPACITY 0x00000000U
-#define SDMMC_CHECK_PATTERN 0x000001AAU
+#define SDMMC_VOLTAGE_WINDOW_SD 0x80100000U
+#define SDMMC_HIGH_CAPACITY 0x40000000U
+#define SDMMC_STD_CAPACITY 0x00000000U
+#define SDMMC_CHECK_PATTERN 0x000001AAU
+#define SD_SWITCH_1_8V_CAPACITY 0x01000000U
-#define SDMMC_MAX_VOLT_TRIAL 0x0000FFFFU
-
-#define SDMMC_MAX_TRIAL 0x0000FFFFU
-
-#define SDMMC_ALLZERO 0x00000000U
+#define SDMMC_MAX_VOLT_TRIAL 0x0000FFFFU
+
+#define SDMMC_MAX_TRIAL 0x0000FFFFU
+
+#define SDMMC_ALLZERO 0x00000000U
-#define SDMMC_WIDE_BUS_SUPPORT 0x00040000U
-#define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U
-#define SDMMC_CARD_LOCKED 0x02000000U
+#define SDMMC_WIDE_BUS_SUPPORT 0x00040000U
+#define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U
+#define SDMMC_CARD_LOCKED 0x02000000U
-#define SDMMC_DATATIMEOUT 0xFFFFFFFFU
+#ifndef SDMMC_DATATIMEOUT
+#define SDMMC_DATATIMEOUT 0xFFFFFFFFU
+#endif /* SDMMC_DATATIMEOUT */
-#define SDMMC_0TO7BITS 0x000000FFU
-#define SDMMC_8TO15BITS 0x0000FF00U
-#define SDMMC_16TO23BITS 0x00FF0000U
-#define SDMMC_24TO31BITS 0xFF000000U
-#define SDMMC_MAX_DATA_LENGTH 0x01FFFFFFU
+#define SDMMC_0TO7BITS 0x000000FFU
+#define SDMMC_8TO15BITS 0x0000FF00U
+#define SDMMC_16TO23BITS 0x00FF0000U
+#define SDMMC_24TO31BITS 0xFF000000U
+#define SDMMC_MAX_DATA_LENGTH 0x01FFFFFFU
-#define SDMMC_HALFFIFO 0x00000008U
-#define SDMMC_HALFFIFOBYTES 0x00000020U
+#define SDMMC_HALFFIFO 0x00000008U
+#define SDMMC_HALFFIFOBYTES 0x00000020U
/**
* @brief Command Class supported
*/
-#define SDIO_CCCC_ERASE 0x00000020U
-
-#define SDIO_CMDTIMEOUT 5000U /* Command send and response timeout */
-#define SDIO_MAXERASETIMEOUT 63000U /* Max erase Timeout 63 s */
+#define SDIO_CCCC_ERASE 0x00000020U
+#define SDIO_CMDTIMEOUT 5000U /* Command send and response timeout */
+#define SDIO_MAXERASETIMEOUT 63000U /* Max erase Timeout 63 s */
+#define SDIO_STOPTRANSFERTIMEOUT 100000000U /* Timeout for STOP TRANSMISSION command */
/** @defgroup SDIO_LL_Clock_Edge Clock Edge
* @{
@@ -331,7 +330,7 @@ typedef struct
#define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE
#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
- ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
+ ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
/**
* @}
*/
@@ -343,7 +342,7 @@ typedef struct
#define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS
#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
- ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
+ ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
/**
* @}
*/
@@ -355,7 +354,7 @@ typedef struct
#define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV
#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
- ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
+ ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
/**
* @}
*/
@@ -368,8 +367,8 @@ typedef struct
#define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1
#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
- ((WIDE) == SDIO_BUS_WIDE_4B) || \
- ((WIDE) == SDIO_BUS_WIDE_8B))
+ ((WIDE) == SDIO_BUS_WIDE_4B) || \
+ ((WIDE) == SDIO_BUS_WIDE_8B))
/**
* @}
*/
@@ -381,7 +380,7 @@ typedef struct
#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN
#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
- ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
+ ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
/**
* @}
*/
@@ -410,8 +409,8 @@ typedef struct
#define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP
#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \
- ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
- ((RESPONSE) == SDIO_RESPONSE_LONG))
+ ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
+ ((RESPONSE) == SDIO_RESPONSE_LONG))
/**
* @}
*/
@@ -424,8 +423,8 @@ typedef struct
#define SDIO_WAIT_PEND SDIO_CMD_WAITPEND
#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
- ((WAIT) == SDIO_WAIT_IT) || \
- ((WAIT) == SDIO_WAIT_PEND))
+ ((WAIT) == SDIO_WAIT_IT) || \
+ ((WAIT) == SDIO_WAIT_PEND))
/**
* @}
*/
@@ -437,7 +436,7 @@ typedef struct
#define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN
#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
- ((CPSM) == SDIO_CPSM_ENABLE))
+ ((CPSM) == SDIO_CPSM_ENABLE))
/**
* @}
*/
@@ -451,14 +450,14 @@ typedef struct
#define SDIO_RESP4 0x0000000CU
#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
- ((RESP) == SDIO_RESP2) || \
- ((RESP) == SDIO_RESP3) || \
- ((RESP) == SDIO_RESP4))
+ ((RESP) == SDIO_RESP2) || \
+ ((RESP) == SDIO_RESP3) || \
+ ((RESP) == SDIO_RESP4))
/**
* @}
*/
-/** @defgroup SDIO_LL_Data_Length Data Lenght
+/** @defgroup SDIO_LL_Data_Length Data Length
* @{
*/
#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
@@ -486,20 +485,20 @@ typedef struct
#define SDIO_DATABLOCK_SIZE_16384B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
+ ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
/**
* @}
*/
@@ -508,10 +507,10 @@ typedef struct
* @{
*/
#define SDIO_TRANSFER_DIR_TO_CARD 0x00000000U
-#define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR
+#define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR
#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
- ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
+ ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
/**
* @}
*/
@@ -523,7 +522,7 @@ typedef struct
#define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE
#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
- ((MODE) == SDIO_TRANSFER_MODE_STREAM))
+ ((MODE) == SDIO_TRANSFER_MODE_STREAM))
/**
* @}
*/
@@ -535,7 +534,7 @@ typedef struct
#define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN
#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
- ((DPSM) == SDIO_DPSM_ENABLE))
+ ((DPSM) == SDIO_DPSM_ENABLE))
/**
* @}
*/
@@ -547,7 +546,7 @@ typedef struct
#define SDIO_READ_WAIT_MODE_CLK (SDIO_DCTRL_RWMOD)
#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
- ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
+ ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
/**
* @}
*/
@@ -555,30 +554,34 @@ typedef struct
/** @defgroup SDIO_LL_Interrupt_sources Interrupt Sources
* @{
*/
-#define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL
-#define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL
-#define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT
-#define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT
-#define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR
-#define SDIO_IT_RXOVERR SDIO_STA_RXOVERR
-#define SDIO_IT_CMDREND SDIO_STA_CMDREND
-#define SDIO_IT_CMDSENT SDIO_STA_CMDSENT
-#define SDIO_IT_DATAEND SDIO_STA_DATAEND
-#define SDIO_IT_STBITERR SDIO_STA_STBITERR
-#define SDIO_IT_DBCKEND SDIO_STA_DBCKEND
-#define SDIO_IT_CMDACT SDIO_STA_CMDACT
-#define SDIO_IT_TXACT SDIO_STA_TXACT
-#define SDIO_IT_RXACT SDIO_STA_RXACT
-#define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE
-#define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF
-#define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF
-#define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF
-#define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE
-#define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE
-#define SDIO_IT_TXDAVL SDIO_STA_TXDAVL
-#define SDIO_IT_RXDAVL SDIO_STA_RXDAVL
-#define SDIO_IT_SDIOIT SDIO_STA_SDIOIT
-#define SDIO_IT_CEATAEND SDIO_STA_CEATAEND
+#define SDIO_IT_CCRCFAIL SDIO_MASK_CCRCFAILIE
+#define SDIO_IT_DCRCFAIL SDIO_MASK_DCRCFAILIE
+#define SDIO_IT_CTIMEOUT SDIO_MASK_CTIMEOUTIE
+#define SDIO_IT_DTIMEOUT SDIO_MASK_DTIMEOUTIE
+#define SDIO_IT_TXUNDERR SDIO_MASK_TXUNDERRIE
+#define SDIO_IT_RXOVERR SDIO_MASK_RXOVERRIE
+#define SDIO_IT_CMDREND SDIO_MASK_CMDRENDIE
+#define SDIO_IT_CMDSENT SDIO_MASK_CMDSENTIE
+#define SDIO_IT_DATAEND SDIO_MASK_DATAENDIE
+#if defined(SDIO_STA_STBITERR)
+#define SDIO_IT_STBITERR SDIO_MASK_STBITERRIE
+#endif
+#define SDIO_IT_DBCKEND SDIO_MASK_DBCKENDIE
+#define SDIO_IT_CMDACT SDIO_MASK_CMDACTIE
+#define SDIO_IT_TXACT SDIO_MASK_TXACTIE
+#define SDIO_IT_RXACT SDIO_MASK_RXACTIE
+#define SDIO_IT_TXFIFOHE SDIO_MASK_TXFIFOHEIE
+#define SDIO_IT_RXFIFOHF SDIO_MASK_RXFIFOHFIE
+#define SDIO_IT_TXFIFOF SDIO_MASK_TXFIFOFIE
+#define SDIO_IT_RXFIFOF SDIO_MASK_RXFIFOFIE
+#define SDIO_IT_TXFIFOE SDIO_MASK_TXFIFOEIE
+#define SDIO_IT_RXFIFOE SDIO_MASK_RXFIFOEIE
+#define SDIO_IT_TXDAVL SDIO_MASK_TXDAVLIE
+#define SDIO_IT_RXDAVL SDIO_MASK_RXDAVLIE
+#define SDIO_IT_SDIOIT SDIO_MASK_SDIOITIE
+#if defined(SDIO_CMD_CEATACMD)
+#define SDIO_IT_CEATAEND SDIO_MASK_CEATAENDIE
+#endif
/**
* @}
*/
@@ -595,7 +598,9 @@ typedef struct
#define SDIO_FLAG_CMDREND SDIO_STA_CMDREND
#define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT
#define SDIO_FLAG_DATAEND SDIO_STA_DATAEND
+#if defined(SDIO_STA_STBITERR)
#define SDIO_FLAG_STBITERR SDIO_STA_STBITERR
+#endif
#define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND
#define SDIO_FLAG_CMDACT SDIO_STA_CMDACT
#define SDIO_FLAG_TXACT SDIO_STA_TXACT
@@ -609,11 +614,19 @@ typedef struct
#define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL
#define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL
#define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT
+#if defined(SDIO_CMD_CEATACMD)
#define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND
+#endif
#define SDIO_STATIC_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\
SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR |\
SDIO_FLAG_CMDREND | SDIO_FLAG_CMDSENT | SDIO_FLAG_DATAEND |\
- SDIO_FLAG_DBCKEND))
+ SDIO_FLAG_DBCKEND | SDIO_FLAG_SDIOIT))
+
+#define SDIO_STATIC_CMD_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CTIMEOUT | SDIO_FLAG_CMDREND |\
+ SDIO_FLAG_CMDSENT))
+
+#define SDIO_STATIC_DATA_FLAGS ((uint32_t)(SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR |\
+ SDIO_FLAG_RXOVERR | SDIO_FLAG_DATAEND | SDIO_FLAG_DBCKEND))
/**
* @}
*/
@@ -705,11 +718,10 @@ typedef struct
SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND))
/* SDIO Initialization Frequency (400KHz max) */
-#define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
+#define SDIO_INIT_CLK_DIV ((uint8_t)0x76) /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */
/* SDIO Data Transfer Frequency (25MHz max) */
-#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)
-
+#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0) /* 48MHz / (SDMMC_TRANSFER_CLK_DIV + 2) < 25MHz */
/**
* @}
*/
@@ -721,35 +733,36 @@ typedef struct
/**
* @brief Enable the SDIO device.
- * @param __INSTANCE__ SDIO Instance
+ * @param __INSTANCE__: SDIO Instance
* @retval None
- */
+ */
#define __SDIO_ENABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
/**
* @brief Disable the SDIO device.
- * @param __INSTANCE__ SDIO Instance
+ * @param __INSTANCE__: SDIO Instance
* @retval None
*/
#define __SDIO_DISABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
/**
* @brief Enable the SDIO DMA transfer.
- * @param __INSTANCE__ SDIO Instance
+ * @param __INSTANCE__: SDIO Instance
* @retval None
- */
+ */
#define __SDIO_DMA_ENABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
+
/**
* @brief Disable the SDIO DMA transfer.
- * @param __INSTANCE__ SDIO Instance
+ * @param __INSTANCE__: SDIO Instance
* @retval None
*/
#define __SDIO_DMA_DISABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
/**
* @brief Enable the SDIO device interrupt.
- * @param __INSTANCE__ Pointer to SDIO register base
- * @param __INTERRUPT__ specifies the SDIO interrupt sources to be enabled.
+ * @param __INSTANCE__ : Pointer to SDIO register base
+ * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -759,7 +772,7 @@ typedef struct
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
@@ -772,15 +785,15 @@ typedef struct
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
* @retval None
*/
#define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
/**
* @brief Disable the SDIO device interrupt.
- * @param __INSTANCE__ Pointer to SDIO register base
- * @param __INTERRUPT__ specifies the SDIO interrupt sources to be disabled.
+ * @param __INSTANCE__ : Pointer to SDIO register base
+ * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -790,7 +803,7 @@ typedef struct
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
@@ -803,15 +816,15 @@ typedef struct
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
* @retval None
*/
#define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
/**
* @brief Checks whether the specified SDIO flag is set or not.
- * @param __INSTANCE__ Pointer to SDIO register base
- * @param __FLAG__ specifies the flag to check.
+ * @param __INSTANCE__ : Pointer to SDIO register base
+ * @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
@@ -821,7 +834,7 @@ typedef struct
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDIO_FLAG_CMDACT: Command transfer in progress
* @arg SDIO_FLAG_TXACT: Data transmit in progress
@@ -834,16 +847,16 @@ typedef struct
* @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
- * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
+ * @arg SDIO_FLAG_SDIOIT: SDIO interrupt received
* @retval The new state of SDIO_FLAG (SET or RESET).
*/
-#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
+#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U)
/**
* @brief Clears the SDIO pending flags.
- * @param __INSTANCE__ Pointer to SDIO register base
- * @param __FLAG__ specifies the flag to clear.
+ * @param __INSTANCE__ : Pointer to SDIO register base
+ * @param __FLAG__: specifies the flag to clear.
* This parameter can be one or a combination of the following values:
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
@@ -853,17 +866,17 @@ typedef struct
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
+ * @arg SDIO_FLAG_SDIOIT: SDIO interrupt received
* @retval None
*/
#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
/**
* @brief Checks whether the specified SDIO interrupt has occurred or not.
- * @param __INSTANCE__ Pointer to SDIO register base
- * @param __INTERRUPT__ specifies the SDIO interrupt source to check.
+ * @param __INSTANCE__ : Pointer to SDIO register base
+ * @param __INTERRUPT__: specifies the SDIO interrupt source to check.
* This parameter can be one of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -873,7 +886,7 @@ typedef struct
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
@@ -886,15 +899,15 @@ typedef struct
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
* @retval The new state of SDIO_IT (SET or RESET).
*/
#define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
/**
* @brief Clears the SDIO's interrupt pending bits.
- * @param __INSTANCE__ Pointer to SDIO register base
- * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * @param __INSTANCE__ : Pointer to SDIO register base
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -904,71 +917,69 @@ typedef struct
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
+ * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
* @retval None
*/
#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
/**
* @brief Enable Start the SD I/O Read Wait operation.
- * @param __INSTANCE__ Pointer to SDIO register base
+ * @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
- */
+ */
#define __SDIO_START_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
/**
* @brief Disable Start the SD I/O Read Wait operations.
- * @param __INSTANCE__ Pointer to SDIO register base
+ * @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
- */
+ */
#define __SDIO_START_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
/**
* @brief Enable Start the SD I/O Read Wait operation.
- * @param __INSTANCE__ Pointer to SDIO register base
+ * @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
- */
+ */
#define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
/**
* @brief Disable Stop the SD I/O Read Wait operations.
- * @param __INSTANCE__ Pointer to SDIO register base
+ * @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
- */
+ */
#define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
/**
* @brief Enable the SD I/O Mode Operation.
- * @param __INSTANCE__ Pointer to SDIO register base
+ * @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
- */
+ */
#define __SDIO_OPERATION_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
/**
* @brief Disable the SD I/O Mode Operation.
- * @param __INSTANCE__ Pointer to SDIO register base
+ * @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
- */
+ */
#define __SDIO_OPERATION_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
/**
* @brief Enable the SD I/O Suspend command sending.
- * @param __INSTANCE__ Pointer to SDIO register base
+ * @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
- */
+ */
#define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
/**
* @brief Disable the SD I/O Suspend command sending.
- * @param __INSTANCE__ Pointer to SDIO register base
+ * @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
- */
+ */
#define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+
+#if defined(SDIO_CMD_CEATACMD)
/**
* @brief Enable the command completion signal.
* @retval None
@@ -1004,9 +1015,8 @@ typedef struct
* @retval None
*/
#define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE ||\
- STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
-
+
+#endif
/**
* @}
*/
@@ -1066,7 +1076,9 @@ uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
+uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
+uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx);
uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx);
@@ -1074,19 +1086,17 @@ uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr);
uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx);
uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx);
uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument);
-uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t SdType);
+uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t Argument);
uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth);
uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx);
uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx);
uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument);
+uint32_t SDMMC_CmdSendEXTCSD(SDIO_TypeDef *SDIOx, uint32_t Argument);
uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA);
uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument);
uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx);
-
uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument);
uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument);
-uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
-uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
/**
* @}
@@ -1104,14 +1114,12 @@ uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
- STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
- STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+#endif /* SDIO */
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F4xx_LL_SDMMC_H */
+#endif /* STM32F4xx_LL_SDMMC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_spi.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_spi.h
index 13d1883af3..ec61b36e7f 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_spi.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_spi.h
@@ -710,8 +710,8 @@ __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
*/
__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
{
- register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
- register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
+ uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
+ uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
return (Ssm | Ssoe);
}
@@ -1056,7 +1056,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
{
- return (uint32_t) & (SPIx->DR);
+ return (uint32_t) &(SPIx->DR);
}
/**
@@ -1103,7 +1103,7 @@ __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
*spidr = TxData;
#else
*((__IO uint8_t *)&SPIx->DR) = TxData;
-#endif
+#endif /* __GNUC__ */
}
/**
@@ -1120,7 +1120,7 @@ __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
*spidr = TxData;
#else
SPIx->DR = TxData;
-#endif
+#endif /* __GNUC__ */
}
/**
@@ -1242,10 +1242,10 @@ typedef struct
/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
* @{
*/
-#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */
-#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */
-#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */
-#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */
+#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel length 16bit */
+#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel length 32bit */
+#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel length 32bit */
+#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel length 32bit */
/**
* @}
*/
@@ -1580,7 +1580,7 @@ __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
}
/**
- * @brief Enable the master clock ouput (Pin MCK)
+ * @brief Enable the master clock output (Pin MCK)
* @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
* @param SPIx SPI Instance
* @retval None
@@ -1591,7 +1591,7 @@ __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
}
/**
- * @brief Disable the master clock ouput (Pin MCK)
+ * @brief Disable the master clock output (Pin MCK)
* @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
* @param SPIx SPI Instance
* @retval None
@@ -1602,7 +1602,7 @@ __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
}
/**
- * @brief Check if the master clock ouput (Pin MCK) is enabled
+ * @brief Check if the master clock output (Pin MCK) is enabled
* @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h
index fcdfd6e461..e9b0b74268 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h
@@ -147,12 +147,12 @@ static const uint8_t SHIFT_TAB_OISx[] =
* @retval none
*/
#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
-(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
+ (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
/** @brief Calculate the deadtime sampling period(in ps).
* @param __TIMCLK__ timer input clock frequency (in Hz).
@@ -163,9 +163,9 @@ static const uint8_t SHIFT_TAB_OISx[] =
* @retval none
*/
#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
- (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
- ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
- ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
+ (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
+ ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
+ ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
/**
* @}
*/
@@ -204,13 +204,14 @@ typedef struct
This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
- uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
+ uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
reaches zero, an update event is generated and counting restarts
from the RCR value (N).
This means in PWM mode that (N+1) corresponds to:
- the number of PWM periods in edge-aligned mode
- the number of half PWM period in center-aligned mode
- This parameter must be a number between 0x00 and 0xFF.
+ GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+ Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
} LL_TIM_InitTypeDef;
@@ -507,8 +508,8 @@ typedef struct
/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
* @{
*/
-#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */
-#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */
+#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
+#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
/**
* @}
*/
@@ -518,8 +519,8 @@ typedef struct
*/
#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
- (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
- (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
- 0U)
+ ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
+ (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
+ (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
+ (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
+ 0U)
/**
* @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
@@ -968,7 +992,7 @@ typedef struct
* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
- (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
+ (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
/**
* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
@@ -979,7 +1003,7 @@ typedef struct
* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
- ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
+ ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
/**
* @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
@@ -990,8 +1014,8 @@ typedef struct
* @retval Compare value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
-((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
- / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+ ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
+ / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
/**
* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
@@ -1003,8 +1027,8 @@ typedef struct
* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
- ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
- + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
+ ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
+ + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
/**
* @brief HELPER macro retrieving the ratio of the input capture prescaler
@@ -1017,7 +1041,7 @@ typedef struct
* @retval Input capture prescaler ratio (1, 2, 4 or 8)
*/
#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
- ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
+ ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
/**
@@ -1166,7 +1190,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
/**
* @brief Set the timer counter counting mode.
- * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+ * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
* check whether or not the counter mode selection feature is supported
* by a timer instance.
* @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
@@ -1190,7 +1214,7 @@ __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMo
/**
* @brief Get actual counter mode.
- * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+ * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
* check whether or not the counter mode selection feature is supported
* by a timer instance.
* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
@@ -1205,7 +1229,16 @@ __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMo
*/
__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
{
- return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));
+ uint32_t counter_mode;
+
+ counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
+
+ if (counter_mode == 0U)
+ {
+ counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+ }
+
+ return counter_mode;
}
/**
@@ -1227,7 +1260,7 @@ __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
{
- CLEAR_BIT(TIMx->CR1,TIM_CR1_ARPE);
+ CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
}
/**
@@ -1243,7 +1276,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
/**
* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
- * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
* whether or not the clock division feature is supported by the timer
* instance.
* @rmtoll CR1 CKD LL_TIM_SetClockDivision
@@ -1261,7 +1294,7 @@ __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDi
/**
* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
- * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
* whether or not the clock division feature is supported by the timer
* instance.
* @rmtoll CR1 CKD LL_TIM_GetClockDivision
@@ -1278,7 +1311,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
/**
* @brief Set the counter value.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @rmtoll CNT CNT LL_TIM_SetCounter
* @param TIMx Timer instance
@@ -1292,7 +1325,7 @@ __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
/**
* @brief Get the counter value.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @rmtoll CNT CNT LL_TIM_GetCounter
* @param TIMx Timer instance
@@ -1346,7 +1379,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
/**
* @brief Set the auto-reload value.
* @note The counter is blocked while the auto-reload value is null.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
* @rmtoll ARR ARR LL_TIM_SetAutoReload
@@ -1362,7 +1395,7 @@ __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload
/**
* @brief Get the auto-reload value.
* @rmtoll ARR ARR LL_TIM_GetAutoReload
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @param TIMx Timer instance
* @retval Auto-reload value
@@ -1374,11 +1407,11 @@ __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
/**
* @brief Set the repetition counter value.
- * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a repetition counter.
* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
* @param TIMx Timer instance
- * @param RepetitionCounter between Min_Data=0 and Max_Data=255
+ * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
@@ -1388,7 +1421,7 @@ __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t Rep
/**
* @brief Get the repetition counter value.
- * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a repetition counter.
* @rmtoll RCR REP LL_TIM_GetRepetitionCounter
* @param TIMx Timer instance
@@ -1411,7 +1444,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
* @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
* they are updated only when a commutation event (COM) occurs.
* @note Only on channels that have a complementary output.
- * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* whether or not a timer instance is able to generate a commutation event.
* @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
* @param TIMx Timer instance
@@ -1424,7 +1457,7 @@ __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
/**
* @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
- * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* whether or not a timer instance is able to generate a commutation event.
* @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
* @param TIMx Timer instance
@@ -1437,7 +1470,7 @@ __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
/**
* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
- * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* whether or not a timer instance is able to generate a commutation event.
* @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
* @param TIMx Timer instance
@@ -1481,7 +1514,7 @@ __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
/**
* @brief Set the lock level to freeze the
* configuration of several capture/compare parameters.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* the lock mechanism is supported by a timer instance.
* @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
* @param TIMx Timer instance
@@ -1606,8 +1639,8 @@ __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t
*/
__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
@@ -1641,8 +1674,8 @@ __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel,
*/
__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
}
@@ -1670,8 +1703,8 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
}
@@ -1700,7 +1733,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
*/
__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
}
@@ -1728,14 +1761,14 @@ __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel,
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
}
/**
* @brief Set the IDLE state of an output channel
* @note This function is significant only for the timer instances
- * supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
+ * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
* can be used to check whether or not a timer instance provides
* a break input.
* @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
@@ -1761,7 +1794,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Chann
*/
__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
}
@@ -1789,7 +1822,7 @@ __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel,
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
}
@@ -1810,8 +1843,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Chan
*/
__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -1832,8 +1865,8 @@ __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
*/
__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -1854,9 +1887,9 @@ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
*/
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
@@ -1876,8 +1909,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Cha
*/
__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -1897,8 +1930,8 @@ __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel
*/
__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -1918,16 +1951,16 @@ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channe
*/
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
/**
* @brief Enable clearing the output channel on an external event.
* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
- * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
* or not a timer instance can clear the OCxREF signal on an external event.
* @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
* CCMR1 OC2CE LL_TIM_OC_EnableClear\n
@@ -1943,14 +1976,14 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t
*/
__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
}
/**
* @brief Disable clearing the output channel on an external event.
- * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
* or not a timer instance can clear the OCxREF signal on an external event.
* @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
* CCMR1 OC2CE LL_TIM_OC_DisableClear\n
@@ -1966,8 +1999,8 @@ __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
*/
__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -1975,7 +2008,7 @@ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
* @brief Indicates clearing the output channel on an external event is enabled for the output channel.
* @note This function enables clearing the output channel on an external event.
* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
- * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
* or not a timer instance can clear the OCxREF signal on an external event.
* @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
* CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
@@ -1991,15 +2024,15 @@ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
*/
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
/**
* @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* dead-time insertion feature is supported by a timer instance.
* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
* @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
@@ -2015,9 +2048,9 @@ __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
/**
* @brief Set compare value for output channel 1 (TIMx_CCR1).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
* output channel 1 is supported by a timer instance.
* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
* @param TIMx Timer instance
@@ -2032,9 +2065,9 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t Compare
/**
* @brief Set compare value for output channel 2 (TIMx_CCR2).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
* output channel 2 is supported by a timer instance.
* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
* @param TIMx Timer instance
@@ -2049,9 +2082,9 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t Compare
/**
* @brief Set compare value for output channel 3 (TIMx_CCR3).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
* output channel is supported by a timer instance.
* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
* @param TIMx Timer instance
@@ -2066,9 +2099,9 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t Compare
/**
* @brief Set compare value for output channel 4 (TIMx_CCR4).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
* output channel 4 is supported by a timer instance.
* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
* @param TIMx Timer instance
@@ -2083,9 +2116,9 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t Compare
/**
* @brief Get compare value (TIMx_CCR1) set for output channel 1.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
* output channel 1 is supported by a timer instance.
* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
* @param TIMx Timer instance
@@ -2099,9 +2132,9 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
/**
* @brief Get compare value (TIMx_CCR2) set for output channel 2.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
* output channel 2 is supported by a timer instance.
* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
* @param TIMx Timer instance
@@ -2115,9 +2148,9 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
/**
* @brief Get compare value (TIMx_CCR3) set for output channel 3.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
* output channel 3 is supported by a timer instance.
* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
* @param TIMx Timer instance
@@ -2131,9 +2164,9 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
/**
* @brief Get compare value (TIMx_CCR4) set for output channel 4.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
* output channel 4 is supported by a timer instance.
* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
* @param TIMx Timer instance
@@ -2188,8 +2221,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
@@ -2216,8 +2249,8 @@ __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint3
*/
__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
@@ -2240,8 +2273,8 @@ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channe
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@@ -2266,8 +2299,8 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Ch
*/
__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
@@ -2291,8 +2324,8 @@ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel,
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@@ -2329,8 +2362,8 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Chan
*/
__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
@@ -2366,8 +2399,8 @@ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, ui
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@@ -2395,7 +2428,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel
*/
__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
ICPolarity << SHIFT_TAB_CCxP[iChannel]);
}
@@ -2423,14 +2456,14 @@ __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel,
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
SHIFT_TAB_CCxP[iChannel]);
}
/**
* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
- * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an XOR input.
* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
* @param TIMx Timer instance
@@ -2443,7 +2476,7 @@ __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
/**
* @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
- * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an XOR input.
* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
* @param TIMx Timer instance
@@ -2456,7 +2489,7 @@ __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
/**
* @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
- * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an XOR input.
* @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
* @param TIMx Timer instance
@@ -2470,9 +2503,9 @@ __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
/**
* @brief Get captured value for input channel 1.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
* input channel 1 is supported by a timer instance.
* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
* @param TIMx Timer instance
@@ -2486,9 +2519,9 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
/**
* @brief Get captured value for input channel 2.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
* input channel 2 is supported by a timer instance.
* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
* @param TIMx Timer instance
@@ -2502,9 +2535,9 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
/**
* @brief Get captured value for input channel 3.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
* input channel 3 is supported by a timer instance.
* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
* @param TIMx Timer instance
@@ -2518,9 +2551,9 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
/**
* @brief Get captured value for input channel 4.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
* input channel 4 is supported by a timer instance.
* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
* @param TIMx Timer instance
@@ -2541,7 +2574,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
/**
* @brief Enable external clock mode 2.
* @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
- * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR ECE LL_TIM_EnableExternalClock
* @param TIMx Timer instance
@@ -2554,7 +2587,7 @@ __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
/**
* @brief Disable external clock mode 2.
- * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR ECE LL_TIM_DisableExternalClock
* @param TIMx Timer instance
@@ -2567,7 +2600,7 @@ __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
/**
* @brief Indicate whether external clock mode 2 is enabled.
- * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
* @param TIMx Timer instance
@@ -2584,9 +2617,9 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
* the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
* function. This timer input must be configured by calling
* the @ref LL_TIM_IC_Config() function.
- * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode1.
- * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
* SMCR ECE LL_TIM_SetClockSource
@@ -2604,7 +2637,7 @@ __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSour
/**
* @brief Set the encoder interface mode.
- * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports the encoder mode.
* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
* @param TIMx Timer instance
@@ -2628,7 +2661,7 @@ __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMo
*/
/**
* @brief Set the trigger output (TRGO) used for timer synchronization .
- * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance can operate as a master timer.
* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
* @param TIMx Timer instance
@@ -2650,7 +2683,7 @@ __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSy
/**
* @brief Set the synchronization mode of a slave timer.
- * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
* @param TIMx Timer instance
@@ -2668,7 +2701,7 @@ __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
/**
* @brief Set the selects the trigger input to be used to synchronize the counter.
- * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR TS LL_TIM_SetTriggerInput
* @param TIMx Timer instance
@@ -2690,7 +2723,7 @@ __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerI
/**
* @brief Enable the Master/Slave mode.
- * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
* @param TIMx Timer instance
@@ -2703,7 +2736,7 @@ __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
/**
* @brief Disable the Master/Slave mode.
- * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
* @param TIMx Timer instance
@@ -2716,7 +2749,7 @@ __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
/**
* @brief Indicates whether the Master/Slave mode is enabled.
- * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
* @param TIMx Timer instance
@@ -2729,7 +2762,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
/**
* @brief Configure the external trigger (ETR) input.
- * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an external trigger input.
* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
* SMCR ETPS LL_TIM_ConfigETR\n
@@ -2777,7 +2810,7 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u
*/
/**
* @brief Enable the break function.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR BKE LL_TIM_EnableBRK
* @param TIMx Timer instance
@@ -2796,7 +2829,7 @@ __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
* @brief Disable the break function.
* @rmtoll BDTR BKE LL_TIM_DisableBRK
* @param TIMx Timer instance
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @retval None
*/
@@ -2811,7 +2844,7 @@ __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
/**
* @brief Configure the break input.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR BKP LL_TIM_ConfigBRK
* @param TIMx Timer instance
@@ -2831,7 +2864,7 @@ __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
/**
* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
* BDTR OSSR LL_TIM_SetOffStates
@@ -2851,7 +2884,7 @@ __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdl
/**
* @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
* @param TIMx Timer instance
@@ -2864,7 +2897,7 @@ __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
/**
* @brief Disable automatic output (MOE can be set only by software).
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
* @param TIMx Timer instance
@@ -2877,7 +2910,7 @@ __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
/**
* @brief Indicate whether automatic output is enabled.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
* @param TIMx Timer instance
@@ -2892,7 +2925,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
* @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
* software and is reset in case of break or break2 event
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
* @param TIMx Timer instance
@@ -2907,7 +2940,7 @@ __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
* @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
* software and is reset in case of break or break2 event.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
* @param TIMx Timer instance
@@ -2920,7 +2953,7 @@ __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
/**
* @brief Indicates whether outputs are enabled.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
* @param TIMx Timer instance
@@ -2940,7 +2973,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
*/
/**
* @brief Configures the timer DMA burst feature.
- * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
+ * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
* not a timer instance supports the DMA burst mode.
* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
* DCR DBA LL_TIM_ConfigDMABurst
@@ -2999,11 +3032,15 @@ __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstB
*/
/**
* @brief Remap TIM inputs (input channel, internal/external triggers).
- * @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
* a some timer inputs can be remapped.
- * @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n
+ * @rmtoll TIM1_OR ITR2_RMP LL_TIM_SetRemap\n
+ * TIM2_OR ITR1_RMP LL_TIM_SetRemap\n
+ * TIM5_OR ITR1_RMP LL_TIM_SetRemap\n
* TIM5_OR TI4_RMP LL_TIM_SetRemap\n
- * TIM11_OR TI1_RMP LL_TIM_SetRemap
+ * TIM9_OR ITR1_RMP LL_TIM_SetRemap\n
+ * TIM11_OR TI1_RMP LL_TIM_SetRemap\n
+ * LPTIM1_OR OR LL_TIM_SetRemap
* @param TIMx Timer instance
* @param Remap Remap param depends on the TIMx. Description available only
* in CHM version of the User Manual (not in .pdf).
@@ -3011,6 +3048,12 @@ __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstB
*
* Below description summarizes "Timer Instance" and "Remap" param combinations:
*
+ * TIM1: one of the following values
+ *
+ * ITR2_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM1_ITR2_RMP_TIM3_TRGO (*)
+ * @arg @ref LL_TIM_TIM1_ITR2_RMP_LPTIM (*)
+ *
* TIM2: one of the following values
*
* ITR1_RMP can be one of the following values
@@ -3024,19 +3067,45 @@ __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstB
* @arg @ref LL_TIM_TIM5_TI4_RMP_LSI
* @arg @ref LL_TIM_TIM5_TI4_RMP_LSE
* @arg @ref LL_TIM_TIM5_TI4_RMP_RTC
+ * @arg @ref LL_TIM_TIM5_ITR1_RMP_TIM3_TRGO (*)
+ * @arg @ref LL_TIM_TIM5_ITR1_RMP_LPTIM (*)
+ *
+ * TIM9: one of the following values
+ *
+ * ITR1_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM9_ITR1_RMP_TIM3_TRGO (*)
+ * @arg @ref LL_TIM_TIM9_ITR1_RMP_LPTIM (*)
*
* TIM11: one of the following values
*
* @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO
- * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO1
+ * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO1 (*)
* @arg @ref LL_TIM_TIM11_TI1_RMP_HSE_RTC
* @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO2
+ * @arg @ref LL_TIM_TIM11_TI1_RMP_SPDIFRX (*)
+ *
+ * (*) Value not defined in all devices. \n
*
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
{
+#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM9_ITR1_RMP)
+ if ((Remap & LL_TIM_LPTIM_REMAP_MASK) == LL_TIM_LPTIM_REMAP_MASK)
+ {
+ /* Connect TIMx internal trigger to LPTIM1 output */
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);
+ MODIFY_REG(LPTIM1->OR,
+ (LPTIM_OR_TIM1_ITR2_RMP | LPTIM_OR_TIM5_ITR1_RMP | LPTIM_OR_TIM9_ITR1_RMP),
+ Remap & ~(LL_TIM_LPTIM_REMAP_MASK));
+ }
+ else
+ {
+ MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
+ }
+#else
MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
+#endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM9_ITR1_RMP */
}
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h
index c75c68f335..1ddddb48dd 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h
@@ -357,9 +357,9 @@ typedef struct
* @param __BAUDRATE__ Baud rate value to achieve
* @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
*/
-#define __LL_USART_DIV_SAMPLING8_100(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__)*25)/(2*(__BAUDRATE__)))
+#define __LL_USART_DIV_SAMPLING8_100(__PERIPHCLK__, __BAUDRATE__) ((uint32_t)((((uint64_t)(__PERIPHCLK__))*25)/(2*((uint64_t)(__BAUDRATE__)))))
#define __LL_USART_DIVMANT_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__))/100)
-#define __LL_USART_DIVFRAQ_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 8 + 50) / 100)
+#define __LL_USART_DIVFRAQ_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 8) + 50) / 100)
/* UART BRR = mantissa + overflow + fraction
= (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07) */
#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \
@@ -373,9 +373,9 @@ typedef struct
* @param __BAUDRATE__ Baud rate value to achieve
* @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
*/
-#define __LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__)*25)/(4*(__BAUDRATE__)))
+#define __LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__, __BAUDRATE__) ((uint32_t)((((uint64_t)(__PERIPHCLK__))*25)/(4*((uint64_t)(__BAUDRATE__)))))
#define __LL_USART_DIVMANT_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__))/100)
-#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16 + 50) / 100)
+#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) ((((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16) + 50) / 100)
/* USART BRR = mantissa + overflow + fraction
= (USART DIVMANT << 4) + (USART DIVFRAQ & 0xF0) + (USART DIVFRAQ & 0x0F) */
#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \
@@ -1043,8 +1043,8 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph
*/
__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)
{
- register uint32_t usartdiv = 0x0U;
- register uint32_t brrresult = 0x0U;
+ uint32_t usartdiv = 0x0U;
+ uint32_t brrresult = 0x0U;
usartdiv = USARTx->BRR;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h
index a1f31b3a64..28be518656 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h
@@ -81,7 +81,7 @@ typedef enum
} USB_OTG_HCStateTypeDef;
/**
- * @brief USB OTG Initialization Structure definition
+ * @brief USB Instance Initialization Structure definition
*/
typedef struct
{
@@ -94,14 +94,14 @@ typedef struct
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint32_t speed; /*!< USB Core speed.
- This parameter can be any value of @ref USB_Core_Speed_ */
+ This parameter can be any value of @ref USB_Core_Speed */
uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
uint32_t phy_itface; /*!< Select the used PHY interface.
- This parameter can be any value of @ref USB_Core_PHY_ */
+ This parameter can be any value of @ref USB_Core_PHY */
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
@@ -116,6 +116,7 @@ typedef struct
uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
+
} USB_OTG_CfgTypeDef;
typedef struct
@@ -155,7 +156,7 @@ typedef struct
typedef struct
{
- uint8_t dev_addr ; /*!< USB device address.
+ uint8_t dev_addr; /*!< USB device address.
This parameter must be a number between Min_Data = 1 and Max_Data = 255 */
uint8_t ch_num; /*!< Host channel number.
@@ -185,6 +186,8 @@ typedef struct
uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */
+ uint32_t XferSize; /*!< OTG Channel transfer size. */
+
uint32_t xfer_len; /*!< Current transfer length. */
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */
@@ -197,13 +200,13 @@ typedef struct
uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */
- uint32_t ErrCnt; /*!< Host channel error count.*/
+ uint32_t ErrCnt; /*!< Host channel error count. */
- USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
+ USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
- USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
- This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
+ USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
+ This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
} USB_OTG_HCTypeDef;
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
@@ -237,11 +240,11 @@ typedef struct
/** @defgroup USB_LL Device Speed
* @{
*/
-#define USBD_HS_SPEED 0U
-#define USBD_HSINFS_SPEED 1U
-#define USBH_HS_SPEED 0U
-#define USBD_FS_SPEED 2U
-#define USBH_FS_SPEED 1U
+#define USBD_HS_SPEED 0U
+#define USBD_HSINFS_SPEED 1U
+#define USBH_HS_SPEED 0U
+#define USBD_FS_SPEED 2U
+#define USBH_FSLS_SPEED 1U
/**
* @}
*/
@@ -269,11 +272,11 @@ typedef struct
* @{
*/
#ifndef USBD_HS_TRDT_VALUE
-#define USBD_HS_TRDT_VALUE 9U
+#define USBD_HS_TRDT_VALUE 9U
#endif /* USBD_HS_TRDT_VALUE */
#ifndef USBD_FS_TRDT_VALUE
-#define USBD_FS_TRDT_VALUE 5U
-#define USBD_DEFAULT_TRDT_VALUE 9U
+#define USBD_FS_TRDT_VALUE 5U
+#define USBD_DEFAULT_TRDT_VALUE 9U
#endif /* USBD_HS_TRDT_VALUE */
/**
* @}
@@ -282,9 +285,9 @@ typedef struct
/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS
* @{
*/
-#define USB_OTG_HS_MAX_PACKET_SIZE 512U
-#define USB_OTG_FS_MAX_PACKET_SIZE 64U
-#define USB_OTG_MAX_EP0_SIZE 64U
+#define USB_OTG_HS_MAX_PACKET_SIZE 512U
+#define USB_OTG_FS_MAX_PACKET_SIZE 64U
+#define USB_OTG_MAX_EP0_SIZE 64U
/**
* @}
*/
@@ -294,7 +297,6 @@ typedef struct
*/
#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1)
#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1)
-#define DSTS_ENUMSPD_LS_PHY_6MHZ (2U << 1)
#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1)
/**
* @}
@@ -314,10 +316,10 @@ typedef struct
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
* @{
*/
-#define DEP0CTL_MPS_64 0U
-#define DEP0CTL_MPS_32 1U
-#define DEP0CTL_MPS_16 2U
-#define DEP0CTL_MPS_8 3U
+#define EP_MPS_64 0U
+#define EP_MPS_32 1U
+#define EP_MPS_16 2U
+#define EP_MPS_8 3U
/**
* @}
*/
@@ -443,7 +445,9 @@ HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB
HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
-HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma);
+HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
+ uint8_t ch_ep_num, uint16_t len, uint8_t dma);
+
void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
@@ -468,14 +472,12 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state);
uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
- uint8_t ch_num,
- uint8_t epnum,
- uint8_t dev_address,
- uint8_t speed,
- uint8_t ep_type,
- uint16_t mps);
-HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma);
+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
+ uint8_t epnum, uint8_t dev_address, uint8_t speed,
+ uint8_t ep_type, uint16_t mps);
+HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx,
+ USB_OTG_HCTypeDef *hc, uint8_t dma);
+
uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h
index 60ea7070c7..3bac30cf08 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h
@@ -279,6 +279,7 @@ void LL_mDelay(uint32_t Delay);
*/
void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
+ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency);
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_wwdg.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_wwdg.h
index 9fed6aad0d..f20b82dd80 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_wwdg.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_wwdg.h
@@ -58,8 +58,8 @@ extern "C" {
*/
/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
-* @{
-*/
+ * @{
+ */
#define LL_WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
@@ -175,7 +175,7 @@ __STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
* @arg @ref LL_WWDG_PRESCALER_2
* @arg @ref LL_WWDG_PRESCALER_4
* @arg @ref LL_WWDG_PRESCALER_8
-* @retval None
+ * @retval None
*/
__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
{
@@ -314,6 +314,6 @@ __STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
}
#endif
-#endif /* __STM32F4xx_LL_WWDG_H */
+#endif /* STM32F4xx_LL_WWDG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Release_Notes.html b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Release_Notes.html
index db2e37a931..02dfb15151 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Release_Notes.html
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Release_Notes.html
@@ -19,6 +19,15 @@
+
+
+
+
+
+
+
+
+
@@ -930,7 +939,7 @@ ul
Release Notes for STM32F4xx HAL Drivers
Copyright
2017 STMicroelectronics
- 
+ 
@@ -940,8 +949,243 @@ ul
V1.2.0 / 11-September-2013
Main
@@ -565,7 +584,7 @@ STOP Mode current, SAI, PCROP, SDRAM and DMA2D Main
@@ -592,23 +611,23 @@ address and data lines V1.1.0 /
+
V1.1.0 /
11-January-2013
of PSRAM (PSRAM is available only on STM324xG-EVAL RevA) and update timing
valuesV1.0.2 / 05-March-2012
+V1.0.2 / 05-March-2012
Main
Changes
- All source files: license disclaimer text update and add link to the License file on ST Internet.
V1.0.1 / 28-December-2011
Main
+ Main
Changes Main
+ Main
Changes Main
+ Main
Changes Main
+ Main
Changes Copyright
2017 STMicroelectronics V1.0.1 / 28-December-2011
V1.0.0 / 30-September-2011
V1.0.0 / 30-September-2011
V1.0.0RC2 / 26-September-2011
V1.0.0RC2 / 26-September-2011
V1.0.0RC1 / 25-August-2011
V1.0.0RC1 / 25-August-2011
-License
License
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f401xc.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f401xc.s
index 457838798b..8891f3b391 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f401xc.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f401xc.s
@@ -1,4 +1,4 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;*******************************************************************************
;* File Name : startup_stm32f401xc.s
;* Author : MCD Application Team
;* Description : STM32F401xc devices vector table for MDK-ARM toolchain.
@@ -10,33 +10,20 @@
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;********************************************************************************
+;* @attention
+;*
+;*
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
;
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
;
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
;
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
;
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
;
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
;
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
;
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
;
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
;
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
;
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
;
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
;
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
;
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
;
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
;
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
;
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
;
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
;
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
;
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
;
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
;
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
;
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
;*******************************************************************************
-
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
;
+ *
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xe.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xe.s
index eb8959e0b2..9c0365b0a2 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xe.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xe.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- *
+ *
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,37 +62,40 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
bx lr
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f405xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f405xx.s
index 628c57efec..9329632479 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f405xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f405xx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- *
+ *
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s
index 75c97e9abc..8c1612047c 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- *
+ *
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410cx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410cx.s
index d44de86099..c063b38d80 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410cx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410cx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- *
+ *
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410rx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410rx.s
index 2c8250aa7d..525f9b9ec7 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410rx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410rx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- *
+ *
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410tx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410tx.s
index 43bde68565..f9533d1a67 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410tx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410tx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- *
+ *
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f411xe.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f411xe.s
index ad12201155..bc1631b935 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f411xe.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f411xe.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- *
+ *
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412cx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412cx.s
index 30301904d2..cfdb79bc02 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412cx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412cx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- *
+ *
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,37 +62,40 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
bx lr
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412rx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412rx.s
index 06377d97d7..05dce21556 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412rx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412rx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- *
+ *
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412vx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412vx.s
index 4c5a42e865..b6e99badf0 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412vx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412vx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- *
+ *
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412zx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412zx.s
index 10411aa683..035a4723f3 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412zx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412zx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- *
+ *
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f413xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f413xx.s
index 77d079cfa6..e4fdc23516 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f413xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f413xx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- *
+ *
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f415xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f415xx.s
index 36aca9cc04..ad0b242df1 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f415xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f415xx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- *
+ *
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f417xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f417xx.s
index 4e9c137d09..70b7e981c6 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f417xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f417xx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- *
+ *
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f423xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f423xx.s
index c9e93753fd..92d6e1ffea 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f423xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f423xx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- *
+ *
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f427xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f427xx.s
index 6cb9fb655e..6384221551 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f427xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f427xx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- *
+ *
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,37 +62,40 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
bx lr
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f429xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f429xx.s
index d0d3b3a329..b0311ffc4e 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f429xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f429xx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- *
+ *
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f437xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f437xx.s
index 46468d362d..a110faf141 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f437xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f437xx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- *
+ *
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f439xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f439xx.s
index b97cfc3e22..4bd6b6fd0a 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f439xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f439xx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- *
+ *
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f446xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f446xx.s
index a751533537..804f286bdd 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f446xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f446xx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- *
+ *
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f469xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f469xx.s
index b7a127f9c4..c52b895e93 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f469xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f469xx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- *
+ *
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f479xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f479xx.s
index 2b9c91064e..cc70ac5b6f 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f479xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f479xx.s
@@ -14,29 +14,13 @@
******************************************************************************
* @attention
*
- *
+ *
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,40 +62,43 @@ Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-/* bl __libc_init_array */
+ bl __libc_init_array
/* Call the application's entry point.*/
bl entry
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f401xc.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f401xc.s
index f987c5339a..a326e61ab9 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f401xc.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f401xc.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f401xc.s
;* Author : MCD Application Team
;* Description : STM32F401xCxx devices vector table for EWARM toolchain.
@@ -13,29 +13,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;*
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f401xe.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f401xe.s
index 68bf762b91..1342ced8bb 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f401xe.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f401xe.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f401xe.s
;* Author : MCD Application Team
;* Description : STM32F401xExx devices vector table for EWARM toolchain.
@@ -13,29 +13,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;*
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f405xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f405xx.s
index f4ca8320fe..ab5c263e5f 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f405xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f405xx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f405xx.s
;* Author : MCD Application Team
;* Description : STM32F405xx devices vector table for EWARM toolchain.
@@ -12,29 +12,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;*
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f407xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f407xx.s
index 57738bbdc3..261246e249 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f407xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f407xx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f407xx.s
;* Author : MCD Application Team
;* Description : STM32F407xx devices vector table for EWARM toolchain.
@@ -12,29 +12,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;*
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f410cx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f410cx.s
index 2c66d25424..0a545d352a 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f410cx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f410cx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f410cx.s
;* Author : MCD Application Team
;* Description : STM32F410Cx devices vector table for EWARM toolchain.
@@ -13,29 +13,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;*
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f410rx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f410rx.s
index f301994f41..933e77a38e 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f410rx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f410rx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f410rx.s
;* Author : MCD Application Team
;* Description : STM32F410Rx devices vector table for EWARM toolchain.
@@ -13,29 +13,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;*
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f410tx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f410tx.s
index 20c8d53c17..3315a9be11 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f410tx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f410tx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f410tx.s
;* Author : MCD Application Team
;* Description : STM32F410Tx devices vector table for EWARM toolchain.
@@ -13,29 +13,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;*
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f411xe.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f411xe.s
index b56c8f521d..9f2a6c67e0 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f411xe.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f411xe.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f411xe.s
;* Author : MCD Application Team
;* Description : STM32F411xExx devices vector table for EWARM toolchain.
@@ -13,29 +13,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;*
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f412cx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f412cx.s
index dd77bf0cd7..d561b12bbc 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f412cx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f412cx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f412cx.s
;* Author : MCD Application Team
;* Description : STM32F412Cx devices vector table for EWARM toolchain.
@@ -13,29 +13,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;*
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f412rx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f412rx.s
index 14bb437fcc..220280b28c 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f412rx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f412rx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f412rx.s
;* Author : MCD Application Team
;* Description : STM32F412Rx devices vector table for EWARM toolchain.
@@ -13,29 +13,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;*
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f412vx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f412vx.s
index 4312c16f9c..107ca64263 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f412vx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f412vx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f412vx.s
;* Author : MCD Application Team
;* Description : STM32F412Vx devices vector table for EWARM toolchain.
@@ -13,29 +13,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;*
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f412zx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f412zx.s
index f065a99560..cd4189e6da 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f412zx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f412zx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f412zx.s
;* Author : MCD Application Team
;* Description : STM32F412Zx devices vector table for EWARM toolchain.
@@ -13,29 +13,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;*
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f413xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f413xx.s
index da2b6b6924..4ae7c197ba 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f413xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f413xx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f413xx.s
;* Author : MCD Application Team
;* Description : STM32F413xx devices vector table for EWARM toolchain.
@@ -13,29 +13,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;*
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f415xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f415xx.s
index 932a34d2ad..9a8070dc02 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f415xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f415xx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f415xx.s
;* Author : MCD Application Team
;* Description : STM32F415xx devices vector table for EWARM toolchain.
@@ -12,29 +12,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;*
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f417xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f417xx.s
index 0a087c423e..dd9a54dad2 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f417xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f417xx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f417xx.s
;* Author : MCD Application Team
;* Description : STM32F417xx devices vector table for EWARM toolchain.
@@ -12,29 +12,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;*
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f423xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f423xx.s
index a1c60ae46a..b154532aa4 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f423xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f423xx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f423xx.s
;* Author : MCD Application Team
;* Description : STM32F423xx devices vector table for EWARM toolchain.
@@ -13,29 +13,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;*
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f427xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f427xx.s
index c3e08b6aa5..28912fe2b4 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f427xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f427xx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f427xx.s
;* Author : MCD Application Team
;* Description : STM32F427xx devices vector table for EWARM toolchain.
@@ -12,29 +12,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;*
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f429xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f429xx.s
index 242307e967..475dc6b763 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f429xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f429xx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f429xx.s
;* Author : MCD Application Team
;* Description : STM32F429xx devices vector table for EWARM toolchain.
@@ -12,29 +12,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;*
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f437xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f437xx.s
index 4ad01cf25a..d8703371cd 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f437xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f437xx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f437xx.s
;* Author : MCD Application Team
;* Description : STM32F437xx devices vector table for EWARM toolchain.
@@ -12,29 +12,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;*
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f439xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f439xx.s
index 59e3fef3d4..d91d4919ba 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f439xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f439xx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f439xx.s
;* Author : MCD Application Team
;* Description : STM32F439xx devices vector table for EWARM toolchain.
@@ -12,29 +12,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;*
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f446xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f446xx.s
index 85c7c51f69..b3d6720043 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f446xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f446xx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f446xx.s
;* Author : MCD Application Team
;* Description : STM32F446xx devices vector table for EWARM toolchain.
@@ -12,29 +12,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;*
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f469xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f469xx.s
index 4089305089..d1f8f3a280 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f469xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f469xx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f469xx.s
;* Author : MCD Application Team
;* Description : STM32F469xx devices vector table for EWARM toolchain.
@@ -12,29 +12,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;*
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f479xx.s b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f479xx.s
index 88eaddcf3f..3b8cac9ae0 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f479xx.s
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f479xx.s
@@ -1,4 +1,4 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;********************************************************************************
;* File Name : startup_stm32f479xx.s
;* Author : MCD Application Team
;* Description : STM32F479xx devices vector table for EWARM toolchain.
@@ -12,29 +12,16 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
+;* @attention
+;*
+;*
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
;*******************************************************************************
;
;
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c
index 3303f969d9..d1acf9ed2e 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c
@@ -22,29 +22,13 @@
******************************************************************************
* @attention
*
- *
+ *
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -103,11 +87,29 @@
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
STM32F479xx */
-/*!< Uncomment the following line if you need to relocate your vector Table in
- Internal SRAM. */
+/* Note: Following vector table addresses must be defined in line with linker
+ configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+ anywhere in Flash or Sram, else the vector table is kept at the automatic
+ remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+/*!< Uncomment the following line if you need to relocate your vector Table
+ in Sram else user remap will be done in Flash. */
/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
- This value must be a multiple of 0x200. */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+#else
+#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+#endif /* VECT_TAB_SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
/******************************************************************************/
/**
@@ -169,35 +171,15 @@ void SystemInit(void)
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
#endif
- /* Reset the RCC clock configuration to the default reset state ------------*/
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
-
- /* Reset CFGR register */
- RCC->CFGR = 0x00000000;
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFF;
-
- /* Reset PLLCFGR register */
- RCC->PLLCFGR = 0x24003010;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000;
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
- /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
+ /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
}
/**
@@ -403,6 +385,7 @@ void SystemInit_ExtMemCtl(void)
/* PALL command */
FMC_Bank5_6->SDCMR = 0x00000012;
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
@@ -411,6 +394,7 @@ void SystemInit_ExtMemCtl(void)
/* Auto refresh command */
FMC_Bank5_6->SDCMR = 0x00000073;
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
@@ -419,6 +403,7 @@ void SystemInit_ExtMemCtl(void)
/* MRD register program */
FMC_Bank5_6->SDCMR = 0x00046014;
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
@@ -608,6 +593,7 @@ void SystemInit_ExtMemCtl(void)
/* PALL command */
FMC_Bank5_6->SDCMR = 0x00000012;
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
@@ -620,6 +606,7 @@ void SystemInit_ExtMemCtl(void)
#else
FMC_Bank5_6->SDCMR = 0x00000073;
#endif /* STM32F446xx */
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
@@ -632,6 +619,7 @@ void SystemInit_ExtMemCtl(void)
#else
FMC_Bank5_6->SDCMR = 0x00046014;
#endif /* STM32F446xx */
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
index 889db8f18f..299ed70498 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
@@ -7,7 +7,7 @@
******************************************************************************
* @attention
*
- *
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -23,7 +23,7 @@
#define STM32_HAL_LEGACY
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -38,7 +38,6 @@
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
-
/**
* @}
*/
@@ -236,6 +235,16 @@
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
+#if defined(STM32G4) || defined(STM32H7)
+#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
+#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
+#endif
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
+#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
+#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
+#endif
+
/**
* @}
*/
@@ -296,8 +305,22 @@
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
+#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
+#endif
+
#endif /* STM32L4 */
+#if defined(STM32G0)
+#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
+#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM
+#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM
+
+#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM
+#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM
+#endif
+
#if defined(STM32H7)
#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
@@ -355,6 +378,9 @@
#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
+#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT
+#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
+
#endif /* STM32H7 */
/**
@@ -450,7 +476,9 @@
#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
-#endif
+#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
+#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
+#endif /* STM32H7 */
/**
* @}
@@ -486,6 +514,13 @@
#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
+#if defined(STM32G4)
+
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster
+#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD
+#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
+#endif /* STM32G4 */
/**
* @}
*/
@@ -494,7 +529,7 @@
/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
* @{
*/
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7)
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
@@ -547,30 +582,37 @@
#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
-#endif
+
+#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \
+ defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx)
+#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
+#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
+#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
+#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
+#endif /* STM32H7 */
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32H7)
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32H7*/
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB*/
#if defined(STM32L1)
- #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
- #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
- #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
- #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
+#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
#endif /* STM32L1 */
#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
- #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
- #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
- #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
#endif /* STM32F0 || STM32F3 || STM32F1 */
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
@@ -599,6 +641,146 @@
#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
+
+#if defined(STM32G4)
+#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig
+#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
+#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable
+#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset
+#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A
+#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B
+#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
+#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
+#endif /* STM32G4 */
+
+#if defined(STM32H7)
+#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+
+#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+#endif /* STM32H7 */
+
+#if defined(STM32F3)
+/** @brief Constants defining available sources associated to external events.
+ */
+#define HRTIM_EVENTSRC_1 (0x00000000U)
+#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0)
+#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
+#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
+
+/** @brief Constants defining the DLL calibration periods (in micro seconds)
+ */
+#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
+#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
+#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
+#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
+
+#endif /* STM32F3 */
/**
* @}
*/
@@ -738,6 +920,17 @@
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
+#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
+#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
+#endif
+
+#if defined(STM32L4) || defined(STM32L5)
+#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER
+#elif defined(STM32G4)
+#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED
+#endif
+
/**
* @}
*/
@@ -748,16 +941,15 @@
#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
#if defined(STM32H7)
- #define I2S_IT_TXE I2S_IT_TXP
- #define I2S_IT_RXNE I2S_IT_RXP
+#define I2S_IT_TXE I2S_IT_TXP
+#define I2S_IT_RXNE I2S_IT_RXP
- #define I2S_FLAG_TXE I2S_FLAG_TXP
- #define I2S_FLAG_RXNE I2S_FLAG_RXP
- #define I2S_FLAG_FRE I2S_FLAG_TIFRE
+#define I2S_FLAG_TXE I2S_FLAG_TXP
+#define I2S_FLAG_RXNE I2S_FLAG_RXP
#endif
#if defined(STM32F7)
- #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
+#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
#endif
/**
* @}
@@ -824,6 +1016,16 @@
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
+#if defined(STM32H7)
+#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
+#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
+
+#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
+#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
+#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
+#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
+#endif /* STM32H7 */
+
/**
* @}
*/
@@ -882,16 +1084,16 @@
#if defined(STM32H7)
- #define SPI_FLAG_TXE SPI_FLAG_TXP
- #define SPI_FLAG_RXNE SPI_FLAG_RXP
+#define SPI_FLAG_TXE SPI_FLAG_TXP
+#define SPI_FLAG_RXNE SPI_FLAG_RXP
- #define SPI_IT_TXE SPI_IT_TXP
- #define SPI_IT_RXNE SPI_IT_RXP
+#define SPI_IT_TXE SPI_IT_TXP
+#define SPI_IT_RXNE SPI_IT_RXP
- #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
- #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
- #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
- #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
+#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
+#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
+#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
+#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
#endif /* STM32H7 */
@@ -971,6 +1173,24 @@
#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
#endif
+#if defined(STM32H7)
+#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1
+#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2
+#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1
+#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2
+#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1
+#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2
+#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1
+#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1
+#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2
+#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1
+#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2
+#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2
+#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1
+#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2
+#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
+#endif
+
/**
* @}
*/
@@ -1199,6 +1419,30 @@
#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
+
+#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
+
+#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
+#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
+#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT
+#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT
+
+#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt
+#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End
+#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT
+#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt
+#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End
+#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT
+#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt
+#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End
+#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
+#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
+
+#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
/**
* @}
*/
@@ -1212,7 +1456,8 @@
#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
-#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
+ )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
#if defined(STM32L0)
@@ -1220,7 +1465,15 @@
#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
#endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
-#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
+ )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
+#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
+#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
+#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
+#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
+#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode
+#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */
+
/**
* @}
*/
@@ -1236,9 +1489,9 @@
#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
- /**
+/**
* @}
- */
+ */
/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
* @{
@@ -1248,18 +1501,21 @@
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
-#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\
+ )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7)
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
-#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 */
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
#if defined(STM32F4)
#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
@@ -1271,13 +1527,20 @@
#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA
#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA
#endif /* STM32F4 */
- /**
+/**
* @}
- */
+ */
/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
* @{
*/
+
+#if defined(STM32G0)
+#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
+#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
+#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
+#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
+#endif
#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
@@ -1321,9 +1584,9 @@
#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
- /**
+/**
* @}
- */
+ */
/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
* @{
@@ -1350,14 +1613,14 @@
#define HAL_TIM_DMAError TIM_DMAError
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
-#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0)
+#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
-#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */
+#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
/**
* @}
*/
@@ -1572,15 +1835,15 @@
#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
#if defined(STM32H7)
- #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
- #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
- #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
- #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
#else
- #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
- #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
- #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
- #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
#endif /* STM32H7 */
#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
@@ -1791,8 +2054,8 @@
*/
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
- ((WAVE) == DAC_WAVE_NOISE)|| \
- ((WAVE) == DAC_WAVE_TRIANGLE))
+ ((WAVE) == DAC_WAVE_NOISE)|| \
+ ((WAVE) == DAC_WAVE_TRIANGLE))
/**
* @}
@@ -1848,7 +2111,7 @@
#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
#if defined(STM32H7)
- #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
+#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
#endif
/**
@@ -1985,7 +2248,8 @@
#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
-#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\
+ )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
@@ -2476,12 +2740,28 @@
#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
+
+#if defined(STM32H7)
+#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE
+#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
+
+#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/
+#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
+
+
+#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
+#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
+#endif
+
#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
+
#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
@@ -2814,6 +3094,15 @@
#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
+#if defined(STM32L1)
+#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
+#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
+#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
+#endif /* STM32L1 */
+
#if defined(STM32F4)
#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
@@ -2928,9 +3217,8 @@
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
-#if defined(STM32L4)
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
-#elif defined(STM32WB) || defined(STM32G0)
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
#endif
@@ -3058,7 +3346,7 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
-#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx)
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@@ -3078,19 +3366,19 @@
#else
#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
#endif /* STM32F1 */
#define IS_ALARM IS_RTC_ALARM
@@ -3166,22 +3454,22 @@
#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
-#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
-#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
-#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
+#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
+#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
+#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
/* alias CMSIS for compatibilities */
#define SDIO_IRQn SDMMC1_IRQn
#define SDIO_IRQHandler SDMMC1_IRQHandler
#endif
-#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2)
+#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
#endif
-#if defined(STM32H7)
+#if defined(STM32H7) || defined(STM32L5)
#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
@@ -3274,6 +3562,13 @@
#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7)
+#define USART_OVERSAMPLING_16 0x00000000U
+#define USART_OVERSAMPLING_8 USART_CR1_OVER8
+
+#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
+ ((__SAMPLING__) == USART_OVERSAMPLING_8))
+#endif /* STM32F0 || STM32F3 || STM32F7 */
/**
* @}
*/
@@ -3421,18 +3716,28 @@
/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
* @{
*/
-#if defined (STM32H7) || defined (STM32F3)
-#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
-#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
-#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
-#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
-#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
-#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
+#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
+#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
+#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
+#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
+#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
+#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
+#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
#endif
/**
* @}
*/
+/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
+#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
+#endif /* STM32L4 || STM32F4 || STM32F7 */
+/**
+ * @}
+ */
+
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
* @{
*/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/Legacy/stm32f4xx_hal_can_legacy.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/Legacy/stm32f4xx_hal_can_legacy.h
index 7788f06c2c..aacf0f0727 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/Legacy/stm32f4xx_hal_can_legacy.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/Legacy/stm32f4xx_hal_can_legacy.h
@@ -6,13 +6,29 @@
******************************************************************************
* @attention
*
- *
+ *
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h
index 5b800df7de..209864d530 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h
@@ -197,6 +197,18 @@ typedef enum
* @}
*/
+/* Exported variables --------------------------------------------------------*/
+
+/** @addtogroup HAL_Exported_Variables
+ * @{
+ */
+extern __IO uint32_t uwTick;
+extern uint32_t uwTickPrio;
+extern HAL_TickFreqTypeDef uwTickFreq;
+/**
+ * @}
+ */
+
/* Exported functions --------------------------------------------------------*/
/** @addtogroup HAL_Exported_Functions
* @{
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h
index badeabc401..a041e76965 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h
@@ -28,6 +28,9 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
+/* Include low level driver */
+#include "stm32f4xx_ll_adc.h"
+
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h
index ed38931dc0..b0cdd2abd3 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h
@@ -304,17 +304,18 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
*/
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \
- defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
- defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+ defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \
+ defined(STM32F412Cx)
#define IS_ADC_CHANNEL(CHANNEL) ((CHANNEL) <= ADC_CHANNEL_18)
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE ||
- STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE ||
+ STM32F410xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+
+#if defined(STM32F411xE) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || \
+ defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx)
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18) || \
((CHANNEL) == ADC_CHANNEL_TEMPSENSOR))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+#endif /* STM32F411xE || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \
((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h
index 0611a6521a..062abd6925 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h
@@ -255,7 +255,7 @@ typedef enum
HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID = 0x08U, /*!< CAN Rx FIFO 1 message pending callback ID */
HAL_CAN_RX_FIFO1_FULL_CB_ID = 0x09U, /*!< CAN Rx FIFO 1 full callback ID */
HAL_CAN_SLEEP_CB_ID = 0x0AU, /*!< CAN Sleep callback ID */
- HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID = 0x0BU, /*!< CAN Wake Up fropm Rx msg callback ID */
+ HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID = 0x0BU, /*!< CAN Wake Up from Rx msg callback ID */
HAL_CAN_ERROR_CB_ID = 0x0CU, /*!< CAN Error callback ID */
HAL_CAN_MSPINIT_CB_ID = 0x0DU, /*!< CAN MspInit callback ID */
@@ -295,11 +295,11 @@ typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to
#define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */
#define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */
#define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
-#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 1 transmit failure due to tranmit error */
-#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
-#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to tranmit error */
-#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
-#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 1 transmit failure due to tranmit error */
+#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 0 transmit failure due to transmit error */
+#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 1 transmit failure due to arbitration lost */
+#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to transmit error */
+#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 2 transmit failure due to arbitration lost */
+#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 2 transmit failure due to transmit error */
#define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */
#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */
#define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cec.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cec.h
index 3519cbd863..f371a9cf13 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cec.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cec.h
@@ -121,7 +121,7 @@ typedef struct
* b6 Error information
* 0 : No Error
* 1 : Error
- * b5 IP initilisation status
+ * b5 IP initialization status
* 0 : Reset (IP not initialized)
* 1 : Init done (IP initialized. HAL CEC Init function already called)
* b4-b3 (not used)
@@ -138,7 +138,7 @@ typedef struct
* RxState value coding follow below described bitmap :
* b7-b6 (not used)
* xx : Should be set to 00
- * b5 IP initilisation status
+ * b5 IP initialization status
* 0 : Reset (IP not initialized)
* 1 : Init done (IP initialized)
* b4-b2 (not used)
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_conf_template.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_conf_template.h
index 37c8780fa4..afa2f56876 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_conf_template.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_conf_template.h
@@ -79,6 +79,7 @@
#define HAL_PCD_MODULE_ENABLED
#define HAL_HCD_MODULE_ENABLED
#define HAL_FMPI2C_MODULE_ENABLED
+#define HAL_FMPSMBUS_MODULE_ENABLED
#define HAL_SPDIFRX_MODULE_ENABLED
#define HAL_DFSDM_MODULE_ENABLED
#define HAL_LPTIM_MODULE_ENABLED
@@ -163,6 +164,7 @@
#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */
+#define USE_HAL_FMPSMBUS_REGISTER_CALLBACKS 0U /* FMPSMBUS register callback disabled */
#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */
@@ -451,6 +453,10 @@
#include "stm32f4xx_hal_fmpi2c.h"
#endif /* HAL_FMPI2C_MODULE_ENABLED */
+#ifdef HAL_FMPSMBUS_MODULE_ENABLED
+ #include "stm32f4xx_hal_fmpsmbus.h"
+#endif /* HAL_FMPSMBUS_MODULE_ENABLED */
+
#ifdef HAL_SPDIFRX_MODULE_ENABLED
#include "stm32f4xx_hal_spdifrx.h"
#endif /* HAL_SPDIFRX_MODULE_ENABLED */
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cryp.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cryp.h
index 8251ebd255..8596fe7d21 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cryp.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cryp.h
@@ -6,23 +6,23 @@
******************************************************************************
* @attention
*
- *
*
* This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
+ * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_CRYP_H
#define __STM32F4xx_HAL_CRYP_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
@@ -51,87 +51,98 @@ typedef struct
{
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
This parameter can be a value of @ref CRYP_Data_Type */
- uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
+ uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
128 or 256 bit key length in TinyAES This parameter can be a value of @ref CRYP_Key_Size */
- uint32_t* pKey; /*!< The key used for encryption/decryption */
- uint32_t* pInitVect; /*!< The initialization vector used also as initialization
+ uint32_t *pKey; /*!< The key used for encryption/decryption */
+ uint32_t *pInitVect; /*!< The initialization vector used also as initialization
counter in CTR mode */
- uint32_t Algorithm; /*!< DES/ TDES Algorithm ECB/CBC
+ uint32_t Algorithm; /*!< DES/ TDES Algorithm ECB/CBC
AES Algorithm ECB/CBC/CTR/GCM or CCM
This parameter can be a value of @ref CRYP_Algorithm_Mode */
- uint32_t* Header; /*!< used only in AES GCM and CCM Algorithm for authentication,
+ uint32_t *Header; /*!< used only in AES GCM and CCM Algorithm for authentication,
GCM : also known as Additional Authentication Data
CCM : named B1 composed of the associated data length and Associated Data. */
uint32_t HeaderSize; /*!< The size of header buffer in word */
- uint32_t* B0; /*!< B0 is first authentication block used only in AES CCM mode */
+ uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */
uint32_t DataWidthUnit; /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
+ uint32_t HeaderWidthUnit; /*!< Header Width Unit, this parameter can be value of @ref CRYP_Header_Width_Unit*/
+ uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization
+ Vector only once and to skip configuration for consecutive processings.
+ This parameter can be a value of @ref CRYP_Configuration_Skip */
-}CRYP_ConfigTypeDef;
+} CRYP_ConfigTypeDef;
/**
* @brief CRYP State Structure definition
*/
-
+
typedef enum
{
HAL_CRYP_STATE_RESET = 0x00U, /*!< CRYP not yet initialized or disabled */
HAL_CRYP_STATE_READY = 0x01U, /*!< CRYP initialized and ready for use */
HAL_CRYP_STATE_BUSY = 0x02U /*!< CRYP BUSY, internal processing is ongoing */
-}HAL_CRYP_STATETypeDef;
-
+} HAL_CRYP_STATETypeDef;
+
/**
* @brief CRYP handle Structure definition
*/
-
+
typedef struct __CRYP_HandleTypeDef
{
#if defined (CRYP)
- CRYP_TypeDef *Instance; /*!< CRYP registers base address */
+ CRYP_TypeDef *Instance; /*!< CRYP registers base address */
#else /* AES*/
- AES_TypeDef *Instance; /*!< AES Register base address */
+ AES_TypeDef *Instance; /*!< AES Register base address */
#endif /* End AES or CRYP */
- CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */
-
- FunctionalState AutoKeyDerivation; /*!< Used only in TinyAES to allows to bypass or not key write-up before decryption.
- This parameter can be a value of ENABLE/DISABLE */
-
- uint32_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
+ CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */
+
+ FunctionalState AutoKeyDerivation; /*!< Used only in TinyAES to allows to bypass or not key write-up before decryption.
+ This parameter can be a value of ENABLE/DISABLE */
+
+ uint32_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
+
+ uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
- uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
+ __IO uint16_t CrypHeaderCount; /*!< Counter of header data */
- __IO uint16_t CrypHeaderCount; /*!< Counter of header data */
-
- __IO uint16_t CrypInCount; /*!< Counter of input data */
+ __IO uint16_t CrypInCount; /*!< Counter of input data */
- __IO uint16_t CrypOutCount; /*!< Counter of output data */
-
- uint16_t Size; /*!< length of input data in word */
+ __IO uint16_t CrypOutCount; /*!< Counter of output data */
- uint32_t Phase; /*!< CRYP peripheral phase */
+ uint16_t Size; /*!< length of input data in word */
- DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */
+ uint32_t Phase; /*!< CRYP peripheral phase */
- DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */
+ DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */
- HAL_LockTypeDef Lock; /*!< CRYP locking object */
+ DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< CRYP locking object */
+
+ __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
+
+ __IO uint32_t ErrorCode; /*!< CRYP peripheral error code */
+
+ uint32_t KeyIVConfig; /*!< CRYP peripheral Key and IV configuration flag, used when
+ configuration can be skipped */
+
+ uint32_t SizesSum; /*!< Sum of successive payloads lengths (in bytes), stored
+ for a single signature computation after several
+ messages processing */
- __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
-
- __IO uint32_t ErrorCode; /*!< CRYP peripheral error code */
-
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
- void (*InCpltCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Input FIFO transfer completed callback */
- void (*OutCpltCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Output FIFO transfer completed callback */
- void (*ErrorCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Error callback */
-
- void (* MspInitCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Msp Init callback */
- void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Msp DeInit callback */
+ void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Input FIFO transfer completed callback */
+ void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Output FIFO transfer completed callback */
+ void (*ErrorCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Error callback */
-#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
-}CRYP_HandleTypeDef;
+ void (* MspInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp Init callback */
+ void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp DeInit callback */
+
+#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
+} CRYP_HandleTypeDef;
/**
@@ -152,7 +163,7 @@ typedef enum
HAL_CRYP_MSPINIT_CB_ID = 0x04U, /*!< CRYP MspInit callback ID */
HAL_CRYP_MSPDEINIT_CB_ID = 0x05U /*!< CRYP MspDeInit callback ID */
-}HAL_CRYP_CallbackIDTypeDef;
+} HAL_CRYP_CallbackIDTypeDef;
/**
* @}
*/
@@ -162,7 +173,7 @@ typedef enum
* @{
*/
-typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< pointer to a common CRYP callback function */
+typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< pointer to a common CRYP callback function */
/**
* @}
@@ -181,7 +192,7 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
#define HAL_CRYP_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_CRYP_ERROR_WRITE 0x00000001U /*!< Write error */
#define HAL_CRYP_ERROR_READ 0x00000002U /*!< Read error */
-#define HAL_CRYP_ERROR_DMA 0x00000004U /*!< DMA error */
+#define HAL_CRYP_ERROR_DMA 0x00000004U /*!< DMA error */
#define HAL_CRYP_ERROR_BUSY 0x00000008U /*!< Busy flag error */
#define HAL_CRYP_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */
#define HAL_CRYP_ERROR_NOT_SUPPORTED 0x00000020U /*!< Not supported mode */
@@ -189,21 +200,32 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
#define HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid Callback error */
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
-/**
+/**
* @}
*/
-/** @defgroup CRYP_Data_Width_Unit CRYP Data Width Unit
+/** @defgroup CRYP_Data_Width_Unit CRYP Data Width Unit
* @{
*/
#define CRYP_DATAWIDTHUNIT_WORD 0x00000000U /*!< By default, size unit is word */
-#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is word */
+#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is word */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Header_Width_Unit CRYP Header Width Unit
+ * @{
+ */
-/**
+#define CRYP_HEADERWIDTHUNIT_WORD 0x00000000U /*!< By default, header size unit is word */
+#define CRYP_HEADERWIDTHUNIT_BYTE 0x00000001U /*!< By default, header size unit is byte */
+
+/**
* @}
- */
-
+ */
+
/** @defgroup CRYP_Algorithm_Mode CRYP Algorithm Mode
* @{
*/
@@ -212,14 +234,14 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
#define CRYP_DES_ECB CRYP_CR_ALGOMODE_DES_ECB
#define CRYP_DES_CBC CRYP_CR_ALGOMODE_DES_CBC
#define CRYP_TDES_ECB CRYP_CR_ALGOMODE_TDES_ECB
-#define CRYP_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC
+#define CRYP_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC
#define CRYP_AES_ECB CRYP_CR_ALGOMODE_AES_ECB
#define CRYP_AES_CBC CRYP_CR_ALGOMODE_AES_CBC
#define CRYP_AES_CTR CRYP_CR_ALGOMODE_AES_CTR
#if defined (CRYP_CR_ALGOMODE_AES_GCM)
-#define CRYP_AES_GCM CRYP_CR_ALGOMODE_AES_GCM
+#define CRYP_AES_GCM CRYP_CR_ALGOMODE_AES_GCM
#define CRYP_AES_CCM CRYP_CR_ALGOMODE_AES_CCM
-#endif /* GCM CCM defined*/
+#endif /* GCM CCM defined*/
#else /* AES*/
#define CRYP_AES_ECB 0x00000000U /*!< Electronic codebook chaining algorithm */
#define CRYP_AES_CBC AES_CR_CHMOD_0 /*!< Cipher block chaining algorithm */
@@ -228,7 +250,7 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
#define CRYP_AES_CCM AES_CR_CHMOD_2 /*!< Counter with Cipher Mode */
#endif /* End AES or CRYP */
-/**
+/**
* @}
*/
@@ -240,10 +262,10 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
#define CRYP_KEYSIZE_192B CRYP_CR_KEYSIZE_0
#define CRYP_KEYSIZE_256B CRYP_CR_KEYSIZE_1
#else /* AES*/
-#define CRYP_KEYSIZE_128B 0x00000000U /*!< 128-bit long key */
-#define CRYP_KEYSIZE_256B AES_CR_KEYSIZE /*!< 256-bit long key */
+#define CRYP_KEYSIZE_128B 0x00000000U /*!< 128-bit long key */
+#define CRYP_KEYSIZE_256B AES_CR_KEYSIZE /*!< 256-bit long key */
#endif /* End AES or CRYP */
-/**
+/**
* @}
*/
@@ -261,15 +283,15 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
#define CRYP_DATATYPE_8B AES_CR_DATATYPE_1 /*!< 8-bit data type (byte swapping) */
#define CRYP_DATATYPE_1B AES_CR_DATATYPE /*!< 1-bit data type (bit swapping) */
#endif /* End AES or CRYP */
-
-/**
+
+/**
* @}
*/
/** @defgroup CRYP_Interrupt CRYP Interrupt
* @{
*/
-#if defined (CRYP)
+#if defined (CRYP)
#define CRYP_IT_INI CRYP_IMSCR_INIM /*!< Input FIFO Interrupt */
#define CRYP_IT_OUTI CRYP_IMSCR_OUTIM /*!< Output FIFO Interrupt */
#else /* AES*/
@@ -297,7 +319,7 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
or a key preparation (for AES decryption). */
/* Flags in the RISR register */
#define CRYP_FLAG_OUTRIS 0x01000002U /*!< Output FIFO service raw interrupt status */
-#define CRYP_FLAG_INRIS 0x01000001U /*!< Input FIFO service raw interrupt status*/
+#define CRYP_FLAG_INRIS 0x01000001U /*!< Input FIFO service raw interrupt status*/
#else /* AES*/
/* status flags */
#define CRYP_FLAG_BUSY AES_SR_BUSY /*!< GCM process suspension forbidden */
@@ -312,7 +334,18 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
/**
* @}
*/
-
+
+/** @defgroup CRYP_Configuration_Skip CRYP Key and IV Configuration Skip Mode
+ * @{
+ */
+
+#define CRYP_KEYIVCONFIG_ALWAYS 0x00000000U /*!< Peripheral Key and IV configuration to do systematically */
+#define CRYP_KEYIVCONFIG_ONCE 0x00000001U /*!< Peripheral Key and IV configuration to do only once */
+
+/**
+ * @}
+ */
+
/**
* @}
@@ -336,7 +369,7 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
#else
#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_CRYP_STATE_RESET)
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
-
+
/**
* @brief Enable/Disable the CRYP peripheral.
* @param __HANDLE__: specifies the CRYP handle.
@@ -345,33 +378,33 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
#if defined(CRYP)
#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_CRYPEN)
#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CRYP_CR_CRYPEN)
-#else /* AES*/
+#else /* AES*/
#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= AES_CR_EN)
#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~AES_CR_EN)
-#endif /* End AES or CRYP */
+#endif /* End AES or CRYP */
/** @brief Check whether the specified CRYP status flag is set or not.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values for TinyAES:
- * @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden
- * @arg @ref CRYP_IT_WRERR Write Error
- * @arg @ref CRYP_IT_RDERR Read Error
- * @arg @ref CRYP_IT_CCF Computation Complete
+ * @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden
+ * @arg @ref CRYP_IT_WRERR Write Error
+ * @arg @ref CRYP_IT_RDERR Read Error
+ * @arg @ref CRYP_IT_CCF Computation Complete
* This parameter can be one of the following values for CRYP:
- * @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
- * or a key preparation (for AES decryption).
+ * @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
+ * or a key preparation (for AES decryption).
* @arg CRYP_FLAG_IFEM: Input FIFO is empty
* @arg CRYP_FLAG_IFNF: Input FIFO is not full
* @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
* @arg CRYP_FLAG_OFNE: Output FIFO is not empty
* @arg CRYP_FLAG_OFFU: Output FIFO is full
- * @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
- * @retval The state of __FLAG__ (TRUE or FALSE).
+ * @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
+ * @retval The state of __FLAG__ (TRUE or FALSE).
*/
#define CRYP_FLAG_MASK 0x0000001FU
-#if defined(CRYP)
+#if defined(CRYP)
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
- ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
+ ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
#else /* AES*/
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
#endif /* End AES or CRYP */
@@ -380,12 +413,12 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
* @param __FLAG__: specifies the flag to clear.
* This parameter can be one of the following values:
* @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
- * @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
+ * @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
* @param __HANDLE__: specifies the CRYP handle.
* @retval None
*/
-#if defined(AES)
+#if defined(AES)
#define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT((__HANDLE__)->Instance->CR, (__FLAG__))
@@ -393,37 +426,39 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
* @param __INTERRUPT__: CRYP interrupt source to check
* This parameter can be one of the following values for TinyAES:
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
- * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
+ * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
* @param __HANDLE__: specifies the CRYP handle.
* @retval State of interruption (TRUE or FALSE).
*/
-#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\
+ & (__INTERRUPT__)) == (__INTERRUPT__))
#endif /* AES */
/** @brief Check whether the specified CRYP interrupt is set or not.
* @param __INTERRUPT__: specifies the interrupt to check.
* This parameter can be one of the following values for TinyAES:
- * @arg @ref CRYP_IT_WRERR Write Error
- * @arg @ref CRYP_IT_RDERR Read Error
- * @arg @ref CRYP_IT_CCF Computation Complete
+ * @arg @ref CRYP_IT_WRERR Write Error
+ * @arg @ref CRYP_IT_RDERR Read Error
+ * @arg @ref CRYP_IT_CCF Computation Complete
* This parameter can be one of the following values for CRYP:
* @arg CRYP_IT_INI: Input FIFO service masked interrupt status
* @arg CRYP_IT_OUTI: Output FIFO service masked interrupt status
* @param __HANDLE__: specifies the CRYP handle.
* @retval The state of __INTERRUPT__ (TRUE or FALSE).
*/
-#if defined(CRYP)
-#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
+#if defined(CRYP)
+#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR\
+ & (__INTERRUPT__)) == (__INTERRUPT__))
#else /* AES*/
#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
#endif /* End AES or CRYP */
/**
- * @brief Enable the CRYP interrupt.
+ * @brief Enable the CRYP interrupt.
* @param __INTERRUPT__: CRYP Interrupt.
- * This parameter can be one of the following values for TinyAES:
+ * This parameter can be one of the following values for TinyAES:
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
* This parameter can be one of the following values for CRYP:
@@ -432,16 +467,16 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
* @param __HANDLE__: specifies the CRYP handle.
* @retval None
*/
-#if defined(CRYP)
+#if defined(CRYP)
#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__))
-#else /* AES*/
+#else /* AES*/
#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
#endif /* End AES or CRYP */
/**
* @brief Disable the CRYP interrupt.
* @param __INTERRUPT__: CRYP Interrupt.
- * This parameter can be one of the following values for TinyAES:
+ * This parameter can be one of the following values for TinyAES:
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
* This parameter can be one of the following values for CRYP:
@@ -450,9 +485,9 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
* @param __HANDLE__: specifies the CRYP handle.
* @retval None
*/
-#if defined(CRYP)
+#if defined(CRYP)
#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__))
-#else /* AES*/
+#else /* AES*/
#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
#endif /* End AES or CRYP */
@@ -462,7 +497,7 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
#if defined (CRYP_CR_ALGOMODE_AES_GCM)|| defined (AES)
/* Include CRYP HAL Extended module */
#include "stm32f4xx_hal_cryp_ex.h"
-#endif /* AES or GCM CCM defined*/
+#endif /* AES or GCM CCM defined*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
* @{
@@ -470,28 +505,31 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
/** @addtogroup CRYP_Exported_Functions_Group1
* @{
- */
+ */
HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
-HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf );
-HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf );
+HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
+HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID,
+ pCRYP_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
/**
* @}
- */
+ */
/** @addtogroup CRYP_Exported_Functions_Group2
* @{
- */
+ */
/* encryption/decryption ***********************************/
-HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
+ uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
@@ -499,12 +537,12 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu
/**
* @}
- */
+ */
/** @addtogroup CRYP_Exported_Functions_Group3
* @{
- */
+ */
/* Interrupt Handler functions **********************************************/
void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
@@ -515,8 +553,8 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
/**
* @}
- */
-
+ */
+
/**
* @}
*/
@@ -532,32 +570,32 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
#if defined(CRYP)
#if defined (CRYP_CR_ALGOMODE_AES_GCM)
#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_DES_ECB) || \
- ((ALGORITHM) == CRYP_DES_CBC) || \
- ((ALGORITHM) == CRYP_TDES_ECB) || \
- ((ALGORITHM) == CRYP_TDES_CBC) || \
- ((ALGORITHM) == CRYP_AES_ECB) || \
- ((ALGORITHM) == CRYP_AES_CBC) || \
- ((ALGORITHM) == CRYP_AES_CTR) || \
- ((ALGORITHM) == CRYP_AES_GCM) || \
- ((ALGORITHM) == CRYP_AES_CCM))
+ ((ALGORITHM) == CRYP_DES_CBC) || \
+ ((ALGORITHM) == CRYP_TDES_ECB) || \
+ ((ALGORITHM) == CRYP_TDES_CBC) || \
+ ((ALGORITHM) == CRYP_AES_ECB) || \
+ ((ALGORITHM) == CRYP_AES_CBC) || \
+ ((ALGORITHM) == CRYP_AES_CTR) || \
+ ((ALGORITHM) == CRYP_AES_GCM) || \
+ ((ALGORITHM) == CRYP_AES_CCM))
#else /*NO GCM CCM */
#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_DES_ECB) || \
- ((ALGORITHM) == CRYP_DES_CBC) || \
- ((ALGORITHM) == CRYP_TDES_ECB) || \
- ((ALGORITHM) == CRYP_TDES_CBC) || \
- ((ALGORITHM) == CRYP_AES_ECB) || \
- ((ALGORITHM) == CRYP_AES_CBC) || \
- ((ALGORITHM) == CRYP_AES_CTR))
-#endif /* GCM CCM defined*/
+ ((ALGORITHM) == CRYP_DES_CBC) || \
+ ((ALGORITHM) == CRYP_TDES_ECB) || \
+ ((ALGORITHM) == CRYP_TDES_CBC) || \
+ ((ALGORITHM) == CRYP_AES_ECB) || \
+ ((ALGORITHM) == CRYP_AES_CBC) || \
+ ((ALGORITHM) == CRYP_AES_CTR))
+#endif /* GCM CCM defined*/
#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B) || \
((KEYSIZE) == CRYP_KEYSIZE_192B) || \
((KEYSIZE) == CRYP_KEYSIZE_256B))
-#else /* AES*/
+#else /* AES*/
#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_AES_ECB) || \
- ((ALGORITHM) == CRYP_AES_CBC) || \
- ((ALGORITHM) == CRYP_AES_CTR) || \
- ((ALGORITHM) == CRYP_AES_GCM_GMAC)|| \
- ((ALGORITHM) == CRYP_AES_CCM))
+ ((ALGORITHM) == CRYP_AES_CBC) || \
+ ((ALGORITHM) == CRYP_AES_CTR) || \
+ ((ALGORITHM) == CRYP_AES_GCM_GMAC)|| \
+ ((ALGORITHM) == CRYP_AES_CCM))
#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B) || \
@@ -569,6 +607,8 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
((DATATYPE) == CRYP_DATATYPE_8B) || \
((DATATYPE) == CRYP_DATATYPE_1B))
+#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
+ ((CONFIG) == CRYP_KEYIVCONFIG_ONCE))
/**
* @}
*/
@@ -585,7 +625,7 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
/**
* @}
- */
+ */
/* Private defines -----------------------------------------------------------*/
/** @defgroup CRYP_Private_Defines CRYP Private Defines
* @{
@@ -593,8 +633,8 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
/**
* @}
- */
-
+ */
+
/* Private variables ---------------------------------------------------------*/
/** @defgroup CRYP_Private_Variables CRYP Private Variables
* @{
@@ -602,7 +642,7 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
/**
* @}
- */
+ */
/* Private functions prototypes ----------------------------------------------*/
/** @defgroup CRYP_Private_Functions_Prototypes CRYP Private Functions Prototypes
* @{
@@ -620,21 +660,21 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
/**
* @}
*/
-
-
+
+
/**
* @}
- */
+ */
/**
* @}
- */
+ */
#endif /* TinyAES or CRYP*/
/**
* @}
- */
+ */
#ifdef __cplusplus
}
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cryp_ex.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cryp_ex.h
index f93a3b789a..251e94b1da 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cryp_ex.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cryp_ex.h
@@ -6,23 +6,23 @@
******************************************************************************
* @attention
*
- *
*
* This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
+ * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_CRYP_EX_H
#define __STM32F4xx_HAL_CRYP_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -35,14 +35,14 @@
/** @addtogroup CRYPEx
* @{
*/
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
/** @defgroup CRYPEx_Exported_Types CRYPEx Exported types
* @{
*/
/**
* @}
- */
+ */
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRYPEx_Exported_Constants CRYPEx Exported constants
* @{
@@ -50,8 +50,8 @@
/**
* @}
- */
-
+ */
+
/* Private types -------------------------------------------------------------*/
/** @defgroup CRYPEx_Private_Types CRYPEx Private Types
* @{
@@ -59,7 +59,7 @@
/**
* @}
- */
+ */
/* Private variables ---------------------------------------------------------*/
/** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables
@@ -68,7 +68,7 @@
/**
* @}
- */
+ */
/* Private constants ---------------------------------------------------------*/
/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
@@ -77,17 +77,17 @@
/**
* @}
- */
+ */
/* Private macros ------------------------------------------------------------*/
/** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros
* @{
*/
- /**
+/**
* @}
- */
-
+ */
+
/* Private functions ---------------------------------------------------------*/
/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
* @{
@@ -104,7 +104,7 @@
#if defined (CRYP) || defined (AES)
/** @addtogroup CRYPEx_Exported_Functions_Group1
* @{
- */
+ */
HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
/**
@@ -112,10 +112,10 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
*/
#endif /* CRYP||AES */
-#if defined (AES)
+#if defined (AES)
/** @addtogroup CRYPEx_Exported_Functions_Group2
* @{
- */
+ */
void HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
void HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
/**
@@ -125,16 +125,16 @@ void HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
/**
* @}
- */
-
+ */
+
/**
* @}
- */
+ */
/**
* @}
- */
-
+ */
+
#ifdef __cplusplus
}
#endif
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac.h
index fc9ce32efb..a1f49eae9e 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- *
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -18,36 +18,34 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_DAC_H
-#define __STM32F4xx_HAL_DAC_H
+#ifndef STM32F4xx_HAL_DAC_H
+#define STM32F4xx_HAL_DAC_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
- defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
- defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx)
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
-/** @addtogroup STM32F4xx_HAL_Driver
- * @{
- */
+#if defined(DAC)
/** @addtogroup DAC
* @{
*/
/* Exported types ------------------------------------------------------------*/
+
/** @defgroup DAC_Exported_Types DAC Exported Types
* @{
*/
-/**
- * @brief HAL State structures definition
+/**
+ * @brief HAL State structures definition
*/
typedef enum
{
@@ -56,16 +54,17 @@ typedef enum
HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */
HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */
HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */
-}HAL_DAC_StateTypeDef;
-
-/**
- * @brief DAC handle Structure definition
+
+} HAL_DAC_StateTypeDef;
+
+/**
+ * @brief DAC handle Structure definition
*/
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
typedef struct __DAC_HandleTypeDef
#else
typedef struct
-#endif
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
{
DAC_TypeDef *Instance; /*!< Register base address */
@@ -80,32 +79,35 @@ typedef struct
__IO uint32_t ErrorCode; /*!< DAC Error code */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
- void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
- void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
- void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
- void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
- void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
- void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
- void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
- void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
-
- void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac);
- void (* MspDeInitCallback ) (struct __DAC_HandleTypeDef *hdac);
+ void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
+ void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
+ void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
+ void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
+#if defined(DAC_CHANNEL2_SUPPORT)
+ void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
+ void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
+ void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
+ void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+ void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac);
+ void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-}DAC_HandleTypeDef;
+} DAC_HandleTypeDef;
-/**
- * @brief DAC Configuration regular Channel structure definition
+/**
+ * @brief DAC Configuration regular Channel structure definition
*/
typedef struct
{
- uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
- This parameter can be a value of @ref DAC_trigger_selection */
+ uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
+ This parameter can be a value of @ref DAC_trigger_selection */
- uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
- This parameter can be a value of @ref DAC_output_buffer */
-}DAC_ChannelConfTypeDef;
+ uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+ This parameter can be a value of @ref DAC_output_buffer */
+
+} DAC_ChannelConfTypeDef;
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/**
@@ -117,25 +119,29 @@ typedef enum
HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */
HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */
HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */
+#if defined(DAC_CHANNEL2_SUPPORT)
HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */
HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */
HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */
HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */
- HAL_DAC_MSP_INIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
- HAL_DAC_MSP_DEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
+#endif /* DAC_CHANNEL2_SUPPORT */
+ HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
+ HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */
-}HAL_DAC_CallbackIDTypeDef;
+} HAL_DAC_CallbackIDTypeDef;
/**
* @brief HAL DAC Callback pointer definition
*/
typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
+
/** @defgroup DAC_Exported_Constants DAC Exported Constants
* @{
*/
@@ -144,77 +150,89 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
* @{
*/
#define HAL_DAC_ERROR_NONE 0x00U /*!< No error */
-#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DAM underrun error */
-#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DAM underrun error */
+#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DMA underrun error */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DMA underrun error */
+#endif /* DAC_CHANNEL2_SUPPORT */
#define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */
+#define HAL_DAC_ERROR_TIMEOUT 0x08U /*!< Timeout error */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
#define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
/**
* @}
*/
-/** @defgroup DAC_trigger_selection DAC Trigger Selection
+/** @defgroup DAC_trigger_selection DAC trigger selection
* @{
*/
+#define DAC_TRIGGER_NONE 0x00000000UL /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */
+#define DAC_TRIGGER_T2_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T6_TRGO ( DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */
+#define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_SOFTWARE (DAC_CR_TSEL1 | DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */
-#define DAC_TRIGGER_NONE 0x00000000U /*!< Conversion is automatic once the DAC1_DHRxxxx register
- has been loaded, and not by external trigger */
-#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T8_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
-
-#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
/**
* @}
*/
-/** @defgroup DAC_output_buffer DAC Output Buffer
+/** @defgroup DAC_output_buffer DAC output buffer
* @{
*/
#define DAC_OUTPUTBUFFER_ENABLE 0x00000000U
-#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
+#define DAC_OUTPUTBUFFER_DISABLE (DAC_CR_BOFF1)
+
/**
* @}
*/
-/** @defgroup DAC_Channel_selection DAC Channel Selection
+/** @defgroup DAC_Channel_selection DAC Channel selection
* @{
*/
#define DAC_CHANNEL_1 0x00000000U
+#if defined(DAC_CHANNEL2_SUPPORT)
#define DAC_CHANNEL_2 0x00000010U
+#endif /* DAC_CHANNEL2_SUPPORT */
/**
* @}
*/
-/** @defgroup DAC_data_alignment DAC Data Alignment
+/** @defgroup DAC_data_alignment DAC data alignment
* @{
*/
#define DAC_ALIGN_12B_R 0x00000000U
#define DAC_ALIGN_12B_L 0x00000004U
#define DAC_ALIGN_8B_R 0x00000008U
+
/**
* @}
*/
-/** @defgroup DAC_flags_definition DAC Flags Definition
+/** @defgroup DAC_flags_definition DAC flags definition
* @{
- */
-#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
-#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
+ */
+#define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)
+#endif /* DAC_CHANNEL2_SUPPORT */
+
/**
* @}
*/
-/** @defgroup DAC_IT_definition DAC IT Definition
+/** @defgroup DAC_IT_definition DAC IT definition
* @{
- */
-#define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
-#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
+ */
+#define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1)
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2)
+#endif /* DAC_CHANNEL2_SUPPORT */
+
/**
* @}
*/
@@ -224,233 +242,241 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
*/
/* Exported macro ------------------------------------------------------------*/
+
/** @defgroup DAC_Exported_Macros DAC Exported Macros
* @{
*/
-/** @brief Reset DAC handle state
+/** @brief Reset DAC handle state.
* @param __HANDLE__ specifies the DAC handle.
* @retval None
*/
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \
- (__HANDLE__)->State = HAL_DAC_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
+#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_DAC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
#else
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-/** @brief Enable the DAC channel
+/** @brief Enable the DAC channel.
* @param __HANDLE__ specifies the DAC handle.
* @param __DAC_Channel__ specifies the DAC channel
* @retval None
*/
-#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
+#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
+ ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
-/** @brief Disable the DAC channel
+/** @brief Disable the DAC channel.
* @param __HANDLE__ specifies the DAC handle
* @param __DAC_Channel__ specifies the DAC channel.
* @retval None
*/
-#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
+#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
+ ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
-/** @brief Enable the DAC interrupt
+/** @brief Set DHR12R1 alignment.
+ * @param __ALIGNMENT__ specifies the DAC alignment
+ * @retval None
+ */
+#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__))
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/** @brief Set DHR12R2 alignment.
+ * @param __ALIGNMENT__ specifies the DAC alignment
+ * @retval None
+ */
+#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__))
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/** @brief Set DHR12RD alignment.
+ * @param __ALIGNMENT__ specifies the DAC alignment
+ * @retval None
+ */
+#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__))
+
+/** @brief Enable the DAC interrupt.
* @param __HANDLE__ specifies the DAC handle
* @param __INTERRUPT__ specifies the DAC interrupt.
+ * This parameter can be any combination of the following values:
+ * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
+ * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
* @retval None
*/
#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
-/** @brief Disable the DAC interrupt
+/** @brief Disable the DAC interrupt.
* @param __HANDLE__ specifies the DAC handle
* @param __INTERRUPT__ specifies the DAC interrupt.
+ * This parameter can be any combination of the following values:
+ * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
+ * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
* @retval None
*/
#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
-/** @brief Checks if the specified DAC interrupt source is enabled or disabled.
+/** @brief Check whether the specified DAC interrupt source is enabled or not.
* @param __HANDLE__ DAC handle
* @param __INTERRUPT__ DAC interrupt source to check
* This parameter can be any combination of the following values:
- * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
- * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
+ * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
+ * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
* @retval State of interruption (SET or RESET)
*/
-#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\
+ & (__INTERRUPT__)) == (__INTERRUPT__))
/** @brief Get the selected DAC's flag status.
* @param __HANDLE__ specifies the DAC handle.
- * @param __FLAG__ specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
- * @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
+ * @param __FLAG__ specifies the DAC flag to get.
+ * This parameter can be any combination of the following values:
+ * @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
+ * @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
* @retval None
*/
#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clear the DAC's flag.
* @param __HANDLE__ specifies the DAC handle.
- * @param __FLAG__ specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
- * @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
+ * @param __FLAG__ specifies the DAC flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
+ * @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
* @retval None
*/
#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
+
/**
* @}
*/
-/* Include DAC HAL Extension module */
-#include "stm32f4xx_hal_dac_ex.h"
+/* Private macro -------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DAC_Exported_Functions
+/** @defgroup DAC_Private_Macros DAC Private Macros
* @{
*/
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
+ ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
+ ((CHANNEL) == DAC_CHANNEL_2))
+#else
+#define IS_DAC_CHANNEL(CHANNEL) ((CHANNEL) == DAC_CHANNEL_1)
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
+ ((ALIGN) == DAC_ALIGN_12B_L) || \
+ ((ALIGN) == DAC_ALIGN_8B_R))
+
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL)
-/** @addtogroup DAC_Exported_Functions_Group1
- * @{
- */
-/* Initialization/de-initialization functions *********************************/
-HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
-HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
-void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
-void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
/**
* @}
*/
-/** @addtogroup DAC_Exported_Functions_Group2
+/* Include DAC HAL Extended module */
+#include "stm32f4xx_hal_dac_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup DAC_Exported_Functions
* @{
*/
-/* I/O operation functions ****************************************************/
-HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
-HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
-/**
- * @}
- */
-/** @addtogroup DAC_Exported_Functions_Group3
+/** @addtogroup DAC_Exported_Functions_Group1
* @{
*/
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac);
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac);
+void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac);
+void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
+
/**
* @}
*/
-/** @addtogroup DAC_Exported_Functions_Group4
+/** @addtogroup DAC_Exported_Functions_Group2
* @{
*/
-/* Peripheral State functions *************************************************/
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
-void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
-uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
-
-void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
-void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
+ uint32_t Alignment);
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
+
+void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac);
+void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac);
void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/* DAC callback registering/unregistering */
-HAL_StatusTypeDef HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
+ pDAC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-/**
- * @}
- */
/**
* @}
*/
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup DAC_Private_Constants DAC Private Constants
+
+/** @addtogroup DAC_Exported_Functions_Group3
* @{
*/
-
+/* Peripheral Control functions ***********************************************/
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
/**
* @}
*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DAC_Private_Macros DAC Private Macros
+/** @addtogroup DAC_Exported_Functions_Group4
* @{
*/
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
-#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
- ((ALIGN) == DAC_ALIGN_12B_L) || \
- ((ALIGN) == DAC_ALIGN_8B_R))
-#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
- ((CHANNEL) == DAC_CHANNEL_2))
-#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
- ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
-
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
- ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
- ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
-
-/** @brief Set DHR12R1 alignment
- * @param __ALIGNMENT__ specifies the DAC alignment
- * @retval None
- */
-#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008U + (__ALIGNMENT__))
-
-/** @brief Set DHR12R2 alignment
- * @param __ALIGNMENT__ specifies the DAC alignment
- * @retval None
- */
-#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014U) + (__ALIGNMENT__))
+/* Peripheral State and Error functions ***************************************/
+HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac);
+uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
-/** @brief Set DHR12RD alignment
- * @param __ALIGNMENT__ specifies the DAC alignment
- * @retval None
+/**
+ * @}
*/
-#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020U + (__ALIGNMENT__))
/**
* @}
*/
-/* Private functions ---------------------------------------------------------*/
/** @defgroup DAC_Private_Functions DAC Private Functions
* @{
*/
+void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
+void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
+void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
- STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
- STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx ||\
- STM32F413xx || STM32F423xx */
/**
* @}
*/
+#endif /* DAC */
+
/**
* @}
*/
-
+
#ifdef __cplusplus
}
#endif
-#endif /*__STM32F4xx_HAL_DAC_H */
+
+#endif /* STM32F4xx_HAL_DAC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac_ex.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac_ex.h
index 4e9793a561..03159d4fe5 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac_ex.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac_ex.h
@@ -1,12 +1,12 @@
/**
******************************************************************************
- * @file stm32f4xx_hal_dac.h
+ * @file stm32f4xx_hal_dac_ex.h
* @author MCD Application Team
- * @brief Header file of DAC HAL Extension module.
+ * @brief Header file of DAC HAL Extended module.
******************************************************************************
* @attention
*
- *
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -18,89 +18,66 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_DAC_EX_H
-#define __STM32F4xx_HAL_DAC_EX_H
+#ifndef STM32F4xx_HAL_DAC_EX_H
+#define STM32F4xx_HAL_DAC_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
- defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
- defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx)
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
-/** @addtogroup STM32F4xx_HAL_Driver
- * @{
- */
+#if defined(DAC)
/** @addtogroup DACEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DACEx_Exported_Constants DAC Exported Constants
- * @{
- */
-/** @defgroup DACEx_lfsrunmask_triangleamplitude DAC LFS Run Mask Triangle Amplitude
- * @{
- */
-#define DAC_LFSRUNMASK_BIT0 0x00000000U /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
-#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
-#define DAC_TRIANGLEAMPLITUDE_1 0x00000000U /*!< Select max triangle amplitude of 1 */
-#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
-#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
-#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
-#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
-#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
-#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
-#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
-#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
-#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
-#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
-#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
/**
- * @}
+ * @brief HAL State structures definition
*/
-/**
- * @}
- */
+/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DACEx_Exported_Functions
+/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
* @{
*/
-/** @addtogroup DACEx_Exported_Functions_Group1
+/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude
* @{
*/
-/* Extension features functions ***********************************************/
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
-HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
+#define DAC_LFSRUNMASK_BIT0 0x00000000UL /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TRIANGLEAMPLITUDE_1 0x00000000UL /*!< Select max triangle amplitude of 1 */
+#define DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
+#define DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 7 */
+#define DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
+#define DAC_TRIANGLEAMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Select max triangle amplitude of 31 */
+#define DAC_TRIANGLEAMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
+#define DAC_TRIANGLEAMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 127 */
+#define DAC_TRIANGLEAMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
+#define DAC_TRIANGLEAMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Select max triangle amplitude of 511 */
+#define DAC_TRIANGLEAMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TRIANGLEAMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TRIANGLEAMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
-void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
/**
* @}
*/
@@ -108,21 +85,25 @@ void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
/**
* @}
*/
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup DACEx_Private_Constants DAC Private Constants
- * @{
- */
-/**
- * @}
- */
+/* Exported macro ------------------------------------------------------------*/
+
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DACEx_Private_Macros DAC Private Macros
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup DACEx_Private_Macros DACEx Private Macros
* @{
*/
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+ ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
@@ -151,33 +132,76 @@ void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
* @}
*/
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup DACEx_Private_Functions DAC Private Functions
+/* Exported functions --------------------------------------------------------*/
+/* Extended features functions ***********************************************/
+
+/** @addtogroup DACEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DACEx_Exported_Functions_Group2
+ * @{
+ */
+/* IO operation functions *****************************************************/
+
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+#endif
+HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac);
+HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac);
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac);
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+#endif
+void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac);
+void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac);
+void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac);
+void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DACEx_Private_Functions
* @{
*/
+#if defined(DAC_CHANNEL2_SUPPORT)
+/* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */
+/* are called by HAL_DAC_Start_DMA */
void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
-void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
+void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
+#endif /* DAC_CHANNEL2_SUPPORT */
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
- STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
- STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx ||\
- STM32F413xx || STM32F423xx */
/**
* @}
*/
+#endif /* DAC */
+
/**
* @}
*/
-
+
#ifdef __cplusplus
}
#endif
-#endif /*__STM32F4xx_HAL_DAC_EX_H */
+#endif /* STM32F4xx_HAL_DAC_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dcmi.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dcmi.h
index 021f37e4ee..2a9edb6c47 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dcmi.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dcmi.h
@@ -48,6 +48,16 @@
/** @defgroup DCMI_Exported_Types DCMI Exported Types
* @{
*/
+/**
+ * @brief DCMI Embedded Synchronisation CODE Init structure definition
+ */
+typedef struct
+{
+ uint8_t FrameStartUnmask; /*!< Specifies the frame start delimiter unmask. */
+ uint8_t LineStartUnmask; /*!< Specifies the line start delimiter unmask. */
+ uint8_t LineEndUnmask; /*!< Specifies the line end delimiter unmask. */
+ uint8_t FrameEndUnmask; /*!< Specifies the frame end delimiter unmask. */
+}DCMI_SyncUnmaskTypeDef;
/**
* @brief HAL DCMI State structures definition
*/
@@ -458,6 +468,7 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi);
HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask);
/**
* @}
*/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h
index e32e362ddd..975f70bd4b 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h
@@ -107,7 +107,14 @@ typedef enum
}while (0U)
#endif /* USE_RTOS */
-#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
+ #ifndef __weak
+ #define __weak __attribute__((weak))
+ #endif
+ #ifndef __packed
+ #define __packed __attribute__((packed))
+ #endif
+#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
@@ -118,7 +125,14 @@ typedef enum
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
-#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
+ #ifndef __ALIGN_BEGIN
+ #define __ALIGN_BEGIN
+ #endif
+ #ifndef __ALIGN_END
+ #define __ALIGN_END __attribute__ ((aligned (4)))
+ #endif
+#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif /* __ALIGN_END */
@@ -130,7 +144,7 @@ typedef enum
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
- #if defined (__CC_ARM) /* ARM Compiler */
+ #if defined (__CC_ARM) /* ARM Compiler V5*/
#define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
@@ -142,9 +156,9 @@ typedef enum
/**
* @brief __RAM_FUNC definition
*/
-#if defined ( __CC_ARM )
-/* ARM Compiler
- ------------
+#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+/* ARM Compiler V4/V5 and V6
+ --------------------------
RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate source module.
Using the 'Options for File' dialog you can simply change the 'Code / Const'
@@ -174,9 +188,9 @@ typedef enum
/**
* @brief __NOINLINE definition
*/
-#if defined ( __CC_ARM ) || defined ( __GNUC__ )
-/* ARM & GNUCompiler
- ----------------
+#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
+/* ARM V4/V5 and V6 & GNU Compiler
+ -------------------------------
*/
#define __NOINLINE __attribute__ ( (noinline) )
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma2d.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma2d.h
index 5bb7b6dfba..158ed67d0e 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma2d.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma2d.h
@@ -22,11 +22,9 @@
#define STM32F4xx_HAL_DMA2D_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-#if defined (DMA2D)
-
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -34,6 +32,8 @@
* @{
*/
+#if defined (DMA2D)
+
/** @addtogroup DMA2D DMA2D
* @brief DMA2D HAL module driver
* @{
@@ -71,7 +71,8 @@ typedef struct
This parameter can be one value of @ref DMA2D_Output_Color_Mode. */
uint32_t OutputOffset; /*!< Specifies the Offset value.
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
+ This parameter must be a number between
+ Min_Data = 0x0000 and Max_Data = 0x3FFF. */
@@ -85,7 +86,8 @@ typedef struct
typedef struct
{
uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset.
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
+ This parameter must be a number between
+ Min_Data = 0x0000 and Max_Data = 0x3FFF. */
uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode.
This parameter can be one value of @ref DMA2D_Input_Color_Mode. */
@@ -93,9 +95,12 @@ typedef struct
uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode.
This parameter can be one value of @ref DMA2D_Alpha_Mode. */
- uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below.
- @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between
+ uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value
+ in case of A8 or A4 color mode.
+ This parameter must be a number between Min_Data = 0x00
+ and Max_Data = 0xFF except for the color modes detailed below.
+ @note In case of A8 or A4 color mode (ARGB),
+ this parameter must be a number between
Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where
- InputAlpha[24:31] is the alpha value ALPHA[0:7]
- InputAlpha[16:23] is the red value RED[0:7]
@@ -116,46 +121,46 @@ typedef enum
HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */
HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */
-}HAL_DMA2D_StateTypeDef;
+} HAL_DMA2D_StateTypeDef;
/**
* @brief DMA2D handle Structure definition
*/
typedef struct __DMA2D_HandleTypeDef
{
- DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */
+ DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */
- DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */
+ DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */
- void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback. */
+ void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer complete callback. */
- void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback. */
+ void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer error callback. */
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
- void (* LineEventCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D line event callback. */
+ void (* LineEventCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D line event callback. */
- void (* CLUTLoadingCpltCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D CLUT loading completion callback. */
+ void (* CLUTLoadingCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D CLUT loading completion callback */
- void (* MspInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp Init callback. */
+ void (* MspInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp Init callback. */
- void (* MspDeInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp DeInit callback. */
+ void (* MspDeInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp DeInit callback. */
#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
- DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
+ DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
- HAL_LockTypeDef Lock; /*!< DMA2D lock. */
+ HAL_LockTypeDef Lock; /*!< DMA2D lock. */
- __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */
+ __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */
- __IO uint32_t ErrorCode; /*!< DMA2D error code. */
+ __IO uint32_t ErrorCode; /*!< DMA2D error code. */
} DMA2D_HandleTypeDef;
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
/**
* @brief HAL DMA2D Callback pointer definition
*/
-typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Pointer to a DMA2D common callback function */
+typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d); /*!< Pointer to a DMA2D common callback function */
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
/**
* @}
@@ -226,10 +231,10 @@ typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Poin
/** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode
* @{
*/
-#define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */
+#define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */
#define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */
#define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value
- with original alpha channel value */
+ with original alpha channel value */
/**
* @}
*/
@@ -277,7 +282,8 @@ typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Poin
/** @defgroup DMA2D_Aliases DMA2D API Aliases
* @{
*/
-#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */
+#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort
+ for compatibility with legacy code */
/**
* @}
*/
@@ -294,7 +300,7 @@ typedef enum
HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U, /*!< DMA2D transfer error callback ID */
HAL_DMA2D_LINEEVENT_CB_ID = 0x04U, /*!< DMA2D line event callback ID */
HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U, /*!< DMA2D CLUT loading completion callback ID */
-}HAL_DMA2D_CallbackIDTypeDef;
+} HAL_DMA2D_CallbackIDTypeDef;
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
@@ -311,10 +317,10 @@ typedef enum
* @retval None
*/
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
-#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
+#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
}while(0)
#else
#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
@@ -420,12 +426,13 @@ typedef enum
/* Initialization and de-initialization functions *******************************/
HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
-HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
-void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
-void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d);
+void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d);
+void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID,
+ pDMA2D_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
@@ -439,14 +446,22 @@ HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_
*/
/* IO operation functions *******************************************************/
-HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
-HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
-HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
-HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
+ uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
+ uint32_t DstAddress, uint32_t Width, uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
+ uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
+ uint32_t DstAddress, uint32_t Width, uint32_t Height);
HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
+ uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
+ uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
@@ -566,13 +581,16 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
/** @defgroup DMA2D_Private_Macros DMA2D Private Macros
* @{
*/
-#define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER) || ((LAYER) == DMA2D_FOREGROUND_LAYER))
+#define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER)\
+ || ((LAYER) == DMA2D_FOREGROUND_LAYER))
#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
-#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \
- ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
+#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || \
+ ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \
+ ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || \
+ ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE)
@@ -580,11 +598,16 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
#define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
-#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \
- ((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
- ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \
- ((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \
- ((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \
+#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || \
+ ((INPUT_CM) == DMA2D_INPUT_RGB888) || \
+ ((INPUT_CM) == DMA2D_INPUT_RGB565) || \
+ ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
+ ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || \
+ ((INPUT_CM) == DMA2D_INPUT_L8) || \
+ ((INPUT_CM) == DMA2D_INPUT_AL44) || \
+ ((INPUT_CM) == DMA2D_INPUT_AL88) || \
+ ((INPUT_CM) == DMA2D_INPUT_L4) || \
+ ((INPUT_CM) == DMA2D_INPUT_A8) || \
((INPUT_CM) == DMA2D_INPUT_A4))
#define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
@@ -599,11 +622,11 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
#define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
- ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
- ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
+ ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
+ ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
- ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
- ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
+ ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
+ ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
/**
* @}
*/
@@ -612,12 +635,12 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
* @}
*/
+#endif /* defined (DMA2D) */
+
/**
* @}
*/
-#endif /* defined (DMA2D) */
-
#ifdef __cplusplus
}
#endif
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dsi.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dsi.h
index df61c5e30d..716dea17da 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dsi.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dsi.h
@@ -25,10 +25,11 @@
extern "C" {
#endif
-#if defined(DSI)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
+#if defined(DSI)
+
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
@@ -347,6 +348,9 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to
#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
/* Exported constants --------------------------------------------------------*/
+/** @defgroup DSI_Exported_Constants DSI Exported Constants
+ * @{
+ */
/** @defgroup DSI_DCS_Command DSI DCS Command
* @{
*/
@@ -908,10 +912,18 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to
* @}
*/
+/**
+ * @}
+ */
+
/* Exported macros -----------------------------------------------------------*/
+/** @defgroup DSI_Exported_Macros DSI Exported Macros
+ * @{
+ */
+
/**
* @brief Reset DSI handle state.
- * @param __HANDLE__: DSI handle
+ * @param __HANDLE__ DSI handle
* @retval None
*/
#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
@@ -1101,6 +1113,10 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to
*/
#define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER & (__INTERRUPT__))
+/**
+ * @}
+ */
+
/* Exported functions --------------------------------------------------------*/
/** @defgroup DSI_Exported_Functions DSI Exported Functions
* @{
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h
index 24dccffee3..857011236b 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h
@@ -44,9 +44,7 @@ extern "C" {
*/
typedef enum
{
- HAL_EXTI_COMMON_CB_ID = 0x00U,
- HAL_EXTI_RISING_CB_ID = 0x01U,
- HAL_EXTI_FALLING_CB_ID = 0x02U,
+ HAL_EXTI_COMMON_CB_ID = 0x00U
} EXTI_CallbackIDTypeDef;
/**
@@ -55,8 +53,7 @@ typedef enum
typedef struct
{
uint32_t Line; /*!< Exti line number */
- void (* RisingCallback)(void); /*!< Exti rising callback */
- void (* FallingCallback)(void); /*!< Exti falling callback */
+ void (* PendingCallback)(void); /*!< Exti pending callback */
} EXTI_HandleTypeDef;
/**
@@ -69,7 +66,10 @@ typedef struct
uint32_t Mode; /*!< The Exit Mode to be configured for a core.
This parameter can be a combination of @ref EXTI_Mode */
uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
- can be a value of @ref EXTI_Trigger */
+ can be a value of @ref EXTI_Trigger */
+ uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
+ This parameter is only possible for line 0 to 15. It
+ can be a value of @ref EXTI_GPIOSel */
} EXTI_ConfigTypeDef;
/**
@@ -84,29 +84,44 @@ typedef struct
/** @defgroup EXTI_Line EXTI Line
* @{
*/
-#define EXTI_LINE_0 EXTI_IMR_IM0 /*!< External interrupt line 0 */
-#define EXTI_LINE_1 EXTI_IMR_IM1 /*!< External interrupt line 1 */
-#define EXTI_LINE_2 EXTI_IMR_IM2 /*!< External interrupt line 2 */
-#define EXTI_LINE_3 EXTI_IMR_IM3 /*!< External interrupt line 3 */
-#define EXTI_LINE_4 EXTI_IMR_IM4 /*!< External interrupt line 4 */
-#define EXTI_LINE_5 EXTI_IMR_IM5 /*!< External interrupt line 5 */
-#define EXTI_LINE_6 EXTI_IMR_IM6 /*!< External interrupt line 6 */
-#define EXTI_LINE_7 EXTI_IMR_IM7 /*!< External interrupt line 7 */
-#define EXTI_LINE_8 EXTI_IMR_IM8 /*!< External interrupt line 8 */
-#define EXTI_LINE_9 EXTI_IMR_IM9 /*!< External interrupt line 9 */
-#define EXTI_LINE_10 EXTI_IMR_IM10 /*!< External interrupt line 10 */
-#define EXTI_LINE_11 EXTI_IMR_IM11 /*!< External interrupt line 11 */
-#define EXTI_LINE_12 EXTI_IMR_IM12 /*!< External interrupt line 12 */
-#define EXTI_LINE_13 EXTI_IMR_IM13 /*!< External interrupt line 13 */
-#define EXTI_LINE_14 EXTI_IMR_IM14 /*!< External interrupt line 14 */
-#define EXTI_LINE_15 EXTI_IMR_IM15 /*!< External interrupt line 15 */
-#define EXTI_LINE_16 EXTI_IMR_IM16 /*!< External interrupt line 16 Connected to the PVD Output */
-#define EXTI_LINE_17 EXTI_IMR_IM17 /*!< External interrupt line 17 Connected to the RTC Alarm event */
-#define EXTI_LINE_18 EXTI_IMR_IM18 /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */
-#define EXTI_LINE_19 EXTI_IMR_IM19 /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
-#define EXTI_LINE_20 EXTI_IMR_IM20 /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */
-#define EXTI_LINE_21 EXTI_IMR_IM21 /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
-#define EXTI_LINE_22 EXTI_IMR_IM22 /*!< External interrupt line 22 Connected to the RTC Wakeup event */
+#define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */
+#define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */
+#define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */
+#define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */
+#define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */
+#define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */
+#define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */
+#define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */
+#define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */
+#define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */
+#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */
+#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */
+#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */
+#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */
+#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */
+#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */
+#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */
+#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */
+#if defined(EXTI_IMR_IM18)
+#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */
+#else
+#define EXTI_LINE_18 (EXTI_RESERVED | 0x12u) /*!< No interrupt supported in this line */
+#endif /* EXTI_IMR_IM18 */
+#if defined(EXTI_IMR_IM19)
+#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
+#else
+#define EXTI_LINE_19 (EXTI_RESERVED | 0x13u) /*!< No interrupt supported in this line */
+#endif /* EXTI_IMR_IM19 */
+#if defined(EXTI_IMR_IM20)
+#define EXTI_LINE_20 (EXTI_CONFIG | 0x14u) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */
+#else
+#define EXTI_LINE_20 (EXTI_RESERVED | 0x14u) /*!< No interrupt supported in this line */
+#endif /* EXTI_IMR_IM20 */
+#define EXTI_LINE_21 (EXTI_CONFIG | 0x15u) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
+#define EXTI_LINE_22 (EXTI_CONFIG | 0x16u) /*!< External interrupt line 22 Connected to the RTC Wakeup event */
+#if defined(EXTI_IMR_IM23)
+#define EXTI_LINE_23 (EXTI_CONFIG | 0x17u) /*!< External interrupt line 23 Connected to the LPTIM1 asynchronous event */
+#endif /* EXTI_IMR_IM23 */
/**
* @}
@@ -115,8 +130,9 @@ typedef struct
/** @defgroup EXTI_Mode EXTI Mode
* @{
*/
-#define EXTI_MODE_INTERRUPT 0x00000000U
-#define EXTI_MODE_EVENT 0x00000004U
+#define EXTI_MODE_NONE 0x00000000u
+#define EXTI_MODE_INTERRUPT 0x00000001u
+#define EXTI_MODE_EVENT 0x00000002u
/**
* @}
*/
@@ -125,13 +141,50 @@ typedef struct
* @{
*/
-#define EXTI_TRIGGER_RISING 0x00000008U
-#define EXTI_TRIGGER_FALLING 0x0000000CU
-#define EXTI_TRIGGER_RISING_FALLING 0x00000010U
+#define EXTI_TRIGGER_NONE 0x00000000u
+#define EXTI_TRIGGER_RISING 0x00000001u
+#define EXTI_TRIGGER_FALLING 0x00000002u
+#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
/**
* @}
*/
-
+
+/** @defgroup EXTI_GPIOSel EXTI GPIOSel
+ * @brief
+ * @{
+ */
+#define EXTI_GPIOA 0x00000000u
+#define EXTI_GPIOB 0x00000001u
+#define EXTI_GPIOC 0x00000002u
+#if defined (GPIOD)
+#define EXTI_GPIOD 0x00000003u
+#endif /* GPIOD */
+#if defined (GPIOE)
+#define EXTI_GPIOE 0x00000004u
+#endif /* GPIOE */
+#if defined (GPIOF)
+#define EXTI_GPIOF 0x00000005u
+#endif /* GPIOF */
+#if defined (GPIOG)
+#define EXTI_GPIOG 0x00000006u
+#endif /* GPIOG */
+#if defined (GPIOH)
+#define EXTI_GPIOH 0x00000007u
+#endif /* GPIOH */
+#if defined (GPIOI)
+#define EXTI_GPIOI 0x00000008u
+#endif /* GPIOI */
+#if defined (GPIOJ)
+#define EXTI_GPIOJ 0x00000009u
+#endif /* GPIOJ */
+#if defined (GPIOK)
+#define EXTI_GPIOK 0x0000000Au
+#endif /* GPIOK */
+
+/**
+ * @}
+ */
+
/**
* @}
*/
@@ -149,6 +202,20 @@ typedef struct
/** @defgroup EXTI_Private_Constants EXTI Private Constants
* @{
*/
+/**
+ * @brief EXTI Line property definition
+ */
+#define EXTI_PROPERTY_SHIFT 24u
+#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
+#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
+#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
+#define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO)
+
+/**
+ * @brief EXTI bit usage
+ */
+#define EXTI_PIN_MASK 0x0000001Fu
+
/**
* @brief EXTI Mask for interrupt & event mode
*/
@@ -157,12 +224,16 @@ typedef struct
/**
* @brief EXTI Mask for trigger possibilities
*/
-#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING | EXTI_TRIGGER_RISING_FALLING)
+#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
/**
* @brief EXTI Line number
*/
+#if defined(EXTI_IMR_IM23)
+#define EXTI_LINE_NB 24UL
+#else
#define EXTI_LINE_NB 23UL
+#endif /* EXTI_IMR_IM23 */
/**
* @}
@@ -172,37 +243,70 @@ typedef struct
/** @defgroup EXTI_Private_Macros EXTI Private Macros
* @{
*/
-#define IS_EXTI_LINE(__LINE__) (((__LINE__) == EXTI_LINE_0) || \
- ((__LINE__) == EXTI_LINE_1) || \
- ((__LINE__) == EXTI_LINE_2) || \
- ((__LINE__) == EXTI_LINE_3) || \
- ((__LINE__) == EXTI_LINE_4) || \
- ((__LINE__) == EXTI_LINE_5) || \
- ((__LINE__) == EXTI_LINE_6) || \
- ((__LINE__) == EXTI_LINE_7) || \
- ((__LINE__) == EXTI_LINE_8) || \
- ((__LINE__) == EXTI_LINE_9) || \
- ((__LINE__) == EXTI_LINE_10) || \
- ((__LINE__) == EXTI_LINE_11) || \
- ((__LINE__) == EXTI_LINE_12) || \
- ((__LINE__) == EXTI_LINE_13) || \
- ((__LINE__) == EXTI_LINE_14) || \
- ((__LINE__) == EXTI_LINE_15) || \
- ((__LINE__) == EXTI_LINE_16) || \
- ((__LINE__) == EXTI_LINE_17) || \
- ((__LINE__) == EXTI_LINE_18) || \
- ((__LINE__) == EXTI_LINE_19) || \
- ((__LINE__) == EXTI_LINE_20) || \
- ((__LINE__) == EXTI_LINE_21) || \
- ((__LINE__) == EXTI_LINE_22))
-
-#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & ~EXTI_MODE_MASK) == 0x00U))
-
-#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U)
-
-#define IS_EXTI_PENDING_EDGE(__LINE__) (((__LINE__) == EXTI_TRIGGER_FALLING) || \
- ((__LINE__) == EXTI_TRIGGER_RISING) || \
- ((__LINE__) == EXTI_TRIGGER_RISING_FALLING))
+#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \
+ ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
+ (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
+ (((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
+
+#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \
+ (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))
+
+#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
+
+#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)
+
+#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
+
+#if !defined (GPIOD)
+#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
+ ((__PORT__) == EXTI_GPIOB) || \
+ ((__PORT__) == EXTI_GPIOC) || \
+ ((__PORT__) == EXTI_GPIOH))
+#elif !defined (GPIOE)
+#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
+ ((__PORT__) == EXTI_GPIOB) || \
+ ((__PORT__) == EXTI_GPIOC) || \
+ ((__PORT__) == EXTI_GPIOD) || \
+ ((__PORT__) == EXTI_GPIOH))
+#elif !defined (GPIOF)
+#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
+ ((__PORT__) == EXTI_GPIOB) || \
+ ((__PORT__) == EXTI_GPIOC) || \
+ ((__PORT__) == EXTI_GPIOD) || \
+ ((__PORT__) == EXTI_GPIOE) || \
+ ((__PORT__) == EXTI_GPIOH))
+#elif !defined (GPIOI)
+#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
+ ((__PORT__) == EXTI_GPIOB) || \
+ ((__PORT__) == EXTI_GPIOC) || \
+ ((__PORT__) == EXTI_GPIOD) || \
+ ((__PORT__) == EXTI_GPIOE) || \
+ ((__PORT__) == EXTI_GPIOF) || \
+ ((__PORT__) == EXTI_GPIOG) || \
+ ((__PORT__) == EXTI_GPIOH))
+#elif !defined (GPIOJ)
+#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
+ ((__PORT__) == EXTI_GPIOB) || \
+ ((__PORT__) == EXTI_GPIOC) || \
+ ((__PORT__) == EXTI_GPIOD) || \
+ ((__PORT__) == EXTI_GPIOE) || \
+ ((__PORT__) == EXTI_GPIOF) || \
+ ((__PORT__) == EXTI_GPIOG) || \
+ ((__PORT__) == EXTI_GPIOH) || \
+ ((__PORT__) == EXTI_GPIOI))
+#else
+#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
+ ((__PORT__) == EXTI_GPIOB) || \
+ ((__PORT__) == EXTI_GPIOC) || \
+ ((__PORT__) == EXTI_GPIOD) || \
+ ((__PORT__) == EXTI_GPIOE) || \
+ ((__PORT__) == EXTI_GPIOF) || \
+ ((__PORT__) == EXTI_GPIOG) || \
+ ((__PORT__) == EXTI_GPIOH) || \
+ ((__PORT__) == EXTI_GPIOI) || \
+ ((__PORT__) == EXTI_GPIOJ) || \
+ ((__PORT__) == EXTI_GPIOK))
+#endif /* GPIOD */
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U)
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c.h
index f0fd230e80..270a92b747 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c.h
@@ -496,7 +496,8 @@ typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint
*
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
-#define __HAL_FMPI2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_FMPI2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \
+ (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified FMPI2C flag is set or not.
* @param __HANDLE__ specifies the FMPI2C Handle.
@@ -522,7 +523,8 @@ typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint
* @retval The new state of __FLAG__ (SET or RESET).
*/
#define FMPI2C_FLAG_MASK (0x0001FFFFU)
-#define __HAL_FMPI2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+#define __HAL_FMPI2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \
+ (__FLAG__)) == (__FLAG__)) ? SET : RESET)
/** @brief Clear the FMPI2C pending flags which are cleared by writing 1 in a specific bit.
* @param __HANDLE__ specifies the FMPI2C Handle.
@@ -542,7 +544,7 @@ typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint
* @retval None
*/
#define __HAL_FMPI2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == FMPI2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
- : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
+ : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
/** @brief Enable the specified FMPI2C peripheral.
* @param __HANDLE__ specifies the FMPI2C Handle.
@@ -584,7 +586,8 @@ void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_FMPI2C_RegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, HAL_FMPI2C_CallbackIDTypeDef CallbackID, pFMPI2C_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FMPI2C_RegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, HAL_FMPI2C_CallbackIDTypeDef CallbackID,
+ pFMPI2C_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_FMPI2C_UnRegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, HAL_FMPI2C_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_FMPI2C_RegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2c, pFMPI2C_AddrCallbackTypeDef pCallback);
@@ -599,49 +602,70 @@ HAL_StatusTypeDef HAL_FMPI2C_UnRegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2
*/
/* IO operation functions ****************************************************/
/******* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout);
HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint32_t Trials,
+ uint32_t Timeout);
/******* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size);
HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-
-HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions);
HAL_StatusTypeDef HAL_FMPI2C_EnableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c);
HAL_StatusTypeDef HAL_FMPI2C_DisableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c);
HAL_StatusTypeDef HAL_FMPI2C_Master_Abort_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress);
/******* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size);
HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-
-HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions);
/**
* @}
*/
/** @addtogroup FMPI2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
- * @{
- */
+ * @{
+ */
/******* FMPI2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
void HAL_FMPI2C_EV_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c);
void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c);
@@ -733,7 +757,8 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c);
#define IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPI2C_OTHER_FRAME) || \
((REQUEST) == FMPI2C_OTHER_AND_LAST_FRAME))
-#define FMPI2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_RD_WRN)))
+#define FMPI2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
+ (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_RD_WRN)))
#define FMPI2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) >> 16U))
#define FMPI2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) >> 16U))
@@ -744,13 +769,15 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c);
#define IS_FMPI2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define IS_FMPI2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
-#define FMPI2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
+#define FMPI2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \
+ (uint16_t)(0xFF00U))) >> 8U)))
#define FMPI2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define FMPI2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPI2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & (~FMPI2C_CR2_RD_WRN)) : \
- (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN)))
+ (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN)))
-#define FMPI2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & FMPI2C_FLAG_MASK)) == ((__FLAG__) & FMPI2C_FLAG_MASK)) ? SET : RESET)
+#define FMPI2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & FMPI2C_FLAG_MASK)) == \
+ ((__FLAG__) & FMPI2C_FLAG_MASK)) ? SET : RESET)
#define FMPI2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
/**
* @}
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c_ex.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c_ex.h
index 2be2c288e2..326b05853a 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c_ex.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c_ex.h
@@ -39,7 +39,6 @@ extern "C" {
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
-
/** @defgroup FMPI2CEx_Exported_Constants FMPI2C Extended Exported Constants
* @{
*/
@@ -67,22 +66,49 @@ extern "C" {
*/
/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
+/** @defgroup FMPI2CEx_Exported_Macros FMPI2C Extended Exported Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
/** @addtogroup FMPI2CEx_Exported_Functions FMPI2C Extended Exported Functions
* @{
*/
-/** @addtogroup FMPI2CEx_Exported_Functions_Group1 Extended features functions
- * @brief Extended features functions
+/** @addtogroup FMPI2CEx_Exported_Functions_Group1 FMPI2C Extended Filter Mode Functions
* @{
*/
-
/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_FMPI2CEx_ConfigAnalogFilter(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t AnalogFilter);
HAL_StatusTypeDef HAL_FMPI2CEx_ConfigDigitalFilter(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t DigitalFilter);
+/**
+ * @}
+ */
+
+/** @addtogroup FMPI2CEx_Exported_Functions_Group2 FMPI2C Extended WakeUp Mode Functions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @addtogroup FMPI2CEx_Exported_Functions_Group3 FMPI2C Extended FastModePlus Functions
+ * @{
+ */
void HAL_FMPI2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
/* Private constants ---------------------------------------------------------*/
/** @defgroup FMPI2CEx_Private_Constants FMPI2C Extended Private Constants
@@ -98,17 +124,12 @@ void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
* @{
*/
#define IS_FMPI2C_ANALOG_FILTER(FILTER) (((FILTER) == FMPI2C_ANALOGFILTER_ENABLE) || \
- ((FILTER) == FMPI2C_ANALOGFILTER_DISABLE))
+ ((FILTER) == FMPI2C_ANALOGFILTER_DISABLE))
#define IS_FMPI2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define IS_FMPI2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (FMPI2C_FASTMODEPLUS_SCL)) == FMPI2C_FASTMODEPLUS_SCL) || \
- (((__CONFIG__) & (FMPI2C_FASTMODEPLUS_SDA)) == FMPI2C_FASTMODEPLUS_SDA))
-
-
-
-
-
+ (((__CONFIG__) & (FMPI2C_FASTMODEPLUS_SDA)) == FMPI2C_FASTMODEPLUS_SDA))
/**
* @}
*/
@@ -130,14 +151,6 @@ void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
* @}
*/
-/**
- * @}
- */
-
-/**
- * @}
- */
-
#endif /* FMPI2C_CR1_PE */
#ifdef __cplusplus
}
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus.h
new file mode 100644
index 0000000000..c0dce28974
--- /dev/null
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus.h
@@ -0,0 +1,764 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_fmpsmbus.h
+ * @author MCD Application Team
+ * @brief Header file of FMPSMBUS HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ *
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F4xx_HAL_FMPSMBUS_H
+#define STM32F4xx_HAL_FMPSMBUS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(FMPI2C_CR1_PE)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+#include "stm32f4xx_hal_fmpsmbus_ex.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FMPSMBUS
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FMPSMBUS_Exported_Types FMPSMBUS Exported Types
+ * @{
+ */
+
+/** @defgroup FMPSMBUS_Configuration_Structure_definition FMPSMBUS Configuration Structure definition
+ * @brief FMPSMBUS Configuration Structure definition
+ * @{
+ */
+typedef struct
+{
+ uint32_t Timing; /*!< Specifies the FMPSMBUS_TIMINGR_register value.
+ This parameter calculated by referring to FMPSMBUS initialization
+ section in Reference manual */
+ uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not.
+ This parameter can be a value of @ref FMPSMBUS_Analog_Filter */
+
+ uint32_t OwnAddress1; /*!< Specifies the first device own address.
+ This parameter can be a 7-bit or 10-bit address. */
+
+ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
+ This parameter can be a value of @ref FMPSMBUS_addressing_mode */
+
+ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
+ This parameter can be a value of @ref FMPSMBUS_dual_addressing_mode */
+
+ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
+ This parameter can be a 7-bit address. */
+
+ uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
+ This parameter can be a value of @ref FMPSMBUS_own_address2_masks. */
+
+ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
+ This parameter can be a value of @ref FMPSMBUS_general_call_addressing_mode. */
+
+ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
+ This parameter can be a value of @ref FMPSMBUS_nostretch_mode */
+
+ uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected.
+ This parameter can be a value of @ref FMPSMBUS_packet_error_check_mode */
+
+ uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected.
+ This parameter can be a value of @ref FMPSMBUS_peripheral_mode */
+
+ uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits FMPSMBUS_TIMEOUT_register value.
+ (Enable bits and different timeout values)
+ This parameter calculated by referring to FMPSMBUS initialization
+ section in Reference manual */
+} FMPSMBUS_InitTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HAL_state_definition HAL state definition
+ * @brief HAL State definition
+ * @{
+ */
+#define HAL_FMPSMBUS_STATE_RESET (0x00000000U) /*!< FMPSMBUS not yet initialized or disabled */
+#define HAL_FMPSMBUS_STATE_READY (0x00000001U) /*!< FMPSMBUS initialized and ready for use */
+#define HAL_FMPSMBUS_STATE_BUSY (0x00000002U) /*!< FMPSMBUS internal process is ongoing */
+#define HAL_FMPSMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */
+#define HAL_FMPSMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */
+#define HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */
+#define HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */
+#define HAL_FMPSMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */
+#define HAL_FMPSMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */
+#define HAL_FMPSMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_Error_Code_definition FMPSMBUS Error Code definition
+ * @brief FMPSMBUS Error Code definition
+ * @{
+ */
+#define HAL_FMPSMBUS_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_FMPSMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */
+#define HAL_FMPSMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */
+#define HAL_FMPSMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */
+#define HAL_FMPSMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */
+#define HAL_FMPSMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */
+#define HAL_FMPSMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */
+#define HAL_FMPSMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */
+#define HAL_FMPSMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */
+#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
+#define HAL_FMPSMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
+#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
+#define HAL_FMPSMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_handle_Structure_definition FMPSMBUS handle Structure definition
+ * @brief FMPSMBUS handle Structure definition
+ * @{
+ */
+#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
+typedef struct __FMPSMBUS_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
+{
+ FMPI2C_TypeDef *Instance; /*!< FMPSMBUS registers base address */
+
+ FMPSMBUS_InitTypeDef Init; /*!< FMPSMBUS communication parameters */
+
+ uint8_t *pBuffPtr; /*!< Pointer to FMPSMBUS transfer buffer */
+
+ uint16_t XferSize; /*!< FMPSMBUS transfer size */
+
+ __IO uint16_t XferCount; /*!< FMPSMBUS transfer counter */
+
+ __IO uint32_t XferOptions; /*!< FMPSMBUS transfer options */
+
+ __IO uint32_t PreviousState; /*!< FMPSMBUS communication Previous state */
+
+ HAL_LockTypeDef Lock; /*!< FMPSMBUS locking object */
+
+ __IO uint32_t State; /*!< FMPSMBUS communication state */
+
+ __IO uint32_t ErrorCode; /*!< FMPSMBUS Error code */
+
+#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
+ void (* MasterTxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Master Tx Transfer completed callback */
+ void (* MasterRxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Master Rx Transfer completed callback */
+ void (* SlaveTxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Slave Tx Transfer completed callback */
+ void (* SlaveRxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Slave Rx Transfer completed callback */
+ void (* ListenCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Listen Complete callback */
+ void (* ErrorCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Error callback */
+
+ void (* AddrCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< FMPSMBUS Slave Address Match callback */
+
+ void (* MspInitCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Msp Init callback */
+ void (* MspDeInitCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Msp DeInit callback */
+
+#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
+} FMPSMBUS_HandleTypeDef;
+
+#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL FMPSMBUS Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_FMPSMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< FMPSMBUS Master Tx Transfer completed callback ID */
+ HAL_FMPSMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< FMPSMBUS Master Rx Transfer completed callback ID */
+ HAL_FMPSMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< FMPSMBUS Slave Tx Transfer completed callback ID */
+ HAL_FMPSMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< FMPSMBUS Slave Rx Transfer completed callback ID */
+ HAL_FMPSMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< FMPSMBUS Listen Complete callback ID */
+ HAL_FMPSMBUS_ERROR_CB_ID = 0x05U, /*!< FMPSMBUS Error callback ID */
+
+ HAL_FMPSMBUS_MSPINIT_CB_ID = 0x06U, /*!< FMPSMBUS Msp Init callback ID */
+ HAL_FMPSMBUS_MSPDEINIT_CB_ID = 0x07U /*!< FMPSMBUS Msp DeInit callback ID */
+
+} HAL_FMPSMBUS_CallbackIDTypeDef;
+
+/**
+ * @brief HAL FMPSMBUS Callback pointer definition
+ */
+typedef void (*pFMPSMBUS_CallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< pointer to an FMPSMBUS callback function */
+typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an FMPSMBUS Address Match callback function */
+
+#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FMPSMBUS_Exported_Constants FMPSMBUS Exported Constants
+ * @{
+ */
+
+/** @defgroup FMPSMBUS_Analog_Filter FMPSMBUS Analog Filter
+ * @{
+ */
+#define FMPSMBUS_ANALOGFILTER_ENABLE (0x00000000U)
+#define FMPSMBUS_ANALOGFILTER_DISABLE FMPI2C_CR1_ANFOFF
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_addressing_mode FMPSMBUS addressing mode
+ * @{
+ */
+#define FMPSMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
+#define FMPSMBUS_ADDRESSINGMODE_10BIT (0x00000002U)
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_dual_addressing_mode FMPSMBUS dual addressing mode
+ * @{
+ */
+
+#define FMPSMBUS_DUALADDRESS_DISABLE (0x00000000U)
+#define FMPSMBUS_DUALADDRESS_ENABLE FMPI2C_OAR2_OA2EN
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_own_address2_masks FMPSMBUS ownaddress2 masks
+ * @{
+ */
+
+#define FMPSMBUS_OA2_NOMASK ((uint8_t)0x00U)
+#define FMPSMBUS_OA2_MASK01 ((uint8_t)0x01U)
+#define FMPSMBUS_OA2_MASK02 ((uint8_t)0x02U)
+#define FMPSMBUS_OA2_MASK03 ((uint8_t)0x03U)
+#define FMPSMBUS_OA2_MASK04 ((uint8_t)0x04U)
+#define FMPSMBUS_OA2_MASK05 ((uint8_t)0x05U)
+#define FMPSMBUS_OA2_MASK06 ((uint8_t)0x06U)
+#define FMPSMBUS_OA2_MASK07 ((uint8_t)0x07U)
+/**
+ * @}
+ */
+
+
+/** @defgroup FMPSMBUS_general_call_addressing_mode FMPSMBUS general call addressing mode
+ * @{
+ */
+#define FMPSMBUS_GENERALCALL_DISABLE (0x00000000U)
+#define FMPSMBUS_GENERALCALL_ENABLE FMPI2C_CR1_GCEN
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_nostretch_mode FMPSMBUS nostretch mode
+ * @{
+ */
+#define FMPSMBUS_NOSTRETCH_DISABLE (0x00000000U)
+#define FMPSMBUS_NOSTRETCH_ENABLE FMPI2C_CR1_NOSTRETCH
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_packet_error_check_mode FMPSMBUS packet error check mode
+ * @{
+ */
+#define FMPSMBUS_PEC_DISABLE (0x00000000U)
+#define FMPSMBUS_PEC_ENABLE FMPI2C_CR1_PECEN
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_peripheral_mode FMPSMBUS peripheral mode
+ * @{
+ */
+#define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_HOST FMPI2C_CR1_SMBHEN
+#define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE (0x00000000U)
+#define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP FMPI2C_CR1_SMBDEN
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_ReloadEndMode_definition FMPSMBUS ReloadEndMode definition
+ * @{
+ */
+
+#define FMPSMBUS_SOFTEND_MODE (0x00000000U)
+#define FMPSMBUS_RELOAD_MODE FMPI2C_CR2_RELOAD
+#define FMPSMBUS_AUTOEND_MODE FMPI2C_CR2_AUTOEND
+#define FMPSMBUS_SENDPEC_MODE FMPI2C_CR2_PECBYTE
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_StartStopMode_definition FMPSMBUS StartStopMode definition
+ * @{
+ */
+
+#define FMPSMBUS_NO_STARTSTOP (0x00000000U)
+#define FMPSMBUS_GENERATE_STOP (uint32_t)(0x80000000U | FMPI2C_CR2_STOP)
+#define FMPSMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN)
+#define FMPSMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START)
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_XferOptions_definition FMPSMBUS XferOptions definition
+ * @{
+ */
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition when direction change
+ * 2- No Restart condition in other use cases
+ */
+#define FMPSMBUS_FIRST_FRAME FMPSMBUS_SOFTEND_MODE
+#define FMPSMBUS_NEXT_FRAME ((uint32_t)(FMPSMBUS_RELOAD_MODE | FMPSMBUS_SOFTEND_MODE))
+#define FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC FMPSMBUS_AUTOEND_MODE
+#define FMPSMBUS_LAST_FRAME_NO_PEC FMPSMBUS_AUTOEND_MODE
+#define FMPSMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_SOFTEND_MODE | FMPSMBUS_SENDPEC_MODE))
+#define FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE))
+#define FMPSMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE))
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition in all use cases (direction change or not)
+ */
+#define FMPSMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
+#define FMPSMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
+#define FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
+#define FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_Interrupt_configuration_definition FMPSMBUS Interrupt configuration definition
+ * @brief FMPSMBUS Interrupt definition
+ * Elements values convention: 0xXXXXXXXX
+ * - XXXXXXXX : Interrupt control mask
+ * @{
+ */
+#define FMPSMBUS_IT_ERRI FMPI2C_CR1_ERRIE
+#define FMPSMBUS_IT_TCI FMPI2C_CR1_TCIE
+#define FMPSMBUS_IT_STOPI FMPI2C_CR1_STOPIE
+#define FMPSMBUS_IT_NACKI FMPI2C_CR1_NACKIE
+#define FMPSMBUS_IT_ADDRI FMPI2C_CR1_ADDRIE
+#define FMPSMBUS_IT_RXI FMPI2C_CR1_RXIE
+#define FMPSMBUS_IT_TXI FMPI2C_CR1_TXIE
+#define FMPSMBUS_IT_TX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI | \
+ FMPSMBUS_IT_TXI)
+#define FMPSMBUS_IT_RX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_NACKI | FMPSMBUS_IT_RXI)
+#define FMPSMBUS_IT_ALERT (FMPSMBUS_IT_ERRI)
+#define FMPSMBUS_IT_ADDR (FMPSMBUS_IT_ADDRI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI)
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_Flag_definition FMPSMBUS Flag definition
+ * @brief Flag definition
+ * Elements values convention: 0xXXXXYYYY
+ * - XXXXXXXX : Flag mask
+ * @{
+ */
+
+#define FMPSMBUS_FLAG_TXE FMPI2C_ISR_TXE
+#define FMPSMBUS_FLAG_TXIS FMPI2C_ISR_TXIS
+#define FMPSMBUS_FLAG_RXNE FMPI2C_ISR_RXNE
+#define FMPSMBUS_FLAG_ADDR FMPI2C_ISR_ADDR
+#define FMPSMBUS_FLAG_AF FMPI2C_ISR_NACKF
+#define FMPSMBUS_FLAG_STOPF FMPI2C_ISR_STOPF
+#define FMPSMBUS_FLAG_TC FMPI2C_ISR_TC
+#define FMPSMBUS_FLAG_TCR FMPI2C_ISR_TCR
+#define FMPSMBUS_FLAG_BERR FMPI2C_ISR_BERR
+#define FMPSMBUS_FLAG_ARLO FMPI2C_ISR_ARLO
+#define FMPSMBUS_FLAG_OVR FMPI2C_ISR_OVR
+#define FMPSMBUS_FLAG_PECERR FMPI2C_ISR_PECERR
+#define FMPSMBUS_FLAG_TIMEOUT FMPI2C_ISR_TIMEOUT
+#define FMPSMBUS_FLAG_ALERT FMPI2C_ISR_ALERT
+#define FMPSMBUS_FLAG_BUSY FMPI2C_ISR_BUSY
+#define FMPSMBUS_FLAG_DIR FMPI2C_ISR_DIR
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup FMPSMBUS_Exported_Macros FMPSMBUS Exported Macros
+ * @{
+ */
+
+/** @brief Reset FMPSMBUS handle state.
+ * @param __HANDLE__ specifies the FMPSMBUS Handle.
+ * @retval None
+ */
+#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
+#define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET)
+#endif
+
+/** @brief Enable the specified FMPSMBUS interrupts.
+ * @param __HANDLE__ specifies the FMPSMBUS Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable
+ * @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable
+ * @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable
+ * @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable
+ * @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable
+ * @arg @ref FMPSMBUS_IT_RXI RX interrupt enable
+ * @arg @ref FMPSMBUS_IT_TXI TX interrupt enable
+ *
+ * @retval None
+ */
+#define __HAL_FMPSMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
+
+/** @brief Disable the specified FMPSMBUS interrupts.
+ * @param __HANDLE__ specifies the FMPSMBUS Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable
+ * @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable
+ * @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable
+ * @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable
+ * @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable
+ * @arg @ref FMPSMBUS_IT_RXI RX interrupt enable
+ * @arg @ref FMPSMBUS_IT_TXI TX interrupt enable
+ *
+ * @retval None
+ */
+#define __HAL_FMPSMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
+
+/** @brief Check whether the specified FMPSMBUS interrupt source is enabled or not.
+ * @param __HANDLE__ specifies the FMPSMBUS Handle.
+ * @param __INTERRUPT__ specifies the FMPSMBUS interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable
+ * @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable
+ * @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable
+ * @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable
+ * @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable
+ * @arg @ref FMPSMBUS_IT_RXI RX interrupt enable
+ * @arg @ref FMPSMBUS_IT_TXI TX interrupt enable
+ *
+ * @retval The new state of __IT__ (SET or RESET).
+ */
+#define __HAL_FMPSMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Check whether the specified FMPSMBUS flag is set or not.
+ * @param __HANDLE__ specifies the FMPSMBUS Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref FMPSMBUS_FLAG_TXE Transmit data register empty
+ * @arg @ref FMPSMBUS_FLAG_TXIS Transmit interrupt status
+ * @arg @ref FMPSMBUS_FLAG_RXNE Receive data register not empty
+ * @arg @ref FMPSMBUS_FLAG_ADDR Address matched (slave mode)
+ * @arg @ref FMPSMBUS_FLAG_AF NACK received flag
+ * @arg @ref FMPSMBUS_FLAG_STOPF STOP detection flag
+ * @arg @ref FMPSMBUS_FLAG_TC Transfer complete (master mode)
+ * @arg @ref FMPSMBUS_FLAG_TCR Transfer complete reload
+ * @arg @ref FMPSMBUS_FLAG_BERR Bus error
+ * @arg @ref FMPSMBUS_FLAG_ARLO Arbitration lost
+ * @arg @ref FMPSMBUS_FLAG_OVR Overrun/Underrun
+ * @arg @ref FMPSMBUS_FLAG_PECERR PEC error in reception
+ * @arg @ref FMPSMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
+ * @arg @ref FMPSMBUS_FLAG_ALERT SMBus alert
+ * @arg @ref FMPSMBUS_FLAG_BUSY Bus busy
+ * @arg @ref FMPSMBUS_FLAG_DIR Transfer direction (slave mode)
+ *
+ * @retval The new state of __FLAG__ (SET or RESET).
+ */
+#define FMPSMBUS_FLAG_MASK (0x0001FFFFU)
+#define __HAL_FMPSMBUS_GET_FLAG(__HANDLE__, __FLAG__) \
+ (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & FMPSMBUS_FLAG_MASK)) == ((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET)
+
+/** @brief Clear the FMPSMBUS pending flags which are cleared by writing 1 in a specific bit.
+ * @param __HANDLE__ specifies the FMPSMBUS Handle.
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg @ref FMPSMBUS_FLAG_ADDR Address matched (slave mode)
+ * @arg @ref FMPSMBUS_FLAG_AF NACK received flag
+ * @arg @ref FMPSMBUS_FLAG_STOPF STOP detection flag
+ * @arg @ref FMPSMBUS_FLAG_BERR Bus error
+ * @arg @ref FMPSMBUS_FLAG_ARLO Arbitration lost
+ * @arg @ref FMPSMBUS_FLAG_OVR Overrun/Underrun
+ * @arg @ref FMPSMBUS_FLAG_PECERR PEC error in reception
+ * @arg @ref FMPSMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
+ * @arg @ref FMPSMBUS_FLAG_ALERT SMBus alert
+ *
+ * @retval None
+ */
+#define __HAL_FMPSMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief Enable the specified FMPSMBUS peripheral.
+ * @param __HANDLE__ specifies the FMPSMBUS Handle.
+ * @retval None
+ */
+#define __HAL_FMPSMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE))
+
+/** @brief Disable the specified FMPSMBUS peripheral.
+ * @param __HANDLE__ specifies the FMPSMBUS Handle.
+ * @retval None
+ */
+#define __HAL_FMPSMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE))
+
+/** @brief Generate a Non-Acknowledge FMPSMBUS peripheral in Slave mode.
+ * @param __HANDLE__ specifies the FMPSMBUS Handle.
+ * @retval None
+ */
+#define __HAL_FMPSMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, FMPI2C_CR2_NACK))
+
+/**
+ * @}
+ */
+
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FMPSMBUS_Private_Macro FMPSMBUS Private Macros
+ * @{
+ */
+
+#define IS_FMPSMBUS_ANALOG_FILTER(FILTER) (((FILTER) == FMPSMBUS_ANALOGFILTER_ENABLE) || \
+ ((FILTER) == FMPSMBUS_ANALOGFILTER_DISABLE))
+
+#define IS_FMPSMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
+
+#define IS_FMPSMBUS_ADDRESSING_MODE(MODE) (((MODE) == FMPSMBUS_ADDRESSINGMODE_7BIT) || \
+ ((MODE) == FMPSMBUS_ADDRESSINGMODE_10BIT))
+
+#define IS_FMPSMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == FMPSMBUS_DUALADDRESS_DISABLE) || \
+ ((ADDRESS) == FMPSMBUS_DUALADDRESS_ENABLE))
+
+#define IS_FMPSMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == FMPSMBUS_OA2_NOMASK) || \
+ ((MASK) == FMPSMBUS_OA2_MASK01) || \
+ ((MASK) == FMPSMBUS_OA2_MASK02) || \
+ ((MASK) == FMPSMBUS_OA2_MASK03) || \
+ ((MASK) == FMPSMBUS_OA2_MASK04) || \
+ ((MASK) == FMPSMBUS_OA2_MASK05) || \
+ ((MASK) == FMPSMBUS_OA2_MASK06) || \
+ ((MASK) == FMPSMBUS_OA2_MASK07))
+
+#define IS_FMPSMBUS_GENERAL_CALL(CALL) (((CALL) == FMPSMBUS_GENERALCALL_DISABLE) || \
+ ((CALL) == FMPSMBUS_GENERALCALL_ENABLE))
+
+#define IS_FMPSMBUS_NO_STRETCH(STRETCH) (((STRETCH) == FMPSMBUS_NOSTRETCH_DISABLE) || \
+ ((STRETCH) == FMPSMBUS_NOSTRETCH_ENABLE))
+
+#define IS_FMPSMBUS_PEC(PEC) (((PEC) == FMPSMBUS_PEC_DISABLE) || \
+ ((PEC) == FMPSMBUS_PEC_ENABLE))
+
+#define IS_FMPSMBUS_PERIPHERAL_MODE(MODE) (((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_HOST) || \
+ ((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE) || \
+ ((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP))
+
+#define IS_FMPSMBUS_TRANSFER_MODE(MODE) (((MODE) == FMPSMBUS_RELOAD_MODE) || \
+ ((MODE) == FMPSMBUS_AUTOEND_MODE) || \
+ ((MODE) == FMPSMBUS_SOFTEND_MODE) || \
+ ((MODE) == FMPSMBUS_SENDPEC_MODE) || \
+ ((MODE) == (FMPSMBUS_RELOAD_MODE | FMPSMBUS_SENDPEC_MODE)) || \
+ ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) || \
+ ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_RELOAD_MODE)) || \
+ ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE | FMPSMBUS_RELOAD_MODE )))
+
+
+#define IS_FMPSMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_GENERATE_STOP) || \
+ ((REQUEST) == FMPSMBUS_GENERATE_START_READ) || \
+ ((REQUEST) == FMPSMBUS_GENERATE_START_WRITE) || \
+ ((REQUEST) == FMPSMBUS_NO_STARTSTOP))
+
+
+#define IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
+ ((REQUEST) == FMPSMBUS_FIRST_FRAME) || \
+ ((REQUEST) == FMPSMBUS_NEXT_FRAME) || \
+ ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == FMPSMBUS_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == FMPSMBUS_FIRST_FRAME_WITH_PEC) || \
+ ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
+ ((REQUEST) == FMPSMBUS_LAST_FRAME_WITH_PEC))
+
+#define IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_OTHER_FRAME_NO_PEC) || \
+ ((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == FMPSMBUS_OTHER_FRAME_WITH_PEC) || \
+ ((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
+
+#define FMPSMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \
+ (uint32_t)~((uint32_t)(FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN | FMPI2C_CR1_PECEN)))
+#define FMPSMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
+ (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_RD_WRN)))
+
+#define FMPSMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPSMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & (~FMPI2C_CR2_RD_WRN)) : \
+ (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN)))
+
+#define FMPSMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) >> 17U)
+#define FMPSMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) >> 16U)
+#define FMPSMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_AUTOEND)
+#define FMPSMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_PECBYTE)
+#define FMPSMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & FMPI2C_CR1_ALERTEN)
+
+#define FMPSMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & FMPSMBUS_FLAG_MASK)) == \
+ ((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET)
+#define FMPSMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
+
+#define IS_FMPSMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
+#define IS_FMPSMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FMPSMBUS_Exported_Functions FMPSMBUS Exported Functions
+ * @{
+ */
+
+/** @addtogroup FMPSMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_FMPSMBUS_Init(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+HAL_StatusTypeDef HAL_FMPSMBUS_DeInit(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+void HAL_FMPSMBUS_MspInit(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+void HAL_FMPSMBUS_MspDeInit(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+HAL_StatusTypeDef HAL_FMPSMBUS_ConfigAnalogFilter(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_FMPSMBUS_ConfigDigitalFilter(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t DigitalFilter);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, HAL_FMPSMBUS_CallbackIDTypeDef CallbackID,
+ pFMPSMBUS_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, HAL_FMPSMBUS_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, pFMPSMBUS_AddrCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @addtogroup FMPSMBUS_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+/** @addtogroup Blocking_mode_Polling Blocking mode Polling
+ * @{
+ */
+/******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_FMPSMBUS_IsDeviceReady(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint32_t Trials,
+ uint32_t Timeout);
+/**
+ * @}
+ */
+
+/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
+ * @{
+ */
+/******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPSMBUS_Master_Abort_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress);
+HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions);
+
+HAL_StatusTypeDef HAL_FMPSMBUS_EnableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+HAL_StatusTypeDef HAL_FMPSMBUS_DisableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+HAL_StatusTypeDef HAL_FMPSMBUS_EnableListen_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+HAL_StatusTypeDef HAL_FMPSMBUS_DisableListen_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+/**
+ * @}
+ */
+
+/** @addtogroup FMPSMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+/******* FMPSMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
+void HAL_FMPSMBUS_EV_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+void HAL_FMPSMBUS_ER_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+void HAL_FMPSMBUS_MasterTxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+void HAL_FMPSMBUS_MasterRxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+void HAL_FMPSMBUS_SlaveTxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+void HAL_FMPSMBUS_SlaveRxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+void HAL_FMPSMBUS_AddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
+void HAL_FMPSMBUS_ListenCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+void HAL_FMPSMBUS_ErrorCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+
+/**
+ * @}
+ */
+
+/** @addtogroup FMPSMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @{
+ */
+
+/* Peripheral State and Errors functions **************************************************/
+uint32_t HAL_FMPSMBUS_GetState(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+uint32_t HAL_FMPSMBUS_GetError(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup FMPSMBUS_Private_Functions FMPSMBUS Private Functions
+ * @{
+ */
+/* Private functions are defined in stm32f4xx_hal_fmpsmbus.c file */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* FMPI2C_CR1_PE */
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32F4xx_HAL_FMPSMBUS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus_ex.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus_ex.h
new file mode 100644
index 0000000000..541ce73228
--- /dev/null
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus_ex.h
@@ -0,0 +1,130 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_fmpsmbus_ex.h
+ * @author MCD Application Team
+ * @brief Header file of FMPSMBUS HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ *
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F4xx_HAL_FMPSMBUS_EX_H
+#define STM32F4xx_HAL_FMPSMBUS_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(FMPI2C_CR1_PE)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FMPSMBUSEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FMPSMBUSEx_Exported_Constants FMPSMBUS Extended Exported Constants
+ * @{
+ */
+
+/** @defgroup FMPSMBUSEx_FastModePlus FMPSMBUS Extended Fast Mode Plus
+ * @{
+ */
+#define FMPSMBUS_FASTMODEPLUS_SCL SYSCFG_CFGR_FMPI2C1_SCL /*!< Enable Fast Mode Plus on FMPI2C1 SCL pins */
+#define FMPSMBUS_FASTMODEPLUS_SDA SYSCFG_CFGR_FMPI2C1_SDA /*!< Enable Fast Mode Plus on FMPI2C1 SDA pins */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FMPSMBUSEx_Exported_Macros FMPSMBUS Extended Exported Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FMPSMBUSEx_Exported_Functions FMPSMBUS Extended Exported Functions
+ * @{
+ */
+
+/** @addtogroup FMPSMBUSEx_Exported_Functions_Group3 FMPSMBUS Extended FastModePlus Functions
+ * @{
+ */
+void HAL_FMPSMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
+void HAL_FMPSMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FMPSMBUSEx_Private_Constants FMPSMBUS Extended Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FMPSMBUSEx_Private_Macro FMPSMBUS Extended Private Macros
+ * @{
+ */
+#define IS_FMPSMBUS_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (FMPSMBUS_FASTMODEPLUS_SCL)) == FMPSMBUS_FASTMODEPLUS_SCL) || \
+ (((__CONFIG__) & (FMPSMBUS_FASTMODEPLUS_SDA)) == FMPSMBUS_FASTMODEPLUS_SDA))
+/**
+ * @}
+ */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup FMPSMBUSEx_Private_Functions FMPSMBUS Extended Private Functions
+ * @{
+ */
+/* Private functions are defined in stm32f4xx_hal_fmpfmpsmbus_ex.c file */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* FMPI2C_CR1_PE */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F4xx_HAL_FMPSMBUS_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h
index 5110d634b0..38b567d105 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h
@@ -115,22 +115,23 @@ typedef enum
* - Y : Output type (Push Pull or Open Drain)
* - Z : IO Direction mode (Input, Output, Alternate or Analog)
* @{
- */
-#define GPIO_MODE_INPUT 0x00000000U /*!< Input Floating Mode */
-#define GPIO_MODE_OUTPUT_PP 0x00000001U /*!< Output Push Pull Mode */
-#define GPIO_MODE_OUTPUT_OD 0x00000011U /*!< Output Open Drain Mode */
-#define GPIO_MODE_AF_PP 0x00000002U /*!< Alternate Function Push Pull Mode */
-#define GPIO_MODE_AF_OD 0x00000012U /*!< Alternate Function Open Drain Mode */
-
-#define GPIO_MODE_ANALOG 0x00000003U /*!< Analog Mode */
-
-#define GPIO_MODE_IT_RISING 0x10110000U /*!< External Interrupt Mode with Rising edge trigger detection */
-#define GPIO_MODE_IT_FALLING 0x10210000U /*!< External Interrupt Mode with Falling edge trigger detection */
-#define GPIO_MODE_IT_RISING_FALLING 0x10310000U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-
-#define GPIO_MODE_EVT_RISING 0x10120000U /*!< External Event Mode with Rising edge trigger detection */
-#define GPIO_MODE_EVT_FALLING 0x10220000U /*!< External Event Mode with Falling edge trigger detection */
-#define GPIO_MODE_EVT_RISING_FALLING 0x10320000U /*!< External Event Mode with Rising/Falling edge trigger detection */
+ */
+#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */
+#define GPIO_MODE_OUTPUT_PP (MODE_PP | MODE_OUTPUT) /*!< Output Push Pull Mode */
+#define GPIO_MODE_OUTPUT_OD (MODE_OD | MODE_OUTPUT) /*!< Output Open Drain Mode */
+#define GPIO_MODE_AF_PP (MODE_PP | MODE_AF) /*!< Alternate Function Push Pull Mode */
+#define GPIO_MODE_AF_OD (MODE_OD | MODE_AF) /*!< Alternate Function Open Drain Mode */
+
+#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */
+
+#define GPIO_MODE_IT_RISING (EXTI_MODE | GPIO_MODE_IT | RISING_EDGE) /*!< External Interrupt Mode with Rising edge trigger detection */
+#define GPIO_MODE_IT_FALLING (EXTI_MODE | GPIO_MODE_IT | FALLING_EDGE) /*!< External Interrupt Mode with Falling edge trigger detection */
+#define GPIO_MODE_IT_RISING_FALLING (EXTI_MODE | GPIO_MODE_IT | RISING_EDGE | FALLING_EDGE) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+
+#define GPIO_MODE_EVT_RISING (EXTI_MODE | GPIO_MODE_EVT | RISING_EDGE) /*!< External Event Mode with Rising edge trigger detection */
+#define GPIO_MODE_EVT_FALLING (EXTI_MODE | GPIO_MODE_EVT | FALLING_EDGE) /*!< External Event Mode with Falling edge trigger detection */
+#define GPIO_MODE_EVT_RISING_FALLING (EXTI_MODE | GPIO_MODE_EVT | RISING_EDGE | FALLING_EDGE) /*!< External Event Mode with Rising/Falling edge trigger detection */
+
/**
* @}
*/
@@ -252,6 +253,21 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
/** @defgroup GPIO_Private_Constants GPIO Private Constants
* @{
*/
+#define GPIO_MODE 0x00000003U
+#define EXTI_MODE 0x10000000U
+#define GPIO_MODE_IT 0x00010000U
+#define GPIO_MODE_EVT 0x00020000U
+#define RISING_EDGE 0x00100000U
+#define FALLING_EDGE 0x00200000U
+#define GPIO_OUTPUT_TYPE 0x00000010U
+
+#define MODE_INPUT 0x00000000U /*!< Input Mode */
+#define MODE_OUTPUT 0x00000001U /*!< Output Mode */
+#define MODE_AF 0x00000002U /*!< Alternate Function Mode */
+#define MODE_ANALOG 0x00000003U /*!< Analog Mode */
+
+#define MODE_PP 0x00000000U /*!< Push Pull Mode */
+#define MODE_OD 0x00000010U /*!< Open Drain Mode */
/**
* @}
@@ -262,7 +278,7 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
* @{
*/
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
-#define IS_GPIO_PIN(PIN) ((((PIN) & GPIO_PIN_MASK ) != 0x00U) && (((PIN) & ~GPIO_PIN_MASK) == 0x00U))
+#define IS_GPIO_PIN(PIN) (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00U) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00U))
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
((MODE) == GPIO_MODE_OUTPUT_PP) ||\
((MODE) == GPIO_MODE_OUTPUT_OD) ||\
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h
index aa1e34d884..7db36ccaec 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h
@@ -1442,21 +1442,21 @@
/*----------------------------------------------------------------------------*/
/*---------------------------------------- STM32F401xx------------------------*/
-#if defined(STM32F401xC) || defined(STM32F401xE)
+#if defined(STM32F401xC) || defined(STM32F401xE)
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF12_SDIO) || \
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
- ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF4_I2C1) || \
- ((AF) == GPIO_AF4_I2C2) || ((AF) == GPIO_AF4_I2C3) || \
- ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \
- ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF5_SPI4) || \
- ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
- ((AF) == GPIO_AF8_USART6) || ((AF) == GPIO_AF10_OTG_FS) || \
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM9) || \
+ ((AF) == GPIO_AF3_TIM10) || ((AF) == GPIO_AF3_TIM11) || \
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
+ ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF5_SPI4) || \
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF7_USART1) || \
+ ((AF) == GPIO_AF7_USART2) || ((AF) == GPIO_AF8_USART6) || \
((AF) == GPIO_AF9_I2C2) || ((AF) == GPIO_AF9_I2C3) || \
- ((AF) == GPIO_AF15_EVENTOUT))
-
+ ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF15_EVENTOUT))
#endif /* STM32F401xC || STM32F401xE */
/*----------------------------------------------------------------------------*/
/*---------------------------------------- STM32F410xx------------------------*/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hash.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hash.h
index da6d5d92b4..f7c0b9d73e 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hash.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hash.h
@@ -22,7 +22,7 @@
#define STM32F4xx_HAL_HASH_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -51,7 +51,7 @@ typedef struct
uint32_t KeySize; /*!< The key size is used only in HMAC operation. */
- uint8_t* pKey; /*!< The key is used only in HMAC operation. */
+ uint8_t *pKey; /*!< The key is used only in HMAC operation. */
} HASH_InitTypeDef;
@@ -66,7 +66,7 @@ typedef enum
HAL_HASH_STATE_TIMEOUT = 0x06U, /*!< Timeout state */
HAL_HASH_STATE_ERROR = 0x07U, /*!< Error state */
HAL_HASH_STATE_SUSPENDED = 0x08U /*!< Suspended state */
-}HAL_HASH_StateTypeDef;
+} HAL_HASH_StateTypeDef;
/**
* @brief HAL phase structures definition
@@ -81,7 +81,7 @@ typedef enum
(step 2 consists in entering the message text) */
HAL_HASH_PHASE_HMAC_STEP_3 = 0x05U /*!< HASH peripheral is in HMAC step 3 processing phase
(step 3 consists in entering the outer hash function key) */
-}HAL_HASH_PhaseTypeDef;
+} HAL_HASH_PhaseTypeDef;
/**
* @brief HAL HASH mode suspend definitions
@@ -90,7 +90,7 @@ typedef enum
{
HAL_HASH_SUSPEND_NONE = 0x00U, /*!< HASH peripheral suspension not requested */
HAL_HASH_SUSPEND = 0x01U /*!< HASH peripheral suspension is requested */
-}HAL_HASH_SuspendTypeDef;
+} HAL_HASH_SuspendTypeDef;
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
/**
@@ -103,7 +103,7 @@ typedef enum
HAL_HASH_INPUTCPLT_CB_ID = 0x02U, /*!< HASH input completion callback ID */
HAL_HASH_DGSTCPLT_CB_ID = 0x03U, /*!< HASH digest computation completion callback ID */
HAL_HASH_ERROR_CB_ID = 0x04U, /*!< HASH error callback ID */
-}HAL_HASH_CallbackIDTypeDef;
+} HAL_HASH_CallbackIDTypeDef;
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
@@ -152,16 +152,18 @@ typedef struct
__IO uint32_t ErrorCode; /*!< HASH Error code */
+ __IO uint32_t Accumulation; /*!< HASH multi buffers accumulation flag */
+
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
- void (* InCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH input completion callback */
+ void (* InCpltCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH input completion callback */
- void (* DgstCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH digest computation completion callback */
+ void (* DgstCpltCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH digest computation completion callback */
- void (* ErrorCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH error callback */
+ void (* ErrorCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH error callback */
- void (* MspInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp Init callback */
+ void (* MspInitCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH Msp Init callback */
- void (* MspDeInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp DeInit callback */
+ void (* MspDeInitCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH Msp DeInit callback */
#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
} HASH_HandleTypeDef;
@@ -170,7 +172,7 @@ typedef struct
/**
* @brief HAL HASH Callback pointer definition
*/
-typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer to a HASH common callback functions */
+typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef *hhash); /*!< pointer to a HASH common callback functions */
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
/**
@@ -226,11 +228,11 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
/** @defgroup HASH_flags_definition HASH flags definitions
* @{
*/
-#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : a new block can be entered in the IP */
-#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
-#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
-#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy, processing a block of data */
-#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : the input buffer contains at least one word of data */
+#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : a new block can be entered in the Peripheral */
+#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
+#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
+#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy, processing a block of data */
+#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : the input buffer contains at least one word of data */
/**
* @}
@@ -248,7 +250,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
/** @defgroup HASH_alias HASH API alias
* @{
*/
-#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< HAL_HASHEx_IRQHandler() is re-directed to HAL_HASH_IRQHandler() for compatibility with legacy code */
+#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */
/**
* @}
*/
@@ -276,7 +278,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
*/
/** @brief Check whether or not the specified HASH flag is set.
- * @param __FLAG__: specifies the flag to check.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
* @arg @ref HASH_FLAG_DCIS Digest calculation complete.
@@ -286,12 +288,12 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? \
- ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
- ((HASH->SR & (__FLAG__)) == (__FLAG__)) )
+ ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
+ ((HASH->SR & (__FLAG__)) == (__FLAG__)) )
/** @brief Clear the specified HASH flag.
- * @param __FLAG__: specifies the flag to clear.
+ * @param __FLAG__ specifies the flag to clear.
* This parameter can be one of the following values:
* @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
* @arg @ref HASH_FLAG_DCIS Digest calculation complete
@@ -301,7 +303,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
/** @brief Enable the specified HASH interrupt.
- * @param __INTERRUPT__: specifies the HASH interrupt source to enable.
+ * @param __INTERRUPT__ specifies the HASH interrupt source to enable.
* This parameter can be one of the following values:
* @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)
* @arg @ref HASH_IT_DCI Digest calculation complete
@@ -310,7 +312,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
#define __HAL_HASH_ENABLE_IT(__INTERRUPT__) SET_BIT(HASH->IMR, (__INTERRUPT__))
/** @brief Disable the specified HASH interrupt.
- * @param __INTERRUPT__: specifies the HASH interrupt source to disable.
+ * @param __INTERRUPT__ specifies the HASH interrupt source to disable.
* This parameter can be one of the following values:
* @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)
* @arg @ref HASH_IT_DCI Digest calculation complete
@@ -319,7 +321,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
#define __HAL_HASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(HASH->IMR, (__INTERRUPT__))
/** @brief Reset HASH handle state.
- * @param __HANDLE__: HASH handle.
+ * @param __HANDLE__ HASH handle.
* @retval None
*/
@@ -335,7 +337,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
/** @brief Reset HASH handle status.
- * @param __HANDLE__: HASH handle.
+ * @param __HANDLE__ HASH handle.
* @retval None
*/
#define __HAL_HASH_RESET_HANDLE_STATUS(__HANDLE__) ((__HANDLE__)->Status = HAL_OK)
@@ -362,9 +364,9 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
/**
* @brief Set the number of valid bits in the last word written in data register DIN.
- * @param __SIZE__: size in bytes of last data written in Data register.
+ * @param __SIZE__ size in bytes of last data written in Data register.
* @retval None
-*/
+ */
#define __HAL_HASH_SET_NBVALIDBITS(__SIZE__) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * ((__SIZE__) % 4U))
/**
@@ -388,11 +390,11 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
*/
#if defined(HASH_CR_MDMAT)
#define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1) ? 20U : \
- ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ? 28U : \
- ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ? 32U : 16U ) ) )
+ ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ? 28U : \
+ ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ? 32U : 16U ) ) )
#else
#define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1) ? 20U : 16)
-#endif
+#endif /* HASH_CR_MDMAT*/
/**
* @brief Return number of words already pushed in the FIFO.
* @retval Number of words already pushed in the FIFO
@@ -401,7 +403,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
/**
* @brief Ensure that HASH input data type is valid.
- * @param __DATATYPE__: HASH input data type.
+ * @param __DATATYPE__ HASH input data type.
* @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)
*/
#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \
@@ -409,21 +411,11 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
((__DATATYPE__) == HASH_DATATYPE_8B) || \
((__DATATYPE__) == HASH_DATATYPE_1B))
-
-
-/**
- * @brief Ensure that input data buffer size is valid for multi-buffer HASH
- * processing in polling mode.
- * @note This check is valid only for multi-buffer HASH processing in polling mode.
- * @param __SIZE__: input data buffer size.
- * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
- */
-#define IS_HASH_POLLING_MULTIBUFFER_SIZE(__SIZE__) (((__SIZE__) % 4U) == 0U)
/**
* @brief Ensure that input data buffer size is valid for multi-buffer HASH
* processing in DMA mode.
* @note This check is valid only for multi-buffer HASH processing in DMA mode.
- * @param __SIZE__: input data buffer size.
+ * @param __SIZE__ input data buffer size.
* @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
*/
#define IS_HASH_DMA_MULTIBUFFER_SIZE(__SIZE__) ((READ_BIT(HASH->CR, HASH_CR_MDMAT) == 0U) || (((__SIZE__) % 4U) == 0U))
@@ -432,21 +424,22 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
* @brief Ensure that input data buffer size is valid for multi-buffer HMAC
* processing in DMA mode.
* @note This check is valid only for multi-buffer HMAC processing in DMA mode.
- * @param __HANDLE__: HASH handle.
- * @param __SIZE__: input data buffer size.
+ * @param __HANDLE__ HASH handle.
+ * @param __SIZE__ input data buffer size.
* @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
*/
-#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4U) == 0U))
+#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET)\
+ || (((__SIZE__) % 4U) == 0U))
/**
* @brief Ensure that handle phase is set to HASH processing.
- * @param __HANDLE__: HASH handle.
+ * @param __HANDLE__ HASH handle.
* @retval SET (handle phase is set to HASH processing) or RESET (handle phase is not set to HASH processing)
*/
#define IS_HASH_PROCESSING(__HANDLE__) ((__HANDLE__)->Phase == HAL_HASH_PHASE_PROCESS)
/**
* @brief Ensure that handle phase is set to HMAC processing.
- * @param __HANDLE__: HASH handle.
+ * @param __HANDLE__ HASH handle.
* @retval SET (handle phase is set to HMAC processing) or RESET (handle phase is not set to HMAC processing)
*/
#define IS_HMAC_PROCESSING(__HANDLE__) (((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || \
@@ -479,7 +472,8 @@ void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID,
+ pHASH_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
@@ -494,10 +488,17 @@ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HAS
/* HASH processing using polling *********************************************/
-HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
+
/**
* @}
@@ -508,8 +509,16 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *p
*/
/* HASH processing using IT **************************************************/
-HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
/**
* @}
@@ -521,9 +530,9 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
/* HASH processing using DMA *************************************************/
HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
/**
* @}
@@ -534,8 +543,10 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBu
*/
/* HASH-MAC processing using polling *****************************************/
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout);
/**
* @}
@@ -545,8 +556,10 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
* @{
*/
-HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
/**
* @}
@@ -572,8 +585,8 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn
/* Peripheral State methods **************************************************/
HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash);
-void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
-void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
+void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer);
+void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer);
void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash);
@@ -593,13 +606,18 @@ uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash);
*/
/* Private functions */
-HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
-HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Algorithm);
HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
-HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
-HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout, uint32_t Algorithm);
+HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Algorithm);
HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hash_ex.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hash_ex.h
index e594b63b2b..0a9844c0ae 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hash_ex.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hash_ex.h
@@ -22,7 +22,7 @@
#define STM32F4xx_HAL_HASH_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -51,10 +51,16 @@
* @{
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
/**
* @}
@@ -64,8 +70,16 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_
* @{
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
/**
* @}
@@ -75,9 +89,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
* @{
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
/**
* @}
@@ -86,8 +100,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p
/** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode
* @{
*/
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
/**
* @}
*/
@@ -96,8 +112,10 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
* @{
*/
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
/**
* @}
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h
index 5f4cccdc5b..c9ac38a956 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h
@@ -33,7 +33,7 @@ extern "C" {
* @{
*/
-/** @addtogroup HCD
+/** @addtogroup HCD HCD
* @{
*/
@@ -109,8 +109,12 @@ typedef struct
* @{
*/
#define HCD_SPEED_HIGH USBH_HS_SPEED
-#define HCD_SPEED_FULL USBH_FS_SPEED
-#define HCD_SPEED_LOW USBH_LS_SPEED
+#define HCD_SPEED_FULL USBH_FSLS_SPEED
+#define HCD_SPEED_LOW USBH_FSLS_SPEED
+
+#define HCD_DEVICE_SPEED_HIGH 0U
+#define HCD_DEVICE_SPEED_FULL 1U
+#define HCD_DEVICE_SPEED_LOW 2U
/**
* @}
@@ -143,9 +147,9 @@ typedef struct
/* Exported macro ------------------------------------------------------------*/
/** @defgroup HCD_Exported_Macros HCD Exported Macros
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
#define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
@@ -170,19 +174,15 @@ typedef struct
/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
-HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
- uint8_t ch_num,
- uint8_t epnum,
- uint8_t dev_address,
- uint8_t speed,
- uint8_t ep_type,
- uint16_t mps);
+HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
+ uint8_t epnum, uint8_t dev_address,
+ uint8_t speed, uint8_t ep_type, uint16_t mps);
-HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
-void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
+void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
/** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition
@@ -191,14 +191,14 @@ void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
*/
typedef enum
{
- HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */
- HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */
- HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */
- HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */
- HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */
+ HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */
+ HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */
+ HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */
+ HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */
+ HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */
- HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */
- HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */
+ HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */
+ HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */
} HAL_HCD_CallbackIDTypeDef;
/**
@@ -218,10 +218,16 @@ typedef void (*pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd,
* @}
*/
-HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd,
+ HAL_HCD_CallbackIDTypeDef CallbackID,
+ pHCD_CallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd,
+ HAL_HCD_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd,
+ pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
/**
@@ -232,25 +238,21 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef
/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
-HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
- uint8_t ch_num,
- uint8_t direction,
- uint8_t ep_type,
- uint8_t token,
- uint8_t *pbuff,
- uint16_t length,
- uint8_t do_ping);
+HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
+ uint8_t direction, uint8_t ep_type,
+ uint8_t token, uint8_t *pbuff,
+ uint16_t length, uint8_t do_ping);
/* Non-Blocking mode: Interrupt */
-void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
- uint8_t chnum,
- HCD_URBStateTypeDef urb_state);
+void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_WKUP_IRQHandler(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum,
+ HCD_URBStateTypeDef urb_state);
/**
* @}
*/
@@ -259,9 +261,9 @@ void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
-HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
/**
* @}
*/
@@ -272,10 +274,11 @@ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
*/
HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
+
/**
* @}
*/
@@ -286,36 +289,17 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
/* Private macros ------------------------------------------------------------*/
/** @defgroup HCD_Private_Macros HCD Private Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup HCD_Private_Functions_Prototypes HCD Private Functions Prototypes
* @{
*/
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup HCD_Private_Functions HCD Private Functions
- * @{
- */
-
/**
* @}
*/
+/* Private functions prototypes ----------------------------------------------*/
-/**
+ /**
* @}
*/
-
-/**
+ /**
* @}
*/
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h
index 2f3f947c4d..9a622b82b3 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h
@@ -85,7 +85,7 @@ typedef struct
* 01 : Abort (Abort user request on going)
* 10 : Timeout
* 11 : Error
- * b5 Peripheral initilisation status
+ * b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
* 1 : Init done (Peripheral initialized and ready to use. HAL I2C Init function called)
* b4 (not used)
@@ -170,6 +170,7 @@ typedef enum
#define HAL_I2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout Error */
#define HAL_I2C_ERROR_SIZE 0x00000040U /*!< Size Management error */
#define HAL_I2C_ERROR_DMA_PARAM 0x00000080U /*!< DMA Parameter Error */
+#define HAL_I2C_WRONG_START 0x00000200U /*!< Wrong start Error */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
#define HAL_I2C_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid Callback error */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
@@ -181,7 +182,11 @@ typedef enum
* @brief I2C handle Structure definition
* @{
*/
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
typedef struct __I2C_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
{
I2C_TypeDef *Instance; /*!< I2C registers base address */
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h
index 6530a5c2ee..1e9676f868 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h
@@ -181,6 +181,7 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid Callback error */
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+#define HAL_I2S_ERROR_BUSY_LINE_RX (0x00000040U) /*!< Busy Rx Line error */
/**
* @}
*/
@@ -286,7 +287,8 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
#define I2S_FLAG_BSY SPI_SR_BSY
-#define I2S_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY)
+#define I2S_FLAG_MASK (SPI_SR_RXNE\
+ | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY)
/**
* @}
*/
@@ -337,7 +339,7 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
} while(0)
#else
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
-#endif
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/** @brief Enable the specified SPI peripheral (in I2S mode).
* @param __HANDLE__ specifies the I2S Handle.
@@ -383,7 +385,8 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
* @arg I2S_IT_ERR: Error interrupt enable
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
+ & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks whether the specified I2S flag is set or not.
* @param __HANDLE__ specifies the I2S Handle.
@@ -405,19 +408,28 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
* @retval None
*/
#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
- __IO uint32_t tmpreg_ovr = 0x00U; \
- tmpreg_ovr = (__HANDLE__)->Instance->DR; \
- tmpreg_ovr = (__HANDLE__)->Instance->SR; \
- UNUSED(tmpreg_ovr); \
+ __IO uint32_t tmpreg_ovr = 0x00U; \
+ tmpreg_ovr = (__HANDLE__)->Instance->DR; \
+ tmpreg_ovr = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg_ovr); \
}while(0U)
/** @brief Clears the I2S UDR pending flag.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\
- __IO uint32_t tmpreg_udr = 0x00U;\
- tmpreg_udr = ((__HANDLE__)->Instance->SR);\
- UNUSED(tmpreg_udr); \
+ __IO uint32_t tmpreg_udr = 0x00U;\
+ tmpreg_udr = ((__HANDLE__)->Instance->SR);\
+ UNUSED(tmpreg_udr); \
+ }while(0U)
+/** @brief Flush the I2S DR Register.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_FLUSH_RX_DR(__HANDLE__) do{\
+ __IO uint32_t tmpreg_dr = 0x00U;\
+ tmpreg_dr = ((__HANDLE__)->Instance->DR);\
+ UNUSED(tmpreg_dr); \
}while(0U)
/**
* @}
@@ -442,7 +454,8 @@ void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
+ pI2S_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/**
@@ -497,21 +510,13 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2S_Private_Constants I2S Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2S_Private_Macros I2S Private Macros
* @{
*/
/** @brief Check whether the specified SPI flag is set or not.
- * @param __SR__ copy of I2S SR regsiter.
+ * @param __SR__ copy of I2S SR register.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
@@ -522,10 +527,11 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
* @arg I2S_FLAG_BSY: Busy flag
* @retval SET or RESET.
*/
-#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
+#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__)\
+ & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
/** @brief Check whether the specified SPI Interrupt is set or not.
- * @param __CR2__ copy of I2S CR2 regsiter.
+ * @param __CR2__ copy of I2S CR2 register.
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
* This parameter can be one of the following values:
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
@@ -533,7 +539,8 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
* @arg I2S_IT_ERR: Error interrupt enable
* @retval SET or RESET.
*/
-#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__)\
+ & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks if I2S Mode parameter is in allowed range.
* @param __MODE__ specifies the I2S Mode.
@@ -561,7 +568,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \
((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
- ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
+ ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
#define IS_I2S_FULLDUPLEX_MODE(MODE) (((MODE) == I2S_FULLDUPLEXMODE_DISABLE) || \
((MODE) == I2S_FULLDUPLEXMODE_ENABLE))
@@ -572,7 +579,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
* @retval None
*/
#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \
- ((__CPOL__) == I2S_CPOL_HIGH))
+ ((__CPOL__) == I2S_CPOL_HIGH))
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || defined(STM32F479xx)
#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s_ex.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s_ex.h
index 19cd806181..10335f49f4 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s_ex.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s_ex.h
@@ -74,7 +74,8 @@ extern "C" {
* @arg I2S_IT_ERR: Error interrupt enable
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_I2SEXT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((I2SxEXT((__HANDLE__)->Instance)->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_I2SEXT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((I2SxEXT((__HANDLE__)->Instance)->CR2\
+ & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks whether the specified I2SExt flag is set or not.
* @param __HANDLE__ specifies the I2S Handle.
@@ -96,19 +97,29 @@ extern "C" {
* @retval None
*/
#define __HAL_I2SEXT_CLEAR_OVRFLAG(__HANDLE__) do{ \
- __IO uint32_t tmpreg_ovr = 0x00U; \
- tmpreg_ovr = I2SxEXT((__HANDLE__)->Instance)->DR;\
- tmpreg_ovr = I2SxEXT((__HANDLE__)->Instance)->SR;\
- UNUSED(tmpreg_ovr); \
+ __IO uint32_t tmpreg_ovr = 0x00U; \
+ tmpreg_ovr = I2SxEXT((__HANDLE__)->Instance)->DR;\
+ tmpreg_ovr = I2SxEXT((__HANDLE__)->Instance)->SR;\
+ UNUSED(tmpreg_ovr); \
}while(0U)
/** @brief Clears the I2SExt UDR pending flag.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2SEXT_CLEAR_UDRFLAG(__HANDLE__) do{ \
- __IO uint32_t tmpreg_udr = 0x00U; \
- tmpreg_udr = I2SxEXT((__HANDLE__)->Instance)->SR;\
- UNUSED(tmpreg_udr); \
+ __IO uint32_t tmpreg_udr = 0x00U; \
+ tmpreg_udr = I2SxEXT((__HANDLE__)->Instance)->SR;\
+ UNUSED(tmpreg_udr); \
+ }while(0U)
+/** @brief Flush the I2S and I2SExt DR Registers.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2SEXT_FLUSH_RX_DR(__HANDLE__) do{ \
+ __IO uint32_t tmpreg_dr = 0x00U; \
+ tmpreg_dr = I2SxEXT((__HANDLE__)->Instance)->DR; \
+ tmpreg_dr = ((__HANDLE__)->Instance->DR); \
+ UNUSED(tmpreg_dr); \
}while(0U)
/**
* @}
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_irda.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_irda.h
index b30945e78f..4d83abc22d 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_irda.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_irda.h
@@ -83,9 +83,9 @@ typedef struct
* 01 : (Not Used)
* 10 : Timeout
* 11 : Error
- * b5 IP initilisation status
+ * b5 IP initialisation status
* 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized. HAL IRDA Init function already called)
+ * 1 : Init done (IP initialized. HAL IRDA Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
@@ -100,9 +100,9 @@ typedef struct
* RxState value coding follow below described bitmap :
* b7-b6 (not used)
* xx : Should be set to 00
- * b5 IP initilisation status
+ * b5 IP initialisation status
* 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized)
+ * 1 : Init done (IP initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
@@ -642,11 +642,11 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
#define IS_IRDA_BAUDRATE(BAUDRATE) ((BAUDRATE) < 115201U)
-#define IRDA_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
+#define IRDA_DIV(_PCLK_, _BAUD_) ((uint32_t)((((uint64_t)(_PCLK_))*25U)/(4U*(((uint64_t)(_BAUD_))))))
#define IRDA_DIVMANT(_PCLK_, _BAUD_) (IRDA_DIV((_PCLK_), (_BAUD_))/100U)
-#define IRDA_DIVFRAQ(_PCLK_, _BAUD_) (((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
+#define IRDA_DIVFRAQ(_PCLK_, _BAUD_) ((((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U) + 50U) / 100U)
/* UART BRR = mantissa + overflow + fraction
= (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h
index ced1099f31..32f5ff027a 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h
@@ -84,13 +84,10 @@ typedef struct
#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
-
/**
* @}
*/
-
-
/**
* @}
*/
@@ -128,7 +125,7 @@ typedef struct
* @{
*/
/* Initialization/Start functions ********************************************/
-HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
/**
* @}
*/
@@ -137,7 +134,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
* @{
*/
/* I/O operation functions ****************************************************/
-HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
/**
* @}
*/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_lptim.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_lptim.h
index 39a8164553..a5ab815fdd 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_lptim.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_lptim.h
@@ -4,7 +4,7 @@
* @author MCD Application Team
* @brief Header file of LPTIM HAL module.
******************************************************************************
- * @attention
+ * @attention
*
*
@@ -13,7 +13,8 @@
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
- * ******************************************************************************
+ *
+ ******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@@ -355,10 +356,10 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
*/
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \
- (__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
+ (__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
#else
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
@@ -376,6 +377,8 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @note The following sequence is required to solve LPTIM disable HW limitation.
* Please check Errata Sheet ES0335 for more details under "MCU may remain
* stuck in LPTIM interrupt when entering Stop mode" section.
+ * @note Please call @ref HAL_LPTIM_GetState() after a call to __HAL_LPTIM_DISABLE to
+ * check for TIMEOUT.
* @retval None
*/
#define __HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__)
@@ -398,6 +401,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @param __HANDLE__ LPTIM handle
* @param __VALUE__ Autoreload value
* @retval None
+ * @note The ARR register can only be modified when the LPTIM instance is enabled.
*/
#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
@@ -406,6 +410,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @param __HANDLE__ LPTIM handle
* @param __VALUE__ Compare value
* @retval None
+ * @note The CMP register can only be modified when the LPTIM instance is enabled.
*/
#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
@@ -454,6 +459,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
* @retval None.
+ * @note The LPTIM interrupts can only be enabled when the LPTIM instance is disabled.
*/
#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
@@ -470,6 +476,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
* @retval None.
+ * @note The LPTIM interrupts can only be disabled when the LPTIM instance is disabled.
*/
#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
@@ -488,7 +495,8 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @retval Interrupt status.
*/
-#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\
+ & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief LPTIM Option Register
* @param __HANDLE__ LPTIM handle
@@ -506,49 +514,58 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @brief Enable interrupt on the LPTIM Wake-up Timer associated Exti line.
* @retval None
*/
-#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR\
+ |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Disable interrupt on the LPTIM Wake-up Timer associated Exti line.
* @retval None
*/
-#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR\
+ &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
/**
* @brief Enable event on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
-#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR\
+ |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Disable event on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
-#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR\
+ &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
+#if defined(EXTI_IMR_MR23)
/**
* @brief Enable falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
-#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR\
+ |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Disable falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
-#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR\
+ &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
/**
* @brief Enable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
-#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR\
+ |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Disable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
-#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR\
+ &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
/**
* @brief Enable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
@@ -563,26 +580,30 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @retval None.
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\
- __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\
}while(0)
/**
* @brief Check whether the LPTIM Wake-up Timer associated Exti line interrupt flag is set or not.
* @retval Line Status.
*/
-#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR\
+ & LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Clear the LPTIM Wake-up Timer associated Exti line flag.
* @retval None.
*/
-#define __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR\
+ = LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Generate a Software interrupt on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
-#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER\
+ |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+#endif /* EXTI_IMR_MR23 */
/**
* @}
@@ -593,6 +614,10 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @{
*/
+/** @addtogroup LPTIM_Exported_Functions_Group1
+ * @brief Initialization and Configuration functions.
+ * @{
+ */
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
@@ -600,7 +625,14 @@ HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
/* MSP functions *************************************************************/
void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
+/**
+ * @}
+ */
+/** @addtogroup LPTIM_Exported_Functions_Group2
+ * @brief Start-Stop operation functions.
+ * @{
+ */
/* Start/Stop operation functions *********************************************/
/* ################################# PWM Mode ################################*/
/* Blocking mode: Polling */
@@ -649,12 +681,26 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+/**
+ * @}
+ */
+/** @addtogroup LPTIM_Exported_Functions_Group3
+ * @brief Read operation functions.
+ * @{
+ */
/* Reading operation functions ************************************************/
uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
+/**
+ * @}
+ */
+/** @addtogroup LPTIM_Exported_Functions_Group4
+ * @brief LPTIM IRQ handler and callback functions.
+ * @{
+ */
/* LPTIM IRQ functions *******************************************************/
void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
@@ -669,12 +715,23 @@ void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID,
+ pLPTIM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+/** @addtogroup LPTIM_Group5
+ * @brief Peripheral State functions.
+ * @{
+ */
/* Peripheral State functions ************************************************/
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
+/**
+ * @}
+ */
/**
* @}
@@ -739,13 +796,13 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
-#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
- ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
- ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
- ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
- ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
- ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
- ((__TRIG__) == LPTIM_TRIGSOURCE_5))
+#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_5))
#define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING ) || \
((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING ) || \
@@ -778,7 +835,7 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
* @{
*/
-void LPTIM_Disable(LPTIM_HandleTypeDef *lptim);
+void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim);
/**
* @}
*/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc.h
index a862f2cc8e..0cab8446ef 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc.h
@@ -25,11 +25,10 @@
extern "C" {
#endif
-#if defined (LTDC)
-
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
+#if defined (LTDC)
/** @addtogroup STM32F4xx_HAL_Driver
* @{
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc_ex.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc_ex.h
index b46457fea4..37a5fdf47a 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc_ex.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc_ex.h
@@ -25,10 +25,11 @@
extern "C" {
#endif
-#if defined (LTDC) && defined (DSI)
-
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
+
+#if defined (LTDC) && defined (DSI)
+
#include "stm32f4xx_hal_dsi.h"
/** @addtogroup STM32F4xx_HAL_Driver
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_mmc.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_mmc.h
index 90a44befcd..e65172acd6 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_mmc.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_mmc.h
@@ -12,25 +12,21 @@
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_MMC_H
-#define __STM32F4xx_HAL_MMC_H
+#ifndef STM32F4xx_HAL_MMC_H
+#define STM32F4xx_HAL_MMC_H
+
+#if defined(SDIO)
#ifdef __cplusplus
extern "C" {
#endif
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
- defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
- defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_ll_sdmmc.h"
@@ -38,8 +34,7 @@
* @{
*/
-/** @defgroup MMC MMC
- * @brief MMC HAL module driver
+/** @addtogroup MMC
* @{
*/
@@ -59,7 +54,7 @@ typedef enum
HAL_MMC_STATE_BUSY = 0x00000003U, /*!< MMC process ongoing */
HAL_MMC_STATE_PROGRAMMING = 0x00000004U, /*!< MMC Programming State */
HAL_MMC_STATE_RECEIVING = 0x00000005U, /*!< MMC Receinving State */
- HAL_MMC_STATE_TRANSFER = 0x00000006U, /*!< MMC Transfert State */
+ HAL_MMC_STATE_TRANSFER = 0x00000006U, /*!< MMC Transfer State */
HAL_MMC_STATE_ERROR = 0x0000000FU /*!< MMC is in error state */
}HAL_MMC_StateTypeDef;
/**
@@ -69,18 +64,17 @@ typedef enum
/** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure
* @{
*/
-typedef enum
-{
- HAL_MMC_CARD_READY = 0x00000001U, /*!< Card state is ready */
- HAL_MMC_CARD_IDENTIFICATION = 0x00000002U, /*!< Card is in identification state */
- HAL_MMC_CARD_STANDBY = 0x00000003U, /*!< Card is in standby state */
- HAL_MMC_CARD_TRANSFER = 0x00000004U, /*!< Card is in transfer state */
- HAL_MMC_CARD_SENDING = 0x00000005U, /*!< Card is sending an operation */
- HAL_MMC_CARD_RECEIVING = 0x00000006U, /*!< Card is receiving operation information */
- HAL_MMC_CARD_PROGRAMMING = 0x00000007U, /*!< Card is in programming state */
- HAL_MMC_CARD_DISCONNECTED = 0x00000008U, /*!< Card is disconnected */
- HAL_MMC_CARD_ERROR = 0x000000FFU /*!< Card response Error */
-}HAL_MMC_CardStateTypeDef;
+typedef uint32_t HAL_MMC_CardStateTypeDef;
+
+#define HAL_MMC_CARD_READY 0x00000001U /*!< Card state is ready */
+#define HAL_MMC_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */
+#define HAL_MMC_CARD_STANDBY 0x00000003U /*!< Card is in standby state */
+#define HAL_MMC_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */
+#define HAL_MMC_CARD_SENDING 0x00000005U /*!< Card is sending an operation */
+#define HAL_MMC_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */
+#define HAL_MMC_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */
+#define HAL_MMC_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */
+#define HAL_MMC_CARD_ERROR 0x000000FFU /*!< Card response Error */
/**
* @}
*/
@@ -121,17 +115,17 @@ typedef struct __MMC_HandleTypeDef
typedef struct
#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
{
- MMC_TypeDef *Instance; /*!< MMC registers base address */
+ MMC_TypeDef *Instance; /*!< MMC registers base address */
MMC_InitTypeDef Init; /*!< MMC required parameters */
HAL_LockTypeDef Lock; /*!< MMC locking object */
- uint32_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */
+ uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */
uint32_t TxXferSize; /*!< MMC Tx Transfer size */
- uint32_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */
+ uint8_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */
uint32_t RxXferSize; /*!< MMC Rx Transfer size */
@@ -146,11 +140,12 @@ typedef struct
DMA_HandleTypeDef *hdmatx; /*!< MMC Tx DMA handle parameters */
HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */
-
+
uint32_t CSD[4U]; /*!< MMC card specific data table */
uint32_t CID[4U]; /*!< MMC card identification number table */
- #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
void (* TxCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
void (* RxCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
void (* ErrorCallback) (struct __MMC_HandleTypeDef *hmmc);
@@ -199,7 +194,7 @@ typedef struct
__IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
__IO uint8_t Reserved3; /*!< Reserved */
__IO uint8_t ContentProtectAppli; /*!< Content protection application */
- __IO uint8_t FileFormatGrouop; /*!< File format group */
+ __IO uint8_t FileFormatGroup; /*!< File format group */
__IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
__IO uint8_t PermWrProtect; /*!< Permanent write protection */
__IO uint8_t TempWrProtect; /*!< Temporary write protection */
@@ -234,28 +229,8 @@ typedef struct
* @}
*/
-/** @defgroup MMC_Exported_Types_Group6 MMC Card Status returned by ACMD13
- * @{
- */
-typedef struct
-{
- __IO uint8_t DataBusWidth; /*!< Shows the currently defined data bus width */
- __IO uint8_t SecuredMode; /*!< Card is in secured mode of operation */
- __IO uint16_t CardType; /*!< Carries information about card type */
- __IO uint32_t ProtectedAreaSize; /*!< Carries information about the capacity of protected area */
- __IO uint8_t SpeedClass; /*!< Carries information about the speed class of the card */
- __IO uint8_t PerformanceMove; /*!< Carries information about the card's performance move */
- __IO uint8_t AllocationUnitSize; /*!< Carries information about the card's allocation unit size */
- __IO uint16_t EraseSize; /*!< Determines the number of AUs to be erased in one operation */
- __IO uint8_t EraseTimeout; /*!< Determines the timeout for any number of AU erase */
- __IO uint8_t EraseOffset; /*!< Carries information about the erase offset */
-
-}HAL_MMC_CardStatusTypeDef;
-/**
- * @}
- */
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
-/** @defgroup MMC_Exported_Types_Group7 MMC Callback ID enumeration definition
+/** @defgroup MMC_Exported_Types_Group6 MMC Callback ID enumeration definition
* @{
*/
typedef enum
@@ -268,15 +243,15 @@ typedef enum
HAL_MMC_MSP_INIT_CB_ID = 0x10U, /*!< MMC MspInit Callback ID */
HAL_MMC_MSP_DEINIT_CB_ID = 0x11U /*!< MMC MspDeInit Callback ID */
}HAL_MMC_CallbackIDTypeDef;
-/**
+/**
* @}
*/
-/** @defgroup MMC_Exported_Types_Group7 MMC Callback pointer definition
+/** @defgroup MMC_Exported_Types_Group7 MMC Callback pointer definition
* @{
*/
typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
-/**
+/**
* @}
*/
#endif
@@ -289,9 +264,7 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
* @{
*/
-#define BLOCKSIZE 512U /*!< Block size is 512 bytes */
-
-#define CAPACITY 0x400000U /*!< Log Block Nuumber for 2 G bytes Cards */
+#define MMC_BLOCKSIZE 512U /*!< Block size is 512 bytes */
/** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition
* @{
@@ -332,6 +305,7 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
+
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */
#endif
@@ -339,16 +313,16 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
* @}
*/
-/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration structure
+/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration
* @{
*/
-#define MMC_CONTEXT_NONE 0x00000000U /*!< None */
-#define MMC_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */
-#define MMC_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */
-#define MMC_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */
-#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */
-#define MMC_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */
-#define MMC_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */
+#define MMC_CONTEXT_NONE 0x00000000U /*!< None */
+#define MMC_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */
+#define MMC_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */
+#define MMC_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */
+#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */
+#define MMC_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */
+#define MMC_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */
/**
* @}
@@ -372,8 +346,9 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
/** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards
* @{
*/
-#define MMC_HIGH_VOLTAGE_CARD 0x00000000U
-#define MMC_DUAL_VOLTAGE_CARD 0x00000001U
+#define MMC_LOW_CAPACITY_CARD 0x00000000U /*!< MMC Card Capacity <=2Gbytes */
+#define MMC_HIGH_CAPACITY_CARD 0x00000001U /*!< MMC Card Capacity >2Gbytes and <2Tbytes */
+
/**
* @}
*/
@@ -427,8 +402,8 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
/**
* @brief Enable the MMC device interrupt.
- * @param __HANDLE__ MMC Handle
- * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled.
+ * @param __HANDLE__: MMC Handle
+ * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -438,7 +413,7 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
@@ -458,8 +433,8 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
/**
* @brief Disable the MMC device interrupt.
- * @param __HANDLE__ MMC Handle
- * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled.
+ * @param __HANDLE__: MMC Handle
+ * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -469,7 +444,7 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
@@ -489,8 +464,8 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
/**
* @brief Check whether the specified MMC flag is set or not.
- * @param __HANDLE__ MMC Handle
- * @param __FLAG__ specifies the flag to check.
+ * @param __HANDLE__: MMC Handle
+ * @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
@@ -500,7 +475,7 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDIO_FLAG_CMDACT: Command transfer in progress
* @arg SDIO_FLAG_TXACT: Data transmit in progress
@@ -520,8 +495,8 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
/**
* @brief Clear the MMC's pending flags.
- * @param __HANDLE__ MMC Handle
- * @param __FLAG__ specifies the flag to clear.
+ * @param __HANDLE__: MMC Handle
+ * @param __FLAG__: specifies the flag to clear.
* This parameter can be one or a combination of the following values:
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
@@ -531,7 +506,7 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
* @retval None
@@ -540,8 +515,8 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
/**
* @brief Check whether the specified MMC interrupt has occurred or not.
- * @param __HANDLE__ MMC Handle
- * @param __INTERRUPT__ specifies the SDMMC interrupt source to check.
+ * @param __HANDLE__: MMC Handle
+ * @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
* This parameter can be one of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -551,7 +526,7 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
@@ -571,8 +546,8 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
/**
* @brief Clear the MMC's interrupt pending bits.
- * @param __HANDLE__ MMC Handle
- * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * @param __HANDLE__: MMC Handle
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -582,7 +557,12 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
* @retval None
*/
@@ -605,6 +585,7 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc);
HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc);
void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc);
void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc);
+
/**
* @}
*/
@@ -652,9 +633,9 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32
* @{
*/
HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc);
-HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID);
-HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD);
-HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);
+HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID);
+HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD);
+HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);
/**
* @}
*/
@@ -740,6 +721,7 @@ HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc);
* @}
*/
+
/**
* @}
*/
@@ -752,15 +734,12 @@ HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc);
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
- STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
- STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
-
#ifdef __cplusplus
}
#endif
+#endif /* SDIO */
-#endif /* __STM32F4xx_HAL_MMC_H */
+#endif /* STM32F4xx_HAL_MMC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h
index 2db595c44c..87b9efa0a9 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h
@@ -96,16 +96,16 @@ typedef struct __PCD_HandleTypeDef
typedef struct
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
- PCD_TypeDef *Instance; /*!< Register base address */
- PCD_InitTypeDef Init; /*!< PCD required parameters */
- __IO uint8_t USB_Address; /*!< USB Address */
- PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
- PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
- HAL_LockTypeDef Lock; /*!< PCD peripheral status */
- __IO PCD_StateTypeDef State; /*!< PCD communication state */
- __IO uint32_t ErrorCode; /*!< PCD Error code */
- uint32_t Setup[12]; /*!< Setup packet buffer */
- PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
+ PCD_TypeDef *Instance; /*!< Register base address */
+ PCD_InitTypeDef Init; /*!< PCD required parameters */
+ __IO uint8_t USB_Address; /*!< USB Address */
+ PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
+ PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
+ HAL_LockTypeDef Lock; /*!< PCD peripheral status */
+ __IO PCD_StateTypeDef State; /*!< PCD communication state */
+ __IO uint32_t ErrorCode; /*!< PCD Error code */
+ uint32_t Setup[12]; /*!< Setup packet buffer */
+ PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
uint32_t BESL;
@@ -187,9 +187,9 @@ typedef struct
/* Exported macros -----------------------------------------------------------*/
/** @defgroup PCD_Exported_Macros PCD Exported Macros
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
@@ -199,12 +199,11 @@ typedef struct
#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
-#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
- ~(USB_OTG_PCGCCTL_STOPCLK)
+#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK)
-#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
+#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
-#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
+#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
@@ -212,20 +211,20 @@ typedef struct
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
- do { \
- EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE); \
- EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE; \
- } while(0U)
+ do { \
+ EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE); \
+ EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE; \
+ } while(0U)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
- do { \
- EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
- EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
- } while(0U)
+ do { \
+ EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
+ EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
+ } while(0U)
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
@@ -260,7 +259,7 @@ typedef enum
HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */
HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */
HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */
- HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
+ HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */
HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */
@@ -287,25 +286,41 @@ typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgType
* @}
*/
-HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
+ HAL_PCD_CallbackIDTypeDef CallbackID,
+ pPCD_CallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd,
+ HAL_PCD_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_DataOutStageCallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_DataInStageCallbackTypeDef pCallback);
+
HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_IsoOutIncpltCallbackTypeDef pCallback);
+
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_IsoInIncpltCallbackTypeDef pCallback);
+
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_BcdCallbackTypeDef pCallback);
+
HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_LpmCallbackTypeDef pCallback);
+
HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/**
@@ -320,6 +335,7 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_WKUP_IRQHandler(PCD_HandleTypeDef *hpcd);
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
@@ -344,16 +360,24 @@ void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
+ uint16_t ep_mps, uint8_t ep_type);
+
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
-uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
+ uint8_t *pBuf, uint32_t len);
+
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
+ uint8_t *pBuf, uint32_t len);
+
+
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+
+uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
/**
* @}
*/
@@ -379,14 +403,6 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @{
*/
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
-#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 0x08U
-#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
-#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
-
-#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 0x08U
-#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
-#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
-
#define USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */
#define USB_OTG_HS_WAKEUP_EXTI_LINE (0x1U << 20) /*!< USB HS EXTI Line WakeUp Interrupt */
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
@@ -427,8 +443,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
/* Private macros ------------------------------------------------------------*/
/** @defgroup PCD_Private_Macros PCD Private Macros
- * @{
- */
+ * @{
+ */
/**
* @}
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_qspi.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_qspi.h
index 4c5de584d8..97e9324f34 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_qspi.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_qspi.h
@@ -6,82 +6,74 @@
******************************************************************************
* @attention
*
- *
*
* This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
+ * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_QSPI_H
-#define __STM32F4xx_HAL_QSPI_H
+#ifndef STM32F4xx_HAL_QSPI_H
+#define STM32F4xx_HAL_QSPI_H
#ifdef __cplusplus
extern "C" {
#endif
-#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
- defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
+#if defined(QUADSPI)
+
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
/** @addtogroup QSPI
* @{
- */
+ */
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
/** @defgroup QSPI_Exported_Types QSPI Exported Types
* @{
*/
-
-/**
- * @brief QSPI Init structure definition
- */
+/**
+ * @brief QSPI Init structure definition
+ */
typedef struct
{
uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
- This parameter can be a number between 0 and 255 */
-
+ This parameter can be a number between 0 and 255 */
uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
This parameter can be a value between 1 and 32 */
-
- uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
+ uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
This parameter can be a value of @ref QSPI_SampleShifting */
-
- uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
- required to address the flash memory. The flash capacity can be up to 4GB
- (addressed using 32 bits) in indirect mode, but the addressable space in
+ uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
+ required to address the flash memory. The flash capacity can be up to 4GB
+ (addressed using 32 bits) in indirect mode, but the addressable space in
memory-mapped mode is limited to 256MB
This parameter can be a number between 0 and 31 */
-
- uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
+ uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
of clock cycles which the chip select must remain high between commands.
- This parameter can be a value of @ref QSPI_ChipSelectHighTime */
-
+ This parameter can be a value of @ref QSPI_ChipSelectHighTime */
uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
This parameter can be a value of @ref QSPI_ClockMode */
-
uint32_t FlashID; /* Specifies the Flash which will be used,
This parameter can be a value of @ref QSPI_Flash_Select */
-
uint32_t DualFlash; /* Specifies the Dual Flash Mode State
This parameter can be a value of @ref QSPI_DualFlash_Mode */
}QSPI_InitTypeDef;
-/**
- * @brief HAL QSPI State structures definition
- */
+/**
+ * @brief HAL QSPI State structures definition
+ */
typedef enum
{
HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */
@@ -134,17 +126,17 @@ typedef struct
#endif
}QSPI_HandleTypeDef;
-/**
- * @brief QSPI Command structure definition
+/**
+ * @brief QSPI Command structure definition
*/
typedef struct
{
uint32_t Instruction; /* Specifies the Instruction to be sent
This parameter can be a value (8-bit) between 0x00 and 0xFF */
uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
- This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFFU */
+ This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
- This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFFU */
+ This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
uint32_t AddressSize; /* Specifies the Address Size
This parameter can be a value of @ref QSPI_AddressSize */
uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
@@ -159,29 +151,29 @@ typedef struct
This parameter can be a value of @ref QSPI_AlternateBytesMode */
uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
This parameter can be a value of @ref QSPI_DataMode */
- uint32_t NbData; /* Specifies the number of data to transfer.
- This parameter can be any value between 0 and 0xFFFFFFFFU (0 means undefined length
+ uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes)
+ This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
until end of memory)*/
uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
This parameter can be a value of @ref QSPI_DdrMode */
- uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of
- system clock in DDR mode.
+ uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the data
+ output by one half of system clock in DDR mode.
This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
- uint32_t SIOOMode; /* Specifies the send instruction only once mode
+ uint32_t SIOOMode; /* Specifies the send instruction only once mode
This parameter can be a value of @ref QSPI_SIOOMode */
}QSPI_CommandTypeDef;
-/**
- * @brief QSPI Auto Polling mode configuration structure definition
+/**
+ * @brief QSPI Auto Polling mode configuration structure definition
*/
typedef struct
{
uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
- This parameter can be any value between 0 and 0xFFFFFFFFU */
- uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
- This parameter can be any value between 0 and 0xFFFFFFFFU */
+ This parameter can be any value between 0 and 0xFFFFFFFF */
+ uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
+ This parameter can be any value between 0 and 0xFFFFFFFF */
uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
- This parameter can be any value between 0 and 0xFFFFU */
+ This parameter can be any value between 0 and 0xFFFF */
uint32_t StatusBytesSize; /* Specifies the size of the status bytes received.
This parameter can be any value between 1 and 4 */
uint32_t MatchMode; /* Specifies the method used for determining a match.
@@ -190,14 +182,14 @@ typedef struct
This parameter can be a value of @ref QSPI_AutomaticStop */
}QSPI_AutoPollingTypeDef;
-/**
- * @brief QSPI Memory Mapped mode configuration structure definition
+/**
+ * @brief QSPI Memory Mapped mode configuration structure definition
*/
typedef struct
{
uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
- This parameter can be any value between 0 and 0xFFFFU */
- uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select.
+ This parameter can be any value between 0 and 0xFFFF */
+ uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select.
This parameter can be a value of @ref QSPI_TimeOutActivation */
}QSPI_MemoryMappedTypeDef;
@@ -235,41 +227,42 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_Exported_Constants QSPI Exported Constants
* @{
*/
+
/** @defgroup QSPI_ErrorCode QSPI Error Code
* @{
- */
-#define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */
-#define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */
-#define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */
-#define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */
+ */
+#define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */
+#define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */
+#define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */
+#define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
#define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */
#endif
/**
* @}
- */
-
+ */
+
/** @defgroup QSPI_SampleShifting QSPI Sample Shifting
* @{
*/
-#define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -18,8 +18,8 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_LL_DAC_H
-#define __STM32F4xx_LL_DAC_H
+#ifndef STM32F4xx_LL_DAC_H
+#define STM32F4xx_LL_DAC_H
#ifdef __cplusplus
extern "C" {
@@ -48,52 +48,86 @@ extern "C" {
/* Internal masks for DAC channels definition */
/* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
-/* - channel bits position into register CR */
+/* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */
/* - channel bits position into register SWTRIG */
/* - channel register offset of data holding register DHRx */
/* - channel register offset of data output register DORx */
-#define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
-#define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
+#define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers
+ CR, MCR, CCR, SHHR, SHRR of channel 1 */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers
+ CR, MCR, CCR, SHHR, SHRR of channel 2 */
#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
+#else
+#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET)
+#endif /* DAC_CHANNEL2_SUPPORT */
-#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
+#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
#if defined(DAC_CHANNEL2_SUPPORT)
-#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
+#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
#else
#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1)
#endif /* DAC_CHANNEL2_SUPPORT */
-#define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
-#define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
-#define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
+#define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
+#define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus
+ DHR12Rx channel 1 (shifted left of 20 bits) */
+#define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus
+ DHR12Rx channel 1 (shifted left of 24 bits) */
#if defined(DAC_CHANNEL2_SUPPORT)
-#define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
-#define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
-#define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
+#define DAC_REG_DHR12R2_REGOFFSET 0x00030000UL /* Register offset of DHR12Rx channel 2 versus
+ DHR12Rx channel 1 (shifted left of 16 bits) */
+#define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus
+ DHR12Rx channel 1 (shifted left of 20 bits) */
+#define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus
+ DHR12Rx channel 1 (shifted left of 24 bits) */
#endif /* DAC_CHANNEL2_SUPPORT */
-#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
-#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
-#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
-#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
+#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000UL
+#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
+#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
+#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\
+ | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
-#define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
+#define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
#if defined(DAC_CHANNEL2_SUPPORT)
-#define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
+#define DAC_REG_DOR2_REGOFFSET 0x10000000UL /* Register offset of DORx channel 1 versus
+ DORx channel 2 (shifted left of 28 bits) */
#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
-#else
-#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET)
#endif /* DAC_CHANNEL2_SUPPORT */
+
+#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
+ DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
+#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted
+ to position 0 */
+#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted
+ to position 0 */
+
+#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 16UL /* Position of bits register offset of DHR12Rx
+ channel 1 or 2 versus DHR12Rx channel 1
+ (shifted left of 16 bits) */
+#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx
+ channel 1 or 2 versus DHR12Rx channel 1
+ (shifted left of 20 bits) */
+#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx
+ channel 1 or 2 versus DHR12Rx channel 1
+ (shifted left of 24 bits) */
+#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DORx
+ channel 1 or 2 versus DORx channel 1
+ (shifted left of 28 bits) */
+
/* DAC registers bits positions */
#if defined(DAC_CHANNEL2_SUPPORT)
-#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
-#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
-#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
-#endif /* DAC_CHANNEL2_SUPPORT */
+#endif
+#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
+#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
+#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
/* Miscellaneous data */
-#define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
+#define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12
+ bits (voltage range determined by analog voltage
+ references Vref+ and Vref-, refer to reference manual) */
/**
* @}
@@ -105,27 +139,16 @@ extern "C" {
* @{
*/
-/**
- * @brief Driver macro reserved for internal use: isolate bits with the
- * selected mask and shift them to the register LSB
- * (shift mask on register position bit 0).
- * @param __BITS__ Bits in register 32 bits
- * @param __MASK__ Mask in register 32 bits
- * @retval Bits in register 32 bits
-*/
-#define __DAC_MASK_SHIFT(__BITS__, __MASK__) \
- (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
-
/**
* @brief Driver macro reserved for internal use: set a pointer to
* a register from a register basis from which an offset
* is applied.
* @param __REG__ Register basis from which the offset is applied.
- * @param __REG_OFFFSET__ Offset to be applied (unit number of registers).
+ * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
* @retval Pointer to register address
-*/
+ */
#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
- ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
+ ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
/**
* @}
@@ -143,28 +166,38 @@ extern "C" {
*/
typedef struct
{
- uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
+ uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel:
+ internal (SW start) or from external peripheral
+ (timer event, external interrupt line).
This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
-
- This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_DAC_SetTriggerSource(). */
uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
-
- This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_DAC_SetWaveAutoGeneration(). */
uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
- If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
- If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
- @note If waveform automatic generation mode is disabled, this parameter is discarded.
-
- This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
+ If waveform automatic generation mode is set to noise, this parameter
+ can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
+ If waveform automatic generation mode is set to triangle,
+ this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
+ @note If waveform automatic generation mode is disabled,
+ this parameter is discarded.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_DAC_SetWaveNoiseLFSR(),
+ @ref LL_DAC_SetWaveTriangleAmplitude()
+ depending on the wave automatic generation selected. */
uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
-
- This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
+ This feature can be modified afterwards using unitary
+ function @ref LL_DAC_SetOutputBuffer(). */
} LL_DAC_InitTypeDef;
/**
@@ -183,7 +216,6 @@ typedef struct
*/
/* DAC channel 1 flags */
#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
-
#if defined(DAC_CHANNEL2_SUPPORT)
/* DAC channel 2 flags */
#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
@@ -219,13 +251,13 @@ typedef struct
* @{
*/
#define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
-#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
-#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
+#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM4 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000UL /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM5 TRGO. */
+#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */
/**
* @}
*/
@@ -233,9 +265,9 @@ typedef struct
/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
* @{
*/
-#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */
-#define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
-#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
+#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */
+#define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
+#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
/**
* @}
*/
@@ -243,7 +275,7 @@ typedef struct
/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
* @{
*/
-#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
@@ -262,7 +294,7 @@ typedef struct
/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
* @{
*/
-#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
@@ -281,18 +313,17 @@ typedef struct
/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
* @{
*/
-#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
+#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
/**
* @}
*/
-
/** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
* @{
*/
-#define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */
-#define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */
+#define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */
+#define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */
/**
* @}
*/
@@ -303,15 +334,15 @@ typedef struct
/* List of DAC registers intended to be used (most commonly) with */
/* DMA transfer. */
/* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
-#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */
-#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */
-#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK /*!< DAC channel data holding register 8 bits right aligned */
+#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
+#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
+#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */
/**
* @}
*/
/** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
- * @note Only DAC IP HW delays are defined in DAC LL driver driver,
+ * @note Only DAC peripheral HW delays are defined in DAC LL driver driver,
* not timeout values.
* For details on delays values, refer to descriptions in source code
* above each literal definition.
@@ -330,7 +361,7 @@ typedef struct
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tWAKEUP"). */
/* Unit: us */
-#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
+#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
/* Delay for DAC channel voltage settling time. */
/* Note: DAC channel startup time depends on board application environment: */
@@ -343,7 +374,8 @@ typedef struct
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tSETTLING"). */
/* Unit: us */
-#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */
+#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12UL /*!< Delay for DAC channel voltage settling time */
+
/**
* @}
*/
@@ -397,7 +429,7 @@ typedef struct
* @param __CHANNEL__ This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval 1...2 (value "2" depending on DAC channel 2 availability)
@@ -417,39 +449,39 @@ typedef struct
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
*/
#if defined(DAC_CHANNEL2_SUPPORT)
#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
- (((__DECIMAL_NB__) == 1U) \
+ (((__DECIMAL_NB__) == 1UL) \
? ( \
LL_DAC_CHANNEL_1 \
) \
: \
- (((__DECIMAL_NB__) == 2U) \
+ (((__DECIMAL_NB__) == 2UL) \
? ( \
LL_DAC_CHANNEL_2 \
) \
: \
( \
- 0 \
+ 0UL \
) \
) \
)
#else
#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
- (((__DECIMAL_NB__) == 1U) \
+ (((__DECIMAL_NB__) == 1UL) \
? ( \
LL_DAC_CHANNEL_1 \
) \
: \
( \
- 0 \
+ 0UL \
) \
)
-#endif /* DAC_CHANNEL2_SUPPORT */
+#endif /* DAC_CHANNEL2_SUPPORT */
/**
* @brief Helper macro to define the DAC conversion data full-scale digital
@@ -463,7 +495,7 @@ typedef struct
* @retval ADC conversion data equivalent voltage value (unit: mVolt)
*/
#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
- ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
+ ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
/**
* @brief Helper macro to calculate the DAC conversion data (unit: digital
@@ -474,8 +506,8 @@ typedef struct
* @ref LL_DAC_ConvertData12RightAligned().
* @note Analog reference voltage (Vref+) must be either known from
* user board environment or can be calculated using ADC measurement
- * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
- * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV)
+ * and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
* @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
* (unit: mVolt).
* @param __DAC_RESOLUTION__ This parameter can be one of the following values:
@@ -486,9 +518,9 @@ typedef struct
#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
__DAC_VOLTAGE__,\
__DAC_RESOLUTION__) \
- ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
- / (__VREFANALOG_VOLTAGE__) \
- )
+((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
+ / (__VREFANALOG_VOLTAGE__) \
+)
/**
* @}
@@ -503,10 +535,6 @@ typedef struct
/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
* @{
*/
-/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
- * @{
- */
-
/**
* @brief Set the conversion trigger source for the selected DAC channel.
* @note For conversion trigger source to be effective, DAC trigger
@@ -521,7 +549,7 @@ typedef struct
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param TriggerSource This parameter can be one of the following values:
@@ -554,7 +582,7 @@ __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Cha
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval Returned value can be one of the following values:
@@ -583,7 +611,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param WaveAutoGeneration This parameter can be one of the following values:
@@ -608,7 +636,7 @@ __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DA
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval Returned value can be one of the following values:
@@ -637,7 +665,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param NoiseLFSRMask This parameter can be one of the following values:
@@ -663,7 +691,7 @@ __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Cha
}
/**
- * @brief Set the noise waveform generation for the selected DAC channel:
+ * @brief Get the noise waveform generation for the selected DAC channel:
* Noise mode and parameters LFSR (linear feedback shift register).
* @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
* CR MAMP2 LL_DAC_GetWaveNoiseLFSR
@@ -671,7 +699,7 @@ __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Cha
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval Returned value can be one of the following values:
@@ -709,7 +737,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param TriangleAmplitude This parameter can be one of the following values:
@@ -727,7 +755,8 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
* @retval None
*/
-__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
+__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
+ uint32_t TriangleAmplitude)
{
MODIFY_REG(DACx->CR,
DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
@@ -735,7 +764,7 @@ __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t
}
/**
- * @brief Set the triangle waveform generation for the selected DAC channel:
+ * @brief Get the triangle waveform generation for the selected DAC channel:
* triangle mode and amplitude.
* @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
* CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
@@ -743,7 +772,7 @@ __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval Returned value can be one of the following values:
@@ -775,7 +804,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param OutputBuffer This parameter can be one of the following values:
@@ -798,7 +827,7 @@ __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Chan
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval Returned value can be one of the following values:
@@ -830,7 +859,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval None
@@ -851,7 +880,7 @@ __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval None
@@ -871,16 +900,16 @@ __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channe
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
- return (READ_BIT(DACx->CR,
- DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
- == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
+ return ((READ_BIT(DACx->CR,
+ DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
}
/**
@@ -896,7 +925,8 @@ __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_
* LL_DMA_ConfigAddresses(DMA1,
* LL_DMA_CHANNEL_1,
* (uint32_t)&< array or variable >,
- * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
+ * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1,
+ * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
* LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
* @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
* DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
@@ -908,7 +938,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param Register This parameter can be one of the following values:
@@ -921,7 +951,8 @@ __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_C
{
/* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
/* DAC channel selected. */
- return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register))));
+ return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
+ & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
}
/**
* @}
@@ -942,7 +973,7 @@ __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_C
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval None
@@ -961,7 +992,7 @@ __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval None
@@ -981,16 +1012,16 @@ __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
- return (READ_BIT(DACx->CR,
- DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
- == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
+ return ((READ_BIT(DACx->CR,
+ DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
}
/**
@@ -1009,7 +1040,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channe
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval None
@@ -1028,7 +1059,7 @@ __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channe
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval None
@@ -1048,22 +1079,24 @@ __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Chann
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
- return (READ_BIT(DACx->CR,
- DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
- == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
+ return ((READ_BIT(DACx->CR,
+ DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
}
/**
* @brief Trig DAC conversion by software for the selected DAC channel.
* @note Preliminarily, DAC trigger must be set to software trigger
- * using function @ref LL_DAC_SetTriggerSource()
+ * using function
+ * @ref LL_DAC_Init()
+ * @ref LL_DAC_SetTriggerSource()
* with parameter "LL_DAC_TRIGGER_SOFTWARE".
* and DAC trigger must be enabled using
* function @ref LL_DAC_EnableTrigger().
@@ -1077,7 +1110,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC
* @param DAC_Channel This parameter can a combination of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval None
@@ -1098,7 +1131,7 @@ __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Cha
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
@@ -1106,11 +1139,10 @@ __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Cha
*/
__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
{
- register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK));
-
- MODIFY_REG(*preg,
- DAC_DHR12R1_DACC1DHR,
- Data);
+ __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
+ & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
+
+ MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
}
/**
@@ -1123,7 +1155,7 @@ __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
@@ -1131,11 +1163,10 @@ __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_
*/
__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
{
- register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK));
-
- MODIFY_REG(*preg,
- DAC_DHR12L1_DACC1DHR,
- Data);
+ __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
+ & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
+
+ MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
}
/**
@@ -1148,7 +1179,7 @@ __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param Data Value between Min_Data=0x00 and Max_Data=0xFF
@@ -1156,11 +1187,10 @@ __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t
*/
__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
{
- register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK));
-
- MODIFY_REG(*preg,
- DAC_DHR8R1_DACC1DHR,
- Data);
+ __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
+ & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
+
+ MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
}
#if defined(DAC_CHANNEL2_SUPPORT)
@@ -1175,7 +1205,8 @@ __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t
* @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval None
*/
-__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
+__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
+ uint32_t DataChannel2)
{
MODIFY_REG(DACx->DHR12RD,
(DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
@@ -1193,7 +1224,8 @@ __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uin
* @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval None
*/
-__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
+__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
+ uint32_t DataChannel2)
{
/* Note: Data of DAC channel 2 shift value subtracted of 4 because */
/* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
@@ -1214,14 +1246,15 @@ __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint
* @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
* @retval None
*/
-__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
+__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
+ uint32_t DataChannel2)
{
MODIFY_REG(DACx->DHR8RD,
(DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
}
-
#endif /* DAC_CHANNEL2_SUPPORT */
+
/**
* @brief Retrieve output data currently generated for the selected DAC channel.
* @note Whatever alignment and resolution settings
@@ -1234,15 +1267,16 @@ __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
- *
+ *
* (1) On this STM32 serie, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
- register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK));
-
+ __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
+ & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
+
return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
}
@@ -1253,6 +1287,8 @@ __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t D
/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
* @{
*/
+
+
/**
* @brief Get DAC underrun flag for DAC channel 1
* @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
@@ -1261,7 +1297,7 @@ __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t D
*/
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
{
- return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
+ return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
}
#if defined(DAC_CHANNEL2_SUPPORT)
@@ -1273,7 +1309,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
*/
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
{
- return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
+ return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
}
#endif /* DAC_CHANNEL2_SUPPORT */
@@ -1365,7 +1401,7 @@ __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
*/
__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
{
- return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
+ return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
}
#if defined(DAC_CHANNEL2_SUPPORT)
@@ -1377,7 +1413,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
*/
__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
{
- return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
+ return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
}
#endif /* DAC_CHANNEL2_SUPPORT */
@@ -1390,9 +1426,9 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
* @{
*/
-ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
-ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
-void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
+ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx);
+ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct);
+void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
/**
* @}
@@ -1417,6 +1453,6 @@ void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
}
#endif
-#endif /* __STM32F4xx_LL_DAC_H */
+#endif /* STM32F4xx_LL_DAC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h
index a1560d6477..63264e614d 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h
@@ -285,14 +285,24 @@ typedef struct
/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
* @{
*/
-#define LL_DMA_CHANNEL_0 0x00000000U /* Select Channel0 of DMA Instance */
-#define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 /* Select Channel1 of DMA Instance */
-#define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 /* Select Channel2 of DMA Instance */
-#define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1) /* Select Channel3 of DMA Instance */
-#define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 /* Select Channel4 of DMA Instance */
-#define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel5 of DMA Instance */
-#define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel6 of DMA Instance */
-#define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel7 of DMA Instance */
+#define LL_DMA_CHANNEL_0 0x00000000U /* Select Channel0 of DMA Instance */
+#define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 /* Select Channel1 of DMA Instance */
+#define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 /* Select Channel2 of DMA Instance */
+#define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1) /* Select Channel3 of DMA Instance */
+#define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 /* Select Channel4 of DMA Instance */
+#define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel5 of DMA Instance */
+#define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel6 of DMA Instance */
+#define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel7 of DMA Instance */
+#if defined (DMA_SxCR_CHSEL_3)
+#define LL_DMA_CHANNEL_8 DMA_SxCR_CHSEL_3 /* Select Channel8 of DMA Instance */
+#define LL_DMA_CHANNEL_9 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_0) /* Select Channel9 of DMA Instance */
+#define LL_DMA_CHANNEL_10 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1) /* Select Channel10 of DMA Instance */
+#define LL_DMA_CHANNEL_11 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel11 of DMA Instance */
+#define LL_DMA_CHANNEL_12 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2) /* Select Channel12 of DMA Instance */
+#define LL_DMA_CHANNEL_13 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel13 of DMA Instance */
+#define LL_DMA_CHANNEL_14 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel14 of DMA Instance */
+#define LL_DMA_CHANNEL_15 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel15 of DMA Instance */
+#endif /* DMA_SxCR_CHSEL_3 */
/**
* @}
*/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma2d.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma2d.h
index 6864b54c47..a783d058af 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma2d.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma2d.h
@@ -66,73 +66,103 @@ typedef struct
uint32_t Mode; /*!< Specifies the DMA2D transfer mode.
- This parameter can be one value of @ref DMA2D_LL_EC_MODE.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetMode().*/
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetMode(). */
uint32_t ColorMode; /*!< Specifies the color format of the output image.
- This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */
+ This parameter can be modified afterwards using,
+ unitary function @ref LL_DMA2D_SetOutputColorMode(). */
uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
-
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
-
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+ This parameter can be modified afterwards
+ using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
uint32_t OutputRed; /*!< Specifies the Red value of the output image.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
-
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+ This parameter can be modified afterwards
+ using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
- This parameter is not considered if RGB888 or RGB565 color mode is selected.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ This parameter can be modified afterwards using,
+ unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
uint32_t OutputMemoryAddress; /*!< Specifies the memory address.
- - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
+ - This parameter must be a number between:
+ Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */
uint32_t LineOffset; /*!< Specifies the output line offset value.
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffset(). */
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetLineOffset(). */
uint32_t NbrOfLines; /*!< Specifies the number of lines of the area to be transferred.
- - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
+ - This parameter must be a number between:
+ Min_Data = 0x0000 and Max_Data = 0xFFFF.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfLines(). */
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetNbrOfLines(). */
- uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transfered.
+ uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transferred.
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */
+ This parameter can be modified afterwards using,
+ unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */
} LL_DMA2D_InitTypeDef;
@@ -143,7 +173,8 @@ typedef struct
typedef struct
{
uint32_t MemoryAddress; /*!< Specifies the foreground or background memory address.
- - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
+ - This parameter must be a number between:
+ Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
This parameter can be modified afterwards using unitary functions
- @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer,
@@ -213,7 +244,8 @@ typedef struct
- @ref LL_DMA2D_BGND_SetRedColor() for background layer. */
uint32_t CLUTMemoryAddress; /*!< Specifies the foreground or background CLUT memory address.
- - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
+ - This parameter must be a number between:
+ Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
This parameter can be modified afterwards using unitary functions
- @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer,
@@ -231,45 +263,68 @@ typedef struct
uint32_t ColorMode; /*!< Specifies the color format of the output image.
- This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */
+ This parameter can be modified afterwards using
+ unitary function @ref LL_DMA2D_SetOutputColorMode(). */
uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
-
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+ This parameter can be modified afterwards using,
+ unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
-
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between
+ Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
uint32_t OutputRed; /*!< Specifies the Red value of the output image.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
-
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
- This parameter is not considered if RGB888 or RGB565 color mode is selected.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
} LL_DMA2D_ColorTypeDef;
@@ -357,9 +412,11 @@ typedef struct
* @{
*/
#define LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U /*!< No modification of the alpha channel value */
-#define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by programmed alpha value */
-#define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by programmed alpha value
- with original alpha channel value */
+#define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by
+ programmed alpha value */
+#define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by
+ programmed alpha value with,
+ original alpha channel value */
/**
* @}
*/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmpi2c.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmpi2c.h
new file mode 100644
index 0000000000..1f2e707b1a
--- /dev/null
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmpi2c.h
@@ -0,0 +1,2193 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_fmpi2c.h
+ * @author MCD Application Team
+ * @brief Header file of FMPI2C LL module.
+ ******************************************************************************
+ * @attention
+ *
+ *
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F4xx_LL_FMPI2C_H
+#define STM32F4xx_LL_FMPI2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(FMPI2C_CR1_PE)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined (FMPI2C1)
+
+/** @defgroup FMPI2C_LL FMPI2C
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FMPI2C_LL_Private_Constants FMPI2C Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup FMPI2C_LL_Private_Macros FMPI2C Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup FMPI2C_LL_ES_INIT FMPI2C Exported Init structure
+ * @{
+ */
+typedef struct
+{
+ uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
+ This parameter can be a value of @ref FMPI2C_LL_EC_PERIPHERAL_MODE.
+
+ This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetMode(). */
+
+ uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
+ This parameter must be set by referring to the STM32CubeMX Tool and
+ the helper macro @ref __LL_FMPI2C_CONVERT_TIMINGS().
+
+ This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetTiming(). */
+
+ uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
+ This parameter can be a value of @ref FMPI2C_LL_EC_ANALOGFILTER_SELECTION.
+
+ This feature can be modified afterwards using unitary functions @ref LL_FMPI2C_EnableAnalogFilter() or LL_FMPI2C_DisableAnalogFilter(). */
+
+ uint32_t DigitalFilter; /*!< Configures the digital noise filter.
+ This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F.
+
+ This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetDigitalFilter(). */
+
+ uint32_t OwnAddress1; /*!< Specifies the device own address 1.
+ This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF.
+
+ This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetOwnAddress1(). */
+
+ uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
+ This parameter can be a value of @ref FMPI2C_LL_EC_I2C_ACKNOWLEDGE.
+
+ This feature can be modified afterwards using unitary function @ref LL_FMPI2C_AcknowledgeNextData(). */
+
+ uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
+ This parameter can be a value of @ref FMPI2C_LL_EC_OWNADDRESS1.
+
+ This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetOwnAddress1(). */
+} LL_FMPI2C_InitTypeDef;
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FMPI2C_LL_Exported_Constants FMPI2C Exported Constants
+ * @{
+ */
+
+/** @defgroup FMPI2C_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_FMPI2C_WriteReg function
+ * @{
+ */
+#define LL_FMPI2C_ICR_ADDRCF FMPI2C_ICR_ADDRCF /*!< Address Matched flag */
+#define LL_FMPI2C_ICR_NACKCF FMPI2C_ICR_NACKCF /*!< Not Acknowledge flag */
+#define LL_FMPI2C_ICR_STOPCF FMPI2C_ICR_STOPCF /*!< Stop detection flag */
+#define LL_FMPI2C_ICR_BERRCF FMPI2C_ICR_BERRCF /*!< Bus error flag */
+#define LL_FMPI2C_ICR_ARLOCF FMPI2C_ICR_ARLOCF /*!< Arbitration Lost flag */
+#define LL_FMPI2C_ICR_OVRCF FMPI2C_ICR_OVRCF /*!< Overrun/Underrun flag */
+#define LL_FMPI2C_ICR_PECCF FMPI2C_ICR_PECCF /*!< PEC error flag */
+#define LL_FMPI2C_ICR_TIMOUTCF FMPI2C_ICR_TIMOUTCF /*!< Timeout detection flag */
+#define LL_FMPI2C_ICR_ALERTCF FMPI2C_ICR_ALERTCF /*!< Alert flag */
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_FMPI2C_ReadReg function
+ * @{
+ */
+#define LL_FMPI2C_ISR_TXE FMPI2C_ISR_TXE /*!< Transmit data register empty */
+#define LL_FMPI2C_ISR_TXIS FMPI2C_ISR_TXIS /*!< Transmit interrupt status */
+#define LL_FMPI2C_ISR_RXNE FMPI2C_ISR_RXNE /*!< Receive data register not empty */
+#define LL_FMPI2C_ISR_ADDR FMPI2C_ISR_ADDR /*!< Address matched (slave mode) */
+#define LL_FMPI2C_ISR_NACKF FMPI2C_ISR_NACKF /*!< Not Acknowledge received flag */
+#define LL_FMPI2C_ISR_STOPF FMPI2C_ISR_STOPF /*!< Stop detection flag */
+#define LL_FMPI2C_ISR_TC FMPI2C_ISR_TC /*!< Transfer Complete (master mode) */
+#define LL_FMPI2C_ISR_TCR FMPI2C_ISR_TCR /*!< Transfer Complete Reload */
+#define LL_FMPI2C_ISR_BERR FMPI2C_ISR_BERR /*!< Bus error */
+#define LL_FMPI2C_ISR_ARLO FMPI2C_ISR_ARLO /*!< Arbitration lost */
+#define LL_FMPI2C_ISR_OVR FMPI2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */
+#define LL_FMPI2C_ISR_PECERR FMPI2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */
+#define LL_FMPI2C_ISR_TIMEOUT FMPI2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */
+#define LL_FMPI2C_ISR_ALERT FMPI2C_ISR_ALERT /*!< SMBus alert (SMBus mode) */
+#define LL_FMPI2C_ISR_BUSY FMPI2C_ISR_BUSY /*!< Bus busy */
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_FMPI2C_ReadReg and LL_FMPI2C_WriteReg functions
+ * @{
+ */
+#define LL_FMPI2C_CR1_TXIE FMPI2C_CR1_TXIE /*!< TX Interrupt enable */
+#define LL_FMPI2C_CR1_RXIE FMPI2C_CR1_RXIE /*!< RX Interrupt enable */
+#define LL_FMPI2C_CR1_ADDRIE FMPI2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */
+#define LL_FMPI2C_CR1_NACKIE FMPI2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */
+#define LL_FMPI2C_CR1_STOPIE FMPI2C_CR1_STOPIE /*!< STOP detection Interrupt enable */
+#define LL_FMPI2C_CR1_TCIE FMPI2C_CR1_TCIE /*!< Transfer Complete interrupt enable */
+#define LL_FMPI2C_CR1_ERRIE FMPI2C_CR1_ERRIE /*!< Error interrupts enable */
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
+ * @{
+ */
+#define LL_FMPI2C_MODE_I2C 0x00000000U /*!< FMPI2C Master or Slave mode */
+#define LL_FMPI2C_MODE_SMBUS_HOST FMPI2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */
+#define LL_FMPI2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode (Default address not acknowledge) */
+#define LL_FMPI2C_MODE_SMBUS_DEVICE_ARP FMPI2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
+ * @{
+ */
+#define LL_FMPI2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */
+#define LL_FMPI2C_ANALOGFILTER_DISABLE FMPI2C_CR1_ANFOFF /*!< Analog filter is disabled. */
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
+ * @{
+ */
+#define LL_FMPI2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */
+#define LL_FMPI2C_ADDRESSING_MODE_10BIT FMPI2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_OWNADDRESS1 Own Address 1 Length
+ * @{
+ */
+#define LL_FMPI2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */
+#define LL_FMPI2C_OWNADDRESS1_10BIT FMPI2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
+ * @{
+ */
+#define LL_FMPI2C_OWNADDRESS2_NOMASK FMPI2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */
+#define LL_FMPI2C_OWNADDRESS2_MASK01 FMPI2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */
+#define LL_FMPI2C_OWNADDRESS2_MASK02 FMPI2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */
+#define LL_FMPI2C_OWNADDRESS2_MASK03 FMPI2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */
+#define LL_FMPI2C_OWNADDRESS2_MASK04 FMPI2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */
+#define LL_FMPI2C_OWNADDRESS2_MASK05 FMPI2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */
+#define LL_FMPI2C_OWNADDRESS2_MASK06 FMPI2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */
+#define LL_FMPI2C_OWNADDRESS2_MASK07 FMPI2C_OAR2_OA2MASK07 /*!< No comparison is done. All Address2 are acknowledged.*/
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
+ * @{
+ */
+#define LL_FMPI2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */
+#define LL_FMPI2C_NACK FMPI2C_CR2_NACK /*!< NACK is sent after current received byte.*/
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_ADDRSLAVE Slave Address Length
+ * @{
+ */
+#define LL_FMPI2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */
+#define LL_FMPI2C_ADDRSLAVE_10BIT FMPI2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_REQUEST Transfer Request Direction
+ * @{
+ */
+#define LL_FMPI2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */
+#define LL_FMPI2C_REQUEST_READ FMPI2C_CR2_RD_WRN /*!< Master request a read transfer. */
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_MODE Transfer End Mode
+ * @{
+ */
+#define LL_FMPI2C_MODE_RELOAD FMPI2C_CR2_RELOAD /*!< Enable FMPI2C Reload mode. */
+#define LL_FMPI2C_MODE_AUTOEND FMPI2C_CR2_AUTOEND /*!< Enable FMPI2C Automatic end mode with no HW PEC comparison. */
+#define LL_FMPI2C_MODE_SOFTEND 0x00000000U /*!< Enable FMPI2C Software end mode with no HW PEC comparison. */
+#define LL_FMPI2C_MODE_SMBUS_RELOAD LL_FMPI2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
+#define LL_FMPI2C_MODE_SMBUS_AUTOEND_NO_PEC LL_FMPI2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
+#define LL_FMPI2C_MODE_SMBUS_SOFTEND_NO_PEC LL_FMPI2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode with HW PEC comparison. */
+#define LL_FMPI2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_FMPI2C_MODE_AUTOEND | FMPI2C_CR2_PECBYTE) /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
+#define LL_FMPI2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_FMPI2C_MODE_SOFTEND | FMPI2C_CR2_PECBYTE) /*!< Enable SMBUS Software end mode with HW PEC comparison. */
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_GENERATE Start And Stop Generation
+ * @{
+ */
+#define LL_FMPI2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */
+#define LL_FMPI2C_GENERATE_STOP (uint32_t)(0x80000000U | FMPI2C_CR2_STOP) /*!< Generate Stop condition (Size should be set to 0). */
+#define LL_FMPI2C_GENERATE_START_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN) /*!< Generate Start for read request. */
+#define LL_FMPI2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) /*!< Generate Start for write request. */
+#define LL_FMPI2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */
+#define LL_FMPI2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) /*!< Generate Restart for write request, slave 7Bit address. */
+#define LL_FMPI2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN | FMPI2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */
+#define LL_FMPI2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) /*!< Generate Restart for write request, slave 10Bit address.*/
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_DIRECTION Read Write Direction
+ * @{
+ */
+#define LL_FMPI2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, slave enters receiver mode. */
+#define LL_FMPI2C_DIRECTION_READ FMPI2C_ISR_DIR /*!< Read transfer request by master, slave enters transmitter mode.*/
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_DMA_REG_DATA DMA Register Data
+ * @{
+ */
+#define LL_FMPI2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
+#define LL_FMPI2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
+ * @{
+ */
+#define LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect SCL low level timeout. */
+#define LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH FMPI2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
+ * @{
+ */
+#define LL_FMPI2C_SMBUS_TIMEOUTA FMPI2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */
+#define LL_FMPI2C_SMBUS_TIMEOUTB FMPI2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) enable bit */
+#define LL_FMPI2C_SMBUS_ALL_TIMEOUT (uint32_t)(FMPI2C_TIMEOUTR_TIMOUTEN | FMPI2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB (extended clock) enable bits */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FMPI2C_LL_Exported_Macros FMPI2C Exported Macros
+ * @{
+ */
+
+/** @defgroup FMPI2C_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in FMPI2C register
+ * @param __INSTANCE__ FMPI2C Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_FMPI2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in FMPI2C register
+ * @param __INSTANCE__ FMPI2C Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_FMPI2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
+ * @{
+ */
+/**
+ * @brief Configure the SDA setup, hold time and the SCL high, low period.
+ * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
+ * @param __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc)
+ * @param __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc)
+ * @param __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc)
+ * @param __CLOCK_LOW_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc)
+ * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+ */
+#define __LL_FMPI2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \
+ ((((uint32_t)(__PRESCALER__) << FMPI2C_TIMINGR_PRESC_Pos) & FMPI2C_TIMINGR_PRESC) | \
+ (((uint32_t)(__DATA_SETUP_TIME__) << FMPI2C_TIMINGR_SCLDEL_Pos) & FMPI2C_TIMINGR_SCLDEL) | \
+ (((uint32_t)(__DATA_HOLD_TIME__) << FMPI2C_TIMINGR_SDADEL_Pos) & FMPI2C_TIMINGR_SDADEL) | \
+ (((uint32_t)(__CLOCK_HIGH_PERIOD__) << FMPI2C_TIMINGR_SCLH_Pos) & FMPI2C_TIMINGR_SCLH) | \
+ (((uint32_t)(__CLOCK_LOW_PERIOD__) << FMPI2C_TIMINGR_SCLL_Pos) & FMPI2C_TIMINGR_SCLL))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FMPI2C_LL_Exported_Functions FMPI2C Exported Functions
+ * @{
+ */
+
+/** @defgroup FMPI2C_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Enable FMPI2C peripheral (PE = 1).
+ * @rmtoll CR1 PE LL_FMPI2C_Enable
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_Enable(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PE);
+}
+
+/**
+ * @brief Disable FMPI2C peripheral (PE = 0).
+ * @note When PE = 0, the FMPI2C SCL and SDA lines are released.
+ * Internal state machines and status bits are put back to their reset value.
+ * When cleared, PE must be kept low for at least 3 APB clock cycles.
+ * @rmtoll CR1 PE LL_FMPI2C_Disable
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_Disable(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PE);
+}
+
+/**
+ * @brief Check if the FMPI2C peripheral is enabled or disabled.
+ * @rmtoll CR1 PE LL_FMPI2C_IsEnabled
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabled(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PE) == (FMPI2C_CR1_PE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure Noise Filters (Analog and Digital).
+ * @note If the analog filter is also enabled, the digital filter is added to analog filter.
+ * The filters can only be programmed when the FMPI2C is disabled (PE = 0).
+ * @rmtoll CR1 ANFOFF LL_FMPI2C_ConfigFilters\n
+ * CR1 DNF LL_FMPI2C_ConfigFilters
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param AnalogFilter This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_ANALOGFILTER_ENABLE
+ * @arg @ref LL_FMPI2C_ANALOGFILTER_DISABLE
+ * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*tfmpi2cclk).
+ * This parameter is used to configure the digital noise filter on SDA and SCL input.
+ * The digital filter will filter spikes with a length of up to DNF[3:0]*tfmpi2cclk.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ConfigFilters(FMPI2C_TypeDef *FMPI2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
+{
+ MODIFY_REG(FMPI2Cx->CR1, FMPI2C_CR1_ANFOFF | FMPI2C_CR1_DNF, AnalogFilter | (DigitalFilter << FMPI2C_CR1_DNF_Pos));
+}
+
+/**
+ * @brief Configure Digital Noise Filter.
+ * @note If the analog filter is also enabled, the digital filter is added to analog filter.
+ * This filter can only be programmed when the FMPI2C is disabled (PE = 0).
+ * @rmtoll CR1 DNF LL_FMPI2C_SetDigitalFilter
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*tfmpi2cclk).
+ * This parameter is used to configure the digital noise filter on SDA and SCL input.
+ * The digital filter will filter spikes with a length of up to DNF[3:0]*tfmpi2cclk.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetDigitalFilter(FMPI2C_TypeDef *FMPI2Cx, uint32_t DigitalFilter)
+{
+ MODIFY_REG(FMPI2Cx->CR1, FMPI2C_CR1_DNF, DigitalFilter << FMPI2C_CR1_DNF_Pos);
+}
+
+/**
+ * @brief Get the current Digital Noise Filter configuration.
+ * @rmtoll CR1 DNF LL_FMPI2C_GetDigitalFilter
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0xF
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetDigitalFilter(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_DNF) >> FMPI2C_CR1_DNF_Pos);
+}
+
+/**
+ * @brief Enable Analog Noise Filter.
+ * @note This filter can only be programmed when the FMPI2C is disabled (PE = 0).
+ * @rmtoll CR1 ANFOFF LL_FMPI2C_EnableAnalogFilter
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableAnalogFilter(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ANFOFF);
+}
+
+/**
+ * @brief Disable Analog Noise Filter.
+ * @note This filter can only be programmed when the FMPI2C is disabled (PE = 0).
+ * @rmtoll CR1 ANFOFF LL_FMPI2C_DisableAnalogFilter
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableAnalogFilter(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ANFOFF);
+}
+
+/**
+ * @brief Check if Analog Noise Filter is enabled or disabled.
+ * @rmtoll CR1 ANFOFF LL_FMPI2C_IsEnabledAnalogFilter
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledAnalogFilter(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ANFOFF) != (FMPI2C_CR1_ANFOFF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable DMA transmission requests.
+ * @rmtoll CR1 TXDMAEN LL_FMPI2C_EnableDMAReq_TX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableDMAReq_TX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXDMAEN);
+}
+
+/**
+ * @brief Disable DMA transmission requests.
+ * @rmtoll CR1 TXDMAEN LL_FMPI2C_DisableDMAReq_TX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableDMAReq_TX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXDMAEN);
+}
+
+/**
+ * @brief Check if DMA transmission requests are enabled or disabled.
+ * @rmtoll CR1 TXDMAEN LL_FMPI2C_IsEnabledDMAReq_TX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledDMAReq_TX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXDMAEN) == (FMPI2C_CR1_TXDMAEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable DMA reception requests.
+ * @rmtoll CR1 RXDMAEN LL_FMPI2C_EnableDMAReq_RX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableDMAReq_RX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXDMAEN);
+}
+
+/**
+ * @brief Disable DMA reception requests.
+ * @rmtoll CR1 RXDMAEN LL_FMPI2C_DisableDMAReq_RX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableDMAReq_RX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXDMAEN);
+}
+
+/**
+ * @brief Check if DMA reception requests are enabled or disabled.
+ * @rmtoll CR1 RXDMAEN LL_FMPI2C_IsEnabledDMAReq_RX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledDMAReq_RX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXDMAEN) == (FMPI2C_CR1_RXDMAEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get the data register address used for DMA transfer
+ * @rmtoll TXDR TXDATA LL_FMPI2C_DMA_GetRegAddr\n
+ * RXDR RXDATA LL_FMPI2C_DMA_GetRegAddr
+ * @param FMPI2Cx FMPI2C Instance
+ * @param Direction This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_DMA_REG_DATA_TRANSMIT
+ * @arg @ref LL_FMPI2C_DMA_REG_DATA_RECEIVE
+ * @retval Address of data register
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_DMA_GetRegAddr(FMPI2C_TypeDef *FMPI2Cx, uint32_t Direction)
+{
+ uint32_t data_reg_addr;
+
+ if (Direction == LL_FMPI2C_DMA_REG_DATA_TRANSMIT)
+ {
+ /* return address of TXDR register */
+ data_reg_addr = (uint32_t) &(FMPI2Cx->TXDR);
+ }
+ else
+ {
+ /* return address of RXDR register */
+ data_reg_addr = (uint32_t) &(FMPI2Cx->RXDR);
+ }
+
+ return data_reg_addr;
+}
+
+/**
+ * @brief Enable Clock stretching.
+ * @note This bit can only be programmed when the FMPI2C is disabled (PE = 0).
+ * @rmtoll CR1 NOSTRETCH LL_FMPI2C_EnableClockStretching
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableClockStretching(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NOSTRETCH);
+}
+
+/**
+ * @brief Disable Clock stretching.
+ * @note This bit can only be programmed when the FMPI2C is disabled (PE = 0).
+ * @rmtoll CR1 NOSTRETCH LL_FMPI2C_DisableClockStretching
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableClockStretching(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NOSTRETCH);
+}
+
+/**
+ * @brief Check if Clock stretching is enabled or disabled.
+ * @rmtoll CR1 NOSTRETCH LL_FMPI2C_IsEnabledClockStretching
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledClockStretching(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NOSTRETCH) != (FMPI2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable hardware byte control in slave mode.
+ * @rmtoll CR1 SBC LL_FMPI2C_EnableSlaveByteControl
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableSlaveByteControl(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_SBC);
+}
+
+/**
+ * @brief Disable hardware byte control in slave mode.
+ * @rmtoll CR1 SBC LL_FMPI2C_DisableSlaveByteControl
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableSlaveByteControl(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_SBC);
+}
+
+/**
+ * @brief Check if hardware byte control in slave mode is enabled or disabled.
+ * @rmtoll CR1 SBC LL_FMPI2C_IsEnabledSlaveByteControl
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSlaveByteControl(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_SBC) == (FMPI2C_CR1_SBC)) ? 1UL : 0UL);
+}
+
+
+/**
+ * @brief Enable General Call.
+ * @note When enabled the Address 0x00 is ACKed.
+ * @rmtoll CR1 GCEN LL_FMPI2C_EnableGeneralCall
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableGeneralCall(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_GCEN);
+}
+
+/**
+ * @brief Disable General Call.
+ * @note When disabled the Address 0x00 is NACKed.
+ * @rmtoll CR1 GCEN LL_FMPI2C_DisableGeneralCall
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableGeneralCall(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_GCEN);
+}
+
+/**
+ * @brief Check if General Call is enabled or disabled.
+ * @rmtoll CR1 GCEN LL_FMPI2C_IsEnabledGeneralCall
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledGeneralCall(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_GCEN) == (FMPI2C_CR1_GCEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode.
+ * @note Changing this bit is not allowed, when the START bit is set.
+ * @rmtoll CR2 ADD10 LL_FMPI2C_SetMasterAddressingMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param AddressingMode This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_ADDRESSING_MODE_7BIT
+ * @arg @ref LL_FMPI2C_ADDRESSING_MODE_10BIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetMasterAddressingMode(FMPI2C_TypeDef *FMPI2Cx, uint32_t AddressingMode)
+{
+ MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_ADD10, AddressingMode);
+}
+
+/**
+ * @brief Get the Master addressing mode.
+ * @rmtoll CR2 ADD10 LL_FMPI2C_GetMasterAddressingMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_FMPI2C_ADDRESSING_MODE_7BIT
+ * @arg @ref LL_FMPI2C_ADDRESSING_MODE_10BIT
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetMasterAddressingMode(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_ADD10));
+}
+
+/**
+ * @brief Set the Own Address1.
+ * @rmtoll OAR1 OA1 LL_FMPI2C_SetOwnAddress1\n
+ * OAR1 OA1MODE LL_FMPI2C_SetOwnAddress1
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
+ * @param OwnAddrSize This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_OWNADDRESS1_7BIT
+ * @arg @ref LL_FMPI2C_OWNADDRESS1_10BIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetOwnAddress1(FMPI2C_TypeDef *FMPI2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
+{
+ MODIFY_REG(FMPI2Cx->OAR1, FMPI2C_OAR1_OA1 | FMPI2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
+}
+
+/**
+ * @brief Enable acknowledge on Own Address1 match address.
+ * @rmtoll OAR1 OA1EN LL_FMPI2C_EnableOwnAddress1
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableOwnAddress1(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->OAR1, FMPI2C_OAR1_OA1EN);
+}
+
+/**
+ * @brief Disable acknowledge on Own Address1 match address.
+ * @rmtoll OAR1 OA1EN LL_FMPI2C_DisableOwnAddress1
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableOwnAddress1(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->OAR1, FMPI2C_OAR1_OA1EN);
+}
+
+/**
+ * @brief Check if Own Address1 acknowledge is enabled or disabled.
+ * @rmtoll OAR1 OA1EN LL_FMPI2C_IsEnabledOwnAddress1
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledOwnAddress1(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->OAR1, FMPI2C_OAR1_OA1EN) == (FMPI2C_OAR1_OA1EN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set the 7bits Own Address2.
+ * @note This action has no effect if own address2 is enabled.
+ * @rmtoll OAR2 OA2 LL_FMPI2C_SetOwnAddress2\n
+ * OAR2 OA2MSK LL_FMPI2C_SetOwnAddress2
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
+ * @param OwnAddrMask This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_OWNADDRESS2_NOMASK
+ * @arg @ref LL_FMPI2C_OWNADDRESS2_MASK01
+ * @arg @ref LL_FMPI2C_OWNADDRESS2_MASK02
+ * @arg @ref LL_FMPI2C_OWNADDRESS2_MASK03
+ * @arg @ref LL_FMPI2C_OWNADDRESS2_MASK04
+ * @arg @ref LL_FMPI2C_OWNADDRESS2_MASK05
+ * @arg @ref LL_FMPI2C_OWNADDRESS2_MASK06
+ * @arg @ref LL_FMPI2C_OWNADDRESS2_MASK07
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetOwnAddress2(FMPI2C_TypeDef *FMPI2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
+{
+ MODIFY_REG(FMPI2Cx->OAR2, FMPI2C_OAR2_OA2 | FMPI2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
+}
+
+/**
+ * @brief Enable acknowledge on Own Address2 match address.
+ * @rmtoll OAR2 OA2EN LL_FMPI2C_EnableOwnAddress2
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableOwnAddress2(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->OAR2, FMPI2C_OAR2_OA2EN);
+}
+
+/**
+ * @brief Disable acknowledge on Own Address2 match address.
+ * @rmtoll OAR2 OA2EN LL_FMPI2C_DisableOwnAddress2
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableOwnAddress2(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->OAR2, FMPI2C_OAR2_OA2EN);
+}
+
+/**
+ * @brief Check if Own Address1 acknowledge is enabled or disabled.
+ * @rmtoll OAR2 OA2EN LL_FMPI2C_IsEnabledOwnAddress2
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledOwnAddress2(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->OAR2, FMPI2C_OAR2_OA2EN) == (FMPI2C_OAR2_OA2EN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure the SDA setup, hold time and the SCL high, low period.
+ * @note This bit can only be programmed when the FMPI2C is disabled (PE = 0).
+ * @rmtoll TIMINGR TIMINGR LL_FMPI2C_SetTiming
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
+ * @note This parameter is computed with the STM32CubeMX Tool.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetTiming(FMPI2C_TypeDef *FMPI2Cx, uint32_t Timing)
+{
+ WRITE_REG(FMPI2Cx->TIMINGR, Timing);
+}
+
+/**
+ * @brief Get the Timing Prescaler setting.
+ * @rmtoll TIMINGR PRESC LL_FMPI2C_GetTimingPrescaler
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0xF
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetTimingPrescaler(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_PRESC) >> FMPI2C_TIMINGR_PRESC_Pos);
+}
+
+/**
+ * @brief Get the SCL low period setting.
+ * @rmtoll TIMINGR SCLL LL_FMPI2C_GetClockLowPeriod
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetClockLowPeriod(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_SCLL) >> FMPI2C_TIMINGR_SCLL_Pos);
+}
+
+/**
+ * @brief Get the SCL high period setting.
+ * @rmtoll TIMINGR SCLH LL_FMPI2C_GetClockHighPeriod
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetClockHighPeriod(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_SCLH) >> FMPI2C_TIMINGR_SCLH_Pos);
+}
+
+/**
+ * @brief Get the SDA hold time.
+ * @rmtoll TIMINGR SDADEL LL_FMPI2C_GetDataHoldTime
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0xF
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetDataHoldTime(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_SDADEL) >> FMPI2C_TIMINGR_SDADEL_Pos);
+}
+
+/**
+ * @brief Get the SDA setup time.
+ * @rmtoll TIMINGR SCLDEL LL_FMPI2C_GetDataSetupTime
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0xF
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetDataSetupTime(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_SCLDEL) >> FMPI2C_TIMINGR_SCLDEL_Pos);
+}
+
+/**
+ * @brief Configure peripheral mode.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll CR1 SMBHEN LL_FMPI2C_SetMode\n
+ * CR1 SMBDEN LL_FMPI2C_SetMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param PeripheralMode This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_MODE_I2C
+ * @arg @ref LL_FMPI2C_MODE_SMBUS_HOST
+ * @arg @ref LL_FMPI2C_MODE_SMBUS_DEVICE
+ * @arg @ref LL_FMPI2C_MODE_SMBUS_DEVICE_ARP
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetMode(FMPI2C_TypeDef *FMPI2Cx, uint32_t PeripheralMode)
+{
+ MODIFY_REG(FMPI2Cx->CR1, FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN, PeripheralMode);
+}
+
+/**
+ * @brief Get peripheral mode.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll CR1 SMBHEN LL_FMPI2C_GetMode\n
+ * CR1 SMBDEN LL_FMPI2C_GetMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_FMPI2C_MODE_I2C
+ * @arg @ref LL_FMPI2C_MODE_SMBUS_HOST
+ * @arg @ref LL_FMPI2C_MODE_SMBUS_DEVICE
+ * @arg @ref LL_FMPI2C_MODE_SMBUS_DEVICE_ARP
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetMode(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN));
+}
+
+/**
+ * @brief Enable SMBus alert (Host or Device mode)
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note SMBus Device mode:
+ * - SMBus Alert pin is drived low and
+ * Alert Response Address Header acknowledge is enabled.
+ * SMBus Host mode:
+ * - SMBus Alert pin management is supported.
+ * @rmtoll CR1 ALERTEN LL_FMPI2C_EnableSMBusAlert
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableSMBusAlert(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ALERTEN);
+}
+
+/**
+ * @brief Disable SMBus alert (Host or Device mode)
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note SMBus Device mode:
+ * - SMBus Alert pin is not drived (can be used as a standard GPIO) and
+ * Alert Response Address Header acknowledge is disabled.
+ * SMBus Host mode:
+ * - SMBus Alert pin management is not supported.
+ * @rmtoll CR1 ALERTEN LL_FMPI2C_DisableSMBusAlert
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableSMBusAlert(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ALERTEN);
+}
+
+/**
+ * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll CR1 ALERTEN LL_FMPI2C_IsEnabledSMBusAlert
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusAlert(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ALERTEN) == (FMPI2C_CR1_ALERTEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable SMBus Packet Error Calculation (PEC).
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll CR1 PECEN LL_FMPI2C_EnableSMBusPEC
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableSMBusPEC(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PECEN);
+}
+
+/**
+ * @brief Disable SMBus Packet Error Calculation (PEC).
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll CR1 PECEN LL_FMPI2C_DisableSMBusPEC
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableSMBusPEC(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PECEN);
+}
+
+/**
+ * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll CR1 PECEN LL_FMPI2C_IsEnabledSMBusPEC
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusPEC(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PECEN) == (FMPI2C_CR1_PECEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure the SMBus Clock Timeout.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
+ * @rmtoll TIMEOUTR TIMEOUTA LL_FMPI2C_ConfigSMBusTimeout\n
+ * TIMEOUTR TIDLE LL_FMPI2C_ConfigSMBusTimeout\n
+ * TIMEOUTR TIMEOUTB LL_FMPI2C_ConfigSMBusTimeout
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
+ * @param TimeoutAMode This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
+ * @param TimeoutB
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ConfigSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
+ uint32_t TimeoutB)
+{
+ MODIFY_REG(FMPI2Cx->TIMEOUTR, FMPI2C_TIMEOUTR_TIMEOUTA | FMPI2C_TIMEOUTR_TIDLE | FMPI2C_TIMEOUTR_TIMEOUTB,
+ TimeoutA | TimeoutAMode | (TimeoutB << FMPI2C_TIMEOUTR_TIMEOUTB_Pos));
+}
+
+/**
+ * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note These bits can only be programmed when TimeoutA is disabled.
+ * @rmtoll TIMEOUTR TIMEOUTA LL_FMPI2C_SetSMBusTimeoutA
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutA(FMPI2C_TypeDef *FMPI2Cx, uint32_t TimeoutA)
+{
+ WRITE_REG(FMPI2Cx->TIMEOUTR, TimeoutA);
+}
+
+/**
+ * @brief Get the SMBus Clock TimeoutA setting.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll TIMEOUTR TIMEOUTA LL_FMPI2C_GetSMBusTimeoutA
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutA(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->TIMEOUTR, FMPI2C_TIMEOUTR_TIMEOUTA));
+}
+
+/**
+ * @brief Set the SMBus Clock TimeoutA mode.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note This bit can only be programmed when TimeoutA is disabled.
+ * @rmtoll TIMEOUTR TIDLE LL_FMPI2C_SetSMBusTimeoutAMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param TimeoutAMode This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutAMode(FMPI2C_TypeDef *FMPI2Cx, uint32_t TimeoutAMode)
+{
+ WRITE_REG(FMPI2Cx->TIMEOUTR, TimeoutAMode);
+}
+
+/**
+ * @brief Get the SMBus Clock TimeoutA mode.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll TIMEOUTR TIDLE LL_FMPI2C_GetSMBusTimeoutAMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutAMode(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->TIMEOUTR, FMPI2C_TIMEOUTR_TIDLE));
+}
+
+/**
+ * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note These bits can only be programmed when TimeoutB is disabled.
+ * @rmtoll TIMEOUTR TIMEOUTB LL_FMPI2C_SetSMBusTimeoutB
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutB(FMPI2C_TypeDef *FMPI2Cx, uint32_t TimeoutB)
+{
+ WRITE_REG(FMPI2Cx->TIMEOUTR, TimeoutB << FMPI2C_TIMEOUTR_TIMEOUTB_Pos);
+}
+
+/**
+ * @brief Get the SMBus Extended Cumulative Clock TimeoutB setting.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll TIMEOUTR TIMEOUTB LL_FMPI2C_GetSMBusTimeoutB
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutB(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->TIMEOUTR, FMPI2C_TIMEOUTR_TIMEOUTB) >> FMPI2C_TIMEOUTR_TIMEOUTB_Pos);
+}
+
+/**
+ * @brief Enable the SMBus Clock Timeout.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll TIMEOUTR TIMOUTEN LL_FMPI2C_EnableSMBusTimeout\n
+ * TIMEOUTR TEXTEN LL_FMPI2C_EnableSMBusTimeout
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param ClockTimeout This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTB
+ * @arg @ref LL_FMPI2C_SMBUS_ALL_TIMEOUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint32_t ClockTimeout)
+{
+ SET_BIT(FMPI2Cx->TIMEOUTR, ClockTimeout);
+}
+
+/**
+ * @brief Disable the SMBus Clock Timeout.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll TIMEOUTR TIMOUTEN LL_FMPI2C_DisableSMBusTimeout\n
+ * TIMEOUTR TEXTEN LL_FMPI2C_DisableSMBusTimeout
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param ClockTimeout This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTB
+ * @arg @ref LL_FMPI2C_SMBUS_ALL_TIMEOUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint32_t ClockTimeout)
+{
+ CLEAR_BIT(FMPI2Cx->TIMEOUTR, ClockTimeout);
+}
+
+/**
+ * @brief Check if the SMBus Clock Timeout is enabled or disabled.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll TIMEOUTR TIMOUTEN LL_FMPI2C_IsEnabledSMBusTimeout\n
+ * TIMEOUTR TEXTEN LL_FMPI2C_IsEnabledSMBusTimeout
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param ClockTimeout This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTB
+ * @arg @ref LL_FMPI2C_SMBUS_ALL_TIMEOUT
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint32_t ClockTimeout)
+{
+ return ((READ_BIT(FMPI2Cx->TIMEOUTR, (FMPI2C_TIMEOUTR_TIMOUTEN | FMPI2C_TIMEOUTR_TEXTEN)) == (ClockTimeout)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable TXIS interrupt.
+ * @rmtoll CR1 TXIE LL_FMPI2C_EnableIT_TX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableIT_TX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXIE);
+}
+
+/**
+ * @brief Disable TXIS interrupt.
+ * @rmtoll CR1 TXIE LL_FMPI2C_DisableIT_TX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableIT_TX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXIE);
+}
+
+/**
+ * @brief Check if the TXIS Interrupt is enabled or disabled.
+ * @rmtoll CR1 TXIE LL_FMPI2C_IsEnabledIT_TX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_TX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXIE) == (FMPI2C_CR1_TXIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable RXNE interrupt.
+ * @rmtoll CR1 RXIE LL_FMPI2C_EnableIT_RX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableIT_RX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXIE);
+}
+
+/**
+ * @brief Disable RXNE interrupt.
+ * @rmtoll CR1 RXIE LL_FMPI2C_DisableIT_RX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableIT_RX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXIE);
+}
+
+/**
+ * @brief Check if the RXNE Interrupt is enabled or disabled.
+ * @rmtoll CR1 RXIE LL_FMPI2C_IsEnabledIT_RX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_RX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXIE) == (FMPI2C_CR1_RXIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable Address match interrupt (slave mode only).
+ * @rmtoll CR1 ADDRIE LL_FMPI2C_EnableIT_ADDR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableIT_ADDR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ADDRIE);
+}
+
+/**
+ * @brief Disable Address match interrupt (slave mode only).
+ * @rmtoll CR1 ADDRIE LL_FMPI2C_DisableIT_ADDR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableIT_ADDR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ADDRIE);
+}
+
+/**
+ * @brief Check if Address match interrupt is enabled or disabled.
+ * @rmtoll CR1 ADDRIE LL_FMPI2C_IsEnabledIT_ADDR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_ADDR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ADDRIE) == (FMPI2C_CR1_ADDRIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable Not acknowledge received interrupt.
+ * @rmtoll CR1 NACKIE LL_FMPI2C_EnableIT_NACK
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableIT_NACK(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NACKIE);
+}
+
+/**
+ * @brief Disable Not acknowledge received interrupt.
+ * @rmtoll CR1 NACKIE LL_FMPI2C_DisableIT_NACK
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableIT_NACK(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NACKIE);
+}
+
+/**
+ * @brief Check if Not acknowledge received interrupt is enabled or disabled.
+ * @rmtoll CR1 NACKIE LL_FMPI2C_IsEnabledIT_NACK
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_NACK(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NACKIE) == (FMPI2C_CR1_NACKIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable STOP detection interrupt.
+ * @rmtoll CR1 STOPIE LL_FMPI2C_EnableIT_STOP
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableIT_STOP(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_STOPIE);
+}
+
+/**
+ * @brief Disable STOP detection interrupt.
+ * @rmtoll CR1 STOPIE LL_FMPI2C_DisableIT_STOP
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableIT_STOP(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_STOPIE);
+}
+
+/**
+ * @brief Check if STOP detection interrupt is enabled or disabled.
+ * @rmtoll CR1 STOPIE LL_FMPI2C_IsEnabledIT_STOP
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_STOP(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_STOPIE) == (FMPI2C_CR1_STOPIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable Transfer Complete interrupt.
+ * @note Any of these events will generate interrupt :
+ * Transfer Complete (TC)
+ * Transfer Complete Reload (TCR)
+ * @rmtoll CR1 TCIE LL_FMPI2C_EnableIT_TC
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableIT_TC(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TCIE);
+}
+
+/**
+ * @brief Disable Transfer Complete interrupt.
+ * @note Any of these events will generate interrupt :
+ * Transfer Complete (TC)
+ * Transfer Complete Reload (TCR)
+ * @rmtoll CR1 TCIE LL_FMPI2C_DisableIT_TC
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableIT_TC(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TCIE);
+}
+
+/**
+ * @brief Check if Transfer Complete interrupt is enabled or disabled.
+ * @rmtoll CR1 TCIE LL_FMPI2C_IsEnabledIT_TC
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_TC(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TCIE) == (FMPI2C_CR1_TCIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable Error interrupts.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note Any of these errors will generate interrupt :
+ * Arbitration Loss (ARLO)
+ * Bus Error detection (BERR)
+ * Overrun/Underrun (OVR)
+ * SMBus Timeout detection (TIMEOUT)
+ * SMBus PEC error detection (PECERR)
+ * SMBus Alert pin event detection (ALERT)
+ * @rmtoll CR1 ERRIE LL_FMPI2C_EnableIT_ERR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableIT_ERR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ERRIE);
+}
+
+/**
+ * @brief Disable Error interrupts.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note Any of these errors will generate interrupt :
+ * Arbitration Loss (ARLO)
+ * Bus Error detection (BERR)
+ * Overrun/Underrun (OVR)
+ * SMBus Timeout detection (TIMEOUT)
+ * SMBus PEC error detection (PECERR)
+ * SMBus Alert pin event detection (ALERT)
+ * @rmtoll CR1 ERRIE LL_FMPI2C_DisableIT_ERR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableIT_ERR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ERRIE);
+}
+
+/**
+ * @brief Check if Error interrupts are enabled or disabled.
+ * @rmtoll CR1 ERRIE LL_FMPI2C_IsEnabledIT_ERR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_ERR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ERRIE) == (FMPI2C_CR1_ERRIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EF_FLAG_management FLAG_management
+ * @{
+ */
+
+/**
+ * @brief Indicate the status of Transmit data register empty flag.
+ * @note RESET: When next data is written in Transmit data register.
+ * SET: When Transmit data register is empty.
+ * @rmtoll ISR TXE LL_FMPI2C_IsActiveFlag_TXE
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TXE(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TXE) == (FMPI2C_ISR_TXE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Transmit interrupt flag.
+ * @note RESET: When next data is written in Transmit data register.
+ * SET: When Transmit data register is empty.
+ * @rmtoll ISR TXIS LL_FMPI2C_IsActiveFlag_TXIS
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TXIS(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TXIS) == (FMPI2C_ISR_TXIS)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Receive data register not empty flag.
+ * @note RESET: When Receive data register is read.
+ * SET: When the received data is copied in Receive data register.
+ * @rmtoll ISR RXNE LL_FMPI2C_IsActiveFlag_RXNE
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_RXNE(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_RXNE) == (FMPI2C_ISR_RXNE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Address matched flag (slave mode).
+ * @note RESET: Clear default value.
+ * SET: When the received slave address matched with one of the enabled slave address.
+ * @rmtoll ISR ADDR LL_FMPI2C_IsActiveFlag_ADDR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_ADDR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_ADDR) == (FMPI2C_ISR_ADDR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Not Acknowledge received flag.
+ * @note RESET: Clear default value.
+ * SET: When a NACK is received after a byte transmission.
+ * @rmtoll ISR NACKF LL_FMPI2C_IsActiveFlag_NACK
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_NACK(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_NACKF) == (FMPI2C_ISR_NACKF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Stop detection flag.
+ * @note RESET: Clear default value.
+ * SET: When a Stop condition is detected.
+ * @rmtoll ISR STOPF LL_FMPI2C_IsActiveFlag_STOP
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_STOP(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_STOPF) == (FMPI2C_ISR_STOPF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Transfer complete flag (master mode).
+ * @note RESET: Clear default value.
+ * SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
+ * @rmtoll ISR TC LL_FMPI2C_IsActiveFlag_TC
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TC(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TC) == (FMPI2C_ISR_TC)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Transfer complete flag (master mode).
+ * @note RESET: Clear default value.
+ * SET: When RELOAD=1 and NBYTES date have been transferred.
+ * @rmtoll ISR TCR LL_FMPI2C_IsActiveFlag_TCR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TCR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TCR) == (FMPI2C_ISR_TCR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Bus error flag.
+ * @note RESET: Clear default value.
+ * SET: When a misplaced Start or Stop condition is detected.
+ * @rmtoll ISR BERR LL_FMPI2C_IsActiveFlag_BERR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_BERR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_BERR) == (FMPI2C_ISR_BERR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Arbitration lost flag.
+ * @note RESET: Clear default value.
+ * SET: When arbitration lost.
+ * @rmtoll ISR ARLO LL_FMPI2C_IsActiveFlag_ARLO
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_ARLO(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_ARLO) == (FMPI2C_ISR_ARLO)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Overrun/Underrun flag (slave mode).
+ * @note RESET: Clear default value.
+ * SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
+ * @rmtoll ISR OVR LL_FMPI2C_IsActiveFlag_OVR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_OVR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_OVR) == (FMPI2C_ISR_OVR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of SMBus PEC error flag in reception.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note RESET: Clear default value.
+ * SET: When the received PEC does not match with the PEC register content.
+ * @rmtoll ISR PECERR LL_FMPI2C_IsActiveSMBusFlag_PECERR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_PECERR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_PECERR) == (FMPI2C_ISR_PECERR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of SMBus Timeout detection flag.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note RESET: Clear default value.
+ * SET: When a timeout or extended clock timeout occurs.
+ * @rmtoll ISR TIMEOUT LL_FMPI2C_IsActiveSMBusFlag_TIMEOUT
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_TIMEOUT(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TIMEOUT) == (FMPI2C_ISR_TIMEOUT)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of SMBus alert flag.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note RESET: Clear default value.
+ * SET: When SMBus host configuration, SMBus alert enabled and
+ * a falling edge event occurs on SMBA pin.
+ * @rmtoll ISR ALERT LL_FMPI2C_IsActiveSMBusFlag_ALERT
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_ALERT(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_ALERT) == (FMPI2C_ISR_ALERT)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Bus Busy flag.
+ * @note RESET: Clear default value.
+ * SET: When a Start condition is detected.
+ * @rmtoll ISR BUSY LL_FMPI2C_IsActiveFlag_BUSY
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_BUSY(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_BUSY) == (FMPI2C_ISR_BUSY)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear Address Matched flag.
+ * @rmtoll ICR ADDRCF LL_FMPI2C_ClearFlag_ADDR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ClearFlag_ADDR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_ADDRCF);
+}
+
+/**
+ * @brief Clear Not Acknowledge flag.
+ * @rmtoll ICR NACKCF LL_FMPI2C_ClearFlag_NACK
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ClearFlag_NACK(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_NACKCF);
+}
+
+/**
+ * @brief Clear Stop detection flag.
+ * @rmtoll ICR STOPCF LL_FMPI2C_ClearFlag_STOP
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ClearFlag_STOP(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_STOPCF);
+}
+
+/**
+ * @brief Clear Transmit data register empty flag (TXE).
+ * @note This bit can be clear by software in order to flush the transmit data register (TXDR).
+ * @rmtoll ISR TXE LL_FMPI2C_ClearFlag_TXE
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ClearFlag_TXE(FMPI2C_TypeDef *FMPI2Cx)
+{
+ WRITE_REG(FMPI2Cx->ISR, FMPI2C_ISR_TXE);
+}
+
+/**
+ * @brief Clear Bus error flag.
+ * @rmtoll ICR BERRCF LL_FMPI2C_ClearFlag_BERR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ClearFlag_BERR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_BERRCF);
+}
+
+/**
+ * @brief Clear Arbitration lost flag.
+ * @rmtoll ICR ARLOCF LL_FMPI2C_ClearFlag_ARLO
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ClearFlag_ARLO(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_ARLOCF);
+}
+
+/**
+ * @brief Clear Overrun/Underrun flag.
+ * @rmtoll ICR OVRCF LL_FMPI2C_ClearFlag_OVR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ClearFlag_OVR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_OVRCF);
+}
+
+/**
+ * @brief Clear SMBus PEC error flag.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll ICR PECCF LL_FMPI2C_ClearSMBusFlag_PECERR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ClearSMBusFlag_PECERR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_PECCF);
+}
+
+/**
+ * @brief Clear SMBus Timeout detection flag.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll ICR TIMOUTCF LL_FMPI2C_ClearSMBusFlag_TIMEOUT
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ClearSMBusFlag_TIMEOUT(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_TIMOUTCF);
+}
+
+/**
+ * @brief Clear SMBus Alert flag.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll ICR ALERTCF LL_FMPI2C_ClearSMBusFlag_ALERT
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ClearSMBusFlag_ALERT(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_ALERTCF);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EF_Data_Management Data_Management
+ * @{
+ */
+
+/**
+ * @brief Enable automatic STOP condition generation (master mode).
+ * @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
+ * This bit has no effect in slave mode or when RELOAD bit is set.
+ * @rmtoll CR2 AUTOEND LL_FMPI2C_EnableAutoEndMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableAutoEndMode(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_AUTOEND);
+}
+
+/**
+ * @brief Disable automatic STOP condition generation (master mode).
+ * @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
+ * @rmtoll CR2 AUTOEND LL_FMPI2C_DisableAutoEndMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableAutoEndMode(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR2, FMPI2C_CR2_AUTOEND);
+}
+
+/**
+ * @brief Check if automatic STOP condition is enabled or disabled.
+ * @rmtoll CR2 AUTOEND LL_FMPI2C_IsEnabledAutoEndMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledAutoEndMode(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_AUTOEND) == (FMPI2C_CR2_AUTOEND)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable reload mode (master mode).
+ * @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
+ * @rmtoll CR2 RELOAD LL_FMPI2C_EnableReloadMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableReloadMode(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_RELOAD);
+}
+
+/**
+ * @brief Disable reload mode (master mode).
+ * @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
+ * @rmtoll CR2 RELOAD LL_FMPI2C_DisableReloadMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableReloadMode(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR2, FMPI2C_CR2_RELOAD);
+}
+
+/**
+ * @brief Check if reload mode is enabled or disabled.
+ * @rmtoll CR2 RELOAD LL_FMPI2C_IsEnabledReloadMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledReloadMode(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_RELOAD) == (FMPI2C_CR2_RELOAD)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure the number of bytes for transfer.
+ * @note Changing these bits when START bit is set is not allowed.
+ * @rmtoll CR2 NBYTES LL_FMPI2C_SetTransferSize
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetTransferSize(FMPI2C_TypeDef *FMPI2Cx, uint32_t TransferSize)
+{
+ MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_NBYTES, TransferSize << FMPI2C_CR2_NBYTES_Pos);
+}
+
+/**
+ * @brief Get the number of bytes configured for transfer.
+ * @rmtoll CR2 NBYTES LL_FMPI2C_GetTransferSize
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetTransferSize(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_NBYTES) >> FMPI2C_CR2_NBYTES_Pos);
+}
+
+/**
+ * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
+ * @note Usage in Slave mode only.
+ * @rmtoll CR2 NACK LL_FMPI2C_AcknowledgeNextData
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param TypeAcknowledge This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_ACK
+ * @arg @ref LL_FMPI2C_NACK
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_AcknowledgeNextData(FMPI2C_TypeDef *FMPI2Cx, uint32_t TypeAcknowledge)
+{
+ MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_NACK, TypeAcknowledge);
+}
+
+/**
+ * @brief Generate a START or RESTART condition
+ * @note The START bit can be set even if bus is BUSY or FMPI2C is in slave mode.
+ * This action has no effect when RELOAD is set.
+ * @rmtoll CR2 START LL_FMPI2C_GenerateStartCondition
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_GenerateStartCondition(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_START);
+}
+
+/**
+ * @brief Generate a STOP condition after the current byte transfer (master mode).
+ * @rmtoll CR2 STOP LL_FMPI2C_GenerateStopCondition
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_GenerateStopCondition(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_STOP);
+}
+
+/**
+ * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode).
+ * @note The master sends the complete 10bit slave address read sequence :
+ * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
+ * @rmtoll CR2 HEAD10R LL_FMPI2C_EnableAuto10BitRead
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableAuto10BitRead(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR2, FMPI2C_CR2_HEAD10R);
+}
+
+/**
+ * @brief Disable automatic RESTART Read request condition for 10bit address header (master mode).
+ * @note The master only sends the first 7 bits of 10bit address in Read direction.
+ * @rmtoll CR2 HEAD10R LL_FMPI2C_DisableAuto10BitRead
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableAuto10BitRead(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_HEAD10R);
+}
+
+/**
+ * @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
+ * @rmtoll CR2 HEAD10R LL_FMPI2C_IsEnabledAuto10BitRead
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledAuto10BitRead(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_HEAD10R) != (FMPI2C_CR2_HEAD10R)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure the transfer direction (master mode).
+ * @note Changing these bits when START bit is set is not allowed.
+ * @rmtoll CR2 RD_WRN LL_FMPI2C_SetTransferRequest
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param TransferRequest This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_REQUEST_WRITE
+ * @arg @ref LL_FMPI2C_REQUEST_READ
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetTransferRequest(FMPI2C_TypeDef *FMPI2Cx, uint32_t TransferRequest)
+{
+ MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_RD_WRN, TransferRequest);
+}
+
+/**
+ * @brief Get the transfer direction requested (master mode).
+ * @rmtoll CR2 RD_WRN LL_FMPI2C_GetTransferRequest
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_FMPI2C_REQUEST_WRITE
+ * @arg @ref LL_FMPI2C_REQUEST_READ
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetTransferRequest(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_RD_WRN));
+}
+
+/**
+ * @brief Configure the slave address for transfer (master mode).
+ * @note Changing these bits when START bit is set is not allowed.
+ * @rmtoll CR2 SADD LL_FMPI2C_SetSlaveAddr
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetSlaveAddr(FMPI2C_TypeDef *FMPI2Cx, uint32_t SlaveAddr)
+{
+ MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_SADD, SlaveAddr);
+}
+
+/**
+ * @brief Get the slave address programmed for transfer.
+ * @rmtoll CR2 SADD LL_FMPI2C_GetSlaveAddr
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0x3F
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetSlaveAddr(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_SADD));
+}
+
+/**
+ * @brief Handles FMPI2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
+ * @rmtoll CR2 SADD LL_FMPI2C_HandleTransfer\n
+ * CR2 ADD10 LL_FMPI2C_HandleTransfer\n
+ * CR2 RD_WRN LL_FMPI2C_HandleTransfer\n
+ * CR2 START LL_FMPI2C_HandleTransfer\n
+ * CR2 STOP LL_FMPI2C_HandleTransfer\n
+ * CR2 RELOAD LL_FMPI2C_HandleTransfer\n
+ * CR2 NBYTES LL_FMPI2C_HandleTransfer\n
+ * CR2 AUTOEND LL_FMPI2C_HandleTransfer\n
+ * CR2 HEAD10R LL_FMPI2C_HandleTransfer
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param SlaveAddr Specifies the slave address to be programmed.
+ * @param SlaveAddrSize This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_ADDRSLAVE_7BIT
+ * @arg @ref LL_FMPI2C_ADDRSLAVE_10BIT
+ * @param TransferSize Specifies the number of bytes to be programmed.
+ * This parameter must be a value between Min_Data=0 and Max_Data=255.
+ * @param EndMode This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_MODE_RELOAD
+ * @arg @ref LL_FMPI2C_MODE_AUTOEND
+ * @arg @ref LL_FMPI2C_MODE_SOFTEND
+ * @arg @ref LL_FMPI2C_MODE_SMBUS_RELOAD
+ * @arg @ref LL_FMPI2C_MODE_SMBUS_AUTOEND_NO_PEC
+ * @arg @ref LL_FMPI2C_MODE_SMBUS_SOFTEND_NO_PEC
+ * @arg @ref LL_FMPI2C_MODE_SMBUS_AUTOEND_WITH_PEC
+ * @arg @ref LL_FMPI2C_MODE_SMBUS_SOFTEND_WITH_PEC
+ * @param Request This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_GENERATE_NOSTARTSTOP
+ * @arg @ref LL_FMPI2C_GENERATE_STOP
+ * @arg @ref LL_FMPI2C_GENERATE_START_READ
+ * @arg @ref LL_FMPI2C_GENERATE_START_WRITE
+ * @arg @ref LL_FMPI2C_GENERATE_RESTART_7BIT_READ
+ * @arg @ref LL_FMPI2C_GENERATE_RESTART_7BIT_WRITE
+ * @arg @ref LL_FMPI2C_GENERATE_RESTART_10BIT_READ
+ * @arg @ref LL_FMPI2C_GENERATE_RESTART_10BIT_WRITE
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_HandleTransfer(FMPI2C_TypeDef *FMPI2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
+ uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
+{
+ MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_SADD | FMPI2C_CR2_ADD10 |
+ (FMPI2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - FMPI2C_CR2_RD_WRN_Pos))) |
+ FMPI2C_CR2_START | FMPI2C_CR2_STOP | FMPI2C_CR2_RELOAD |
+ FMPI2C_CR2_NBYTES | FMPI2C_CR2_AUTOEND | FMPI2C_CR2_HEAD10R,
+ SlaveAddr | SlaveAddrSize | (TransferSize << FMPI2C_CR2_NBYTES_Pos) | EndMode | Request);
+}
+
+/**
+ * @brief Indicate the value of transfer direction (slave mode).
+ * @note RESET: Write transfer, Slave enters in receiver mode.
+ * SET: Read transfer, Slave enters in transmitter mode.
+ * @rmtoll ISR DIR LL_FMPI2C_GetTransferDirection
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_FMPI2C_DIRECTION_WRITE
+ * @arg @ref LL_FMPI2C_DIRECTION_READ
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetTransferDirection(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_DIR));
+}
+
+/**
+ * @brief Return the slave matched address.
+ * @rmtoll ISR ADDCODE LL_FMPI2C_GetAddressMatchCode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0x00 and Max_Data=0x3F
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetAddressMatchCode(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_ADDCODE) >> FMPI2C_ISR_ADDCODE_Pos << 1);
+}
+
+/**
+ * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received.
+ * This bit has no effect when RELOAD bit is set.
+ * This bit has no effect in device mode when SBC bit is not set.
+ * @rmtoll CR2 PECBYTE LL_FMPI2C_EnableSMBusPECCompare
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableSMBusPECCompare(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_PECBYTE);
+}
+
+/**
+ * @brief Check if the SMBus Packet Error byte internal comparison is requested or not.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll CR2 PECBYTE LL_FMPI2C_IsEnabledSMBusPECCompare
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusPECCompare(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_PECBYTE) == (FMPI2C_CR2_PECBYTE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get the SMBus Packet Error byte calculated.
+ * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll PECR PEC LL_FMPI2C_GetSMBusPEC
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusPEC(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->PECR, FMPI2C_PECR_PEC));
+}
+
+/**
+ * @brief Read Receive Data register.
+ * @rmtoll RXDR RXDATA LL_FMPI2C_ReceiveData8
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t LL_FMPI2C_ReceiveData8(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint8_t)(READ_BIT(FMPI2Cx->RXDR, FMPI2C_RXDR_RXDATA));
+}
+
+/**
+ * @brief Write in Transmit Data Register .
+ * @rmtoll TXDR TXDATA LL_FMPI2C_TransmitData8
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_TransmitData8(FMPI2C_TypeDef *FMPI2Cx, uint8_t Data)
+{
+ WRITE_REG(FMPI2Cx->TXDR, Data);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup FMPI2C_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_FMPI2C_Init(FMPI2C_TypeDef *FMPI2Cx, LL_FMPI2C_InitTypeDef *FMPI2C_InitStruct);
+ErrorStatus LL_FMPI2C_DeInit(FMPI2C_TypeDef *FMPI2Cx);
+void LL_FMPI2C_StructInit(LL_FMPI2C_InitTypeDef *FMPI2C_InitStruct);
+
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* FMPI2C1 */
+
+/**
+ * @}
+ */
+
+#endif /* FMPI2C_CR1_PE */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F4xx_LL_FMPI2C_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h
index 3f1b3a1d6e..76e9170a0d 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h
@@ -939,7 +939,8 @@ __STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMas
*/
__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
- WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask);
+ uint32_t odr = READ_REG(GPIOx->ODR);
+ WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
}
/**
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h
index b173cc699b..5a46babfdc 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h
@@ -837,8 +837,8 @@ __STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx)
__STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed,
uint32_t DutyCycle)
{
- register uint32_t freqrange = 0x0U;
- register uint32_t clockconfig = 0x0U;
+ uint32_t freqrange = 0x0U;
+ uint32_t clockconfig = 0x0U;
/* Compute frequency range */
freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock);
@@ -1468,7 +1468,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef *I2Cx)
/**
* @brief Indicate the status of General call address reception (Slave mode).
- * @note RESET: No Generall call address
+ * @note RESET: No General call address
* SET: General call address received.
* @note This status is cleared by hardware after a STOP condition or repeated START condition.
* @rmtoll SR2 GENCALL LL_I2C_IsActiveFlag_GENCALL
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_iwdg.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_iwdg.h
index 5711351180..2f1b844a9c 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_iwdg.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_iwdg.h
@@ -236,7 +236,6 @@ __STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
return (READ_REG(IWDGx->RLR));
}
-
/**
* @}
*/
@@ -283,7 +282,6 @@ __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
* @}
*/
-
/**
* @}
*/
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_lptim.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_lptim.h
index 636e5fa4e6..0d8e8eaee8 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_lptim.h
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_lptim.h
@@ -4,7 +4,7 @@
* @author MCD Application Team
* @brief Header file of LPTIM LL module.
******************************************************************************
- * @attention
+ * @attention
*
*
@@ -155,7 +155,7 @@ typedef struct
/** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
* @{
*/
-#define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!Release Notes for STM32F4xx HAL Drivers