From 592284c66c8a93270cb77cb2a0afb36b64d2bc51 Mon Sep 17 00:00:00 2001 From: Meco Man <920369182@qq.com> Date: Sun, 8 Jan 2023 21:16:47 -0500 Subject: format link scripts --- .../board/linker_scripts/link.icf | 254 +++++++++---------- .../board/linker_scripts/link.lds | 2 +- .../board/linker_scripts/link.sct | 268 ++++++++++----------- .../board/linker_scripts/link.lds | 2 +- .../board/linker_scripts/link.sct | 16 +- .../board/linker_scripts/link.lds | 8 +- .../board/linker_scripts/link.lds | 2 +- .../board/linker_scripts/link.sct | 44 ++-- .../board/linker_scripts/link.lds | 2 +- .../board/linker_scripts/link.sct | 16 +- .../board/linker_scripts/link.lds | 2 +- .../board/linker_scripts/link.lds | 2 +- .../board/linker_scripts/link.sct | 26 +- .../MIMXRT1021/iar/MIMXRT1021xxxxx_flexspi_nor.icf | 186 +++++++------- .../iar/MIMXRT1021xxxxx_flexspi_nor_sdram.icf | 202 ++++++++-------- .../MIMXRT1021/iar/MIMXRT1021xxxxx_ram.icf | 162 ++++++------- .../MIMXRT1021/iar/MIMXRT1021xxxxx_sdram.icf | 178 +++++++------- .../MIMXRT1021/iar/MIMXRT1021xxxxx_sdram_txt.icf | 178 +++++++------- .../imxrt1050xxx/board/linker_scripts/link.lds | 8 +- .../imxrt1064xxx/board/linker_scripts/link.lds | 2 +- .../imxrt1064xxx/board/linker_scripts/link.sct | 28 +-- 21 files changed, 794 insertions(+), 794 deletions(-) (limited to 'bsp/imxrt') diff --git a/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.icf b/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.icf index 0f11aa45cb..1563925f19 100644 --- a/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.icf +++ b/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.icf @@ -1,127 +1,127 @@ -/* -** ################################################################### -** Processors: MIMXRT1052CVL5A -** MIMXRT1052DVL6A -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: IMXRT1050RM Rev.C, 08/2017 -** Version: rev. 0.1, 2017-01-10 -** Build: b170927 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -define symbol m_interrupts_start = 0x60002000; -define symbol m_interrupts_end = 0x600023FF; - -define symbol m_itcm_start = 0x00000000; -define symbol m_itcm_end = 0x0001FFFF; - -define symbol m_spiflash_start = 0x60002400; -define symbol m_spiflash_end = 0x7F7FFFFF; - -define symbol m_dtcm_start = 0x20000000; -define symbol m_dtcm_end = 0x2001FFFF;/* DTCM 128KB */ - -define symbol m_ocram_start = 0x20200000; -define symbol m_ocram_end = 0x2020FFFF;/* OCRAM 64KB */ - -define symbol m_sdram_start = 0x80000000; -define symbol m_sdram_end = 0x81DFFFFF; - -define symbol m_ncache_start = 0x81E00000; -define symbol m_ncache_end = 0x81FFFFFF; - -define exported symbol m_boot_hdr_conf_start = 0x60000000; -define symbol m_boot_hdr_ivt_start = 0x60001000; -define symbol m_boot_hdr_boot_data_start = 0x60001020; -define symbol m_boot_hdr_dcd_data_start = 0x60001030; - -/* Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define exported symbol __VECTOR_TABLE = m_interrupts_start; -define exported symbol __VECTOR_RAM = m_interrupts_start; -define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; -define exported symbol __RTT_HEAP_END = m_dtcm_end; - -define memory mem with size = 4G; -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_spiflash_start to m_spiflash_end]; - -define region ITCM_region = mem:[from m_itcm_start to m_itcm_end]; -define region DTCM_region = mem:[from m_dtcm_start to m_dtcm_end]; -define region OCRAM_region = mem:[from m_ocram_start to m_ocram_end]; -define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; -define region SDRAM_region = mem:[from m_sdram_start to m_sdram_end]; - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; -define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; - -initialize by copy { readwrite, section .textrw}; -do not initialize { section .noinit }; - -place at address mem: m_interrupts_start { readonly section .intvec }; - -place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf }; -place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt }; -place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data }; -place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data }; - -keep { section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data }; -keep { section FSymTab }; -keep { section VSymTab }; -keep { section .rti_fn* }; - -place in TEXT_region { readonly }; -place in DTCM_region { block RW }; -place in DTCM_region { block ZI }; -place in DTCM_region { last block HEAP }; -place in DTCM_region { block CSTACK }; -place in NCACHE_region { block NCACHE_VAR }; \ No newline at end of file +/* +** ################################################################### +** Processors: MIMXRT1052CVL5A +** MIMXRT1052DVL6A +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1050RM Rev.C, 08/2017 +** Version: rev. 0.1, 2017-01-10 +** Build: b170927 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** 1. Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** 2. Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** 3. Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +define symbol m_interrupts_start = 0x60002000; +define symbol m_interrupts_end = 0x600023FF; + +define symbol m_itcm_start = 0x00000000; +define symbol m_itcm_end = 0x0001FFFF; + +define symbol m_spiflash_start = 0x60002400; +define symbol m_spiflash_end = 0x7F7FFFFF; + +define symbol m_dtcm_start = 0x20000000; +define symbol m_dtcm_end = 0x2001FFFF;/* DTCM 128KB */ + +define symbol m_ocram_start = 0x20200000; +define symbol m_ocram_end = 0x2020FFFF;/* OCRAM 64KB */ + +define symbol m_sdram_start = 0x80000000; +define symbol m_sdram_end = 0x81DFFFFF; + +define symbol m_ncache_start = 0x81E00000; +define symbol m_ncache_end = 0x81FFFFFF; + +define exported symbol m_boot_hdr_conf_start = 0x60000000; +define symbol m_boot_hdr_ivt_start = 0x60001000; +define symbol m_boot_hdr_boot_data_start = 0x60001020; +define symbol m_boot_hdr_dcd_data_start = 0x60001030; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_interrupts_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; +define exported symbol __RTT_HEAP_END = m_dtcm_end; + +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_spiflash_start to m_spiflash_end]; + +define region ITCM_region = mem:[from m_itcm_start to m_itcm_end]; +define region DTCM_region = mem:[from m_dtcm_start to m_dtcm_end]; +define region OCRAM_region = mem:[from m_ocram_start to m_ocram_end]; +define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; +define region SDRAM_region = mem:[from m_sdram_start to m_sdram_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; +define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; + +initialize by copy { readwrite, section .textrw}; +do not initialize { section .noinit }; + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf }; +place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt }; +place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data }; +place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data }; + +keep { section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data }; +keep { section FSymTab }; +keep { section VSymTab }; +keep { section .rti_fn* }; + +place in TEXT_region { readonly }; +place in DTCM_region { block RW }; +place in DTCM_region { block ZI }; +place in DTCM_region { last block HEAP }; +place in DTCM_region { block CSTACK }; +place in NCACHE_region { block NCACHE_VAR }; diff --git a/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.lds b/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.lds index 7ef0bb392e..cf0b16b7b9 100644 --- a/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.lds +++ b/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.lds @@ -260,7 +260,7 @@ SECTIONS stack_end = .; __StackTop = .; } > m_dtcm - + .RTT_HEAP : { heap_start = .; diff --git a/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.sct b/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.sct index d6a1f80056..24ecc854aa 100644 --- a/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.sct +++ b/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.sct @@ -1,134 +1,134 @@ -#! armcc -E -/* -** ################################################################### -** Processors: MIMXRT1052CVL5A -** MIMXRT1052DVL6A -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: IMXRT1050RM Rev.C, 08/2017 -** Version: rev. 0.1, 2017-01-10 -** Build: b170927 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -#define m_flash_config_start 0x60000000 -#define m_flash_config_size 0x00001000 - -#define m_ivt_start 0x60001000 -#define m_ivt_size 0x00001000 - -#define m_text_start 0x60002000 -#define m_text_size 0x007FE000 - -#define m_data_start 0x20000000 -#define m_data_size 0x00020000 - -#define m_ncache_start 0x81E00000 -#define m_ncache_size 0x00200000 - -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x1000 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -#include "../../rtconfig.h" -;BSP_USING_HYPERFLASH -#if (defined(BOARD_USING_QSPIFLASH)) -LR_m_rom_config m_flash_config_start m_flash_config_size ; load region size_region -{ - RW_m_config_text m_flash_config_start m_flash_config_size ; load address = execution address - { - * (.boot_hdr.conf, +FIRST) - } -} - -LR_m_rom_ivt m_ivt_start m_ivt_size ; load region size_region -{ - RW_m_ivt_text m_ivt_start m_ivt_size ; load address = execution address - { - * (.boot_hdr.ivt, +FIRST) - * (.boot_hdr.boot_data) - * (.boot_hdr.dcd_data) - } -} -#endif - -#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK)) - -; load region size_region -LR_IROM1 m_text_start m_text_size -{ - ER_IROM1 m_text_start m_text_size ; load address = execution address - { - * (RESET,+FIRST) - * (InRoot$$Sections) - .ANY (+RO) - } - - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data - { - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP +0 EMPTY Heap_Size{} ; Heap region growing up - ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down - RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{} - - ; ncache RW data - RW_m_ncache m_ncache_start m_ncache_size - { - * (NonCacheable.init) - * (NonCacheable) - } - ITCM 0x400 0xFBFF { - ;drv_flexspi_hyper.o(+RO) - ;fsl_flexspi.o(+RO) - * (*CLOCK_DisableClock) - * (*CLOCK_ControlGate) - * (*CLOCK_EnableClock) - * (*CLOCK_SetDiv) - * (itcm) - } -} +#! armcc -E +/* +** ################################################################### +** Processors: MIMXRT1052CVL5A +** MIMXRT1052DVL6A +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: IMXRT1050RM Rev.C, 08/2017 +** Version: rev. 0.1, 2017-01-10 +** Build: b170927 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** 1. Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** 2. Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** 3. Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +#define m_flash_config_start 0x60000000 +#define m_flash_config_size 0x00001000 + +#define m_ivt_start 0x60001000 +#define m_ivt_size 0x00001000 + +#define m_text_start 0x60002000 +#define m_text_size 0x007FE000 + +#define m_data_start 0x20000000 +#define m_data_size 0x00020000 + +#define m_ncache_start 0x81E00000 +#define m_ncache_size 0x00200000 + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x1000 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +#include "../../rtconfig.h" +;BSP_USING_HYPERFLASH +#if (defined(BOARD_USING_QSPIFLASH)) +LR_m_rom_config m_flash_config_start m_flash_config_size ; load region size_region +{ + RW_m_config_text m_flash_config_start m_flash_config_size ; load address = execution address + { + * (.boot_hdr.conf, +FIRST) + } +} + +LR_m_rom_ivt m_ivt_start m_ivt_size ; load region size_region +{ + RW_m_ivt_text m_ivt_start m_ivt_size ; load address = execution address + { + * (.boot_hdr.ivt, +FIRST) + * (.boot_hdr.boot_data) + * (.boot_hdr.dcd_data) + } +} +#endif + +#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK)) + +; load region size_region +LR_IROM1 m_text_start m_text_size +{ + ER_IROM1 m_text_start m_text_size ; load address = execution address + { + * (RESET,+FIRST) + * (InRoot$$Sections) + .ANY (+RO) + } + + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data + { + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP +0 EMPTY Heap_Size{} ; Heap region growing up + ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down + RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{} + + ; ncache RW data + RW_m_ncache m_ncache_start m_ncache_size + { + * (NonCacheable.init) + * (NonCacheable) + } + ITCM 0x400 0xFBFF { + ;drv_flexspi_hyper.o(+RO) + ;fsl_flexspi.o(+RO) + * (*CLOCK_DisableClock) + * (*CLOCK_ControlGate) + * (*CLOCK_EnableClock) + * (*CLOCK_SetDiv) + * (itcm) + } +} diff --git a/bsp/imxrt/imxrt1052-atk-commander/board/linker_scripts/link.lds b/bsp/imxrt/imxrt1052-atk-commander/board/linker_scripts/link.lds index b8c229ae3c..d21ddb6a79 100644 --- a/bsp/imxrt/imxrt1052-atk-commander/board/linker_scripts/link.lds +++ b/bsp/imxrt/imxrt1052-atk-commander/board/linker_scripts/link.lds @@ -261,7 +261,7 @@ SECTIONS stack_end = .; __StackTop = .; } > m_dtcm - + .RTT_HEAP : { heap_start = .; diff --git a/bsp/imxrt/imxrt1052-atk-commander/board/linker_scripts/link.sct b/bsp/imxrt/imxrt1052-atk-commander/board/linker_scripts/link.sct index 7200f9d479..ef0ddf80f3 100644 --- a/bsp/imxrt/imxrt1052-atk-commander/board/linker_scripts/link.sct +++ b/bsp/imxrt/imxrt1052-atk-commander/board/linker_scripts/link.sct @@ -76,27 +76,27 @@ #define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK)) ; load region size_region -LR_IROM1 m_text_start m_text_size -{ +LR_IROM1 m_text_start m_text_size +{ ER_IROM1 m_text_start m_text_size ; load address = execution address - { + { * (RESET,+FIRST) * (InRoot$$Sections) .ANY (+RO) } - + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data - { + { .ANY (+RW +ZI) } - + ARM_LIB_HEAP +0 EMPTY Heap_Size{} ; Heap region growing up ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{} ; ncache RW data - RW_m_ncache m_ncache_start m_ncache_size - { + RW_m_ncache m_ncache_start m_ncache_size + { * (NonCacheable.init) * (NonCacheable) } diff --git a/bsp/imxrt/imxrt1052-fire-pro/board/linker_scripts/link.lds b/bsp/imxrt/imxrt1052-fire-pro/board/linker_scripts/link.lds index f585fbced8..1e11ddc014 100644 --- a/bsp/imxrt/imxrt1052-fire-pro/board/linker_scripts/link.lds +++ b/bsp/imxrt/imxrt1052-fire-pro/board/linker_scripts/link.lds @@ -86,9 +86,9 @@ SECTIONS .ivt : AT(ivt_begin) { . = ALIGN(4); - KEEP(* (.boot_hdr.ivt)) /* ivt section */ - KEEP(* (.boot_hdr.boot_data)) /* boot section */ - KEEP(* (.boot_hdr.dcd_data)) /* dcd section */ + KEEP(* (.boot_hdr.ivt)) /* ivt section */ + KEEP(* (.boot_hdr.boot_data)) /* boot section */ + KEEP(* (.boot_hdr.dcd_data)) /* dcd section */ . = ALIGN(4); } > m_ivt @@ -278,7 +278,7 @@ SECTIONS stack_end = .; __StackTop = .; } > m_data - + .RTT_HEAP : { heap_start = .; diff --git a/bsp/imxrt/imxrt1052-nxp-evk/board/linker_scripts/link.lds b/bsp/imxrt/imxrt1052-nxp-evk/board/linker_scripts/link.lds index b8c229ae3c..d21ddb6a79 100644 --- a/bsp/imxrt/imxrt1052-nxp-evk/board/linker_scripts/link.lds +++ b/bsp/imxrt/imxrt1052-nxp-evk/board/linker_scripts/link.lds @@ -261,7 +261,7 @@ SECTIONS stack_end = .; __StackTop = .; } > m_dtcm - + .RTT_HEAP : { heap_start = .; diff --git a/bsp/imxrt/imxrt1052-nxp-evk/board/linker_scripts/link.sct b/bsp/imxrt/imxrt1052-nxp-evk/board/linker_scripts/link.sct index 654c165f02..9e7f6546d2 100644 --- a/bsp/imxrt/imxrt1052-nxp-evk/board/linker_scripts/link.sct +++ b/bsp/imxrt/imxrt1052-nxp-evk/board/linker_scripts/link.sct @@ -77,58 +77,58 @@ #if (defined(BSP_USING_HYPERFLASH)) LR_m_rom_config m_flash_config_start m_flash_config_size ; load region size_region -{ +{ RW_m_config_text m_flash_config_start m_flash_config_size ; load address = execution address - { + { * (.boot_hdr.conf, +FIRST) - } + } } LR_m_rom_ivt m_ivt_start m_ivt_size ; load region size_region -{ +{ RW_m_ivt_text m_ivt_start m_ivt_size ; load address = execution address - { + { * (.boot_hdr.ivt, +FIRST) * (.boot_hdr.boot_data) * (.boot_hdr.dcd_data) - } + } } #endif #define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK)) ; load region size_region -LR_IROM1 m_text_start m_text_size -{ +LR_IROM1 m_text_start m_text_size +{ ER_IROM1 m_text_start m_text_size ; load address = execution address - { + { * (RESET,+FIRST) * (InRoot$$Sections) .ANY (+RO) } - + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data - { + { .ANY (+RW +ZI) } - + ARM_LIB_HEAP +0 EMPTY Heap_Size{} ; Heap region growing up ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{} ; ncache RW data - RW_m_ncache m_ncache_start m_ncache_size - { + RW_m_ncache m_ncache_start m_ncache_size + { * (NonCacheable.init) * (NonCacheable) } ITCM 0x400 0xFBFF { - ;drv_flexspi_hyper.o(+RO) - ;fsl_flexspi.o(+RO) - * (*CLOCK_DisableClock) - * (*CLOCK_ControlGate) - * (*CLOCK_EnableClock) - * (*CLOCK_SetDiv) - * (itcm) - } + ;drv_flexspi_hyper.o(+RO) + ;fsl_flexspi.o(+RO) + * (*CLOCK_DisableClock) + * (*CLOCK_ControlGate) + * (*CLOCK_EnableClock) + * (*CLOCK_SetDiv) + * (itcm) + } } diff --git a/bsp/imxrt/imxrt1052-seeed-ArchMix/board/linker_scripts/link.lds b/bsp/imxrt/imxrt1052-seeed-ArchMix/board/linker_scripts/link.lds index b8c229ae3c..d21ddb6a79 100644 --- a/bsp/imxrt/imxrt1052-seeed-ArchMix/board/linker_scripts/link.lds +++ b/bsp/imxrt/imxrt1052-seeed-ArchMix/board/linker_scripts/link.lds @@ -261,7 +261,7 @@ SECTIONS stack_end = .; __StackTop = .; } > m_dtcm - + .RTT_HEAP : { heap_start = .; diff --git a/bsp/imxrt/imxrt1052-seeed-ArchMix/board/linker_scripts/link.sct b/bsp/imxrt/imxrt1052-seeed-ArchMix/board/linker_scripts/link.sct index 7200f9d479..ef0ddf80f3 100644 --- a/bsp/imxrt/imxrt1052-seeed-ArchMix/board/linker_scripts/link.sct +++ b/bsp/imxrt/imxrt1052-seeed-ArchMix/board/linker_scripts/link.sct @@ -76,27 +76,27 @@ #define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK)) ; load region size_region -LR_IROM1 m_text_start m_text_size -{ +LR_IROM1 m_text_start m_text_size +{ ER_IROM1 m_text_start m_text_size ; load address = execution address - { + { * (RESET,+FIRST) * (InRoot$$Sections) .ANY (+RO) } - + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data - { + { .ANY (+RW +ZI) } - + ARM_LIB_HEAP +0 EMPTY Heap_Size{} ; Heap region growing up ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{} ; ncache RW data - RW_m_ncache m_ncache_start m_ncache_size - { + RW_m_ncache m_ncache_start m_ncache_size + { * (NonCacheable.init) * (NonCacheable) } diff --git a/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link.lds b/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link.lds index 0691d0fe48..ab64f3ef37 100644 --- a/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link.lds +++ b/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link.lds @@ -268,7 +268,7 @@ SECTIONS stack_end = .; __StackTop = .; } > m_sdram - + .RTT_HEAP : { heap_start = .; diff --git a/bsp/imxrt/imxrt1064-nxp-evk/board/linker_scripts/link.lds b/bsp/imxrt/imxrt1064-nxp-evk/board/linker_scripts/link.lds index 9942889d58..169a2d310a 100644 --- a/bsp/imxrt/imxrt1064-nxp-evk/board/linker_scripts/link.lds +++ b/bsp/imxrt/imxrt1064-nxp-evk/board/linker_scripts/link.lds @@ -268,7 +268,7 @@ SECTIONS stack_end = .; __StackTop = .; } > m_dtcm - + .RTT_HEAP : { heap_start = .; diff --git a/bsp/imxrt/imxrt1064-nxp-evk/board/linker_scripts/link.sct b/bsp/imxrt/imxrt1064-nxp-evk/board/linker_scripts/link.sct index f36201c200..d2a77d7319 100644 --- a/bsp/imxrt/imxrt1064-nxp-evk/board/linker_scripts/link.sct +++ b/bsp/imxrt/imxrt1064-nxp-evk/board/linker_scripts/link.sct @@ -86,48 +86,48 @@ #if (defined(BSP_USING_4MFLASH)) LR_m_rom_config m_flash_config_start m_flash_config_size ; load region size_region -{ +{ RW_m_config_text m_flash_config_start m_flash_config_size ; load address = execution address - { + { * (.boot_hdr.conf, +FIRST) - } + } } LR_m_rom_ivt m_ivt_start m_ivt_size ; load region size_region -{ +{ RW_m_ivt_text m_ivt_start m_ivt_size ; load address = execution address - { + { * (.boot_hdr.ivt, +FIRST) * (.boot_hdr.boot_data) * (.boot_hdr.dcd_data) - } + } } #endif #define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK)) ; load region size_region -LR_IROM1 m_text_start m_text_size -{ +LR_IROM1 m_text_start m_text_size +{ ER_IROM1 m_text_start m_text_size ; load address = execution address - { + { * (RESET,+FIRST) * (InRoot$$Sections) .ANY (+RO) } - + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data - { + { .ANY (+RW +ZI) } - + ARM_LIB_HEAP +0 EMPTY Heap_Size{} ; Heap region growing up ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{} ; ncache RW data RW_m_ncache m_ncache_start m_ncache_size - { + { * (NonCacheable.init) * (NonCacheable) } diff --git a/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_flexspi_nor.icf b/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_flexspi_nor.icf index a3a39c4731..497e6285c5 100644 --- a/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_flexspi_nor.icf +++ b/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_flexspi_nor.icf @@ -1,93 +1,93 @@ -/* -** ################################################################### -** Processors: MIMXRT1021CAF4A -** MIMXRT1021CAG4A -** MIMXRT1021DAF5A -** MIMXRT1021DAG5A -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: IMXRT1020RM Rev. 1RC, 05/2018 -** Version: rev. 0.1, 2017-06-06 -** Build: b180801 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -define symbol m_interrupts_start = 0x60002000; -define symbol m_interrupts_end = 0x600023FF; - -define symbol m_text_start = 0x60002400; -define symbol m_text_end = 0x607FFFFF; - -define symbol m_data_start = 0x20000000; -define symbol m_data_end = 0x2000FFFF; - -define symbol m_data2_start = 0x20200000; -define symbol m_data2_end = 0x2021FFFF; - -define exported symbol m_boot_hdr_conf_start = 0x60000000; -define symbol m_boot_hdr_ivt_start = 0x60001000; -define symbol m_boot_hdr_boot_data_start = 0x60001020; -define symbol m_boot_hdr_dcd_data_start = 0x60001030; - -/* Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define exported symbol __VECTOR_TABLE = m_interrupts_start; -define exported symbol __VECTOR_RAM = m_interrupts_start; -define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; - -define memory mem with size = 4G; -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; - -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; -define region DATA2_region = mem:[from m_data2_start to m_data2_end]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; -define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; - -initialize by copy { readwrite, section .textrw }; -do not initialize { section .noinit }; - -place at address mem: m_interrupts_start { readonly section .intvec }; - -place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf }; -place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt }; -place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data }; -place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data }; - -keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data }; - -place in TEXT_region { readonly }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { last block HEAP }; -place in DATA_region { block NCACHE_VAR }; -place in CSTACK_region { block CSTACK }; - +/* +** ################################################################### +** Processors: MIMXRT1021CAF4A +** MIMXRT1021CAG4A +** MIMXRT1021DAF5A +** MIMXRT1021DAG5A +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1020RM Rev. 1RC, 05/2018 +** Version: rev. 0.1, 2017-06-06 +** Build: b180801 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +define symbol m_interrupts_start = 0x60002000; +define symbol m_interrupts_end = 0x600023FF; + +define symbol m_text_start = 0x60002400; +define symbol m_text_end = 0x607FFFFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x2000FFFF; + +define symbol m_data2_start = 0x20200000; +define symbol m_data2_end = 0x2021FFFF; + +define exported symbol m_boot_hdr_conf_start = 0x60000000; +define symbol m_boot_hdr_ivt_start = 0x60001000; +define symbol m_boot_hdr_boot_data_start = 0x60001020; +define symbol m_boot_hdr_dcd_data_start = 0x60001030; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_interrupts_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; + +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; + +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region DATA2_region = mem:[from m_data2_start to m_data2_end]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; +define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; + +initialize by copy { readwrite, section .textrw }; +do not initialize { section .noinit }; + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf }; +place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt }; +place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data }; +place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data }; + +keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data }; + +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in DATA_region { block NCACHE_VAR }; +place in CSTACK_region { block CSTACK }; + diff --git a/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_flexspi_nor_sdram.icf b/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_flexspi_nor_sdram.icf index 5da51d70c6..54b091e58f 100644 --- a/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_flexspi_nor_sdram.icf +++ b/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_flexspi_nor_sdram.icf @@ -1,101 +1,101 @@ -/* -** ################################################################### -** Processors: MIMXRT1021CAF4A -** MIMXRT1021CAG4A -** MIMXRT1021DAF5A -** MIMXRT1021DAG5A -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: IMXRT1020RM Rev. 1RC, 05/2018 -** Version: rev. 0.1, 2017-06-06 -** Build: b180801 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -define symbol m_interrupts_start = 0x60002000; -define symbol m_interrupts_end = 0x600023FF; - -define symbol m_text_start = 0x60002400; -define symbol m_text_end = 0x607FFFFF; - -define symbol m_data_start = 0x20000000; -define symbol m_data_end = 0x2000FFFF; - -define symbol m_data2_start = 0x20200000; -define symbol m_data2_end = 0x2021FFFF; - -define symbol m_data3_start = 0x80000000; -define symbol m_data3_end = 0x81DFFFFF; - -define symbol m_ncache_start = 0x81E00000; -define symbol m_ncache_end = 0x81FFFFFF; - -define exported symbol m_boot_hdr_conf_start = 0x60000000; -define symbol m_boot_hdr_ivt_start = 0x60001000; -define symbol m_boot_hdr_boot_data_start = 0x60001020; -define symbol m_boot_hdr_dcd_data_start = 0x60001030; - -/* Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define exported symbol __VECTOR_TABLE = m_interrupts_start; -define exported symbol __VECTOR_RAM = m_interrupts_start; -define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; - -define memory mem with size = 4G; -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; - -define region DATA_region = mem:[from m_data_start to m_data_end]; -define region DATA2_region = mem:[from m_data2_start to m_data2_end]; -define region DATA3_region = mem:[from m_data3_start to m_data3_end-__size_cstack__]; -define region CSTACK_region = mem:[from m_data3_end-__size_cstack__+1 to m_data3_end]; -define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { first readwrite, section m_usb_dma_init_data }; -define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data }; -define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000 { section NonCacheable , section NonCacheable.init }; - -initialize by copy { readwrite, section .textrw }; -do not initialize { section .noinit }; - -place at address mem: m_interrupts_start { readonly section .intvec }; - -place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf }; -place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt }; -place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data }; -place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data }; - -keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data }; - -place in TEXT_region { readonly }; -place in DATA3_region { block RW }; -place in DATA3_region { block ZI }; -place in DATA3_region { last block HEAP }; -place in CSTACK_region { block CSTACK }; -place in NCACHE_region { block NCACHE_VAR }; - +/* +** ################################################################### +** Processors: MIMXRT1021CAF4A +** MIMXRT1021CAG4A +** MIMXRT1021DAF5A +** MIMXRT1021DAG5A +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1020RM Rev. 1RC, 05/2018 +** Version: rev. 0.1, 2017-06-06 +** Build: b180801 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +define symbol m_interrupts_start = 0x60002000; +define symbol m_interrupts_end = 0x600023FF; + +define symbol m_text_start = 0x60002400; +define symbol m_text_end = 0x607FFFFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x2000FFFF; + +define symbol m_data2_start = 0x20200000; +define symbol m_data2_end = 0x2021FFFF; + +define symbol m_data3_start = 0x80000000; +define symbol m_data3_end = 0x81DFFFFF; + +define symbol m_ncache_start = 0x81E00000; +define symbol m_ncache_end = 0x81FFFFFF; + +define exported symbol m_boot_hdr_conf_start = 0x60000000; +define symbol m_boot_hdr_ivt_start = 0x60001000; +define symbol m_boot_hdr_boot_data_start = 0x60001020; +define symbol m_boot_hdr_dcd_data_start = 0x60001030; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_interrupts_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; + +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; + +define region DATA_region = mem:[from m_data_start to m_data_end]; +define region DATA2_region = mem:[from m_data2_start to m_data2_end]; +define region DATA3_region = mem:[from m_data3_start to m_data3_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data3_end-__size_cstack__+1 to m_data3_end]; +define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { first readwrite, section m_usb_dma_init_data }; +define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data }; +define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000 { section NonCacheable , section NonCacheable.init }; + +initialize by copy { readwrite, section .textrw }; +do not initialize { section .noinit }; + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf }; +place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt }; +place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data }; +place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data }; + +keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data }; + +place in TEXT_region { readonly }; +place in DATA3_region { block RW }; +place in DATA3_region { block ZI }; +place in DATA3_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; +place in NCACHE_region { block NCACHE_VAR }; + diff --git a/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_ram.icf b/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_ram.icf index a835ba92c7..73a34d0385 100644 --- a/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_ram.icf +++ b/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_ram.icf @@ -1,81 +1,81 @@ -/* -** ################################################################### -** Processors: MIMXRT1021CAF4A -** MIMXRT1021CAG4A -** MIMXRT1021DAF5A -** MIMXRT1021DAG5A -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: IMXRT1020RM Rev. 1RC, 05/2018 -** Version: rev. 0.1, 2017-06-06 -** Build: b180801 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -define symbol m_interrupts_start = 0x00000000; -define symbol m_interrupts_end = 0x000003FF; - -define symbol m_text_start = 0x00000400; -define symbol m_text_end = 0x0000FFFF; - -define symbol m_data_start = 0x20000000; -define symbol m_data_end = 0x2000FFFF; - -define symbol m_data2_start = 0x20200000; -define symbol m_data2_end = 0x2021FFFF; - -/* Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define exported symbol __VECTOR_TABLE = m_interrupts_start; -define exported symbol __VECTOR_RAM = m_interrupts_start; -define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; - -define memory mem with size = 4G; -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; - -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; -define region DATA2_region = mem:[from m_data2_start to m_data2_end]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; -define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; - -initialize by copy { readwrite, section .textrw }; -do not initialize { section .noinit }; - -place at address mem: m_interrupts_start { readonly section .intvec }; - -place in TEXT_region { readonly }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { last block HEAP }; -place in DATA_region { block NCACHE_VAR }; -place in CSTACK_region { block CSTACK }; - +/* +** ################################################################### +** Processors: MIMXRT1021CAF4A +** MIMXRT1021CAG4A +** MIMXRT1021DAF5A +** MIMXRT1021DAG5A +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1020RM Rev. 1RC, 05/2018 +** Version: rev. 0.1, 2017-06-06 +** Build: b180801 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +define symbol m_interrupts_start = 0x00000000; +define symbol m_interrupts_end = 0x000003FF; + +define symbol m_text_start = 0x00000400; +define symbol m_text_end = 0x0000FFFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x2000FFFF; + +define symbol m_data2_start = 0x20200000; +define symbol m_data2_end = 0x2021FFFF; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_interrupts_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; + +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; + +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region DATA2_region = mem:[from m_data2_start to m_data2_end]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; +define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; + +initialize by copy { readwrite, section .textrw }; +do not initialize { section .noinit }; + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in DATA_region { block NCACHE_VAR }; +place in CSTACK_region { block CSTACK }; + diff --git a/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_sdram.icf b/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_sdram.icf index c2056d3ddc..6788c317e2 100644 --- a/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_sdram.icf +++ b/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_sdram.icf @@ -1,89 +1,89 @@ -/* -** ################################################################### -** Processors: MIMXRT1021CAF4A -** MIMXRT1021CAG4A -** MIMXRT1021DAF5A -** MIMXRT1021DAG5A -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: IMXRT1020RM Rev. 1RC, 05/2018 -** Version: rev. 0.1, 2017-06-06 -** Build: b180801 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -define symbol m_interrupts_start = 0x00000000; -define symbol m_interrupts_end = 0x000003FF; - -define symbol m_text_start = 0x00000400; -define symbol m_text_end = 0x0000FFFF; - -define symbol m_data_start = 0x20000000; -define symbol m_data_end = 0x2000FFFF; - -define symbol m_data2_start = 0x20200000; -define symbol m_data2_end = 0x2021FFFF; - -define symbol m_data3_start = 0x80000000; -define symbol m_data3_end = 0x81DFFFFF; - -define symbol m_ncache_start = 0x81E00000; -define symbol m_ncache_end = 0x81FFFFFF; - -/* Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define exported symbol __VECTOR_TABLE = m_interrupts_start; -define exported symbol __VECTOR_RAM = m_interrupts_start; -define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; - -define memory mem with size = 4G; -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; - -define region DATA_region = mem:[from m_data_start to m_data_end]; -define region DATA2_region = mem:[from m_data2_start to m_data2_end]; -define region DATA3_region = mem:[from m_data3_start to m_data3_end-__size_cstack__]; -define region CSTACK_region = mem:[from m_data3_end-__size_cstack__+1 to m_data3_end]; -define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { first readwrite, section m_usb_dma_init_data }; -define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data }; -define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000 { section NonCacheable , section NonCacheable.init }; - -initialize by copy { readwrite, section .textrw }; -do not initialize { section .noinit }; - -place at address mem: m_interrupts_start { readonly section .intvec }; - -place in TEXT_region { readonly }; -place in DATA3_region { block RW }; -place in DATA3_region { block ZI }; -place in DATA3_region { last block HEAP }; -place in CSTACK_region { block CSTACK }; -place in NCACHE_region { block NCACHE_VAR }; - +/* +** ################################################################### +** Processors: MIMXRT1021CAF4A +** MIMXRT1021CAG4A +** MIMXRT1021DAF5A +** MIMXRT1021DAG5A +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1020RM Rev. 1RC, 05/2018 +** Version: rev. 0.1, 2017-06-06 +** Build: b180801 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +define symbol m_interrupts_start = 0x00000000; +define symbol m_interrupts_end = 0x000003FF; + +define symbol m_text_start = 0x00000400; +define symbol m_text_end = 0x0000FFFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x2000FFFF; + +define symbol m_data2_start = 0x20200000; +define symbol m_data2_end = 0x2021FFFF; + +define symbol m_data3_start = 0x80000000; +define symbol m_data3_end = 0x81DFFFFF; + +define symbol m_ncache_start = 0x81E00000; +define symbol m_ncache_end = 0x81FFFFFF; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_interrupts_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; + +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; + +define region DATA_region = mem:[from m_data_start to m_data_end]; +define region DATA2_region = mem:[from m_data2_start to m_data2_end]; +define region DATA3_region = mem:[from m_data3_start to m_data3_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data3_end-__size_cstack__+1 to m_data3_end]; +define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { first readwrite, section m_usb_dma_init_data }; +define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data }; +define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000 { section NonCacheable , section NonCacheable.init }; + +initialize by copy { readwrite, section .textrw }; +do not initialize { section .noinit }; + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place in TEXT_region { readonly }; +place in DATA3_region { block RW }; +place in DATA3_region { block ZI }; +place in DATA3_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; +place in NCACHE_region { block NCACHE_VAR }; + diff --git a/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_sdram_txt.icf b/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_sdram_txt.icf index b94c4e4939..827d248639 100644 --- a/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_sdram_txt.icf +++ b/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_sdram_txt.icf @@ -1,89 +1,89 @@ -/* -** ################################################################### -** Processors: MIMXRT1021CAF4A -** MIMXRT1021CAG4A -** MIMXRT1021DAF5A -** MIMXRT1021DAG5A -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: IMXRT1020RM Rev. 1RC, 05/2018 -** Version: rev. 0.1, 2017-06-06 -** Build: b180801 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -define symbol m_interrupts_start = 0x80000000; -define symbol m_interrupts_end = 0x800003FF; - -define symbol m_text_start = 0x80000400; -define symbol m_text_end = 0x801FFFFF; - -define symbol m_data_start = 0x20000000; -define symbol m_data_end = 0x2000FFFF; - -define symbol m_data2_start = 0x20200000; -define symbol m_data2_end = 0x2021FFFF; - -define symbol m_data3_start = 0x80200000; -define symbol m_data3_end = 0x81DFFFFF; - -define symbol m_ncache_start = 0x81E00000; -define symbol m_ncache_end = 0x81FFFFFF; - -/* Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define exported symbol __VECTOR_TABLE = m_interrupts_start; -define exported symbol __VECTOR_RAM = m_interrupts_start; -define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; - -define memory mem with size = 4G; -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; - -define region DATA_region = mem:[from m_data_start to m_data_end]; -define region DATA2_region = mem:[from m_data2_start to m_data2_end-__size_cstack__]; -define region DATA3_region = mem:[from m_data3_start to m_data3_end]; -define region CSTACK_region = mem:[from m_data2_end-__size_cstack__+1 to m_data2_end]; -define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { first readwrite, section m_usb_dma_init_data }; -define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data }; -define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000 { section NonCacheable , section NonCacheable.init }; - -initialize by copy { readwrite, section .textrw }; -do not initialize { section .noinit }; - -place at address mem: m_interrupts_start { readonly section .intvec }; - -place in TEXT_region { readonly }; -place in DATA2_region { block RW }; -place in DATA2_region { block ZI }; -place in DATA2_region { last block HEAP }; -place in CSTACK_region { block CSTACK }; -place in NCACHE_region { block NCACHE_VAR }; - +/* +** ################################################################### +** Processors: MIMXRT1021CAF4A +** MIMXRT1021CAG4A +** MIMXRT1021DAF5A +** MIMXRT1021DAG5A +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1020RM Rev. 1RC, 05/2018 +** Version: rev. 0.1, 2017-06-06 +** Build: b180801 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +define symbol m_interrupts_start = 0x80000000; +define symbol m_interrupts_end = 0x800003FF; + +define symbol m_text_start = 0x80000400; +define symbol m_text_end = 0x801FFFFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x2000FFFF; + +define symbol m_data2_start = 0x20200000; +define symbol m_data2_end = 0x2021FFFF; + +define symbol m_data3_start = 0x80200000; +define symbol m_data3_end = 0x81DFFFFF; + +define symbol m_ncache_start = 0x81E00000; +define symbol m_ncache_end = 0x81FFFFFF; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_interrupts_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; + +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; + +define region DATA_region = mem:[from m_data_start to m_data_end]; +define region DATA2_region = mem:[from m_data2_start to m_data2_end-__size_cstack__]; +define region DATA3_region = mem:[from m_data3_start to m_data3_end]; +define region CSTACK_region = mem:[from m_data2_end-__size_cstack__+1 to m_data2_end]; +define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { first readwrite, section m_usb_dma_init_data }; +define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data }; +define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000 { section NonCacheable , section NonCacheable.init }; + +initialize by copy { readwrite, section .textrw }; +do not initialize { section .noinit }; + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place in TEXT_region { readonly }; +place in DATA2_region { block RW }; +place in DATA2_region { block ZI }; +place in DATA2_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; +place in NCACHE_region { block NCACHE_VAR }; + diff --git a/bsp/imxrt/libraries/templates/imxrt1050xxx/board/linker_scripts/link.lds b/bsp/imxrt/libraries/templates/imxrt1050xxx/board/linker_scripts/link.lds index a0a306f370..d2f73ebaf0 100644 --- a/bsp/imxrt/libraries/templates/imxrt1050xxx/board/linker_scripts/link.lds +++ b/bsp/imxrt/libraries/templates/imxrt1050xxx/board/linker_scripts/link.lds @@ -86,9 +86,9 @@ SECTIONS .ivt : AT(ivt_begin) { . = ALIGN(4); - KEEP(* (.boot_hdr.ivt)) /* ivt section */ - KEEP(* (.boot_hdr.boot_data)) /* boot section */ - KEEP(* (.boot_hdr.dcd_data)) /* dcd section */ + KEEP(* (.boot_hdr.ivt)) /* ivt section */ + KEEP(* (.boot_hdr.boot_data)) /* boot section */ + KEEP(* (.boot_hdr.dcd_data)) /* dcd section */ . = ALIGN(4); } > m_ivt @@ -278,7 +278,7 @@ SECTIONS stack_end = .; __StackTop = .; } > m_data - + .RTT_HEAP : { heap_start = .; diff --git a/bsp/imxrt/libraries/templates/imxrt1064xxx/board/linker_scripts/link.lds b/bsp/imxrt/libraries/templates/imxrt1064xxx/board/linker_scripts/link.lds index 9942889d58..169a2d310a 100644 --- a/bsp/imxrt/libraries/templates/imxrt1064xxx/board/linker_scripts/link.lds +++ b/bsp/imxrt/libraries/templates/imxrt1064xxx/board/linker_scripts/link.lds @@ -268,7 +268,7 @@ SECTIONS stack_end = .; __StackTop = .; } > m_dtcm - + .RTT_HEAP : { heap_start = .; diff --git a/bsp/imxrt/libraries/templates/imxrt1064xxx/board/linker_scripts/link.sct b/bsp/imxrt/libraries/templates/imxrt1064xxx/board/linker_scripts/link.sct index 7b7bf4fbba..d179e6093f 100644 --- a/bsp/imxrt/libraries/templates/imxrt1064xxx/board/linker_scripts/link.sct +++ b/bsp/imxrt/libraries/templates/imxrt1064xxx/board/linker_scripts/link.sct @@ -84,48 +84,48 @@ #if (defined(BSP_USING_4MFLASH)) LR_m_rom_config m_flash_config_start m_flash_config_size ; load region size_region -{ +{ RW_m_config_text m_flash_config_start m_flash_config_size ; load address = execution address - { + { * (.boot_hdr.conf, +FIRST) - } + } } LR_m_rom_ivt m_ivt_start m_ivt_size ; load region size_region -{ +{ RW_m_ivt_text m_ivt_start m_ivt_size ; load address = execution address - { + { * (.boot_hdr.ivt, +FIRST) * (.boot_hdr.boot_data) * (.boot_hdr.dcd_data) - } + } } #endif #define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK)) ; load region size_region -LR_IROM1 m_text_start m_text_size -{ +LR_IROM1 m_text_start m_text_size +{ ER_IROM1 m_text_start m_text_size ; load address = execution address - { + { * (RESET,+FIRST) * (InRoot$$Sections) .ANY (+RO) } - + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data - { + { .ANY (+RW +ZI) } - + ARM_LIB_HEAP +0 EMPTY Heap_Size{} ; Heap region growing up ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{} ; ncache RW data - RW_m_ncache m_data2_start m_data2_size - { + RW_m_ncache m_data2_start m_data2_size + { * (NonCacheable.init) * (NonCacheable) } -- cgit v1.3.1