From 71751eb6f1dada410ab404d5ee8ae501db70b022 Mon Sep 17 00:00:00 2001 From: SummerGift Date: Mon, 17 Dec 2018 10:38:15 +0800 Subject: [bsp][stm32] add sdio, hw_timer and pwm drivers --- bsp/stm32/libraries/HAL_Drivers/SConscript | 16 +- .../libraries/HAL_Drivers/config/f1/pwm_config.h | 60 ++ .../libraries/HAL_Drivers/config/f1/sdio_config.h | 36 + .../libraries/HAL_Drivers/config/f1/tim_config.h | 70 ++ .../libraries/HAL_Drivers/config/f4/pwm_config.h | 60 ++ .../libraries/HAL_Drivers/config/f4/sdio_config.h | 38 + .../libraries/HAL_Drivers/config/f4/tim_config.h | 59 ++ .../libraries/HAL_Drivers/config/l4/pwm_config.h | 60 ++ .../libraries/HAL_Drivers/config/l4/tim_config.h | 59 ++ bsp/stm32/libraries/HAL_Drivers/drv_config.h | 8 + bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c | 525 +++++++++++++ bsp/stm32/libraries/HAL_Drivers/drv_pwm.c | 480 ++++++++++++ bsp/stm32/libraries/HAL_Drivers/drv_sdio.c | 846 +++++++++++++++++++++ bsp/stm32/libraries/HAL_Drivers/drv_sdio.h | 178 +++++ 14 files changed, 2490 insertions(+), 5 deletions(-) create mode 100644 bsp/stm32/libraries/HAL_Drivers/config/f1/pwm_config.h create mode 100644 bsp/stm32/libraries/HAL_Drivers/config/f1/sdio_config.h create mode 100644 bsp/stm32/libraries/HAL_Drivers/config/f1/tim_config.h create mode 100644 bsp/stm32/libraries/HAL_Drivers/config/f4/pwm_config.h create mode 100644 bsp/stm32/libraries/HAL_Drivers/config/f4/sdio_config.h create mode 100644 bsp/stm32/libraries/HAL_Drivers/config/f4/tim_config.h create mode 100644 bsp/stm32/libraries/HAL_Drivers/config/l4/pwm_config.h create mode 100644 bsp/stm32/libraries/HAL_Drivers/config/l4/tim_config.h create mode 100644 bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c create mode 100644 bsp/stm32/libraries/HAL_Drivers/drv_pwm.c create mode 100644 bsp/stm32/libraries/HAL_Drivers/drv_sdio.c create mode 100644 bsp/stm32/libraries/HAL_Drivers/drv_sdio.h (limited to 'bsp/stm32/libraries') diff --git a/bsp/stm32/libraries/HAL_Drivers/SConscript b/bsp/stm32/libraries/HAL_Drivers/SConscript index c37704bb80..ff0725e3b0 100644 --- a/bsp/stm32/libraries/HAL_Drivers/SConscript +++ b/bsp/stm32/libraries/HAL_Drivers/SConscript @@ -13,7 +13,13 @@ if GetDepend(['RT_USING_PIN']): if GetDepend(['RT_USING_SERIAL']): src += ['drv_usart.c'] - + +if GetDepend(['RT_USING_HWTIMER']): + src += ['drv_hwtimer.c'] + +if GetDepend(['RT_USING_PWM']): + src += ['drv_pwm.c'] + if GetDepend(['RT_USING_SPI']): src += ['drv_spi.c'] @@ -22,10 +28,7 @@ if GetDepend(['RT_USING_QSPI']): if GetDepend(['RT_USING_USB_DEVICE']): src += ['drv_usb.c'] - -if GetDepend(['RT_USING_SDCARD']): - src += ['drv_sdcard.c'] - + if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']): src += ['drv_soft_i2c.c'] @@ -53,6 +56,9 @@ if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32L4']): if GetDepend(['BSP_USING_WDT']): src += ['drv_wdt.c'] +if GetDepend(['BSP_USING_SDIO']): + src += ['drv_sdio.c'] + src += ['drv_common.c'] path = [cwd] diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f1/pwm_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f1/pwm_config.h new file mode 100644 index 0000000000..2474460ccd --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/f1/pwm_config.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-13 zylx first version + */ + +#ifndef __PWM_CONFIG_H__ +#define __PWM_CONFIG_H__ + +#include + +#ifdef BSP_USING_PWM2 +#ifndef PWM2_CONFIG +#define PWM2_CONFIG \ + { \ + .tim_handle.Instance = TIM2, \ + .name = "pwm2", \ + .channel = 0 \ + } +#endif /* PWM2_CONFIG */ +#endif /* BSP_USING_PWM2 */ + +#ifdef BSP_USING_PWM3 +#ifndef PWM3_CONFIG +#define PWM3_CONFIG \ + { \ + .tim_handle.Instance = TIM3, \ + .name = "pwm3", \ + .channel = 0 \ + } +#endif /* PWM3_CONFIG */ +#endif /* BSP_USING_PWM3 */ + +#ifdef BSP_USING_PWM4 +#ifndef PWM4_CONFIG +#define PWM4_CONFIG \ + { \ + .tim_handle.Instance = TIM4, \ + .name = "pwm4", \ + .channel = 0 \ + } +#endif /* PWM4_CONFIG */ +#endif /* BSP_USING_PWM4 */ + +#ifdef BSP_USING_PWM5 +#ifndef PWM5_CONFIG +#define PWM5_CONFIG \ + { \ + .tim_handle.Instance = TIM5, \ + .name = "pwm5", \ + .channel = 0 \ + } +#endif /* PWM5_CONFIG */ +#endif /* BSP_USING_PWM5 */ + +#endif /* __PWM_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f1/sdio_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f1/sdio_config.h new file mode 100644 index 0000000000..5bee78d7fa --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/f1/sdio_config.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-13 BalanceTWK first version + */ + +#ifndef __SDIO_CONFIG_H__ +#define __SDIO_CONFIG_H__ + +#include +#include "stm32f1xx_hal.h" + +#ifdef BSP_USING_SDIO +#define SDIO_BUS_CONFIG \ + { \ + .Instance = SDIO, \ + .dma_rx.dma_rcc = RCC_AHBENR_DMA2EN, \ + .dma_tx.dma_rcc = RCC_AHBENR_DMA2EN, \ + .dma_rx.Instance = DMA2_Channel4, \ + .dma_rx.dma_irq = DMA2_Channel4_IRQn, \ + .dma_tx.Instance = DMA2_Channel4, \ + .dma_tx.dma_irq = DMA2_Channel4_IRQn, \ + } + +#define SPI1_DMA_RX_IRQHandler DMA2_Channel4_IRQHandler +#define SPI1_DMA_TX_IRQHandler DMA2_Channel4_IRQHandler +#endif + +#endif /*__SDIO_CONFIG_H__ */ + + + diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f1/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f1/tim_config.h new file mode 100644 index 0000000000..75a3e0b84a --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/f1/tim_config.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-11 zylx first version + */ + +#ifndef __TIM_CONFIG_H__ +#define __TIM_CONFIG_H__ + +#include + +#ifndef TIM_DEV_INFO_CONFIG +#define TIM_DEV_INFO_CONFIG \ + { \ + .maxfreq = 1000000, \ + .minfreq = 2000, \ + .maxcnt = 0xFFFF, \ + .cntmode = HWTIMER_CNTMODE_UP, \ + } +#endif /* TIM_DEV_INFO_CONFIG */ + +#ifdef BSP_USING_TIM2 +#ifndef TIM2_CONFIG +#define TIM2_CONFIG \ + { \ + .tim_handle.Instance = TIM2, \ + .tim_irqn = TIM2_IRQn, \ + .name = "timer2", \ + } +#endif /* TIM2_CONFIG */ +#endif /* BSP_USING_TIM2 */ + +#ifdef BSP_USING_TIM3 +#ifndef TIM3_CONFIG +#define TIM3_CONFIG \ + { \ + .tim_handle.Instance = TIM3, \ + .tim_irqn = TIM3_IRQn, \ + .name = "timer3", \ + } +#endif /* TIM3_CONFIG */ +#endif /* BSP_USING_TIM3 */ + +#ifdef BSP_USING_TIM4 +#ifndef TIM4_CONFIG +#define TIM4_CONFIG \ + { \ + .tim_handle.Instance = TIM4, \ + .tim_irqn = TIM4_IRQn, \ + .name = "timer4", \ + } +#endif /* TIM4_CONFIG */ +#endif /* BSP_USING_TIM4 */ + +#ifdef BSP_USING_TIM5 +#ifndef TIM5_CONFIG +#define TIM5_CONFIG \ + { \ + .tim_handle.Instance = TIM5, \ + .tim_irqn = TIM5_IRQn, \ + .name = "timer5", \ + } +#endif /* TIM5_CONFIG */ +#endif /* BSP_USING_TIM5 */ + +#endif /* __TIM_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/pwm_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/pwm_config.h new file mode 100644 index 0000000000..2474460ccd --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/pwm_config.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-13 zylx first version + */ + +#ifndef __PWM_CONFIG_H__ +#define __PWM_CONFIG_H__ + +#include + +#ifdef BSP_USING_PWM2 +#ifndef PWM2_CONFIG +#define PWM2_CONFIG \ + { \ + .tim_handle.Instance = TIM2, \ + .name = "pwm2", \ + .channel = 0 \ + } +#endif /* PWM2_CONFIG */ +#endif /* BSP_USING_PWM2 */ + +#ifdef BSP_USING_PWM3 +#ifndef PWM3_CONFIG +#define PWM3_CONFIG \ + { \ + .tim_handle.Instance = TIM3, \ + .name = "pwm3", \ + .channel = 0 \ + } +#endif /* PWM3_CONFIG */ +#endif /* BSP_USING_PWM3 */ + +#ifdef BSP_USING_PWM4 +#ifndef PWM4_CONFIG +#define PWM4_CONFIG \ + { \ + .tim_handle.Instance = TIM4, \ + .name = "pwm4", \ + .channel = 0 \ + } +#endif /* PWM4_CONFIG */ +#endif /* BSP_USING_PWM4 */ + +#ifdef BSP_USING_PWM5 +#ifndef PWM5_CONFIG +#define PWM5_CONFIG \ + { \ + .tim_handle.Instance = TIM5, \ + .name = "pwm5", \ + .channel = 0 \ + } +#endif /* PWM5_CONFIG */ +#endif /* BSP_USING_PWM5 */ + +#endif /* __PWM_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/sdio_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/sdio_config.h new file mode 100644 index 0000000000..40f3d03e10 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/sdio_config.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-13 BalanceTWK first version + */ + +#ifndef __SDIO_CONFIG_H__ +#define __SDIO_CONFIG_H__ + +#include +#include "stm32f4xx_hal.h" + +#ifdef BSP_USING_SDIO +#define SDIO_BUS_CONFIG \ + { \ + .Instance = SDIO, \ + .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ + .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ + .dma_rx.Instance = DMA2_Stream3, \ + .dma_rx.channel = DMA_CHANNEL_4, \ + .dma_rx.dma_irq = DMA2_Stream3_IRQn, \ + .dma_tx.Instance = DMA2_Stream6, \ + .dma_tx.channel = DMA_CHANNEL_4, \ + .dma_tx.dma_irq = DMA2_Stream6_IRQn, \ + } + +#define SPI1_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler +#define SPI1_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler +#endif + +#endif /*__SDIO_CONFIG_H__ */ + + + diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/tim_config.h new file mode 100644 index 0000000000..169d07a7a4 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/tim_config.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-11 zylx first version + */ + +#ifndef __TIM_CONFIG_H__ +#define __TIM_CONFIG_H__ + +#include + +#ifndef TIM_DEV_INFO_CONFIG +#define TIM_DEV_INFO_CONFIG \ + { \ + .maxfreq = 1000000, \ + .minfreq = 3000, \ + .maxcnt = 0xFFFF, \ + .cntmode = HWTIMER_CNTMODE_UP, \ + } +#endif /* TIM_DEV_INFO_CONFIG */ + +#ifdef BSP_USING_TIM11 +#ifndef TIM11_CONFIG +#define TIM11_CONFIG \ + { \ + .tim_handle.Instance = TIM11, \ + .tim_irqn = TIM1_TRG_COM_TIM11_IRQn, \ + .name = "timer11", \ + } +#endif /* TIM11_CONFIG */ +#endif /* BSP_USING_TIM11 */ + +#ifdef BSP_USING_TIM13 +#ifndef TIM13_CONFIG +#define TIM13_CONFIG \ + { \ + .tim_handle.Instance = TIM13, \ + .tim_irqn = TIM8_UP_TIM13_IRQn, \ + .name = "timer13", \ + } +#endif /* TIM13_CONFIG */ +#endif /* BSP_USING_TIM13 */ + +#ifdef BSP_USING_TIM14 +#ifndef TIM14_CONFIG +#define TIM14_CONFIG \ + { \ + .tim_handle.Instance = TIM14, \ + .tim_irqn = TIM8_TRG_COM_TIM14_IRQn, \ + .name = "timer14", \ + } +#endif /* TIM14_CONFIG */ +#endif /* BSP_USING_TIM14 */ + +#endif /* __TIM_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/pwm_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/pwm_config.h new file mode 100644 index 0000000000..2474460ccd --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/pwm_config.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-13 zylx first version + */ + +#ifndef __PWM_CONFIG_H__ +#define __PWM_CONFIG_H__ + +#include + +#ifdef BSP_USING_PWM2 +#ifndef PWM2_CONFIG +#define PWM2_CONFIG \ + { \ + .tim_handle.Instance = TIM2, \ + .name = "pwm2", \ + .channel = 0 \ + } +#endif /* PWM2_CONFIG */ +#endif /* BSP_USING_PWM2 */ + +#ifdef BSP_USING_PWM3 +#ifndef PWM3_CONFIG +#define PWM3_CONFIG \ + { \ + .tim_handle.Instance = TIM3, \ + .name = "pwm3", \ + .channel = 0 \ + } +#endif /* PWM3_CONFIG */ +#endif /* BSP_USING_PWM3 */ + +#ifdef BSP_USING_PWM4 +#ifndef PWM4_CONFIG +#define PWM4_CONFIG \ + { \ + .tim_handle.Instance = TIM4, \ + .name = "pwm4", \ + .channel = 0 \ + } +#endif /* PWM4_CONFIG */ +#endif /* BSP_USING_PWM4 */ + +#ifdef BSP_USING_PWM5 +#ifndef PWM5_CONFIG +#define PWM5_CONFIG \ + { \ + .tim_handle.Instance = TIM5, \ + .name = "pwm5", \ + .channel = 0 \ + } +#endif /* PWM5_CONFIG */ +#endif /* BSP_USING_PWM5 */ + +#endif /* __PWM_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/tim_config.h new file mode 100644 index 0000000000..fe857cc360 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/tim_config.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-12 zylx first version + */ + +#ifndef __TIM_CONFIG_H__ +#define __TIM_CONFIG_H__ + +#include + +#ifndef TIM_DEV_INFO_CONFIG +#define TIM_DEV_INFO_CONFIG \ + { \ + .maxfreq = 1000000, \ + .minfreq = 2000, \ + .maxcnt = 0xFFFF, \ + .cntmode = HWTIMER_CNTMODE_UP, \ + } +#endif /* TIM_DEV_INFO_CONFIG */ + +#ifdef BSP_USING_TIM15 +#ifndef TIM15_CONFIG +#define TIM15_CONFIG \ + { \ + .tim_handle.Instance = TIM15, \ + .tim_irqn = TIM1_BRK_TIM15_IRQn, \ + .name = "timer15", \ + } +#endif /* TIM15_CONFIG */ +#endif /* BSP_USING_TIM15 */ + +#ifdef BSP_USING_TIM16 +#ifndef TIM16_CONFIG +#define TIM16_CONFIG \ + { \ + .tim_handle.Instance = TIM16, \ + .tim_irqn = TIM1_UP_TIM16_IRQn, \ + .name = "timer16", \ + } +#endif /* TIM16_CONFIG */ +#endif /* BSP_USING_TIM16 */ + +#ifdef BSP_USING_TIM17 +#ifndef TIM17_CONFIG +#define TIM17_CONFIG \ + { \ + .tim_handle.Instance = TIM17, \ + .tim_irqn = TIM1_TRG_COM_TIM17_IRQn, \ + .name = "timer17", \ + } +#endif /* TIM17_CONFIG */ +#endif /* BSP_USING_TIM17 */ + +#endif /* __TIM_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_config.h b/bsp/stm32/libraries/HAL_Drivers/drv_config.h index 5a1aae7b40..1887d12ffa 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drv_config.h @@ -18,14 +18,22 @@ #include "f1/uart_config.h" #include "f1/spi_config.h" #include "f1/adc_config.h" +#include "f1/tim_config.h" +#include "f1/sdio_config.h" +#include "f1/pwm_config.h" #elif defined(SOC_SERIES_STM32F4) #include "f4/uart_config.h" #include "f4/spi_config.h" #include "f4/adc_config.h" +#include "f4/tim_config.h" +#include "f4/sdio_config.h" +#include "f4/pwm_config.h" #elif defined(SOC_SERIES_STM32L4) #include "l4/uart_config.h" #include "l4/spi_config.h" #include "l4/adc_config.h" +#include "l4/tim_config.h" +#include "l4/pwm_config.h" #endif #endif diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c b/bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c new file mode 100644 index 0000000000..4f17425d86 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c @@ -0,0 +1,525 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 zylx first version + */ + +#include +#ifdef BSP_USING_TIM +#include "drv_config.h" + +//#define DRV_DEBUG +#define LOG_TAG "drv.hwtimer" +#include + +#ifdef RT_USING_HWTIMER +enum +{ +#ifdef BSP_USING_TIM1 + TIM1_INDEX, +#endif +#ifdef BSP_USING_TIM2 + TIM2_INDEX, +#endif +#ifdef BSP_USING_TIM3 + TIM3_INDEX, +#endif +#ifdef BSP_USING_TIM4 + TIM4_INDEX, +#endif +#ifdef BSP_USING_TIM5 + TIM5_INDEX, +#endif +#ifdef BSP_USING_TIM6 + TIM6_INDEX, +#endif +#ifdef BSP_USING_TIM7 + TIM7_INDEX, +#endif +#ifdef BSP_USING_TIM8 + TIM8_INDEX, +#endif +#ifdef BSP_USING_TIM9 + TIM9_INDEX, +#endif +#ifdef BSP_USING_TIM10 + TIM10_INDEX, +#endif +#ifdef BSP_USING_TIM11 + TIM11_INDEX, +#endif +#ifdef BSP_USING_TIM12 + TIM12_INDEX, +#endif +#ifdef BSP_USING_TIM13 + TIM13_INDEX, +#endif +#ifdef BSP_USING_TIM14 + TIM14_INDEX, +#endif +#ifdef BSP_USING_TIM15 + TIM15_INDEX, +#endif +#ifdef BSP_USING_TIM16 + TIM16_INDEX, +#endif +#ifdef BSP_USING_TIM17 + TIM17_INDEX, +#endif +}; + +struct stm32_hwtimer +{ + rt_hwtimer_t time_device; + TIM_HandleTypeDef tim_handle; + IRQn_Type tim_irqn; + char *name; +}; + +static struct stm32_hwtimer stm32_hwtimer_obj[] = +{ +#ifdef BSP_USING_TIM1 + TIM1_CONFIG, +#endif + +#ifdef BSP_USING_TIM2 + TIM2_CONFIG, +#endif + +#ifdef BSP_USING_TIM3 + TIM3_CONFIG, +#endif + +#ifdef BSP_USING_TIM4 + TIM4_CONFIG, +#endif + +#ifdef BSP_USING_TIM5 + TIM5_CONFIG, +#endif + +#ifdef BSP_USING_TIM6 + TIM6_CONFIG, +#endif + +#ifdef BSP_USING_TIM7 + TIM7_CONFIG, +#endif + +#ifdef BSP_USING_TIM8 + TIM8_CONFIG, +#endif + +#ifdef BSP_USING_TIM9 + TIM9_CONFIG, +#endif + +#ifdef BSP_USING_TIM10 + TIM10_CONFIG, +#endif + +#ifdef BSP_USING_TIM11 + TIM11_CONFIG, +#endif + +#ifdef BSP_USING_TIM12 + TIM12_CONFIG, +#endif + +#ifdef BSP_USING_TIM13 + TIM13_CONFIG, +#endif + +#ifdef BSP_USING_TIM14 + TIM14_CONFIG, +#endif + +#ifdef BSP_USING_TIM15 + TIM15_CONFIG, +#endif + +#ifdef BSP_USING_TIM16 + TIM16_CONFIG, +#endif + +#ifdef BSP_USING_TIM17 + TIM17_CONFIG, +#endif +}; + +static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) +{ + uint32_t prescaler_value = 0; + TIM_HandleTypeDef *tim = RT_NULL; + struct stm32_hwtimer *tim_device = RT_NULL; + + RT_ASSERT(timer != RT_NULL); + if (state) + { + tim = (TIM_HandleTypeDef *)timer->parent.user_data; + tim_device = (struct stm32_hwtimer *)timer; + + /* time init */ +#if defined(SOC_SERIES_STM32F4) + if (tim->Instance == TIM9 || tim->Instance == TIM10 || tim->Instance == TIM11) +#elif defined(SOC_SERIES_STM32L4) + if (tim->Instance == TIM15 || tim->Instance == TIM16 || tim->Instance == TIM17) +#elif defined(SOC_SERIES_STM32F1) + if (0) +#endif + { + prescaler_value = (uint32_t)(HAL_RCC_GetPCLK2Freq() * 2 / 10000) - 1; + } + else + { + prescaler_value = (uint32_t)(HAL_RCC_GetPCLK1Freq() * 2 / 10000) - 1; + } + tim->Init.Period = 10000 - 1; + tim->Init.Prescaler = prescaler_value; + tim->Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + if (timer->info->cntmode == HWTIMER_CNTMODE_UP) + { + tim->Init.CounterMode = TIM_COUNTERMODE_UP; + } + else + { + tim->Init.CounterMode = TIM_COUNTERMODE_DOWN; + } + tim->Init.RepetitionCounter = 0; +#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) + tim->Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; +#endif + if (HAL_TIM_Base_Init(tim) != HAL_OK) + { + LOG_E("%s init failed", tim_device->name); + return; + } + else + { + /* set the TIMx priority */ + HAL_NVIC_SetPriority(tim_device->tim_irqn, 3, 0); + + /* enable the TIMx global Interrupt */ + HAL_NVIC_EnableIRQ(tim_device->tim_irqn); + + /* clear update flag */ + __HAL_TIM_CLEAR_FLAG(tim, TIM_FLAG_UPDATE); + /* enable update request source */ + __HAL_TIM_URS_ENABLE(tim); + + LOG_D("%s init success", tim_device->name); + } + } +} + +static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode) +{ + rt_err_t result = RT_EOK; + TIM_HandleTypeDef *tim = RT_NULL; + + RT_ASSERT(timer != RT_NULL); + + tim = (TIM_HandleTypeDef *)timer->parent.user_data; + + /* set tim cnt */ + __HAL_TIM_SET_AUTORELOAD(tim, t); + + if (opmode == HWTIMER_MODE_ONESHOT) + { + /* set timer to single mode */ + tim->Instance->CR1 |= TIM_OPMODE_SINGLE; + } + + /* start timer */ + if (HAL_TIM_Base_Start_IT(tim) != HAL_OK) + { + LOG_E("TIM2 start failed"); + result = -RT_ERROR; + } + + return result; +} + +static void timer_stop(rt_hwtimer_t *timer) +{ + TIM_HandleTypeDef *tim = RT_NULL; + + RT_ASSERT(timer != RT_NULL); + + tim = (TIM_HandleTypeDef *)timer->parent.user_data; + + /* stop timer */ + HAL_TIM_Base_Stop_IT(tim); +} + +static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) +{ + TIM_HandleTypeDef *tim = RT_NULL; + rt_err_t result = RT_EOK; + + RT_ASSERT(timer != RT_NULL); + RT_ASSERT(arg != RT_NULL); + + tim = (TIM_HandleTypeDef *)timer->parent.user_data; + + switch (cmd) + { + case HWTIMER_CTRL_FREQ_SET: + { + rt_uint32_t freq; + rt_uint16_t val; + + /* set timer frequence */ + freq = *((rt_uint32_t *)arg); + +#if defined(SOC_SERIES_STM32F4) + if (tim->Instance == TIM9 || tim->Instance == TIM10 || tim->Instance == TIM11) +#elif defined(SOC_SERIES_STM32L4) + if (tim->Instance == TIM15 || tim->Instance == TIM16 || tim->Instance == TIM17) +#elif defined(SOC_SERIES_STM32F1) + if (0) +#endif + { +#if defined(SOC_SERIES_STM32L4) + val = HAL_RCC_GetPCLK2Freq() / freq; +#else + val = HAL_RCC_GetPCLK2Freq() * 2 / freq; +#endif + } + else + { + val = HAL_RCC_GetPCLK1Freq() * 2 / freq; + } + __HAL_TIM_SET_PRESCALER(tim, val - 1); + + /* Update frequency value */ + tim->Instance->EGR |= TIM_EVENTSOURCE_UPDATE; + } + break; + default: + { + result = -RT_ENOSYS; + } + break; + } + + return result; +} + +static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer) +{ + TIM_HandleTypeDef *tim = RT_NULL; + + RT_ASSERT(timer != RT_NULL); + + tim = (TIM_HandleTypeDef *)timer->parent.user_data; + + return tim->Instance->CNT; +} + +static const struct rt_hwtimer_info _info = TIM_DEV_INFO_CONFIG; + +static const struct rt_hwtimer_ops _ops = +{ + .init = timer_init, + .start = timer_start, + .stop = timer_stop, + .count_get = timer_counter_get, + .control = timer_ctrl, +}; + +#ifdef BSP_USING_TIM2 +void TIM2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM2_INDEX].tim_handle); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_TIM3 +void TIM3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM3_INDEX].tim_handle); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_TIM4 +void TIM4_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM4_INDEX].tim_handle); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_TIM5 +void TIM5_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM5_INDEX].tim_handle); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_TIM11 +void TIM1_TRG_COM_TIM11_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM11_INDEX].tim_handle); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_TIM13 +void TIM8_UP_TIM13_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM13_INDEX].tim_handle); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_TIM14 +void TIM8_TRG_COM_TIM14_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM14_INDEX].tim_handle); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_TIM15 +void TIM1_BRK_TIM15_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM15_INDEX].tim_handle); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_TIM16 +void TIM1_UP_TIM16_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM16_INDEX].tim_handle); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_TIM17 +void TIM1_TRG_COM_TIM17_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM17_INDEX].tim_handle); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ +#ifdef BSP_USING_TIM2 + if (htim->Instance == TIM2) + { + rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM2_INDEX].time_device); + } +#endif +#ifdef BSP_USING_TIM3 + if (htim->Instance == TIM3) + { + rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM3_INDEX].time_device); + } +#endif +#ifdef BSP_USING_TIM4 + if (htim->Instance == TIM4) + { + rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM4_INDEX].time_device); + } +#endif +#ifdef BSP_USING_TIM5 + if (htim->Instance == TIM5) + { + rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM5_INDEX].time_device); + } +#endif +#ifdef BSP_USING_TIM11 + if (htim->Instance == TIM11) + { + rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM11_INDEX].time_device); + } +#endif +#ifdef BSP_USING_TIM13 + if (htim->Instance == TIM13) + { + rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM13_INDEX].time_device); + } +#endif +#ifdef BSP_USING_TIM14 + if (htim->Instance == TIM14) + { + rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM14_INDEX].time_device); + } +#endif +#ifdef BSP_USING_TIM15 + if (htim->Instance == TIM15) + { + rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM15_INDEX].time_device); + } +#endif +#ifdef BSP_USING_TIM16 + if (htim->Instance == TIM16) + { + rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM16_INDEX].time_device); + } +#endif +#ifdef BSP_USING_TIM17 + if (htim->Instance == TIM17) + { + rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM17_INDEX].time_device); + } +#endif +} + +static int stm32_hwtimer_init(void) +{ + int i = 0; + int result = RT_EOK; + + for (i = 0; i < sizeof(stm32_hwtimer_obj) / sizeof(stm32_hwtimer_obj[0]); i++) + { + stm32_hwtimer_obj[i].time_device.info = &_info; + stm32_hwtimer_obj[i].time_device.ops = &_ops; + if (rt_device_hwtimer_register(&stm32_hwtimer_obj[i].time_device, stm32_hwtimer_obj[i].name, &stm32_hwtimer_obj[i].tim_handle) == RT_EOK) + { + LOG_D("%s register success", stm32_hwtimer_obj[i].name); + } + else + { + LOG_E("%s register failed", stm32_hwtimer_obj[i].name); + result = -RT_ERROR; + } + } + + return result; +} +INIT_BOARD_EXPORT(stm32_hwtimer_init); + +#endif /* RT_USING_HWTIMER */ +#endif /* BSP_USING_TIM */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_pwm.c b/bsp/stm32/libraries/HAL_Drivers/drv_pwm.c new file mode 100644 index 0000000000..5fa290c1bb --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drv_pwm.c @@ -0,0 +1,480 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-13 zylx first version + */ + +#include +#ifdef RT_USING_PWM +#include "drv_config.h" + +//#define DRV_DEBUG +#define LOG_TAG "drv.pwm" +#include + +#define MAX_PERIOD 65535 +#define MIN_PERIOD 3 +#define MIN_PULSE 2 + +extern void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + +enum +{ +#ifdef BSP_USING_PWM1 + PWM1_INDEX, +#endif +#ifdef BSP_USING_PWM2 + PWM2_INDEX, +#endif +#ifdef BSP_USING_PWM3 + PWM3_INDEX, +#endif +#ifdef BSP_USING_PWM4 + PWM4_INDEX, +#endif +#ifdef BSP_USING_PWM5 + PWM5_INDEX, +#endif +#ifdef BSP_USING_PWM6 + PWM6_INDEX, +#endif +#ifdef BSP_USING_PWM7 + PWM7_INDEX, +#endif +#ifdef BSP_USING_PWM8 + PWM8_INDEX, +#endif +#ifdef BSP_USING_PWM9 + PWM9_INDEX, +#endif +#ifdef BSP_USING_PWM10 + PWM10_INDEX, +#endif +#ifdef BSP_USING_PWM11 + PWM11_INDEX, +#endif +#ifdef BSP_USING_PWM12 + PWM12_INDEX, +#endif +#ifdef BSP_USING_PWM13 + PWM13_INDEX, +#endif +#ifdef BSP_USING_PWM14 + PWM14_INDEX, +#endif +#ifdef BSP_USING_PWM15 + PWM15_INDEX, +#endif +#ifdef BSP_USING_PWM16 + PWM16_INDEX, +#endif +#ifdef BSP_USING_PWM17 + PWM17_INDEX, +#endif +}; + +struct stm32_pwm +{ + struct rt_device_pwm pwm_device; + TIM_HandleTypeDef tim_handle; + rt_uint8_t channel; + char *name; +}; + +static struct stm32_pwm stm32_pwm_obj[] = +{ +#ifdef BSP_USING_PWM1 + PWM1_CONFIG, +#endif + +#ifdef BSP_USING_PWM2 + PWM2_CONFIG, +#endif + +#ifdef BSP_USING_PWM3 + PWM3_CONFIG, +#endif + +#ifdef BSP_USING_PWM4 + PWM4_CONFIG, +#endif + +#ifdef BSP_USING_PWM5 + PWM5_CONFIG, +#endif + +#ifdef BSP_USING_PWM6 + PWM6_CONFIG, +#endif + +#ifdef BSP_USING_PWM7 + PWM7_CONFIG, +#endif + +#ifdef BSP_USING_PWM8 + PWM8_CONFIG, +#endif + +#ifdef BSP_USING_PWM9 + PWM9_CONFIG, +#endif + +#ifdef BSP_USING_PWM10 + PWM10_CONFIG, +#endif + +#ifdef BSP_USING_PWM11 + PWM11_CONFIG, +#endif + +#ifdef BSP_USING_PWM12 + PWM12_CONFIG, +#endif + +#ifdef BSP_USING_PWM13 + PWM13_CONFIG, +#endif + +#ifdef BSP_USING_PWM14 + PWM14_CONFIG, +#endif + +#ifdef BSP_USING_PWM15 + PWM15_CONFIG, +#endif + +#ifdef BSP_USING_PWM16 + PWM16_CONFIG, +#endif + +#ifdef BSP_USING_PWM17 + PWM17_CONFIG, +#endif +}; + +static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg); +static struct rt_pwm_ops drv_ops = +{ + drv_pwm_control +}; + +static rt_err_t drv_pwm_enable(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration, rt_bool_t enable) +{ + /* Converts the channel number to the channel number of Hal library */ + rt_uint32_t channel = 0x04 * (configuration->channel - 1); + + if (!enable) + { + HAL_TIM_PWM_Stop(htim, channel); + } + else + { + HAL_TIM_PWM_Start(htim, channel); + } + + return RT_EOK; +} + +static rt_err_t drv_pwm_get(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration) +{ + /* Converts the channel number to the channel number of Hal library */ + rt_uint32_t channel = 0x04 * (configuration->channel - 1); + rt_uint64_t tim_clock; + +#if defined(SOC_SERIES_STM32F4) + if (htim->Instance == TIM9 || htim->Instance == TIM10 || htim->Instance == TIM11) +#elif defined(SOC_SERIES_STM32L4) + if (htim->Instance == TIM15 || htim->Instance == TIM16 || htim->Instance == TIM17) +#elif defined(SOC_SERIES_STM32F1) + if (0) +#endif + { + tim_clock = HAL_RCC_GetPCLK2Freq() * 2; + } + else + { +#if defined(SOC_SERIES_STM32L4) + tim_clock = HAL_RCC_GetPCLK1Freq(); +#else + tim_clock = HAL_RCC_GetPCLK1Freq() * 2; +#endif + } + + if (__HAL_TIM_GET_CLOCKDIVISION(htim) == TIM_CLOCKDIVISION_DIV2) + { + tim_clock = tim_clock / 2; + } + else if (__HAL_TIM_GET_CLOCKDIVISION(htim) == TIM_CLOCKDIVISION_DIV4) + { + tim_clock = tim_clock / 4; + } + + /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */ + tim_clock /= 1000000UL; + configuration->period = (__HAL_TIM_GET_AUTORELOAD(htim) + 1) * (htim->Instance->PSC + 1) * 1000UL / tim_clock; + configuration->pulse = (__HAL_TIM_GET_COMPARE(htim, channel) + 1) * (htim->Instance->PSC + 1) * 1000UL / tim_clock; + + return RT_EOK; +} + +static rt_err_t drv_pwm_set(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration) +{ + rt_uint32_t period, pulse; + rt_uint64_t tim_clock, psc; + /* Converts the channel number to the channel number of Hal library */ + rt_uint32_t channel = 0x04 * (configuration->channel - 1); + +#if defined(SOC_SERIES_STM32F4) + if (htim->Instance == TIM9 || htim->Instance == TIM10 || htim->Instance == TIM11) +#elif defined(SOC_SERIES_STM32L4) + if (htim->Instance == TIM15 || htim->Instance == TIM16 || htim->Instance == TIM17) +#elif defined(SOC_SERIES_STM32F1) + if (0) +#endif + { + tim_clock = HAL_RCC_GetPCLK2Freq() * 2; + } + else + { +#if defined(SOC_SERIES_STM32L4) + tim_clock = HAL_RCC_GetPCLK1Freq(); +#else + tim_clock = HAL_RCC_GetPCLK1Freq() * 2; +#endif + } + + /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */ + tim_clock /= 1000000UL; + period = (unsigned long long)configuration->period * tim_clock / 1000ULL ; + psc = period / MAX_PERIOD + 1; + period = period / psc; + __HAL_TIM_SET_PRESCALER(htim, psc - 1); + + if (period < MIN_PERIOD) + { + period = MIN_PERIOD; + } + __HAL_TIM_SET_AUTORELOAD(htim, period - 1); + + pulse = (unsigned long long)configuration->pulse * tim_clock / psc / 1000ULL; + if (pulse < MIN_PULSE) + { + pulse = MIN_PULSE; + } + else if (pulse > period) + { + pulse = period; + } + __HAL_TIM_SET_COMPARE(htim, channel, pulse - 1); + __HAL_TIM_SET_COUNTER(htim, 0); + + /* Update frequency value */ + HAL_TIM_GenerateEvent(htim, TIM_EVENTSOURCE_UPDATE); + + return RT_EOK; +} + +static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg) +{ + struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg; + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)device->parent.user_data; + + switch (cmd) + { + case PWM_CMD_ENABLE: + return drv_pwm_enable(htim, configuration, RT_TRUE); + case PWM_CMD_DISABLE: + return drv_pwm_enable(htim, configuration, RT_FALSE); + case PWM_CMD_SET: + return drv_pwm_set(htim, configuration); + case PWM_CMD_GET: + return drv_pwm_get(htim, configuration); + default: + return RT_EINVAL; + } +} + +static rt_err_t stm32_hw_pwm_init(struct stm32_pwm *device) +{ + rt_err_t result = RT_EOK; + TIM_HandleTypeDef *tim = RT_NULL; + TIM_OC_InitTypeDef oc_config = {0}; + TIM_MasterConfigTypeDef master_config = {0}; + TIM_ClockConfigTypeDef clock_config = {0}; + + RT_ASSERT(device != RT_NULL); + + tim = (TIM_HandleTypeDef *)&device->tim_handle; + + /* configure the timer to pwm mode */ + tim->Init.Prescaler = 0; + tim->Init.CounterMode = TIM_COUNTERMODE_UP; + tim->Init.Period = 0; + tim->Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; +#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) + tim->Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; +#endif + if (HAL_TIM_Base_Init(tim) != HAL_OK) + { + LOG_E("%s time base init failed", device->name); + result = -RT_ERROR; + goto __exit; + } + + clock_config.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(tim, &clock_config) != HAL_OK) + { + LOG_E("%s clock init failed", device->name); + result = -RT_ERROR; + goto __exit; + } + + if (HAL_TIM_PWM_Init(tim) != HAL_OK) + { + LOG_E("%s pwm init failed", device->name); + result = -RT_ERROR; + goto __exit; + } + + master_config.MasterOutputTrigger = TIM_TRGO_RESET; + master_config.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(tim, &master_config) != HAL_OK) + { + LOG_E("%s master config failed", device->name); + result = -RT_ERROR; + goto __exit; + } + + oc_config.OCMode = TIM_OCMODE_PWM1; + oc_config.Pulse = 0; + oc_config.OCPolarity = TIM_OCPOLARITY_HIGH; + oc_config.OCFastMode = TIM_OCFAST_DISABLE; + + /* config pwm channel */ + if (device->channel & 0x01) + { + if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_1) != HAL_OK) + { + LOG_E("%s channel1 config failed", device->name); + result = -RT_ERROR; + goto __exit; + } + } + + if (device->channel & 0x02) + { + if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_2) != HAL_OK) + { + LOG_E("%s channel2 config failed", device->name); + result = -RT_ERROR; + goto __exit; + } + } + + if (device->channel & 0x04) + { + if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_3) != HAL_OK) + { + LOG_E("%s channel3 config failed", device->name); + result = -RT_ERROR; + goto __exit; + } + } + + if (device->channel & 0x08) + { + if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_4) != HAL_OK) + { + LOG_E("%s channel4 config failed", device->name); + result = -RT_ERROR; + goto __exit; + } + } + + /* pwm pin configuration */ + HAL_TIM_MspPostInit(tim); + + /* enable update request source */ + __HAL_TIM_URS_ENABLE(tim); + +__exit: + return result; +} + +static void pwm_get_channel(void) +{ +#ifdef BSP_USING_PWM2_CH4 + stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 3; +#endif +#ifdef BSP_USING_PWM3_CH1 + stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 0; +#endif +#ifdef BSP_USING_PWM3_CH2 + stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 1; +#endif +#ifdef BSP_USING_PWM3_CH3 + stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 2; +#endif +#ifdef BSP_USING_PWM3_CH4 + stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 3; +#endif +#ifdef BSP_USING_PWM4_CH2 + stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 1; +#endif +#ifdef BSP_USING_PWM4_CH3 + stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 2; +#endif +#ifdef BSP_USING_PWM5_CH1 + stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 1; +#endif +#ifdef BSP_USING_PWM5_CH2 + stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 2; +#endif +#ifdef BSP_USING_PWM5_CH3 + stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 3; +#endif +} + +static int stm32_pwm_init(void) +{ + int i = 0; + int result = RT_EOK; + + pwm_get_channel(); + + for (i = 0; i < sizeof(stm32_pwm_obj) / sizeof(stm32_pwm_obj[0]); i++) + { + /* pwm init */ + if (stm32_hw_pwm_init(&stm32_pwm_obj[i]) != RT_EOK) + { + LOG_E("%s init failed", stm32_pwm_obj[i].name); + result = -RT_ERROR; + goto __exit; + } + else + { + LOG_D("%s init success", stm32_pwm_obj[i].name); + + /* register pwm device */ + if (rt_device_pwm_register(rt_calloc(1, sizeof(struct rt_device_pwm)), stm32_pwm_obj[i].name, &drv_ops, &stm32_pwm_obj[i].tim_handle) == RT_EOK) + { + + LOG_D("%s register success", stm32_pwm_obj[i].name); + } + else + { + LOG_E("%s register failed", stm32_pwm_obj[i].name); + result = -RT_ERROR; + } + } + } + +__exit: + return result; +} +INIT_DEVICE_EXPORT(stm32_pwm_init); +#endif /* RT_USING_PWM */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_sdio.c b/bsp/stm32/libraries/HAL_Drivers/drv_sdio.c new file mode 100644 index 0000000000..f2d6867343 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drv_sdio.c @@ -0,0 +1,846 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-06-22 tyx first + * 2018-12-12 balanceTWK change to new framework + */ + +#include "board.h" +#include "drv_sdio.h" +#include "drv_config.h" + +#ifdef BSP_USING_SDIO + +//#define DRV_DEBUG +#define LOG_TAG "drv.sdio" +#include + +static struct stm32_sdio_config sdio_config = SDIO_BUS_CONFIG; +static struct stm32_sdio_class sdio_obj; +static struct rt_mmcsd_host *host; + +#define SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS (100000) + +#define RTHW_SDIO_LOCK(_sdio) rt_mutex_take(&_sdio->mutex, RT_WAITING_FOREVER) +#define RTHW_SDIO_UNLOCK(_sdio) rt_mutex_release(&_sdio->mutex); + +struct sdio_pkg +{ + struct rt_mmcsd_cmd *cmd; + void *buff; + rt_uint32_t flag; +}; + +struct rthw_sdio +{ + struct rt_mmcsd_host *host; + struct stm32_sdio_des sdio_des; + struct rt_event event; + struct rt_mutex mutex; + struct sdio_pkg *pkg; +}; + +ALIGN(SDIO_ALIGN_LEN) +static rt_uint8_t cache_buf[SDIO_BUFF_SIZE]; + +static rt_uint32_t stm32_sdio_clk_get(struct stm32_sdio *hw_sdio) +{ + return SDIO_CLOCK_FREQ; +} + +/** + * @brief This function get order from sdio. + * @param data + * @retval sdio order + */ +static int get_order(rt_uint32_t data) +{ + int order = 0; + + switch (data) + { + case 1: + order = 0; + break; + case 2: + order = 1; + break; + case 4: + order = 2; + break; + case 8: + order = 3; + break; + case 16: + order = 4; + break; + case 32: + order = 5; + break; + case 64: + order = 6; + break; + case 128: + order = 7; + break; + case 256: + order = 8; + break; + case 512: + order = 9; + break; + case 1024: + order = 10; + break; + case 2048: + order = 11; + break; + case 4096: + order = 12; + break; + case 8192: + order = 13; + break; + case 16384: + order = 14; + break; + default : + order = 0; + break; + } + + return order; +} + +/** + * @brief This function wait sdio completed. + * @param sdio rthw_sdio + * @retval None + */ +static void rthw_sdio_wait_completed(struct rthw_sdio *sdio) +{ + rt_uint32_t status; + struct rt_mmcsd_cmd *cmd = sdio->pkg->cmd; + struct rt_mmcsd_data *data = cmd->data; + struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio; + + if (rt_event_recv(&sdio->event, 0xffffffff, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, + rt_tick_from_millisecond(5000), &status) != RT_EOK) + { + LOG_E("wait completed timeout"); + cmd->err = -RT_ETIMEOUT; + return; + } + + if (sdio->pkg == RT_NULL) + { + return; + } + + cmd->resp[0] = hw_sdio->resp1; + cmd->resp[1] = hw_sdio->resp2; + cmd->resp[2] = hw_sdio->resp3; + cmd->resp[3] = hw_sdio->resp4; + + if (status & HW_SDIO_ERRORS) + { + if ((status & HW_SDIO_IT_CCRCFAIL) && (resp_type(cmd) & (RESP_R3 | RESP_R4))) + { + cmd->err = RT_EOK; + } + else + { + cmd->err = -RT_ERROR; + } + + if (status & HW_SDIO_IT_CTIMEOUT) + { + cmd->err = -RT_ETIMEOUT; + } + + if (status & HW_SDIO_IT_DCRCFAIL) + { + data->err = -RT_ERROR; + } + + if (status & HW_SDIO_IT_DTIMEOUT) + { + data->err = -RT_ETIMEOUT; + } + + if (cmd->err == RT_EOK) + { + LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); + } + else + { + LOG_D("err:0x%08x, %s%s%s%s%s%s%s cmd:%d arg:0x%08x rw:%c len:%d blksize:%d", + status, + status & HW_SDIO_IT_CCRCFAIL ? "CCRCFAIL " : "", + status & HW_SDIO_IT_DCRCFAIL ? "DCRCFAIL " : "", + status & HW_SDIO_IT_CTIMEOUT ? "CTIMEOUT " : "", + status & HW_SDIO_IT_DTIMEOUT ? "DTIMEOUT " : "", + status & HW_SDIO_IT_TXUNDERR ? "TXUNDERR " : "", + status & HW_SDIO_IT_RXOVERR ? "RXOVERR " : "", + status == 0 ? "NULL" : "", + cmd->cmd_code, + cmd->arg, + data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-', + data ? data->blks * data->blksize : 0, + data ? data->blksize : 0 + ); + } + } + else +{ + cmd->err = RT_EOK; + LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); + } +} + +/** + * @brief This function transfer data by dma. + * @param sdio rthw_sdio + * @param pkg sdio package + * @retval None + */ +static void rthw_sdio_transfer_by_dma(struct rthw_sdio *sdio, struct sdio_pkg *pkg) +{ + struct rt_mmcsd_data *data; + int size; + void *buff; + struct stm32_sdio *hw_sdio; + + if ((RT_NULL == pkg) || (RT_NULL == sdio)) + { + LOG_E("rthw_sdio_transfer_by_dma invalid args"); + return; + } + + data = pkg->cmd->data; + if (RT_NULL == data) + { + LOG_E("rthw_sdio_transfer_by_dma invalid args"); + return; + } + + buff = pkg->buff; + if (RT_NULL == buff) + { + LOG_E("rthw_sdio_transfer_by_dma invalid args"); + return; + } + hw_sdio = sdio->sdio_des.hw_sdio; + size = data->blks * data->blksize; + + if (data->flags & DATA_DIR_WRITE) + { + sdio->sdio_des.txconfig((rt_uint32_t *)buff, (rt_uint32_t *)&hw_sdio->fifo, size); + hw_sdio->dctrl |= HW_SDIO_DMA_ENABLE; + } + else if (data->flags & DATA_DIR_READ) + { + sdio->sdio_des.rxconfig((rt_uint32_t *)&hw_sdio->fifo, (rt_uint32_t *)buff, size); + hw_sdio->dctrl |= HW_SDIO_DMA_ENABLE | HW_SDIO_DPSM_ENABLE; + } +} + +/** + * @brief This function send command. + * @param sdio rthw_sdio + * @param pkg sdio package + * @retval None + */ +static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg) +{ + struct rt_mmcsd_cmd *cmd = pkg->cmd; + struct rt_mmcsd_data *data = cmd->data; + struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio; + rt_uint32_t reg_cmd; + + /* save pkg */ + sdio->pkg = pkg; + + LOG_D("CMD:%d ARG:0x%08x RES:%s%s%s%s%s%s%s%s%s rw:%c len:%d blksize:%d", + cmd->cmd_code, + cmd->arg, + resp_type(cmd) == RESP_NONE ? "NONE" : "", + resp_type(cmd) == RESP_R1 ? "R1" : "", + resp_type(cmd) == RESP_R1B ? "R1B" : "", + resp_type(cmd) == RESP_R2 ? "R2" : "", + resp_type(cmd) == RESP_R3 ? "R3" : "", + resp_type(cmd) == RESP_R4 ? "R4" : "", + resp_type(cmd) == RESP_R5 ? "R5" : "", + resp_type(cmd) == RESP_R6 ? "R6" : "", + resp_type(cmd) == RESP_R7 ? "R7" : "", + data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-', + data ? data->blks * data->blksize : 0, + data ? data->blksize : 0 + ); + + /* config cmd reg */ + reg_cmd = cmd->cmd_code | HW_SDIO_CPSM_ENABLE; + if (resp_type(cmd) == RESP_NONE) + reg_cmd |= HW_SDIO_RESPONSE_NO; + else if (resp_type(cmd) == RESP_R2) + reg_cmd |= HW_SDIO_RESPONSE_LONG; + else + reg_cmd |= HW_SDIO_RESPONSE_SHORT; + + /* config data reg */ + if (data != RT_NULL) +{ + rt_uint32_t dir = 0; + rt_uint32_t size = data->blks * data->blksize; + int order; + + hw_sdio->dctrl = 0; + hw_sdio->dtimer = HW_SDIO_DATATIMEOUT; + hw_sdio->dlen = size; + order = get_order(data->blksize); + dir = (data->flags & DATA_DIR_READ) ? HW_SDIO_TO_HOST : 0; + hw_sdio->dctrl = HW_SDIO_IO_ENABLE | (order << 4) | dir; + } + + /* transfer config */ + if (data != RT_NULL) + { + rthw_sdio_transfer_by_dma(sdio, pkg); + } + + /* open irq */ + hw_sdio->mask |= HW_SDIO_IT_CMDSENT | HW_SDIO_IT_CMDREND | HW_SDIO_ERRORS; + if (data != RT_NULL) + { + hw_sdio->mask |= HW_SDIO_IT_DATAEND; + } + + /* send cmd */ + hw_sdio->arg = cmd->arg; + hw_sdio->cmd = reg_cmd; + + /* wait completed */ + rthw_sdio_wait_completed(sdio); + + /* Waiting for data to be sent to completion */ + if (data != RT_NULL) + { + volatile rt_uint32_t count = SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS; + + while (count && (hw_sdio->sta & (HW_SDIO_IT_TXACT | HW_SDIO_IT_RXACT))) + { + count--; + } + + if ((count == 0) || (hw_sdio->sta & HW_SDIO_ERRORS)) + { + cmd->err = -RT_ERROR; + } + } + + /* close irq, keep sdio irq */ + hw_sdio->mask = hw_sdio->mask & HW_SDIO_IT_SDIOIT ? HW_SDIO_IT_SDIOIT : 0x00; + + /* clear pkg */ + sdio->pkg = RT_NULL; +} + +/** + * @brief This function send sdio request. + * @param sdio rthw_sdio + * @param req request + * @retval None + */ +static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) +{ + struct sdio_pkg pkg; + struct rthw_sdio *sdio = host->private_data; + struct rt_mmcsd_data *data; + + RTHW_SDIO_LOCK(sdio); + + if (req->cmd != RT_NULL) + { + memset(&pkg, 0, sizeof(pkg)); + data = req->cmd->data; + pkg.cmd = req->cmd; + + if (data != RT_NULL) + { + rt_uint32_t size = data->blks * data->blksize; + + RT_ASSERT(size <= SDIO_BUFF_SIZE); + + pkg.buff = data->buf; + if ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1)) + { + pkg.buff = cache_buf; + if (data->flags & DATA_DIR_WRITE) + { + memcpy(cache_buf, data->buf, size); + } + } + } + + rthw_sdio_send_command(sdio, &pkg); + + if ((data != RT_NULL) && (data->flags & DATA_DIR_READ) && ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1))) + { + memcpy(data->buf, cache_buf, data->blksize * data->blks); + } + } + + if (req->stop != RT_NULL) + { + memset(&pkg, 0, sizeof(pkg)); + pkg.cmd = req->stop; + rthw_sdio_send_command(sdio, &pkg); + } + + RTHW_SDIO_UNLOCK(sdio); + + mmcsd_req_complete(sdio->host); +} + +/** + * @brief This function config sdio. + * @param host rt_mmcsd_host + * @param io_cfg rt_mmcsd_io_cfg + * @retval None + */ +static void rthw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) +{ + rt_uint32_t clkcr, div, clk_src; + rt_uint32_t clk = io_cfg->clock; + struct rthw_sdio *sdio = host->private_data; + struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio; + + clk_src = sdio->sdio_des.clk_get(sdio->sdio_des.hw_sdio); + if (clk_src < 400 * 1000) + { + LOG_E("The clock rate is too low! rata:%d", clk_src); + return; + } + + if (clk > host->freq_max) clk = host->freq_max; + + if (clk > clk_src) + { + LOG_W("Setting rate is greater than clock source rate."); + clk = clk_src; + } + + LOG_D("clk:%d width:%s%s%s power:%s%s%s", + clk, + io_cfg->bus_width == MMCSD_BUS_WIDTH_8 ? "8" : "", + io_cfg->bus_width == MMCSD_BUS_WIDTH_4 ? "4" : "", + io_cfg->bus_width == MMCSD_BUS_WIDTH_1 ? "1" : "", + io_cfg->power_mode == MMCSD_POWER_OFF ? "OFF" : "", + io_cfg->power_mode == MMCSD_POWER_UP ? "UP" : "", + io_cfg->power_mode == MMCSD_POWER_ON ? "ON" : "" + ); + + RTHW_SDIO_LOCK(sdio); + + div = clk_src / clk; + if ((clk == 0) || (div == 0)) + { + clkcr = 0; + } + else + { + if (div < 2) + { + div = 2; + } + else if (div > 0xFF) + { + div = 0xFF; + } + div -= 2; + clkcr = div | HW_SDIO_CLK_ENABLE; + } + + if (io_cfg->bus_width == MMCSD_BUS_WIDTH_8) + { + clkcr |= HW_SDIO_BUSWIDE_8B; + } + else if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4) + { + clkcr |= HW_SDIO_BUSWIDE_4B; + } + else + { + clkcr |= HW_SDIO_BUSWIDE_1B; + } + + hw_sdio->clkcr = clkcr; + + switch (io_cfg->power_mode) + { + case MMCSD_POWER_OFF: + hw_sdio->power = HW_SDIO_POWER_OFF; + break; + case MMCSD_POWER_UP: + hw_sdio->power = HW_SDIO_POWER_UP; + break; + case MMCSD_POWER_ON: + hw_sdio->power = HW_SDIO_POWER_ON; + break; + default: + LOG_W("unknown power_mode %d", io_cfg->power_mode); + break; + } + + RTHW_SDIO_UNLOCK(sdio); +} + +/** + * @brief This function update sdio interrupt. + * @param host rt_mmcsd_host + * @param enable + * @retval None + */ +void rthw_sdio_irq_update(struct rt_mmcsd_host *host, rt_int32_t enable) +{ + struct rthw_sdio *sdio = host->private_data; + struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio; + + if (enable) + { + LOG_D("enable sdio irq"); + hw_sdio->mask |= HW_SDIO_IT_SDIOIT; + } + else + { + LOG_D("disable sdio irq"); + hw_sdio->mask &= ~HW_SDIO_IT_SDIOIT; + } +} + +/** + * @brief This function delect sdcard. + * @param host rt_mmcsd_host + * @retval 0x01 + */ +static rt_int32_t rthw_sd_delect(struct rt_mmcsd_host *host) +{ + LOG_D("try to detect device"); + return 0x01; +} + +/** + * @brief This function interrupt process function. + * @param host rt_mmcsd_host + * @retval None + */ +void rthw_sdio_irq_process(struct rt_mmcsd_host *host) +{ + int complete = 0; + struct rthw_sdio *sdio = host->private_data; + struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio; + rt_uint32_t intstatus = hw_sdio->sta; + + if (intstatus & HW_SDIO_ERRORS) + { + hw_sdio->icr = HW_SDIO_ERRORS; + complete = 1; + } + else + { + if (intstatus & HW_SDIO_IT_CMDREND) + { + hw_sdio->icr = HW_SDIO_IT_CMDREND; + + if (sdio->pkg != RT_NULL) + { + if (!sdio->pkg->cmd->data) + { + complete = 1; + } + else if ((sdio->pkg->cmd->data->flags & DATA_DIR_WRITE)) + { + hw_sdio->dctrl |= HW_SDIO_DPSM_ENABLE; + } + } + } + + if (intstatus & HW_SDIO_IT_CMDSENT) + { + hw_sdio->icr = HW_SDIO_IT_CMDSENT; + + if (resp_type(sdio->pkg->cmd) == RESP_NONE) + { + complete = 1; + } + } + + if (intstatus & HW_SDIO_IT_DATAEND) + { + hw_sdio->icr = HW_SDIO_IT_DATAEND; + complete = 1; + } + } + + if ((intstatus & HW_SDIO_IT_SDIOIT) && (hw_sdio->mask & HW_SDIO_IT_SDIOIT)) + { + hw_sdio->icr = HW_SDIO_IT_SDIOIT; + sdio_irq_wakeup(host); + } + + if (complete) + { + hw_sdio->mask &= ~HW_SDIO_ERRORS; + rt_event_send(&sdio->event, intstatus); + } +} + +static const struct rt_mmcsd_host_ops ops = +{ + rthw_sdio_request, + rthw_sdio_iocfg, + rthw_sd_delect, + rthw_sdio_irq_update, +}; + +/** + * @brief This function create mmcsd host. + * @param sdio_des stm32_sdio_des + * @retval rt_mmcsd_host + */ +struct rt_mmcsd_host *sdio_host_create(struct stm32_sdio_des *sdio_des) +{ + struct rt_mmcsd_host *host; + struct rthw_sdio *sdio = RT_NULL; + + if ((sdio_des == RT_NULL) || (sdio_des->txconfig == RT_NULL) || (sdio_des->rxconfig == RT_NULL)) + { + LOG_E("L:%d F:%s %s %s %s", + (sdio_des == RT_NULL ? "sdio_des is NULL" : ""), + (sdio_des ? (sdio_des->txconfig ? "txconfig is NULL" : "") : ""), + (sdio_des ? (sdio_des->rxconfig ? "rxconfig is NULL" : "") : "") + ); + return RT_NULL; + } + + sdio = rt_malloc(sizeof(struct rthw_sdio)); + if (sdio == RT_NULL) + { + LOG_E("L:%d F:%s malloc rthw_sdio fail"); + return RT_NULL; + } + rt_memset(sdio, 0, sizeof(struct rthw_sdio)); + + host = mmcsd_alloc_host(); + if (host == RT_NULL) + { + LOG_E("L:%d F:%s mmcsd alloc host fail"); + rt_free(sdio); + return RT_NULL; + } + + rt_memcpy(&sdio->sdio_des, sdio_des, sizeof(struct stm32_sdio_des)); + sdio->sdio_des.hw_sdio = (sdio_des->hw_sdio == RT_NULL ? (struct stm32_sdio *)SDIO_BASE_ADDRESS : sdio_des->hw_sdio); + sdio->sdio_des.clk_get = (sdio_des->clk_get == RT_NULL ? stm32_sdio_clk_get : sdio_des->clk_get); + + rt_event_init(&sdio->event, "sdio", RT_IPC_FLAG_FIFO); + rt_mutex_init(&sdio->mutex, "sdio", RT_IPC_FLAG_FIFO); + + /* set host defautl attributes */ + host->ops = &ops; + host->freq_min = 400 * 1000; + host->freq_max = SDIO_MAX_FREQ; + host->valid_ocr = 0X00FFFF80;/* The voltage range supported is 1.65v-3.6v */ +#ifndef SDIO_USING_1_BIT + host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ; +#else + host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ; +#endif + host->max_seg_size = SDIO_BUFF_SIZE; + host->max_dma_segs = 1; + host->max_blk_size = 512; + host->max_blk_count = 512; + + /* link up host and sdio */ + sdio->host = host; + host->private_data = sdio; + + rthw_sdio_irq_update(host, 1); + + /* ready to change */ + mmcsd_change(host); + + return host; +} + +/** + * @brief This function configures the DMATX. + * @param BufferSRC: pointer to the source buffer + * @param BufferSize: buffer size + * @retval None + */ +void SD_LowLevel_DMA_TxConfig(uint32_t *src, uint32_t *dst, uint32_t BufferSize) +{ +#if defined(SOC_SERIES_STM32F1) + static uint32_t size = 0; + size += BufferSize * 4; + sdio_obj.cfg = &sdio_config; + sdio_obj.dma.handle_tx.Instance = sdio_config.dma_tx.Instance; + sdio_obj.dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + sdio_obj.dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + sdio_obj.dma.handle_tx.Init.MemInc = DMA_MINC_ENABLE; + sdio_obj.dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + sdio_obj.dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE; + sdio_obj.dma.handle_tx.Init.Priority = DMA_PRIORITY_MEDIUM; + /* DMA_PFCTRL */ + HAL_DMA_DeInit(&sdio_obj.dma.handle_tx); + HAL_DMA_Init(&sdio_obj.dma.handle_tx); + + HAL_DMA_Start(&sdio_obj.dma.handle_tx, (uint32_t)src, (uint32_t)dst, BufferSize); +#else + static uint32_t size = 0; + size += BufferSize * 4; + sdio_obj.cfg = &sdio_config; + sdio_obj.dma.handle_tx.Instance = sdio_config.dma_tx.Instance; + sdio_obj.dma.handle_tx.Init.Channel = sdio_config.dma_tx.channel; + sdio_obj.dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + sdio_obj.dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE; + sdio_obj.dma.handle_tx.Init.MemInc = DMA_MINC_ENABLE; + sdio_obj.dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + sdio_obj.dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + sdio_obj.dma.handle_tx.Init.Mode = DMA_PFCTRL; + sdio_obj.dma.handle_tx.Init.Priority = DMA_PRIORITY_MEDIUM; + sdio_obj.dma.handle_tx.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + sdio_obj.dma.handle_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + sdio_obj.dma.handle_tx.Init.MemBurst = DMA_MBURST_INC4; + sdio_obj.dma.handle_tx.Init.PeriphBurst = DMA_PBURST_INC4; + /* DMA_PFCTRL */ + HAL_DMA_DeInit(&sdio_obj.dma.handle_tx); + HAL_DMA_Init(&sdio_obj.dma.handle_tx); + + HAL_DMA_Start(&sdio_obj.dma.handle_tx, (uint32_t)src, (uint32_t)dst, BufferSize); +#endif +} + +/** + * @brief This function configures the DMARX. + * @param BufferDST: pointer to the destination buffer + * @param BufferSize: buffer size + * @retval None + */ +void SD_LowLevel_DMA_RxConfig(uint32_t *src, uint32_t *dst, uint32_t BufferSize) +{ +#if defined(SOC_SERIES_STM32F1) + sdio_obj.cfg = &sdio_config; + sdio_obj.dma.handle_tx.Instance = sdio_config.dma_tx.Instance; + sdio_obj.dma.handle_tx.Init.Direction = DMA_PERIPH_TO_MEMORY; + sdio_obj.dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + sdio_obj.dma.handle_tx.Init.MemInc = DMA_MINC_ENABLE; + sdio_obj.dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + sdio_obj.dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE; + sdio_obj.dma.handle_tx.Init.Priority = DMA_PRIORITY_MEDIUM; + + HAL_DMA_DeInit(&sdio_obj.dma.handle_tx); + HAL_DMA_Init(&sdio_obj.dma.handle_tx); + + HAL_DMA_Start(&sdio_obj.dma.handle_tx, (uint32_t)src, (uint32_t)dst, BufferSize); +#else + sdio_obj.cfg = &sdio_config; + sdio_obj.dma.handle_tx.Instance = sdio_config.dma_tx.Instance; + sdio_obj.dma.handle_tx.Init.Channel = sdio_config.dma_tx.channel; + sdio_obj.dma.handle_tx.Init.Direction = DMA_PERIPH_TO_MEMORY; + sdio_obj.dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE; + sdio_obj.dma.handle_tx.Init.MemInc = DMA_MINC_ENABLE; + sdio_obj.dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + sdio_obj.dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + sdio_obj.dma.handle_tx.Init.Mode = DMA_PFCTRL; + sdio_obj.dma.handle_tx.Init.Priority = DMA_PRIORITY_MEDIUM; + sdio_obj.dma.handle_tx.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + sdio_obj.dma.handle_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + sdio_obj.dma.handle_tx.Init.MemBurst = DMA_MBURST_INC4; + sdio_obj.dma.handle_tx.Init.PeriphBurst = DMA_PBURST_INC4; + + HAL_DMA_DeInit(&sdio_obj.dma.handle_tx); + HAL_DMA_Init(&sdio_obj.dma.handle_tx); + + HAL_DMA_Start(&sdio_obj.dma.handle_tx, (uint32_t)src, (uint32_t)dst, BufferSize); +#endif + +} + +/** + * @brief This function get stm32 sdio clock. + * @param hw_sdio: stm32_sdio + * @retval PCLK2Freq + */ +static rt_uint32_t stm32_sdio_clock_get(struct stm32_sdio *hw_sdio) +{ + return HAL_RCC_GetPCLK2Freq(); +} + +static rt_err_t DMA_TxConfig(rt_uint32_t *src, rt_uint32_t *dst, int Size) +{ + SD_LowLevel_DMA_TxConfig((uint32_t *)src, (uint32_t *)dst, Size / 4); + return RT_EOK; +} + +static rt_err_t DMA_RxConfig(rt_uint32_t *src, rt_uint32_t *dst, int Size) +{ + SD_LowLevel_DMA_RxConfig((uint32_t *)src, (uint32_t *)dst, Size / 4); + return RT_EOK; +} + +void SDIO_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + /* Process All SDIO Interrupt Sources */ + rthw_sdio_irq_process(host); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +int rt_hw_sdio_init(void) +{ + struct stm32_sdio_des sdio_des; + SD_HandleTypeDef hsd; + hsd.Instance = SDIO; + { + rt_uint32_t tmpreg = 0x00U; +#if defined(SOC_SERIES_STM32F1) + /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ + SET_BIT(RCC->AHBENR, sdio_config.dma_rx.dma_rcc); + tmpreg = READ_BIT(RCC->AHBENR, sdio_config.dma_rx.dma_rcc); +#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L4) + SET_BIT(RCC->AHB1ENR, sdio_config.dma_rx.dma_rcc); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1ENR, sdio_config.dma_rx.dma_rcc); +#endif + UNUSED(tmpreg); /* To avoid compiler warnings */ + } + HAL_NVIC_SetPriority(SDIO_IRQn, 2, 0); + HAL_NVIC_EnableIRQ(SDIO_IRQn); + HAL_SD_MspInit(&hsd); + + sdio_des.clk_get = stm32_sdio_clock_get; + sdio_des.hw_sdio = (struct stm32_sdio *)SDIO; + sdio_des.rxconfig = DMA_RxConfig; + sdio_des.txconfig = DMA_TxConfig; + + host = sdio_host_create(&sdio_des); + if (host == RT_NULL) + { + LOG_E("host create fail"); + return -1; + } + + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_sdio_init); + +#endif diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_sdio.h b/bsp/stm32/libraries/HAL_Drivers/drv_sdio.h new file mode 100644 index 0000000000..f0b3cdb347 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drv_sdio.h @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-13 BalanceTWK first version + */ + +#ifndef _DRV_SDIO_H +#define _DRV_SDIO_H +#include +#include "rtdevice.h" +#include +#include +#include "drv_dma.h" +#include +#include +#include + +#define SDIO_BUFF_SIZE 4096 +#define SDIO_MAX_FREQ 2000000 +#define SDIO_ALIGN_LEN 32 + +#ifndef SDIO_BASE_ADDRESS +#define SDIO_BASE_ADDRESS (0x40012800U) +#endif + +#ifndef SDIO_CLOCK_FREQ +#define SDIO_CLOCK_FREQ (48U * 1000 * 1000) +#endif + +#ifndef SDIO_BUFF_SIZE +#define SDIO_BUFF_SIZE (4096) +#endif + +#ifndef SDIO_ALIGN_LEN +#define SDIO_ALIGN_LEN (32) +#endif + +#ifndef SDIO_MAX_FREQ +#define SDIO_MAX_FREQ (24 * 1000 * 1000) +#endif + +#define HW_SDIO_IT_CCRCFAIL (0x01U << 0) +#define HW_SDIO_IT_DCRCFAIL (0x01U << 1) +#define HW_SDIO_IT_CTIMEOUT (0x01U << 2) +#define HW_SDIO_IT_DTIMEOUT (0x01U << 3) +#define HW_SDIO_IT_TXUNDERR (0x01U << 4) +#define HW_SDIO_IT_RXOVERR (0x01U << 5) +#define HW_SDIO_IT_CMDREND (0x01U << 6) +#define HW_SDIO_IT_CMDSENT (0x01U << 7) +#define HW_SDIO_IT_DATAEND (0x01U << 8) +#define HW_SDIO_IT_STBITERR (0x01U << 9) +#define HW_SDIO_IT_DBCKEND (0x01U << 10) +#define HW_SDIO_IT_CMDACT (0x01U << 11) +#define HW_SDIO_IT_TXACT (0x01U << 12) +#define HW_SDIO_IT_RXACT (0x01U << 13) +#define HW_SDIO_IT_TXFIFOHE (0x01U << 14) +#define HW_SDIO_IT_RXFIFOHF (0x01U << 15) +#define HW_SDIO_IT_TXFIFOF (0x01U << 16) +#define HW_SDIO_IT_RXFIFOF (0x01U << 17) +#define HW_SDIO_IT_TXFIFOE (0x01U << 18) +#define HW_SDIO_IT_RXFIFOE (0x01U << 19) +#define HW_SDIO_IT_TXDAVL (0x01U << 20) +#define HW_SDIO_IT_RXDAVL (0x01U << 21) +#define HW_SDIO_IT_SDIOIT (0x01U << 22) + +#define HW_SDIO_ERRORS \ + (HW_SDIO_IT_CCRCFAIL | HW_SDIO_IT_CTIMEOUT | \ + HW_SDIO_IT_DCRCFAIL | HW_SDIO_IT_DTIMEOUT | \ + HW_SDIO_IT_RXOVERR | HW_SDIO_IT_TXUNDERR) + +#define HW_SDIO_POWER_OFF (0x00U) +#define HW_SDIO_POWER_UP (0x02U) +#define HW_SDIO_POWER_ON (0x03U) + +#define HW_SDIO_FLOW_ENABLE (0x01U << 14) +#define HW_SDIO_BUSWIDE_1B (0x00U << 11) +#define HW_SDIO_BUSWIDE_4B (0x01U << 11) +#define HW_SDIO_BUSWIDE_8B (0x02U << 11) +#define HW_SDIO_BYPASS_ENABLE (0x01U << 10) +#define HW_SDIO_IDLE_ENABLE (0x01U << 9) +#define HW_SDIO_CLK_ENABLE (0x01U << 8) + +#define HW_SDIO_SUSPEND_CMD (0x01U << 11) +#define HW_SDIO_CPSM_ENABLE (0x01U << 10) +#define HW_SDIO_WAIT_END (0x01U << 9) +#define HW_SDIO_WAIT_INT (0x01U << 8) +#define HW_SDIO_RESPONSE_NO (0x00U << 6) +#define HW_SDIO_RESPONSE_SHORT (0x01U << 6) +#define HW_SDIO_RESPONSE_LONG (0x03U << 6) + +#define HW_SDIO_DATA_LEN_MASK (0x01FFFFFFU) + +#define HW_SDIO_IO_ENABLE (0x01U << 11) +#define HW_SDIO_RWMOD_CK (0x01U << 10) +#define HW_SDIO_RWSTOP_ENABLE (0x01U << 9) +#define HW_SDIO_RWSTART_ENABLE (0x01U << 8) +#define HW_SDIO_DBLOCKSIZE_1 (0x00U << 4) +#define HW_SDIO_DBLOCKSIZE_2 (0x01U << 4) +#define HW_SDIO_DBLOCKSIZE_4 (0x02U << 4) +#define HW_SDIO_DBLOCKSIZE_8 (0x03U << 4) +#define HW_SDIO_DBLOCKSIZE_16 (0x04U << 4) +#define HW_SDIO_DBLOCKSIZE_32 (0x05U << 4) +#define HW_SDIO_DBLOCKSIZE_64 (0x06U << 4) +#define HW_SDIO_DBLOCKSIZE_128 (0x07U << 4) +#define HW_SDIO_DBLOCKSIZE_256 (0x08U << 4) +#define HW_SDIO_DBLOCKSIZE_512 (0x09U << 4) +#define HW_SDIO_DBLOCKSIZE_1024 (0x0AU << 4) +#define HW_SDIO_DBLOCKSIZE_2048 (0x0BU << 4) +#define HW_SDIO_DBLOCKSIZE_4096 (0x0CU << 4) +#define HW_SDIO_DBLOCKSIZE_8192 (0x0DU << 4) +#define HW_SDIO_DBLOCKSIZE_16384 (0x0EU << 4) +#define HW_SDIO_DMA_ENABLE (0x01U << 3) +#define HW_SDIO_STREAM_ENABLE (0x01U << 2) +#define HW_SDIO_TO_HOST (0x01U << 1) +#define HW_SDIO_DPSM_ENABLE (0x01U << 0) + +#define HW_SDIO_DATATIMEOUT (0xF0000000U) + +struct stm32_sdio +{ + volatile rt_uint32_t power; + volatile rt_uint32_t clkcr; + volatile rt_uint32_t arg; + volatile rt_uint32_t cmd; + volatile rt_uint32_t respcmd; + volatile rt_uint32_t resp1; + volatile rt_uint32_t resp2; + volatile rt_uint32_t resp3; + volatile rt_uint32_t resp4; + volatile rt_uint32_t dtimer; + volatile rt_uint32_t dlen; + volatile rt_uint32_t dctrl; + volatile rt_uint32_t dcount; + volatile rt_uint32_t sta; + volatile rt_uint32_t icr; + volatile rt_uint32_t mask; + volatile rt_uint32_t reserved0[2]; + volatile rt_uint32_t fifocnt; + volatile rt_uint32_t reserved1[13]; + volatile rt_uint32_t fifo; +}; + +typedef rt_err_t (*dma_txconfig)(rt_uint32_t *src, rt_uint32_t *dst, int size); +typedef rt_err_t (*dma_rxconfig)(rt_uint32_t *src, rt_uint32_t *dst, int size); +typedef rt_uint32_t (*sdio_clk_get)(struct stm32_sdio *hw_sdio); + +struct stm32_sdio_des +{ + struct stm32_sdio *hw_sdio; + dma_txconfig txconfig; + dma_rxconfig rxconfig; + sdio_clk_get clk_get; +}; + +struct stm32_sdio_config +{ + SDIO_TypeDef *Instance; + struct dma_config dma_rx, dma_tx; +}; + +/* stm32 sdio dirver class */ +struct stm32_sdio_class +{ + struct stm32_sdio_des *des; + const struct stm32_sdio_config *cfg; + struct rt_mmcsd_host host; + struct + { + DMA_HandleTypeDef handle_rx; + DMA_HandleTypeDef handle_tx; + } dma; +}; + +#endif -- cgit v1.3.1 From d830b6cbf8ccb11ad246661c68d145e6bf4d0b71 Mon Sep 17 00:00:00 2001 From: SummerGift Date: Thu, 20 Dec 2018 14:00:33 +0800 Subject: [bsp][stm32] modify drv_config.h --- bsp/stm32/libraries/HAL_Drivers/drv_config.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'bsp/stm32/libraries') diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_config.h b/bsp/stm32/libraries/HAL_Drivers/drv_config.h index f6bcdedb2c..5667b6d05d 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drv_config.h @@ -18,10 +18,16 @@ #include "f1/uart_config.h" #include "f1/spi_config.h" #include "f1/adc_config.h" +#include "f1/tim_config.h" +#include "f1/sdio_config.h" +#include "f1/pwm_config.h" #elif defined(SOC_SERIES_STM32F4) #include "f4/uart_config.h" #include "f4/spi_config.h" #include "f4/adc_config.h" +#include "f4/tim_config.h" +#include "f4/sdio_config.h" +#include "f4/pwm_config.h" #elif defined(SOC_SERIES_STM32F7) #include "f7/uart_config.h" #include "f7/spi_config.h" @@ -30,6 +36,8 @@ #include "l4/uart_config.h" #include "l4/spi_config.h" #include "l4/adc_config.h" +#include "l4/tim_config.h" +#include "l4/pwm_config.h" #endif #endif -- cgit v1.3.1 From 63dbe799120efbed2db25cf3d169086ff389b613 Mon Sep 17 00:00:00 2001 From: SummerGift Date: Thu, 20 Dec 2018 14:50:07 +0800 Subject: [bsp][stm32] Sync SConscript --- bsp/stm32/libraries/STM32F1xx_HAL/SConscript | 113 +++++++++++---------- bsp/stm32/libraries/STM32F4xx_HAL/SConscript | 124 +++++++++++++---------- bsp/stm32/libraries/STM32L4xx_HAL/SConscript | 143 ++++++++++++--------------- 3 files changed, 196 insertions(+), 184 deletions(-) (limited to 'bsp/stm32/libraries') diff --git a/bsp/stm32/libraries/STM32F1xx_HAL/SConscript b/bsp/stm32/libraries/STM32F1xx_HAL/SConscript index 4ee2fabd48..37101b6c74 100644 --- a/bsp/stm32/libraries/STM32F1xx_HAL/SConscript +++ b/bsp/stm32/libraries/STM32F1xx_HAL/SConscript @@ -8,69 +8,80 @@ cwd = GetCurrentDir() # The set of source files associated with this SConscript file. src = Split(""" CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_crc.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_irda.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_smartcard.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_usart.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_wwdg.c STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_adc.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_crc.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_dac.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_dma.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_exti.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_fsmc.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_gpio.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_i2c.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_pwr.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_rcc.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_rtc.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_sdmmc.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_spi.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_tim.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usart.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_utils.c STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cec.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dac.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dac_ex.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_eth.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_hcd.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2s.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_mmc.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sd.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nand.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pccard.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nor.c STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.c """) -#device options + +if GetDepend(['RT_USING_PIN']): + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c'] + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c'] + +if GetDepend(['RT_USING_SERIAL']): + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c'] + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_usart.c'] + +if GetDepend(['RT_USING_I2C']): + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.c'] + +if GetDepend(['RT_USING_SPI']): + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c'] + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c'] + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_spi.c'] + +if GetDepend(['RT_USING_USB_HOST']) or GetDepend(['RT_USING_USB_DEVICE']): + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c'] + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.c'] + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c'] + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_hcd.c'] + +if GetDepend(['RT_USING_CAN']): + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c'] + +if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']): + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c'] + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c'] + +if GetDepend(['BSP_USING_ETH']): + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_eth.c'] + +if GetDepend(['RT_USING_ADC']): + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c'] + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c'] + +if GetDepend(['RT_USING_RTC']): + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c'] + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c'] + +if GetDepend(['RT_USING_WDT']): + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c'] + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_wwdg.c'] + +if GetDepend(['RT_USING_SDIO']): + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_mmc.c'] + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sd.c'] + +if GetDepend(['RT_USING_AUDIO']): + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2s.c'] + +if GetDepend(['RT_USING_MTD_NOR']): + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nor.c'] + +if GetDepend(['RT_USING_MTD_NAND']): + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nand.c'] + +if GetDepend(['BSP_USING_ON_CHIP_FLASH']): + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c'] + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c'] path = [cwd + '/CMSIS/Device/ST/STM32F1xx/Include', - cwd + '/STM32F1xx_HAL_Driver/Inc', + cwd + '/STM32F1xx_HAL_Driver/Inc', cwd + '/CMSIS/Include'] if GetDepend(['RT_USING_RTT_CMSIS']): diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/SConscript b/bsp/stm32/libraries/STM32F4xx_HAL/SConscript index 9b16e71735..375bf546f8 100644 --- a/bsp/stm32/libraries/STM32F4xx_HAL/SConscript +++ b/bsp/stm32/libraries/STM32F4xx_HAL/SConscript @@ -9,74 +9,92 @@ cwd = GetCurrentDir() src = Split(''' CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cec.c STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_crc.c STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp.c STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp_ex.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac_ex.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dcmi.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dcmi_ex.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dfsdm.c STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma2d.c STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dsi.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c_ex.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hash.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hash_ex.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_irda.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_lptim.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc_ex.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nand.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nor.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pccard.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rng.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai_ex.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smartcard.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spdifrx.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sram.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_usart.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c ''') +if GetDepend(['RT_USING_PIN']): + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c'] + +if GetDepend(['RT_USING_SERIAL']): + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_usart.c'] + +if GetDepend(['RT_USING_I2C']): + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c'] + +if GetDepend(['RT_USING_SPI']): + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c'] + +if GetDepend(['RT_USING_USB_HOST']) or GetDepend(['RT_USING_USB_DEVICE']): + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pccard.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c'] + +if GetDepend(['RT_USING_CAN']): + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c'] + +if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']): + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_lptim.c'] + +if GetDepend(['BSP_USING_ETH']): + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c'] + +if GetDepend(['RT_USING_ADC']): + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c'] + +if GetDepend(['RT_USING_RTC']): + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c'] + +if GetDepend(['RT_USING_WDT']): + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c'] + +if GetDepend(['RT_USING_SDIO']): + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c'] + +if GetDepend(['RT_USING_AUDIO']): + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai_ex.c'] + +if GetDepend(['RT_USING_MTD_NOR']): + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nor.c'] + +if GetDepend(['RT_USING_MTD_NAND']): + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nand.c'] + +if GetDepend(['BSP_USING_SDRAM']): + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c'] + +if GetDepend(['BSP_USING_ON_CHIP_FLASH']): + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c'] + path = [cwd + '/STM32F4xx_HAL_Driver/Inc', cwd + '/CMSIS/Device/ST/STM32F4xx/Include', cwd + '/CMSIS/Include'] diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/SConscript b/bsp/stm32/libraries/STM32L4xx_HAL/SConscript index f8baad95d4..5d6f0d9032 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/SConscript +++ b/bsp/stm32/libraries/STM32L4xx_HAL/SConscript @@ -9,103 +9,86 @@ cwd = GetCurrentDir() src = Split(''' CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_can.c STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_comp.c STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc.c STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc_ex.c STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cryp.c STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cryp_ex.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac_ex.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dcmi.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm_ex.c STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma2d.c STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dsi.c STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_firewall.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gfxmmu.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hash.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hash_ex.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hcd.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_irda.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lcd.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lptim.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc_ex.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_nand.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_nor.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_opamp.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_opamp_ex.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ospi.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai_ex.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd_ex.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smartcard.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smartcard_ex.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smbus.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sram.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_swpmi.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tsc.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart_ex.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_wwdg.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_adc.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_comp.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_crc.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_crs.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dac.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dma.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dma2d.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_exti.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_fmc.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_gpio.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_i2c.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_lptim.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_lpuart.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_opamp.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_pwr.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rcc.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rng.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rtc.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_sdmmc.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_spi.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_swpmi.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_tim.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usart.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c ''') +if GetDepend(['RT_USING_PIN']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c'] + +if GetDepend(['RT_USING_SERIAL']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart_ex.c'] + +if GetDepend(['RT_USING_I2C']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c'] + +if GetDepend(['RT_USING_SPI']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c'] + +if GetDepend(['RT_USING_USB_HOST']) or GetDepend(['RT_USING_USB_DEVICE']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hcd.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c'] + +if GetDepend(['RT_USING_CAN']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_can.c'] + +if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lptim.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c'] + +if GetDepend(['RT_USING_ADC']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c'] + +if GetDepend(['RT_USING_RTC']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c'] + +if GetDepend(['RT_USING_WDT']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_wwdg.c'] + +if GetDepend(['RT_USING_SDIO']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd_ex.c'] + +if GetDepend(['RT_USING_AUDIO']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai_ex.c'] + +if GetDepend(['RT_USING_MTD_NOR']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_nor.c'] + +if GetDepend(['RT_USING_MTD_NAND']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_nand.c'] + +if GetDepend(['BSP_USING_ON_CHIP_FLASH']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c'] + path = [cwd + '/STM32L4xx_HAL_Driver/Inc', cwd + '/CMSIS/Device/ST/STM32L4xx/Include', cwd + '/CMSIS/Include'] -- cgit v1.3.1 From d5c7d8d41fe3a1d7b82bb16b42096660036bf451 Mon Sep 17 00:00:00 2001 From: SummerGift Date: Thu, 20 Dec 2018 14:52:32 +0800 Subject: [bsp][stm32] Sync kconfig --- bsp/stm32/libraries/templates/stm32f7xx/board/Kconfig | 4 ---- bsp/stm32/stm32f103-atk-nano/board/Kconfig | 4 ---- bsp/stm32/stm32f103-fire-arbitrary/board/Kconfig | 4 ---- bsp/stm32/stm32f407-atk-explorer/board/Kconfig | 4 ---- bsp/stm32/stm32f429-atk-apollo/board/Kconfig | 4 ---- bsp/stm32/stm32f429-fire-challenger/board/Kconfig | 4 ---- bsp/stm32/stm32l475-atk-pandora/board/Kconfig | 4 ---- 7 files changed, 28 deletions(-) (limited to 'bsp/stm32/libraries') diff --git a/bsp/stm32/libraries/templates/stm32f7xx/board/Kconfig b/bsp/stm32/libraries/templates/stm32f7xx/board/Kconfig index a15665c848..02454235c7 100644 --- a/bsp/stm32/libraries/templates/stm32f7xx/board/Kconfig +++ b/bsp/stm32/libraries/templates/stm32f7xx/board/Kconfig @@ -21,10 +21,6 @@ menu "On-chip Peripheral Drivers" select RT_USING_SERIAL default y - config BSP_UART_USING_DMA_RX - bool "Enable UART RX DMA support" - default n - config BSP_USING_SPI1 bool "Enable SPI1 BUS" select RT_USING_SPI diff --git a/bsp/stm32/stm32f103-atk-nano/board/Kconfig b/bsp/stm32/stm32f103-atk-nano/board/Kconfig index 2b6d6b3fc1..20cbf0ccc6 100644 --- a/bsp/stm32/stm32f103-atk-nano/board/Kconfig +++ b/bsp/stm32/stm32f103-atk-nano/board/Kconfig @@ -54,10 +54,6 @@ menu "On-chip Peripheral Drivers" select RT_USING_SERIAL default n - config BSP_UART_USING_DMA_RX - bool "Enable UART RX DMA support" - default n - menuconfig BSP_USING_TIM bool "Enable timer" default n diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/Kconfig b/bsp/stm32/stm32f103-fire-arbitrary/board/Kconfig index ae55be5fab..4227ae9bf5 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/Kconfig +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/Kconfig @@ -103,10 +103,6 @@ menu "On-chip Peripheral Drivers" bool "Enable UART3" select RT_USING_SERIAL default n - - config BSP_UART_USING_DMA_RX - bool "Enable UART RX DMA support" - default n config BSP_USING_ON_CHIP_FLASH bool "Enable on-chip FLASH" diff --git a/bsp/stm32/stm32f407-atk-explorer/board/Kconfig b/bsp/stm32/stm32f407-atk-explorer/board/Kconfig index 319cb49c92..0f22133a55 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/Kconfig +++ b/bsp/stm32/stm32f407-atk-explorer/board/Kconfig @@ -118,10 +118,6 @@ menu "On-chip Peripheral Drivers" bool "Enable on-chip FLASH" default n - config BSP_UART_USING_DMA_RX - bool "Enable UART RX DMA support" - default n - config BSP_USING_SPI1 bool "Enable SPI1 BUS" select RT_USING_SPI diff --git a/bsp/stm32/stm32f429-atk-apollo/board/Kconfig b/bsp/stm32/stm32f429-atk-apollo/board/Kconfig index 9d85754053..c88b1efec9 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/Kconfig +++ b/bsp/stm32/stm32f429-atk-apollo/board/Kconfig @@ -82,10 +82,6 @@ menu "On-chip Peripheral Drivers" select RT_USING_SERIAL default n - config BSP_UART_USING_DMA_RX - bool "Enable UART RX DMA support" - default y - config BSP_USING_ON_CHIP_FLASH bool "Enable on-chip FLASH" default n diff --git a/bsp/stm32/stm32f429-fire-challenger/board/Kconfig b/bsp/stm32/stm32f429-fire-challenger/board/Kconfig index 0323f139ce..e1c6928049 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/Kconfig +++ b/bsp/stm32/stm32f429-fire-challenger/board/Kconfig @@ -92,10 +92,6 @@ menu "On-chip Peripheral Drivers" select RT_USING_SERIAL default n - config BSP_UART_USING_DMA_RX - bool "Enable UART RX DMA support" - default n - config BSP_USING_ON_CHIP_FLASH bool "Enable on-chip FLASH" default n diff --git a/bsp/stm32/stm32l475-atk-pandora/board/Kconfig b/bsp/stm32/stm32l475-atk-pandora/board/Kconfig index a389b5beca..cf4bf952f4 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/Kconfig +++ b/bsp/stm32/stm32l475-atk-pandora/board/Kconfig @@ -46,10 +46,6 @@ menu "On-chip Peripheral Drivers" bool "Enable UART2" select RT_USING_SERIAL default n - - config BSP_UART_USING_DMA_RX - bool "Enable UART RX DMA support" - default n config BSP_USING_ON_CHIP_FLASH bool "Enable on-chip FLASH" -- cgit v1.3.1 From 938bbb030d5c94e845257e46e020d6bbab8b4fea Mon Sep 17 00:00:00 2001 From: SummerGift Date: Thu, 20 Dec 2018 14:53:46 +0800 Subject: [bsp][stm32] optimize main func --- bsp/stm32/libraries/templates/stm32f10x/applications/main.c | 11 ++++++++++- bsp/stm32/libraries/templates/stm32f10x/board/board.c | 9 --------- bsp/stm32/libraries/templates/stm32f10x/board/board.h | 6 ------ bsp/stm32/libraries/templates/stm32f4xx/applications/main.c | 11 ++++++++++- bsp/stm32/libraries/templates/stm32f4xx/board/board.c | 9 --------- bsp/stm32/libraries/templates/stm32f4xx/board/board.h | 6 ------ bsp/stm32/libraries/templates/stm32l4xx/applications/main.c | 11 ++++++++++- bsp/stm32/libraries/templates/stm32l4xx/board/board.c | 9 --------- bsp/stm32/libraries/templates/stm32l4xx/board/board.h | 6 ------ bsp/stm32/stm32f103-atk-nano/applications/main.c | 11 ++++++++++- bsp/stm32/stm32f103-atk-nano/board/board.c | 9 +-------- bsp/stm32/stm32f103-atk-nano/board/board.h | 7 ------- bsp/stm32/stm32f103-fire-arbitrary/applications/main.c | 11 ++++++++++- bsp/stm32/stm32f103-fire-arbitrary/board/board.c | 11 ----------- bsp/stm32/stm32f103-fire-arbitrary/board/board.h | 7 ------- bsp/stm32/stm32f407-atk-explorer/applications/main.c | 11 ++++++++++- bsp/stm32/stm32f407-atk-explorer/board/board.c | 11 ----------- bsp/stm32/stm32f407-atk-explorer/board/board.h | 7 ------- bsp/stm32/stm32f429-atk-apollo/applications/main.c | 11 ++++++++++- bsp/stm32/stm32f429-atk-apollo/board/board.c | 11 ----------- bsp/stm32/stm32f429-atk-apollo/board/board.h | 9 --------- bsp/stm32/stm32f429-fire-challenger/applications/main.c | 11 ++++++++++- bsp/stm32/stm32f429-fire-challenger/board/board.c | 11 ----------- bsp/stm32/stm32f429-fire-challenger/board/board.h | 8 -------- bsp/stm32/stm32l475-atk-pandora/applications/main.c | 11 ++++++++++- bsp/stm32/stm32l475-atk-pandora/board/board.c | 9 --------- bsp/stm32/stm32l475-atk-pandora/board/board.h | 8 -------- 27 files changed, 91 insertions(+), 161 deletions(-) (limited to 'bsp/stm32/libraries') diff --git a/bsp/stm32/libraries/templates/stm32f10x/applications/main.c b/bsp/stm32/libraries/templates/stm32f10x/applications/main.c index 87a07a6246..7c40c1518d 100644 --- a/bsp/stm32/libraries/templates/stm32f10x/applications/main.c +++ b/bsp/stm32/libraries/templates/stm32f10x/applications/main.c @@ -11,14 +11,23 @@ #include #include #include +#include "drv_gpio.h" +/* defined the LED0 pin: PB1 */ +#define LED0_PIN GET_PIN(B, 1) int main(void) { int count = 1; + /* set LED0 pin mode to output */ + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); + while (count++) { - // rt_pin_write(LED0_PIN, !rt_pin_read(LED0_PIN)); + rt_pin_write(LED0_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } + return RT_EOK; } diff --git a/bsp/stm32/libraries/templates/stm32f10x/board/board.c b/bsp/stm32/libraries/templates/stm32f10x/board/board.c index ac55193461..36c127c5b7 100644 --- a/bsp/stm32/libraries/templates/stm32f10x/board/board.c +++ b/bsp/stm32/libraries/templates/stm32f10x/board/board.c @@ -51,12 +51,3 @@ void MX_GPIO_Init(void) __HAL_RCC_GPIOA_CLK_ENABLE(); } - -#ifdef RT_USING_PIN -// int board_pin_init(void) -// { -// rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); -// return 0; -// } -// INIT_BOARD_EXPORT(board_pin_init); -#endif /* RT_USING_PIN */ diff --git a/bsp/stm32/libraries/templates/stm32f10x/board/board.h b/bsp/stm32/libraries/templates/stm32f10x/board/board.h index cc2079f0e7..1c00e71dca 100644 --- a/bsp/stm32/libraries/templates/stm32f10x/board/board.h +++ b/bsp/stm32/libraries/templates/stm32f10x/board/board.h @@ -15,12 +15,6 @@ #include #include "drv_common.h" -#ifdef BSP_USING_GPIO -#include "drv_gpio.h" -/* Board Pin definitions */ -// #define LED0_PIN GET_PIN(C, 0) -#endif - /* Internal SRAM memory size[Kbytes] <8-64>, Default: 64*/ #define STM32_SRAM_SIZE 20 #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) diff --git a/bsp/stm32/libraries/templates/stm32f4xx/applications/main.c b/bsp/stm32/libraries/templates/stm32f4xx/applications/main.c index 87a07a6246..7c40c1518d 100644 --- a/bsp/stm32/libraries/templates/stm32f4xx/applications/main.c +++ b/bsp/stm32/libraries/templates/stm32f4xx/applications/main.c @@ -11,14 +11,23 @@ #include #include #include +#include "drv_gpio.h" +/* defined the LED0 pin: PB1 */ +#define LED0_PIN GET_PIN(B, 1) int main(void) { int count = 1; + /* set LED0 pin mode to output */ + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); + while (count++) { - // rt_pin_write(LED0_PIN, !rt_pin_read(LED0_PIN)); + rt_pin_write(LED0_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } + return RT_EOK; } diff --git a/bsp/stm32/libraries/templates/stm32f4xx/board/board.c b/bsp/stm32/libraries/templates/stm32f4xx/board/board.c index 928bbdbbde..b3cf3b0754 100644 --- a/bsp/stm32/libraries/templates/stm32f4xx/board/board.c +++ b/bsp/stm32/libraries/templates/stm32f4xx/board/board.c @@ -56,12 +56,3 @@ void MX_GPIO_Init(void) __HAL_RCC_GPIOA_CLK_ENABLE(); } - -#ifdef RT_USING_PIN -// int board_pin_init(void) -// { -// rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); -// return 0; -// } -// INIT_BOARD_EXPORT(board_pin_init); -#endif /* RT_USING_PIN */ diff --git a/bsp/stm32/libraries/templates/stm32f4xx/board/board.h b/bsp/stm32/libraries/templates/stm32f4xx/board/board.h index 8cb36267f7..f7944b4ed7 100644 --- a/bsp/stm32/libraries/templates/stm32f4xx/board/board.h +++ b/bsp/stm32/libraries/templates/stm32f4xx/board/board.h @@ -15,12 +15,6 @@ #include #include "drv_common.h" -#ifdef BSP_USING_GPIO -#include "drv_gpio.h" -/* Board Pin definitions */ -// #define LED0_PIN GET_PIN(C, 0) -#endif - #define STM32_SRAM_SIZE 128 #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) diff --git a/bsp/stm32/libraries/templates/stm32l4xx/applications/main.c b/bsp/stm32/libraries/templates/stm32l4xx/applications/main.c index 87a07a6246..7c40c1518d 100644 --- a/bsp/stm32/libraries/templates/stm32l4xx/applications/main.c +++ b/bsp/stm32/libraries/templates/stm32l4xx/applications/main.c @@ -11,14 +11,23 @@ #include #include #include +#include "drv_gpio.h" +/* defined the LED0 pin: PB1 */ +#define LED0_PIN GET_PIN(B, 1) int main(void) { int count = 1; + /* set LED0 pin mode to output */ + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); + while (count++) { - // rt_pin_write(LED0_PIN, !rt_pin_read(LED0_PIN)); + rt_pin_write(LED0_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } + return RT_EOK; } diff --git a/bsp/stm32/libraries/templates/stm32l4xx/board/board.c b/bsp/stm32/libraries/templates/stm32l4xx/board/board.c index d0e25eaf04..5f8113f4d7 100644 --- a/bsp/stm32/libraries/templates/stm32l4xx/board/board.c +++ b/bsp/stm32/libraries/templates/stm32l4xx/board/board.c @@ -66,12 +66,3 @@ void MX_GPIO_Init(void) __HAL_RCC_GPIOA_CLK_ENABLE(); } - -#ifdef RT_USING_PIN -// int board_pin_init(void) -// { -// rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); -// return 0; -// } -// INIT_BOARD_EXPORT(board_pin_init); -#endif /* RT_USING_PIN */ diff --git a/bsp/stm32/libraries/templates/stm32l4xx/board/board.h b/bsp/stm32/libraries/templates/stm32l4xx/board/board.h index 2b3e8b6cb1..29e1ba4267 100644 --- a/bsp/stm32/libraries/templates/stm32l4xx/board/board.h +++ b/bsp/stm32/libraries/templates/stm32l4xx/board/board.h @@ -15,12 +15,6 @@ #include #include "drv_common.h" -#ifdef BSP_USING_GPIO -#include "drv_gpio.h" -/* Board Pin definitions */ -// #define LED0_PIN GET_PIN(C, 0) -#endif - #define STM32_SRAM_SIZE 96 #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) diff --git a/bsp/stm32/stm32f103-atk-nano/applications/main.c b/bsp/stm32/stm32f103-atk-nano/applications/main.c index 61f0263ca2..e5b96d8280 100644 --- a/bsp/stm32/stm32f103-atk-nano/applications/main.c +++ b/bsp/stm32/stm32f103-atk-nano/applications/main.c @@ -11,14 +11,23 @@ #include #include #include +#include "drv_gpio.h" +/* defined the LED0 pin: PC0 */ +#define LED0_PIN GET_PIN(C, 0) int main(void) { int count = 1; + /* set LED0 pin mode to output */ + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); + while (count++) { - rt_pin_write(LED0_PIN, !rt_pin_read(LED0_PIN)); + rt_pin_write(LED0_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } + return RT_EOK; } diff --git a/bsp/stm32/stm32f103-atk-nano/board/board.c b/bsp/stm32/stm32f103-atk-nano/board/board.c index 28bb36889c..981fffc85e 100644 --- a/bsp/stm32/stm32f103-atk-nano/board/board.c +++ b/bsp/stm32/stm32f103-atk-nano/board/board.c @@ -62,11 +62,4 @@ void MX_GPIO_Init(void) __HAL_RCC_GPIOA_CLK_ENABLE(); } -#ifdef RT_USING_PIN -int board_pin_init(void) -{ - rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - return 0; -} -INIT_BOARD_EXPORT(board_pin_init); -#endif /* RT_USING_PIN */ + diff --git a/bsp/stm32/stm32f103-atk-nano/board/board.h b/bsp/stm32/stm32f103-atk-nano/board/board.h index 410414c202..a22d23632a 100644 --- a/bsp/stm32/stm32f103-atk-nano/board/board.h +++ b/bsp/stm32/stm32f103-atk-nano/board/board.h @@ -15,13 +15,6 @@ #include #include "drv_common.h" -#ifdef BSP_USING_GPIO -#include "drv_gpio.h" -/* Board Pin definitions */ -#define LED0_PIN GET_PIN(C, 0) -#define LED1_PIN GET_PIN(C, 1) -#endif - #define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000) #define STM32_FLASH_SIZE (128 * 1024) #define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE)) diff --git a/bsp/stm32/stm32f103-fire-arbitrary/applications/main.c b/bsp/stm32/stm32f103-fire-arbitrary/applications/main.c index 2042a40378..4024c1ae3f 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/applications/main.c +++ b/bsp/stm32/stm32f103-fire-arbitrary/applications/main.c @@ -11,14 +11,23 @@ #include #include #include +#include "drv_gpio.h" +/* defined the LED0 pin: PF7 */ +#define LED0_PIN GET_PIN(F, 7) int main(void) { int count = 1; + /* set LED0 pin mode to output */ + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); + while (count++) { - rt_pin_write(LED0_PIN, !rt_pin_read(LED0_PIN)); + rt_pin_write(LED0_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } + return RT_EOK; } diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/board.c b/bsp/stm32/stm32f103-fire-arbitrary/board/board.c index 3188bdb616..829addae08 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/board.c +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/board.c @@ -63,14 +63,3 @@ void MX_GPIO_Init(void) __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); } - -#ifdef RT_USING_PIN -int board_pin_init(void) -{ - rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); - - return 0; -} -INIT_BOARD_EXPORT(board_pin_init); -#endif /* RT_USING_PIN */ diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/board.h b/bsp/stm32/stm32f103-fire-arbitrary/board/board.h index fc77f71a95..d0718d5525 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/board.h +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/board.h @@ -15,13 +15,6 @@ #include #include "drv_common.h" -#ifdef BSP_USING_GPIO -#include "drv_gpio.h" -/* Board Pin definitions */ -#define LED0_PIN GET_PIN(F, 7) -#define LED1_PIN GET_PIN(F, 8) -#endif - /* Internal SRAM memory size[Kbytes] <8-64>, Default: 64*/ #define STM32_SRAM_SIZE 64 #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) diff --git a/bsp/stm32/stm32f407-atk-explorer/applications/main.c b/bsp/stm32/stm32f407-atk-explorer/applications/main.c index 5d7f42bdab..b7bd6a1249 100644 --- a/bsp/stm32/stm32f407-atk-explorer/applications/main.c +++ b/bsp/stm32/stm32f407-atk-explorer/applications/main.c @@ -12,14 +12,23 @@ #include #include #include +#include "drv_gpio.h" +/* defined the LED0 pin: PF9 */ +#define LED0_PIN GET_PIN(F, 9) int main(void) { int count = 1; + /* set LED0 pin mode to output */ + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); + while (count++) { - rt_pin_write(LED1_PIN, !rt_pin_read(LED1_PIN)); + rt_pin_write(LED0_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } + return RT_EOK; } diff --git a/bsp/stm32/stm32f407-atk-explorer/board/board.c b/bsp/stm32/stm32f407-atk-explorer/board/board.c index 52145fe832..cea8c7fff9 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/board.c +++ b/bsp/stm32/stm32f407-atk-explorer/board/board.c @@ -67,14 +67,3 @@ void MX_GPIO_Init(void) __HAL_RCC_GPIOB_CLK_ENABLE(); } - -#ifdef RT_USING_PIN -int board_pin_init(void) -{ - rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); - - return 0; -} -INIT_BOARD_EXPORT(board_pin_init); -#endif /* RT_USING_PIN */ diff --git a/bsp/stm32/stm32f407-atk-explorer/board/board.h b/bsp/stm32/stm32f407-atk-explorer/board/board.h index 4dab0eddd3..77928f7f80 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/board.h +++ b/bsp/stm32/stm32f407-atk-explorer/board/board.h @@ -15,13 +15,6 @@ #include #include "drv_common.h" -#ifdef BSP_USING_GPIO -#include "drv_gpio.h" -/* Board Pin definitions */ -#define LED0_PIN GET_PIN(F, 9) -#define LED1_PIN GET_PIN(F, 10) -#endif - #define STM32_SRAM_SIZE (128) #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) diff --git a/bsp/stm32/stm32f429-atk-apollo/applications/main.c b/bsp/stm32/stm32f429-atk-apollo/applications/main.c index 768cedfae7..7c40c1518d 100644 --- a/bsp/stm32/stm32f429-atk-apollo/applications/main.c +++ b/bsp/stm32/stm32f429-atk-apollo/applications/main.c @@ -11,14 +11,23 @@ #include #include #include +#include "drv_gpio.h" +/* defined the LED0 pin: PB1 */ +#define LED0_PIN GET_PIN(B, 1) int main(void) { int count = 1; + /* set LED0 pin mode to output */ + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); + while (count++) { - rt_pin_write(LED1_PIN, !rt_pin_read(LED1_PIN)); + rt_pin_write(LED0_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } + return RT_EOK; } diff --git a/bsp/stm32/stm32f429-atk-apollo/board/board.c b/bsp/stm32/stm32f429-atk-apollo/board/board.c index 91cde7a95d..a0d2cd17a5 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/board.c +++ b/bsp/stm32/stm32f429-atk-apollo/board/board.c @@ -77,14 +77,3 @@ void MX_GPIO_Init(void) __HAL_RCC_GPIOD_CLK_ENABLE(); __HAL_RCC_GPIOG_CLK_ENABLE(); } - -#ifdef RT_USING_PIN -int board_pin_init(void) -{ - rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); - - return 0; -} -INIT_BOARD_EXPORT(board_pin_init); -#endif /* RT_USING_PIN */ diff --git a/bsp/stm32/stm32f429-atk-apollo/board/board.h b/bsp/stm32/stm32f429-atk-apollo/board/board.h index 5d59b9bd77..8be558340c 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/board.h +++ b/bsp/stm32/stm32f429-atk-apollo/board/board.h @@ -15,10 +15,6 @@ #include #include "drv_common.h" -#ifdef BSP_USING_GPIO -#include "drv_gpio.h" -#endif - #define STM32_SRAM_SIZE (192) #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) @@ -39,12 +35,7 @@ extern int __bss_end; #define HEAP_END STM32_SRAM_END -/* Board Pin definitions */ -#define LED0_PIN GET_PIN(B, 1) -#define LED1_PIN GET_PIN(B, 0) - void SystemClock_Config(void); void MX_GPIO_Init(void); #endif - diff --git a/bsp/stm32/stm32f429-fire-challenger/applications/main.c b/bsp/stm32/stm32f429-fire-challenger/applications/main.c index 582e5ed887..cee539b083 100644 --- a/bsp/stm32/stm32f429-fire-challenger/applications/main.c +++ b/bsp/stm32/stm32f429-fire-challenger/applications/main.c @@ -12,14 +12,23 @@ #include #include #include +#include "drv_gpio.h" +/* defined the LED0 pin: PH10 */ +#define LED0_PIN GET_PIN(H, 10) int main(void) { int count = 1; + /* set LED0 pin mode to output */ + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); + while (count++) { - rt_pin_write(LED1_PIN, !rt_pin_read(LED1_PIN)); + rt_pin_write(LED0_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } + return RT_EOK; } diff --git a/bsp/stm32/stm32f429-fire-challenger/board/board.c b/bsp/stm32/stm32f429-fire-challenger/board/board.c index 77961c793c..19559f4059 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/board.c +++ b/bsp/stm32/stm32f429-fire-challenger/board/board.c @@ -76,14 +76,3 @@ void MX_GPIO_Init(void) __HAL_RCC_GPIOG_CLK_ENABLE(); } - -#ifdef RT_USING_PIN -int board_pin_init(void) -{ - rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); - - return 0; -} -INIT_BOARD_EXPORT(board_pin_init); -#endif /* RT_USING_PIN */ diff --git a/bsp/stm32/stm32f429-fire-challenger/board/board.h b/bsp/stm32/stm32f429-fire-challenger/board/board.h index 4348bb5fb7..69a99bf672 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/board.h +++ b/bsp/stm32/stm32f429-fire-challenger/board/board.h @@ -15,10 +15,6 @@ #include #include "drv_common.h" -#ifdef BSP_USING_GPIO -#include "drv_gpio.h" -#endif - #define STM32_SRAM_SIZE (192) #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) @@ -39,10 +35,6 @@ extern int __bss_end; #define HEAP_END STM32_SRAM_END -/* Board Pin definitions */ -#define LED0_PIN GET_PIN(H, 10) -#define LED1_PIN GET_PIN(H, 11) - void SystemClock_Config(void); void MX_GPIO_Init(void); diff --git a/bsp/stm32/stm32l475-atk-pandora/applications/main.c b/bsp/stm32/stm32l475-atk-pandora/applications/main.c index a802fd07e8..208dd4525f 100644 --- a/bsp/stm32/stm32l475-atk-pandora/applications/main.c +++ b/bsp/stm32/stm32l475-atk-pandora/applications/main.c @@ -11,14 +11,23 @@ #include #include #include +#include "drv_gpio.h" +/* defined the LED0 pin: PE7 */ +#define LED0_PIN GET_PIN(E, 7) int main(void) { int count = 1; + /* set LED0 pin mode to output */ + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); + while (count++) { - rt_pin_write(LED0_PIN, !rt_pin_read(LED0_PIN)); + rt_pin_write(LED0_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } + return RT_EOK; } diff --git a/bsp/stm32/stm32l475-atk-pandora/board/board.c b/bsp/stm32/stm32l475-atk-pandora/board/board.c index 4c6d7f61ea..78eb82025c 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/board.c +++ b/bsp/stm32/stm32l475-atk-pandora/board/board.c @@ -74,12 +74,3 @@ void MX_GPIO_Init(void) __HAL_RCC_GPIOB_CLK_ENABLE(); } - -#ifdef RT_USING_PIN -int board_pin_init(void) -{ - rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - return 0; -} -INIT_BOARD_EXPORT(board_pin_init); -#endif /* RT_USING_PIN */ diff --git a/bsp/stm32/stm32l475-atk-pandora/board/board.h b/bsp/stm32/stm32l475-atk-pandora/board/board.h index 43ea79b4e4..df4023b4bb 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/board.h +++ b/bsp/stm32/stm32l475-atk-pandora/board/board.h @@ -15,10 +15,6 @@ #include #include "drv_common.h" -#ifdef BSP_USING_GPIO -#include "drv_gpio.h" -#endif - #define STM32_SRAM1_SIZE (96) #define STM32_SRAM1_START (0x20000000) #define STM32_SRAM1_END (STM32_SRAM1_START + STM32_SRAM1_SIZE * 1024) @@ -30,10 +26,6 @@ #define HEAP_BEGIN STM32_SRAM1_START #define HEAP_END STM32_SRAM1_END -/* Board Pin definitions */ -#define LED0_PIN GET_PIN(E, 7) -#define LED1_PIN GET_PIN(E, 8) - void SystemClock_Config(void); void MX_GPIO_Init(void); -- cgit v1.3.1 From 08bc2b3f5d2a6cd3d46b5d4770bfacdc0ed9ba0a Mon Sep 17 00:00:00 2001 From: SummerGift Date: Thu, 20 Dec 2018 15:04:19 +0800 Subject: [bsp][stm32] fix flash bug --- bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f4.c | 16 +++++++++++++--- bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_l4.c | 2 +- 2 files changed, 14 insertions(+), 4 deletions(-) (limited to 'bsp/stm32/libraries') diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f4.c b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f4.c index 8cbfc040b6..fd704f7362 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f4.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f4.c @@ -91,22 +91,30 @@ static rt_uint32_t GetSector(rt_uint32_t Address) { sector = FLASH_SECTOR_7; } +#if defined(FLASH_SECTOR_8) else if((Address < ADDR_FLASH_SECTOR_9) && (Address >= ADDR_FLASH_SECTOR_8)) { sector = FLASH_SECTOR_8; } +#endif +#if defined(FLASH_SECTOR_9) else if((Address < ADDR_FLASH_SECTOR_10) && (Address >= ADDR_FLASH_SECTOR_9)) { sector = FLASH_SECTOR_9; } +#endif +#if defined(FLASH_SECTOR_10) else if((Address < ADDR_FLASH_SECTOR_11) && (Address >= ADDR_FLASH_SECTOR_10)) { sector = FLASH_SECTOR_10; } +#endif +#if defined(FLASH_SECTOR_11) else if((Address < ADDR_FLASH_SECTOR_12) && (Address >= ADDR_FLASH_SECTOR_11)) { sector = FLASH_SECTOR_11; } +#endif #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) else if((Address < ADDR_FLASH_SECTOR_13) && (Address >= ADDR_FLASH_SECTOR_12)) { @@ -219,7 +227,7 @@ int stm32_flash_write(long offset, const rt_uint8_t *buf, size_t size) HAL_FLASH_Unlock(); - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGSERR); + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR); for (size_t i = 0; i < size; i++, addr++, buf++) { @@ -278,17 +286,19 @@ int stm32_flash_erase(long offset, size_t size) /* Unlock the Flash to enable the flash control register access */ HAL_FLASH_Unlock(); + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR); + /* Get the 1st sector to erase */ FirstSector = GetSector(addr); /* Get the number of sector to erase from 1st sector*/ - NbOfSectors = GetSector(addr + size) - FirstSector + 1; + NbOfSectors = GetSector(addr + size - 1) - FirstSector + 1; /* Fill EraseInit structure*/ EraseInitStruct.TypeErase = FLASH_TYPEERASE_SECTORS; EraseInitStruct.VoltageRange = FLASH_VOLTAGE_RANGE_3; EraseInitStruct.Sector = FirstSector; EraseInitStruct.NbSectors = NbOfSectors; - if (HAL_FLASHEx_Erase(&EraseInitStruct, &SECTORError) != HAL_OK) + if (HAL_FLASHEx_Erase(&EraseInitStruct, (uint32_t *)&SECTORError) != HAL_OK) { result = -RT_ERROR; goto __exit; diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_l4.c b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_l4.c index caafce2466..37fce587a9 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_l4.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_l4.c @@ -244,7 +244,7 @@ int stm32_flash_erase(long offset, size_t size) /* Get the 1st page to erase */ FirstPage = GetPage(addr); /* Get the number of pages to erase from 1st page */ - NbOfPages = GetPage(addr + size) - FirstPage + 1; + NbOfPages = GetPage(addr + size - 1) - FirstPage + 1; /* Get the bank */ BankNumber = GetBank(addr); /* Fill EraseInit structure*/ -- cgit v1.3.1 From 8f9c72b05e6320a591c4b620800b9b293151edc5 Mon Sep 17 00:00:00 2001 From: SummerGift Date: Thu, 20 Dec 2018 15:56:18 +0800 Subject: 【更新】：menuconfig 配置文件 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/stm32/libraries/templates/stm32f10x/.config | 5 ++++- bsp/stm32/libraries/templates/stm32f10x/rtconfig.h | 1 + bsp/stm32/libraries/templates/stm32f4xx/.config | 5 ++++- bsp/stm32/libraries/templates/stm32f4xx/rtconfig.h | 1 + bsp/stm32/libraries/templates/stm32f7xx/.config | 12 ++++++++---- bsp/stm32/libraries/templates/stm32f7xx/rtconfig.h | 11 +++++++++-- bsp/stm32/libraries/templates/stm32l4xx/.config | 5 ++++- bsp/stm32/libraries/templates/stm32l4xx/rtconfig.h | 1 + 8 files changed, 32 insertions(+), 9 deletions(-) (limited to 'bsp/stm32/libraries') diff --git a/bsp/stm32/libraries/templates/stm32f10x/.config b/bsp/stm32/libraries/templates/stm32f10x/.config index 4a931cf1e2..b74dd34859 100644 --- a/bsp/stm32/libraries/templates/stm32f10x/.config +++ b/bsp/stm32/libraries/templates/stm32f10x/.config @@ -62,6 +62,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x40000 CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y CONFIG_ARCH_ARM_CORTEX_M3=y @@ -180,12 +181,14 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set # # ARM CMSIS # # CONFIG_RT_USING_CMSIS_OS is not set # CONFIG_RT_USING_RTT_CMSIS is not set +# CONFIG_RT_USING_LWP is not set # # RT-Thread online packages @@ -278,6 +281,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_LITTLEVGL2RTT is not set # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set # # peripheral libraries and drivers @@ -340,7 +344,6 @@ CONFIG_SOC_STM32F103RB=y # CONFIG_BSP_USING_GPIO=y CONFIG_BSP_USING_UART1=y -# CONFIG_BSP_UART_USING_DMA_RX is not set # CONFIG_BSP_USING_SPI1 is not set # CONFIG_BSP_SPI_USING_DMA is not set # CONFIG_BSP_USING_I2C1 is not set diff --git a/bsp/stm32/libraries/templates/stm32f10x/rtconfig.h b/bsp/stm32/libraries/templates/stm32f10x/rtconfig.h index ed7bf5a5f7..908c0d760d 100644 --- a/bsp/stm32/libraries/templates/stm32f10x/rtconfig.h +++ b/bsp/stm32/libraries/templates/stm32f10x/rtconfig.h @@ -38,6 +38,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40000 #define ARCH_ARM #define ARCH_ARM_CORTEX_M #define ARCH_ARM_CORTEX_M3 diff --git a/bsp/stm32/libraries/templates/stm32f4xx/.config b/bsp/stm32/libraries/templates/stm32f4xx/.config index 935757f65a..ed06540dab 100644 --- a/bsp/stm32/libraries/templates/stm32f4xx/.config +++ b/bsp/stm32/libraries/templates/stm32f4xx/.config @@ -62,6 +62,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x40000 CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y CONFIG_ARCH_ARM_CORTEX_M4=y @@ -180,12 +181,14 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set # # ARM CMSIS # # CONFIG_RT_USING_CMSIS_OS is not set # CONFIG_RT_USING_RTT_CMSIS is not set +# CONFIG_RT_USING_LWP is not set # # RT-Thread online packages @@ -279,6 +282,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_LITTLEVGL2RTT is not set # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set # # peripheral libraries and drivers @@ -341,7 +345,6 @@ CONFIG_SOC_STM32F407ZG=y # CONFIG_BSP_USING_GPIO=y CONFIG_BSP_USING_UART1=y -# CONFIG_BSP_UART_USING_DMA_RX is not set # CONFIG_BSP_USING_SPI1 is not set # CONFIG_BSP_SPI_USING_DMA is not set # CONFIG_BSP_USING_I2C1 is not set diff --git a/bsp/stm32/libraries/templates/stm32f4xx/rtconfig.h b/bsp/stm32/libraries/templates/stm32f4xx/rtconfig.h index 21d3064ad0..b8700de08d 100644 --- a/bsp/stm32/libraries/templates/stm32f4xx/rtconfig.h +++ b/bsp/stm32/libraries/templates/stm32f4xx/rtconfig.h @@ -38,6 +38,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40000 #define ARCH_ARM #define ARCH_ARM_CORTEX_M #define ARCH_ARM_CORTEX_M4 diff --git a/bsp/stm32/libraries/templates/stm32f7xx/.config b/bsp/stm32/libraries/templates/stm32f7xx/.config index 1491b26f9a..5b2fbd74ae 100644 --- a/bsp/stm32/libraries/templates/stm32f7xx/.config +++ b/bsp/stm32/libraries/templates/stm32f7xx/.config @@ -62,9 +62,10 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x40000 CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y -CONFIG_ARCH_ARM_CORTEX_M4=y +CONFIG_ARCH_ARM_CORTEX_M7=y # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # @@ -110,6 +111,7 @@ CONFIG_FINSH_ARG_MAX=10 CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set @@ -179,12 +181,14 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set # # ARM CMSIS # # CONFIG_RT_USING_CMSIS_OS is not set # CONFIG_RT_USING_RTT_CMSIS is not set +# CONFIG_RT_USING_LWP is not set # # RT-Thread online packages @@ -278,6 +282,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_LITTLEVGL2RTT is not set # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set # # peripheral libraries and drivers @@ -324,12 +329,12 @@ CONFIG_RT_USING_PIN=y # # CONFIG_PKG_USING_HELLO is not set CONFIG_SOC_FAMILY_STM32=y -CONFIG_SOC_SERIES_STM32F4=y +CONFIG_SOC_SERIES_STM32F7=y # # Hardware Drivers Config # -CONFIG_SOC_STM32F407ZG=y +CONFIG_SOC_STM32F767IG=y # # Onboard Peripheral Drivers @@ -340,7 +345,6 @@ CONFIG_SOC_STM32F407ZG=y # CONFIG_BSP_USING_GPIO=y CONFIG_BSP_USING_UART1=y -# CONFIG_BSP_UART_USING_DMA_RX is not set # CONFIG_BSP_USING_SPI1 is not set # CONFIG_BSP_SPI_USING_DMA is not set # CONFIG_BSP_USING_I2C1 is not set diff --git a/bsp/stm32/libraries/templates/stm32f7xx/rtconfig.h b/bsp/stm32/libraries/templates/stm32f7xx/rtconfig.h index 01f98d0c58..f1dff62d4b 100644 --- a/bsp/stm32/libraries/templates/stm32f7xx/rtconfig.h +++ b/bsp/stm32/libraries/templates/stm32f7xx/rtconfig.h @@ -39,6 +39,9 @@ #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" #define RT_VER_NUM 0x40000 +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M7 /* RT-Thread Components */ @@ -74,6 +77,7 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA #define RT_USING_PIN /* Using WiFi */ @@ -105,6 +109,9 @@ /* Utilities */ +/* ARM CMSIS */ + + /* RT-Thread online packages */ /* IoT - internet of things */ @@ -149,6 +156,8 @@ /* example package: hello */ +#define SOC_FAMILY_STM32 +#define SOC_SERIES_STM32F7 /* Hardware Drivers Config */ @@ -156,8 +165,6 @@ /* Onboard Peripheral Drivers */ -#define BSP_USING_USB_TO_USART - /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO diff --git a/bsp/stm32/libraries/templates/stm32l4xx/.config b/bsp/stm32/libraries/templates/stm32l4xx/.config index 233ed0577f..2ace5a3beb 100644 --- a/bsp/stm32/libraries/templates/stm32l4xx/.config +++ b/bsp/stm32/libraries/templates/stm32l4xx/.config @@ -62,6 +62,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=256 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x40000 CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y CONFIG_ARCH_ARM_CORTEX_M4=y @@ -180,12 +181,14 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set # # ARM CMSIS # # CONFIG_RT_USING_CMSIS_OS is not set # CONFIG_RT_USING_RTT_CMSIS is not set +# CONFIG_RT_USING_LWP is not set # # RT-Thread online packages @@ -279,6 +282,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_LITTLEVGL2RTT is not set # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set # # peripheral libraries and drivers @@ -341,7 +345,6 @@ CONFIG_SOC_STM32L475VE=y # CONFIG_BSP_USING_GPIO=y CONFIG_BSP_USING_UART1=y -# CONFIG_BSP_UART_USING_DMA_RX is not set # CONFIG_BSP_USING_SPI1 is not set # CONFIG_BSP_SPI_USING_DMA is not set # CONFIG_BSP_USING_I2C1 is not set diff --git a/bsp/stm32/libraries/templates/stm32l4xx/rtconfig.h b/bsp/stm32/libraries/templates/stm32l4xx/rtconfig.h index 1b16eff99f..512a1832ce 100644 --- a/bsp/stm32/libraries/templates/stm32l4xx/rtconfig.h +++ b/bsp/stm32/libraries/templates/stm32l4xx/rtconfig.h @@ -38,6 +38,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 256 #define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40000 #define ARCH_ARM #define ARCH_ARM_CORTEX_M #define ARCH_ARM_CORTEX_M4 -- cgit v1.3.1 From 96fcf5dc291e9ce459d92e4aabb3bd9bfa48eb2c Mon Sep 17 00:00:00 2001 From: SummerGift Date: Thu, 20 Dec 2018 16:08:57 +0800 Subject: [bsp][stm32] update templates Kconfig --- bsp/stm32/libraries/templates/stm32f10x/board/Kconfig | 4 ---- bsp/stm32/libraries/templates/stm32f4xx/board/Kconfig | 4 ---- bsp/stm32/libraries/templates/stm32l4xx/board/Kconfig | 4 ---- 3 files changed, 12 deletions(-) (limited to 'bsp/stm32/libraries') diff --git a/bsp/stm32/libraries/templates/stm32f10x/board/Kconfig b/bsp/stm32/libraries/templates/stm32f10x/board/Kconfig index 20427606ef..39a000d371 100644 --- a/bsp/stm32/libraries/templates/stm32f10x/board/Kconfig +++ b/bsp/stm32/libraries/templates/stm32f10x/board/Kconfig @@ -21,10 +21,6 @@ menu "On-chip Peripheral Drivers" select RT_USING_SERIAL default y - config BSP_UART_USING_DMA_RX - bool "Enable UART RX DMA support" - default n - config BSP_USING_SPI1 bool "Enable SPI1 BUS" select RT_USING_SPI diff --git a/bsp/stm32/libraries/templates/stm32f4xx/board/Kconfig b/bsp/stm32/libraries/templates/stm32f4xx/board/Kconfig index 7889393544..5ba6059541 100644 --- a/bsp/stm32/libraries/templates/stm32f4xx/board/Kconfig +++ b/bsp/stm32/libraries/templates/stm32f4xx/board/Kconfig @@ -21,10 +21,6 @@ menu "On-chip Peripheral Drivers" select RT_USING_SERIAL default y - config BSP_UART_USING_DMA_RX - bool "Enable UART RX DMA support" - default n - config BSP_USING_SPI1 bool "Enable SPI1 BUS" select RT_USING_SPI diff --git a/bsp/stm32/libraries/templates/stm32l4xx/board/Kconfig b/bsp/stm32/libraries/templates/stm32l4xx/board/Kconfig index 2f87aceeb5..5d0299fe3b 100644 --- a/bsp/stm32/libraries/templates/stm32l4xx/board/Kconfig +++ b/bsp/stm32/libraries/templates/stm32l4xx/board/Kconfig @@ -21,10 +21,6 @@ menu "On-chip Peripheral Drivers" select RT_USING_SERIAL default y - config BSP_UART_USING_DMA_RX - bool "Enable UART RX DMA support" - default n - config BSP_USING_SPI1 bool "Enable SPI1 BUS" select RT_USING_SPI -- cgit v1.3.1