From cd267a30e4151c306d2de84c8431c5f6e34db47c Mon Sep 17 00:00:00 2001 From: xuzhuoyi Date: Thu, 3 Oct 2019 22:29:13 +0800 Subject: [bsp][stm32][stm32g431-st-nucleo] Add stm32g431-st-nucleo bsp --- .../libraries/HAL_Drivers/config/g4/adc_config.h | 87 +++++++ .../libraries/HAL_Drivers/config/g4/dma_config.h | 284 +++++++++++++++++++++ .../HAL_Drivers/config/g4/pulse_encoder_config.h | 68 +++++ .../libraries/HAL_Drivers/config/g4/pwm_config.h | 79 ++++++ .../libraries/HAL_Drivers/config/g4/qspi_config.h | 56 ++++ .../libraries/HAL_Drivers/config/g4/sdio_config.h | 44 ++++ .../libraries/HAL_Drivers/config/g4/spi_config.h | 195 ++++++++++++++ .../libraries/HAL_Drivers/config/g4/tim_config.h | 67 +++++ .../libraries/HAL_Drivers/config/g4/uart_config.h | 223 ++++++++++++++++ .../HAL_Drivers/config/g4/usbd_fs_config.h | 15 ++ bsp/stm32/libraries/HAL_Drivers/drv_config.h | 11 + bsp/stm32/libraries/HAL_Drivers/drv_dma.h | 4 +- bsp/stm32/libraries/HAL_Drivers/drv_usart.c | 14 +- bsp/stm32/libraries/HAL_Drivers/drv_usart.h | 5 +- bsp/stm32/libraries/STM32G4xx_HAL/SConscript | 3 +- 15 files changed, 1145 insertions(+), 10 deletions(-) create mode 100644 bsp/stm32/libraries/HAL_Drivers/config/g4/adc_config.h create mode 100644 bsp/stm32/libraries/HAL_Drivers/config/g4/dma_config.h create mode 100644 bsp/stm32/libraries/HAL_Drivers/config/g4/pulse_encoder_config.h create mode 100644 bsp/stm32/libraries/HAL_Drivers/config/g4/pwm_config.h create mode 100644 bsp/stm32/libraries/HAL_Drivers/config/g4/qspi_config.h create mode 100644 bsp/stm32/libraries/HAL_Drivers/config/g4/sdio_config.h create mode 100644 bsp/stm32/libraries/HAL_Drivers/config/g4/spi_config.h create mode 100644 bsp/stm32/libraries/HAL_Drivers/config/g4/tim_config.h create mode 100644 bsp/stm32/libraries/HAL_Drivers/config/g4/uart_config.h create mode 100644 bsp/stm32/libraries/HAL_Drivers/config/g4/usbd_fs_config.h (limited to 'bsp/stm32/libraries') diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g4/adc_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g4/adc_config.h new file mode 100644 index 0000000000..bda1a06485 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/g4/adc_config.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-06 zylx first version + */ + +#ifndef __ADC_CONFIG_H__ +#define __ADC_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_ADC1 +#ifndef ADC1_CONFIG +#define ADC1_CONFIG \ + { \ + .Instance = ADC1, \ + .Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \ + .Init.Resolution = ADC_RESOLUTION_12B, \ + .Init.DataAlign = ADC_DATAALIGN_RIGHT, \ + .Init.ScanConvMode = DISABLE, \ + .Init.EOCSelection = DISABLE, \ + .Init.ContinuousConvMode = DISABLE, \ + .Init.NbrOfConversion = 1, \ + .Init.DiscontinuousConvMode = DISABLE, \ + .Init.NbrOfDiscConversion = 0, \ + .Init.ExternalTrigConv = ADC_SOFTWARE_START, \ + .Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \ + .Init.DMAContinuousRequests = DISABLE, \ + } +#endif /* ADC1_CONFIG */ +#endif /* BSP_USING_ADC1 */ + +#ifdef BSP_USING_ADC2 +#ifndef ADC2_CONFIG +#define ADC2_CONFIG \ + { \ + .Instance = ADC2, \ + .Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \ + .Init.Resolution = ADC_RESOLUTION_12B, \ + .Init.DataAlign = ADC_DATAALIGN_RIGHT, \ + .Init.ScanConvMode = DISABLE, \ + .Init.EOCSelection = DISABLE, \ + .Init.ContinuousConvMode = DISABLE, \ + .Init.NbrOfConversion = 1, \ + .Init.DiscontinuousConvMode = DISABLE, \ + .Init.NbrOfDiscConversion = 0, \ + .Init.ExternalTrigConv = ADC_SOFTWARE_START, \ + .Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \ + .Init.DMAContinuousRequests = DISABLE, \ + } +#endif /* ADC2_CONFIG */ +#endif /* BSP_USING_ADC2 */ + +#ifdef BSP_USING_ADC3 +#ifndef ADC3_CONFIG +#define ADC3_CONFIG \ + { \ + .Instance = ADC3, \ + .Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \ + .Init.Resolution = ADC_RESOLUTION_12B, \ + .Init.DataAlign = ADC_DATAALIGN_RIGHT, \ + .Init.ScanConvMode = DISABLE, \ + .Init.EOCSelection = DISABLE, \ + .Init.ContinuousConvMode = DISABLE, \ + .Init.NbrOfConversion = 1, \ + .Init.DiscontinuousConvMode = DISABLE, \ + .Init.NbrOfDiscConversion = 0, \ + .Init.ExternalTrigConv = ADC_SOFTWARE_START, \ + .Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \ + .Init.DMAContinuousRequests = DISABLE, \ + } +#endif /* ADC3_CONFIG */ +#endif /* BSP_USING_ADC3 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADC_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g4/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g4/dma_config.h new file mode 100644 index 0000000000..46411c5441 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/g4/dma_config.h @@ -0,0 +1,284 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-01-02 zylx first version + * 2019-01-08 SummerGift clean up the code + */ + +#ifndef __DMA_CONFIG_H__ +#define __DMA_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* DMA1 stream0 */ +#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) +#define SPI3_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler +#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI3_RX_DMA_INSTANCE DMA1_Stream0 +#define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0 +#define SPI3_RX_DMA_IRQ DMA1_Stream0_IRQn +#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE) +#define UART5_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler +#define UART5_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART5_RX_DMA_INSTANCE DMA1_Stream0 +#define UART5_RX_DMA_CHANNEL DMA_CHANNEL_4 +#define UART5_RX_DMA_IRQ DMA1_Stream0_IRQn +#elif defined(BSP_UART8_TX_USING_DMA) && !defined(UART8_TX_DMA_INSTANCE) +#define UART8_DMA_TX_IRQHandler DMA1_Stream0_IRQHandler +#define UART8_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART8_TX_DMA_INSTANCE DMA1_Stream0 +#define UART8_TX_DMA_CHANNEL DMA_CHANNEL_5 +#define UART8_TX_DMA_IRQ DMA1_Stream0_IRQn +#endif + +/* DMA1 stream1 */ +#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE) +#define UART3_DMA_RX_IRQHandler DMA1_Stream1_IRQHandler +#define UART3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART3_RX_DMA_INSTANCE DMA1_Stream1 +#define UART3_RX_DMA_CHANNEL DMA_CHANNEL_4 +#define UART3_RX_DMA_IRQ DMA1_Stream1_IRQn +#elif defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA_INSTANCE) +#define UART7_DMA_RX_IRQHandler DMA1_Stream1_IRQHandler +#define UART7_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART7_RX_DMA_INSTANCE DMA1_Stream1 +#define UART7_RX_DMA_CHANNEL DMA_CHANNEL_5 +#define UART7_RX_DMA_IRQ DMA1_Stream1_IRQn +#endif + +/* DMA1 stream2 */ +#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) +#define SPI3_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler +#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI3_RX_DMA_INSTANCE DMA1_Stream2 +#define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0 +#define SPI3_RX_DMA_IRQ DMA1_Stream2_IRQn +#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE) +#define UART4_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler +#define UART4_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART4_RX_DMA_INSTANCE DMA1_Stream2 +#define UART4_RX_DMA_CHANNEL DMA_CHANNEL_4 +#define UART4_RX_DMA_IRQ DMA1_Stream2_IRQn +#endif + +/* DMA1 stream3 */ +#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) +#define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler +#define SPI2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI2_RX_DMA_INSTANCE DMA1_Stream3 +#define SPI2_RX_DMA_CHANNEL DMA_CHANNEL_0 +#define SPI2_RX_DMA_IRQ DMA1_Stream3_IRQn +#elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE) +#define UART3_DMA_TX_IRQHandler DMA1_Stream3_IRQHandler +#define UART3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART3_TX_DMA_INSTANCE DMA1_Stream3 +#define UART3_TX_DMA_CHANNEL DMA_CHANNEL_4 +#define UART3_TX_DMA_IRQ DMA1_Stream3_IRQn +#elif defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA_INSTANCE) +#define UART7_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler +#define UART7_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART7_RX_DMA_INSTANCE DMA1_Stream3 +#define UART7_RX_DMA_CHANNEL DMA_CHANNEL_5 +#define UART7_RX_DMA_IRQ DMA1_Stream3_IRQn +#endif + +/* DMA1 stream4 */ +#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) +#define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler +#define SPI2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI2_TX_DMA_INSTANCE DMA1_Stream4 +#define SPI2_TX_DMA_CHANNEL DMA_CHANNEL_0 +#define SPI2_TX_DMA_IRQ DMA1_Stream4_IRQn +#elif defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE) +#define UART4_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler +#define UART4_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART4_TX_DMA_INSTANCE DMA1_Stream4 +#define UART4_TX_DMA_CHANNEL DMA_CHANNEL_4 +#define UART4_TX_DMA_IRQ DMA1_Stream4_IRQn +#endif + +/* DMA1 stream5 */ +#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) +#define SPI3_DMA_TX_IRQHandler DMA1_Stream5_IRQHandler +#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI3_TX_DMA_INSTANCE DMA1_Stream5 +#define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0 +#define SPI3_TX_DMA_IRQ DMA1_Stream5_IRQn +#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) +#define UART2_DMA_RX_IRQHandler DMA1_Stream5_IRQHandler +#define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART2_RX_DMA_INSTANCE DMA1_Stream5 +#define UART2_RX_DMA_CHANNEL DMA_CHANNEL_4 +#define UART2_RX_DMA_IRQ DMA1_Stream5_IRQn +#endif + +/* DMA1 stream6 */ +#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) +#define UART2_DMA_TX_IRQHandler DMA1_Stream6_IRQHandler +#define UART2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART2_TX_DMA_INSTANCE DMA1_Stream6 +#define UART2_TX_DMA_CHANNEL DMA_CHANNEL_4 +#define UART2_TX_DMA_IRQ DMA1_Stream6_IRQn +#elif defined(BSP_UART8_RX_USING_DMA) && !defined(UART8_RX_DMA_INSTANCE) +#define UART8_DMA_RX_IRQHandler DMA1_Stream6_IRQHandler +#define UART8_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART8_RX_DMA_INSTANCE DMA1_Stream6 +#define UART8_RX_DMA_CHANNEL DMA_CHANNEL_5 +#define UART8_RX_DMA_IRQ DMA1_Stream6_IRQn +#endif + +/* DMA1 stream7 */ +#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) +#define SPI3_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler +#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI3_TX_DMA_INSTANCE DMA1_Stream7 +#define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0 +#define SPI3_TX_DMA_IRQ DMA1_Stream7_IRQn +#elif defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE) +#define UART5_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler +#define UART5_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART5_TX_DMA_INSTANCE DMA1_Stream7 +#define UART5_TX_DMA_CHANNEL DMA_CHANNEL_4 +#define UART5_TX_DMA_IRQ DMA1_Stream7_IRQn +#endif + +/* DMA2 stream0 */ +#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) +#define SPI1_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler +#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI1_RX_DMA_INSTANCE DMA2_Stream0 +#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3 +#define SPI1_RX_DMA_IRQ DMA2_Stream0_IRQn +#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) +#define SPI4_DMA_TX_IRQHandler DMA2_Stream0_IRQHandler +#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI4_TX_DMA_INSTANCE DMA2_Stream0 +#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_4 +#define SPI4_TX_DMA_IRQ DMA2_Stream0_IRQn +#endif + +/* DMA2 stream1 */ +#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) +#define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler +#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI4_TX_DMA_INSTANCE DMA2_Stream1 +#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_4 +#define SPI4_TX_DMA_IRQ DMA2_Stream1_IRQn +#elif defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE) +#define UART6_DMA_RX_IRQHandler DMA2_Stream1_IRQHandler +#define UART6_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define UART6_RX_DMA_INSTANCE DMA2_Stream1 +#define UART6_RX_DMA_CHANNEL DMA_CHANNEL_5 +#define UART6_RX_DMA_IRQ DMA2_Stream1_IRQn +#endif + +/* DMA2 stream2 */ +#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) +#define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler +#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI1_RX_DMA_INSTANCE DMA2_Stream2 +#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3 +#define SPI1_RX_DMA_IRQ DMA2_Stream2_IRQn +#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) +#define UART1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler +#define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define UART1_RX_DMA_INSTANCE DMA2_Stream2 +#define UART1_RX_DMA_CHANNEL DMA_CHANNEL_4 +#define UART1_RX_DMA_IRQ DMA2_Stream2_IRQn +#endif + +/* DMA2 stream3 */ +#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE) +#define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler +#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI5_RX_DMA_INSTANCE DMA2_Stream3 +#define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_2 +#define SPI5_RX_DMA_IRQ DMA2_Stream3_IRQn +#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) +#define SPI1_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler +#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI1_TX_DMA_INSTANCE DMA2_Stream3 +#define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3 +#define SPI1_TX_DMA_IRQ DMA2_Stream3_IRQn +#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) +#define SPI4_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler +#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI4_TX_DMA_INSTANCE DMA2_Stream3 +#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_5 +#define SPI4_TX_DMA_IRQ DMA2_Stream3_IRQn +#endif + +/* DMA2 stream4 */ +#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE) +#define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler +#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI5_TX_DMA_INSTANCE DMA2_Stream4 +#define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_2 +#define SPI5_TX_DMA_IRQ DMA2_Stream4_IRQn +#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) +#define SPI4_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler +#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI4_TX_DMA_INSTANCE DMA2_Stream4 +#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_5 +#define SPI4_TX_DMA_IRQ DMA2_Stream4_IRQn +#endif + +/* DMA2 stream5 */ +#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) +#define SPI1_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler +#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI1_TX_DMA_INSTANCE DMA2_Stream5 +#define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3 +#define SPI1_TX_DMA_IRQ DMA2_Stream5_IRQn +#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) +#define UART1_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler +#define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define UART1_RX_DMA_INSTANCE DMA2_Stream5 +#define UART1_RX_DMA_CHANNEL DMA_CHANNEL_4 +#define UART1_RX_DMA_IRQ DMA2_Stream5_IRQn +#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE) +#define SPI5_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler +#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI5_RX_DMA_INSTANCE DMA2_Stream5 +#define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_7 +#define SPI5_RX_DMA_IRQ DMA2_Stream5_IRQn +#endif + +/* DMA2 stream6 */ +#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE) +#define SPI5_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler +#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI5_TX_DMA_INSTANCE DMA2_Stream6 +#define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_7 +#define SPI5_TX_DMA_IRQ DMA2_Stream6_IRQn +#elif defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA_INSTANCE) +#define UART6_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler +#define UART6_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define UART6_TX_DMA_INSTANCE DMA2_Stream6 +#define UART6_TX_DMA_CHANNEL DMA_CHANNEL_5 +#define UART6_TX_DMA_IRQ DMA2_Stream6_IRQn +#endif + +/* DMA2 stream7 */ +#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE) +#define UART1_DMA_TX_IRQHandler DMA2_Stream7_IRQHandler +#define UART1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define UART1_TX_DMA_INSTANCE DMA2_Stream7 +#define UART1_TX_DMA_CHANNEL DMA_CHANNEL_4 +#define UART1_TX_DMA_IRQ DMA2_Stream7_IRQn +#endif + +#ifdef __cplusplus +} +#endif + + +#endif /* __DMA_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g4/pulse_encoder_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g4/pulse_encoder_config.h new file mode 100644 index 0000000000..53320efda1 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/g4/pulse_encoder_config.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-08-23 balanceTWK first version + */ + +#ifndef __PULSE_ENCODER_CONFIG_H__ +#define __PULSE_ENCODER_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_PULSE_ENCODER1 +#ifndef PULSE_ENCODER1_CONFIG +#define PULSE_ENCODER1_CONFIG \ + { \ + .tim_handler.Instance = TIM1, \ + .encoder_irqn = TIM1_UP_TIM10_IRQn, \ + .name = "pulse1" \ + } +#endif /* PULSE_ENCODER1_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER1 */ + +#ifdef BSP_USING_PULSE_ENCODER2 +#ifndef PULSE_ENCODER2_CONFIG +#define PULSE_ENCODER2_CONFIG \ + { \ + .tim_handler.Instance = TIM2, \ + .encoder_irqn = TIM2_IRQn, \ + .name = "pulse2" \ + } +#endif /* PULSE_ENCODER2_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER2 */ + +#ifdef BSP_USING_PULSE_ENCODER3 +#ifndef PULSE_ENCODER3_CONFIG +#define PULSE_ENCODER3_CONFIG \ + { \ + .tim_handler.Instance = TIM3, \ + .encoder_irqn = TIM3_IRQn, \ + .name = "pulse3" \ + } +#endif /* PULSE_ENCODER3_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER3 */ + +#ifdef BSP_USING_PULSE_ENCODER4 +#ifndef PULSE_ENCODER4_CONFIG +#define PULSE_ENCODER4_CONFIG \ + { \ + .tim_handler.Instance = TIM4, \ + .encoder_irqn = TIM4_IRQn, \ + .name = "pulse4" \ + } +#endif /* PULSE_ENCODER4_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER4 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PULSE_ENCODER_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g4/pwm_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g4/pwm_config.h new file mode 100644 index 0000000000..14d4aa2aff --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/g4/pwm_config.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-13 zylx first version + */ + +#ifndef __PWM_CONFIG_H__ +#define __PWM_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_PWM2 +#ifndef PWM2_CONFIG +#define PWM2_CONFIG \ + { \ + .tim_handle.Instance = TIM2, \ + .name = "pwm2", \ + .channel = 0 \ + } +#endif /* PWM2_CONFIG */ +#endif /* BSP_USING_PWM2 */ + +#ifdef BSP_USING_PWM3 +#ifndef PWM3_CONFIG +#define PWM3_CONFIG \ + { \ + .tim_handle.Instance = TIM3, \ + .name = "pwm3", \ + .channel = 0 \ + } +#endif /* PWM3_CONFIG */ +#endif /* BSP_USING_PWM3 */ + +#ifdef BSP_USING_PWM4 +#ifndef PWM4_CONFIG +#define PWM4_CONFIG \ + { \ + .tim_handle.Instance = TIM4, \ + .name = "pwm4", \ + .channel = 0 \ + } +#endif /* PWM4_CONFIG */ +#endif /* BSP_USING_PWM4 */ + +#ifdef BSP_USING_PWM5 +#ifndef PWM5_CONFIG +#define PWM5_CONFIG \ + { \ + .tim_handle.Instance = TIM5, \ + .name = "pwm5", \ + .channel = 0 \ + } +#endif /* PWM5_CONFIG */ +#endif /* BSP_USING_PWM5 */ + +#ifdef BSP_USING_PWM12 +#ifndef PWM12_CONFIG +#define PWM12_CONFIG \ + { \ + .tim_handle.Instance = TIM12, \ + .name = "pwm12", \ + .channel = 0 \ + } +#endif /* PWM12_CONFIG */ +#endif /* BSP_USING_PWM12 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PWM_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g4/qspi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g4/qspi_config.h new file mode 100644 index 0000000000..8450dc257f --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/g4/qspi_config.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-22 zylx first version + */ + +#ifndef __QSPI_CONFIG_H__ +#define __QSPI_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_QSPI +#ifndef QSPI_BUS_CONFIG +#define QSPI_BUS_CONFIG \ + { \ + .Instance = QUADSPI, \ + .Init.FifoThreshold = 4, \ + .Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE, \ + .Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_5_CYCLE, \ + } +#endif /* QSPI_BUS_CONFIG */ +#endif /* BSP_USING_QSPI */ + +#ifdef BSP_QSPI_USING_DMA +#ifndef QSPI_DMA_CONFIG +#define QSPI_DMA_CONFIG \ + { \ + .Instance = QSPI_DMA_INSTANCE, \ + .Init.Channel = QSPI_DMA_CHANNEL, \ + .Init.Direction = DMA_PERIPH_TO_MEMORY, \ + .Init.PeriphInc = DMA_PINC_DISABLE, \ + .Init.MemInc = DMA_MINC_ENABLE, \ + .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE, \ + .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE, \ + .Init.Mode = DMA_NORMAL, \ + .Init.Priority = DMA_PRIORITY_LOW \ + } +#endif /* QSPI_DMA_CONFIG */ +#endif /* BSP_QSPI_USING_DMA */ + +#define QSPI_IRQn QUADSPI_IRQn +#define QSPI_IRQHandler QUADSPI_IRQHandler + +#ifdef __cplusplus +} +#endif + +#endif /* __QSPI_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g4/sdio_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g4/sdio_config.h new file mode 100644 index 0000000000..7d6837d74f --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/g4/sdio_config.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-13 BalanceTWK first version + */ + +#ifndef __SDIO_CONFIG_H__ +#define __SDIO_CONFIG_H__ + +#include +#include "stm32g4xx_hal.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_SDIO +#define SDIO_BUS_CONFIG \ + { \ + .Instance = SDIO, \ + .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ + .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ + .dma_rx.Instance = DMA2_Stream3, \ + .dma_rx.channel = DMA_CHANNEL_4, \ + .dma_rx.dma_irq = DMA2_Stream3_IRQn, \ + .dma_tx.Instance = DMA2_Stream6, \ + .dma_tx.channel = DMA_CHANNEL_4, \ + .dma_tx.dma_irq = DMA2_Stream6_IRQn, \ + } + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /*__SDIO_CONFIG_H__ */ + + + diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g4/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g4/spi_config.h new file mode 100644 index 0000000000..34b0590eb3 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/g4/spi_config.h @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-06 SummerGift first version + * 2019-01-03 zylx modify DMA support + */ + +#ifndef __SPI_CONFIG_H__ +#define __SPI_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_SPI1 +#ifndef SPI1_BUS_CONFIG +#define SPI1_BUS_CONFIG \ + { \ + .Instance = SPI1, \ + .bus_name = "spi1", \ + } +#endif /* SPI1_BUS_CONFIG */ +#endif /* BSP_USING_SPI1 */ + +#ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_CONFIG +#define SPI1_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI1_TX_DMA_RCC, \ + .Instance = SPI1_TX_DMA_INSTANCE, \ + .channel = SPI1_TX_DMA_CHANNEL, \ + .dma_irq = SPI1_TX_DMA_IRQ, \ + } +#endif /* SPI1_TX_DMA_CONFIG */ +#endif /* BSP_SPI1_TX_USING_DMA */ + +#ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_CONFIG +#define SPI1_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI1_RX_DMA_RCC, \ + .Instance = SPI1_RX_DMA_INSTANCE, \ + .channel = SPI1_RX_DMA_CHANNEL, \ + .dma_irq = SPI1_RX_DMA_IRQ, \ + } +#endif /* SPI1_RX_DMA_CONFIG */ +#endif /* BSP_SPI1_RX_USING_DMA */ + +#ifdef BSP_USING_SPI2 +#ifndef SPI2_BUS_CONFIG +#define SPI2_BUS_CONFIG \ + { \ + .Instance = SPI2, \ + .bus_name = "spi2", \ + } +#endif /* SPI2_BUS_CONFIG */ +#endif /* BSP_USING_SPI2 */ + +#ifdef BSP_SPI2_TX_USING_DMA +#ifndef SPI2_TX_DMA_CONFIG +#define SPI2_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI2_TX_DMA_RCC, \ + .Instance = SPI2_TX_DMA_INSTANCE, \ + .channel = SPI2_TX_DMA_CHANNEL, \ + .dma_irq = SPI2_TX_DMA_IRQ, \ + } +#endif /* SPI2_TX_DMA_CONFIG */ +#endif /* BSP_SPI2_TX_USING_DMA */ + +#ifdef BSP_SPI2_RX_USING_DMA +#ifndef SPI2_RX_DMA_CONFIG +#define SPI2_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI2_RX_DMA_RCC, \ + .Instance = SPI2_RX_DMA_INSTANCE, \ + .channel = SPI2_RX_DMA_CHANNEL, \ + .dma_irq = SPI2_RX_DMA_IRQ, \ + } +#endif /* SPI2_RX_DMA_CONFIG */ +#endif /* BSP_SPI2_RX_USING_DMA */ + +#ifdef BSP_USING_SPI3 +#ifndef SPI3_BUS_CONFIG +#define SPI3_BUS_CONFIG \ + { \ + .Instance = SPI3, \ + .bus_name = "spi3", \ + } +#endif /* SPI3_BUS_CONFIG */ +#endif /* BSP_USING_SPI3 */ + +#ifdef BSP_SPI3_TX_USING_DMA +#ifndef SPI3_TX_DMA_CONFIG +#define SPI3_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI3_TX_DMA_RCC, \ + .Instance = SPI3_TX_DMA_INSTANCE, \ + .channel = SPI3_TX_DMA_CHANNEL, \ + .dma_irq = SPI3_TX_DMA_IRQ, \ + } +#endif /* SPI3_TX_DMA_CONFIG */ +#endif /* BSP_SPI3_TX_USING_DMA */ + +#ifdef BSP_SPI3_RX_USING_DMA +#ifndef SPI3_RX_DMA_CONFIG +#define SPI3_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI3_RX_DMA_RCC, \ + .Instance = SPI3_RX_DMA_INSTANCE, \ + .channel = SPI3_RX_DMA_CHANNEL, \ + .dma_irq = SPI3_RX_DMA_IRQ, \ + } +#endif /* SPI3_RX_DMA_CONFIG */ +#endif /* BSP_SPI3_RX_USING_DMA */ + +#ifdef BSP_USING_SPI4 +#ifndef SPI4_BUS_CONFIG +#define SPI4_BUS_CONFIG \ + { \ + .Instance = SPI4, \ + .bus_name = "spi4", \ + } +#endif /* SPI4_BUS_CONFIG */ +#endif /* BSP_USING_SPI4 */ + +#ifdef BSP_SPI4_TX_USING_DMA +#ifndef SPI4_TX_DMA_CONFIG +#define SPI4_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI4_TX_DMA_RCC, \ + .Instance = SPI4_TX_DMA_INSTANCE, \ + .channel = SPI4_TX_DMA_CHANNEL, \ + .dma_irq = SPI4_TX_DMA_IRQ, \ + } +#endif /* SPI4_TX_DMA_CONFIG */ +#endif /* BSP_SPI4_TX_USING_DMA */ + +#ifdef BSP_SPI4_RX_USING_DMA +#ifndef SPI4_RX_DMA_CONFIG +#define SPI4_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI4_RX_DMA_RCC, \ + .Instance = SPI4_RX_DMA_INSTANCE, \ + .channel = SPI4_RX_DMA_CHANNEL, \ + .dma_irq = SPI4_RX_DMA_IRQ, \ + } +#endif /* SPI4_RX_DMA_CONFIG */ +#endif /* BSP_SPI4_RX_USING_DMA */ + +#ifdef BSP_USING_SPI5 +#ifndef SPI5_BUS_CONFIG +#define SPI5_BUS_CONFIG \ + { \ + .Instance = SPI5, \ + .bus_name = "spi5", \ + } +#endif /* SPI5_BUS_CONFIG */ +#endif /* BSP_USING_SPI5 */ + +#ifdef BSP_SPI5_TX_USING_DMA +#ifndef SPI5_TX_DMA_CONFIG +#define SPI5_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI5_TX_DMA_RCC, \ + .Instance = SPI5_TX_DMA_INSTANCE, \ + .channel = SPI5_TX_DMA_CHANNEL, \ + .dma_irq = SPI5_TX_DMA_IRQ, \ + } +#endif /* SPI5_TX_DMA_CONFIG */ +#endif /* BSP_SPI5_TX_USING_DMA */ + +#ifdef BSP_SPI5_RX_USING_DMA +#ifndef SPI5_RX_DMA_CONFIG +#define SPI5_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI5_RX_DMA_RCC, \ + .Instance = SPI5_RX_DMA_INSTANCE, \ + .channel = SPI5_RX_DMA_CHANNEL, \ + .dma_irq = SPI5_RX_DMA_IRQ, \ + } +#endif /* SPI5_RX_DMA_CONFIG */ +#endif /* BSP_SPI5_RX_USING_DMA */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SPI_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g4/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g4/tim_config.h new file mode 100644 index 0000000000..cd116d9e19 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/g4/tim_config.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-11 zylx first version + */ + +#ifndef __TIM_CONFIG_H__ +#define __TIM_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef TIM_DEV_INFO_CONFIG +#define TIM_DEV_INFO_CONFIG \ + { \ + .maxfreq = 1000000, \ + .minfreq = 3000, \ + .maxcnt = 0xFFFF, \ + .cntmode = HWTIMER_CNTMODE_UP, \ + } +#endif /* TIM_DEV_INFO_CONFIG */ + +#ifdef BSP_USING_TIM11 +#ifndef TIM11_CONFIG +#define TIM11_CONFIG \ + { \ + .tim_handle.Instance = TIM11, \ + .tim_irqn = TIM1_TRG_COM_TIM11_IRQn, \ + .name = "timer11", \ + } +#endif /* TIM11_CONFIG */ +#endif /* BSP_USING_TIM11 */ + +#ifdef BSP_USING_TIM13 +#ifndef TIM13_CONFIG +#define TIM13_CONFIG \ + { \ + .tim_handle.Instance = TIM13, \ + .tim_irqn = TIM8_UP_TIM13_IRQn, \ + .name = "timer13", \ + } +#endif /* TIM13_CONFIG */ +#endif /* BSP_USING_TIM13 */ + +#ifdef BSP_USING_TIM14 +#ifndef TIM14_CONFIG +#define TIM14_CONFIG \ + { \ + .tim_handle.Instance = TIM14, \ + .tim_irqn = TIM8_TRG_COM_TIM14_IRQn, \ + .name = "timer14", \ + } +#endif /* TIM14_CONFIG */ +#endif /* BSP_USING_TIM14 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TIM_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g4/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g4/uart_config.h new file mode 100644 index 0000000000..5a77643a55 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/g4/uart_config.h @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-10-30 SummerGift first version + * 2019-01-03 zylx modify dma support + * 2019-10-03 xuzhuoyi modify for STM32G4 + */ + +#ifndef __UART_CONFIG_H__ +#define __UART_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(BSP_USING_LPUART1) +#ifndef LPUART1_CONFIG +#define LPUART1_CONFIG \ + { \ + .name = "lpuart1", \ + .Instance = LPUART1, \ + .irq_type = LPUART1_IRQn, \ + } +#endif /* LPUART1_CONFIG */ +#if defined(BSP_LPUART1_RX_USING_DMA) +#ifndef LPUART1_DMA_CONFIG +#define LPUART1_DMA_CONFIG \ + { \ + .Instance = LPUART1_RX_DMA_INSTANCE, \ + .request = LPUART1_RX_DMA_REQUEST, \ + .dma_rcc = LPUART1_RX_DMA_RCC, \ + .dma_irq = LPUART1_RX_DMA_IRQ, \ + } +#endif /* LPUART1_DMA_CONFIG */ +#endif /* BSP_LPUART1_RX_USING_DMA */ +#endif /* BSP_USING_LPUART1 */ + +#if defined(BSP_USING_UART1) +#ifndef UART1_CONFIG +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = USART1, \ + .irq_type = USART1_IRQn, \ + } +#endif /* UART1_CONFIG */ + +#if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_DMA_RX_CONFIG +#define UART1_DMA_RX_CONFIG \ + { \ + .Instance = UART1_RX_DMA_INSTANCE, \ + .channel = UART1_RX_DMA_CHANNEL, \ + .dma_rcc = UART1_RX_DMA_RCC, \ + .dma_irq = UART1_RX_DMA_IRQ, \ + } +#endif /* UART1_DMA_RX_CONFIG */ +#endif /* BSP_UART1_RX_USING_DMA */ + +#if defined(BSP_UART1_TX_USING_DMA) +#ifndef UART1_DMA_TX_CONFIG +#define UART1_DMA_TX_CONFIG \ + { \ + .Instance = UART1_TX_DMA_INSTANCE, \ + .channel = UART1_TX_DMA_CHANNEL, \ + .dma_rcc = UART1_TX_DMA_RCC, \ + .dma_irq = UART1_TX_DMA_IRQ, \ + } +#endif /* UART1_DMA_TX_CONFIG */ +#endif /* BSP_UART1_TX_USING_DMA */ +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +#ifndef UART2_CONFIG +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = USART2, \ + .irq_type = USART2_IRQn, \ + } +#endif /* UART2_CONFIG */ + +#if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_DMA_RX_CONFIG +#define UART2_DMA_RX_CONFIG \ + { \ + .Instance = UART2_RX_DMA_INSTANCE, \ + .channel = UART2_RX_DMA_CHANNEL, \ + .dma_rcc = UART2_RX_DMA_RCC, \ + .dma_irq = UART2_RX_DMA_IRQ, \ + } +#endif /* UART2_DMA_RX_CONFIG */ +#endif /* BSP_UART2_RX_USING_DMA */ + +#if defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_DMA_TX_CONFIG +#define UART2_DMA_TX_CONFIG \ + { \ + .Instance = UART2_TX_DMA_INSTANCE, \ + .channel = UART2_TX_DMA_CHANNEL, \ + .dma_rcc = UART2_TX_DMA_RCC, \ + .dma_irq = UART2_TX_DMA_IRQ, \ + } +#endif /* UART2_DMA_TX_CONFIG */ +#endif /* BSP_UART2_TX_USING_DMA */ +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +#ifndef UART3_CONFIG +#define UART3_CONFIG \ + { \ + .name = "uart3", \ + .Instance = USART3, \ + .irq_type = USART3_IRQn, \ + } +#endif /* UART3_CONFIG */ + +#if defined(BSP_UART3_RX_USING_DMA) +#ifndef UART3_DMA_RX_CONFIG +#define UART3_DMA_RX_CONFIG \ + { \ + .Instance = UART3_RX_DMA_INSTANCE, \ + .channel = UART3_RX_DMA_CHANNEL, \ + .dma_rcc = UART3_RX_DMA_RCC, \ + .dma_irq = UART3_RX_DMA_IRQ, \ + } +#endif /* UART3_DMA_RX_CONFIG */ +#endif /* BSP_UART3_RX_USING_DMA */ + +#if defined(BSP_UART3_TX_USING_DMA) +#ifndef UART3_DMA_TX_CONFIG +#define UART3_DMA_TX_CONFIG \ + { \ + .Instance = UART3_TX_DMA_INSTANCE, \ + .channel = UART3_TX_DMA_CHANNEL, \ + .dma_rcc = UART3_TX_DMA_RCC, \ + .dma_irq = UART3_TX_DMA_IRQ, \ + } +#endif /* UART3_DMA_TX_CONFIG */ +#endif /* BSP_UART3_TX_USING_DMA */ +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +#ifndef UART4_CONFIG +#define UART4_CONFIG \ + { \ + .name = "uart4", \ + .Instance = UART4, \ + .irq_type = UART4_IRQn, \ + } +#endif /* UART4_CONFIG */ + +#if defined(BSP_UART4_RX_USING_DMA) +#ifndef UART4_DMA_RX_CONFIG +#define UART4_DMA_RX_CONFIG \ + { \ + .Instance = UART4_RX_DMA_INSTANCE, \ + .channel = UART4_RX_DMA_CHANNEL, \ + .dma_rcc = UART4_RX_DMA_RCC, \ + .dma_irq = UART4_RX_DMA_IRQ, \ + } +#endif /* UART4_DMA_RX_CONFIG */ +#endif /* BSP_UART4_RX_USING_DMA */ + +#if defined(BSP_UART4_TX_USING_DMA) +#ifndef UART4_DMA_TX_CONFIG +#define UART4_DMA_TX_CONFIG \ + { \ + .Instance = UART4_TX_DMA_INSTANCE, \ + .channel = UART4_TX_DMA_CHANNEL, \ + .dma_rcc = UART4_TX_DMA_RCC, \ + .dma_irq = UART4_TX_DMA_IRQ, \ + } +#endif /* UART4_DMA_TX_CONFIG */ +#endif /* BSP_UART4_RX_USING_DMA */ +#endif /* BSP_USING_UART4 */ + +#if defined(BSP_USING_UART5) +#ifndef UART5_CONFIG +#define UART5_CONFIG \ + { \ + .name = "uart5", \ + .Instance = UART5, \ + .irq_type = UART5_IRQn, \ + } +#endif /* UART5_CONFIG */ + +#if defined(BSP_UART5_RX_USING_DMA) +#ifndef UART5_DMA_RX_CONFIG +#define UART5_DMA_RX_CONFIG \ + { \ + .Instance = UART5_RX_DMA_INSTANCE, \ + .channel = UART5_RX_DMA_CHANNEL, \ + .dma_rcc = UART5_RX_DMA_RCC, \ + .dma_irq = UART5_RX_DMA_IRQ, \ + } +#endif /* UART5_DMA_RX_CONFIG */ +#endif /* BSP_UART5_RX_USING_DMA */ + +#if defined(BSP_UART5_TX_USING_DMA) +#ifndef UART5_DMA_TX_CONFIG +#define UART5_DMA_TX_CONFIG \ + { \ + .Instance = UART5_TX_DMA_INSTANCE, \ + .channel = UART5_TX_DMA_CHANNEL, \ + .dma_rcc = UART5_TX_DMA_RCC, \ + .dma_irq = UART5_TX_DMA_IRQ, \ + } +#endif /* UART5_DMA_TX_CONFIG */ +#endif /* BSP_UART5_TX_USING_DMA */ +#endif /* BSP_USING_UART5 */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g4/usbd_fs_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g4/usbd_fs_config.h new file mode 100644 index 0000000000..b987356c7d --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/g4/usbd_fs_config.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-04-10 ZYH first version + */ +#ifndef __USBD_FS_CONFIG_H__ +#define __USBD_FS_CONFIG_H__ + +#define USBD_FS_IRQ_HANDLER OTG_FS_IRQHandler +#define USBD_INSTANCE USB_OTG_FS +#endif diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_config.h b/bsp/stm32/libraries/HAL_Drivers/drv_config.h index fa4555fe50..b10628e988 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drv_config.h @@ -83,6 +83,17 @@ extern "C" { #include "g0/adc_config.h" #include "g0/tim_config.h" #include "g0/pwm_config.h" +#elif defined(SOC_SERIES_STM32G4) +#include "g4/dma_config.h" +#include "g4/uart_config.h" +#include "g4/spi_config.h" +#include "g4/qspi_config.h" +#include "g4/usbd_fs_config.h" +#include "g4/adc_config.h" +#include "g4/tim_config.h" +#include "g4/sdio_config.h" +#include "g4/pwm_config.h" +#include "g4/pulse_encoder_config.h" #elif defined(SOC_SERIES_STM32H7) #include "h7/dma_config.h" #include "h7/uart_config.h" diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_dma.h b/bsp/stm32/libraries/HAL_Drivers/drv_dma.h index 6bff0b05f8..934579349a 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_dma.h +++ b/bsp/stm32/libraries/HAL_Drivers/drv_dma.h @@ -19,7 +19,7 @@ extern "C" { #endif #if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L0) \ - || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) + || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) #define DMA_INSTANCE_TYPE DMA_Channel_TypeDef #elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)\ || defined(SOC_SERIES_STM32H7) @@ -35,7 +35,7 @@ struct dma_config { rt_uint32_t channel; #endif -#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) +#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) rt_uint32_t request; #endif }; diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_usart.c b/bsp/stm32/libraries/HAL_Drivers/drv_usart.c index 79118e51b2..365d64aff4 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_usart.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_usart.c @@ -198,7 +198,8 @@ static int stm32_putc(struct rt_serial_device *serial, char c) uart = rt_container_of(serial, struct stm32_uart, serial); UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC); #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \ - || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) + || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) \ + || defined(SOC_SERIES_STM32G4) uart->handle.Instance->TDR = c; #else uart->handle.Instance->DR = c; @@ -218,7 +219,8 @@ static int stm32_getc(struct rt_serial_device *serial) if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET) { #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \ - || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) + || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) \ + || defined(SOC_SERIES_STM32G4) ch = uart->handle.Instance->RDR & 0xff; #else ch = uart->handle.Instance->DR & 0xff; @@ -330,7 +332,8 @@ static void uart_isr(struct rt_serial_device *serial) __HAL_UART_CLEAR_PEFLAG(&uart->handle); } #if !defined(SOC_SERIES_STM32L4) && !defined(SOC_SERIES_STM32F7) && !defined(SOC_SERIES_STM32F0) \ - && !defined(SOC_SERIES_STM32L0) && !defined(SOC_SERIES_STM32G0) && !defined(SOC_SERIES_STM32H7) + && !defined(SOC_SERIES_STM32L0) && !defined(SOC_SERIES_STM32G0) && !defined(SOC_SERIES_STM32H7) \ + && !defined(SOC_SERIES_STM32G4) if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBD) != RESET) { UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_LBD); @@ -741,7 +744,8 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ SET_BIT(RCC->AHBENR, dma_config->dma_rcc); tmpreg = READ_BIT(RCC->AHBENR, dma_config->dma_rcc); -#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) +#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) \ + || defined(SOC_SERIES_STM32G4) /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ SET_BIT(RCC->AHB1ENR, dma_config->dma_rcc); tmpreg = READ_BIT(RCC->AHB1ENR, dma_config->dma_rcc); @@ -763,7 +767,7 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) #elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) DMA_Handle->Instance = dma_config->Instance; DMA_Handle->Init.Channel = dma_config->channel; -#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) DMA_Handle->Instance = dma_config->Instance; DMA_Handle->Init.Request = dma_config->request; #endif diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_usart.h b/bsp/stm32/libraries/HAL_Drivers/drv_usart.h index c248a0dfd1..f8b0703a33 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_usart.h +++ b/bsp/stm32/libraries/HAL_Drivers/drv_usart.h @@ -21,14 +21,15 @@ int rt_hw_usart_init(void); #if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) \ - || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) + || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) #define DMA_INSTANCE_TYPE DMA_Channel_TypeDef #elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32H7) #define DMA_INSTANCE_TYPE DMA_Stream_TypeDef #endif /* defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) */ #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F2) \ - || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) + || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) \ + || defined(SOC_SERIES_STM32G4) #define UART_INSTANCE_CLEAR_FUNCTION __HAL_UART_CLEAR_FLAG #elif defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) #define UART_INSTANCE_CLEAR_FUNCTION __HAL_UART_CLEAR_IT diff --git a/bsp/stm32/libraries/STM32G4xx_HAL/SConscript b/bsp/stm32/libraries/STM32G4xx_HAL/SConscript index c7b2ec38b2..d367a99fc3 100644 --- a/bsp/stm32/libraries/STM32G4xx_HAL/SConscript +++ b/bsp/stm32/libraries/STM32G4xx_HAL/SConscript @@ -9,7 +9,6 @@ cwd = GetCurrentDir() src = Split(''' CMSIS/Device/ST/STM32G4xx/Source/Templates/system_stm32g4xx.c STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c -STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cec.c STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_crc.c STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cryp.c @@ -26,7 +25,9 @@ STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c if GetDepend(['RT_USING_SERIAL']): src += ['STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c'] + src += ['STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c'] src += ['STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_usart.c'] + src += ['STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_usart_ex.c'] if GetDepend(['RT_USING_I2C']): src += ['STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c'] -- cgit v1.3.1