From b9c660587680fc503ddec6717bd228630dd2d527 Mon Sep 17 00:00:00 2001 From: RTsien Date: Sat, 11 Jan 2014 15:04:19 +0800 Subject: add operating definitions of UART0 to UART5 --- bsp/beaglebone/drivers/serial.c | 233 ++++++++++++++++++++++++++++++++++------ 1 file changed, 203 insertions(+), 30 deletions(-) (limited to 'bsp') diff --git a/bsp/beaglebone/drivers/serial.c b/bsp/beaglebone/drivers/serial.c index b29ffc9963..077f78ea3b 100644 --- a/bsp/beaglebone/drivers/serial.c +++ b/bsp/beaglebone/drivers/serial.c @@ -10,6 +10,7 @@ * Change Logs: * Date Author Notes * 2013-07-06 Bernard the first version + * 2014-01-11 RTsien add definitions of UART0 to UART5 */ #include @@ -162,14 +163,18 @@ static const struct rt_uart_ops am33xx_uart_ops = am33xx_getc, }; -/* UART1 device driver structure */ -struct serial_ringbuffer uart1_int_rx; -struct am33xx_uart uart1 = +/* UART device driver structure */ +struct serial_ringbuffer uart_int_rx[6]; +struct am33xx_uart uart[6] = { - UART0_BASE, - UART0_INT, + {UART0_BASE,UART0_INT}, + {UART1_BASE,UART1_INT}, + {UART2_BASE,UART2_INT}, + {UART3_BASE,UART3_INT}, + {UART4_BASE,UART4_INT}, + {UART5_BASE,UART5_INT} }; -struct rt_serial_device serial1; +struct rt_serial_device serial[6]; #define write_reg(base, value) *(int*)(base) = value #define read_reg(base) *(int*)(base) @@ -219,11 +224,46 @@ static void start_uart_clk(void) ; /* enable uart1 */ +#ifdef RT_USING_UART1 CM_PER_UART1_CLKCTRL_REG(prcm_base) |= 0x2; /* wait for uart1 clk */ while ((CM_PER_UART1_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0) ; +#endif + +#ifdef RT_USING_UART2 + CM_PER_UART2_CLKCTRL_REG(prcm_base) |= 0x2; + + /* wait for uart2 clk */ + while ((CM_PER_UART2_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0) + ; +#endif + +#ifdef RT_USING_UART3 + CM_PER_UART3_CLKCTRL_REG(prcm_base) |= 0x2; + + /* wait for uart3 clk */ + while ((CM_PER_UART3_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0) + ; +#endif + +#ifdef RT_USING_UART4 + CM_PER_UART4_CLKCTRL_REG(prcm_base) |= 0x2; + + /* wait for uart4 clk */ + while ((CM_PER_UART4_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0) + ; +#endif + +#ifdef RT_USING_UART5 + CM_PER_UART5_CLKCTRL_REG(prcm_base) |= 0x2; + + /* wait for uart5 clk */ + while ((CM_PER_UART5_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0) + ; +#endif + /* Waiting for the L4LS UART clock */ while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & (1<<10))) ; @@ -236,44 +276,177 @@ static void config_pinmux(void) ctlm_base = AM33XX_CTLM_REGS; /* make sure the pin mux is OK for uart */ +#ifdef RT_USING_UART1 REG32(ctlm_base + 0x800 + 0x180) = 0x20; REG32(ctlm_base + 0x800 + 0x184) = 0x00; +#endif + +#ifdef RT_USING_UART2 + REG32(ctlm_base + 0x800 + 0x150) = 0x20; + REG32(ctlm_base + 0x800 + 0x154) = 0x00; +#endif + +#ifdef RT_USING_UART3 + REG32(ctlm_base + 0x800 + 0x164) = 0x01; +#endif + +#ifdef RT_USING_UART4 + REG32(ctlm_base + 0x800 + 0x070) = 0x26; + REG32(ctlm_base + 0x800 + 0x074) = 0x06; +#endif + +#ifdef RT_USING_UART5 + REG32(ctlm_base + 0x800 + 0x0C4) = 0x24; + REG32(ctlm_base + 0x800 + 0x0C0) = 0x04; +#endif + + } int rt_hw_serial_init(void) { - struct am33xx_uart* uart; - struct serial_configure config; - - uart = &uart1; - uart->base = UART1_BASE; + struct serial_configure config[6]; poweron_per_domain(); start_uart_clk(); config_pinmux(); - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - - serial1.ops = &am33xx_uart_ops; - serial1.int_rx = &uart1_int_rx; - serial1.config = config; - +#ifdef RT_USING_UART0 + config[0].baud_rate = BAUD_RATE_115200; + config[0].bit_order = BIT_ORDER_LSB; + config[0].data_bits = DATA_BITS_8; + config[0].parity = PARITY_NONE; + config[0].stop_bits = STOP_BITS_1; + config[0].invert = NRZ_NORMAL; + + serial[0].ops = &am33xx_uart_ops; + serial[0].int_rx = &uart_int_rx[0]; + serial[0].config = config[0]; /* enable RX interrupt */ - UART_IER_REG(uart->base) = 0x01; + UART_IER_REG(uart[0].base) = 0x01; /* install ISR */ - rt_hw_interrupt_install(uart->irq, am33xx_uart_isr, &serial1, "uart1"); - rt_hw_interrupt_control(uart->irq, 0, 0); - rt_hw_interrupt_mask(uart->irq); - - /* register UART1 device */ - rt_hw_serial_register(&serial1, "uart1", + rt_hw_interrupt_install(uart[0].irq, am33xx_uart_isr, &serial[0], "uart0"); + rt_hw_interrupt_control(uart[0].irq, 0, 0); + rt_hw_interrupt_mask(uart[0].irq); + /* register UART0 device */ + rt_hw_serial_register(&serial[0], "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart[0]); +#endif + +#ifdef RT_USING_UART1 + config[1].baud_rate = BAUD_RATE_115200; + config[1].bit_order = BIT_ORDER_LSB; + config[1].data_bits = DATA_BITS_8; + config[1].parity = PARITY_NONE; + config[1].stop_bits = STOP_BITS_1; + config[1].invert = NRZ_NORMAL; + + serial[1].ops = &am33xx_uart_ops; + serial[1].int_rx = &uart_int_rx[1]; + serial[1].config = config[1]; + /* enable RX interrupt */ + UART_IER_REG(uart[1].base) = 0x01; + /* install ISR */ + rt_hw_interrupt_install(uart[1].irq, am33xx_uart_isr, &serial[1], "uart1"); + rt_hw_interrupt_control(uart[1].irq, 0, 0); + rt_hw_interrupt_mask(uart[1].irq); + /* register UART0 device */ + rt_hw_serial_register(&serial[1], "uart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart[1]); +#endif + +#ifdef RT_USING_UART2 + config[2].baud_rate = BAUD_RATE_115200; + config[2].bit_order = BIT_ORDER_LSB; + config[2].data_bits = DATA_BITS_8; + config[2].parity = PARITY_NONE; + config[2].stop_bits = STOP_BITS_1; + config[2].invert = NRZ_NORMAL; + + serial[2].ops = &am33xx_uart_ops; + serial[2].int_rx = &uart_int_rx[2]; + serial[2].config = config[2]; + /* enable RX interrupt */ + UART_IER_REG(uart[2].base) = 0x01; + /* install ISR */ + rt_hw_interrupt_install(uart[2].irq, am33xx_uart_isr, &serial[2], "uart2"); + rt_hw_interrupt_control(uart[2].irq, 0, 0); + rt_hw_interrupt_mask(uart[2].irq); + /* register UART2 device */ + rt_hw_serial_register(&serial[2], "uart2", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart[2]); +#endif + +#ifdef RT_USING_UART3 + config[3].baud_rate = BAUD_RATE_115200; + config[3].bit_order = BIT_ORDER_LSB; + config[3].data_bits = DATA_BITS_8; + config[3].parity = PARITY_NONE; + config[3].stop_bits = STOP_BITS_1; + config[3].invert = NRZ_NORMAL; + serial[3].ops = &am33xx_uart_ops; + serial[3].int_rx = &uart_int_rx[3]; + serial[3].config = config[3]; + /* enable RX interrupt */ + UART_IER_REG(uart[3].base) = 0x01; + /* install ISR */ + rt_hw_interrupt_install(uart[3].irq, am33xx_uart_isr, &serial[3], "uart3"); + rt_hw_interrupt_control(uart[3].irq, 0, 0); + rt_hw_interrupt_mask(uart[3].irq); + /* register UART3 device */ + rt_hw_serial_register(&serial[3], "uart3", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart[3]); +#endif + +#ifdef RT_USING_UART4 + config[4].baud_rate = BAUD_RATE_115200; + config[4].bit_order = BIT_ORDER_LSB; + config[4].data_bits = DATA_BITS_8; + config[4].parity = PARITY_NONE; + config[4].stop_bits = STOP_BITS_1; + config[4].invert = NRZ_NORMAL; + + serial[4].ops = &am33xx_uart_ops; + serial[4].int_rx = &uart_int_rx[4]; + serial[4].config = config[4]; + /* enable RX interrupt */ + UART_IER_REG(uart[4].base) = 0x01; + /* install ISR */ + rt_hw_interrupt_install(uart[4].irq, am33xx_uart_isr, &serial[4], "uart4"); + rt_hw_interrupt_control(uart[4].irq, 0, 0); + rt_hw_interrupt_mask(uart[4].irq); + /* register UART4 device */ + rt_hw_serial_register(&serial[4], "uart4", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart[4]); +#endif + +#ifdef RT_USING_UART5 + config[5].baud_rate = BAUD_RATE_115200; + config[5].bit_order = BIT_ORDER_LSB; + config[5].data_bits = DATA_BITS_8; + config[5].parity = PARITY_NONE; + config[5].stop_bits = STOP_BITS_1; + config[5].invert = NRZ_NORMAL; + + serial[5].ops = &am33xx_uart_ops; + serial[5].int_rx = &uart_int_rx[5]; + serial[5].config = config[5]; + /* enable RX interrupt */ + UART_IER_REG(uart[5].base) = 0x01; + /* install ISR */ + rt_hw_interrupt_install(uart[5].irq, am33xx_uart_isr, &serial[5], "uart5"); + rt_hw_interrupt_control(uart[5].irq, 0, 0); + rt_hw_interrupt_mask(uart[5].irq); + /* register UART4 device */ + rt_hw_serial_register(&serial[5], "uart5", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - uart); + &uart[5]); +#endif return 0; } -- cgit v1.3.1 From faf3515e6bcbd049ca2a0eaea339fc687de7f8e0 Mon Sep 17 00:00:00 2001 From: RTsien Date: Sat, 11 Jan 2014 15:05:51 +0800 Subject: support UART0 to UART5 straightly --- bsp/beaglebone/drivers/serial.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'bsp') diff --git a/bsp/beaglebone/drivers/serial.c b/bsp/beaglebone/drivers/serial.c index 077f78ea3b..af93048ac9 100644 --- a/bsp/beaglebone/drivers/serial.c +++ b/bsp/beaglebone/drivers/serial.c @@ -10,7 +10,7 @@ * Change Logs: * Date Author Notes * 2013-07-06 Bernard the first version - * 2014-01-11 RTsien add definitions of UART0 to UART5 + * 2014-01-11 RTsien support UART0 to UART5 straightly */ #include -- cgit v1.3.1 From ef09b822b71795759a9bfbf5903e069b7b2668d6 Mon Sep 17 00:00:00 2001 From: RTsien Date: Sat, 11 Jan 2014 15:09:43 +0800 Subject: add RT_USING_UARTx and set console via uart0 --- bsp/beaglebone/rtconfig.h | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) (limited to 'bsp') diff --git a/bsp/beaglebone/rtconfig.h b/bsp/beaglebone/rtconfig.h index 27992c84cd..15326d74cf 100644 --- a/bsp/beaglebone/rtconfig.h +++ b/bsp/beaglebone/rtconfig.h @@ -73,6 +73,18 @@ #define RT_USING_DEVICE_IPC // #define RT_USING_SERIAL +// +#define RT_USING_UART0 +// +#define RT_USING_UART1 +// +#define RT_USING_UART2 +// +//#define RT_USING_UART3 +// +#define RT_USING_UART4 +// +#define RT_USING_UART5 // #define RT_UART_RX_BUFFER_SIZE 64 // @@ -84,7 +96,7 @@ // #define RT_CONSOLEBUF_SIZE 128 // -#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_CONSOLE_DEVICE_NAME "uart0" // // -- cgit v1.3.1 From d71b86c750d99ea2cb98b3e657f4f3baf104d3ea Mon Sep 17 00:00:00 2001 From: RTsien Date: Sat, 11 Jan 2014 22:03:51 +0800 Subject: friendly for uart count under 6 --- bsp/beaglebone/drivers/serial.c | 263 +++++++++++++++++++++++----------------- 1 file changed, 150 insertions(+), 113 deletions(-) (limited to 'bsp') diff --git a/bsp/beaglebone/drivers/serial.c b/bsp/beaglebone/drivers/serial.c index af93048ac9..d07621080b 100644 --- a/bsp/beaglebone/drivers/serial.c +++ b/bsp/beaglebone/drivers/serial.c @@ -39,7 +39,7 @@ static void am33xx_uart_isr(int irqno, void* param) iir = UART_IIR_REG(uart->base); - if ((iir & (0x02 << 1)) || (iir & (0x6 << 1))) + if ((iir & (0x02 << 1)) || (iir & (0x6 << 1))) { rt_hw_serial_isr(serial); } @@ -164,17 +164,65 @@ static const struct rt_uart_ops am33xx_uart_ops = }; /* UART device driver structure */ -struct serial_ringbuffer uart_int_rx[6]; -struct am33xx_uart uart[6] = +#ifdef RT_USING_UART0 +struct serial_ringbuffer uart0_int_rx; +struct am33xx_uart uart0 = +{ + UART0_BASE, + UART0_INT, +}; +struct rt_serial_device serial0; +#endif + +#ifdef RT_USING_UART1 +struct serial_ringbuffer uart1_int_rx; +struct am33xx_uart uart1 = +{ + UART1_BASE, + UART1_INT, +}; +struct rt_serial_device serial1; +#endif + +#ifdef RT_USING_UART2 +struct serial_ringbuffer uart2_int_rx; +struct am33xx_uart uart2 = { - {UART0_BASE,UART0_INT}, - {UART1_BASE,UART1_INT}, - {UART2_BASE,UART2_INT}, - {UART3_BASE,UART3_INT}, - {UART4_BASE,UART4_INT}, - {UART5_BASE,UART5_INT} + UART2_BASE, + UART2_INT, }; -struct rt_serial_device serial[6]; +struct rt_serial_device serial2; +#endif + +#ifdef RT_USING_UART3 +struct serial_ringbuffer uart3_int_rx; +struct am33xx_uart uart3 = +{ + UART3_BASE, + UART3_INT, +}; +struct rt_serial_device serial3; +#endif + +#ifdef RT_USING_UART4 +struct serial_ringbuffer uart4_int_rx; +struct am33xx_uart uart4 = +{ + UART4_BASE, + UART4_INT, +}; +struct rt_serial_device serial4; +#endif + +#ifdef RT_USING_UART5 +struct serial_ringbuffer uart5_int_rx; +struct am33xx_uart uart5 = +{ + UART5_BASE, + UART5_INT, +}; +struct rt_serial_device serial5; +#endif #define write_reg(base, value) *(int*)(base) = value #define read_reg(base) *(int*)(base) @@ -226,7 +274,6 @@ static void start_uart_clk(void) /* enable uart1 */ #ifdef RT_USING_UART1 CM_PER_UART1_CLKCTRL_REG(prcm_base) |= 0x2; - /* wait for uart1 clk */ while ((CM_PER_UART1_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0) ; @@ -234,7 +281,6 @@ static void start_uart_clk(void) #ifdef RT_USING_UART2 CM_PER_UART2_CLKCTRL_REG(prcm_base) |= 0x2; - /* wait for uart2 clk */ while ((CM_PER_UART2_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0) ; @@ -242,7 +288,6 @@ static void start_uart_clk(void) #ifdef RT_USING_UART3 CM_PER_UART3_CLKCTRL_REG(prcm_base) |= 0x2; - /* wait for uart3 clk */ while ((CM_PER_UART3_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0) ; @@ -250,7 +295,6 @@ static void start_uart_clk(void) #ifdef RT_USING_UART4 CM_PER_UART4_CLKCTRL_REG(prcm_base) |= 0x2; - /* wait for uart4 clk */ while ((CM_PER_UART4_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0) ; @@ -258,7 +302,6 @@ static void start_uart_clk(void) #ifdef RT_USING_UART5 CM_PER_UART5_CLKCTRL_REG(prcm_base) |= 0x2; - /* wait for uart5 clk */ while ((CM_PER_UART5_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0) ; @@ -299,156 +342,150 @@ static void config_pinmux(void) REG32(ctlm_base + 0x800 + 0x0C4) = 0x24; REG32(ctlm_base + 0x800 + 0x0C0) = 0x04; #endif - - } int rt_hw_serial_init(void) { - struct serial_configure config[6]; + struct serial_configure config; poweron_per_domain(); start_uart_clk(); config_pinmux(); #ifdef RT_USING_UART0 - config[0].baud_rate = BAUD_RATE_115200; - config[0].bit_order = BIT_ORDER_LSB; - config[0].data_bits = DATA_BITS_8; - config[0].parity = PARITY_NONE; - config[0].stop_bits = STOP_BITS_1; - config[0].invert = NRZ_NORMAL; - - serial[0].ops = &am33xx_uart_ops; - serial[0].int_rx = &uart_int_rx[0]; - serial[0].config = config[0]; + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + serial0.ops = &am33xx_uart_ops; + serial0.int_rx = &uart0_int_rx; + serial0.config = config; /* enable RX interrupt */ - UART_IER_REG(uart[0].base) = 0x01; + UART_IER_REG(uart0.base) = 0x01; /* install ISR */ - rt_hw_interrupt_install(uart[0].irq, am33xx_uart_isr, &serial[0], "uart0"); - rt_hw_interrupt_control(uart[0].irq, 0, 0); - rt_hw_interrupt_mask(uart[0].irq); + rt_hw_interrupt_install(uart0.irq, am33xx_uart_isr, &serial0, "uart0"); + rt_hw_interrupt_control(uart0.irq, 0, 0); + rt_hw_interrupt_mask(uart0.irq); /* register UART0 device */ - rt_hw_serial_register(&serial[0], "uart0", + rt_hw_serial_register(&serial0, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart[0]); + &uart0); #endif #ifdef RT_USING_UART1 - config[1].baud_rate = BAUD_RATE_115200; - config[1].bit_order = BIT_ORDER_LSB; - config[1].data_bits = DATA_BITS_8; - config[1].parity = PARITY_NONE; - config[1].stop_bits = STOP_BITS_1; - config[1].invert = NRZ_NORMAL; - - serial[1].ops = &am33xx_uart_ops; - serial[1].int_rx = &uart_int_rx[1]; - serial[1].config = config[1]; + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + serial1.ops = &am33xx_uart_ops; + serial1.int_rx = &uart1_int_rx; + serial1.config = config; /* enable RX interrupt */ - UART_IER_REG(uart[1].base) = 0x01; + UART_IER_REG(uart1.base) = 0x01; /* install ISR */ - rt_hw_interrupt_install(uart[1].irq, am33xx_uart_isr, &serial[1], "uart1"); - rt_hw_interrupt_control(uart[1].irq, 0, 0); - rt_hw_interrupt_mask(uart[1].irq); + rt_hw_interrupt_install(uart1.irq, am33xx_uart_isr, &serial1, "uart1"); + rt_hw_interrupt_control(uart1.irq, 0, 0); + rt_hw_interrupt_mask(uart1.irq); /* register UART0 device */ - rt_hw_serial_register(&serial[1], "uart1", + rt_hw_serial_register(&serial1, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart[1]); + &uart1); #endif #ifdef RT_USING_UART2 - config[2].baud_rate = BAUD_RATE_115200; - config[2].bit_order = BIT_ORDER_LSB; - config[2].data_bits = DATA_BITS_8; - config[2].parity = PARITY_NONE; - config[2].stop_bits = STOP_BITS_1; - config[2].invert = NRZ_NORMAL; - - serial[2].ops = &am33xx_uart_ops; - serial[2].int_rx = &uart_int_rx[2]; - serial[2].config = config[2]; + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + serial2.ops = &am33xx_uart_ops; + serial2.int_rx = &uart2_int_rx; + serial2.config = config; /* enable RX interrupt */ - UART_IER_REG(uart[2].base) = 0x01; + UART_IER_REG(uart2.base) = 0x01; /* install ISR */ - rt_hw_interrupt_install(uart[2].irq, am33xx_uart_isr, &serial[2], "uart2"); - rt_hw_interrupt_control(uart[2].irq, 0, 0); - rt_hw_interrupt_mask(uart[2].irq); + rt_hw_interrupt_install(uart2.irq, am33xx_uart_isr, &serial2, "uart2"); + rt_hw_interrupt_control(uart2.irq, 0, 0); + rt_hw_interrupt_mask(uart2.irq); /* register UART2 device */ - rt_hw_serial_register(&serial[2], "uart2", + rt_hw_serial_register(&serial2, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart[2]); + &uart2); #endif #ifdef RT_USING_UART3 - config[3].baud_rate = BAUD_RATE_115200; - config[3].bit_order = BIT_ORDER_LSB; - config[3].data_bits = DATA_BITS_8; - config[3].parity = PARITY_NONE; - config[3].stop_bits = STOP_BITS_1; - config[3].invert = NRZ_NORMAL; - serial[3].ops = &am33xx_uart_ops; - serial[3].int_rx = &uart_int_rx[3]; - serial[3].config = config[3]; + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + serial3.ops = &am33xx_uart_ops; + serial3.int_rx = &uart_3_int_rx; + serial3.config = config; /* enable RX interrupt */ - UART_IER_REG(uart[3].base) = 0x01; + UART_IER_REG(uart3.base) = 0x01; /* install ISR */ - rt_hw_interrupt_install(uart[3].irq, am33xx_uart_isr, &serial[3], "uart3"); - rt_hw_interrupt_control(uart[3].irq, 0, 0); - rt_hw_interrupt_mask(uart[3].irq); + rt_hw_interrupt_install(uart3.irq, am33xx_uart_isr, &serial3, "uart3"); + rt_hw_interrupt_control(uart3.irq, 0, 0); + rt_hw_interrupt_mask(uart3.irq); /* register UART3 device */ - rt_hw_serial_register(&serial[3], "uart3", + rt_hw_serial_register(&serial3, "uart3", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart[3]); + &uart3); #endif #ifdef RT_USING_UART4 - config[4].baud_rate = BAUD_RATE_115200; - config[4].bit_order = BIT_ORDER_LSB; - config[4].data_bits = DATA_BITS_8; - config[4].parity = PARITY_NONE; - config[4].stop_bits = STOP_BITS_1; - config[4].invert = NRZ_NORMAL; - - serial[4].ops = &am33xx_uart_ops; - serial[4].int_rx = &uart_int_rx[4]; - serial[4].config = config[4]; + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + + serial4.ops = &am33xx_uart_ops; + serial4.int_rx = &uart4_int_rx; + serial4.config = config; /* enable RX interrupt */ - UART_IER_REG(uart[4].base) = 0x01; + UART_IER_REG(uart4.base) = 0x01; /* install ISR */ - rt_hw_interrupt_install(uart[4].irq, am33xx_uart_isr, &serial[4], "uart4"); - rt_hw_interrupt_control(uart[4].irq, 0, 0); - rt_hw_interrupt_mask(uart[4].irq); + rt_hw_interrupt_install(uart4.irq, am33xx_uart_isr, &serial4, "uart4"); + rt_hw_interrupt_control(uart4.irq, 0, 0); + rt_hw_interrupt_mask(uart4.irq); /* register UART4 device */ - rt_hw_serial_register(&serial[4], "uart4", + rt_hw_serial_register(&serial4, "uart4", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart[4]); + &uart4); #endif #ifdef RT_USING_UART5 - config[5].baud_rate = BAUD_RATE_115200; - config[5].bit_order = BIT_ORDER_LSB; - config[5].data_bits = DATA_BITS_8; - config[5].parity = PARITY_NONE; - config[5].stop_bits = STOP_BITS_1; - config[5].invert = NRZ_NORMAL; + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; - serial[5].ops = &am33xx_uart_ops; - serial[5].int_rx = &uart_int_rx[5]; - serial[5].config = config[5]; + serial5.ops = &am33xx_uart_ops; + serial5.int_rx = &uart5_int_rx; + serial5.config = config; /* enable RX interrupt */ - UART_IER_REG(uart[5].base) = 0x01; + UART_IER_REG(uart5.base) = 0x01; /* install ISR */ - rt_hw_interrupt_install(uart[5].irq, am33xx_uart_isr, &serial[5], "uart5"); - rt_hw_interrupt_control(uart[5].irq, 0, 0); - rt_hw_interrupt_mask(uart[5].irq); + rt_hw_interrupt_install(uart5.irq, am33xx_uart_isr, &serial5, "uart5"); + rt_hw_interrupt_control(uart5.irq, 0, 0); + rt_hw_interrupt_mask(uart5.irq); /* register UART4 device */ - rt_hw_serial_register(&serial[5], "uart5", + rt_hw_serial_register(&serial5, "uart5", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart[5]); + &uart5); #endif return 0; } INIT_BOARD_EXPORT(rt_hw_serial_init); - -- cgit v1.3.1 From a4cd949519dc9d511ee9171b255e67c21128827e Mon Sep 17 00:00:00 2001 From: Bright Pan Date: Wed, 26 Feb 2014 11:22:08 +0800 Subject: Fix uart device driver for gpio remap and hardware flow control. Add uart4 and uart5 device driver. --- bsp/stm32f10x/drivers/board.h | 2 + bsp/stm32f10x/drivers/usart.c | 584 ++++++++++++++++++++++++++++++++---------- 2 files changed, 457 insertions(+), 129 deletions(-) (limited to 'bsp') diff --git a/bsp/stm32f10x/drivers/board.h b/bsp/stm32f10x/drivers/board.h index dc84db9c69..ebd121d631 100644 --- a/bsp/stm32f10x/drivers/board.h +++ b/bsp/stm32f10x/drivers/board.h @@ -41,6 +41,8 @@ #define RT_USING_UART1 #define RT_USING_UART2 #define RT_USING_UART3 +//#define RT_USING_UART4 +//#define RT_USING_UART5 #endif /* __BOARD_H__ */ diff --git a/bsp/stm32f10x/drivers/usart.c b/bsp/stm32f10x/drivers/usart.c index ae47db3a14..4bb320269b 100644 --- a/bsp/stm32f10x/drivers/usart.c +++ b/bsp/stm32f10x/drivers/usart.c @@ -21,25 +21,90 @@ #include /* USART1 */ -#define UART1_GPIO_TX GPIO_Pin_9 -#define UART1_GPIO_RX GPIO_Pin_10 -#define UART1_GPIO GPIOA +#define UART1_TX_PIN GPIO_Pin_9 +#define UART1_TX_GPIO GPIOA +#define UART1_RX_PIN GPIO_Pin_10 +#define UART1_RX_GPIO GPIOA + +#define UART1_CTS_PIN ((uint16_t)0x0000)// cts is disable +#define UART1_CTS_GPIO ((GPIO_TypeDef *)0x00000000) +#define UART1_RTS_PIN ((uint16_t)0x0000)// rts is disable +#define UART1_RTS_GPIO ((GPIO_TypeDef *)0x00000000) + +#define UART1_REMAP (((uint32_t)0x00000000))// remap is disable /* USART2 */ -#define UART2_GPIO_TX GPIO_Pin_2 -#define UART2_GPIO_RX GPIO_Pin_3 -#define UART2_GPIO GPIOA +#define UART2_TX_PIN GPIO_Pin_2 +#define UART2_TX_GPIO GPIOA +#define UART2_RX_PIN GPIO_Pin_3 +#define UART2_RX_GPIO GPIOA + +#define UART2_CTS_PIN ((uint16_t)0x0000)// cts is disable +#define UART2_CTS_GPIO ((GPIO_TypeDef *)0x00000000) +#define UART2_RTS_PIN ((uint16_t)0x0000)// rts is disable +#define UART2_RTS_GPIO ((GPIO_TypeDef *)0x00000000) + +#define UART2_REMAP (((uint32_t)0x00000000))// remap is disable + +/* USART3_REMAP[1:0] = 11 */ +#define UART3_TX_PIN GPIO_Pin_8 +#define UART3_TX_GPIO GPIOD +#define UART3_RX_PIN GPIO_Pin_9 +#define UART3_RX_GPIO GPIOD + +#define UART3_CTS_PIN ((uint16_t)0x0000)// cts is disable +#define UART3_CTS_GPIO ((GPIO_TypeDef *)0x00000000) +#define UART3_RTS_PIN ((uint16_t)0x0000)// rts is disable +#define UART3_RTS_GPIO ((GPIO_TypeDef *)0x00000000) + +#define UART3_REMAP GPIO_FullRemap_USART3 + +/* USART4 */ +#define UART4_TX_PIN GPIO_Pin_10 +#define UART4_TX_GPIO GPIOC +#define UART4_RX_PIN GPIO_Pin_11 +#define UART4_RX_GPIO GPIOC + +#define UART4_CTS_PIN ((uint16_t)0x0000)// cts is disable +#define UART4_CTS_GPIO ((GPIO_TypeDef *)0x00000000) +#define UART4_RTS_PIN ((uint16_t)0x0000)// rts is disable +#define UART4_RTS_GPIO ((GPIO_TypeDef *)0x00000000) + +#define UART4_REMAP (((uint32_t)0x00000000))// remap is disable -/* USART3_REMAP[1:0] = 00 */ -#define UART3_GPIO_TX GPIO_Pin_10 -#define UART3_GPIO_RX GPIO_Pin_11 -#define UART3_GPIO GPIOB +/* USART5 */ +#define UART5_TX_PIN GPIO_Pin_12 +#define UART5_TX_GPIO GPIOC +#define UART5_RX_PIN GPIO_Pin_2 +#define UART5_RX_GPIO GPIOD + +#define UART5_CTS_PIN ((uint16_t)0x0000)// cts is disable +#define UART5_CTS_GPIO ((GPIO_TypeDef *)0x00000000) +#define UART5_RTS_PIN ((uint16_t)0x0000)// rts is disable +#define UART5_RTS_GPIO ((GPIO_TypeDef *)0x00000000) + +#define UART4_REMAP (((uint32_t)0x00000000))// remap is disable /* STM32 uart driver */ struct stm32_uart { USART_TypeDef* uart_device; IRQn_Type irq; + + uint16_t uart_tx_pin; + GPIO_TypeDef *uart_tx_gpio; + + uint16_t uart_rx_pin; + GPIO_TypeDef *uart_rx_gpio; + + uint16_t uart_cts_pin; + GPIO_TypeDef *uart_cts_gpio; + + uint16_t uart_rts_pin; + GPIO_TypeDef *uart_rts_gpio; + + uint32_t uart_remap; + }; static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_configure *cfg) @@ -51,7 +116,7 @@ static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_c RT_ASSERT(cfg != RT_NULL); uart = (struct stm32_uart *)serial->parent.user_data; - + USART_StructInit(&USART_InitStructure); USART_InitStructure.USART_BaudRate = cfg->baud_rate; if (cfg->data_bits == DATA_BITS_8) @@ -62,8 +127,18 @@ static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_c else if (cfg->stop_bits == STOP_BITS_2) USART_InitStructure.USART_StopBits = USART_StopBits_2; - USART_InitStructure.USART_Parity = USART_Parity_No; - USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + if (cfg->parity == PARITY_NONE) + USART_InitStructure.USART_Parity = USART_Parity_No; + else if (cfg->parity == PARITY_EVEN) + USART_InitStructure.USART_Parity = USART_Parity_Even; + else if (cfg->parity == PARITY_ODD) + USART_InitStructure.USART_Parity = USART_Parity_Odd; + + if (cfg->hw_control == HW_CONTROL_NONE) + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + else if (cfg->hw_control == HW_CONTROL_RTS_CTS) + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_RTS_CTS; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; USART_Init(uart->uart_device, &USART_InitStructure); @@ -135,180 +210,327 @@ static const struct rt_uart_ops stm32_uart_ops = stm32_getc, }; +__STATIC_INLINE void serial_device_isr(struct rt_serial_device *serial) +{ + volatile int ch = 0; + struct stm32_uart *uart = serial->parent.user_data; + + /* process uart error */ + if(uart->uart_device->SR & (USART_FLAG_ORE | USART_FLAG_NE | USART_FLAG_FE | USART_FLAG_PE)) + { + ch = uart->uart_device->DR; // invalid read + while (uart->uart_device->SR & USART_FLAG_RXNE) + { + ch = uart->uart_device->DR; // invalid read + } + } + /* process usart receive */ + if (uart->uart_device->SR & USART_FLAG_RXNE) + { + rt_hw_serial_isr(serial);//auto clear interrupt flag + } + /* process usart send */ + if (uart->uart_device->SR & USART_IT_TC) + { + /* clear interrupt */ + uart->uart_device->SR = ~((uint16_t)0x01 << (uint16_t)(USART_IT_TC >> 0x08)); + } +} + #if defined(RT_USING_UART1) /* UART1 device driver structure */ struct serial_ringbuffer uart1_int_rx; +#define UART1_POOL_SIZE 64 +rt_uint8_t uart1_pool[UART1_POOL_SIZE]; struct stm32_uart uart1 = { USART1, USART1_IRQn, + + UART1_TX_PIN, + UART1_TX_GPIO, + UART1_RX_PIN, + UART1_RX_GPIO, + + UART1_CTS_PIN, + UART1_CTS_GPIO, + UART1_RTS_PIN, + UART1_RTS_GPIO, + + UART1_REMAP, }; struct rt_serial_device serial1; void USART1_IRQHandler(void) { - struct stm32_uart* uart; - - uart = &uart1; - /* enter interrupt */ rt_interrupt_enter(); - if(USART_GetITStatus(uart->uart_device, USART_IT_RXNE) != RESET) - { - rt_hw_serial_isr(&serial1); - /* clear interrupt */ - USART_ClearITPendingBit(uart->uart_device, USART_IT_RXNE); - } - if (USART_GetITStatus(uart->uart_device, USART_IT_TC) != RESET) - { - /* clear interrupt */ - USART_ClearITPendingBit(uart->uart_device, USART_IT_TC); - } + serial_device_isr(&serial1); + /* leave interrupt */ rt_interrupt_leave(); } #endif /* RT_USING_UART1 */ #if defined(RT_USING_UART2) -/* UART1 device driver structure */ +/* UART2 device driver structure */ struct serial_ringbuffer uart2_int_rx; +#define UART2_POOL_SIZE 64 +rt_uint8_t uart2_pool[UART2_POOL_SIZE]; struct stm32_uart uart2 = { USART2, USART2_IRQn, + + UART2_TX_PIN, + UART2_TX_GPIO, + UART2_RX_PIN, + UART2_RX_GPIO, + + UART2_CTS_PIN, + UART2_CTS_GPIO, + UART2_RTS_PIN, + UART2_RTS_GPIO, + + UART2_REMAP, + }; struct rt_serial_device serial2; void USART2_IRQHandler(void) { - struct stm32_uart* uart; - - uart = &uart2; - /* enter interrupt */ rt_interrupt_enter(); - if(USART_GetITStatus(uart->uart_device, USART_IT_RXNE) != RESET) - { - rt_hw_serial_isr(&serial2); - /* clear interrupt */ - USART_ClearITPendingBit(uart->uart_device, USART_IT_RXNE); - } - if (USART_GetITStatus(uart->uart_device, USART_IT_TC) != RESET) - { - /* clear interrupt */ - USART_ClearITPendingBit(uart->uart_device, USART_IT_TC); - } + serial_device_isr(&serial2); + /* leave interrupt */ rt_interrupt_leave(); } #endif /* RT_USING_UART2 */ #if defined(RT_USING_UART3) -/* UART1 device driver structure */ +/* UART3 device driver structure */ struct serial_ringbuffer uart3_int_rx; +#define UART3_POOL_SIZE 64 +rt_uint8_t uart3_pool[UART3_POOL_SIZE]; struct stm32_uart uart3 = { USART3, USART3_IRQn, + + UART3_TX_PIN, + UART3_TX_GPIO, + UART3_RX_PIN, + UART3_RX_GPIO, + + UART3_CTS_PIN, + UART3_CTS_GPIO, + UART3_RTS_PIN, + UART3_RTS_GPIO, + + UART3_REMAP, }; struct rt_serial_device serial3; void USART3_IRQHandler(void) { - struct stm32_uart* uart; + /* enter interrupt */ + rt_interrupt_enter(); - uart = &uart3; + serial_device_isr(&serial3); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* RT_USING_UART3 */ + +#if defined(RT_USING_UART4) +/* UART4 device driver structure */ +struct serial_ringbuffer uart4_int_rx; +#define UART4_POOL_SIZE 64 +rt_uint8_t uart4_pool[UART4_POOL_SIZE]; +struct stm32_uart uart4 = +{ + UART4, + UART4_IRQn, + UART4_TX_PIN, + UART4_TX_GPIO, + UART4_RX_PIN, + UART4_RX_GPIO, + + UART4_CTS_PIN, + UART4_CTS_GPIO, + UART4_RTS_PIN, + UART4_RTS_GPIO, + + UART4_REMAP, +}; +struct rt_serial_device serial4; + +void UART4_IRQHandler(void) +{ /* enter interrupt */ rt_interrupt_enter(); - if(USART_GetITStatus(uart->uart_device, USART_IT_RXNE) != RESET) - { - rt_hw_serial_isr(&serial3); - /* clear interrupt */ - USART_ClearITPendingBit(uart->uart_device, USART_IT_RXNE); - } - if (USART_GetITStatus(uart->uart_device, USART_IT_TC) != RESET) - { - /* clear interrupt */ - USART_ClearITPendingBit(uart->uart_device, USART_IT_TC); - } + + serial_device_isr(&serial4); /* leave interrupt */ rt_interrupt_leave(); } -#endif /* RT_USING_UART3 */ +#endif /* RT_USING_UART4 */ + +#if defined(RT_USING_UART5) +/* UART5 device driver structure */ +struct serial_ringbuffer uart5_int_rx; +#define UART5_POOL_SIZE 64 +rt_uint8_t uart5_pool[UART5_POOL_SIZE]; +struct stm32_uart uart5 = +{ + UART5, + UART5_IRQn, -static void RCC_Configuration(void) + UART5_TX_PIN, + UART5_TX_GPIO, + UART5_RX_PIN, + UART5_RX_GPIO, + + UART5_CTS_PIN, + UART5_CTS_GPIO, + UART5_RTS_PIN, + UART5_RTS_GPIO, + + UART5_REMAP, +}; +struct rt_serial_device serial5; + +void UART5_IRQHandler(void) { -#ifdef RT_USING_UART1 - /* Enable UART GPIO clocks */ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); - /* Enable UART clock */ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE); -#endif /* RT_USING_UART1 */ + /* enter interrupt */ + rt_interrupt_enter(); -#ifdef RT_USING_UART2 - /* Enable UART GPIO clocks */ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); - /* Enable UART clock */ - RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); -#endif /* RT_USING_UART2 */ + serial_device_isr(&serial5); -#ifdef RT_USING_UART3 + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* RT_USING_UART5 */ + +#define GPIO_RCC_ENABLE(x) \ +do{ \ + if (IS_GPIO_ALL_PERIPH(x)) \ + { \ + if ((x) == GPIOA) \ + { \ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); \ + } \ + if ((x) == GPIOB) \ + { \ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); \ + } \ + if ((x) == GPIOC) \ + { \ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE); \ + } \ + if ((x) == GPIOD) \ + { \ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD, ENABLE); \ + } \ + if ((x) == GPIOE) \ + { \ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOE, ENABLE); \ + } \ + if ((x) == GPIOF) \ + { \ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOF, ENABLE); \ + } \ + if ((x) == GPIOG) \ + { \ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOG, ENABLE); \ + } \ + } \ +}while(0) + +#define UART_RCC_ENABLE(x) \ +do{ \ + if (IS_USART_ALL_PERIPH(x)) \ + { \ + if ((x) == USART1) \ + { \ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE); \ + } \ + if ((x) == USART2) \ + { \ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); \ + } \ + if ((x) == USART3) \ + { \ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE); \ + } \ + if ((x) == UART4) \ + { \ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART4, ENABLE); \ + } \ + if ((x) == UART5) \ + { \ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART5, ENABLE); \ + } \ + } \ +}while(0) + +static void RCC_Configuration(struct stm32_uart* uart) +{ /* Enable UART GPIO clocks */ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); + GPIO_RCC_ENABLE(uart->uart_tx_gpio); + GPIO_RCC_ENABLE(uart->uart_rx_gpio); + GPIO_RCC_ENABLE(uart->uart_cts_gpio); + GPIO_RCC_ENABLE(uart->uart_rts_gpio); + /* Enable UART GPIO AF clocks */ + if (IS_GPIO_REMAP(uart->uart_remap)) + { + RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); + GPIO_PinRemapConfig(uart->uart_remap, ENABLE); + } /* Enable UART clock */ - RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE); -#endif /* RT_USING_UART3 */ + UART_RCC_ENABLE(uart->uart_device); } -static void GPIO_Configuration(void) +static void GPIO_Configuration(struct stm32_uart* uart) { GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - -#ifdef RT_USING_UART1 + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; /* Configure USART Rx/tx PIN */ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_InitStructure.GPIO_Pin = UART1_GPIO_RX; - GPIO_Init(UART1_GPIO, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = uart->uart_rx_pin; + GPIO_Init(uart->uart_rx_gpio, &GPIO_InitStructure); GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_InitStructure.GPIO_Pin = UART1_GPIO_TX; - GPIO_Init(UART1_GPIO, &GPIO_InitStructure); -#endif /* RT_USING_UART1 */ - -#ifdef RT_USING_UART2 - /* Configure USART Rx/tx PIN */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_InitStructure.GPIO_Pin = UART2_GPIO_RX; - GPIO_Init(UART1_GPIO, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_InitStructure.GPIO_Pin = UART2_GPIO_TX; - GPIO_Init(UART2_GPIO, &GPIO_InitStructure); -#endif /* RT_USING_UART2 */ - -#ifdef RT_USING_UART3 - /* Configure USART Rx/tx PIN */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_InitStructure.GPIO_Pin = UART3_GPIO_RX; - GPIO_Init(UART3_GPIO, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = uart->uart_tx_pin; + GPIO_Init(uart->uart_tx_gpio, &GPIO_InitStructure); + /* Configure USART RTS/CTS PIN */ + if (IS_GPIO_ALL_PERIPH(uart->uart_cts_gpio) && + IS_GPIO_ALL_PERIPH(uart->uart_rts_gpio) && + IS_GPIO_PIN(uart->uart_cts_pin) && + IS_GPIO_PIN(uart->uart_rts_pin)) + { + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_InitStructure.GPIO_Pin = uart->uart_cts_pin; + GPIO_Init(uart->uart_cts_gpio, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_InitStructure.GPIO_Pin = UART3_GPIO_TX; - GPIO_Init(UART3_GPIO, &GPIO_InitStructure); -#endif /* RT_USING_UART3 */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitStructure.GPIO_Pin = uart->uart_rts_pin; + GPIO_Init(uart->uart_rts_gpio, &GPIO_InitStructure); + } } static void NVIC_Configuration(struct stm32_uart* uart) { NVIC_InitTypeDef NVIC_InitStructure; - /* Enable the USART1 Interrupt */ + /* Enable the USART Interrupt */ NVIC_InitStructure.NVIC_IRQChannel = uart->irq; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; @@ -319,57 +541,161 @@ static void NVIC_Configuration(struct stm32_uart* uart) void rt_hw_usart_init(void) { struct stm32_uart* uart; + struct rt_serial_device *serial; struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; - RCC_Configuration(); - GPIO_Configuration(); - #ifdef RT_USING_UART1 uart = &uart1; + serial = &serial1; + + uart1_int_rx.pool = uart1_pool; + uart1_int_rx.size = UART1_POOL_SIZE; + config.baud_rate = BAUD_RATE_115200; - serial1.ops = &stm32_uart_ops; - serial1.int_rx = &uart1_int_rx; - serial1.config = config; - - NVIC_Configuration(&uart1); + serial->ops = &stm32_uart_ops; + serial->int_rx = &uart1_int_rx; + serial->config = config; + + RCC_Configuration(uart); + GPIO_Configuration(uart); + NVIC_Configuration(uart); /* register UART1 device */ - rt_hw_serial_register(&serial1, "uart1", + rt_hw_serial_register(serial, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, uart); #endif /* RT_USING_UART1 */ #ifdef RT_USING_UART2 uart = &uart2; + serial = &serial2; + + uart2_int_rx.pool = uart2_pool; + uart2_int_rx.size = UART2_POOL_SIZE; config.baud_rate = BAUD_RATE_115200; - serial2.ops = &stm32_uart_ops; - serial2.int_rx = &uart2_int_rx; - serial2.config = config; - NVIC_Configuration(&uart2); + serial->ops = &stm32_uart_ops; + serial->int_rx = &uart2_int_rx; + serial->config = config; + + RCC_Configuration(uart); + GPIO_Configuration(uart); + NVIC_Configuration(uart); - /* register UART1 device */ - rt_hw_serial_register(&serial2, "uart2", + /* register UART2 device */ + rt_hw_serial_register(serial, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif /* RT_USING_UART2 */ #ifdef RT_USING_UART3 uart = &uart3; + serial = &serial3; + + uart3_int_rx.pool = uart3_pool; + uart3_int_rx.size = UART3_POOL_SIZE; config.baud_rate = BAUD_RATE_115200; - serial3.ops = &stm32_uart_ops; - serial3.int_rx = &uart3_int_rx; - serial3.config = config; - - NVIC_Configuration(&uart3); + serial->ops = &stm32_uart_ops; + serial->int_rx = &uart3_int_rx; + serial->config = config; + + RCC_Configuration(uart); + GPIO_Configuration(uart); + NVIC_Configuration(uart); - /* register UART1 device */ - rt_hw_serial_register(&serial3, "uart3", + /* register UART3 device */ + rt_hw_serial_register(serial, "uart3", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif /* RT_USING_UART3 */ + +#ifdef RT_USING_UART4 + uart = &uart4; + serial = &serial4; + + uart4_int_rx.pool = uart4_pool; + uart4_int_rx.size = UART4_POOL_SIZE; + + config.baud_rate = BAUD_RATE_115200; + + serial->ops = &stm32_uart_ops; + serial->int_rx = &uart4_int_rx; + serial->config = config; + + RCC_Configuration(uart); + GPIO_Configuration(uart); + NVIC_Configuration(uart); + + /* register UART4 device */ + rt_hw_serial_register(serial, "uart4", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +#endif /* RT_USING_UART4 */ + +#ifdef RT_USING_UART5 + uart = &uart5; + serial = &serial5; + + uart5_int_rx.pool = uart5_pool; + uart5_int_rx.size = UART5_POOL_SIZE; + + config.baud_rate = BAUD_RATE_115200; + + serial->ops = &stm32_uart_ops; + serial->int_rx = &uart5_int_rx; + serial->config = config; + + RCC_Configuration(uart); + GPIO_Configuration(uart); + NVIC_Configuration(uart); + + /* register UART5 device */ + rt_hw_serial_register(serial, "uart5", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +#endif /* RT_USING_UART5 */ +} + + +/* uart device test */ +#ifdef RT_USING_FINSH +#include + +#if (defined(RT_USING_UART1) || defined(RT_USING_UART2) || defined(RT_USING_UART3) || defined(RT_USING_UART4) || defined(RT_USING_UART5)) +void uart_rw(const char *name, rt_int8_t cmd, const char *str) +{ + rt_device_t uart; + uart = rt_device_find(name); + if (uart != RT_NULL) + { + if (uart->open_flag == RT_DEVICE_OFLAG_CLOSE) + { + rt_device_open(uart, RT_DEVICE_OFLAG_RDWR); + } + if (cmd == 0) + { + rt_int8_t temp[20]; + memset(temp, '\0', 20); + rt_device_read(uart,0,(void *)temp,20); + rt_kprintf("%s", temp); + } + else + { + rt_kprintf("%s, %d", str, strlen(str)); + rt_device_write(uart,0,str,strlen(str)); + } + //rt_device_close(uart); + } + else + { + rt_kprintf("device %s is not exist!\n", name); + } } +FINSH_FUNCTION_EXPORT(uart_rw, set uart[name 0 xxx] for read.) +#endif + +#endif -- cgit v1.3.1 From f615c1e92de7ff72abe9eea5210a2744a0166692 Mon Sep 17 00:00:00 2001 From: Grissiom Date: Mon, 3 Mar 2014 12:07:13 +0800 Subject: Revert "Merge pull request #241 from bright-pan/master" This reverts commit 5aeedc4f3a3c3fcfffb0cd4a474f5faa75053839, reversing changes made to 3d80e414ff6c03ff04fecb914e7aa9b3fb535e03. This merge breaks every uart driver in all BSPs. @bright-pan , is there any way to get this done without breaking existing code? --- bsp/stm32f10x/drivers/board.h | 2 - bsp/stm32f10x/drivers/usart.c | 584 ++++++---------------------- components/drivers/include/drivers/serial.h | 33 +- components/drivers/serial/serial.c | 52 ++- 4 files changed, 178 insertions(+), 493 deletions(-) (limited to 'bsp') diff --git a/bsp/stm32f10x/drivers/board.h b/bsp/stm32f10x/drivers/board.h index ebd121d631..dc84db9c69 100644 --- a/bsp/stm32f10x/drivers/board.h +++ b/bsp/stm32f10x/drivers/board.h @@ -41,8 +41,6 @@ #define RT_USING_UART1 #define RT_USING_UART2 #define RT_USING_UART3 -//#define RT_USING_UART4 -//#define RT_USING_UART5 #endif /* __BOARD_H__ */ diff --git a/bsp/stm32f10x/drivers/usart.c b/bsp/stm32f10x/drivers/usart.c index 4bb320269b..ae47db3a14 100644 --- a/bsp/stm32f10x/drivers/usart.c +++ b/bsp/stm32f10x/drivers/usart.c @@ -21,90 +21,25 @@ #include /* USART1 */ -#define UART1_TX_PIN GPIO_Pin_9 -#define UART1_TX_GPIO GPIOA -#define UART1_RX_PIN GPIO_Pin_10 -#define UART1_RX_GPIO GPIOA - -#define UART1_CTS_PIN ((uint16_t)0x0000)// cts is disable -#define UART1_CTS_GPIO ((GPIO_TypeDef *)0x00000000) -#define UART1_RTS_PIN ((uint16_t)0x0000)// rts is disable -#define UART1_RTS_GPIO ((GPIO_TypeDef *)0x00000000) - -#define UART1_REMAP (((uint32_t)0x00000000))// remap is disable +#define UART1_GPIO_TX GPIO_Pin_9 +#define UART1_GPIO_RX GPIO_Pin_10 +#define UART1_GPIO GPIOA /* USART2 */ -#define UART2_TX_PIN GPIO_Pin_2 -#define UART2_TX_GPIO GPIOA -#define UART2_RX_PIN GPIO_Pin_3 -#define UART2_RX_GPIO GPIOA - -#define UART2_CTS_PIN ((uint16_t)0x0000)// cts is disable -#define UART2_CTS_GPIO ((GPIO_TypeDef *)0x00000000) -#define UART2_RTS_PIN ((uint16_t)0x0000)// rts is disable -#define UART2_RTS_GPIO ((GPIO_TypeDef *)0x00000000) - -#define UART2_REMAP (((uint32_t)0x00000000))// remap is disable - -/* USART3_REMAP[1:0] = 11 */ -#define UART3_TX_PIN GPIO_Pin_8 -#define UART3_TX_GPIO GPIOD -#define UART3_RX_PIN GPIO_Pin_9 -#define UART3_RX_GPIO GPIOD - -#define UART3_CTS_PIN ((uint16_t)0x0000)// cts is disable -#define UART3_CTS_GPIO ((GPIO_TypeDef *)0x00000000) -#define UART3_RTS_PIN ((uint16_t)0x0000)// rts is disable -#define UART3_RTS_GPIO ((GPIO_TypeDef *)0x00000000) - -#define UART3_REMAP GPIO_FullRemap_USART3 - -/* USART4 */ -#define UART4_TX_PIN GPIO_Pin_10 -#define UART4_TX_GPIO GPIOC -#define UART4_RX_PIN GPIO_Pin_11 -#define UART4_RX_GPIO GPIOC - -#define UART4_CTS_PIN ((uint16_t)0x0000)// cts is disable -#define UART4_CTS_GPIO ((GPIO_TypeDef *)0x00000000) -#define UART4_RTS_PIN ((uint16_t)0x0000)// rts is disable -#define UART4_RTS_GPIO ((GPIO_TypeDef *)0x00000000) - -#define UART4_REMAP (((uint32_t)0x00000000))// remap is disable +#define UART2_GPIO_TX GPIO_Pin_2 +#define UART2_GPIO_RX GPIO_Pin_3 +#define UART2_GPIO GPIOA -/* USART5 */ -#define UART5_TX_PIN GPIO_Pin_12 -#define UART5_TX_GPIO GPIOC -#define UART5_RX_PIN GPIO_Pin_2 -#define UART5_RX_GPIO GPIOD - -#define UART5_CTS_PIN ((uint16_t)0x0000)// cts is disable -#define UART5_CTS_GPIO ((GPIO_TypeDef *)0x00000000) -#define UART5_RTS_PIN ((uint16_t)0x0000)// rts is disable -#define UART5_RTS_GPIO ((GPIO_TypeDef *)0x00000000) - -#define UART4_REMAP (((uint32_t)0x00000000))// remap is disable +/* USART3_REMAP[1:0] = 00 */ +#define UART3_GPIO_TX GPIO_Pin_10 +#define UART3_GPIO_RX GPIO_Pin_11 +#define UART3_GPIO GPIOB /* STM32 uart driver */ struct stm32_uart { USART_TypeDef* uart_device; IRQn_Type irq; - - uint16_t uart_tx_pin; - GPIO_TypeDef *uart_tx_gpio; - - uint16_t uart_rx_pin; - GPIO_TypeDef *uart_rx_gpio; - - uint16_t uart_cts_pin; - GPIO_TypeDef *uart_cts_gpio; - - uint16_t uart_rts_pin; - GPIO_TypeDef *uart_rts_gpio; - - uint32_t uart_remap; - }; static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_configure *cfg) @@ -116,7 +51,7 @@ static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_c RT_ASSERT(cfg != RT_NULL); uart = (struct stm32_uart *)serial->parent.user_data; - USART_StructInit(&USART_InitStructure); + USART_InitStructure.USART_BaudRate = cfg->baud_rate; if (cfg->data_bits == DATA_BITS_8) @@ -127,18 +62,8 @@ static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_c else if (cfg->stop_bits == STOP_BITS_2) USART_InitStructure.USART_StopBits = USART_StopBits_2; - if (cfg->parity == PARITY_NONE) - USART_InitStructure.USART_Parity = USART_Parity_No; - else if (cfg->parity == PARITY_EVEN) - USART_InitStructure.USART_Parity = USART_Parity_Even; - else if (cfg->parity == PARITY_ODD) - USART_InitStructure.USART_Parity = USART_Parity_Odd; - - if (cfg->hw_control == HW_CONTROL_NONE) - USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; - else if (cfg->hw_control == HW_CONTROL_RTS_CTS) - USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_RTS_CTS; - + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; USART_Init(uart->uart_device, &USART_InitStructure); @@ -210,327 +135,180 @@ static const struct rt_uart_ops stm32_uart_ops = stm32_getc, }; -__STATIC_INLINE void serial_device_isr(struct rt_serial_device *serial) -{ - volatile int ch = 0; - struct stm32_uart *uart = serial->parent.user_data; - - /* process uart error */ - if(uart->uart_device->SR & (USART_FLAG_ORE | USART_FLAG_NE | USART_FLAG_FE | USART_FLAG_PE)) - { - ch = uart->uart_device->DR; // invalid read - while (uart->uart_device->SR & USART_FLAG_RXNE) - { - ch = uart->uart_device->DR; // invalid read - } - } - /* process usart receive */ - if (uart->uart_device->SR & USART_FLAG_RXNE) - { - rt_hw_serial_isr(serial);//auto clear interrupt flag - } - /* process usart send */ - if (uart->uart_device->SR & USART_IT_TC) - { - /* clear interrupt */ - uart->uart_device->SR = ~((uint16_t)0x01 << (uint16_t)(USART_IT_TC >> 0x08)); - } -} - #if defined(RT_USING_UART1) /* UART1 device driver structure */ struct serial_ringbuffer uart1_int_rx; -#define UART1_POOL_SIZE 64 -rt_uint8_t uart1_pool[UART1_POOL_SIZE]; struct stm32_uart uart1 = { USART1, USART1_IRQn, - - UART1_TX_PIN, - UART1_TX_GPIO, - UART1_RX_PIN, - UART1_RX_GPIO, - - UART1_CTS_PIN, - UART1_CTS_GPIO, - UART1_RTS_PIN, - UART1_RTS_GPIO, - - UART1_REMAP, }; struct rt_serial_device serial1; void USART1_IRQHandler(void) { + struct stm32_uart* uart; + + uart = &uart1; + /* enter interrupt */ rt_interrupt_enter(); + if(USART_GetITStatus(uart->uart_device, USART_IT_RXNE) != RESET) + { + rt_hw_serial_isr(&serial1); + /* clear interrupt */ + USART_ClearITPendingBit(uart->uart_device, USART_IT_RXNE); + } + if (USART_GetITStatus(uart->uart_device, USART_IT_TC) != RESET) + { + /* clear interrupt */ + USART_ClearITPendingBit(uart->uart_device, USART_IT_TC); + } - serial_device_isr(&serial1); - /* leave interrupt */ rt_interrupt_leave(); } #endif /* RT_USING_UART1 */ #if defined(RT_USING_UART2) -/* UART2 device driver structure */ +/* UART1 device driver structure */ struct serial_ringbuffer uart2_int_rx; -#define UART2_POOL_SIZE 64 -rt_uint8_t uart2_pool[UART2_POOL_SIZE]; struct stm32_uart uart2 = { USART2, USART2_IRQn, - - UART2_TX_PIN, - UART2_TX_GPIO, - UART2_RX_PIN, - UART2_RX_GPIO, - - UART2_CTS_PIN, - UART2_CTS_GPIO, - UART2_RTS_PIN, - UART2_RTS_GPIO, - - UART2_REMAP, - }; struct rt_serial_device serial2; void USART2_IRQHandler(void) { + struct stm32_uart* uart; + + uart = &uart2; + /* enter interrupt */ rt_interrupt_enter(); + if(USART_GetITStatus(uart->uart_device, USART_IT_RXNE) != RESET) + { + rt_hw_serial_isr(&serial2); + /* clear interrupt */ + USART_ClearITPendingBit(uart->uart_device, USART_IT_RXNE); + } + if (USART_GetITStatus(uart->uart_device, USART_IT_TC) != RESET) + { + /* clear interrupt */ + USART_ClearITPendingBit(uart->uart_device, USART_IT_TC); + } - serial_device_isr(&serial2); - /* leave interrupt */ rt_interrupt_leave(); } #endif /* RT_USING_UART2 */ #if defined(RT_USING_UART3) -/* UART3 device driver structure */ +/* UART1 device driver structure */ struct serial_ringbuffer uart3_int_rx; -#define UART3_POOL_SIZE 64 -rt_uint8_t uart3_pool[UART3_POOL_SIZE]; struct stm32_uart uart3 = { USART3, USART3_IRQn, - - UART3_TX_PIN, - UART3_TX_GPIO, - UART3_RX_PIN, - UART3_RX_GPIO, - - UART3_CTS_PIN, - UART3_CTS_GPIO, - UART3_RTS_PIN, - UART3_RTS_GPIO, - - UART3_REMAP, }; struct rt_serial_device serial3; void USART3_IRQHandler(void) { - /* enter interrupt */ - rt_interrupt_enter(); - - serial_device_isr(&serial3); - - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif /* RT_USING_UART3 */ - -#if defined(RT_USING_UART4) -/* UART4 device driver structure */ -struct serial_ringbuffer uart4_int_rx; -#define UART4_POOL_SIZE 64 -rt_uint8_t uart4_pool[UART4_POOL_SIZE]; -struct stm32_uart uart4 = -{ - UART4, - UART4_IRQn, - - UART4_TX_PIN, - UART4_TX_GPIO, - UART4_RX_PIN, - UART4_RX_GPIO, - - UART4_CTS_PIN, - UART4_CTS_GPIO, - UART4_RTS_PIN, - UART4_RTS_GPIO, + struct stm32_uart* uart; - UART4_REMAP, -}; -struct rt_serial_device serial4; + uart = &uart3; -void UART4_IRQHandler(void) -{ /* enter interrupt */ rt_interrupt_enter(); - - serial_device_isr(&serial4); + if(USART_GetITStatus(uart->uart_device, USART_IT_RXNE) != RESET) + { + rt_hw_serial_isr(&serial3); + /* clear interrupt */ + USART_ClearITPendingBit(uart->uart_device, USART_IT_RXNE); + } + if (USART_GetITStatus(uart->uart_device, USART_IT_TC) != RESET) + { + /* clear interrupt */ + USART_ClearITPendingBit(uart->uart_device, USART_IT_TC); + } /* leave interrupt */ rt_interrupt_leave(); } -#endif /* RT_USING_UART4 */ - -#if defined(RT_USING_UART5) -/* UART5 device driver structure */ -struct serial_ringbuffer uart5_int_rx; -#define UART5_POOL_SIZE 64 -rt_uint8_t uart5_pool[UART5_POOL_SIZE]; -struct stm32_uart uart5 = -{ - UART5, - UART5_IRQn, - - UART5_TX_PIN, - UART5_TX_GPIO, - UART5_RX_PIN, - UART5_RX_GPIO, - - UART5_CTS_PIN, - UART5_CTS_GPIO, - UART5_RTS_PIN, - UART5_RTS_GPIO, - - UART5_REMAP, -}; -struct rt_serial_device serial5; +#endif /* RT_USING_UART3 */ -void UART5_IRQHandler(void) +static void RCC_Configuration(void) { - /* enter interrupt */ - rt_interrupt_enter(); +#ifdef RT_USING_UART1 + /* Enable UART GPIO clocks */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); + /* Enable UART clock */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE); +#endif /* RT_USING_UART1 */ - serial_device_isr(&serial5); +#ifdef RT_USING_UART2 + /* Enable UART GPIO clocks */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); + /* Enable UART clock */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); +#endif /* RT_USING_UART2 */ - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif /* RT_USING_UART5 */ - -#define GPIO_RCC_ENABLE(x) \ -do{ \ - if (IS_GPIO_ALL_PERIPH(x)) \ - { \ - if ((x) == GPIOA) \ - { \ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); \ - } \ - if ((x) == GPIOB) \ - { \ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); \ - } \ - if ((x) == GPIOC) \ - { \ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE); \ - } \ - if ((x) == GPIOD) \ - { \ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD, ENABLE); \ - } \ - if ((x) == GPIOE) \ - { \ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOE, ENABLE); \ - } \ - if ((x) == GPIOF) \ - { \ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOF, ENABLE); \ - } \ - if ((x) == GPIOG) \ - { \ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOG, ENABLE); \ - } \ - } \ -}while(0) - -#define UART_RCC_ENABLE(x) \ -do{ \ - if (IS_USART_ALL_PERIPH(x)) \ - { \ - if ((x) == USART1) \ - { \ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE); \ - } \ - if ((x) == USART2) \ - { \ - RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); \ - } \ - if ((x) == USART3) \ - { \ - RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE); \ - } \ - if ((x) == UART4) \ - { \ - RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART4, ENABLE); \ - } \ - if ((x) == UART5) \ - { \ - RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART5, ENABLE); \ - } \ - } \ -}while(0) - -static void RCC_Configuration(struct stm32_uart* uart) -{ +#ifdef RT_USING_UART3 /* Enable UART GPIO clocks */ - GPIO_RCC_ENABLE(uart->uart_tx_gpio); - GPIO_RCC_ENABLE(uart->uart_rx_gpio); - GPIO_RCC_ENABLE(uart->uart_cts_gpio); - GPIO_RCC_ENABLE(uart->uart_rts_gpio); - /* Enable UART GPIO AF clocks */ - if (IS_GPIO_REMAP(uart->uart_remap)) - { - RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); - GPIO_PinRemapConfig(uart->uart_remap, ENABLE); - } + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); /* Enable UART clock */ - UART_RCC_ENABLE(uart->uart_device); + RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE); +#endif /* RT_USING_UART3 */ } -static void GPIO_Configuration(struct stm32_uart* uart) +static void GPIO_Configuration(void) { GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + +#ifdef RT_USING_UART1 /* Configure USART Rx/tx PIN */ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_InitStructure.GPIO_Pin = uart->uart_rx_pin; - GPIO_Init(uart->uart_rx_gpio, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = UART1_GPIO_RX; + GPIO_Init(UART1_GPIO, &GPIO_InitStructure); GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_InitStructure.GPIO_Pin = uart->uart_tx_pin; - GPIO_Init(uart->uart_tx_gpio, &GPIO_InitStructure); - /* Configure USART RTS/CTS PIN */ - if (IS_GPIO_ALL_PERIPH(uart->uart_cts_gpio) && - IS_GPIO_ALL_PERIPH(uart->uart_rts_gpio) && - IS_GPIO_PIN(uart->uart_cts_pin) && - IS_GPIO_PIN(uart->uart_rts_pin)) - { - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_InitStructure.GPIO_Pin = uart->uart_cts_pin; - GPIO_Init(uart->uart_cts_gpio, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = UART1_GPIO_TX; + GPIO_Init(UART1_GPIO, &GPIO_InitStructure); +#endif /* RT_USING_UART1 */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_InitStructure.GPIO_Pin = uart->uart_rts_pin; - GPIO_Init(uart->uart_rts_gpio, &GPIO_InitStructure); - } +#ifdef RT_USING_UART2 + /* Configure USART Rx/tx PIN */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_InitStructure.GPIO_Pin = UART2_GPIO_RX; + GPIO_Init(UART1_GPIO, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitStructure.GPIO_Pin = UART2_GPIO_TX; + GPIO_Init(UART2_GPIO, &GPIO_InitStructure); +#endif /* RT_USING_UART2 */ + +#ifdef RT_USING_UART3 + /* Configure USART Rx/tx PIN */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_InitStructure.GPIO_Pin = UART3_GPIO_RX; + GPIO_Init(UART3_GPIO, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitStructure.GPIO_Pin = UART3_GPIO_TX; + GPIO_Init(UART3_GPIO, &GPIO_InitStructure); +#endif /* RT_USING_UART3 */ } static void NVIC_Configuration(struct stm32_uart* uart) { NVIC_InitTypeDef NVIC_InitStructure; - /* Enable the USART Interrupt */ + /* Enable the USART1 Interrupt */ NVIC_InitStructure.NVIC_IRQChannel = uart->irq; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; @@ -541,161 +319,57 @@ static void NVIC_Configuration(struct stm32_uart* uart) void rt_hw_usart_init(void) { struct stm32_uart* uart; - struct rt_serial_device *serial; struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + RCC_Configuration(); + GPIO_Configuration(); + #ifdef RT_USING_UART1 uart = &uart1; - serial = &serial1; - - uart1_int_rx.pool = uart1_pool; - uart1_int_rx.size = UART1_POOL_SIZE; - config.baud_rate = BAUD_RATE_115200; - serial->ops = &stm32_uart_ops; - serial->int_rx = &uart1_int_rx; - serial->config = config; - - RCC_Configuration(uart); - GPIO_Configuration(uart); - NVIC_Configuration(uart); + serial1.ops = &stm32_uart_ops; + serial1.int_rx = &uart1_int_rx; + serial1.config = config; + + NVIC_Configuration(&uart1); /* register UART1 device */ - rt_hw_serial_register(serial, "uart1", + rt_hw_serial_register(&serial1, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, uart); #endif /* RT_USING_UART1 */ #ifdef RT_USING_UART2 uart = &uart2; - serial = &serial2; - - uart2_int_rx.pool = uart2_pool; - uart2_int_rx.size = UART2_POOL_SIZE; config.baud_rate = BAUD_RATE_115200; + serial2.ops = &stm32_uart_ops; + serial2.int_rx = &uart2_int_rx; + serial2.config = config; - serial->ops = &stm32_uart_ops; - serial->int_rx = &uart2_int_rx; - serial->config = config; - - RCC_Configuration(uart); - GPIO_Configuration(uart); - NVIC_Configuration(uart); + NVIC_Configuration(&uart2); - /* register UART2 device */ - rt_hw_serial_register(serial, "uart2", + /* register UART1 device */ + rt_hw_serial_register(&serial2, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif /* RT_USING_UART2 */ #ifdef RT_USING_UART3 uart = &uart3; - serial = &serial3; - - uart3_int_rx.pool = uart3_pool; - uart3_int_rx.size = UART3_POOL_SIZE; config.baud_rate = BAUD_RATE_115200; - serial->ops = &stm32_uart_ops; - serial->int_rx = &uart3_int_rx; - serial->config = config; - - RCC_Configuration(uart); - GPIO_Configuration(uart); - NVIC_Configuration(uart); - - /* register UART3 device */ - rt_hw_serial_register(serial, "uart3", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, - uart); -#endif /* RT_USING_UART3 */ + serial3.ops = &stm32_uart_ops; + serial3.int_rx = &uart3_int_rx; + serial3.config = config; -#ifdef RT_USING_UART4 - uart = &uart4; - serial = &serial4; - - uart4_int_rx.pool = uart4_pool; - uart4_int_rx.size = UART4_POOL_SIZE; + NVIC_Configuration(&uart3); - config.baud_rate = BAUD_RATE_115200; - - serial->ops = &stm32_uart_ops; - serial->int_rx = &uart4_int_rx; - serial->config = config; - - RCC_Configuration(uart); - GPIO_Configuration(uart); - NVIC_Configuration(uart); - - /* register UART4 device */ - rt_hw_serial_register(serial, "uart4", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, - uart); -#endif /* RT_USING_UART4 */ - -#ifdef RT_USING_UART5 - uart = &uart5; - serial = &serial5; - - uart5_int_rx.pool = uart5_pool; - uart5_int_rx.size = UART5_POOL_SIZE; - - config.baud_rate = BAUD_RATE_115200; - - serial->ops = &stm32_uart_ops; - serial->int_rx = &uart5_int_rx; - serial->config = config; - - RCC_Configuration(uart); - GPIO_Configuration(uart); - NVIC_Configuration(uart); - - /* register UART5 device */ - rt_hw_serial_register(serial, "uart5", + /* register UART1 device */ + rt_hw_serial_register(&serial3, "uart3", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); -#endif /* RT_USING_UART5 */ -} - - -/* uart device test */ -#ifdef RT_USING_FINSH -#include - -#if (defined(RT_USING_UART1) || defined(RT_USING_UART2) || defined(RT_USING_UART3) || defined(RT_USING_UART4) || defined(RT_USING_UART5)) -void uart_rw(const char *name, rt_int8_t cmd, const char *str) -{ - rt_device_t uart; - uart = rt_device_find(name); - if (uart != RT_NULL) - { - if (uart->open_flag == RT_DEVICE_OFLAG_CLOSE) - { - rt_device_open(uart, RT_DEVICE_OFLAG_RDWR); - } - if (cmd == 0) - { - rt_int8_t temp[20]; - memset(temp, '\0', 20); - rt_device_read(uart,0,(void *)temp,20); - rt_kprintf("%s", temp); - } - else - { - rt_kprintf("%s, %d", str, strlen(str)); - rt_device_write(uart,0,str,strlen(str)); - } - //rt_device_close(uart); - } - else - { - rt_kprintf("device %s is not exist!\n", name); - } +#endif /* RT_USING_UART3 */ } -FINSH_FUNCTION_EXPORT(uart_rw, set uart[name 0 xxx] for read.) -#endif - -#endif diff --git a/components/drivers/include/drivers/serial.h b/components/drivers/include/drivers/serial.h index c966f5459b..41132ed916 100644 --- a/components/drivers/include/drivers/serial.h +++ b/components/drivers/include/drivers/serial.h @@ -29,7 +29,6 @@ #define __SERIAL_H__ #include -#include #define BAUD_RATE_4800 4800 #define BAUD_RATE_9600 9600 @@ -56,11 +55,6 @@ #define NRZ_NORMAL 0 /* Non Return to Zero : normal mode */ #define NRZ_INVERTED 1 /* Non Return to Zero : inverted mode */ -#define HW_CONTROL_NONE 0 -#define HW_CONTROL_RTS 1 -#define HW_CONTROL_CTS 2 -#define HW_CONTROL_RTS_CTS 3 - #ifndef RT_SERIAL_RB_BUFSZ #define RT_SERIAL_RB_BUFSZ 64 #endif @@ -81,23 +75,21 @@ #define RT_SERIAL_TX_DATAQUEUE_LWM 30 /* Default config for serial_configure structure */ -#define RT_SERIAL_CONFIG_DEFAULT \ -{ \ - BAUD_RATE_115200, /* 115200 bits/s */ \ - DATA_BITS_8, /* 8 databits */ \ - STOP_BITS_1, /* 1 stopbit */ \ - PARITY_NONE, /* No parity */ \ - BIT_ORDER_LSB, /* LSB first sent */ \ - NRZ_NORMAL, /* Normal mode */ \ - HW_CONTROL_NONE, /* Hardware control */\ - 0 \ +#define RT_SERIAL_CONFIG_DEFAULT \ +{ \ + BAUD_RATE_115200, /* 115200 bits/s */ \ + DATA_BITS_8, /* 8 databits */ \ + STOP_BITS_1, /* 1 stopbit */ \ + PARITY_NONE, /* No parity */ \ + BIT_ORDER_LSB, /* LSB first sent */ \ + NRZ_NORMAL, /* Normal mode */ \ + 0 \ } struct serial_ringbuffer { - struct rt_ringbuffer rb; - rt_uint8_t *pool; - rt_uint16_t size; + rt_uint8_t buffer[RT_SERIAL_RB_BUFSZ]; + rt_uint16_t put_index, get_index; }; struct serial_configure @@ -108,8 +100,7 @@ struct serial_configure rt_uint32_t parity :2; rt_uint32_t bit_order :1; rt_uint32_t invert :1; - rt_uint32_t hw_control :2; - rt_uint32_t reserved :18; + rt_uint32_t reserved :20; }; struct rt_serial_device diff --git a/components/drivers/serial/serial.c b/components/drivers/serial/serial.c index 9a356b6f0c..622d2cd68c 100644 --- a/components/drivers/serial/serial.c +++ b/components/drivers/serial/serial.c @@ -25,9 +25,6 @@ * 2012-11-23 bernard fix compiler warning. * 2013-02-20 bernard use RT_SERIAL_RB_BUFSZ to define * the size of ring buffer. - * 2014-02-26 bright use DeviceDriver ringbuffer. - * add hardware flow support. - * use new struct serial_ringbuffer. */ #include @@ -36,7 +33,9 @@ rt_inline void serial_ringbuffer_init(struct serial_ringbuffer *rbuffer) { - rt_ringbuffer_init(&rbuffer->rb, rbuffer->pool, rbuffer->size); + rt_memset(rbuffer->buffer, 0, sizeof(rbuffer->buffer)); + rbuffer->put_index = 0; + rbuffer->get_index = 0; } rt_inline void serial_ringbuffer_putc(struct serial_ringbuffer *rbuffer, @@ -46,8 +45,17 @@ rt_inline void serial_ringbuffer_putc(struct serial_ringbuffer *rbuffer, /* disable interrupt */ level = rt_hw_interrupt_disable(); - rt_ringbuffer_putchar(&rbuffer->rb, ch); - // enable interrupt + + rbuffer->buffer[rbuffer->put_index] = ch; + rbuffer->put_index = (rbuffer->put_index + 1) & (RT_SERIAL_RB_BUFSZ - 1); + + /* if the next position is read index, discard this 'read char' */ + if (rbuffer->put_index == rbuffer->get_index) + { + rbuffer->get_index = (rbuffer->get_index + 1) & (RT_SERIAL_RB_BUFSZ - 1); + } + + /* enable interrupt */ rt_hw_interrupt_enable(level); } @@ -55,11 +63,25 @@ rt_inline int serial_ringbuffer_putchar(struct serial_ringbuffer *rbuffer, char ch) { rt_base_t level; - //rt_uint16_t next_index; + rt_uint16_t next_index; /* disable interrupt */ level = rt_hw_interrupt_disable(); - rt_ringbuffer_putchar(&rbuffer->rb, ch); + + next_index = (rbuffer->put_index + 1) & (RT_SERIAL_RB_BUFSZ - 1); + if (next_index != rbuffer->get_index) + { + rbuffer->buffer[rbuffer->put_index] = ch; + rbuffer->put_index = next_index; + } + else + { + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + return -1; + } + /* enable interrupt */ rt_hw_interrupt_enable(level); @@ -68,14 +90,17 @@ rt_inline int serial_ringbuffer_putchar(struct serial_ringbuffer *rbuffer, rt_inline int serial_ringbuffer_getc(struct serial_ringbuffer *rbuffer) { - int ch = 0; + int ch; rt_base_t level; + ch = -1; /* disable interrupt */ level = rt_hw_interrupt_disable(); - /* get char */ - if (!rt_ringbuffer_getchar(&rbuffer->rb, (rt_uint8_t *)&ch)) - ch = -1; + if (rbuffer->get_index != rbuffer->put_index) + { + ch = rbuffer->buffer[rbuffer->get_index]; + rbuffer->get_index = (rbuffer->get_index + 1) & (RT_SERIAL_RB_BUFSZ - 1); + } /* enable interrupt */ rt_hw_interrupt_enable(level); @@ -88,10 +113,7 @@ rt_inline rt_uint32_t serial_ringbuffer_size(struct serial_ringbuffer *rbuffer) rt_base_t level; level = rt_hw_interrupt_disable(); - size = rt_ringbuffer_space_len(&rbuffer->rb); - /* size = (rbuffer->put_index - rbuffer->get_index) & (RT_SERIAL_RB_BUFSZ - 1); - */ rt_hw_interrupt_enable(level); return size; -- cgit v1.3.1